From 6ca760540ac5b2ebb8ab5da45f9e63989463d9a1 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 01/52] arm/stm32: add common STM32 Kconfig support Add the shared STM32 Kconfig include and introduce the hidden common ARCH_CHIP_STM32 selector used by concrete STM32 families. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 120 ++- arch/arm/src/common/stm32/Kconfig | 1326 +++++++++++++++++++++++++++++ 2 files changed, 1440 insertions(+), 6 deletions(-) create mode 100644 arch/arm/src/common/stm32/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdf4df2bb137a..36c1510839b6f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -55,7 +55,7 @@ endchoice # ARM Toolchain Selection choice prompt "ARM MCU selection" - default ARCH_CHIP_STM32 + default ARCH_CHIP_STM32F1 config ARCH_CHIP_A1X bool "Allwinner A1X" @@ -489,8 +489,60 @@ config ARCH_CHIP_SIMPLELINK ---help--- TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4) -config ARCH_CHIP_STM32 - bool "STMicro STM32 F1/F2/F3/F4/G4/L1" +config ARCH_CHIP_STM32F1 + bool "STMicro STM32 F1" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F1 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F2 + bool "STMicro STM32 F2" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F2 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F3 + bool "STMicro STM32 F3" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F3 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32F4 + bool "STMicro STM32 F4" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET @@ -503,22 +555,59 @@ config ARCH_CHIP_STM32 select ARMV7M_HAVE_STACKCHECK select ARCH_HAVE_ADJTIME ---help--- - STMicro STM32 architectures (ARM Cortex-M3/4). + STMicro STM32F4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32G4 + bool "STMicro STM32 G4" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32G4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32L1 + bool "STMicro STM32 L1" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32L1 architectures (ARM Cortex-M3). config ARCH_CHIP_STM32F0 bool "STMicro STM32 F0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32F0 architectures (ARM Cortex-M0). config ARCH_CHIP_STM32L0 bool "STMicro STM32 L0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32L0 architectures (ARM Cortex-M0+). config ARCH_CHIP_STM32G0 bool "STMicro STM32 G0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 select ARCH_HAVE_PROGMEM ---help--- @@ -526,12 +615,14 @@ config ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32C0 bool "STMicro STM32 C0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32C0 architectures (ARM Cortex-M0+). config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" + select ARCH_CHIP_STM32 select ARCH_CORTEXM7 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -548,6 +639,7 @@ config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32H7 bool "STMicro STM32 H7" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET select ARCH_HAVE_PROGMEM @@ -563,6 +655,7 @@ config ARCH_CHIP_STM32H7 config ARCH_CHIP_STM32L4 bool "STMicro STM32 L4" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -578,6 +671,7 @@ config ARCH_CHIP_STM32L4 config ARCH_CHIP_STM32H5 bool "STMicro STM32 H5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -606,6 +700,7 @@ config ARCH_CHIP_STM32N6 config ARCH_CHIP_STM32L5 bool "STMicro STM32 L5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -621,6 +716,7 @@ config ARCH_CHIP_STM32L5 config ARCH_CHIP_STM32U5 bool "STMicro STM32 U5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP @@ -637,6 +733,7 @@ config ARCH_CHIP_STM32U5 config ARCH_CHIP_STM32WB bool "STMicro STM32 WB" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_FPU select ARCH_HAVE_MPU @@ -653,6 +750,7 @@ config ARCH_CHIP_STM32WB config ARCH_CHIP_STM32WL5 bool "STMicro STM32 WL5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD @@ -812,6 +910,13 @@ config ARCH_CHIP_ARM_CUSTOM endchoice # ARM MCU selection +config ARCH_CHIP_STM32 + bool + default n + ---help--- + Common STM32 architecture selector. This is selected by the concrete + STM32 family options and gates shared STM32 Kconfig options. + config ARCH_ARM7TDMI bool default n @@ -1211,7 +1316,7 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32 + default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 @@ -1713,7 +1818,7 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32 +if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 source "arch/arm/src/stm32/Kconfig" endif if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 @@ -1746,6 +1851,9 @@ endif if ARCH_CHIP_STM32WL5 source "arch/arm/src/stm32wl5/Kconfig" endif +if ARCH_CHIP_STM32 +source "arch/arm/src/common/stm32/Kconfig" +endif if ARCH_CHIP_STR71X source "arch/arm/src/str71x/Kconfig" endif diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig new file mode 100644 index 0000000000000..9d915d742888b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig @@ -0,0 +1,1326 @@ +# +# Common STM32 Kconfig options shared by STM32 families. +# + +menu "Common STM32 Configuration Options" + depends on ARCH_CHIP_STM32 + +config STM32_SERIALDRIVER + bool + +config STM32_1WIREDRIVER + bool + +config STM32_HCIUART + bool + +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "CAN character driver or SocketCAN support" + depends on STM32_CAN + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32F7 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32F7 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FDCAN1 frame format" + depends on STM32_FDCAN1 + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FDCAN1 mode" + depends on STM32_FDCAN1 + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FDCAN2 frame format" + depends on STM32_FDCAN2 + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FDCAN2 mode" + depends on STM32_FDCAN2 + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" +# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" +# Moved from arch/arm/src/stm32f0l0g0/Kconfig and shared by STM32 families. +choice + prompt "Override Flash Size Designator" + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32F series parts numbering (sans the package type) ends with a number or letter + that designates the FLASH size. + + Designator Size in KiB + 4 16 + 6 32 + 8 64 + B 128 + C 256 + D 384 + E 512 + F 768 + G 1024 + I 2048 + + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. + + Examples: + If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of + the part with a 2048 KiB Flash is released in the future one could simply select + the 'I' designator here. + + +config STM32_FLASH_OVERRIDE_4 + bool "4 16KiB" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_D + bool "D 384KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_F + bool "F 768KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_C_256 + bool "C 256 KB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320 KB" + +config STM32_FLASH_OVERRIDE_E_512 + bool "E 512 KB" + +config STM32_FLASH_OVERRIDE_Y_640 + bool "Y 640 KB" + +config STM32_FLASH_OVERRIDE_G_1024 + bool "G 1024 KB" + +endchoice # Override Flash Size Designator +# Moved from arch/arm/src/stm32f0l0g0/Kconfig and shared by STM32 families. +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "Transfer technique" + depends on STM32_QSPI + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "Bank selection" + depends on STM32_QSPI + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "DMA Priority" + depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable +# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice +# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice +# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. +# Moved from arch/arm/src/stm32l5/Kconfig and shared by STM32 families. +endmenu # Common STM32 Configuration Options From 4b738d81a9c3a0b6f23aa91cc6b0d33537e4a62a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:23:32 +0200 Subject: [PATCH 02/52] !arch/stm32: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32 public hardware definition macros were renamed to the common STM32_* prefix. Out-of-tree code must update IRQ, peripheral-count, SRAM, and related macro references from family-specific prefixes to the new STM32_* names. Rename family-specific hardware definition prefixes to the standard STM32_ prefix across all STM32 families: IRQ vectors: - STM32L4: STM32L4_IRQ_ -> STM32_IRQ_ - STM32L5: STM32L5_IRQ_ -> STM32_IRQ_ - STM32WB: STM32WB_IRQ_ -> STM32_IRQ_ - STM32WL5: STM32WL5_IRQ_ -> STM32_IRQ_ Peripheral count and SRAM macros: - STM32F7: STM32F7_N*, STM32F7_SRAM*, STM32F7_ITCM*, STM32F7_DTCM* -> STM32_* - STM32H5: STM32H5_N*, STM32H5_SRAM*, STM32H5_QSPI*, STM32H5_OCTOSPI* -> STM32_* - STM32WB: STM32WB_N*, STM32WB_SRAM* -> STM32_* - STM32N6: STM32N6_N*, STM32N6_SRAM* -> STM32_* Signed-off-by: raiden00pl --- arch/arm/include/stm32f7/chip.h | 188 +-- arch/arm/include/stm32f7/irq.h | 6 +- arch/arm/include/stm32h5/chip.h | 102 +- arch/arm/include/stm32h5/irq.h | 4 +- arch/arm/include/stm32h5/stm32h5xx_irq.h | 22 +- arch/arm/include/stm32h7/chip.h | 238 ++-- arch/arm/include/stm32h7/irq.h | 12 +- arch/arm/include/stm32l4/chip.h | 474 +++---- arch/arm/include/stm32l4/irq.h | 38 +- arch/arm/include/stm32l4/stm32l4x3xx_irq.h | 174 +-- arch/arm/include/stm32l4/stm32l4x5xx_irq.h | 180 +-- arch/arm/include/stm32l4/stm32l4x6xx_irq.h | 204 +-- arch/arm/include/stm32l4/stm32l4xrxx_irq.h | 200 +-- arch/arm/include/stm32l5/chip.h | 66 +- arch/arm/include/stm32l5/irq.h | 2 +- arch/arm/include/stm32l5/stm32l562xx_irq.h | 224 ++-- arch/arm/include/stm32l5/stm32l5_irq.h | 36 +- arch/arm/include/stm32n6/chip.h | 6 +- arch/arm/include/stm32u5/chip.h | 12 +- arch/arm/include/stm32u5/irq.h | 8 +- arch/arm/include/stm32u5/stm32u5xx_irq.h | 16 +- arch/arm/include/stm32wb/chip.h | 148 +-- arch/arm/include/stm32wb/irq.h | 30 +- arch/arm/include/stm32wb/stm32wb_irq.h | 196 +-- arch/arm/include/stm32wl5/chip.h | 40 +- arch/arm/include/stm32wl5/irq.h | 32 +- .../include/stm32wl5/stm32wl5xxx_cpu1_irq.h | 142 +- arch/arm/src/stm32f7/hardware/stm32_adc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_can.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_dma.h | 6 +- .../arm/src/stm32f7/hardware/stm32_ethernet.h | 10 +- arch/arm/src/stm32f7/hardware/stm32_exti.h | 8 +- arch/arm/src/stm32f7/hardware/stm32_flash.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_gpio.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_i2c.h | 6 +- .../src/stm32f7/hardware/stm32_memorymap.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_pinmap.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_pwr.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32f7/hardware/stm32_rcc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_sai.h | 112 +- arch/arm/src/stm32f7/hardware/stm32_sdmmc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_spi.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_syscfg.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_tim.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_uart.h | 6 +- .../src/stm32f7/hardware/stm32f72xx73xx_adc.h | 6 +- .../src/stm32f7/hardware/stm32f72xx73xx_dma.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_flash.h | 38 +- .../stm32f7/hardware/stm32f72xx73xx_gpio.h | 26 +- .../hardware/stm32f72xx73xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_pinmap.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_rcc.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_spi.h | 12 +- .../stm32f7/hardware/stm32f72xx73xx_syscfg.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_tim.h | 28 +- .../stm32f7/hardware/stm32f72xx73xx_uart.h | 20 +- .../src/stm32f7/hardware/stm32f74xx75xx_dma.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_flash.h | 36 +- .../stm32f7/hardware/stm32f74xx75xx_gpio.h | 26 +- .../hardware/stm32f74xx75xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_pinmap.h | 6 +- .../src/stm32f7/hardware/stm32f74xx75xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f74xx75xx_rcc.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_syscfg.h | 4 +- .../src/stm32f7/hardware/stm32f74xx75xx_tim.h | 28 +- .../src/stm32f7/hardware/stm32f74xx77xx_adc.h | 6 +- .../src/stm32f7/hardware/stm32f74xx77xx_i2c.h | 8 +- .../src/stm32f7/hardware/stm32f74xx77xx_spi.h | 16 +- .../stm32f7/hardware/stm32f74xx77xx_uart.h | 22 +- .../src/stm32f7/hardware/stm32f76xx77xx_dma.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_flash.h | 48 +- .../stm32f7/hardware/stm32f76xx77xx_gpio.h | 26 +- .../hardware/stm32f76xx77xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_pinmap.h | 6 +- .../src/stm32f7/hardware/stm32f76xx77xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f76xx77xx_rcc.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_syscfg.h | 4 +- .../src/stm32f7/hardware/stm32f76xx77xx_tim.h | 28 +- arch/arm/src/stm32f7/stm32_adc.c | 182 +-- arch/arm/src/stm32f7/stm32_adc.h | 494 +++---- arch/arm/src/stm32f7/stm32_allocateheap.c | 14 +- arch/arm/src/stm32f7/stm32_bbsram.c | 20 +- arch/arm/src/stm32f7/stm32_bbsram.h | 24 +- arch/arm/src/stm32f7/stm32_can.c | 36 +- arch/arm/src/stm32f7/stm32_can.h | 46 +- arch/arm/src/stm32f7/stm32_can_sock.c | 62 +- arch/arm/src/stm32f7/stm32_capture.c | 122 +- arch/arm/src/stm32f7/stm32_config.h | 142 +- arch/arm/src/stm32f7/stm32_dma.c | 24 +- arch/arm/src/stm32f7/stm32_dma.h | 2 +- arch/arm/src/stm32f7/stm32_dma2d.c | 42 +- arch/arm/src/stm32f7/stm32_dma2d.h | 2 +- arch/arm/src/stm32f7/stm32_dtcm.h | 8 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 36 +- arch/arm/src/stm32f7/stm32_ethernet.c | 264 ++-- arch/arm/src/stm32f7/stm32_ethernet.h | 10 +- arch/arm/src/stm32f7/stm32_exti_gpio.c | 8 +- arch/arm/src/stm32f7/stm32_fmc.c | 4 +- arch/arm/src/stm32f7/stm32_foc.c | 182 +-- arch/arm/src/stm32f7/stm32_gpio.c | 38 +- arch/arm/src/stm32f7/stm32_gpio.h | 2 +- arch/arm/src/stm32f7/stm32_i2c.c | 112 +- arch/arm/src/stm32f7/stm32_i2c.h | 8 +- arch/arm/src/stm32f7/stm32_i2s.c | 202 +-- arch/arm/src/stm32f7/stm32_irq.c | 8 +- arch/arm/src/stm32f7/stm32_lse.c | 32 +- arch/arm/src/stm32f7/stm32_ltdc.c | 326 ++--- arch/arm/src/stm32f7/stm32_ltdc.h | 4 +- arch/arm/src/stm32f7/stm32_otg.h | 8 +- arch/arm/src/stm32f7/stm32_otgdev.c | 44 +- arch/arm/src/stm32f7/stm32_otghost.c | 82 +- arch/arm/src/stm32f7/stm32_pulsecount.c | 88 +- arch/arm/src/stm32f7/stm32_pwm.c | 588 ++++----- arch/arm/src/stm32f7/stm32_pwm.h | 522 ++++---- arch/arm/src/stm32f7/stm32_pwr.c | 2 +- arch/arm/src/stm32f7/stm32_qencoder.c | 106 +- arch/arm/src/stm32f7/stm32_qencoder.h | 44 +- arch/arm/src/stm32f7/stm32_qspi.c | 102 +- arch/arm/src/stm32f7/stm32_qspi.h | 4 +- arch/arm/src/stm32f7/stm32_rcc.c | 18 +- arch/arm/src/stm32f7/stm32_rcc.h | 8 +- arch/arm/src/stm32f7/stm32_rng.c | 4 +- arch/arm/src/stm32f7/stm32_rtc.c | 44 +- arch/arm/src/stm32f7/stm32_rtc.h | 20 +- arch/arm/src/stm32f7/stm32_sai.c | 210 +-- arch/arm/src/stm32f7/stm32_sdmmc.c | 154 +-- arch/arm/src/stm32f7/stm32_serial.c | 140 +- arch/arm/src/stm32f7/stm32_spi.c | 168 +-- arch/arm/src/stm32f7/stm32_spi.h | 24 +- arch/arm/src/stm32f7/stm32_tickless.c | 60 +- arch/arm/src/stm32f7/stm32_tim.c | 306 ++--- arch/arm/src/stm32f7/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32f7/stm32_uart.h | 104 +- arch/arm/src/stm32f7/stm32_usbhost.h | 20 +- arch/arm/src/stm32f7/stm32_waste.h | 6 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 186 +-- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 166 +-- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 172 +-- .../arm/src/stm32h5/hardware/stm32_ethernet.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_flash.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_gpdma.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_gpio.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_i2c.h | 4 +- .../src/stm32h5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_pinmap.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_pwr.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_rcc.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_sbs.h | 8 +- arch/arm/src/stm32h5/hardware/stm32_uart.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_usbfs.h | 4 +- .../src/stm32h5/hardware/stm32h56xxx_pinmap.h | 6 +- .../src/stm32h5/hardware/stm32h5xxx_flash.h | 28 +- .../src/stm32h5/hardware/stm32h5xxx_gpio.h | 18 +- .../arm/src/stm32h5/hardware/stm32h5xxx_i2c.h | 8 +- .../arm/src/stm32h5/hardware/stm32h5xxx_pwr.h | 4 +- .../arm/src/stm32h5/hardware/stm32h5xxx_rcc.h | 4 +- .../arm/src/stm32h5/hardware/stm32h5xxx_spi.h | 16 +- .../src/stm32h5/hardware/stm32h5xxx_uart.h | 26 +- arch/arm/src/stm32h5/stm32_adc.c | 98 +- arch/arm/src/stm32h5/stm32_adc.h | 456 +++---- arch/arm/src/stm32h5/stm32_dbgmcu.h | 2 +- arch/arm/src/stm32h5/stm32_dma.c | 6 +- arch/arm/src/stm32h5/stm32_dma.h | 8 +- arch/arm/src/stm32h5/stm32_dts.c | 30 +- arch/arm/src/stm32h5/stm32_ethernet.c | 296 ++--- arch/arm/src/stm32h5/stm32_ethernet.h | 10 +- arch/arm/src/stm32h5/stm32_fdcan.c | 138 +- arch/arm/src/stm32h5/stm32_fdcan.h | 4 +- arch/arm/src/stm32h5/stm32_flash.c | 2 +- arch/arm/src/stm32h5/stm32_gpio.c | 24 +- arch/arm/src/stm32h5/stm32_gpio.h | 4 +- arch/arm/src/stm32h5/stm32_hsi48.c | 4 +- arch/arm/src/stm32h5/stm32_hsi48.h | 4 +- arch/arm/src/stm32h5/stm32_i2c.c | 198 +-- arch/arm/src/stm32h5/stm32_i2c.h | 8 +- arch/arm/src/stm32h5/stm32_icache.c | 72 +- arch/arm/src/stm32h5/stm32_idle.c | 2 +- arch/arm/src/stm32h5/stm32_lowputc.c | 426 +++--- arch/arm/src/stm32h5/stm32_lse.c | 20 +- arch/arm/src/stm32h5/stm32_pulsecount.c | 92 +- arch/arm/src/stm32h5/stm32_pwm.c | 662 +++++----- arch/arm/src/stm32h5/stm32_pwm.h | 530 ++++---- arch/arm/src/stm32h5/stm32_qspi.c | 108 +- arch/arm/src/stm32h5/stm32_qspi.h | 4 +- arch/arm/src/stm32h5/stm32_rcc.c | 30 +- arch/arm/src/stm32h5/stm32_rcc.h | 10 +- arch/arm/src/stm32h5/stm32_serial.c | 150 +-- arch/arm/src/stm32h5/stm32_spi.c | 186 +-- arch/arm/src/stm32h5/stm32_spi.h | 24 +- arch/arm/src/stm32h5/stm32_start.c | 10 +- arch/arm/src/stm32h5/stm32_tim.c | 306 ++--- arch/arm/src/stm32h5/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32h5/stm32_timerisr.c | 6 +- arch/arm/src/stm32h5/stm32_uart.h | 230 ++-- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 178 +-- arch/arm/src/stm32h5/stm32_usbdrdhost.h | 12 +- arch/arm/src/stm32h5/stm32_usbfs.c | 16 +- arch/arm/src/stm32h5/stm32h563xx_flash.c | 50 +- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 198 +-- arch/arm/src/stm32h7/hardware/stm32_dmamux.h | 10 +- .../arm/src/stm32h7/hardware/stm32_ethernet.h | 12 +- arch/arm/src/stm32h7/hardware/stm32_exti.h | 12 +- arch/arm/src/stm32h7/hardware/stm32_flash.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_gpio.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_i2c.h | 10 +- .../src/stm32h7/hardware/stm32_memorymap.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_pinmap.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_pwr.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32h7/hardware/stm32_rcc.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_sdmmc.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_spi.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_syscfg.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_uart.h | 10 +- .../src/stm32h7/hardware/stm32h7x3xx_gpio.h | 34 +- .../src/stm32h7/hardware/stm32h7x3xx_i2c.h | 8 +- .../stm32h7/hardware/stm32h7x3xx_memorymap.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 12 +- .../src/stm32h7/hardware/stm32h7x3xx_pwr.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_spi.h | 24 +- .../src/stm32h7/hardware/stm32h7x3xx_syscfg.h | 6 +- .../src/stm32h7/hardware/stm32h7x3xx_uart.h | 28 +- arch/arm/src/stm32h7/stm32_adc.c | 76 +- arch/arm/src/stm32h7/stm32_adc.h | 480 +++---- arch/arm/src/stm32h7/stm32_allocateheap.c | 34 +- arch/arm/src/stm32h7/stm32_bbsram.c | 24 +- arch/arm/src/stm32h7/stm32_bbsram.h | 20 +- arch/arm/src/stm32h7/stm32_capture.c | 160 +-- .../arm/src/stm32h7/stm32_capture_lowerhalf.c | 160 +-- arch/arm/src/stm32h7/stm32_dma.c | 88 +- arch/arm/src/stm32h7/stm32_dma.h | 2 +- arch/arm/src/stm32h7/stm32_dtcm.h | 2 +- arch/arm/src/stm32h7/stm32_dualcore.c | 22 +- arch/arm/src/stm32h7/stm32_dualcore.h | 6 +- arch/arm/src/stm32h7/stm32_ethernet.c | 380 +++--- arch/arm/src/stm32h7/stm32_ethernet.h | 10 +- arch/arm/src/stm32h7/stm32_exti_gpio.c | 12 +- arch/arm/src/stm32h7/stm32_fdcan_sock.c | 54 +- arch/arm/src/stm32h7/stm32_fdcan_sock.h | 4 +- arch/arm/src/stm32h7/stm32_flash.c | 10 +- arch/arm/src/stm32h7/stm32_fmc.c | 6 +- arch/arm/src/stm32h7/stm32_gpio.c | 48 +- arch/arm/src/stm32h7/stm32_gpio.h | 26 +- arch/arm/src/stm32h7/stm32_hsem.c | 6 +- arch/arm/src/stm32h7/stm32_i2c.c | 100 +- arch/arm/src/stm32h7/stm32_i2c.h | 8 +- arch/arm/src/stm32h7/stm32_irq.c | 8 +- arch/arm/src/stm32h7/stm32_iwdg.c | 44 +- arch/arm/src/stm32h7/stm32_lptim.c | 52 +- arch/arm/src/stm32h7/stm32_lse.c | 30 +- arch/arm/src/stm32h7/stm32_ltdc.c | 338 ++--- arch/arm/src/stm32h7/stm32_ltdc.h | 6 +- arch/arm/src/stm32h7/stm32_mdio.c | 2 +- arch/arm/src/stm32h7/stm32_mpuinit.c | 4 +- arch/arm/src/stm32h7/stm32_oneshot.c | 12 +- arch/arm/src/stm32h7/stm32_oneshot.h | 20 +- arch/arm/src/stm32h7/stm32_otg.h | 18 +- arch/arm/src/stm32h7/stm32_otgdev.c | 66 +- arch/arm/src/stm32h7/stm32_otghost.c | 90 +- arch/arm/src/stm32h7/stm32_pulsecount.c | 94 +- arch/arm/src/stm32h7/stm32_pwm.c | 660 +++++----- arch/arm/src/stm32h7/stm32_pwm.h | 530 ++++---- arch/arm/src/stm32h7/stm32_pwr.c | 2 +- arch/arm/src/stm32h7/stm32_qencoder.c | 106 +- arch/arm/src/stm32h7/stm32_qencoder.h | 44 +- arch/arm/src/stm32h7/stm32_qspi.c | 102 +- arch/arm/src/stm32h7/stm32_qspi.h | 4 +- arch/arm/src/stm32h7/stm32_rcc.c | 26 +- arch/arm/src/stm32h7/stm32_rcc.h | 6 +- arch/arm/src/stm32h7/stm32_rng.c | 4 +- arch/arm/src/stm32h7/stm32_rptun.c | 22 +- arch/arm/src/stm32h7/stm32_rtc.c | 44 +- arch/arm/src/stm32h7/stm32_rtc.h | 20 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 98 +- arch/arm/src/stm32h7/stm32_serial.c | 256 ++-- arch/arm/src/stm32h7/stm32_spi.c | 178 +-- arch/arm/src/stm32h7/stm32_spi.h | 24 +- arch/arm/src/stm32h7/stm32_spi_slave.c | 136 +- arch/arm/src/stm32h7/stm32_start.c | 16 +- arch/arm/src/stm32h7/stm32_tickless.c | 60 +- arch/arm/src/stm32h7/stm32_tim.c | 306 ++--- arch/arm/src/stm32h7/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32h7/stm32_timerisr.c | 6 +- arch/arm/src/stm32h7/stm32_uart.h | 104 +- arch/arm/src/stm32h7/stm32_usbhost.h | 20 +- arch/arm/src/stm32h7/stm32_wdg.h | 4 +- arch/arm/src/stm32h7/stm32_wwdg.c | 24 +- arch/arm/src/stm32h7/stm32h743xx_flash.c | 52 +- arch/arm/src/stm32h7/stm32h7b3xx_flash.c | 38 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 112 +- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 96 +- arch/arm/src/stm32l4/chip.h | 2 +- arch/arm/src/stm32l4/hardware/stm32l4_adc.h | 270 ++-- arch/arm/src/stm32l4/hardware/stm32l4_can.h | 198 +-- arch/arm/src/stm32l4/hardware/stm32l4_comp.h | 28 +- arch/arm/src/stm32l4/hardware/stm32l4_crs.h | 22 +- arch/arm/src/stm32l4/hardware/stm32l4_dac.h | 86 +- arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h | 224 ++-- arch/arm/src/stm32l4/hardware/stm32l4_exti.h | 122 +- arch/arm/src/stm32l4/hardware/stm32l4_flash.h | 224 ++-- arch/arm/src/stm32l4/hardware/stm32l4_gpio.h | 264 ++-- arch/arm/src/stm32l4/hardware/stm32l4_i2c.h | 124 +- arch/arm/src/stm32l4/hardware/stm32l4_lptim.h | 56 +- .../src/stm32l4/hardware/stm32l4_memorymap.h | 280 ++-- .../arm/src/stm32l4/hardware/stm32l4_pinmap.h | 14 +- arch/arm/src/stm32l4/hardware/stm32l4_pwr.h | 126 +- arch/arm/src/stm32l4/hardware/stm32l4_qspi.h | 62 +- arch/arm/src/stm32l4/hardware/stm32l4_rng.h | 18 +- arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h | 222 ++-- arch/arm/src/stm32l4/hardware/stm32l4_sai.h | 118 +- arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h | 4 +- arch/arm/src/stm32l4/hardware/stm32l4_spi.h | 70 +- .../arm/src/stm32l4/hardware/stm32l4_syscfg.h | 14 +- arch/arm/src/stm32l4/hardware/stm32l4_tim.h | 514 ++++---- arch/arm/src/stm32l4/hardware/stm32l4_uart.h | 148 +-- .../arm/src/stm32l4/hardware/stm32l4_usbdev.h | 102 +- arch/arm/src/stm32l4/hardware/stm32l4_wdg.h | 38 +- .../src/stm32l4/hardware/stm32l4x3xx_dma.h | 480 +++---- .../stm32l4/hardware/stm32l4x3xx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4x3xx_rcc.h | 132 +- .../src/stm32l4/hardware/stm32l4x3xx_syscfg.h | 48 +- .../src/stm32l4/hardware/stm32l4x5xx_dma.h | 532 ++++---- .../stm32l4/hardware/stm32l4x5xx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4x5xx_otgfs.h | 244 ++-- .../src/stm32l4/hardware/stm32l4x5xx_rcc.h | 124 +- .../src/stm32l4/hardware/stm32l4x5xx_syscfg.h | 48 +- .../src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h | 4 +- .../src/stm32l4/hardware/stm32l4x6xx_dma.h | 550 ++++---- .../stm32l4/hardware/stm32l4x6xx_firewall.h | 32 +- .../src/stm32l4/hardware/stm32l4x6xx_otgfs.h | 242 ++-- .../src/stm32l4/hardware/stm32l4x6xx_rcc.h | 134 +- .../src/stm32l4/hardware/stm32l4x6xx_syscfg.h | 52 +- .../src/stm32l4/hardware/stm32l4xrxx_dma.h | 260 ++-- .../src/stm32l4/hardware/stm32l4xrxx_dmamux.h | 111 +- .../stm32l4/hardware/stm32l4xrxx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4xrxx_rcc.h | 132 +- .../src/stm32l4/hardware/stm32l4xrxx_syscfg.h | 52 +- arch/arm/src/stm32l4/stm32l4.h | 6 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 128 +- arch/arm/src/stm32l4/stm32l4_1wire.h | 6 +- arch/arm/src/stm32l4/stm32l4_adc.c | 420 +++--- arch/arm/src/stm32l4/stm32l4_adc.h | 410 +++--- arch/arm/src/stm32l4/stm32l4_allocateheap.c | 44 +- arch/arm/src/stm32l4/stm32l4_can.c | 266 ++-- arch/arm/src/stm32l4/stm32l4_can.h | 38 +- arch/arm/src/stm32l4/stm32l4_comp.c | 98 +- arch/arm/src/stm32l4/stm32l4_comp.h | 82 +- arch/arm/src/stm32l4/stm32l4_dac.c | 334 ++--- arch/arm/src/stm32l4/stm32l4_dac.h | 62 +- arch/arm/src/stm32l4/stm32l4_dbgmcu.h | 14 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 226 ++-- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 202 +-- arch/arm/src/stm32l4/stm32l4_dfumode.c | 68 +- arch/arm/src/stm32l4/stm32l4_dfumode.h | 8 +- arch/arm/src/stm32l4/stm32l4_dma.c | 6 +- arch/arm/src/stm32l4/stm32l4_dma.h | 24 +- arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 52 +- arch/arm/src/stm32l4/stm32l4_exti.h | 8 +- arch/arm/src/stm32l4/stm32l4_exti_alarm.c | 16 +- arch/arm/src/stm32l4/stm32l4_exti_comp.c | 28 +- arch/arm/src/stm32l4/stm32l4_exti_gpio.c | 30 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.c | 16 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.h | 6 +- arch/arm/src/stm32l4/stm32l4_exti_wakeup.c | 16 +- arch/arm/src/stm32l4/stm32l4_firewall.c | 24 +- arch/arm/src/stm32l4/stm32l4_firewall.h | 14 +- arch/arm/src/stm32l4/stm32l4_flash.c | 112 +- arch/arm/src/stm32l4/stm32l4_flash.h | 6 +- arch/arm/src/stm32l4/stm32l4_freerun.c | 32 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 10 +- arch/arm/src/stm32l4/stm32l4_gpio.c | 82 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 12 +- arch/arm/src/stm32l4/stm32l4_hsi48.c | 26 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 10 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 212 +-- arch/arm/src/stm32l4/stm32l4_i2c.h | 14 +- arch/arm/src/stm32l4/stm32l4_idle.c | 2 +- arch/arm/src/stm32l4/stm32l4_irq.c | 50 +- arch/arm/src/stm32l4/stm32l4_iwdg.c | 44 +- arch/arm/src/stm32l4/stm32l4_lowputc.c | 240 ++-- arch/arm/src/stm32l4/stm32l4_lowputc.h | 6 +- arch/arm/src/stm32l4/stm32l4_lptim.c | 180 +-- arch/arm/src/stm32l4/stm32l4_lptim.h | 64 +- arch/arm/src/stm32l4/stm32l4_lse.c | 34 +- arch/arm/src/stm32l4/stm32l4_lsi.c | 6 +- arch/arm/src/stm32l4/stm32l4_mpuinit.h | 6 +- arch/arm/src/stm32l4/stm32l4_oneshot.c | 40 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 26 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 16 +- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 1010 +++++++------- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 408 +++--- arch/arm/src/stm32l4/stm32l4_pm.h | 6 +- arch/arm/src/stm32l4/stm32l4_pmlpr.c | 14 +- arch/arm/src/stm32l4/stm32l4_pmstandby.c | 6 +- arch/arm/src/stm32l4/stm32l4_pmstop.c | 10 +- arch/arm/src/stm32l4/stm32l4_pulsecount.c | 230 ++-- arch/arm/src/stm32l4/stm32l4_pulsecount.h | 6 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 1157 +++++++++-------- arch/arm/src/stm32l4/stm32l4_pwm.h | 594 ++++----- arch/arm/src/stm32l4/stm32l4_pwr.c | 50 +- arch/arm/src/stm32l4/stm32l4_pwr.h | 12 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 328 ++--- arch/arm/src/stm32l4/stm32l4_qencoder.h | 50 +- arch/arm/src/stm32l4/stm32l4_qspi.c | 308 ++--- arch/arm/src/stm32l4/stm32l4_qspi.h | 10 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 34 +- arch/arm/src/stm32l4/stm32l4_rcc.h | 24 +- arch/arm/src/stm32l4/stm32l4_rng.c | 32 +- arch/arm/src/stm32l4/stm32l4_rtc.c | 234 ++-- arch/arm/src/stm32l4/stm32l4_rtc.h | 30 +- arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 4 +- arch/arm/src/stm32l4/stm32l4_sai.c | 168 +-- arch/arm/src/stm32l4/stm32l4_sai.h | 6 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 150 +-- arch/arm/src/stm32l4/stm32l4_serial.c | 294 ++--- arch/arm/src/stm32l4/stm32l4_spi.c | 158 +-- arch/arm/src/stm32l4/stm32l4_spi.h | 18 +- arch/arm/src/stm32l4/stm32l4_start.c | 6 +- arch/arm/src/stm32l4/stm32l4_start.h | 6 +- arch/arm/src/stm32l4/stm32l4_tickless.c | 20 +- arch/arm/src/stm32l4/stm32l4_tim.c | 692 +++++----- arch/arm/src/stm32l4/stm32l4_tim.h | 92 +- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 138 +- arch/arm/src/stm32l4/stm32l4_timerisr.c | 14 +- arch/arm/src/stm32l4/stm32l4_uart.h | 112 +- arch/arm/src/stm32l4/stm32l4_uid.c | 6 +- arch/arm/src/stm32l4/stm32l4_uid.h | 6 +- arch/arm/src/stm32l4/stm32l4_usbdev.c | 660 +++++----- arch/arm/src/stm32l4/stm32l4_usbdev.h | 6 +- arch/arm/src/stm32l4/stm32l4_usbhost.h | 28 +- arch/arm/src/stm32l4/stm32l4_userspace.h | 6 +- arch/arm/src/stm32l4/stm32l4_waste.h | 6 +- arch/arm/src/stm32l4/stm32l4_wdg.h | 10 +- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 334 ++--- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 324 ++--- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 156 +-- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 386 +++--- arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 214 +-- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 358 ++--- arch/arm/src/stm32l5/chip.h | 2 +- .../src/stm32l5/hardware/stm32l562xx_rcc.h | 164 +-- .../src/stm32l5/hardware/stm32l562xx_syscfg.h | 48 +- arch/arm/src/stm32l5/hardware/stm32l5_exti.h | 98 +- arch/arm/src/stm32l5/hardware/stm32l5_flash.h | 186 +-- arch/arm/src/stm32l5/hardware/stm32l5_gpio.h | 264 ++-- .../src/stm32l5/hardware/stm32l5_memorymap.h | 200 +-- .../arm/src/stm32l5/hardware/stm32l5_pinmap.h | 8 +- arch/arm/src/stm32l5/hardware/stm32l5_pwr.h | 106 +- arch/arm/src/stm32l5/hardware/stm32l5_spi.h | 72 +- .../arm/src/stm32l5/hardware/stm32l5_syscfg.h | 8 +- arch/arm/src/stm32l5/hardware/stm32l5_tim.h | 514 ++++---- arch/arm/src/stm32l5/hardware/stm32l5_uart.h | 160 +-- arch/arm/src/stm32l5/stm32l5.h | 6 +- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 320 ++--- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 44 +- arch/arm/src/stm32l5/stm32l5_dbgmcu.h | 8 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 52 +- arch/arm/src/stm32l5/stm32l5_exti.h | 8 +- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 16 +- arch/arm/src/stm32l5/stm32l5_flash.c | 86 +- arch/arm/src/stm32l5/stm32l5_flash.h | 6 +- arch/arm/src/stm32l5/stm32l5_gpio.c | 64 +- arch/arm/src/stm32l5/stm32l5_gpio.h | 10 +- arch/arm/src/stm32l5/stm32l5_idle.c | 2 +- arch/arm/src/stm32l5/stm32l5_irq.c | 50 +- arch/arm/src/stm32l5/stm32l5_lowputc.c | 244 ++-- arch/arm/src/stm32l5/stm32l5_lowputc.h | 6 +- arch/arm/src/stm32l5/stm32l5_lse.c | 36 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 6 +- arch/arm/src/stm32l5/stm32l5_mpuinit.h | 6 +- arch/arm/src/stm32l5/stm32l5_pwr.c | 32 +- arch/arm/src/stm32l5/stm32l5_pwr.h | 6 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 26 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 20 +- arch/arm/src/stm32l5/stm32l5_serial.c | 290 ++--- arch/arm/src/stm32l5/stm32l5_spi.c | 160 +-- arch/arm/src/stm32l5/stm32l5_spi.h | 18 +- arch/arm/src/stm32l5/stm32l5_start.c | 6 +- arch/arm/src/stm32l5/stm32l5_start.h | 6 +- arch/arm/src/stm32l5/stm32l5_tim.c | 600 ++++----- arch/arm/src/stm32l5/stm32l5_tim.h | 84 +- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 138 +- arch/arm/src/stm32l5/stm32l5_timerisr.c | 14 +- arch/arm/src/stm32l5/stm32l5_uart.h | 110 +- arch/arm/src/stm32l5/stm32l5_uid.c | 6 +- arch/arm/src/stm32l5/stm32l5_uid.h | 6 +- arch/arm/src/stm32l5/stm32l5_userspace.h | 6 +- arch/arm/src/stm32l5/stm32l5_waste.h | 6 +- arch/arm/src/stm32n6/stm32_gpio.c | 8 +- arch/arm/src/stm32n6/stm32_gpio.h | 2 +- arch/arm/src/stm32n6/stm32_serial.c | 10 +- arch/arm/src/stm32u5/hardware/stm32_flash.h | 36 +- .../src/stm32u5/hardware/stm32_memorymap.h | 12 +- arch/arm/src/stm32u5/hardware/stm32_pinmap.h | 2 +- arch/arm/src/stm32u5/hardware/stm32_spi.h | 8 +- arch/arm/src/stm32u5/hardware/stm32_syscfg.h | 2 +- arch/arm/src/stm32u5/hardware/stm32_tim.h | 508 ++++---- arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h | 10 +- arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h | 10 +- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 54 +- arch/arm/src/stm32u5/stm32_allocateheap.c | 36 +- arch/arm/src/stm32u5/stm32_dbgmcu.h | 2 +- arch/arm/src/stm32u5/stm32_exti.h | 2 +- arch/arm/src/stm32u5/stm32_flash.c | 6 +- arch/arm/src/stm32u5/stm32_gpio.h | 2 +- arch/arm/src/stm32u5/stm32_i2c.c | 96 +- arch/arm/src/stm32u5/stm32_i2c.h | 8 +- arch/arm/src/stm32u5/stm32_idle.c | 2 +- arch/arm/src/stm32u5/stm32_lse.c | 20 +- arch/arm/src/stm32u5/stm32_rcc.c | 26 +- arch/arm/src/stm32u5/stm32_rcc.h | 10 +- arch/arm/src/stm32u5/stm32_serial.c | 96 +- arch/arm/src/stm32u5/stm32_spi.c | 118 +- arch/arm/src/stm32u5/stm32_spi.h | 12 +- arch/arm/src/stm32u5/stm32_start.c | 2 +- arch/arm/src/stm32u5/stm32_tim.c | 600 ++++----- arch/arm/src/stm32u5/stm32_tim.h | 72 +- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 138 +- arch/arm/src/stm32u5/stm32_timerisr.c | 6 +- arch/arm/src/stm32u5/stm32_uart.h | 110 +- arch/arm/src/stm32u5/stm32_uid.c | 6 +- arch/arm/src/stm32u5/stm32u5xx_rcc.c | 170 +-- arch/arm/src/stm32wb/chip.h | 2 +- arch/arm/src/stm32wb/hardware/stm32wb_crs.h | 22 +- arch/arm/src/stm32wb/hardware/stm32wb_dma.h | 266 ++-- .../arm/src/stm32wb/hardware/stm32wb_dmamux.h | 117 +- arch/arm/src/stm32wb/hardware/stm32wb_exti.h | 70 +- arch/arm/src/stm32wb/hardware/stm32wb_flash.h | 168 +-- arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 166 +-- arch/arm/src/stm32wb/hardware/stm32wb_i2c.h | 76 +- arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h | 38 +- .../src/stm32wb/hardware/stm32wb_memorymap.h | 174 +-- .../arm/src/stm32wb/hardware/stm32wb_pinmap.h | 12 +- arch/arm/src/stm32wb/hardware/stm32wb_pwr.h | 96 +- arch/arm/src/stm32wb/hardware/stm32wb_rcc.h | 198 +-- arch/arm/src/stm32wb/hardware/stm32wb_rtc.h | 174 +-- arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 54 +- .../arm/src/stm32wb/hardware/stm32wb_syscfg.h | 64 +- arch/arm/src/stm32wb/hardware/stm32wb_tim.h | 290 ++--- arch/arm/src/stm32wb/hardware/stm32wb_uart.h | 56 +- .../src/stm32wb/hardware/stm32wbxx_pinmap.h | 140 +- arch/arm/src/stm32wb/stm32wb.h | 6 +- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 40 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 136 +- arch/arm/src/stm32wb/stm32wb_blehci.h | 6 +- arch/arm/src/stm32wb/stm32wb_dma.c | 210 +-- arch/arm/src/stm32wb/stm32wb_dma.h | 10 +- arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 32 +- arch/arm/src/stm32wb/stm32wb_exti.h | 6 +- arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 16 +- arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 16 +- arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 16 +- arch/arm/src/stm32wb/stm32wb_flash.c | 82 +- arch/arm/src/stm32wb/stm32wb_flash.h | 6 +- arch/arm/src/stm32wb/stm32wb_freerun.c | 36 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 10 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 50 +- arch/arm/src/stm32wb/stm32wb_gpio.h | 22 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 168 +-- arch/arm/src/stm32wb/stm32wb_i2c.h | 14 +- arch/arm/src/stm32wb/stm32wb_idle.c | 2 +- arch/arm/src/stm32wb/stm32wb_ipcc.c | 30 +- arch/arm/src/stm32wb/stm32wb_ipcc.h | 28 +- arch/arm/src/stm32wb/stm32wb_irq.c | 50 +- arch/arm/src/stm32wb/stm32wb_lowputc.c | 136 +- arch/arm/src/stm32wb/stm32wb_lowputc.h | 6 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 130 +- arch/arm/src/stm32wb/stm32wb_mbox.h | 42 +- arch/arm/src/stm32wb/stm32wb_mbox_list.h | 6 +- arch/arm/src/stm32wb/stm32wb_mbox_shci.h | 116 +- arch/arm/src/stm32wb/stm32wb_mpuinit.h | 6 +- arch/arm/src/stm32wb/stm32wb_oneshot.c | 40 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 26 +- arch/arm/src/stm32wb/stm32wb_pm.h | 6 +- arch/arm/src/stm32wb/stm32wb_pmlpr.c | 14 +- arch/arm/src/stm32wb/stm32wb_pmstandby.c | 6 +- arch/arm/src/stm32wb/stm32wb_pmstop.c | 8 +- arch/arm/src/stm32wb/stm32wb_pwr.c | 22 +- arch/arm/src/stm32wb/stm32wb_pwr.h | 6 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 334 ++--- arch/arm/src/stm32wb/stm32wb_rcc.h | 16 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 26 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 34 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 6 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 234 ++-- arch/arm/src/stm32wb/stm32wb_rtc.h | 30 +- arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 4 +- arch/arm/src/stm32wb/stm32wb_serial.c | 212 +-- arch/arm/src/stm32wb/stm32wb_spi.c | 142 +- arch/arm/src/stm32wb/stm32wb_spi.h | 14 +- arch/arm/src/stm32wb/stm32wb_start.c | 18 +- arch/arm/src/stm32wb/stm32wb_start.h | 6 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 78 +- arch/arm/src/stm32wb/stm32wb_tim.c | 360 ++--- arch/arm/src/stm32wb/stm32wb_tim.h | 94 +- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 74 +- arch/arm/src/stm32wb/stm32wb_timerisr.c | 14 +- arch/arm/src/stm32wb/stm32wb_uart.h | 32 +- arch/arm/src/stm32wb/stm32wb_uid.c | 6 +- arch/arm/src/stm32wb/stm32wb_uid.h | 6 +- arch/arm/src/stm32wb/stm32wb_userspace.h | 6 +- arch/arm/src/stm32wb/stm32wb_waste.h | 6 +- arch/arm/src/stm32wl5/chip.h | 2 +- .../arm/src/stm32wl5/hardware/stm32wl5_exti.h | 78 +- .../src/stm32wl5/hardware/stm32wl5_flash.h | 180 +-- .../arm/src/stm32wl5/hardware/stm32wl5_gpio.h | 130 +- .../arm/src/stm32wl5/hardware/stm32wl5_ipcc.h | 50 +- .../stm32wl5/hardware/stm32wl5_memorymap.h | 174 +-- .../src/stm32wl5/hardware/stm32wl5_pinmap.h | 6 +- arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h | 94 +- arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h | 176 +-- arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h | 104 +- .../src/stm32wl5/hardware/stm32wl5_syscfg.h | 74 +- arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h | 278 ++-- .../arm/src/stm32wl5/hardware/stm32wl5_uart.h | 102 +- arch/arm/src/stm32wl5/stm32wl5.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_allocateheap.c | 14 +- arch/arm/src/stm32wl5/stm32wl5_exti.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c | 28 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 80 +- arch/arm/src/stm32wl5/stm32wl5_flash.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_gpio.c | 50 +- arch/arm/src/stm32wl5/stm32wl5_gpio.h | 10 +- arch/arm/src/stm32wl5/stm32wl5_idle.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.c | 74 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 36 +- arch/arm/src/stm32wl5/stm32wl5_irq.c | 50 +- arch/arm/src/stm32wl5/stm32wl5_lowputc.c | 166 +-- arch/arm/src/stm32wl5/stm32wl5_lowputc.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_lse.c | 36 +- arch/arm/src/stm32wl5/stm32wl5_lsi.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_mpuinit.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_pwr.c | 14 +- arch/arm/src/stm32wl5/stm32wl5_pwr.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 258 ++-- arch/arm/src/stm32wl5/stm32wl5_rcc.h | 18 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 228 ++-- arch/arm/src/stm32wl5/stm32wl5_spi.c | 144 +- arch/arm/src/stm32wl5/stm32wl5_spi.h | 14 +- arch/arm/src/stm32wl5/stm32wl5_start.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_start.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_tim.c | 600 ++++----- arch/arm/src/stm32wl5/stm32wl5_tim.h | 78 +- .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 138 +- arch/arm/src/stm32wl5/stm32wl5_timerisr.c | 14 +- arch/arm/src/stm32wl5/stm32wl5_uart.h | 60 +- arch/arm/src/stm32wl5/stm32wl5_uid.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_uid.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_userspace.h | 6 +- arch/arm/src/stm32wl5/stm32wl5_waste.h | 6 +- .../arm/stm32f7/common/include/stm32_bh1750.h | 6 +- .../arm/stm32f7/common/include/stm32_bmi270.h | 6 +- .../stm32f7/common/include/stm32_can_setup.h | 8 +- .../common/include/stm32_cansock_setup.h | 8 +- .../arm/stm32f7/common/include/stm32_cs4344.h | 6 +- .../arm/stm32f7/common/include/stm32_romfs.h | 10 +- .../stm32f7/common/include/stm32_spitest.h | 8 +- .../arm/stm32f7/common/src/stm32_can_setup.c | 6 +- .../stm32f7/common/src/stm32_cansock_setup.c | 6 +- .../common/src/stm32_romfs_initialize.c | 28 +- boards/arm/stm32f7/common/src/stm32_spitest.c | 106 +- .../arm/stm32f7/nucleo-f722ze/include/board.h | 10 +- .../stm32f7/nucleo-f722ze/src/nucleo-f722ze.h | 22 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_adc.c | 22 +- .../stm32f7/nucleo-f722ze/src/stm32_bbsram.c | 22 +- .../stm32f7/nucleo-f722ze/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f722ze/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f722ze/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_usb.c | 4 +- .../arm/stm32f7/nucleo-f746zg/include/board.h | 10 +- .../stm32f7/nucleo-f746zg/src/nucleo-f746zg.h | 22 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_adc.c | 22 +- .../stm32f7/nucleo-f746zg/src/stm32_bbsram.c | 22 +- .../stm32f7/nucleo-f746zg/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f746zg/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f746zg/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_usb.c | 4 +- .../arm/stm32f7/nucleo-f767zi/include/board.h | 10 +- .../stm32f7/nucleo-f767zi/src/nucleo-f767zi.h | 22 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_adc.c | 22 +- .../stm32f7/nucleo-f767zi/src/stm32_bbsram.c | 22 +- .../stm32f7/nucleo-f767zi/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f767zi/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f767zi/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_usb.c | 4 +- .../stm32f7/steval-eth001v1/include/board.h | 6 +- .../steval-eth001v1/src/steval-eth001v1.h | 8 +- .../steval-eth001v1/src/stm32_bringup.c | 2 +- .../stm32f7/steval-eth001v1/src/stm32_foc.c | 28 +- .../arm/stm32f7/stm32f746-ws/include/board.h | 10 +- .../arm/stm32f7/stm32f746-ws/src/stm32_boot.c | 8 +- .../arm/stm32f7/stm32f746-ws/src/stm32_spi.c | 32 +- .../arm/stm32f7/stm32f746-ws/src/stm32_usb.c | 8 +- .../stm32f7/stm32f746-ws/src/stm32f746-ws.h | 8 +- .../stm32f7/stm32f746g-disco/include/board.h | 20 +- .../stm32f7/stm32f746g-disco/src/stm32_adc.c | 8 +- .../stm32f7/stm32f746g-disco/src/stm32_boot.c | 10 +- .../stm32f746g-disco/src/stm32_extmem.c | 4 +- .../stm32f7/stm32f746g-disco/src/stm32_lcd.c | 2 +- .../stm32f7/stm32f746g-disco/src/stm32_spi.c | 28 +- .../stm32f746g-disco/src/stm32_touchscreen.c | 4 +- .../stm32f7/stm32f746g-disco/src/stm32_usb.c | 8 +- .../stm32f746g-disco/src/stm32f746g-disco.h | 14 +- .../stm32f7/stm32f769i-disco/include/board.h | 10 +- .../stm32f7/stm32f769i-disco/src/stm32_boot.c | 8 +- .../stm32f769i-disco/src/stm32_extmem.c | 4 +- .../stm32f7/stm32f769i-disco/src/stm32_spi.c | 28 +- .../stm32f769i-disco/src/stm32f769i-disco.h | 8 +- .../stm32f777zit6-meadow/include/board.h | 12 +- .../stm32f777zit6-meadow/src/stm32_boot.c | 12 +- .../stm32f777zit6-meadow/src/stm32_extmem.c | 4 +- .../stm32f777zit6-meadow/src/stm32_spi.c | 28 +- .../stm32f777zit6-meadow/src/stm32_usb.c | 8 +- .../src/stm32f777zit6-meadow.h | 6 +- .../arm/stm32h5/nucleo-h563zi/include/board.h | 34 +- .../stm32h5/nucleo-h563zi/src/nucleo-h563zi.h | 10 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_adc.c | 14 +- .../stm32h5/nucleo-h563zi/src/stm32_bringup.c | 8 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_can.c | 2 +- .../nucleo-h563zi/src/stm32_clockconfig.c | 4 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_dts.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c | 4 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_usb.c | 4 +- .../stm32h7/linum-stm32h753bi/include/board.h | 10 +- .../linum-stm32h753bi/src/linum-stm32h753bi.h | 12 +- .../linum-stm32h753bi/src/stm32_bringup.c | 12 +- .../stm32h7/linum-stm32h753bi/src/stm32_lcd.c | 2 +- .../linum-stm32h753bi/src/stm32_mfrc522.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_pwm.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_spi.c | 8 +- .../linum-stm32h753bi/src/stm32_touchscreen.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_usb.c | 4 +- .../arm/stm32h7/nucleo-h723zg/include/board.h | 6 +- .../stm32h7/nucleo-h723zg/src/nucleo-h723zg.h | 14 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_adc.c | 28 +- .../stm32h7/nucleo-h723zg/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h723zg/src/stm32_bringup.c | 8 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_spi.c | 30 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_usb.c | 2 +- .../arm/stm32h7/nucleo-h743zi/include/board.h | 6 +- .../stm32h7/nucleo-h743zi/src/nucleo-h743zi.h | 16 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_adc.c | 28 +- .../stm32h7/nucleo-h743zi/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h743zi/src/stm32_bringup.c | 38 +- .../nucleo-h743zi/src/stm32_lsm303agr.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_mmcsd.c | 2 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c | 4 +- .../stm32h7/nucleo-h743zi/src/stm32_romfs.h | 6 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_spi.c | 30 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_usb.c | 4 +- .../stm32h7/nucleo-h743zi2/include/board.h | 6 +- .../nucleo-h743zi2/src/nucleo-h743zi2.h | 14 +- .../stm32h7/nucleo-h743zi2/src/stm32_adc.c | 20 +- .../stm32h7/nucleo-h743zi2/src/stm32_boot.c | 2 +- .../nucleo-h743zi2/src/stm32_bringup.c | 14 +- .../stm32h7/nucleo-h743zi2/src/stm32_pwm.c | 4 +- .../stm32h7/nucleo-h743zi2/src/stm32_usb.c | 4 +- .../arm/stm32h7/nucleo-h745zi/include/board.h | 8 +- .../stm32h7/nucleo-h745zi/src/nucleo-h745zi.h | 16 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_adc.c | 20 +- .../nucleo-h745zi/src/stm32_autoleds.c | 2 +- .../stm32h7/nucleo-h745zi/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h745zi/src/stm32_bringup.c | 20 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_usb.c | 4 +- .../arm/stm32h7/nucleo-h753zi/include/board.h | 6 +- .../stm32h7/nucleo-h753zi/src/nucleo-h753zi.h | 14 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_adc.c | 20 +- .../stm32h7/nucleo-h753zi/src/stm32_boot.c | 2 +- .../stm32h7/nucleo-h753zi/src/stm32_bringup.c | 14 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_usb.c | 4 +- boards/arm/stm32h7/openh743i/include/board.h | 6 +- boards/arm/stm32h7/openh743i/src/openh743i.h | 10 +- boards/arm/stm32h7/openh743i/src/stm32_boot.c | 2 +- .../arm/stm32h7/openh743i/src/stm32_bringup.c | 4 +- .../arm/stm32h7/openh743i/src/stm32_sdmmc.c | 4 +- boards/arm/stm32h7/openh743i/src/stm32_usb.c | 6 +- .../arm/stm32h7/portenta-h7/include/board.h | 8 +- .../arm/stm32h7/portenta-h7/src/portenta-h7.h | 6 +- .../stm32h7/portenta-h7/src/stm32_autoleds.c | 2 +- .../stm32h7/portenta-h7/src/stm32_bringup.c | 8 +- .../stm32h7/stm32h745i-disco/include/board.h | 8 +- .../stm32h7/stm32h745i-disco/src/stm32_boot.c | 2 +- .../stm32h745i-disco/src/stm32_bringup.c | 8 +- .../stm32h745i-disco/src/stm32_ft5x06.c | 4 +- .../stm32h7/stm32h745i-disco/src/stm32_lcd.c | 2 +- .../stm32h7/stm32h745i-disco/src/stm32_usb.c | 4 +- .../stm32h745i-disco/src/stm32h745i_disco.h | 12 +- .../stm32h7/stm32h747i-disco/include/board.h | 6 +- .../stm32h7/stm32h747i-disco/src/stm32_adc.c | 20 +- .../stm32h7/stm32h747i-disco/src/stm32_boot.c | 4 +- .../stm32h747i-disco/src/stm32_bringup.c | 8 +- .../stm32h7/stm32h747i-disco/src/stm32_spi.c | 28 +- .../stm32h7/stm32h747i-disco/src/stm32_usb.c | 6 +- .../stm32h747i-disco/src/stm32h747i-disco.h | 10 +- .../arm/stm32h7/stm32h750b-dk/include/board.h | 8 +- .../stm32h7/stm32h750b-dk/src/stm32_boot.c | 2 +- .../stm32h7/stm32h750b-dk/src/stm32_bringup.c | 8 +- .../stm32h7/stm32h750b-dk/src/stm32_ft5x06.c | 4 +- .../arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c | 2 +- .../arm/stm32h7/stm32h750b-dk/src/stm32_usb.c | 4 +- .../stm32h7/stm32h750b-dk/src/stm32h750b-dk.h | 12 +- .../stm32h7/weact-stm32h743/include/board.h | 6 +- .../stm32h7/weact-stm32h743/src/stm32_boot.c | 6 +- .../stm32h7/weact-stm32h743/src/stm32_spi.c | 4 +- .../stm32h7/weact-stm32h743/src/stm32_usb.c | 2 +- .../weact-stm32h743/src/weact-stm32h743.h | 12 +- .../stm32h7/weact-stm32h750/include/board.h | 6 +- .../stm32h7/weact-stm32h750/src/stm32_boot.c | 6 +- .../stm32h7/weact-stm32h750/src/stm32_spi.c | 4 +- .../stm32h7/weact-stm32h750/src/stm32_usb.c | 2 +- .../weact-stm32h750/src/weact-stm32h750.h | 12 +- .../include/b-l475e-iot01a_clock.h | 310 ++--- .../stm32l4/b-l475e-iot01a/include/board.h | 6 +- .../b-l475e-iot01a/src/b-l475e-iot01a.h | 16 +- .../stm32l4/b-l475e-iot01a/src/stm32_boot.c | 2 +- .../stm32l4/b-l475e-iot01a/src/stm32_spi.c | 34 +- .../stm32l4/b-l475e-iot01a/src/stm32_timer.c | 22 +- .../arm/stm32l4/nucleo-l432kc/include/board.h | 10 +- .../nucleo-l432kc/include/nucleo-l432kc.h | 296 ++--- .../stm32l4/nucleo-l432kc/src/nucleo-l432kc.h | 12 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_adc.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_at45db.c | 2 +- .../stm32l4/nucleo-l432kc/src/stm32_boot.c | 6 +- .../stm32l4/nucleo-l432kc/src/stm32_bringup.c | 26 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_dac.c | 4 +- .../stm32l4/nucleo-l432kc/src/stm32_dac7571.c | 2 +- .../nucleo-l432kc/src/stm32_dac_wgen.c | 14 +- .../stm32l4/nucleo-l432kc/src/stm32_ina219.c | 2 +- .../stm32l4/nucleo-l432kc/src/stm32_ina226.c | 2 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c | 12 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 28 +- .../arm/stm32l4/nucleo-l452re/include/board.h | 6 +- .../nucleo-l452re/include/nucleo-l452re.h | 312 ++--- .../stm32l4/nucleo-l452re/src/nucleo-l452re.h | 26 +- .../arm/stm32l4/nucleo-l452re/src/stm32_adc.c | 4 +- .../stm32l4/nucleo-l452re/src/stm32_bringup.c | 2 +- .../arm/stm32l4/nucleo-l452re/src/stm32_dac.c | 2 +- .../arm/stm32l4/nucleo-l452re/src/stm32_spi.c | 24 +- .../arm/stm32l4/nucleo-l476rg/include/board.h | 6 +- .../nucleo-l476rg/include/nucleo-l476rg.h | 316 ++--- .../stm32l4/nucleo-l476rg/src/nucleo-l476rg.h | 14 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_adc.c | 4 +- .../nucleo-l476rg/src/stm32_ajoystick.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_bmp280.h | 6 +- .../stm32l4/nucleo-l476rg/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_bringup.c | 12 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_can.c | 6 +- .../nucleo-l476rg/src/stm32_lsm303agr.c | 6 +- .../stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c | 6 +- .../stm32l4/nucleo-l476rg/src/stm32_mpu9250.h | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c | 22 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 26 +- .../nucleo-l476rg/src/stm32_spimmcsd.c | 2 +- .../arm/stm32l4/nucleo-l496zg/include/board.h | 306 ++--- .../stm32l4/nucleo-l496zg/src/nucleo-144.h | 14 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 34 +- .../stm32l4/nucleo-l496zg/src/stm32_boot.c | 2 +- .../stm32l4/nucleo-l496zg/src/stm32_bringup.c | 26 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_dac.c | 8 +- .../stm32l4/nucleo-l496zg/src/stm32_dfsdm.c | 20 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_spi.c | 30 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 4 +- .../stm32l4/steval-stlcs01v1/include/board.h | 146 +-- .../steval-stlcs01v1/src/steval-stlcs01v1.h | 8 +- .../stm32l4/steval-stlcs01v1/src/stm32_boot.c | 2 +- .../stm32l4/steval-stlcs01v1/src/stm32_usb.c | 6 +- .../arm/stm32l4/stm32l476-mdk/include/board.h | 6 +- .../include/stm32l476-mdk-clocking.h | 196 +-- .../stm32l476-mdk/src/stm32_clockconfig.c | 84 +- .../stm32l4/stm32l476-mdk/src/stm32l476-mdk.h | 6 +- .../stm32l4/stm32l476vg-disco/include/board.h | 6 +- .../stm32l476vg-disco/include/boardctl.h | 6 +- .../include/stm32l476vg-disco-clocking.h | 274 ++-- .../stm32l476vg-disco/src/stm32_boot.c | 2 +- .../stm32l476vg-disco/src/stm32_clockconfig.c | 84 +- .../stm32l4/stm32l476vg-disco/src/stm32_usb.c | 8 +- .../stm32l476vg-disco/src/stm32l476vg-disco.h | 10 +- .../stm32l4/stm32l4r9ai-disco/include/board.h | 6 +- .../stm32l4r9ai-disco/include/boardctl.h | 6 +- .../include/stm32l4r9ai-disco-clocking.h | 292 ++--- .../stm32l4/stm32l4r9ai-disco/src/stm32_adc.c | 4 +- .../stm32l4r9ai-disco/src/stm32_boot.c | 4 +- .../stm32l4r9ai-disco/src/stm32_bringup.c | 10 +- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 84 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_dac.c | 2 +- .../stm32l4r9ai-disco/src/stm32_dfsdm.c | 20 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_spi.c | 28 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_usb.c | 8 +- .../stm32l4r9ai-disco/src/stm32l4r9ai-disco.h | 14 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 138 +- .../stm32l5/nucleo-l552ze/src/nucleo-l552ze.h | 6 +- .../stm32l5/nucleo-l552ze/src/stm32_boot.c | 2 +- .../arm/stm32l5/stm32l562e-dk/include/board.h | 44 +- .../stm32l562e-dk/src/stm32_clockconfig.c | 4 +- .../stm32l5/stm32l562e-dk/src/stm32l562e-dk.h | 6 +- .../stm32n6/nucleo-n657x0-q/include/board.h | 6 +- .../nucleo-n657x0-q/src/nucleo-n657x0-q.h | 6 +- .../stm32u5/b-u585i-iot02a/include/board.h | 6 +- .../b-u585i-iot02a/src/b-u585i-iot02a.h | 6 +- .../b-u585i-iot02a/src/stm32_clockconfig.c | 2 +- .../stm32u5/b-u585i-iot02a/src/stm32_spi.c | 18 +- .../stm32u5/nucleo-u5a5zj-q/include/board.h | 6 +- .../nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h | 6 +- .../nucleo-u5a5zj-q/src/stm32_bringup.c | 2 +- .../nucleo-u5a5zj-q/src/stm32_clockconfig.c | 2 +- .../stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c | 18 +- .../arm/stm32wb/flipperzero/include/board.h | 14 +- .../include/flipperzero-clocking.h | 128 +- .../arm/stm32wb/flipperzero/src/flipperzero.h | 6 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 4 +- .../flipperzero/src/stm32_lcd_st7565.c | 24 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 6 +- .../arm/stm32wb/nucleo-wb55rg/include/board.h | 6 +- .../nucleo-wb55rg/include/nucleo-wb55rg.h | 128 +- .../stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h | 6 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 4 +- .../stm32wl5/nucleo-wl55jc/include/board.h | 68 +- .../nucleo-wl55jc/src/nucleo-wl55jc.h | 6 +- .../stm32wl5/nucleo-wl55jc/src/stm32_boot.c | 2 +- .../stm32wl5/nucleo-wl55jc/src/stm32_flash.c | 2 +- .../stm32wl5/nucleo-wl55jc/src/stm32_spi.c | 12 +- .../nucleo-wl55jc/src/stm32wl5_ssd1680.h | 6 +- 940 files changed, 30702 insertions(+), 30651 deletions(-) diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 5b2eb34fc1fc6..2d17d6538fc5d 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -181,8 +181,8 @@ * Parts STM32F74xxG have 1024Kb of FLASH * Parts STM32F74xxI have 2048Kb of FLASH * - * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x - * or overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * The correct FLASH size will be set CONFIG_STM32_FLASH_CONFIG_x + * or overridden with CONFIG_STM32_FLASH_OVERRIDE_x * */ #if defined(CONFIG_ARCH_CHIP_STM32F722RC) || \ @@ -264,44 +264,44 @@ /* Size SRAM */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) +# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) +# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) +# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #else # error STM32 F7 chip Family not identified @@ -309,34 +309,34 @@ /* Common to all Advanced (vs Foundation) Family members */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_NSPDIFRX 0 /* Not supported */ -# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32F7_NI2C 3 /* I2C1-3 */ +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) +# define STM32_NSPDIFRX 0 /* Not supported */ +# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NI2C 3 /* I2C1-3 */ #else -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NI2C 4 /* I2C1-4 */ +# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32_NI2C 4 /* I2C1-4 */ #endif /* Common to all Family members */ -# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ -# define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ -# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32F7_NCRC 1 /* CRC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NUART 4 /* UART 4-5 and 7-8 */ +# define STM32_NUSART 4 /* USART1-3 and 6 */ +# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBOTGHS 1 /* USB OTG HS */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ /* TBD FPU Configuration */ @@ -350,83 +350,83 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32F7_HAVE_FMC) -# define STM32F7_NFMC 1 /* Have FMC memory controller */ +#if defined(CONFIG_STM32_HAVE_FMC) +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32F7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif -#if defined(CONFIG_STM32F7_HAVE_ETHRNET) -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHRNET) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32F7_HAVE_RNG) -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +#if defined(CONFIG_STM32_HAVE_RNG) +# define STM32_NRNG 1 /* Random number generator (RNG) */ #else -# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif -#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI5) -# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI4) -# define STM32F7_NSPI 4 /* SPI1-4 V series */ +#if defined(CONFIG_STM32_HAVE_SPI5) && defined(CONFIG_STM32_HAVE_SPI6) +# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +#elif defined(CONFIG_STM32_HAVE_SPI5) +# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +#elif defined(CONFIG_STM32_HAVE_SPI4) +# define STM32_NSPI 4 /* SPI1-4 V series */ #else -# define STM32F7_NSPI 3 /* SPI1-3 R series */ +# define STM32_NSPI 3 /* SPI1-3 R series */ #endif -#if defined(CONFIG_STM32F7_HAVE_SDMMC2) -# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +#if defined(CONFIG_STM32_HAVE_SDMMC2) +# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else -# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +# define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif -#if defined(CONFIG_STM32F7_HAVE_CAN3) -# define STM32F7_NCAN 3 /* CAN1-3 */ -#elif defined(CONFIG_STM32F7_HAVE_CAN2) -# define STM32F7_NCAN 2 /* CAN1-2 */ +#if defined(CONFIG_STM32_HAVE_CAN3) +# define STM32_NCAN 3 /* CAN1-3 */ +#elif defined(CONFIG_STM32_HAVE_CAN2) +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32F7_NCAN 1 /* CAN1 only */ +# define STM32_NCAN 1 /* CAN1 only */ #endif -#if defined(CONFIG_STM32F7_HAVE_DCMI) -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +#if defined(CONFIG_STM32_HAVE_DCMI) +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else -# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif -#if defined(CONFIG_STM32F7_HAVE_DSIHOST) -# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +#if defined(CONFIG_STM32_HAVE_DSIHOST) +# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else -# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +# define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif -#if defined (CONFIG_STM32F7_HAVE_LTDC) -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +#if defined (CONFIG_STM32_HAVE_LTDC) +# define STM32_NLCDTFT 1 /* One LCD-TFT */ #else -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +# define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif -#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +#if defined(CONFIG_STM32_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ +# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else -# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif -#if defined(CONFIG_STM32F7_HAVE_JPEG) -#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#if defined(CONFIG_STM32_HAVE_JPEG) +#define STM32_NJPEG 1 /* One JPEG Converter */ #else -#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#define STM32_NJPEG 0 /* No JPEG Converter */ #endif -#if defined(CONFIG_STM32F7_HAVE_CRYP) -#define STM32F7_NCRYP 1 /* One CRYP engine */ +#if defined(CONFIG_STM32_HAVE_CRYP) +#define STM32_NCRYP 1 /* One CRYP engine */ #else -#define STM32F7_NCRYP 0 /* No CRYP engine */ +#define STM32_NCRYP 0 /* No CRYP engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_HASH) -#define STM32F7_NHASH 1 /* One HASH engine */ +#if defined(CONFIG_STM32_HAVE_HASH) +#define STM32_NHASH 1 /* One HASH engine */ #else -#define STM32F7_NHASH 0 /* No HASH engine */ +#define STM32_NHASH 0 /* No HASH engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_DFSDM) -#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#if defined(CONFIG_STM32_HAVE_DFSDM) +#define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else -#define STM32F7_NDFSDM 0 /* No Digital filters */ +#define STM32_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 3c786310d6806..c755977dfdca5 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -69,11 +69,11 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include #else # error "Unsupported STM32 F7 chip" diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index 3db5fd6905a80..da0f658d7892b 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -33,66 +33,66 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ #else # error "Unsupported STM32H5 chip" #endif -#define STM32H5_NFSMC (1) /* Have FSMC memory controller */ -#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ -#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ -#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ -#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ -#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */ -#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ -#define STM32H5_NRNG (1) /* Random number generator (RNG) */ - -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */ -# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NUART (2) /* UART 4-5 */ -# define STM32H5_NUSART (4) /* USART 1-3, 6*/ +#define STM32_NFSMC (1) /* Have FSMC memory controller */ +#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ +#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ +#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ +#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ +#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */ +#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ +#define STM32_NRNG (1) /* Random number generator (RNG) */ + +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ +# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NUART (2) /* UART 4-5 */ +# define STM32_NUSART (4) /* USART 1-3, 6*/ #endif -#define STM32H5_NLPUART (1) /* LPUART 1 */ -#define STM32H5_QSPI (0) /* No QuadSPI1 */ -#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/ +#define STM32_NLPUART (1) /* LPUART 1 */ +#define STM32_QSPI (0) /* No QuadSPI1 */ +#define STM32_OCTOSPI (1) /* OCTOSPI1*/ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSPI (6) /* SPI1-SPI6 */ -# define STM32H5_NI2C (4) /* I2C1-4 */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSPI (3) /* SPI1-SPI3 */ -# define STM32H5_NI2C (3) /* I2C1-3 */ +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NSPI (6) /* SPI1-SPI6 */ +# define STM32_NI2C (4) /* I2C1-4 */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NSPI (3) /* SPI1-SPI3 */ +# define STM32_NI2C (3) /* I2C1-3 */ #endif -#define STM32H5_NSWPMI (0) /* No SWPMI1 */ -#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */ -#define STM32H5_NUSBFS (1) /* No USB FS */ -#define STM32H5_NCAN (2) /* CAN1 */ -#define STM32H5_NSAI (2) /* SAI1-2 */ +#define STM32_NSWPMI (0) /* No SWPMI1 */ +#define STM32_NUSBOTGFS (0) /* USB OTG FS */ +#define STM32_NUSBFS (1) /* No USB FS */ +#define STM32_NCAN (2) /* CAN1 */ +#define STM32_NSAI (2) /* SAI1-2 */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSDMMC (2) /* SDMMC interface */ -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSDMMC (1) /* SDMMC interface */ +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) +# define STM32_NSDMMC (2) /* SDMMC interface */ +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) +# define STM32_NSDMMC (1) /* SDMMC interface */ #endif -#define STM32H5_NDMA (2) /* DMA1-2 */ -#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ -#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */ -#define STM32H5_NDAC (1) /* 12-bit DAC1 */ -#define STM32H5_NCRC (1) /* CRC */ -#define STM32H5_NCOMP (0) /* Comparators */ -#define STM32H5_NOPAMP (0) /* Operational Amplifiers */ +#define STM32_NDMA (2) /* DMA1-2 */ +#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ +#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */ +#define STM32_NDAC (1) /* 12-bit DAC1 */ +#define STM32_NCRC (1) /* CRC */ +#define STM32_NCOMP (0) /* Comparators */ +#define STM32_NOPAMP (0) /* Operational Amplifiers */ /* NVIC priority levels *****************************************************/ @@ -103,10 +103,10 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -#if defined(CONFIG_STM32H5_HAVE_ETHERNET) -# define STM32H5_NETHERNET 1 /* Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHERNET) +# define STM32_NETHERNET 1 /* Ethernet MAC */ #else -# define STM32H5_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ #endif #endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */ diff --git a/arch/arm/include/stm32h5/irq.h b/arch/arm/include/stm32h5/irq.h index 945ef81a9f2a2..68c53b2704ec2 100644 --- a/arch/arm/include/stm32h5/irq.h +++ b/arch/arm/include/stm32h5/irq.h @@ -65,8 +65,8 @@ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index 6c3746e1fcc60..b6582c3ec075f 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -119,7 +119,7 @@ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */ #endif @@ -132,12 +132,12 @@ # define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ # define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ # define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */ # define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */ #endif # define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */ # define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */ # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */ @@ -151,7 +151,7 @@ # define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ # define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ # define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */ # define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */ # define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */ @@ -161,14 +161,14 @@ # define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */ # define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ # define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */ # define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */ #endif # define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ # define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ # define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */ # define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */ #endif @@ -180,13 +180,13 @@ # define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */ # define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */ # define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */ # define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */ #endif # define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ # define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */ # define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */ # define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */ @@ -194,14 +194,14 @@ # define STM32_IRQ_LPTIM5 (STM32_IRQ_FIRST + 129) /* 129: LPTIM5 global interrupt */ # define STM32_IRQ_LPTIM6 (STM32_IRQ_FIRST + 130) /* 130: LPTIM6 global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 131) /* 131: I3C2_EV global interrupt */ # define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define STM32_IRQ_NEXTINTS 131 -#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#elif defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define STM32_IRQ_NEXTINTS 133 #endif diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b97a8659e6c32..08492c3184b25 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -51,8 +51,8 @@ * * Parts STM32H7xxxI have 2048Kb of FLASH * - * The correct FLASH size will be set CONFIG_STM32H7_FLASH_CONFIG_x or - * overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x + * The correct FLASH size will be set CONFIG_STM32_FLASH_CONFIG_x or + * overridden with CONFIG_STM32_FLASH_OVERRIDE_x */ #if defined (CONFIG_ARCH_CHIP_STM32H723VG) || \ @@ -91,158 +91,158 @@ /* Size SRAM */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || defined(CONFIG_STM32_STM32H7X3XX) || defined(CONFIG_STM32_STM32H7X5XX) /* Memory */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX -# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX +# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# if defined(CONFIG_STM32_IO_CONFIG_A) +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ +# elif defined(CONFIG_STM32_IO_CONFIG_B) +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32_IO_CONFIG_I) +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ +# elif defined(CONFIG_STM32_IO_CONFIG_V) +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# elif defined(CONFIG_STM32_IO_CONFIG_X) +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32_IO_CONFIG_Z) +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else -# error CONFIG_STM32H7_IO_CONFIG_x Not Set +# error CONFIG_STM32_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ +#elif defined(CONFIG_STM32_STM32H7B3XX) /* Memory */ -# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_L) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# if defined(CONFIG_STM32_IO_CONFIG_A) +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ +# elif defined(CONFIG_STM32_IO_CONFIG_B) +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32_IO_CONFIG_I) +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ +# elif defined(CONFIG_STM32_IO_CONFIG_L) +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32_IO_CONFIG_V) +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# elif defined(CONFIG_STM32_IO_CONFIG_X) +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# elif defined(CONFIG_STM32_IO_CONFIG_Z) +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else -# error CONFIG_STM32H7_IO_CONFIG_x Not Set +# error CONFIG_STM32_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ +#elif defined(CONFIG_STM32_STM32H7X7XX) /* Memory */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #else # error STM32 H7 chip Family not identified #endif @@ -259,16 +259,16 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32H7_HAVE_ETHERNET) -# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */ +#if defined(CONFIG_STM32_HAVE_ETHERNET) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32H7_HAVE_FMC) -# define STM32H7_NFMC 1 /* Have FMC memory controller */ +#if defined(CONFIG_STM32_HAVE_FMC) +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32H7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h index 427d6b8c1f25d..bdbdd2e214731 100644 --- a/arch/arm/include/stm32h7/irq.h +++ b/arch/arm/include/stm32h7/irq.h @@ -69,19 +69,19 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X5XX) -# if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#elif defined(CONFIG_STM32_STM32H7X5XX) +# if CONFIG_ARCH_CHIP_STM32_CORTEXM7 # include # else # include # endif -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index febd84d6fac0e..f8d06093bad42 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -61,266 +61,266 @@ * Parts STM32L4x6xE have 512Kb of FLASH * Parts STM32L4x6xG have 1024Kb of FLASH * - * The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_CONFIG_* + * The correct FLASH size must be set with a CONFIG_STM32_FLASH_CONFIG_* * selection. */ -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L496XX) +# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L475XX) || defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) +# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L432XX) || defined(CONFIG_STM32_STM32L433XX) +# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +#elif defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) +# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L4 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 0 /* No QuadSPI1 */ -# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 0 /* No SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4XR */ -#if defined(CONFIG_STM32L4_STM32L4X5) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 3 /* I2C1-3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#if defined(CONFIG_STM32_STM32L4X5) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4X5 */ -#if defined(CONFIG_STM32L4_STM32L4X6) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NI2C 4 /* I2C1-4 */ +#if defined(CONFIG_STM32_STM32L4X6) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NI2C 4 /* I2C1-4 */ #else -# define STM32L4_NI2C 3 /* I2C1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ #endif -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NCAN 2 /* CAN1-2 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32L4_NCAN 1 /* CAN1 */ +# define STM32_NCAN 1 /* CAN1 */ #endif -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +#if defined(CONFIG_STM32_STM32L496XX) +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ #else -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ #endif -# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L4X6 */ -#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 1 /* UART 4 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -#if defined(CONFIG_STM32L4_STM32L451XX) -# define STM32L4_NUSBFS 0 /* No USB FS */ +#if defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 1 /* UART 4 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +#if defined(CONFIG_STM32_STM32L451XX) +# define STM32_NUSBFS 0 /* No USB FS */ #else -# define STM32L4_NUSBFS 1 /* USB FS */ +# define STM32_NUSBFS 1 /* USB FS */ #endif -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -#if defined(CONFIG_STM32L4_HAVE_SDMMC1) -# define STM32L4_NSDMMC 1 /* SDMMC interface */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +#if defined(CONFIG_STM32_HAVE_SDMMC1) +# define STM32_NSDMMC 1 /* SDMMC interface */ #else -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ #endif -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ -# define STM32L4_NDAC 1 /* 12-bit DAC1 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L451XX */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ +# define STM32_NDAC 1 /* 12-bit DAC1 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L451XX */ -#if defined(CONFIG_STM32L4_STM32L432XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 2 /* USART 1-2 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 2 /* SPI1, SPI3 */ -# define STM32L4_NI2C 2 /* I2C1, I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L432XX */ +#if defined(CONFIG_STM32_STM32L432XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 2 /* SPI1, SPI3 */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L432XX */ -#if defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L433XX */ +#if defined(CONFIG_STM32_STM32L433XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L433XX */ -#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 0 /* No SWPMI */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 0 /* No CAN */ -# define STM32L4_NSAI 0 /* No SAI */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */ -# define STM32L4_NDAC 0 /* No DAC */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */ +#if defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 0 /* No SWPMI */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSAI 0 /* No SAI */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L412XX || CONFIG_STM32_STM32L422XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index a17c156715713..11c1a9a9d1f6b 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -44,38 +44,38 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include #else # error "Unsupported STM32 L4 chip" diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 1b3b5b27945ff..e0d1c6bf7d1fa 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -52,99 +52,99 @@ * */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - /* Reserved 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ - /* Reserved 42-48 */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ - /* Reserved 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ - /* Reserved 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ - /* Reserved 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ - /* Reserved 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ - -#if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_IRQ_NEXTINTS 85 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + /* Reserved 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ + /* Reserved 42-48 */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ + /* Reserved 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ + /* Reserved 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ + /* Reserved 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ + /* Reserved 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ + +#if defined(CONFIG_STM32_STM32L4X3) +# define STM32_IRQ_NEXTINTS 85 #else # error "Unsupported STM32L4 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h index 3c0c8f49842a4..e21faaae23000 100644 --- a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h @@ -48,99 +48,99 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */ -#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ - -#define STM32L4_IRQ_NEXTINTS 82 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ + +#define STM32_IRQ_NEXTINTS 82 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h index 039cc81d92a90..7b3eca2a84801 100644 --- a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h @@ -48,117 +48,117 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ /* STM32L496xx/4A6xx only: */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ -#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ -#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ -#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ -#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ - -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_IRQ_NEXTINTS 82 -#elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_IRQ_NEXTINTS 91 +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ + +#if defined(CONFIG_STM32_STM32L476XX) || defined(CONFIG_STM32_STM32L486XX) +# define STM32_IRQ_NEXTINTS 82 +#elif defined(CONFIG_STM32_STM32L496XX) +# define STM32_IRQ_NEXTINTS 91 #else # error "Unsupported STM32L4 chip" #endif /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h index 803bf8dc01240..ec9f7db1f952b 100644 --- a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h @@ -48,109 +48,109 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ - /* Reserved 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ - /* Reserved 86-89: CAN2 */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ -#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ -#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ -#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ -#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ - -#define STM32L4_IRQ_NEXTINTS 95 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ + /* Reserved 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ + /* Reserved 86-89: CAN2 */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ +#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ +#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 95 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l5/chip.h b/arch/arm/include/stm32l5/chip.h index 25fae6e32e0c9..0986ac7a15068 100644 --- a/arch/arm/include/stm32l5/chip.h +++ b/arch/arm/include/stm32l5/chip.h @@ -33,43 +33,43 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L5_NRNG 1 /* Random number generator (RNG) */ -# define STM32L5_NUART 2 /* UART 4-5 */ -# define STM32L5_NUSART 3 /* USART 1-3 */ -# define STM32L5_NLPUART 1 /* LPUART 1 */ -# define STM32L5_QSPI 0 /* No QuadSPI1 */ -# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L5_NSPI 3 /* SPI1-3 */ -# define STM32L5_NI2C 4 /* I2C1-4 */ -# define STM32L5_NSWPMI 0 /* No SWPMI1 */ -# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L5_NUSBFS 0 /* No USB FS */ -# define STM32L5_NCAN 1 /* CAN1 */ -# define STM32L5_NSAI 2 /* SAI1-2 */ -# define STM32L5_NSDMMC 1 /* SDMMC interface */ -# define STM32L5_NDMA 2 /* DMA1-2 */ -# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L5_NCRC 1 /* CRC */ -# define STM32L5_NCOMP 2 /* Comparators */ -# define STM32L5_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L5_STM32L562XX */ +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ +#endif /* CONFIG_STM32_STM32L562XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l5/irq.h b/arch/arm/include/stm32l5/irq.h index 9a35b3bdaf3aa..941262961520d 100644 --- a/arch/arm/include/stm32l5/irq.h +++ b/arch/arm/include/stm32l5/irq.h @@ -33,7 +33,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index a8e283dcc9543..35e326d15b003 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -50,124 +50,124 @@ * */ -#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ -#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ -#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ -#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ -#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ -#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ -#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ -#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ -#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ -#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ -#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ -#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ -#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ -#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ -#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ -#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ -#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ -#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ -#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ -#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ -#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ -#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ -#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ -#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ -#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ -#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ -#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ -#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ -#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ -#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ -#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ -#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ -#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ -#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ -#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ -#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ -#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ -#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ -#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ -#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ -#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ -#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ -#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ -#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ -#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ -#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ -#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ -#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ -#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ -#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ -#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ -#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ -#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ -#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ -#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */ -#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */ -#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */ -#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ - /* 77: Reserved */ -#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ - /* 79: Reserved */ -#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ -#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ -#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ -#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ -#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ -#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */ -#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */ -#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */ -#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */ -#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */ -#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */ -#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ -#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ -#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ -#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ -#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ -#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ -#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD_PVM (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +#define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +#define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +#define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +#define STM32_IRQ_TAMP_S (STM32_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +#define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +#define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +#define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +#define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +#define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +#define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +#define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +#define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +#define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +#define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +#define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +#define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +#define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +#define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ +#define STM32_IRQ_DMAMUX1_OVR_S (STM32_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ +#define STM32_IRQ_ADC1_2 (STM32_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ +#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ +#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ +#define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 73) /* 73: USB global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ + /* 77: Reserved */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ + /* 79: Reserved */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ +#define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ +#define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 92) /* 92: TSC global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 93) /* 93: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 94) /* 94: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 95) /* 95: FPU global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 96) /* 96: HASH global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 97) /* 97: PKA global interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ +#define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ +#define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ +#define STM32_IRQ_DFSDM1_FLT0 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT1 (STM32_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT2 (STM32_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT3 (STM32_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ +#define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ +#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ +#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_IRQ_NEXTINTS 109 +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_IRQ_NEXTINTS 109 #else # error "Unsupported STM32L5 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) #endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */ diff --git a/arch/arm/include/stm32l5/stm32l5_irq.h b/arch/arm/include/stm32l5/stm32l5_irq.h index 8ffbc2ac9a97e..bca9065244e23 100644 --- a/arch/arm/include/stm32l5/stm32l5_irq.h +++ b/arch/arm/include/stm32l5/stm32l5_irq.h @@ -25,8 +25,8 @@ * (e.g. stm32l562xx_irq.h) */ -#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H /**************************************************************************** * Included Files @@ -46,26 +46,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). * These definitions are chip-specific */ -#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Public Types @@ -94,4 +94,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L5_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32n6/chip.h b/arch/arm/include/stm32n6/chip.h index 72f643ba3b687..9c50b19c7c74b 100644 --- a/arch/arm/include/stm32n6/chip.h +++ b/arch/arm/include/stm32n6/chip.h @@ -52,10 +52,10 @@ * Each bank requires its RCC MEMENR clock enable bit to be set. */ -#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ +#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ -#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ -#define STM32N6_NUSART (1) /* USART1 */ +#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ +#define STM32_NUSART (1) /* USART1 */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index 887ca72d38a28..00799d00f38a6 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -33,14 +33,14 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */ @@ -49,7 +49,7 @@ # error "Unsupported STM32U5 chip" #endif -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -78,9 +78,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32U5_STM32U585XX */ +#endif /* CONFIG_STM32_STM32U585XX */ -#if defined(CONFIG_STM32U5_STM32U5A5ZJT) +#if defined(CONFIG_STM32_STM32U5A5ZJT) # define STM32_NUSBOTGHS 1 /* USB OTG HS */ #endif diff --git a/arch/arm/include/stm32u5/irq.h b/arch/arm/include/stm32u5/irq.h index 77c5c600bde0f..1dd4a1abe7c24 100644 --- a/arch/arm/include/stm32u5/irq.h +++ b/arch/arm/include/stm32u5/irq.h @@ -33,10 +33,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index f1042c3d4a91d..bb629ca1eeb0e 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -130,11 +130,11 @@ #define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ #define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ #define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */ #else # error "Unsupported STM32U5 chip" @@ -191,10 +191,10 @@ #define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 123) /* 123: CORDIC interrupt */ #define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_IRQ_NEXTINTS 125 #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 56d7912fe51fd..8d933ab8957fa 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -33,83 +33,83 @@ * Pre-processor Prototypes ****************************************************************************/ -#define STM32WB_NFSMC 0 /* No FSMC */ -#define STM32WB_NBTIM 0 /* No basic timers */ -#define STM32WB_NATIM 1 /* One advanced timers TIM1 */ -#define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ -#define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -#define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */ - -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ +#define STM32_NFSMC 0 /* No FSMC */ +#define STM32_NBTIM 0 /* No basic timers */ +#define STM32_NATIM 1 /* One advanced timers TIM1 */ +#define STM32_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ +#define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +#define STM32_NGTIMNDMA 0 /* No general timers without DMA */ + +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else -# define STM32WB_NGTIM16 0 /* No 16-bit general timers */ +# define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */ -# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */ -# define STM32WB_NI2C 2 /* I2C1, I2C3 */ -# define STM32WB_NUSBOTG 1 /* USB 2.0 FS */ -# define STM32WB_NCMP 2 /* Two Comparators */ -# if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NSPI 3 /* SPI1-2, QSPI */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ +# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NUSBOTG 1 /* USB 2.0 FS */ +# define STM32_NCMP 2 /* Two Comparators */ +# if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +# define STM32_NSPI 3 /* SPI1-2, QSPI */ # else -# define STM32WB_NSPI 2 /* SPI1, QSPI */ +# define STM32_NSPI 2 /* SPI1, QSPI */ # endif #else -# define STM32WB_NDMA 1 /* DMA1 with 7 channels */ -# define STM32WB_NI2S 0 /* No SAI */ -# define STM32WB_NI2C 1 /* I2C1 */ -# define STM32WB_NUSBOTG 0 /* No USB */ -# define STM32WB_NCMP 0 /* No Comparators */ -# define STM32WB_NSPI 1 /* SPI1 */ +# define STM32_NDMA 1 /* DMA1 with 7 channels */ +# define STM32_NI2S 0 /* No SAI */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NUSBOTG 0 /* No USB */ +# define STM32_NCMP 0 /* No Comparators */ +# define STM32_NSPI 1 /* SPI1 */ #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ - || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLPUART 1 /* LPUART1 */ +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) \ + || defined(CONFIG_STM32_STM32WB55) +# define STM32_NLPUART 1 /* LPUART1 */ #else -# define STM32WB_NLPUART 0 /* No LPUART */ +# define STM32_NLPUART 0 /* No LPUART */ #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NCAPSENSE 18 /* Capacitive sensing channels */ +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +# define STM32_NCAPSENSE 18 /* Capacitive sensing channels */ #else -# define STM32WB_NCAPSENSE 0 /* No Capacitive sensing */ +# define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLCD 1 /* One LCD controller with up to 8x40 +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 * 55Rx: 4x28 * 55Vx: 4x44, 8x40 */ #else -# define STM32WB_NLCD 0 /* No LCD */ +# define STM32_NLCD 0 /* No LCD */ #endif -#define STM32WB_NUSART 1 /* USART1 */ -#define STM32WB_NCAN 0 /* No CAN */ -#define STM32WB_NSDIO 0 /* No SDIO interface */ -#define STM32WB_NADC 1 /* ADC1, up to 19-channels */ -#define STM32WB_NDAC 0 /* No DAC */ -#define STM32WB_NCRC 1 /* CRC */ -#define STM32WB_NETHERNET 0 /* No ethernet */ -#define STM32WB_NRNG 1 /* Random number generator (RNG) */ -#define STM32WB_NDCMI 0 /* No digital camera interface (DCMI) */ - -#if defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_NGPIO 30 /* GPIO[A,B,C,E,H] */ -#elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E) -# define STM32WB_NGPIO 37 /* GPIO[A,B,C,E,H] */ -#elif defined(CONFIG_STM32WB_IO_CONFIG_C_49) -# define STM32WB_NGPIO 25 /* GPIO[A,B,C,H] */ -#elif defined(CONFIG_STM32WB_IO_CONFIG_R) -# define STM32WB_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ -#elif defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ +#define STM32_NUSART 1 /* USART1 */ +#define STM32_NCAN 0 /* No CAN */ +#define STM32_NSDIO 0 /* No SDIO interface */ +#define STM32_NADC 1 /* ADC1, up to 19-channels */ +#define STM32_NDAC 0 /* No DAC */ +#define STM32_NCRC 1 /* CRC */ +#define STM32_NETHERNET 0 /* No ethernet */ +#define STM32_NRNG 1 /* Random number generator (RNG) */ +#define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#if defined(CONFIG_STM32_IO_CONFIG_C) +# define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */ +#elif defined(CONFIG_STM32_IO_CONFIG_C_48E) +# define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */ +#elif defined(CONFIG_STM32_IO_CONFIG_C_49) +# define STM32_NGPIO 25 /* GPIO[A,B,C,H] */ +#elif defined(CONFIG_STM32_IO_CONFIG_R) +# define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ +#elif defined(CONFIG_STM32_IO_CONFIG_V) +# define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ #else # error "Unsupported STM32WB chip" #endif @@ -138,24 +138,24 @@ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000 */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_SRAM1_SIZE (12*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (4*1024) -#elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) -# define STM32WB_SRAM1_SIZE (32*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) -#elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ - && defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_SRAM1_SIZE (64*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) -#elif defined(CONFIG_STM32WB_STM32WB55) && \ - (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) -# define STM32WB_SRAM1_SIZE (192*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) +# define STM32_SRAM1_SIZE (12*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (4*1024) +#elif defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) +# define STM32_SRAM1_SIZE (32*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) +#elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \ + && defined(CONFIG_STM32_IO_CONFIG_C) +# define STM32_SRAM1_SIZE (64*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) +#elif defined(CONFIG_STM32_STM32WB55) && \ + (defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V)) +# define STM32_SRAM1_SIZE (192*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #else # error "Unsupported STM32WB chip" #endif diff --git a/arch/arm/include/stm32wb/irq.h b/arch/arm/include/stm32wb/irq.h index 6bd24af39e9d4..381c7e9778db8 100644 --- a/arch/arm/include/stm32wb/irq.h +++ b/arch/arm/include/stm32wb/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WB_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WB_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WB_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WB_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WB_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WB_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WB_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WB_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WB_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WB_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WB_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index 4efaba3559fbb..882ee7971a5a1 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -24,8 +24,8 @@ * through arch/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H /**************************************************************************** * Included Files @@ -51,146 +51,146 @@ * */ -#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ #endif -#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ -#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ -#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ -#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ +#define STM32_IRQ_LSECSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) - #define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ - #define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) + #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ + #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif -#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif -#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ -#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif -#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */ -#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 29) /* 29: PKA Interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ -# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif -#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif -#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) +# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ - || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */ +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) \ + || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif -#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif -#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ -#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ -#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ +#define STM32_IRQ_PWRSOTF (STM32_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ +#define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ +#define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif -#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ -#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ -#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ -#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ -#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ +#define STM32_IRQ_IPCCRX (STM32_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ +#define STM32_IRQ_IPCCTX (STM32_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */ +#if defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ -# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ +# define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif -#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ -#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */ -#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */ +#define STM32_IRQ_AES2 (STM32_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ -# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ -# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ -# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ -# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ -# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ -# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ +# define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ #endif -#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ +#define STM32_IRQ_DMAMUX1 (STM32_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ -#define STM32WB_IRQ_NEXTINTS 63 +#define STM32_IRQ_NEXTINTS 63 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types @@ -219,4 +219,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index d7da1c8c45ee6..95761ec558f53 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -33,30 +33,30 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX) -# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ -# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ +#if defined(CONFIG_STM32_STM32WL5XXX) +# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) -# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */ -# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ -# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ -# define STM32WL5_NRNG 1 /* Random number generator (RNG) */ -# define STM32WL5_NUSART 2 /* USART 1-2 */ -# define STM32WL5_NLPUART 1 /* LPUART 1 */ -# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ -# define STM32WL5_NI2C 3 /* I2C1-3 */ -# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */ -# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */ -# define STM32WL5_NADC 1 /* ADC1 */ -# define STM32WL5_NDAC 1 /* DAC1 */ -# define STM32WL5_NCRC 1 /* CRC1 */ -# define STM32WL5_NCOMP 1 /* COMP1 */ -#endif /* CONFIG_STM32WL5_STM32WL5XXX */ +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ +# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NDMA 2 /* Two DMA channels DMA1-2 */ +# define STM32_NPORTS 4 /* GPIO{A,B,C,H} */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 1 /* DAC1 */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NCOMP 1 /* COMP1 */ +#endif /* CONFIG_STM32_STM32WL5XXX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wl5/irq.h b/arch/arm/include/stm32wl5/irq.h index a8941dbeed680..500a3b957c30e 100644 --- a/arch/arm/include/stm32wl5/irq.h +++ b/arch/arm/include/stm32wl5/irq.h @@ -44,32 +44,32 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h index 88ce31efc5a24..a8c99354b2159 100644 --- a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h +++ b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h @@ -48,80 +48,80 @@ * External interrupts (vectors >= 16) */ -#define STM32WL5_IRQ_WWDG (STM32WL5_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ -#define STM32WL5_IRQ_PVD (STM32WL5_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ -#define STM32WL5_IRQ_PVM (STM32WL5_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ -#define STM32WL5_IRQ_TAMPER (STM32WL5_IRQ_FIRST + 2) /* 2: Tamper */ -#define STM32WL5_IRQ_LSE_CSS (STM32WL5_IRQ_FIRST + 2) /* 2: LSECSS */ -#define STM32WL5_IRQ_RTC_STAMP (STM32WL5_IRQ_FIRST + 2) /* 2: timestamp */ -#define STM32WL5_IRQ_RTC_SSRU (STM32WL5_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ -#define STM32WL5_IRQ_RTC_WKUP (STM32WL5_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ -#define STM32WL5_IRQ_FLASH (STM32WL5_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ -#define STM32WL5_IRQ_RCC (STM32WL5_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WL5_IRQ_EXTI0 (STM32WL5_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ -#define STM32WL5_IRQ_EXTI1 (STM32WL5_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ -#define STM32WL5_IRQ_EXTI2 (STM32WL5_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ -#define STM32WL5_IRQ_EXTI3 (STM32WL5_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ -#define STM32WL5_IRQ_EXTI4 (STM32WL5_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ -#define STM32WL5_IRQ_DMA1CH1 (STM32WL5_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH2 (STM32WL5_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH3 (STM32WL5_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH4 (STM32WL5_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH5 (STM32WL5_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH6 (STM32WL5_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH7 (STM32WL5_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_ADC (STM32WL5_IRQ_FIRST + 18) /* 18: ADC global interrupt */ -#define STM32WL5_IRQ_DAC (STM32WL5_IRQ_FIRST + 19) /* 19: DAC global interrupt */ -#define STM32WL5_IRQ_C2SEV (STM32WL5_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ -#define STM32WL5_IRQ_PWRC2H (STM32WL5_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ -#define STM32WL5_IRQ_COMP (STM32WL5_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ -#define STM32WL5_IRQ_EXTI95 (STM32WL5_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ -#define STM32WL5_IRQ_TIM1BRK (STM32WL5_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ -#define STM32WL5_IRQ_TIM1UP (STM32WL5_IRQ_FIRST + 24) /* 24: Timer 1 Update */ -#define STM32WL5_IRQ_TIM1TRG_COM (STM32WL5_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ -#define STM32WL5_IRQ_TIM1CC (STM32WL5_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ -#define STM32WL5_IRQ_TIM2 (STM32WL5_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ -#define STM32WL5_IRQ_TIM16 (STM32WL5_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ -#define STM32WL5_IRQ_TIM17 (STM32WL5_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ -#define STM32WL5_IRQ_I2C1EV (STM32WL5_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WL5_IRQ_I2C1ER (STM32WL5_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#define STM32WL5_IRQ_I2C2EV (STM32WL5_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ -#define STM32WL5_IRQ_I2C2ER (STM32WL5_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ -#define STM32WL5_IRQ_SPI1 (STM32WL5_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#define STM32WL5_IRQ_SPI2S2 (STM32WL5_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ -#define STM32WL5_IRQ_USART1 (STM32WL5_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#define STM32WL5_IRQ_USART2 (STM32WL5_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ -#define STM32WL5_IRQ_LPUART1 (STM32WL5_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ -#define STM32WL5_IRQ_LPTIM1 (STM32WL5_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ -#define STM32WL5_IRQ_LPTIM2 (STM32WL5_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ -#define STM32WL5_IRQ_EXTI1510 (STM32WL5_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ -#define STM32WL5_IRQ_RTCALRM (STM32WL5_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ -#define STM32WL5_IRQ_LPTIM3 (STM32WL5_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ - /* 44: Reserved */ -#define STM32WL5_IRQ_IPCC_C1_RX_IT (STM32WL5_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ -#define STM32WL5_IRQ_IPCC_C1_TX_IT (STM32WL5_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ -#define STM32WL5_IRQ_HSEM (STM32WL5_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ -#define STM32WL5_IRQ_I2C3EV (STM32WL5_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ -#define STM32WL5_IRQ_I2C3ER (STM32WL5_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ -#define STM32WL5_IRQ_RADIO (STM32WL5_IRQ_FIRST + 50) /* 50: Radio */ -#define STM32WL5_IRQ_RFBUSY (STM32WL5_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ -#define STM32WL5_IRQ_AES (STM32WL5_IRQ_FIRST + 51) /* 51: AES global interrupt */ -#define STM32WL5_IRQ_RNG (STM32WL5_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ -#define STM32WL5_IRQ_PKA (STM32WL5_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ -#define STM32WL5_IRQ_DMA2CH1 (STM32WL5_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH2 (STM32WL5_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH3 (STM32WL5_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH4 (STM32WL5_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH5 (STM32WL5_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH6 (STM32WL5_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH7 (STM32WL5_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_DMAMUX1_OVR (STM32WL5_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ - -#define STM32WL5_IRQ_NEXTINTS 62 +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ +#define STM32_IRQ_PVM (STM32_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper */ +#define STM32_IRQ_LSE_CSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS */ +#define STM32_IRQ_RTC_STAMP (STM32_IRQ_FIRST + 2) /* 2: timestamp */ +#define STM32_IRQ_RTC_SSRU (STM32_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 19) /* 19: DAC global interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ +#define STM32_IRQ_PWRC2H (STM32_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 24) /* 24: Timer 1 Update */ +#define STM32_IRQ_TIM1TRG_COM (STM32_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI2S2 (STM32_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ + /* 44: Reserved */ +#define STM32_IRQ_IPCC_C1_RX_IT (STM32_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ +#define STM32_IRQ_IPCC_C1_TX_IT (STM32_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ +#define STM32_IRQ_RADIO (STM32_IRQ_FIRST + 50) /* 50: Radio */ +#define STM32_IRQ_RFBUSY (STM32_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 51) /* 51: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ + +#define STM32_IRQ_NEXTINTS 62 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WL5_IRQ_FIRST + STM32WL5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32f7/hardware/stm32_adc.h b/arch/arm/src/stm32f7/hardware/stm32_adc.h index cabbd5921ef55..f8e8fb4423c48 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_adc.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_adc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_adc.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_can.h b/arch/arm/src/stm32f7/hardware/stm32_can.h index c5da101f134ac..8124ae8815f44 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_can.h +++ b/arch/arm/src/stm32f7/hardware/stm32_can.h @@ -123,7 +123,7 @@ /* Register Addresses *******************************************************/ -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) # define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) @@ -177,7 +177,7 @@ # define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) # define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) @@ -231,7 +231,7 @@ # define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN3) +#if defined(CONFIG_STM32_CAN3) # define STM32_CAN3_MCR (STM32_CAN3_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN3_MSR (STM32_CAN3_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN3_TSR (STM32_CAN3_BASE+STM32_CAN_TSR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h index 4bc19f87b6d8f..2603a97063a3f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dbgmcu.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_dma.h b/arch/arm/src/stm32f7/hardware/stm32_dma.h index 9df147e270441..1084640b37801 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dma.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h index ff9a5be351cd6..b2e403ca83d32 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h @@ -33,8 +33,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -810,7 +810,7 @@ struct eth_txdesc_s /* Enhanced DMA descriptor words with time stamp */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t tdes4; /* Reserved */ volatile uint32_t tdes5; /* Reserved */ volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ @@ -829,7 +829,7 @@ struct eth_rxdesc_s /* Enhanced DMA descriptor words with time stamp and PTP support */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ volatile uint32_t rdes5; /* Reserved */ volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ @@ -842,5 +842,5 @@ struct eth_rxdesc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_exti.h b/arch/arm/src/stm32f7/hardware/stm32_exti.h index b846f19c0f837..62fe35128bc8c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32f7/hardware/stm32_exti.h @@ -34,9 +34,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -116,5 +116,5 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_flash.h b/arch/arm/src/stm32f7/hardware/stm32_flash.h index 37551dde1b822..79050bf7c7bab 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32_flash.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_gpio.h b/arch/arm/src/stm32f7/hardware/stm32_gpio.h index 9449df0fa0694..03f642dac61fa 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32_gpio.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_i2c.h b/arch/arm/src/stm32f7/hardware/stm32_i2c.h index 15456f503b3e1..bacc9e367e8b4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32_i2c.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_i2c.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h index fe51a5ccc2420..57a9b1298f63a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h index dad7c1251f86d..5c10f75322c73 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pinmap.h" #else # error "Unsupported STM32 F7 Pin map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pwr.h b/arch/arm/src/stm32f7/hardware/stm32_pwr.h index 9eff00fa4929b..09792a2458dfd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pwr.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index 31cf04e853476..b857ca463b5ec 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32F7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32F7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_rcc.h b/arch/arm/src/stm32f7/hardware/stm32_rcc.h index bc41cad8beb99..61a34dd8460b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_rcc.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index c71d7adc87ff0..b93784989026a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32F7_SAI_A_OFFSET 0x0004 -#define STM32F7_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET) - -#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET) - -#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET) - -#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI1_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_DR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h index 563818cc6c2b6..59f1f7ad3cb42 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_spi.h b/arch/arm/src/stm32f7/hardware/stm32_spi.h index 1411319566d4b..94fe7c794cfe3 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_spi.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_spi.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h index 5112e47413064..18ff0709820ed 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h index 46ffb0f4b1186..6dfc200978cb5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_tim.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_uart.h b/arch/arm/src/stm32f7/hardware/stm32_uart.h index 4ef7a625794d5..0cd6b9c8d9663 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32_uart.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_uart.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h index e02cfef5ecfca..0c529af4b75d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h index 7347b6b06d221..e0b4f0d71fee6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -539,5 +539,5 @@ #define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h index a7596397397b4..e24ebcdafbc9c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F72xxC have 256Kb of FLASH * Parts STM32F72xxE have 512Kb of FLASH @@ -44,38 +44,38 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_C) -# define CONFIG_STM32F7_FLASH_OVERRIDE_C +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) +# define CONFIG_STM32_FLASH_OVERRIDE_C # warning "Flash size not defined defaulting to 256KiB (C)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_C -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) -# define CONFIG_STM32F7_FLASH_CONFIG_C +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ _K(64), _K(128)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index 07752be9bf57c..3f961686b388d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h index 1e10e0c06b17d..0ee93e4ee04e4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -188,5 +188,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h index 51ef59e85acd4..9e649c192cea9 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -923,5 +923,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h index b712b40aa6fab..206807751d1ed 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h index a9dc161a5aef5..c7e53682bdd15 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -677,5 +677,5 @@ # define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h index cbcba08dbf47f..00fe52c6f7cda 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h @@ -54,7 +54,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -64,7 +64,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -76,7 +76,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -88,7 +88,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -100,7 +100,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -112,7 +112,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h index 6c206fcebfcea..d777cdddb4cb1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -145,5 +145,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index d9d897fe1e321..5a3e8dbb1d480 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 6473f22947bf1..997b618630326 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -66,7 +66,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -81,7 +81,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -96,7 +96,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -111,7 +111,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -126,7 +126,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -141,7 +141,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -156,7 +156,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) @@ -354,5 +354,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h index d82ff66c0a25a..58a50d908c944 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -545,5 +545,5 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index 23ba0cc2f6bc9..3ed343c6612d6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -42,39 +42,39 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index 7d40fb94d08a2..a423e8c659f1c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h index 350f17cc26039..74f18438de7e5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -199,5 +199,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h index 322f006d44d78..4f355760b2350 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -808,7 +808,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1171,5 +1171,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h index 45fda531bd7fc..984af74a9980b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h index 2af6d3397204c..ef250fe77ba7a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -723,5 +723,5 @@ # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h index 5072c16d68151..e634ebdb7ebc5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 44bea32690327..f3144d3568da8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index 4d6e8e398786a..8f2ede7053f76 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 0194d61ee7479..a6417e0d4a817 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index dd0d8963188a0..c1bfd5b133926 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -38,9 +38,9 @@ * (both pclk1 and pclk2) */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SPI_CLK_MAX 50000000UL -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SPI_CLK_MAX 54000000UL #endif @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -68,7 +68,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -80,7 +80,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -92,7 +92,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -104,7 +104,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -116,7 +116,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index 6dfbba5177a97..bfefcbffcdeea 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) @@ -356,5 +356,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h index dbe7de5cf2f0b..208693831dfe5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -585,5 +585,5 @@ #define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index 84e638d078a67..99463d161364e 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -29,10 +29,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. - * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x + * This value can be overridden with CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32F74xxE have 512Kb of FLASH * Parts STM32F74xxG have 1024Kb of FLASH @@ -42,53 +42,53 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_I) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G -# undef CONFIG_STM32F7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32F7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256), _K(256), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NPAGES 12 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index dc76911406292..a63ce45ffc1d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h index 1f9e1673df36a..b60c2f882c580 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -205,5 +205,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h index 82d795a98c044..5ef7ae8ecde01 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -916,7 +916,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1330,5 +1330,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h index 54afc5d9d3d7f..b6d554f765b23 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h index 7b72de0e625a2..6a56b4494b5dd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -756,5 +756,5 @@ # define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */ # define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h index 11b42882cff3b..ef63b7dede8e1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -163,5 +163,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index fc2fa7bec8174..b2586544aa498 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -99,7 +99,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -127,7 +127,7 @@ # define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -159,7 +159,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -181,7 +181,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -202,7 +202,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -223,7 +223,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -250,7 +250,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -265,7 +265,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -278,7 +278,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -292,7 +292,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -307,7 +307,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -320,7 +320,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -335,7 +335,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -346,7 +346,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index e875c19c71a54..90f56057b4ca5 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -59,7 +59,7 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F7_ADC +#ifdef CONFIG_STM32_ADC /* This implementation is for the STM32 ADC IP version 1 */ @@ -121,21 +121,21 @@ /* ADC scan mode support */ -#ifndef CONFIG_STM32F7_ADC1_SCAN -# define CONFIG_STM32F7_ADC1_SCAN 0 +#ifndef CONFIG_STM32_ADC1_SCAN +# define CONFIG_STM32_ADC1_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC2_SCAN -# define CONFIG_STM32F7_ADC2_SCAN 0 +#ifndef CONFIG_STM32_ADC2_SCAN +# define CONFIG_STM32_ADC2_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC3_SCAN -# define CONFIG_STM32F7_ADC3_SCAN 0 +#ifndef CONFIG_STM32_ADC3_SCAN +# define CONFIG_STM32_ADC3_SCAN 0 #endif /* We have to support ADC callbacks if default ADC interrupts or * DMA transfer are enabled */ -#if !defined(CONFIG_STM32F7_ADC_NOIRQ) || defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) # define ADC_HAVE_CB #else # undef ADC_HAVE_CB @@ -184,7 +184,7 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ struct adc_dev_s *dev; /* Upper-half ADC reference */ #endif @@ -210,7 +210,7 @@ struct stm32_dev_s uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif bool scan; /* True: Scan mode */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. * REVISIT: this takes too much space. We need only 3 bits per channel. */ @@ -252,7 +252,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F7_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -293,10 +293,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc123_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -321,7 +321,7 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable); static int adc_timinit(struct stm32_dev_s *priv); #endif -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -346,7 +346,7 @@ static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static int adc_llops_setup(struct stm32_adc_dev_s *dev); static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); @@ -375,7 +375,7 @@ static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -403,7 +403,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .setup = adc_llops_setup, @@ -428,7 +428,7 @@ static const struct stm32_adc_ops_s g_adc_llops = .inj_get = adc_injget, .inj_startconv = adc_llops_inj_startconv, # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -454,27 +454,27 @@ struct adccmn_data_s g_adc123_cmn = /* ADC1 state */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC1CMN_DATA, .intf = 1, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC1_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC1_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, @@ -483,19 +483,19 @@ static struct stm32_dev_s g_adcpriv1 = .jextcfg = ADC1_JEXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC1_SCAN, + .scan = CONFIG_STM32_ADC1_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -513,27 +513,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC2CMN_DATA, .intf = 2, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC2_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC2_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, #ifdef ADC2_HAVE_EXTCFG .extcfg = ADC2_EXTCFG_VALUE, @@ -542,19 +542,19 @@ static struct stm32_dev_s g_adcpriv2 = .jextcfg = ADC2_JEXTCFG_VALUE, #endif #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC2_SCAN, + .scan = CONFIG_STM32_ADC2_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -572,27 +572,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC3CMN_DATA, .intf = 3, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC3_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC3_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, .base = STM32_ADC3_BASE, #ifdef ADC3_HAVE_EXTCFG .extcfg = ADC3_EXTCFG_VALUE, @@ -601,19 +601,19 @@ static struct stm32_dev_s g_adcpriv3 = .jextcfg = ADC3_JEXTCFG_VALUE, #endif #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC3_SCAN, + .scan = CONFIG_STM32_ADC3_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -1455,7 +1455,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -1587,7 +1587,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); #else struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1673,7 +1673,7 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Start DMA only if standard ADC interrupts used */ stm32_dmasetup(priv->dma, @@ -1853,7 +1853,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1885,7 +1885,7 @@ static int adc_setup(struct adc_dev_s *dev) /* As default conversion is started here */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1909,7 +1909,7 @@ static int adc_setup(struct adc_dev_s *dev) { /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1967,7 +1967,7 @@ static void adc_shutdown(struct adc_dev_s *dev) if (priv->cmn->refcount <= 1) { -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2469,7 +2469,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2570,23 +2570,23 @@ static int adc_interrupt(struct adc_dev_s *dev) static int adc123_interrupt(int irq, void *context, void *arg) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 adc_interrupt(&g_adcdev2); #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 adc_interrupt(&g_adcdev3); #endif return OK; } -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_setup @@ -2821,7 +2821,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; @@ -2911,7 +2911,7 @@ void adc_sampletime_set(struct stm32_adc_dev_s *dev, } } } -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -3017,7 +3017,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) adc_enable(priv, enable); } -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -3032,7 +3032,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * The logic allow initialize ADC regular and injected channels. * * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32F7_ADCx_INJECTED_CHAN definitions + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions * * The number of regular channels is obtained from the equation: * @@ -3056,9 +3056,9 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) * chanlist[channels] -> ADC_JSQR_ISQy * * where: - * y = CONFIG_STM32F7_ADCx_INJECTED_CHAN, and y > 0 + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 * - * If CONFIG_STM32F7_ADCx_INJECTED_CHAN = 0, then all channels from + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from * chanlist are regular channels. * * Input Parameters: @@ -3085,12 +3085,12 @@ struct adc_dev_s *stm32_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); dev = &g_adcdev1; - cj_channels = CONFIG_STM32F7_ADC1_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3100,14 +3100,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); dev = &g_adcdev2; - cj_channels = CONFIG_STM32F7_ADC2_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3117,14 +3117,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); dev = &g_adcdev3; - cj_channels = CONFIG_STM32F7_ADC3_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3135,7 +3135,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, break; } -#endif /* CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC3 */ default: { @@ -3150,10 +3150,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, /* Configure regular channels */ - DEBUGASSERT(cr_channels <= CONFIG_STM32F7_ADC_MAX_SAMPLES); - if (cr_channels > CONFIG_STM32F7_ADC_MAX_SAMPLES) + DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cr_channels = CONFIG_STM32F7_ADC_MAX_SAMPLES; + cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cr_channels = cr_channels; @@ -3172,14 +3172,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, memcpy(priv->j_chanlist, j_chanlist, cj_channels); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Assign default values for the sample time table */ memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* Store reference to the upper-half ADC device */ priv->dev = dev; @@ -3195,4 +3195,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32F7_ADC */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index b7e65e975886c..58b2aff989260 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -58,80 +58,80 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1-6 and 8 may be used. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_ADC -# undef CONFIG_STM32F7_TIM1_ADC1 -# undef CONFIG_STM32F7_TIM1_ADC2 -# undef CONFIG_STM32F7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_ADC -# undef CONFIG_STM32F7_TIM2_ADC1 -# undef CONFIG_STM32F7_TIM2_ADC2 -# undef CONFIG_STM32F7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_ADC -# undef CONFIG_STM32F7_TIM3_ADC1 -# undef CONFIG_STM32F7_TIM3_ADC2 -# undef CONFIG_STM32F7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_ADC -# undef CONFIG_STM32F7_TIM4_ADC1 -# undef CONFIG_STM32F7_TIM4_ADC2 -# undef CONFIG_STM32F7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_ADC -# undef CONFIG_STM32F7_TIM5_ADC1 -# undef CONFIG_STM32F7_TIM5_ADC2 -# undef CONFIG_STM32F7_TIM5_ADC3 +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM6 -# undef CONFIG_STM32F7_TIM6_ADC -# undef CONFIG_STM32F7_TIM6_ADC1 -# undef CONFIG_STM32F7_TIM6_ADC2 -# undef CONFIG_STM32F7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_ADC -# undef CONFIG_STM32F7_TIM8_ADC1 -# undef CONFIG_STM32F7_TIM8_ADC2 -# undef CONFIG_STM32F7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \ - defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \ - defined(CONFIG_STM32F7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -139,9 +139,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32F7_ADC1) && (CONFIG_STM32F7_ADC1_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC2) && (CONFIG_STM32F7_ADC2_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC3) && (CONFIG_STM32F7_ADC3_INJECTED_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -149,31 +149,31 @@ * information about the timer. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC1) +#elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -182,40 +182,40 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC1_TIMTRIG -# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC2) +#elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -224,36 +224,36 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC2_TIMTRIG -# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC3) +#elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -262,11 +262,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC3_TIMTRIG -# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -408,320 +408,320 @@ /* EXTSEL configuration *****************************************************/ /* NOTE: - * this configuration if used only if CONFIG_STM32F7_TIMx_ADCy is selected. + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is selected. * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F7_ADCx_EXTSEL option. + * CONFIG_STM32_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -730,7 +730,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -739,7 +739,7 @@ #ifdef ADC2_EXTSEL_VALUE # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_EXTSEL) +#elif defined(CONFIG_STM32_ADC2_EXTSEL) # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE 0 #else @@ -748,7 +748,7 @@ #ifdef ADC3_EXTSEL_VALUE # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_EXTSEL) +#elif defined(CONFIG_STM32_ADC3_EXTSEL) # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE 0 #else @@ -771,7 +771,7 @@ #ifdef ADC1_JEXTSEL_VALUE # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_JEXTSEL) +#elif defined(CONFIG_STM32_ADC1_JEXTSEL) # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE 0 #else @@ -780,7 +780,7 @@ #ifdef ADC2_JEXTSEL_VALUE # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_JEXTSEL) +#elif defined(CONFIG_STM32_ADC2_JEXTSEL) # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE 0 #else @@ -789,7 +789,7 @@ #ifdef ADC3_JEXTSEL_VALUE # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_JEXTSEL) +#elif defined(CONFIG_STM32_ADC3_JEXTSEL) # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE 0 #else @@ -914,9 +914,9 @@ enum stm32_adc_multimode_e ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ }; -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Channel and sample time pair */ @@ -941,7 +941,7 @@ struct adc_sample_time_s * same value of the sample time */ uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -1024,7 +1024,7 @@ struct stm32_adc_ops_s void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -1046,7 +1046,7 @@ struct stm32_adc_ops_s void (*enable)(struct stm32_adc_dev_s *dev, bool enable); }; -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -1088,7 +1088,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || - * CONFIG_STM32F7_ADC3 +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 0991bcece13cb..8c0a72c9ce1eb 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -62,8 +62,8 @@ * the FMC. In order to use FMC RAM, the following additional things need * to be present in the NuttX configuration file: * - * CONFIG_STM32F7_FMC=y : Enables the FMC - * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. + * CONFIG_STM32_FMC=y : Enables the FMC + * CONFIG_STM32_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. * Either of these autoselects * CONFIG_ARCH_HAVE_HEAP2 * which is what we are interested in here. @@ -79,10 +79,10 @@ /* Set the start and end of SRAM1 and SRAM2 */ #define SRAM1_START STM32_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* The STM32 F7 has DTCM memory */ @@ -94,15 +94,15 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32F7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif /* We can't possibly have FMC external RAM if the FMC is not enabled */ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # ifdef CONFIG_ARCH_HAVE_HEAP2 -# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed? +# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32_FMC! Kconfig flawed? # endif # undef CONFIG_ARCH_HAVE_HEAP2 #endif diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index 36d92cc7de361..65a5b0e510fdb 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -51,14 +51,14 @@ #include "stm32_pwr.h" #include "stm32_rtc.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32F7_BKPSRAM) -#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -130,7 +130,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32F7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -147,7 +147,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -544,7 +544,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -627,13 +627,13 @@ static int stm32_bbsram_unlink(struct inode *inode) static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) { int i; - int avail = STM32F7_BBSRAM_SIZE; + int avail = STM32_BBSRAM_SIZE; int alloc; int size; int ret = -EFBIG; struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; - for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -784,7 +784,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -802,7 +802,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 4d080578c4eeb..a660e0e02b97f 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -25,7 +25,7 @@ /**************************************************************************** * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined. + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. * These files are of fixed size up to the maximum of the backing 4K SRAM. * * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature @@ -44,22 +44,22 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif -#if !defined(CONFIG_STM32F7_BBSRAM_FILES) -# define CONFIG_STM32F7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -110,8 +110,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES - * CONFIG_STM32F7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * @@ -140,7 +140,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index b51547ebe3544..2d571c61b8dc3 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -48,8 +48,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_CAN) && \ - (defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) || \ - defined(CONFIG_STM32F7_CAN3)) + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) || \ + defined(CONFIG_STM32_CAN3)) /**************************************************************************** * Pre-processor Definitions @@ -63,7 +63,7 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO # undef CONFIG_STM32_CAN_REGDEBUG @@ -179,7 +179,7 @@ static const struct can_ops_s g_canops = .co_txempty = stm32can_txempty, }; -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { .port = 1, @@ -192,7 +192,7 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -202,7 +202,7 @@ static struct can_dev_s g_can1dev = }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { .port = 2, @@ -215,7 +215,7 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; static struct can_dev_s g_can2dev = @@ -225,7 +225,7 @@ static struct can_dev_s g_can2dev = }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { .port = 3, @@ -238,7 +238,7 @@ static struct stm32_can_s g_can3priv = .filter = 0, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; static struct can_dev_s g_can3dev = @@ -582,21 +582,21 @@ static void stm32can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -1789,8 +1789,8 @@ static int stm32can_bittiming(struct stm32_can_s *priv) else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2038,7 +2038,7 @@ static int stm32can_filterinit(struct stm32_can_s *priv) regval |= CAN_FMR_FINIT; stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#if defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) if (priv->port == 1 || priv->port == 2) { /* Assign half the filters to CAN1, half to CAN2 */ @@ -2270,7 +2270,7 @@ struct can_dev_s *stm32_caninitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2286,7 +2286,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2302,7 +2302,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index 05dbe1e10c650..cf080ba400d33 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32F7_CAN_H -#define __ARCH_ARM_SRC_STM32_STM32F7_CAN_H +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32F7_STM32_CAN_H /**************************************************************************** * Included Files @@ -40,45 +40,45 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \ - defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3)) +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || \ + defined(CONFIG_STM32_CAN2) || defined(CONFIG_STM32_CAN3)) /* CAN BAUD */ -#if defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN1_BAUD) -# error "CONFIG_STM32F7_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN2) && !defined(CONFIG_STM32F7_CAN2_BAUD) -# error "CONFIG_STM32F7_CAN2_BAUD is not defined" +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN3) && !defined(CONFIG_STM32F7_CAN3_BAUD) -# error "CONFIG_STM32F7_CAN3_BAUD is not defined" +#if defined(CONFIG_STM32_CAN3) && !defined(CONFIG_STM32_CAN3_BAUD) +# error "CONFIG_STM32_CAN3_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32F7_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32F7_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32F7_CAN_TSEG1 -# define CONFIG_STM32F7_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \ - CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +#if CONFIG_STM32_CAN_TSEG1 < 1 || \ + CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX # error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32F7_CAN_TSEG2 -# define CONFIG_STM32F7_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \ - CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +#if CONFIG_STM32_CAN_TSEG2 < 1 || \ + CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX # error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif @@ -105,7 +105,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -125,7 +125,7 @@ struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize @@ -151,4 +151,4 @@ int stm32_cansockinitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_CAN_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index c421e4c0e5e1f..14f9ccda0202e 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -63,10 +63,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F7_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /* Pool configuration *******************************************************/ @@ -146,7 +146,7 @@ static void stm32can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); static void stm32can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); static void stm32can_dumpmbregs(struct stm32_can_s *priv, @@ -233,7 +233,7 @@ static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { @@ -250,12 +250,12 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { @@ -272,12 +272,12 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { @@ -294,7 +294,7 @@ static struct stm32_can_s g_can3priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; #endif @@ -312,7 +312,7 @@ static struct stm32_can_s g_can3priv = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -398,7 +398,7 @@ static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -451,7 +451,7 @@ static void stm32can_putfreg(struct stm32_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { @@ -497,7 +497,7 @@ static void stm32can_dumpctrlregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { @@ -564,7 +564,7 @@ static void stm32can_dumpmbregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { @@ -729,7 +729,7 @@ static void stm32can_errint(struct stm32_can_s *priv, bool enable) } else { - regval &= ~STM32F7_CAN_ERRINT; + regval &= ~STM32_CAN_ERRINT; } stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); @@ -1860,15 +1860,15 @@ static int stm32can_bittiming(struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32F7_CAN_TSEG1, - * ts2 is CONFIG_STM32F7_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2036,21 +2036,21 @@ static void stm32can_reset(struct stm32_can_s *priv) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -2298,9 +2298,9 @@ static int stm32can_filterinit(struct stm32_can_s *priv) /* Assign half the filters to CAN1, half to CAN2 */ -#if defined(CONFIG_STM32F7_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32F7_STM32F20XX) || \ - defined(CONFIG_STM32F7_STM32F4XXX) +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= CAN_FMR_CAN2SB_MASK; regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; @@ -2432,7 +2432,7 @@ int stm32_cansockinitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2448,7 +2448,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2464,7 +2464,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ @@ -2526,15 +2526,15 @@ int stm32_cansockinitialize(int port) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_cansockinitialize(1); #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 stm32_cansockinitialize(2); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 stm32_cansockinitialize(3); #endif } diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index 6e650a6e849e6..84efc445174b5 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -92,18 +92,18 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1_CAP) || \ - defined(CONFIG_STM32F7_TIM2_CAP) || \ - defined(CONFIG_STM32F7_TIM3_CAP) || \ - defined(CONFIG_STM32F7_TIM4_CAP) || \ - defined(CONFIG_STM32F7_TIM5_CAP) || \ - defined(CONFIG_STM32F7_TIM8_CAP) || \ - defined(CONFIG_STM32F7_TIM9_CAP) || \ - defined(CONFIG_STM32F7_TIM10_CAP) || \ - defined(CONFIG_STM32F7_TIM11_CAP) || \ - defined(CONFIG_STM32F7_TIM12_CAP) || \ - defined(CONFIG_STM32F7_TIM13_CAP) || \ - defined(CONFIG_STM32F7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || \ + defined(CONFIG_STM32_TIM2_CAP) || \ + defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || \ + defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || \ + defined(CONFIG_STM32_TIM10_CAP) || \ + defined(CONFIG_STM32_TIM11_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || \ + defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) /**************************************************************************** * Private Types @@ -182,7 +182,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) { switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -209,7 +209,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -236,7 +236,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -263,7 +263,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -290,7 +290,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -320,7 +320,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -348,7 +348,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -376,7 +376,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -404,7 +404,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -432,7 +432,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -460,7 +460,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -488,7 +488,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -528,31 +528,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM5EN; @@ -561,43 +561,43 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM9EN; break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM10EN; break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM11EN; break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM14EN; @@ -1082,7 +1082,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1094,7 +1094,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1106,7 +1106,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1118,7 +1118,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1130,7 +1130,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1144,7 +1144,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1156,7 +1156,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1168,7 +1168,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1180,7 +1180,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1192,7 +1192,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1204,7 +1204,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1216,7 +1216,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1232,54 +1232,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1336,4 +1336,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index 9bec9e5870441..c017552e64dc7 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -38,62 +38,62 @@ /* GPIO IRQs ****************************************************************/ -#ifndef CONFIG_STM32F7_GPIO_IRQ -# undef CONFIG_STM32F7_GPIOA_IRQ -# undef CONFIG_STM32F7_GPIOB_IRQ -# undef CONFIG_STM32F7_GPIOC_IRQ -# undef CONFIG_STM32F7_GPIOD_IRQ -# undef CONFIG_STM32F7_GPIOE_IRQ +#ifndef CONFIG_STM32_GPIO_IRQ +# undef CONFIG_STM32_GPIOA_IRQ +# undef CONFIG_STM32_GPIOB_IRQ +# undef CONFIG_STM32_GPIOC_IRQ +# undef CONFIG_STM32_GPIOD_IRQ +# undef CONFIG_STM32_GPIOE_IRQ #endif -#if STM32F7_NPORTS < 1 -# undef CONFIG_STM32F7_GPIOA_IRQ +#if STM32_NPORTS < 1 +# undef CONFIG_STM32_GPIOA_IRQ #endif -#if STM32F7_NPORTS < 2 -# undef CONFIG_STM32F7_GPIOB_IRQ +#if STM32_NPORTS < 2 +# undef CONFIG_STM32_GPIOB_IRQ #endif -#if STM32F7_NPORTS < 3 -# undef CONFIG_STM32F7_GPIOC_IRQ +#if STM32_NPORTS < 3 +# undef CONFIG_STM32_GPIOC_IRQ #endif -#if STM32F7_NPORTS < 4 -# undef CONFIG_STM32F7_GPIOD_IRQ +#if STM32_NPORTS < 4 +# undef CONFIG_STM32_GPIOD_IRQ #endif -#if STM32F7_NPORTS < 5 -# undef CONFIG_STM32F7_GPIOE_IRQ +#if STM32_NPORTS < 5 +# undef CONFIG_STM32_GPIOE_IRQ #endif /* UARTs ********************************************************************/ /* Don't enable UARTs not supported by the chip. */ -#if STM32F7_NUART < 1 -# undef CONFIG_STM32F7_UART0 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 2 -# undef CONFIG_STM32F7_UART1 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 3 -# undef CONFIG_STM32F7_UART2 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 4 -# undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 5 -# undef CONFIG_STM32F7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART0 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 2 +# undef CONFIG_STM32_UART1 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 3 +# undef CONFIG_STM32_UART2 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 4 +# undef CONFIG_STM32_UART3 +# undef CONFIG_STM32_UART4 +#elif STM32_NUART < 5 +# undef CONFIG_STM32_UART4 #endif /* Are any UARTs enabled? */ #undef HAVE_UART_DEVICE -#if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ - defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ - defined(CONFIG_STM32F7_UART4) +#if defined(CONFIG_STM32_UART0) || defined(CONFIG_STM32_UART1) || \ + defined(CONFIG_STM32_UART2) || defined(CONFIG_STM32_UART3) || \ + defined(CONFIG_STM32_UART4) # define HAVE_UART_DEVICE 1 #endif @@ -104,32 +104,32 @@ */ #ifndef CONFIG_USART0_SERIALDRIVER -# undef CONFIG_STM32F7_USART0 +# undef CONFIG_STM32_USART0 #endif #ifndef CONFIG_USART1_SERIALDRIVER -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif #ifndef CONFIG_USART2_SERIALDRIVER -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Don't enable USARTs not supported by the chip. */ -#if STM32F7_NUSART < 1 -# undef CONFIG_STM32F7_USART0 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 2 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 3 -# undef CONFIG_STM32F7_USART2 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART0 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 +#elif STM32_NUSART < 2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 +#elif STM32_NUSART < 3 +# undef CONFIG_STM32_USART2 #endif /* Are any USARTs enabled? */ -#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \ - defined(CONFIG_STM32F7_USART2) +#if defined(CONFIG_STM32_USART0) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # undef HAVE_UART_DEVICE # define HAVE_UART_DEVICE 1 #endif @@ -158,12 +158,12 @@ /* Is there a serial console? There should be no more than one defined. * It could be on any: - * UARTn, n=1..STM32F7_NUART, or - * USARTn, n=1..STM32F7_NUSART + * UARTn, n=1..STM32_NUART, or + * USARTn, n=1..STM32_NUSART */ #undef HAVE_SERIAL_CONSOLE -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART0) +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART0) # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -172,7 +172,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART1) +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -181,7 +181,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART2) +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART3_SERIAL_CONSOLE @@ -190,7 +190,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART3) +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART3) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -199,7 +199,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -208,7 +208,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART0) +#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART0) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -217,7 +217,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -251,21 +251,21 @@ /* Don't enable SPI peripherals not supported by the chip. */ #if CHIP_NSPI < 1 -# undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI0 +# undef CONFIG_STM32_SPI1 #elif CHIP_NSPI < 2 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif -#ifndef CONFIG_STM32F7_HAVE_SPI -# undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +#ifndef CONFIG_STM32_HAVE_SPI +# undef CONFIG_STM32_SPI0 +# undef CONFIG_STM32_SPI1 #endif /* Are any SPI peripherals enabled? */ -#if !defined(CONFIG_STM32F7_SPI0) && !defined(CONFIG_STM32F7_SPI0) -# undef CONFIG_STM32F7_HAVE_SPI +#if !defined(CONFIG_STM32_SPI0) && !defined(CONFIG_STM32_SPI0) +# undef CONFIG_STM32_HAVE_SPI #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 72e2d1f52d360..75c9f5d952435 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -46,16 +46,16 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM33F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ #define DMA1_NSTREAMS 8 -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NSTREAMS 8 # define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) #else @@ -148,7 +148,7 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 { .stream = 0, .irq = STM32_IRQ_DMA2S0, @@ -268,13 +268,13 @@ static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, { int index; - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32F7_NDMA); + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); /* Convert the controller + stream based on the fact that there are * 8 streams per controller. */ -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 index = controller << 3 | stream; #else index = stream; @@ -376,7 +376,7 @@ static int stm32_dmainterrupt(int irq, void *context, void *arg) controller = DMA1; } else -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -596,7 +596,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); #endif @@ -895,7 +895,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; @@ -958,7 +958,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) dmawarn("stm32_dmacapable:" " dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08" PRIx32 "\n", maddr, mend); -#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1121,4 +1121,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, } #endif -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index d858a62c14ff6..7ad69cd3ec2f5 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -242,7 +242,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index f8cd2d298bb69..cb8cdc15fe60a 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -91,7 +91,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_DMA2D_REGDEBUG +#ifdef CONFIG_STM32_DMA2D_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -109,7 +109,7 @@ struct stm32_dma2d_s { struct dma2d_layer_s dma2d; /* Public dma2d interface */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint32_t *clut; /* Color lookup table */ #endif @@ -172,7 +172,7 @@ static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = STM32_DMA2D_OCOLR }; -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* DMA2D clut memory address register */ static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = @@ -192,7 +192,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); static int stm32_dma2dirq(int irq, void *context, void *arg); static int stm32_dma2d_waitforirq(void); static int stm32_dma2d_start(void); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_loadclut(uintptr_t reg); #endif static uint32_t @@ -212,7 +212,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Public Functions */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); #endif static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, @@ -239,15 +239,15 @@ static bool g_initialized; /* Allocate clut */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static uint32_t g_clut[STM32_DMA2D_NCLUT * -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY 4 # else 3 # endif / 4]; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The DMA2D mutex that enforces mutually exclusive access */ @@ -270,14 +270,14 @@ static struct stm32_dma2d_s g_dma2ddev = { .dma2d = { -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .setclut = stm32_dma2d_setclut, #endif .fillcolor = stm32_dma2d_fillcolor, .blit = stm32_dma2d_blit, .blend = stm32_dma2d_blend }, -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .clut = g_clut, #endif .lock = &g_lock @@ -344,7 +344,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg) putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); priv->error = OK; } -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 else if (regval & DMA2D_ISR_CTCIF) { /* CLUT transfer complete interrupt */ @@ -461,7 +461,7 @@ static int stm32_dma2d_waitforirq(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 static int stm32_dma2d_loadclut(uintptr_t pfcreg) { int ret; @@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, pfccrreg = DMA2D_XGPFCCR_CM(fmt); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (fmt == DMA2D_PF_L8) { struct stm32_dma2d_s *layer = &g_dma2ddev; @@ -692,7 +692,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Set the CLUT color mode */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY pfccrreg |= DMA2D_XGPFCCR_CCM; # endif @@ -708,7 +708,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Set alpha blend mode */ @@ -744,7 +744,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) { int n; @@ -760,7 +760,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) * blit operation becomes active */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY uint8_t *clut = (uint8_t *)g_dma2ddev.clut; uint16_t offset = 3 * n; @@ -789,7 +789,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) nxmutex_unlock(priv->lock); return OK; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_dma2d_fillcolor @@ -822,7 +822,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (oinfo->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1006,7 +1006,7 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (doverlay->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1095,7 +1095,7 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32f7/stm32f7xxxx_rcc.c */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h index 0f84a7732bf37..06ace50a01d2f 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.h +++ b/arch/arm/src/stm32f7/stm32_dma2d.h @@ -65,7 +65,7 @@ struct dma2d_layer_s * On error - -EINVAL */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP int (*setclut)(const struct fb_cmap_s * cmap); #endif diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index 980add5f69fee..4299724554458 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -43,11 +43,11 @@ /* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20010000 -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20020000 #else @@ -58,7 +58,7 @@ * heap. */ -#ifndef CONFIG_STM32F7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index bf70e68ec45f4..727ac68639a25 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -54,31 +54,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32F7_NGPIO] = +static const char g_portchar[STM32_NGPIO] = { -#if STM32F7_NGPIO > 11 +#if STM32_NGPIO > 11 # error "Additional support required for this number of GPIOs" -#elif STM32F7_NGPIO > 10 +#elif STM32_NGPIO > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32F7_NGPIO > 9 +#elif STM32_NGPIO > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32F7_NGPIO > 8 +#elif STM32_NGPIO > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32F7_NGPIO > 7 +#elif STM32_NGPIO > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32F7_NGPIO > 6 +#elif STM32_NGPIO > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32F7_NGPIO > 5 +#elif STM32_NGPIO > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32F7_NGPIO > 4 +#elif STM32_NGPIO > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32F7_NGPIO > 3 +#elif STM32_NGPIO > 3 'A', 'B', 'C', 'D' -#elif STM32F7_NGPIO > 2 +#elif STM32_NGPIO > 2 'A', 'B', 'C' -#elif STM32F7_NGPIO > 1 +#elif STM32_NGPIO > 1 'A', 'B' -#elif STM32F7_NGPIO > 0 +#elif STM32_NGPIO > 0 'A' #else # error "Bad number of GPIOs" @@ -112,7 +112,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32F7_NGPIO); + DEBUGASSERT(port < STM32_NGPIO); gpioinfo("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); @@ -144,5 +144,5 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 22c185ac8f825..666186b2cebb7 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -65,12 +65,12 @@ #include -/* STM32F7_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32F7_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -78,7 +78,7 @@ /* Configuration ************************************************************/ -#if STM32F7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -101,76 +101,76 @@ #define ETHWORK LPWORK -#ifndef CONFIG_STM32F7_PHYADDR -# error "CONFIG_STM32F7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32F7_MII) && !defined(CONFIG_STM32F7_RMII) -# warning "Neither CONFIG_STM32F7_MII nor CONFIG_STM32F7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32F7_MII) && defined(CONFIG_STM32F7_RMII) -# error "Both CONFIG_STM32F7_MII and CONFIG_STM32F7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32F7_MII -# if !defined(CONFIG_STM32F7_MII_MCO1) && !defined(CONFIG_STM32F7_MII_MCO2) && \ - !defined(CONFIG_STM32F7_MII_EXTCLK) -# warning "Neither CONFIG_STM32F7_MII_MCO1, CONFIG_STM32F7_MII_MCO2, nor CONFIG_STM32F7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_MII_MCO1) && defined(CONFIG_STM32F7_MII_MCO2) -# error "Both CONFIG_STM32F7_MII_MCO1 and CONFIG_STM32F7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_RMII -# if !defined(CONFIG_STM32F7_RMII_MCO1) && !defined(CONFIG_STM32F7_RMII_MCO2) && \ - !defined(CONFIG_STM32F7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32F7_RMII_MCO1, CONFIG_STM32F7_RMII_MCO2, nor CONFIG_STM32F7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_RMII_MCO1) && defined(CONFIG_STM32F7_RMII_MCO2) -# error "Both CONFIG_STM32F7_RMII_MCO1 and CONFIG_STM32F7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_AUTONEG -# ifndef CONFIG_STM32F7_PHYSR -# error "CONFIG_STM32F7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32F7_PHYSR_ALTMODE -# error "CONFIG_STM32F7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10HD -# error "CONFIG_STM32F7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100HD -# error "CONFIG_STM32F7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10FD -# error "CONFIG_STM32F7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100FD -# error "CONFIG_STM32F7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32F7_PHYSR_SPEED -# error "CONFIG_STM32F7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100MBPS -# error "CONFIG_STM32F7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_MODE -# error "CONFIG_STM32F7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32F7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP -# warning "CONFIG_STM32F7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* This driver does not use enhanced descriptors. Enhanced descriptors must @@ -178,8 +178,8 @@ * supported. */ -#undef CONFIG_STM32F7_ETH_ENHANCEDDESC -#undef CONFIG_STM32F7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_ENHANCEDDESC +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -189,8 +189,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32F7_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32F7_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -207,16 +207,16 @@ # warning "You using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32F7_ETH_NRXDESC -# define CONFIG_STM32F7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32F7_ETH_NTXDESC -# define CONFIG_STM32F7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32F7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers use for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -231,7 +231,7 @@ #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) -#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -243,21 +243,21 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32F7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -338,7 +338,7 @@ * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_RD Retry disable 1 (disabled) * ETH_MACCR_IPCO IPv4 checksum offload Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_ROD Receive own disable 0 (enabled) * ETH_MACCR_CSD Carrier sense disable 0 (enabled) @@ -353,7 +353,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) #else @@ -471,13 +471,13 @@ * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) * ETH_DMAOMR_TSF Transmit store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_DMAOMR_DFRF Disable flushing of 0 (enabled) * received frames * ETH_DMAOMR_RSF Receive store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on - * error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM + * error frames disable CONFIG_STM32_ETH_HWCHECKSUM * * When the checksum offload feature is enabled, we need to enable the Store * and Forward mode: the store and forward guarantee that a whole frame is @@ -485,7 +485,7 @@ * checksum is OK the DMA can handle the frame otherwise the frame is dropped */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define DMAOMR_SET_MASK \ (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) @@ -525,7 +525,7 @@ * ETH_DMABMR_DA DMA Arbitration 0 (round robin) * ETH_DMABMR_DSL Descriptor skip length 0 * ETH_DMABMR_EDFE Enhanced descriptor Depends on - * format enable CONFIG_STM32F7_ETH_ENHANCEDDESC + * format enable CONFIG_STM32_ETH_ENHANCEDDESC * ETH_DMABMR_PBL Programmable burst length 32 beats * ETH_DMABMR_RTPR RX TX priority ratio 2:1 * ETH_DMABMR_FB Fixed burst 1 (enabled) @@ -536,7 +536,7 @@ * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC # define DMABMR_SET_MASK \ (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) @@ -659,7 +659,7 @@ static uint8_t g_txbuffer[TXBUFFER_ALLOC] /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -667,7 +667,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -754,10 +754,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv); /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -787,7 +787,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -859,7 +859,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -886,7 +886,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1210,7 +1210,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * un-stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMAINT_RI); } @@ -1284,7 +1284,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || @@ -1353,7 +1353,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && @@ -1582,8 +1582,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is the first segment in the frame */ @@ -2657,7 +2657,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].txdesc; @@ -2681,7 +2681,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2751,7 +2751,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].rxdesc; @@ -2773,7 +2773,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2863,7 +2863,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32F7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3070,7 +3070,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3090,7 +3090,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3128,7 +3128,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3149,7 +3149,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_RESET); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3160,7 +3160,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform any necessary, board-specific PHY initialization */ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT ret = stm32_phy_boardinitialize(0); if (ret < 0) { @@ -3181,12 +3181,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3208,7 +3208,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3219,7 +3219,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3241,7 +3241,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, CONFIG_STM32F7_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3250,38 +3250,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. - * IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that + * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for example, * with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32F7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32F7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32F7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3294,13 +3294,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32F7_PHYSR_MODE) == - CONFIG_STM32F7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32F7_PHYSR_SPEED) == CONFIG_STM32F7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3309,14 +3309,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, phyval); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3327,10 +3327,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3356,7 +3356,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3381,7 +3381,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3412,7 +3412,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32F7_MII) || defined(CONFIG_STM32F7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ @@ -3421,7 +3421,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -# if defined(CONFIG_STM32F7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3436,7 +3436,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3444,7 +3444,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3452,7 +3452,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3483,7 +3483,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32F7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3498,7 +3498,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3506,7 +3506,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3514,7 +3514,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3538,7 +3538,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -3861,12 +3861,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list: Chain Mode */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32F7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list: Chain Mode */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32F7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Enable normal MAC operation */ @@ -3899,7 +3899,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) static inline #endif int stm32_ethinitialize(int intf) @@ -3912,7 +3912,7 @@ int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32F7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -3973,7 +3973,7 @@ int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -3988,11 +3988,11 @@ int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32F7_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index 26d0e98ab891f..c23f2dcd21717 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32F7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32F7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32F7_PHYINIT is defined in the + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the * configuration then the board specific logic must provide * stm32_phyinitialize(); The STM32 Ethernet driver will call this * function one time before it first uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32F7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 39f3c0a943d18..4081d9cba2404 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Types @@ -376,4 +376,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_fmc.c b/arch/arm/src/stm32f7/stm32_fmc.c index 03eaea6826d45..d5e955133a487 100644 --- a/arch/arm/src/stm32f7/stm32_fmc.c +++ b/arch/arm/src/stm32f7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F7_FMC) +#if defined(CONFIG_STM32_FMC) #include #include @@ -234,4 +234,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(val, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32F7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index cddddee17d64d..9a3e4e3e17cdd 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -45,7 +45,7 @@ #include #include -#include "stm32_foc.h" +#include "stm32_foc_m3m4_v1.h" #include "hardware/stm32_dbgmcu.h" @@ -89,22 +89,22 @@ /* PWM lower-half ops and ADC lower-half ops must be enabled */ -#ifndef CONFIG_STM32F7_PWM_LL_OPS +#ifndef CONFIG_STM32_PWM_LL_OPS # error PWM low-level operations interface must be enabled #endif -#ifndef CONFIG_STM32F7_ADC_LL_OPS +#ifndef CONFIG_STM32_ADC_LL_OPS # error ADC low-level operations interface must be enabled #endif /* We don't want start conversion during ADC setup */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV # error ADC startup conversion must be disabled #endif /* We need interface to change ADC sample-time */ -#ifndef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME # error ADC sample-time configuration interface must be enabled #endif @@ -114,35 +114,35 @@ /* FOC0 always use TIMER1 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# if CONFIG_STM32F7_TIM1_MODE != 2 +# if CONFIG_STM32_TIM1_MODE != 2 # error TIM1 must be configured in center-aligned mode 1 # endif -#endif /* CONFIG_STM32F7_FOC_FOC0 */ +#endif /* CONFIG_STM32_FOC_FOC0 */ /* FOC1 always use TIMER8 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# if CONFIG_STM32F7_TIM8_MODE != 2 +# if CONFIG_STM32_TIM8_MODE != 2 # error TIM8 must be configured in center-aligned mode 1 # endif #endif /* The maximum supported number of phases depends on the ADC trigger */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) # if CONFIG_MOTOR_FOC_PHASES > 3 # error max 3 phases supported # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) # if CONFIG_MOTOR_FOC_PHASES > 4 # error max 4 phases supported # endif @@ -158,7 +158,7 @@ /* Only one ADC trigger must be selected */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) && defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) # error Invalid ADC trigger configuration #endif @@ -174,7 +174,7 @@ * V0 for CNTR = 0 */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* FOC ADC trigger on CCR4 **************************************************/ @@ -183,12 +183,12 @@ * - 1 channel for ADC injection sequence trigger (CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif @@ -202,10 +202,10 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) #endif @@ -213,20 +213,20 @@ # define ADC_TRIGGER_OFFSET (1) -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* FOC ADC trigger on TRGO **************************************************/ /* PWM TRGO support must be enabled */ -# ifndef CONFIG_STM32F7_PWM_TRGO +# ifndef CONFIG_STM32_PWM_TRGO # error PWM TRGO support must be enabled # endif @@ -238,12 +238,12 @@ * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif @@ -257,17 +257,17 @@ * TIMx TRGO = (ARR) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # error TIM8 and TRGO trigger not supported for ADC IPv1 #endif -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) # endif @@ -280,28 +280,28 @@ /* Phase current samples for FOC0 */ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC 3 # endif #endif /* Phase current samples for FOC1 */ -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC 3 # endif #endif @@ -316,55 +316,55 @@ * 3. ADC software trigger starts only regular conversion. */ -#ifdef CONFIG_STM32F7_FOC_USE_ADC1 -# ifndef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_FOC_USE_ADC1 +# ifndef CONFIG_STM32_ADC1 # error ADC1 not supported ! # endif # ifndef ADC1_HAVE_JEXTCFG # error ADC1 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC1_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC1_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC1 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC2 -# ifndef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 # error ADC2 not supported ! # endif # ifndef ADC2_HAVE_JEXTCFG # error ADC2 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC2_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC2 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC3 -# ifndef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_FOC_USE_ADC3 +# ifndef CONFIG_STM32_ADC3 # error ADC3 not supported ! # endif # ifndef ADC3_HAVE_JEXTCFG # error ADC3 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC3_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC3_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC3 injected channels # endif #endif /* Combine JEXTSEL with JEXTEN default */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) #endif @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -390,40 +390,40 @@ /* FOC ADC configuration ****************************************************/ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -502,7 +502,7 @@ /* Define PWM all outputs */ -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ STM32_PWM_OUT2N| \ STM32_PWM_OUT3N) @@ -510,7 +510,7 @@ # define PMW_OUTPUTS_ALL_COMP (0) #endif -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) # define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) #else # define PMW_OUTPUTS_ALL_OUT4 (0) @@ -683,10 +683,10 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); static int stm32_foc_calibration_start(struct foc_dev_s *dev); static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, uint32_t offset); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, uint8_t rcr); #else @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ @@ -813,7 +813,7 @@ static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY /* Configure deadtime */ PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); @@ -1015,7 +1015,7 @@ static int stm32_foc_adc_cfg(struct foc_dev_s *dev) return OK; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /**************************************************************************** * Name: stm32_foc_adc_ccr4_trg_set @@ -1047,7 +1047,7 @@ static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); } -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /**************************************************************************** * Name: stm32_foc_adc_trgo_trg_set @@ -1140,9 +1140,9 @@ static int stm32_foc_configure(struct foc_dev_s *dev, DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / priv->data.adc_freq) * 2); #else @@ -1156,7 +1156,7 @@ static int stm32_foc_configure(struct foc_dev_s *dev, /* REVISIT: synchronise instances if TRGO trigger selected */ #if (CONFIG_MOTOR_FOC_INST > 1) -# if defined(CONFIG_STM32F7_FOC_ADC_TRGO) +# if defined(CONFIG_STM32_FOC_ADC_TRGO) # error stm32_foc_sync_all breaks TRGO event on V0 vector # endif @@ -1704,9 +1704,9 @@ static int stm32_foc_calibration_start(struct foc_dev_s *dev) DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, 1); #else # error Invalid FOC ADC trigger @@ -2039,7 +2039,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* ADC interrupts frequency is PWM frequency */ priv->data.adc_freq = dev->cfg.pwm_freq; @@ -2048,7 +2048,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) priv->data.notifier_div = (dev->cfg.pwm_freq / freq); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* Call work on every ADC interrupt */ priv->data.notifier_div = 1; @@ -2250,7 +2250,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) switch (inst) { -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 case 0: { pwm_inst = FOC0_PWM; @@ -2264,7 +2264,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) } #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 case 1: { pwm_inst = FOC1_PWM; diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0033faf47da72..611cf9987fda5 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -60,39 +60,39 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 STM32_GPIOF_BASE, #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 STM32_GPIOG_BASE, #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -134,7 +134,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -409,7 +409,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -449,7 +449,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -502,4 +502,4 @@ void stm32_iocompensation(void) } } -#endif /* CONFIG_STM32F7_STM32F72XX || ... || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F72XX || ... || CONFIG_STM32_STM32F77XX */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index 00fee28b71a14..97fcbc8dfafef 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -240,7 +240,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index e805129f8e877..4c3dc112a8b1b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -155,34 +155,34 @@ * * One of: * - * CONFIG_STM32F7_STM32F72XX - * CONFIG_STM32F7_STM32F73XX - * CONFIG_STM32F7_STM32F74XX - * CONFIG_STM32F7_STM32F75XX - * CONFIG_STM32F7_STM32F76XX - * CONFIG_STM32F7_STM32F77XX + * CONFIG_STM32_STM32F72XX + * CONFIG_STM32_STM32F73XX + * CONFIG_STM32_STM32F74XX + * CONFIG_STM32_STM32F75XX + * CONFIG_STM32_STM32F76XX + * CONFIG_STM32_STM32F77XX * * * and one or more interfaces: * - * CONFIG_STM32F7_I2C1 - * CONFIG_STM32F7_I2C2 - * CONFIG_STM32F7_I2C3 - * CONFIG_STM32F7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -256,8 +256,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \ - defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -265,25 +265,25 @@ #undef INVALID_CLOCK_SOURCE -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 # if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 # if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 # if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -300,25 +300,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 -# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F7_I2CTIMEOTICKS -# define CONFIG_STM32F7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -482,9 +482,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -534,7 +534,7 @@ static const struct i2c_ops_s stm32_i2c_ops = #endif }; -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -571,7 +571,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -608,7 +608,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -645,7 +645,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -766,7 +766,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -783,7 +783,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -839,12 +839,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -882,10 +882,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2740,22 +2740,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2827,5 +2827,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || \ - * CONFIG_STM32F7_I2C3 || CONFIG_STM32F7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h index e9bb1656b2937..4580980d9d4dc 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.h +++ b/arch/arm/src/stm32f7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO -# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index f6f6d0c027208..3aa1ef321d4ee 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -76,7 +76,7 @@ #include "stm32_spi.h" #include "stm32_rcc.h" -#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_I2S1) || defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) /**************************************************************************** * Pre-processor Definitions @@ -92,8 +92,8 @@ # error CONFIG_AUDIO required by this driver #endif -#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT -# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16 +#ifndef CONFIG_STM32_I2S_MAXINFLIGHT +# define CONFIG_STM32_I2S_MAXINFLIGHT 16 #endif /* Assume no RX/TX support until we learn better */ @@ -103,28 +103,28 @@ /* Check for I2S RX support */ -# if defined(CONFIG_STM32F7_I2S1_RX) +# if defined(CONFIG_STM32_I2S1_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_RX) +# if defined(CONFIG_STM32_I2S2_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_RX) +# if defined(CONFIG_STM32_I2S3_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -132,28 +132,28 @@ /* Check for I2S3 TX support */ -# if defined(CONFIG_STM32F7_I2S1_TX) +# if defined(CONFIG_STM32_I2S1_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_TX) +# if defined(CONFIG_STM32_I2S2_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_TX) +# if defined(CONFIG_STM32_I2S3_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -163,19 +163,19 @@ /* I2S interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven I2S not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -200,7 +200,7 @@ # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /* Debug ********************************************************************/ @@ -209,56 +209,56 @@ */ #ifndef CONFIG_DEBUG_I2S_INFO -# undef CONFIG_STM32F7_I2S_DMADEBUG -# undef CONFIG_STM32F7_I2S_REGDEBUG -# undef CONFIG_STM32F7_I2S_QDEBUG -# undef CONFIG_STM32F7_I2S_DUMPBUFFERS +# undef CONFIG_STM32_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_REGDEBUG +# undef CONFIG_STM32_I2S_QDEBUG +# undef CONFIG_STM32_I2S_DUMPBUFFERS #endif /* The I2S can handle most any bit width from 8 to 32. However, the DMA * logic here is constrained to byte, half-word, and word sizes. */ -#ifndef CONFIG_STM32F7_I2S1_DATALEN -# define CONFIG_STM32F7_I2S1_DATALEN 16 +#ifndef CONFIG_STM32_I2S1_DATALEN +# define CONFIG_STM32_I2S1_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S2_DATALEN -# define CONFIG_STM32F7_I2S2_DATALEN 16 +#ifndef CONFIG_STM32_I2S2_DATALEN +# define CONFIG_STM32_I2S2_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S3_DATALEN -# define CONFIG_STM32F7_I2S3_DATALEN 16 +#ifndef CONFIG_STM32_I2S3_DATALEN +# define CONFIG_STM32_I2S3_DATALEN 16 #endif -#if CONFIG_STM32F7_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 -#elif CONFIG_STM32F7_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 -#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN +#if CONFIG_STM32_I2S1_DATALEN == 8 +# define STM32_I2S1_DATAMASK 0 +#elif CONFIG_STM32_I2S1_DATALEN == 16 +# define STM32_I2S1_DATAMASK 1 +#elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S1_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 -#elif CONFIG_STM32F7_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 -#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN +#if CONFIG_STM32_I2S2_DATALEN == 8 +# define STM32_I2S2_DATAMASK 0 +#elif CONFIG_STM32_I2S2_DATALEN == 16 +# define STM32_I2S2_DATAMASK 1 +#elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S2_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 -#elif CONFIG_STM32F7_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 -#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN +#if CONFIG_STM32_I2S3_DATALEN == 8 +# define STM32_I2S3_DATAMASK 0 +#elif CONFIG_STM32_I2S3_DATALEN == 16 +# define STM32_I2S3_DATAMASK 1 +#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S3_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN #endif /* Check if we need to build RX and/or TX support */ @@ -266,7 +266,7 @@ #if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_DMADEBUG #endif #define DMA_INITIAL 0 @@ -309,7 +309,7 @@ struct stm32_transport_s sq_queue_t done; /* A queue of completed transfers */ struct work_s work; /* Supports worker thread operations */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif }; @@ -344,11 +344,11 @@ struct stm32_i2s_s sem_t bufsem; /* Buffer wait semaphore */ struct stm32_buffer_s *freelist; /* A list a free buffer containers */ - struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT]; + struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; /* Debug stuff */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG bool wr; /* Last was a write */ uint32_t regaddr; /* Last address */ uint16_t regval; /* Last value */ @@ -362,7 +362,7 @@ struct stm32_i2s_s /* Register helpers */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr); #else @@ -379,7 +379,7 @@ static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); # define i2s_dump_regs(s,m) #endif -#ifdef CONFIG_STM32F7_I2S_DUMPBUFFERS +#ifdef CONFIG_STM32_I2S_DUMPBUFFERS # define i2s_init_buffer(b,s) memset(b, 0x55, s); # define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) #else @@ -397,12 +397,12 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) # define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) # define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -414,7 +414,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) # define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) # define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -467,15 +467,15 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv); static int i2s_dma_allocate(struct stm32_i2s_s *priv); static void i2s_dma_free(struct stm32_i2s_s *priv); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv); #endif @@ -520,7 +520,7 @@ static const struct i2s_ops_s g_i2sops = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr) { @@ -579,7 +579,7 @@ static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint32_t regaddr = priv->base + offset; uint16_t regval = getreg16(regaddr); -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, false, regval, regaddr)) { i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); @@ -610,7 +610,7 @@ static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, { uint32_t regaddr = priv->base + offset; -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, true, regval, regaddr)) { i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); @@ -759,9 +759,9 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT); + nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) { i2s_buf_free(priv, &priv->containers[i]); } @@ -771,7 +771,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * Name: i2s_dma_sampleinit * * Description: - * Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG) + * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) * * Input Parameters: * priv - I2S state instance @@ -781,7 +781,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) +#if defined(CONFIG_STM32_I2S_DMADEBUG) static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt) { @@ -809,7 +809,7 @@ static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -875,7 +875,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -1145,7 +1145,7 @@ static void i2s_rx_worker(void *arg) if (sq_empty(&priv->rx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); if (bfcontainer) { @@ -1543,7 +1543,7 @@ static void i2s_tx_worker(void *arg) if (sq_empty(&priv->tx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); if (bfcontainer) { @@ -2441,7 +2441,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2450,7 +2450,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S1_BASE; -#ifdef CONFIG_STM32F7_I2S1_RX +#ifdef CONFIG_STM32_I2S1_RX priv->rxenab = true; if (!priv->initialized) @@ -2463,9 +2463,9 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_RX */ +#endif /* CONFIG_STM32_I2S1_RX */ -#ifdef CONFIG_STM32F7_I2S1_TX +#ifdef CONFIG_STM32_I2S1_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2480,16 +2480,16 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_TX */ +#endif /* CONFIG_STM32_I2S1_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; + priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S1 */ +#endif /* CONFIG_STM32_I2S1 */ /**************************************************************************** * Name: i2s2_configure @@ -2506,7 +2506,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2515,7 +2515,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S2_BASE; -#ifdef CONFIG_STM32F7_I2S2_RX +#ifdef CONFIG_STM32_I2S2_RX priv->rxenab = true; if (!priv->initialized) @@ -2528,9 +2528,9 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_RX */ +#endif /* CONFIG_STM32_I2S2_RX */ -#ifdef CONFIG_STM32F7_I2S2_TX +#ifdef CONFIG_STM32_I2S2_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2545,16 +2545,16 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_TX */ +#endif /* CONFIG_STM32_I2S2_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; + priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S2 */ +#endif /* CONFIG_STM32_I2S2 */ /**************************************************************************** * Name: i2s3_configure @@ -2571,7 +2571,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2580,7 +2580,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S3_BASE; -#ifdef CONFIG_STM32F7_I2S3_RX +#ifdef CONFIG_STM32_I2S3_RX priv->rxenab = true; if (!priv->initialized) @@ -2593,9 +2593,9 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_RX */ +#endif /* CONFIG_STM32_I2S3_RX */ -#ifdef CONFIG_STM32F7_I2S3_TX +#ifdef CONFIG_STM32_I2S3_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2610,16 +2610,16 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_TX */ +#endif /* CONFIG_STM32_I2S3_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; + priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S3 */ /**************************************************************************** * Public Functions @@ -2677,7 +2677,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 if (port == 1) { /* Select I2S1 */ @@ -2686,7 +2686,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 if (port == 2) { /* Select I2S2 */ @@ -2695,7 +2695,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 if (port == 3) { /* Select I2S3 */ @@ -2736,4 +2736,4 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } #endif /* I2S_HAVE_RX || I2S_HAVE_TX */ -#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S1 || CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 0d7080377e8cf..5b768bb9bcdf8 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -40,7 +40,7 @@ #include "ram_vectors.h" #include "arm_internal.h" -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ # include "stm32_gpio.h" #endif @@ -402,7 +402,7 @@ void up_irqinitialize(void) * GPIO pins. */ -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ stm32_gpioirqinitialize(); #endif @@ -446,7 +446,7 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ @@ -493,7 +493,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32F7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ diff --git a/arch/arm/src/stm32f7/stm32_lse.c b/arch/arm/src/stm32f7/stm32_lse.c index 10846796bba52..ecc5b01ca3d55 100644 --- a/arch/arm/src/stm32f7/stm32_lse.c +++ b/arch/arm/src/stm32f7/stm32_lse.c @@ -41,16 +41,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -59,7 +59,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -85,7 +85,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -109,17 +109,17 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable on. */ regval &= ~(RCC_BDCR_LSEDRV_MASK); - regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -153,13 +153,13 @@ void stm32_rcc_enablelse(void) } while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index c7f1aff78d63c..e33dd053ee37f 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -129,8 +129,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32F7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32F7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -138,23 +138,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32F7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -165,24 +165,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32F7_LTDC_L2 -# if defined(CONFIG_STM32F7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -190,7 +190,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -212,37 +212,37 @@ #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifndef CONFIG_STM32F7_LTDC_L2_WIDTH -# define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH +#ifdef CONFIG_STM32_LTDC_L2 +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif -# if CONFIG_STM32F7_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH # error Width of Layer 2 exceeds the width of the display # endif -# ifndef CONFIG_STM32F7_LTDC_L2_HEIGHT -# define CONFIG_STM32F7_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT # endif -# if CONFIG_STM32F7_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT # error Height of Layer 2 exceeds the height of the display # endif # if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32F7_LTDC_L2_WIDTH) +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) # elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 16 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) # elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 24 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) # elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32F7_LTDC_L2_WIDTH * 32 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) # else # error Undefined or unrecognized base resolution # endif # define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32F7_LTDC_L2_HEIGHT) + CONFIG_STM32_LTDC_L2_HEIGHT) #else # define STM32_LTDC_L2_FBSIZE (0) @@ -256,7 +256,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -271,10 +271,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32F7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32F7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -287,7 +287,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -297,7 +297,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -305,27 +305,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32F7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32F7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32F7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32F7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32F7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -333,63 +333,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32F7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32F7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32F7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32F7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32F7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32F7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32F7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32F7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32F7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32F7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32F7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32F7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifdef CONFIG_STM32F7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32F7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -423,28 +423,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32F7_DMA2D -# if defined(CONFIG_STM32F7_LTDC_L1_L8) || \ - defined(CONFIG_STM32F7_LTDC_L2_L8) -# if !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32F7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32F7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -452,12 +452,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32F7_FB_CMAP -# if defined(CONFIG_STM32F7_DMA2D) && !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -465,7 +465,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -473,7 +473,7 @@ # endif #endif -#ifndef CONFIG_STM32F7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -510,9 +510,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32F7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -520,9 +520,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -530,34 +530,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -579,7 +579,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -612,7 +612,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -637,7 +637,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -645,7 +645,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -693,7 +693,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -702,7 +702,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -725,7 +725,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -795,16 +795,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC mutex that enforces mutually exclusive access */ @@ -836,7 +836,7 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -857,7 +857,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -895,9 +895,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -905,7 +905,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -941,7 +941,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -953,7 +953,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -985,7 +985,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1007,7 +1007,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1017,7 +1017,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1027,7 +1027,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1037,7 +1037,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1047,7 +1047,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1057,7 +1057,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1067,7 +1067,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1077,7 +1077,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1087,7 +1087,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1097,7 +1097,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1109,7 +1109,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1119,7 +1119,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1129,7 +1129,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1139,7 +1139,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1149,7 +1149,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1159,7 +1159,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1169,7 +1169,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1179,7 +1179,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1189,7 +1189,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1199,7 +1199,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1209,22 +1209,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1648,7 +1648,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32F7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1920,7 +1920,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -1990,7 +1990,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { @@ -2095,7 +2095,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2104,7 +2104,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2112,7 +2112,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2155,7 +2155,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2215,7 +2215,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2255,7 +2255,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2291,7 +2291,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2378,7 +2378,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2408,7 +2408,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2478,7 +2478,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2498,7 +2498,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2589,7 +2589,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2636,14 +2636,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2651,7 +2651,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxmutex_lock(layer->lock); -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2671,7 +2671,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxmutex_unlock(layer->lock); return ret; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2699,7 +2699,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2760,7 +2760,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = @@ -2830,7 +2830,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2892,7 +2892,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3006,7 +3006,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3022,31 +3022,31 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT stm32_backlight(true); #endif @@ -3132,10 +3132,10 @@ void stm32_ltdcuninitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32F7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32f7/stm32_ltdc.h b/arch/arm/src/stm32f7/stm32_ltdc.h index d7a432a01cdac..420be63b38599 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.h +++ b/arch/arm/src/stm32f7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index a0d5426727863..9b146f21e61da 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS) /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT #endif -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE # define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ @@ -58,7 +58,7 @@ # define STM32_OTG_FIFO_SIZE 1280 #endif -#if defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFSHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE # define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ @@ -135,5 +135,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 7a1fe72b80c97..96be757e9e3f9 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -52,8 +52,8 @@ #include "stm32_rcc.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ - defined(CONFIG_STM32F7_OTGFSHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGFSHS)) /**************************************************************************** * Pre-processor Definitions @@ -254,7 +254,7 @@ * present */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS # define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS # else @@ -373,7 +373,7 @@ /* Maximum packet sizes for full speed endpoints */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define STM32_MAXPACKET (512) /* Max packet size (1-512) */ # else # define STM32_MAXPACKET (64) /* Max packet size (1-64) */ @@ -573,7 +573,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); # else @@ -898,7 +898,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -961,7 +961,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2163,7 +2163,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -3461,7 +3461,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_GUSBCFG_TRDT(9); # else regval |= OTG_GUSBCFG_TRDT(6); @@ -5345,15 +5345,15 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS -# ifdef CONFIG_STM32F7_NO_ULPI +# ifdef CONFIG_STM32_NO_ULPI regval = stm32_getreg(STM32_OTG_GUSBCFG); regval |= OTG_GUSBCFG_PHYSEL; stm32_putreg(regval, STM32_OTG_GUSBCFG); -# else /* CONFIG_STM32F7_NO_ULPI */ +# else /* CONFIG_STM32_NO_ULPI */ /* Switch off FS transceiver */ @@ -5376,7 +5376,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); stm32_putreg(regval, STM32_OTG_GUSBCFG); -# ifdef CONFIG_STM32F7_INTERNAL_ULPI +# ifdef CONFIG_STM32_INTERNAL_ULPI /* Select UTMI/ULPI Interface */ @@ -5421,9 +5421,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) up_udelay(2000); -# endif /* CONFIG_STM32F7_INTERNAL_ULPI */ -# endif /* CONFIG_STM32F7_NO_ULPI */ -# endif /* CONFIG_STM32F7_OTGFSHS */ +# endif /* CONFIG_STM32_INTERNAL_ULPI */ +# endif /* CONFIG_STM32_NO_ULPI */ +# endif /* CONFIG_STM32_OTGFSHS */ /* Common USB OTG core initialization */ @@ -5465,7 +5465,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI)) +# if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_NO_ULPI)) regval |= OTG_GCCFG_PWRDWN; # endif @@ -5509,7 +5509,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_DCFG_DSPD_HS; # else regval |= OTG_DCFG_DSPD_FS; @@ -5652,7 +5652,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) +# if defined(CONFIG_STM32_OTGFSHS) && defined(CONFIG_STM32_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done * because if both the ULPI and the FS PHY clock enable bits are set at the * same time, the ARM never awakens from WFI due to some bug / errata in @@ -5747,7 +5747,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5919,7 +5919,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) */ stm32_pullup(&priv->usbdev, true); -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -5991,4 +5991,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 69681d2479b37..d66c084a888fe 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -73,61 +73,61 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32F7_SYSCFG_IOCOMPENSATION - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG_IOCOMPENSATION - Needed * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION -# error "CONFIG_STM32F7_SYSCFG_IOCOMPENSATION is required" +#ifndef CONFIG_STM32_SYSCFG_IOCOMPENSATION +# error "CONFIG_STM32_SYSCFG_IOCOMPENSATION is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32F7_OTG_RXFIFO_SIZE -# define CONFIG_STM32F7_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32F7_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32F7_OTG_PTXFIFO_SIZE -# define CONFIG_STM32F7_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32F7_OTG_DESCSIZE -# define CONFIG_STM32F7_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32F7_USBHOST_REGDEBUG -# undef CONFIG_STM32F7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -272,7 +272,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -285,7 +285,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -380,7 +380,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); @@ -496,7 +496,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -511,7 +511,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -575,7 +575,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -597,7 +597,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -2987,7 +2987,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3555,7 +3555,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3721,7 +3721,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32F7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4245,7 +4245,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32F7_OTG_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4254,7 +4254,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32F7_OTG_DESCSIZE; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; return OK; } @@ -5121,21 +5121,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32F7_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32F7_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_NPTXFIFO_SIZE << + (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32F7_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32F7_OTG_PTXFIFO_SIZE << + (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); @@ -5407,7 +5407,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5433,4 +5433,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.c b/arch/arm/src/stm32f7/stm32_pulsecount.c index ed0a19ae07992..664dd33dabd54 100644 --- a/arch/arm/src/stm32f7/stm32_pulsecount.c +++ b/arch/arm/src/stm32f7/stm32_pulsecount.c @@ -173,10 +173,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -203,107 +203,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32F7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32F7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -314,7 +314,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -322,7 +322,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1303,21 +1303,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1390,7 +1390,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1399,7 +1399,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1717,7 +1717,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1727,7 +1727,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index 66f1f90ca68bf..1494220031ae0 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -42,7 +42,7 @@ #include "stm32_rcc.h" #include "stm32_gpio.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ /* Advanced Timer support */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -157,14 +157,14 @@ /* TRGO/TRGO2 support */ -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32F7_TIM1_BREAK1) || defined(CONFIG_STM32F7_TIM1_BREAK2) || \ - defined(CONFIG_STM32F7_TIM8_BREAK1) || defined(CONFIG_STM32F7_TIM8_BREAK2) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) # defined HAVE_BREAK #endif @@ -225,7 +225,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -298,10 +298,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); #endif @@ -342,7 +342,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -372,138 +372,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM1_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1POL, - .idle = CONFIG_STM32F7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1NPOL, - .idle = CONFIG_STM32F7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM1_CH2MODE, -#ifdef CONFIG_STM32F7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2POL, - .idle = CONFIG_STM32F7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2NPOL, - .idle = CONFIG_STM32F7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM1_CH3MODE, -#ifdef CONFIG_STM32F7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3POL, - .idle = CONFIG_STM32F7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3NPOL, - .idle = CONFIG_STM32F7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM1_CH4MODE, -#ifdef CONFIG_STM32F7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH4POL, - .idle = CONFIG_STM32F7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM1_CH5MODE, -#ifdef CONFIG_STM32F7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH5POL, - .idle = CONFIG_STM32F7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM1_CH6MODE, -#ifdef CONFIG_STM32F7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH6POL, - .idle = CONFIG_STM32F7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -514,18 +514,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F7_TIM1_MODE, - .lock = CONFIG_STM32F7_TIM1_LOCK, - .t_dts = CONFIG_STM32F7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -533,72 +533,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM2_CH1MODE, -#ifdef CONFIG_STM32F7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH1POL, - .idle = CONFIG_STM32F7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM2_CH2MODE, -#ifdef CONFIG_STM32F7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH2POL, - .idle = CONFIG_STM32F7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM2_CH3MODE, -#ifdef CONFIG_STM32F7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH3POL, - .idle = CONFIG_STM32F7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM2_CH4MODE, -#ifdef CONFIG_STM32F7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH4POL, - .idle = CONFIG_STM32F7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -610,14 +610,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -629,72 +629,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32F7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM3_CH1MODE, -#ifdef CONFIG_STM32F7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH1POL, - .idle = CONFIG_STM32F7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM3_CH2MODE, -#ifdef CONFIG_STM32F7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH2POL, - .idle = CONFIG_STM32F7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM3_CH3MODE, -#ifdef CONFIG_STM32F7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH3POL, - .idle = CONFIG_STM32F7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM3_CH4MODE, -#ifdef CONFIG_STM32F7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH4POL, - .idle = CONFIG_STM32F7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -706,14 +706,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -725,72 +725,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32F7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM4_CH1MODE, -#ifdef CONFIG_STM32F7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH1POL, - .idle = CONFIG_STM32F7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM4_CH2MODE, -#ifdef CONFIG_STM32F7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH2POL, - .idle = CONFIG_STM32F7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM4_CH3MODE, -#ifdef CONFIG_STM32F7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH3POL, - .idle = CONFIG_STM32F7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM4_CH4MODE, -#ifdef CONFIG_STM32F7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH4POL, - .idle = CONFIG_STM32F7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -802,14 +802,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32F7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -821,71 +821,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32F7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM5_CH1MODE, -#ifdef CONFIG_STM32F7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH1POL, - .idle = CONFIG_STM32F7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM5_CH2MODE, -#ifdef CONFIG_STM32F7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH2POL, - .idle = CONFIG_STM32F7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM5_CH3MODE, -#ifdef CONFIG_STM32F7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH3POL, - .idle = CONFIG_STM32F7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM5_CH4MODE, -#ifdef CONFIG_STM32F7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH4POL, - .idle = CONFIG_STM32F7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -896,14 +896,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32F7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -915,140 +915,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32F7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32F7_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32F7_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32F7_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32F7_TIM8_BRK2POL, - .flt2 = CONFIG_STM32F7_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1POL, - .idle = CONFIG_STM32F7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1NPOL, - .idle = CONFIG_STM32F7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM8_CH2MODE, -#ifdef CONFIG_STM32F7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2POL, - .idle = CONFIG_STM32F7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2NPOL, - .idle = CONFIG_STM32F7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM8_CH3MODE, -#ifdef CONFIG_STM32F7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3POL, - .idle = CONFIG_STM32F7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3NPOL, - .idle = CONFIG_STM32F7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM8_CH4MODE, -#ifdef CONFIG_STM32F7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH4POL, - .idle = CONFIG_STM32F7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM8_CH5MODE, -#ifdef CONFIG_STM32F7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH5POL, - .idle = CONFIG_STM32F7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM8_CH6MODE, -#ifdef CONFIG_STM32F7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH6POL, - .idle = CONFIG_STM32F7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1059,18 +1059,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32F7_TIM8_MODE, - .lock = CONFIG_STM32F7_TIM8_LOCK, - .t_dts = CONFIG_STM32F7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1078,40 +1078,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmchan_s g_pwm9channels[] = { /* TIM9 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM9_CH1MODE, -#ifdef CONFIG_STM32F7_TIM9_CH1OUT + .mode = CONFIG_STM32_TIM9_CH1MODE, +#ifdef CONFIG_STM32_TIM9_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH1POL, - .idle = CONFIG_STM32F7_TIM9_CH1IDLE, + .pol = CONFIG_STM32_TIM9_CH1POL, + .idle = CONFIG_STM32_TIM9_CH1IDLE, .pincfg = PWM_TIM9_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM9_CH2MODE, -#ifdef CONFIG_STM32F7_TIM9_CH2OUT + .mode = CONFIG_STM32_TIM9_CH2MODE, +#ifdef CONFIG_STM32_TIM9_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH2POL, - .idle = CONFIG_STM32F7_TIM9_CH2IDLE, + .pol = CONFIG_STM32_TIM9_CH2POL, + .idle = CONFIG_STM32_TIM9_CH2IDLE, .pincfg = PWM_TIM9_CH2CFG, } #endif @@ -1123,7 +1123,7 @@ static struct stm32_pwmchan_s g_pwm9channels[] = static struct stm32_pwmtimer_s g_pwm9dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 9, @@ -1142,24 +1142,24 @@ static struct stm32_pwmtimer_s g_pwm9dev = .base = STM32_TIM9_BASE, .pclk = TIMCLK_TIM9, }; -#endif /* CONFIG_STM32F7_TIM9_PWM */ +#endif /* CONFIG_STM32_TIM9_PWM */ -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmchan_s g_pwm10channels[] = { /* TIM10 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM10_CH1MODE, -#ifdef CONFIG_STM32F7_TIM10_CH1OUT + .mode = CONFIG_STM32_TIM10_CH1MODE, +#ifdef CONFIG_STM32_TIM10_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM10_CH1POL, - .idle = CONFIG_STM32F7_TIM10_CH1IDLE, + .pol = CONFIG_STM32_TIM10_CH1POL, + .idle = CONFIG_STM32_TIM10_CH1IDLE, .pincfg = PWM_TIM10_CH1CFG, } #endif @@ -1171,7 +1171,7 @@ static struct stm32_pwmchan_s g_pwm10channels[] = static struct stm32_pwmtimer_s g_pwm10dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 10, @@ -1190,24 +1190,24 @@ static struct stm32_pwmtimer_s g_pwm10dev = .base = STM32_TIM10_BASE, .pclk = TIMCLK_TIM10, }; -#endif /* CONFIG_STM32F7_TIM10_PWM */ +#endif /* CONFIG_STM32_TIM10_PWM */ -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmchan_s g_pwm11channels[] = { /* TIM11 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM11_CH1MODE, -#ifdef CONFIG_STM32F7_TIM11_CH1OUT + .mode = CONFIG_STM32_TIM11_CH1MODE, +#ifdef CONFIG_STM32_TIM11_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM11_CH1POL, - .idle = CONFIG_STM32F7_TIM11_CH1IDLE, + .pol = CONFIG_STM32_TIM11_CH1POL, + .idle = CONFIG_STM32_TIM11_CH1IDLE, .pincfg = PWM_TIM11_CH1CFG, } #endif @@ -1219,7 +1219,7 @@ static struct stm32_pwmchan_s g_pwm11channels[] = static struct stm32_pwmtimer_s g_pwm11dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 11, @@ -1238,40 +1238,40 @@ static struct stm32_pwmtimer_s g_pwm11dev = .base = STM32_TIM11_BASE, .pclk = TIMCLK_TIM11, }; -#endif /* CONFIG_STM32F7_TIM11_PWM */ +#endif /* CONFIG_STM32_TIM11_PWM */ -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM12_CH1MODE, -#ifdef CONFIG_STM32F7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH1POL, - .idle = CONFIG_STM32F7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM12_CH2MODE, -#ifdef CONFIG_STM32F7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH2POL, - .idle = CONFIG_STM32F7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1283,7 +1283,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1302,24 +1302,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32F7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM13_CH1MODE, -#ifdef CONFIG_STM32F7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM13_CH1POL, - .idle = CONFIG_STM32F7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1331,7 +1331,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1350,24 +1350,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32F7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM14_CH1MODE, -#ifdef CONFIG_STM32F7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM14_CH1POL, - .idle = CONFIG_STM32F7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1379,7 +1379,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1398,7 +1398,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32F7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ /**************************************************************************** * Private Functions @@ -1698,7 +1698,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1753,7 +1753,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1798,7 +1798,7 @@ static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) } #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /**************************************************************************** * Name: pwm_rcr_get ****************************************************************************/ @@ -2486,7 +2486,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3033,7 +3033,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3042,7 +3042,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3051,7 +3051,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3060,7 +3060,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3069,7 +3069,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3078,7 +3078,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3087,7 +3087,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { regaddr = TIMRCCEN_TIM9; @@ -3096,7 +3096,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { regaddr = TIMRCCEN_TIM10; @@ -3105,7 +3105,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { regaddr = TIMRCCEN_TIM11; @@ -3114,7 +3114,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3123,7 +3123,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3132,7 +3132,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3520,7 +3520,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3531,7 +3531,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3539,7 +3539,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3547,7 +3547,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3555,7 +3555,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3563,7 +3563,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3574,7 +3574,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { lower = &g_pwm9dev; @@ -3582,7 +3582,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { lower = &g_pwm10dev; @@ -3591,7 +3591,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { lower = &g_pwm11dev; @@ -3599,7 +3599,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3607,7 +3607,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3615,7 +3615,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3635,4 +3635,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 06a7671301ab8..0aa3aed6d7143 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32F7_TIM9 -# undef CONFIG_STM32F7_TIM9_PWM +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_PWM #endif -#ifndef CONFIG_STM32F7_TIM10 -# undef CONFIG_STM32F7_TIM10_PWM +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_PWM #endif -#ifndef CONFIG_STM32F7_TIM11 -# undef CONFIG_STM32F7_TIM11_PWM +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_PWM #endif -#ifndef CONFIG_STM32F7_TIM12 -# undef CONFIG_STM32F7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32F7_TIM13 -# undef CONFIG_STM32F7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32F7_TIM14 -# undef CONFIG_STM32F7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32F7_TIM6_PWM -#undef CONFIG_STM32F7_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32F7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 # define PWM_TIM9_CHANNEL1 1 #else # define PWM_TIM9_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 # define PWM_TIM9_CHANNEL2 1 #else # define PWM_TIM9_CHANNEL2 0 #endif #define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 # define PWM_TIM10_CHANNEL1 1 #else # define PWM_TIM10_CHANNEL1 0 #endif #define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 # define PWM_TIM11_CHANNEL1 1 #else # define PWM_TIM11_CHANNEL1 0 #endif #define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. In the * case where there are multiple pin selections, the correct setting must be * provided in the arch/board/board.h file. @@ -336,410 +336,410 @@ * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F7_TIM1_PWM -# if !defined(CONFIG_STM32F7_TIM1_CHANNEL) -# error "CONFIG_STM32F7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM1_CHANNEL == 1 -# define CONFIG_STM32F7_TIM1_CHANNEL1 1 -# define CONFIG_STM32F7_TIM1_CH1MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 2 -# define CONFIG_STM32F7_TIM1_CHANNEL2 1 -# define CONFIG_STM32F7_TIM1_CH2MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 3 -# define CONFIG_STM32F7_TIM1_CHANNEL3 1 -# define CONFIG_STM32F7_TIM1_CH3MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 4 -# define CONFIG_STM32F7_TIM1_CHANNEL4 1 -# define CONFIG_STM32F7_TIM1_CH4MODE CONFIG_STM32F7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM2_PWM -# if !defined(CONFIG_STM32F7_TIM2_CHANNEL) -# error "CONFIG_STM32F7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM2_CHANNEL == 1 -# define CONFIG_STM32F7_TIM2_CHANNEL1 1 -# define CONFIG_STM32F7_TIM2_CH1MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 2 -# define CONFIG_STM32F7_TIM2_CHANNEL2 1 -# define CONFIG_STM32F7_TIM2_CH2MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 3 -# define CONFIG_STM32F7_TIM2_CHANNEL3 1 -# define CONFIG_STM32F7_TIM2_CH3MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 4 -# define CONFIG_STM32F7_TIM2_CHANNEL4 1 -# define CONFIG_STM32F7_TIM2_CH4MODE CONFIG_STM32F7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM3_PWM -# if !defined(CONFIG_STM32F7_TIM3_CHANNEL) -# error "CONFIG_STM32F7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM3_CHANNEL == 1 -# define CONFIG_STM32F7_TIM3_CHANNEL1 1 -# define CONFIG_STM32F7_TIM3_CH1MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 2 -# define CONFIG_STM32F7_TIM3_CHANNEL2 1 -# define CONFIG_STM32F7_TIM3_CH2MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 3 -# define CONFIG_STM32F7_TIM3_CHANNEL3 1 -# define CONFIG_STM32F7_TIM3_CH3MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 4 -# define CONFIG_STM32F7_TIM3_CHANNEL4 1 -# define CONFIG_STM32F7_TIM3_CH4MODE CONFIG_STM32F7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM4_PWM -# if !defined(CONFIG_STM32F7_TIM4_CHANNEL) -# error "CONFIG_STM32F7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM4_CHANNEL == 1 -# define CONFIG_STM32F7_TIM4_CHANNEL1 1 -# define CONFIG_STM32F7_TIM4_CH1MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 2 -# define CONFIG_STM32F7_TIM4_CHANNEL2 1 -# define CONFIG_STM32F7_TIM4_CH2MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 3 -# define CONFIG_STM32F7_TIM4_CHANNEL3 1 -# define CONFIG_STM32F7_TIM4_CH3MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 4 -# define CONFIG_STM32F7_TIM4_CHANNEL4 1 -# define CONFIG_STM32F7_TIM4_CH4MODE CONFIG_STM32F7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM5_PWM -# if !defined(CONFIG_STM32F7_TIM5_CHANNEL) -# error "CONFIG_STM32F7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM5_CHANNEL == 1 -# define CONFIG_STM32F7_TIM5_CHANNEL1 1 -# define CONFIG_STM32F7_TIM5_CH1MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 2 -# define CONFIG_STM32F7_TIM5_CHANNEL2 1 -# define CONFIG_STM32F7_TIM5_CH2MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 3 -# define CONFIG_STM32F7_TIM5_CHANNEL3 1 -# define CONFIG_STM32F7_TIM5_CH3MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 4 -# define CONFIG_STM32F7_TIM5_CHANNEL4 1 -# define CONFIG_STM32F7_TIM5_CH4MODE CONFIG_STM32F7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM8_PWM -# if !defined(CONFIG_STM32F7_TIM8_CHANNEL) -# error "CONFIG_STM32F7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM8_CHANNEL == 1 -# define CONFIG_STM32F7_TIM8_CHANNEL1 1 -# define CONFIG_STM32F7_TIM8_CH1MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 2 -# define CONFIG_STM32F7_TIM8_CHANNEL2 1 -# define CONFIG_STM32F7_TIM8_CH2MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 3 -# define CONFIG_STM32F7_TIM8_CHANNEL3 1 -# define CONFIG_STM32F7_TIM8_CH3MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 4 -# define CONFIG_STM32F7_TIM8_CHANNEL4 1 -# define CONFIG_STM32F7_TIM8_CH4MODE CONFIG_STM32F7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM9_PWM -# if !defined(CONFIG_STM32F7_TIM9_CHANNEL) -# error "CONFIG_STM32F7_TIM9_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM9_CHANNEL == 1 -# define CONFIG_STM32F7_TIM9_CHANNEL1 1 -# define CONFIG_STM32F7_TIM9_CH1MODE CONFIG_STM32F7_TIM9_CHMODE -# elif CONFIG_STM32F7_TIM9_CHANNEL == 2 -# define CONFIG_STM32F7_TIM9_CHANNEL2 1 -# define CONFIG_STM32F7_TIM9_CH2MODE CONFIG_STM32F7_TIM9_CHMODE +#ifdef CONFIG_STM32_TIM9_PWM +# if !defined(CONFIG_STM32_TIM9_CHANNEL) +# error "CONFIG_STM32_TIM9_CHANNEL must be provided" +# elif CONFIG_STM32_TIM9_CHANNEL == 1 +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# elif CONFIG_STM32_TIM9_CHANNEL == 2 +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif # define PWM_TIM9_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM10_PWM -# if !defined(CONFIG_STM32F7_TIM10_CHANNEL) -# error "CONFIG_STM32F7_TIM10_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM10_CHANNEL == 1 -# define CONFIG_STM32F7_TIM10_CHANNEL1 1 -# define CONFIG_STM32F7_TIM10_CH1MODE CONFIG_STM32F7_TIM10_CHMODE +#ifdef CONFIG_STM32_TIM10_PWM +# if !defined(CONFIG_STM32_TIM10_CHANNEL) +# error "CONFIG_STM32_TIM10_CHANNEL must be provided" +# elif CONFIG_STM32_TIM10_CHANNEL == 1 +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif # define PWM_TIM10_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM11_PWM -# if !defined(CONFIG_STM32F7_TIM11_CHANNEL) -# error "CONFIG_STM32F7_TIM11_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM11_CHANNEL == 1 -# define CONFIG_STM32F7_TIM11_CHANNEL1 1 -# define CONFIG_STM32F7_TIM11_CH1MODE CONFIG_STM32F7_TIM11_CHMODE +#ifdef CONFIG_STM32_TIM11_PWM +# if !defined(CONFIG_STM32_TIM11_CHANNEL) +# error "CONFIG_STM32_TIM11_CHANNEL must be provided" +# elif CONFIG_STM32_TIM11_CHANNEL == 1 +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif # define PWM_TIM11_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM12_PWM -# if !defined(CONFIG_STM32F7_TIM12_CHANNEL) -# error "CONFIG_STM32F7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM12_CHANNEL == 1 -# define CONFIG_STM32F7_TIM12_CHANNEL1 1 -# define CONFIG_STM32F7_TIM12_CH1MODE CONFIG_STM32F7_TIM12_CHMODE -# elif CONFIG_STM32F7_TIM12_CHANNEL == 2 -# define CONFIG_STM32F7_TIM12_CHANNEL2 1 -# define CONFIG_STM32F7_TIM12_CH2MODE CONFIG_STM32F7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM13_PWM -# if !defined(CONFIG_STM32F7_TIM13_CHANNEL) -# error "CONFIG_STM32F7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM13_CHANNEL == 1 -# define CONFIG_STM32F7_TIM13_CHANNEL1 1 -# define CONFIG_STM32F7_TIM13_CH1MODE CONFIG_STM32F7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM14_PWM -# if !defined(CONFIG_STM32F7_TIM14_CHANNEL) -# error "CONFIG_STM32F7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM14_CHANNEL == 1 -# define CONFIG_STM32F7_TIM14_CHANNEL1 1 -# define CONFIG_STM32F7_TIM14_CH1MODE CONFIG_STM32F7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#endif /* CONFIG_STM32F7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH1OUT +#ifdef CONFIG_STM32_TIM9_CH1OUT # define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT #else # define PWM_TIM9_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH2OUT +#ifdef CONFIG_STM32_TIM9_CH2OUT # define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT #else # define PWM_TIM9_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM10_CH1OUT +#ifdef CONFIG_STM32_TIM10_CH1OUT # define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT #else # define PWM_TIM10_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM11_CH1OUT +#ifdef CONFIG_STM32_TIM11_CH1OUT # define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT #else # define PWM_TIM11_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 @@ -747,12 +747,12 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined(CONFIG_STM32F7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F7_TIM8_CH1NOUT) || defined(CONFIG_STM32F7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) @@ -761,7 +761,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -786,7 +786,7 @@ (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) #define PWM_RCR_GET(dev) \ (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define PWM_TRGO_SET(dev, trgo) \ (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) #endif @@ -898,7 +898,7 @@ enum stm32_pwm_output_e /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -954,7 +954,7 @@ struct stm32_pwm_ops_s uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO /* Set TRGO/TRGO2 register */ int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); @@ -998,7 +998,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1044,5 +1044,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c index c86b70a247493..5fac63ef0257d 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.c +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -35,7 +35,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index e3afc99eb670c..fdf06b3bb0d4a 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32F7_TIM2_QE) || defined(CONFIG_STM32F7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM3_QE) || \ - defined(CONFIG_STM32F7_TIM4_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F7_QENCODER_FILTER -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32F7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32F7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -943,37 +943,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h index 3531846389ca6..cb0399814da57 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ b/arch/arm/src/stm32f7/stm32_qencoder.h @@ -38,42 +38,42 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F7_TIMn is defined - * then the CONFIG_STM32F7_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder * (at least for the STM32 F7) */ -#undef CONFIG_STM32F7_TIM6_QE -#undef CONFIG_STM32F7_TIM7_QE -#undef CONFIG_STM32F7_TIM9_QE -#undef CONFIG_STM32F7_TIM10_QE -#undef CONFIG_STM32F7_TIM11_QE -#undef CONFIG_STM32F7_TIM12_QE -#undef CONFIG_STM32F7_TIM13_QE -#undef CONFIG_STM32F7_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index a9e46655548cf..7be8093873074 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) && defined(CONFIG_STM32F7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,7 +92,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -104,26 +104,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32F7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32F7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32F7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32F7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -164,14 +164,14 @@ struct stm32f7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -181,11 +181,11 @@ struct stm32f7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32f7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -222,7 +222,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -235,7 +235,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -262,16 +262,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32F7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32f7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32f7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); @@ -281,8 +281,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32F7_QSPI_DMATHRESHOLD -# define CONFIG_STM32F7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -336,13 +336,13 @@ static struct stm32f7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -368,7 +368,7 @@ static struct stm32f7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -420,7 +420,7 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -443,7 +443,7 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -625,7 +625,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -831,7 +831,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -962,7 +962,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1086,7 +1086,7 @@ static void qspi_ccrconfig(struct stm32f7_qspidev_s *priv, } } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1313,7 +1313,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1579,7 +1579,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2011,7 +2011,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2192,7 +2192,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2253,11 +2253,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32F7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2419,18 +2419,18 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32F7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32F7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1) + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2451,10 +2451,10 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32F7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32F7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32F7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2560,7 +2560,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2574,7 +2574,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2608,12 +2608,12 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2679,7 +2679,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2698,7 +2698,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2744,4 +2744,4 @@ void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index 018bf0c117399..9a32fddf891d2 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index 92b4ec75fef6a..3ce0a726002e2 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -63,11 +63,11 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "stm32f72xx73xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "stm32f74xx75xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configurationfile. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -104,14 +104,14 @@ void stm32_clockconfig(void) rcc_reset(); -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); #endif -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -131,7 +131,7 @@ void stm32_clockconfig(void) rcc_enableperipherals(); -#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -151,7 +151,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index b1c7aaefe37fb..a12de0c0471d2 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -124,7 +124,7 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will be + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be * enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * @@ -147,7 +147,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,7 +164,7 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will * be enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * @@ -216,7 +216,7 @@ void stm32_rcc_enablelsi(void); void stm32_rcc_disablelsi(void); -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Name: stm32f7x9_rcc_dsisrcphy * diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c index 7eeb2d4916c6f..10bad1e664e32 100644 --- a/arch/arm/src/stm32f7/stm32_rng.c +++ b/arch/arm/src/stm32f7/stm32_rng.c @@ -40,7 +40,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -329,4 +329,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index c5d1cc56096b3..9e2deaff4a05f 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32F7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32F7_PWR -# error "CONFIG_STM32F7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32F7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h index 91ce504952357..b6130256949f0 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.h +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32F7_RTC_MAGIC) -# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32F7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_REG) -# define CONFIG_STM32F7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32F7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32F7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 3883278b6f33a..c037660ac41da 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -68,7 +68,7 @@ #include "stm32_sai.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32F7_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -86,49 +86,49 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32F7_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32F7_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE -# define CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE (48000) +#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE +# define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE (48000) #endif -#ifndef CONFIG_STM32F7_SAI_DEFAULT_DATALEN -# define CONFIG_STM32F7_SAI_DEFAULT_DATALEN (16) +#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN +# define CONFIG_STM32_SAI_DEFAULT_DATALEN (16) #endif -#ifndef CONFIG_STM32F7_SAI_MAXINFLIGHT -# define CONFIG_STM32F7_SAI_MAXINFLIGHT (16) +#ifndef CONFIG_STM32_SAI_MAXINFLIGHT +# define CONFIG_STM32_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32F7_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifdef CONFIG_STM32_SAI1 +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifdef CONFIG_STM32_SAI2 +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ -# if defined(CONFIG_STM32F7_SAI_DMAPRIO) -# define SAI_DMA_PRIO CONFIG_STM32F7_SAI_DMAPRIO +# if defined(CONFIG_STM32_SAI_DMAPRIO) +# define SAI_DMA_PRIO CONFIG_STM32_SAI_DMAPRIO # else # define SAI_DMA_PRIO DMA_SCR_PRIVERYHI # endif # if (SAI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SAI_DMAPRIO" +# error "Illegal value for CONFIG_STM32_SAI_DMAPRIO" # endif /* DMA channel/stream configuration register settings. The following @@ -194,7 +194,7 @@ struct stm32f7_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -213,7 +213,7 @@ struct stm32f7_sai_s sem_t bufsem; /* Buffer wait semaphore */ struct sai_buffer_s *freelist; /* A list a free buffer containers */ - struct sai_buffer_s containers[CONFIG_STM32F7_SAI_MAXINFLIGHT]; + struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT]; }; /**************************************************************************** @@ -236,7 +236,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32f7_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -274,89 +274,89 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif /* SAI2 state */ -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif - .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32F7_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32F7_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ -#ifdef CONFIG_STM32F7_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); +#ifdef CONFIG_STM32_SAI1 + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -757,7 +757,7 @@ static void sai_timeout(wdparm_t arg) struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32_dmastop(priv->dma); @@ -787,7 +787,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32f7_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -959,7 +959,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -1071,7 +1071,7 @@ static void sai_schedule(struct stm32f7_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1268,7 +1268,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1368,7 +1368,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1485,7 +1485,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv) int i; priv->freelist = NULL; - for (i = 0; i < CONFIG_STM32F7_SAI_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); } @@ -1520,36 +1520,36 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) /* Configure the data width */ sai_datawidth((struct i2s_dev_s *)priv, - CONFIG_STM32F7_SAI_DEFAULT_DATALEN); + CONFIG_STM32_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } @@ -1581,7 +1581,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); @@ -1589,7 +1589,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI1_FS_A); stm32_configgpio(GPIO_SAI1_SCK_A); stm32_configgpio(GPIO_SAI1_MCLK_A); @@ -1598,7 +1598,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); @@ -1606,7 +1606,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI1_FS_B); stm32_configgpio(GPIO_SAI1_SCK_B); stm32_configgpio(GPIO_SAI1_MCLK_B); @@ -1615,7 +1615,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); @@ -1623,7 +1623,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI2_FS_A); stm32_configgpio(GPIO_SAI2_SCK_A); stm32_configgpio(GPIO_SAI2_MCLK_A); @@ -1632,7 +1632,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); @@ -1640,7 +1640,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI2_FS_B); stm32_configgpio(GPIO_SAI2_SCK_B); stm32_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 1bf6eac7bafbf..d82877095a158 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -53,7 +53,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -74,15 +74,15 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally optional. * For most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32F7_SDMMC_DMA is enabled. - * CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output. This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * * CONFIG_SDMMC1/2_SDIO_MODE @@ -100,20 +100,20 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#ifndef CONFIG_STM32F7_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# ifndef CONFIG_STM32F7_DMA2 -# error "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2" +# ifndef CONFIG_STM32_DMA2 +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32F7_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -121,16 +121,16 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32F7_SDMMC1 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO -# define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC1_CLK UINT32_C(48000000) @@ -139,16 +139,16 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC2 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO -# define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC2_CLK UINT32_C(48000000) @@ -163,7 +163,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32F7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -345,8 +345,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -379,7 +379,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -409,7 +409,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -433,7 +433,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -450,7 +450,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -473,7 +473,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -488,7 +488,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -563,7 +563,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -572,7 +572,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen); static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ /* Initialization/uninitialization/reset ************************************/ @@ -583,7 +583,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -615,7 +615,7 @@ struct stm32_dev_s g_sdmmcdev1 = .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -627,7 +627,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif .dmarecvsetup = stm32_recvsetup, .dmasendsetup = stm32_sendsetup, -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ #endif /* CONFIG_SDIO_DMA*/ }, .base = STM32_SDMMC1_BASE, @@ -636,8 +636,8 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -651,7 +651,7 @@ struct stm32_dev_s g_sdmmcdev1 = }; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -696,8 +696,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -712,7 +712,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -859,7 +859,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -952,7 +952,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -968,7 +968,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -992,12 +992,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -1016,7 +1016,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -1046,12 +1046,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -1070,13 +1070,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -1089,7 +1089,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1107,7 +1107,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1515,7 +1515,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1625,7 +1625,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1664,7 +1664,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1884,7 +1884,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1903,7 +1903,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ priv->rxbuffer = 0; priv->rxend = 0; @@ -1944,7 +1944,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2241,7 +2241,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2298,7 +2298,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2354,7 +2354,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2871,7 +2871,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2968,11 +2968,11 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); @@ -3009,7 +3009,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3112,7 +3112,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3315,18 +3315,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; # endif @@ -3356,14 +3356,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; # endif @@ -3398,7 +3398,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32_dmachannel(dmachan); @@ -3499,7 +3499,7 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ #ifdef HAVE_SDMMC_SDIO_MODE void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index dd5a10c0ee0b6..c73b64b0548ce 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -64,7 +64,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -78,16 +78,16 @@ */ # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 # endif # endif # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -135,14 +135,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -172,16 +172,16 @@ */ #if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 transmit DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 transmit DMA requires CONFIG_STM32_DMA2 # endif #endif #if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32_DMA1 # endif #endif @@ -228,7 +228,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -331,8 +331,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. @@ -354,7 +354,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -364,13 +364,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -413,7 +413,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32F7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -720,49 +720,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -770,7 +770,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -839,7 +839,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -908,7 +908,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -977,7 +977,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1046,7 +1046,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1115,7 +1115,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1184,7 +1184,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1253,7 +1253,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1324,28 +1324,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1635,7 +1635,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1790,7 +1790,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -1828,49 +1828,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; @@ -1938,7 +1938,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2291,8 +2291,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2405,11 +2405,11 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2432,7 +2432,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2499,7 +2499,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2550,7 +2550,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2687,8 +2687,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F7_USART_BREAKS -# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2907,7 +2907,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3565,7 +3565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3699,7 +3699,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3728,7 +3728,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 4ddc01a553905..2b43927a3ec48 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -73,9 +73,9 @@ #include "stm32_dma.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,39 +135,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32F7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,10 +182,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -231,7 +231,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -291,7 +291,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -336,11 +336,11 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # ifdef SPI1_DMABUFSIZE_ADJUSTED @@ -362,7 +362,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -407,11 +407,11 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -433,7 +433,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -478,11 +478,11 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI3_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -504,7 +504,7 @@ static struct stm32_spidev_s g_spi3dev = }; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -549,11 +549,11 @@ static struct stm32_spidev_s g_spi4dev = }, .spibase = STM32_SPI4_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI4, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI4_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # ifdef SPI4_DMABUFSIZE_ADJUSTED @@ -575,7 +575,7 @@ static struct stm32_spidev_s g_spi4dev = }; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -620,11 +620,11 @@ static struct stm32_spidev_s g_spi5dev = }, .spibase = STM32_SPI5_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI5, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI5_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # ifdef SPI5_DMABUFSIZE_ADJUSTED @@ -646,7 +646,7 @@ static struct stm32_spidev_s g_spi5dev = }; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -691,11 +691,11 @@ static struct stm32_spidev_s g_spi6dev = }, .spibase = STM32_SPI6_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI6, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI6_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # ifdef SPI6_DMABUFSIZE_ADJUSTED @@ -916,7 +916,7 @@ static inline void spi_writebyte(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -949,7 +949,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -982,7 +982,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -997,7 +997,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -1012,7 +1012,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1032,7 +1032,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1052,7 +1052,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -1103,7 +1103,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -1154,7 +1154,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1170,7 +1170,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1397,7 +1397,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA uint16_t cr2bits; #endif @@ -1440,7 +1440,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_modifycr1(priv, 0, SPI_CR1_SPE); spi_modifycr1(priv, setbits, clrbits); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Enabling SPI causes a spurious received character indication * which confuse the DMA controller so we disable DMA during that * enabling; and flush the SPI RX FIFO before re-enabling DMA. @@ -1461,7 +1461,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_getreg(priv, STM32_SPI_DR_OFFSET); } -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Re-enable DMA (with SPI disabled) */ @@ -1691,9 +1691,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F7_SPI_DMA) || defined(CONFIG_STM32F7_DMACAPABLE) || \ - defined(CONFIG_STM32F7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32F7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1777,8 +1777,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32F7_SPI_DMA || CONFIG_STM32F7_DMACAPABLE || - * CONFIG_STM32F7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1802,7 +1802,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1816,13 +1816,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32F7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() * do the work. */ - if (nbytes <= CONFIG_STM32F7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1840,7 +1840,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* If this bus uses a in driver DMA aligned buffers we can skip the test */ if ((txbuffer && priv->txbuf == 0 && @@ -1948,7 +1948,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, } } } -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1969,7 +1969,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2173,7 +2173,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2235,7 +2235,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2260,7 +2260,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2285,7 +2285,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2310,7 +2310,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2335,7 +2335,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2360,7 +2360,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2393,6 +2393,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F7_SPI1 || CONFIG_STM32F7_SPI2 || CONFIG_STM32F7_SPI3 || - * CONFIG_STM32F7_SPI4 || CONFIG_STM32F7_SPI5 || CONFIG_STM32F7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h index f4adbac6a5e16..346af6685970f 100644 --- a/arch/arm/src/stm32f7/stm32_spi.h +++ b/arch/arm/src/stm32f7/stm32_spi.h @@ -98,42 +98,42 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -161,32 +161,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index 52ddb0e04bd20..d348d93cadb66 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -107,18 +107,18 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32F7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32F7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -426,43 +426,43 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32F7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM1STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM2STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM3STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM4STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM5STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: /* Basic timers not supported by this implementation */ @@ -471,7 +471,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: /* Basic timers not supported by this implementation */ @@ -480,52 +480,52 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM8STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM9STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM10STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM11STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM12STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM13STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM14STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; @@ -534,7 +534,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; @@ -543,7 +543,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; @@ -559,8 +559,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32F7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32F7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1027,10 +1027,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1047,7 +1047,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1068,7 +1068,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index e5ba58297196f..b69490b7e4666 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -53,159 +53,159 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32F7_TIMn is - * defined then CONFIG_STM32F7_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32F7_TIMn is defined - * then CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer * "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32F7_TIMn is defined then - * CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined (CONFIG_STM32F7_TIM1_ADC) || \ - defined(CONFIG_STM32F7_TIM1_DAC) || defined(CONFIG_STM32F7_TIM1_QE) -# undef CONFIG_STM32F7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) || defined (CONFIG_STM32F7_TIM2_ADC) || \ - defined(CONFIG_STM32F7_TIM2_DAC) || defined(CONFIG_STM32F7_TIM2_QE) -# undef CONFIG_STM32F7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) || defined (CONFIG_STM32F7_TIM3_ADC) || \ - defined(CONFIG_STM32F7_TIM3_DAC) || defined(CONFIG_STM32F7_TIM3_QE) -# undef CONFIG_STM32F7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) || defined (CONFIG_STM32F7_TIM4_ADC) || \ - defined(CONFIG_STM32F7_TIM4_DAC) || defined(CONFIG_STM32F7_TIM4_QE) -# undef CONFIG_STM32F7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F7_TIM5_PWM) || defined (CONFIG_STM32F7_TIM5_ADC) || \ - defined(CONFIG_STM32F7_TIM5_DAC) || defined(CONFIG_STM32F7_TIM5_QE) -# undef CONFIG_STM32F7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32F7_TIM6_ADC) || \ - defined(CONFIG_STM32F7_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) -# undef CONFIG_STM32F7_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32F7_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) -# undef CONFIG_STM32F7_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F7_TIM8_PWM) || defined (CONFIG_STM32F7_TIM8_ADC) || \ - defined(CONFIG_STM32F7_TIM8_DAC) || defined(CONFIG_STM32F7_TIM8_QE) -# undef CONFIG_STM32F7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F7_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32F7_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) -# undef CONFIG_STM32F7_TIM9 +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) +# undef CONFIG_STM32_TIM9 #endif -#if defined(CONFIG_STM32F7_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32F7_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) -# undef CONFIG_STM32F7_TIM10 +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) +# undef CONFIG_STM32_TIM10 #endif -#if defined(CONFIG_STM32F7_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32F7_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) -# undef CONFIG_STM32F7_TIM11 +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) +# undef CONFIG_STM32_TIM11 #endif -#if defined(CONFIG_STM32F7_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32F7_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) -# undef CONFIG_STM32F7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F7_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32F7_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) -# undef CONFIG_STM32F7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F7_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32F7_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) -# undef CONFIG_STM32F7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM9) +#if defined(CONFIG_STM32_TIM9) # if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) # define HAVE_TIM9_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM10) +#if defined(CONFIG_STM32_TIM10) # if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) # define HAVE_TIM10_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM11) +#if defined(CONFIG_STM32_TIM11) # if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) # define HAVE_TIM11_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) # define HAVE_TIM12_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) # define HAVE_TIM13_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) # define HAVE_TIM14_GPIOCONFIG 1 @@ -216,13 +216,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) /**************************************************************************** * Private Types @@ -326,14 +326,14 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif /* TIM5 is 32-bits on all except F10x lines */ -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -431,72 +431,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -550,72 +550,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: vectorno = STM32_IRQ_TIM9; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: vectorno = STM32_IRQ_TIM10; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: vectorno = STM32_IRQ_TIM11; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; @@ -818,7 +818,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -843,7 +843,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -872,7 +872,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -901,7 +901,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -930,7 +930,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -984,7 +984,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -# ifdef CONFIG_STM32F7_TIM9 +# ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: switch (channel) { @@ -1013,7 +1013,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: switch (channel) { @@ -1042,7 +1042,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: switch (channel) { @@ -1071,7 +1071,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1100,7 +1100,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1240,7 +1240,7 @@ struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -1249,7 +1249,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -1258,7 +1258,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -1267,7 +1267,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -1276,7 +1276,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -1285,7 +1285,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -1294,7 +1294,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -1303,7 +1303,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -1312,7 +1312,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 struct stm32_tim_priv_s stm32_tim9_priv = { .ops = &stm32_tim_ops, @@ -1321,7 +1321,7 @@ struct stm32_tim_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 struct stm32_tim_priv_s stm32_tim10_priv = { .ops = &stm32_tim_ops, @@ -1330,7 +1330,7 @@ struct stm32_tim_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 struct stm32_tim_priv_s stm32_tim11_priv = { .ops = &stm32_tim_ops, @@ -1339,7 +1339,7 @@ struct stm32_tim_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -1348,7 +1348,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -1357,7 +1357,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -1378,85 +1378,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); @@ -1488,72 +1488,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); break; @@ -1569,4 +1569,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM8) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c index f0f5dda38f092..1005d174f7569 100644 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c @@ -56,13 +56,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -144,7 +144,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -152,7 +152,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -160,7 +160,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -168,7 +168,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -176,7 +176,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -184,7 +184,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -192,7 +192,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -200,7 +200,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -208,7 +208,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -216,7 +216,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -224,7 +224,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -232,7 +232,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -240,7 +240,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -248,7 +248,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -482,72 +482,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 447a020e51f6d..e3f555f43ad5d 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -40,44 +40,44 @@ * device. */ -#if STM32F7_NUART < 4 -# undef CONFIG_STM32F7_UART8 +#if STM32_NUART < 4 +# undef CONFIG_STM32_UART8 #endif -#if STM32F7_NUART < 3 -# undef CONFIG_STM32F7_UART7 +#if STM32_NUART < 3 +# undef CONFIG_STM32_UART7 #endif -#if STM32F7_NUART < 2 -# undef CONFIG_STM32F7_UART5 +#if STM32_NUART < 2 +# undef CONFIG_STM32_UART5 #endif -#if STM32F7_NUART < 1 -# undef CONFIG_STM32F7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART4 #endif -#if STM32F7_NUSART < 4 -# undef CONFIG_STM32F7_USART6 +#if STM32_NUSART < 4 +# undef CONFIG_STM32_USART6 #endif -#if STM32F7_NUSART < 3 -# undef CONFIG_STM32F7_USART3 +#if STM32_NUSART < 3 +# undef CONFIG_STM32_USART3 #endif -#if STM32F7_NUSART < 2 -# undef CONFIG_STM32F7_USART2 +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 #endif -#if STM32F7_NUSART < 1 -# undef CONFIG_STM32F7_USART1 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F7_USART1) || defined(CONFIG_STM32F7_USART2) || \ - defined(CONFIG_STM32F7_USART3) || defined(CONFIG_STM32F7_UART4) || \ - defined(CONFIG_STM32F7_UART5) || defined(CONFIG_STM32F7_USART6) || \ - defined(CONFIG_STM32F7_UART7) || defined(CONFIG_STM32F7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -195,42 +195,42 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F7_USART1 +#ifndef CONFIG_STM32_USART1 # undef CONFIG_USART1_RXDMA # undef CONFIG_USART1_TXDMA #endif -#ifndef CONFIG_STM32F7_USART2 +#ifndef CONFIG_STM32_USART2 # undef CONFIG_USART2_RXDMA # undef CONFIG_USART2_TXDMA #endif -#ifndef CONFIG_STM32F7_USART3 +#ifndef CONFIG_STM32_USART3 # undef CONFIG_USART3_RXDMA # undef CONFIG_USART3_TXDMA #endif -#ifndef CONFIG_STM32F7_UART4 +#ifndef CONFIG_STM32_UART4 # undef CONFIG_UART4_RXDMA # undef CONFIG_UART4_TXDMA #endif -#ifndef CONFIG_STM32F7_UART5 +#ifndef CONFIG_STM32_UART5 # undef CONFIG_UART5_RXDMA # undef CONFIG_UART5_TXDMA #endif -#ifndef CONFIG_STM32F7_USART6 +#ifndef CONFIG_STM32_USART6 # undef CONFIG_USART6_RXDMA # undef CONFIG_USART6_TXDMA #endif -#ifndef CONFIG_STM32F7_UART7 +#ifndef CONFIG_STM32_UART7 # undef CONFIG_UART7_RXDMA # undef CONFIG_UART7_TXDMA #endif -#ifndef CONFIG_STM32F7_UART8 +#ifndef CONFIG_STM32_UART8 # undef CONFIG_UART8_RXDMA # undef CONFIG_UART8_TXDMA #endif @@ -300,42 +300,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 7ae4f8e9d2536..6a1500043ae06 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -28,23 +28,23 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32F7_SYSCFG - Needed + * CONFIG_STM32_OTGFSHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGFSHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32f7/stm32_waste.h b/arch/arm/src/stm32f7/stm32_waste.h index 96eb7e6b40b3c..62ec787da8a65 100644 --- a/arch/arm/src/stm32f7/stm32_waste.h +++ b/arch/arm/src/stm32f7/stm32_waste.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H /* Waste CPU Time */ @@ -63,4 +63,4 @@ void stm32_waste(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 19d3e90346bd3..ab98d258eea1d 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -132,48 +132,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -185,31 +185,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -217,9 +217,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -229,7 +229,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -252,31 +252,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -303,13 +303,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -336,151 +336,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -492,19 +492,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -531,67 +531,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -601,56 +601,56 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_OTGFSHS -#ifdef CONFIG_STM32F7_INTERNAL_ULPI +#ifdef CONFIG_STM32_OTGFSHS +#ifdef CONFIG_STM32_INTERNAL_ULPI regval |= RCC_APB2ENR_OTGPHYCEN; #endif @@ -669,7 +669,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -857,7 +857,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -865,14 +865,14 @@ static void stm32_stdclockconfig(void) regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_PLLSAICFGR_PLLSAIR_MASK # endif ); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIP | STM32_RCC_PLLSAICFGR_PLLSAIQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_PLLSAICFGR_PLLSAIR # endif ); @@ -881,7 +881,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_DCKCFGR1); regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK | RCC_DCKCFGR1_PLLSAIDIVQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_DCKCFGR1_PLLSAIDIVR_MASK # endif | RCC_DCKCFGR1_SAI1SEL_MASK @@ -890,7 +890,7 @@ static void stm32_stdclockconfig(void) regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ | STM32_RCC_DCKCFGR1_PLLSAIDIVQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_DCKCFGR1_PLLSAIDIVR # endif | STM32_RCC_DCKCFGR1_SAI1SRC @@ -912,20 +912,20 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_PLLI2SCFGR_PLLI2SP_MASK # endif | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_PLLI2SCFGR_PLLI2SP # endif | STM32_RCC_PLLI2SCFGR_PLLI2SQ @@ -956,7 +956,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_I2C1SEL_MASK | RCC_DCKCFGR2_I2C2SEL_MASK | RCC_DCKCFGR2_I2C3SEL_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_DCKCFGR2_I2C4SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK # endif @@ -975,7 +975,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_DCKCFGR2_I2C1SRC | STM32_RCC_DCKCFGR2_I2C2SRC | STM32_RCC_DCKCFGR2_I2C3SRC -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_DCKCFGR2_I2C4SRC | STM32_RCC_DCKCFGR2_CECSRC # endif @@ -986,13 +986,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index fac08c1146722..c997b8e8b74f0 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -134,48 +134,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -187,31 +187,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -219,9 +219,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -231,7 +231,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -254,31 +254,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -305,13 +305,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -338,151 +338,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -494,19 +494,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -533,67 +533,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -603,49 +603,49 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; @@ -664,7 +664,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -759,7 +759,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -852,7 +852,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -897,7 +897,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ @@ -961,13 +961,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index ff026b7f8e733..c8c21e693db08 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 -/* If CONFIG_STM32F7_DSIHOST is defined in the board configuration, then +/* If CONFIG_STM32_DSIHOST is defined in the board configuration, then * STM32_RCC_DCKCFGR2_DSISRC must also be defined to select the clock * source. */ @@ -142,48 +142,48 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -195,31 +195,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -227,9 +227,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -239,7 +239,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -262,31 +262,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -313,13 +313,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -346,157 +346,157 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#if defined(CONFIG_STM32F7_SPI2) || defined(CONFIG_STM32F7_I2S2) +#if defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_I2S2) /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#if defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_I2S3) /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 /* CAN3 clock enable. */ regval |= (RCC_APB1ENR_CAN3EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -508,19 +508,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -547,67 +547,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -617,55 +617,55 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_DSIHOST +#ifdef CONFIG_STM32_DSIHOST /* LTDC clock enable */ regval |= RCC_APB2ENR_DSIEN; @@ -684,7 +684,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -779,7 +779,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -846,7 +846,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -872,7 +872,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32_PLLSAI) /* Configure PLLSAI */ @@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || \ +#if defined(CONFIG_STM32_PLLI2S) || \ (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) @@ -990,13 +990,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h index 420f624695c7f..b328ec952ce3d 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h @@ -33,7 +33,7 @@ /* Ethernet support only on STM32H563/573 chips. */ -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) /**************************************************************************** * Pre-processor Definitions @@ -681,5 +681,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_STM32H56XXX */ +#endif /* CONFIG_STM32_STM32H56XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/hardware/stm32_flash.h b/arch/arm/src/stm32h5/hardware/stm32_flash.h index f49c7d02d958f..417c6fdabee2e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32_flash.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h5xxx_flash.h" #else # error "Unsupported STM32 H5 flash" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h index 47125c3173df4..997c2180495ec 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "stm32h56x_dmasigmap.h" #else # error "Unsupported STM32 H5 DMA map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpio.h b/arch/arm/src/stm32h5/hardware/stm32_gpio.h index 0218cb504299a..8ff9b98ab8407 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpio.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_gpio.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_i2c.h b/arch/arm/src/stm32h5/hardware/stm32_i2c.h index 0969c2732df79..d564ba5f1ec04 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32_i2c.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_i2c.h" #else # error "Unsupported STM32 H5 I2C" diff --git a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h index 2900aff29cc13..ff9b80be0fe14 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_memorymap.h" #else # error "Unsupported STM32 H5 memory map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h index 40b57ccf9e52f..555cf41bd49e4 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h56xxx_pinmap.h" #else # error "Unsupported STM32 H5 pin map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pwr.h b/arch/arm/src/stm32h5/hardware/stm32_pwr.h index 1d4ec6386977c..24cddd0b400e6 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pwr.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_pwr.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_qspi.h b/arch/arm/src/stm32h5/hardware/stm32_qspi.h index bda49dd568b11..e4ea385ead69e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h5/hardware/stm32_qspi.h @@ -36,8 +36,8 @@ /* General Characteristics **************************************************/ -#define STM32H5_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H5_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index 239af8377fcaa..ecfa04f7d52db 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_rcc.h" #else # error "Unsupported STM32 H5 rcc" diff --git a/arch/arm/src/stm32h5/hardware/stm32_sbs.h b/arch/arm/src/stm32h5/hardware/stm32_sbs.h index 7ea88c87705c8..06c8a9fb6cfb9 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_sbs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_sbs.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if !defined(CONFIG_STM32H5_STM32H52XXX) && \ - !defined(CONFIG_STM32H5_STM32H53XXX) && \ - !defined(CONFIG_STM32H5_STM32H56XXX) && \ - !defined(CONFIG_STM32H5_STM32H57XXX) +#if !defined(CONFIG_STM32_STM32H52XXX) && \ + !defined(CONFIG_STM32_STM32H53XXX) && \ + !defined(CONFIG_STM32_STM32H56XXX) && \ + !defined(CONFIG_STM32_STM32H57XXX) # warning "SBS not verified on STM32H50x variants." #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_uart.h b/arch/arm/src/stm32h5/hardware/stm32_uart.h index 9ee7d1e1379fe..1b974188d5d30 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32_uart.h @@ -30,8 +30,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # include "hardware/stm32h5xxx_uart.h" #else # error "Unsupported STM32 H5 uart" diff --git a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h index 2f90303f54577..88bf401c4dc69 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_STM32H5_HAVE_USBFS +#ifdef CONFIG_STM32_HAVE_USBFS /**************************************************************************** * Pre-processor Definitions @@ -331,5 +331,5 @@ #define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32H5_HAVE_USBFS */ +#endif /* CONFIG_STM32_HAVE_USBFS */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h index a388e2f69fdd0..57284c4e07cf8 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) || \ - defined(CONFIG_STM32H5_STM32H562XX) +#if defined(CONFIG_STM32_STM32H563XX) || \ + defined(CONFIG_STM32_STM32H562XX) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -786,5 +786,5 @@ #define GPIO_ADC2_INN18_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC2_INP19_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#endif /* CONFIG_STM32H5_STM32H563XX*/ +#endif /* CONFIG_STM32_STM32H563XX*/ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h index 0b93384d725e3..78fffb5e695bb 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h @@ -481,12 +481,12 @@ #define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif @@ -496,12 +496,12 @@ #define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x1f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif @@ -527,12 +527,12 @@ #define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -542,12 +542,12 @@ #define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x1f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -587,12 +587,12 @@ #define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0) #define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x1f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif @@ -618,12 +618,12 @@ #define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif @@ -633,12 +633,12 @@ #define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif -#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) +#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x1f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h index 915d6b4d4b0a8..9718063e46175 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h @@ -53,7 +53,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -69,7 +69,7 @@ # define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -85,7 +85,7 @@ # define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -101,7 +101,7 @@ # define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -117,7 +117,7 @@ # define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -149,7 +149,7 @@ # define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -165,7 +165,7 @@ # define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 8 +#if STM32_NPORTS > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h index eb36e1b58c56a..5b3adf5963e8e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h index 1329727d65df8..8c065d39c4bd5 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_pwr.h @@ -93,13 +93,13 @@ #define PWR_PMCR_ETHERNETSO (1 << 16) /* Ethernet RAM shut-off in Stop Mode */ #define PWR_PMCR_SRAM3SO (1 << 23) /* AHB SRAM3 shut-off in Stop mode */ -#if defined(CONFIG_STM32H5_STM32H56X) || defined(CONFIG_STM32H5_STM32H7X) +#if defined(CONFIG_STM32_STM32H56X) || defined(CONFIG_STM32_STM32H7X) #define PWR_PMCR_SRAM2_16SO (1 << 24) /* AHB SRAM3 16-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_48SO (1 << 25) /* AHB SRAM2 48-Kbyte shut-off in Stop mode **/ #define PWR_PMCR_SRAM1SO (1 << 26) /* AHB SRAM1 shut-off in Stop mode * */ -#elif defined(CONFIG_STM32H5_STM32H2X) || defined(CONFIG_STM32H5_STM32H3X) +#elif defined(CONFIG_STM32_STM32H2X) || defined(CONFIG_STM32_STM32H3X) #define PWR_PMCR_SRAM2_16LSO (1 << 24) /* AHB SRAM3 16-Kbyte Low shut-off in Stop mode **/ #define PWR_PMCR_SRAM2_16HSO (1 << 25) /* AHB SRAM3 16-Kbyte High shut-off in Stop mode **/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h index df39354494518..3e025922ad4a9 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions @@ -1242,5 +1242,5 @@ #define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ #define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ -#endif /* CONFIG_STM32H5_STM32H562XX */ +#endif /* CONFIG_STM32_STM32H562XX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index 1ef4fae584542..14418be67370a 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions @@ -60,7 +60,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -77,7 +77,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -94,7 +94,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -111,7 +111,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -128,7 +128,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -145,7 +145,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) @@ -489,5 +489,5 @@ #define SPI_I2SCFGR_ODD (1 << 24) /* Bit 24: Odd Factor for the Prescaler */ #define SPI_I2SCFGR_MCKOE (1 << 25) /* Bit 24: Master Clock Output Enable */ -#endif /* CONFIG_STM32H5_STM32H5XXX */ +#endif /* CONFIG_STM32_STM32H5XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_SPI_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h index 74d23099c033c..3e9cf17197605 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NLPUART > 0 +#if STM32_NLPUART > 0 # define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 4 +#if STM32_NUSART > 4 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 5 +#if STM32_NUSART > 5 # define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 6 +#if STM32_NUSART > 6 # define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -172,7 +172,7 @@ # define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -187,7 +187,7 @@ # define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -202,7 +202,7 @@ # define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -217,7 +217,7 @@ # define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 4 +#if STM32_NUART > 4 # define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET) @@ -232,7 +232,7 @@ # define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 5 +#if STM32_NUART > 5 # define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index a503d233a9441..b4e73de4960c7 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -53,7 +53,7 @@ #ifdef CONFIG_ADC -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -168,7 +168,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H5_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -260,7 +260,7 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Double the size of the buffer in circular mode * Circular mode utilizes half-transfer DMA interrupts and a 2x buffer @@ -269,10 +269,10 @@ static const struct adc_ops_s g_adcops = */ #ifdef ADC1_HAVE_DMA -# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC1_DMA_BATCH) +# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC1_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG +# ifdef CONFIG_STM32_ADC1_DMA_CFG # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2) # else # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE) @@ -290,18 +290,18 @@ static struct stm32_dev_s g_adcpriv1 = .irq = STM32_IRQ_ADC1, .isr = adc12_interrupt, .intf = 1, - .resolution = CONFIG_STM32H5_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC1_DIFSEL @@ -326,8 +326,8 @@ static struct stm32_dev_s g_adcpriv1 = .hasdma = true, .r_chanbuffer = g_adc1_chanbuffer, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC1_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, +# ifdef CONFIG_STM32_ADC1_DMA_CFG .circular = true, # else .circular = false, @@ -338,25 +338,25 @@ static struct stm32_dev_s g_adcpriv1 = #ifdef ADC1_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC1_TROVS +# ifdef CONFIG_STM32_ADC1_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC1_OVSR, - .ovss = CONFIG_STM32H5_ADC1_OVSS, + .ovsr = CONFIG_STM32_ADC1_OVSR, + .ovss = CONFIG_STM32_ADC1_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC1_WDG1 +#ifdef CONFIG_STM32_ADC1_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC1_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC1_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC1_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC1_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC1_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC1_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC1_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC1_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC1_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -375,13 +375,13 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC2_DMA_BATCH) +# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC2_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG +# ifdef CONFIG_STM32_ADC2_DMA_CFG # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE * 2) # else # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE) @@ -399,18 +399,18 @@ static struct stm32_dev_s g_adcpriv2 = .irq = STM32_IRQ_ADC2, .isr = adc12_interrupt, .intf = 2, - .resolution = CONFIG_STM32H5_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, .mbase = STM32_ADC2_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC2_DIFSEL @@ -435,8 +435,8 @@ static struct stm32_dev_s g_adcpriv2 = .hasdma = true, .r_chanbuffer = g_adc2_chanbuffer, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC2_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, +# ifdef CONFIG_STM32_ADC2_DMA_CFG .circular = true, # else .circular = false, @@ -447,25 +447,25 @@ static struct stm32_dev_s g_adcpriv2 = #ifdef ADC2_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC2_TROVS +# ifdef CONFIG_STM32_ADC2_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC2_OVSR, - .ovss = CONFIG_STM32H5_ADC2_OVSS, + .ovsr = CONFIG_STM32_ADC2_OVSR, + .ovss = CONFIG_STM32_ADC2_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC2_WDG1 +#ifdef CONFIG_STM32_ADC2_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC2_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC2_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC2_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC2_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC2_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC2_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC2_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC2_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC2_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC2_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -1409,7 +1409,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H5_ADC1) && defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1687,7 +1687,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2033,13 +2033,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2048,7 +2048,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2599,13 +2599,13 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; @@ -2621,10 +2621,10 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H5_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H5_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2640,6 +2640,6 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index 7777d539376ca..fe0c523b27407 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -36,95 +36,95 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_ADC -# undef CONFIG_STM32H5_TIM1_ADC1 -# undef CONFIG_STM32H5_TIM1_ADC2 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_ADC -# undef CONFIG_STM32H5_TIM2_ADC1 -# undef CONFIG_STM32H5_TIM2_ADC2 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_ADC -# undef CONFIG_STM32H5_TIM3_ADC1 -# undef CONFIG_STM32H5_TIM3_ADC2 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_ADC -# undef CONFIG_STM32H5_TIM4_ADC1 -# undef CONFIG_STM32H5_TIM4_ADC2 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM6 -# undef CONFIG_STM32H5_TIM6_ADC -# undef CONFIG_STM32H5_TIM6_ADC1 -# undef CONFIG_STM32H5_TIM6_ADC2 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_ADC -# undef CONFIG_STM32H5_TIM8_ADC1 -# undef CONFIG_STM32H5_TIM8_ADC2 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_ADC -# undef CONFIG_STM32H5_TIM15_ADC1 -# undef CONFIG_STM32H5_TIM15_ADC2 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 #endif /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H5_ADC1_DMA) || defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) # define ADC_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC1_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) # define ADC1_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC2_DMA) # define ADC2_HAVE_DMA 1 #endif /* Oversampling support */ #undef ADC_HAVE_OVERSAMPLE -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) || \ - defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) || \ + defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) # define ADC1_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC2_HAVE_OVERSAMPLE 1 #endif #undef ADC_HAVE_WDG1 -#if defined(CONFIG_STM32H5_ADC1_WDG1) || defined(CONFIG_STM32H5_ADC2_WDG1) +#if defined(CONFIG_STM32_ADC1_WDG1) || defined(CONFIG_STM32_ADC2_WDG1) # define ADC_HAVE_WDG1 1 #endif #undef ADC_HAVE_WDG2 -#if defined(CONFIG_STM32H5_ADC1_WDG2) || defined(CONFIG_STM32H5_ADC2_WDG2) +#if defined(CONFIG_STM32_ADC1_WDG2) || defined(CONFIG_STM32_ADC2_WDG2) # define ADC_HAVE_WDG2 1 #endif #undef ADC_HAVE_WDG3 -#if defined(CONFIG_STM32H5_ADC1_WDG3) || defined(CONFIG_STM32H5_ADC2_WDG3) +#if defined(CONFIG_STM32_ADC1_WDG3) || defined(CONFIG_STM32_ADC2_WDG3) # define ADC_HAVE_WDG3 1 #endif @@ -136,43 +136,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H5_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -183,52 +183,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC1_TIMTRIG -# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -239,11 +239,11 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC2_TIMTRIG -# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -254,231 +254,231 @@ # undef ADC_HAVE_TIMER #endif -#if defined(CONFIG_STM32H5_TIM1_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC_CFGR__EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CRFT_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM15)" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM15)" # endif #endif @@ -525,5 +525,5 @@ struct adc_dev_s *stm32h5_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2*/ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2*/ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h5/stm32_dbgmcu.h b/arch/arm/src/stm32h5/stm32_dbgmcu.h index 48d61c970b47b..746fe869c2c25 100644 --- a/arch/arm/src/stm32h5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32h5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_dbgmcu.h" #else # error "Unsupported STM32H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_dma.c b/arch/arm/src/stm32h5/stm32_dma.c index 3f53a85a8dd9b..67465bdb296ac 100644 --- a/arch/arm/src/stm32h5/stm32_dma.c +++ b/arch/arm/src/stm32h5/stm32_dma.c @@ -118,7 +118,7 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 static struct gpdma_ch_s g_chan[] = { { @@ -150,7 +150,7 @@ static struct gpdma_ch_s g_chan[] = .base = STM32_DMA1_BASE + CH_BASE_OFFSET(3) }, #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 { .dma_instance = 2, .channel = 0, @@ -703,7 +703,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return (size_t)(br1 & GPDMA_CXBR1_BNDT_MASK); } -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /**************************************************************************** * Name: stm32_dmacapable * diff --git a/arch/arm/src/stm32h5/stm32_dma.h b/arch/arm/src/stm32h5/stm32_dma.h index 6c94150745748..a9b336d6f8144 100644 --- a/arch/arm/src/stm32h5/stm32_dma.h +++ b/arch/arm/src/stm32h5/stm32_dma.h @@ -39,9 +39,9 @@ # undef CONFIG_DEBUG_DMA_INFO #endif -#ifdef CONFIG_STM32H5_DMACAPABLE -# error "CONFIG_STM32H5_DMACAPABLE not yet implemented." -# undef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE +# error "CONFIG_STM32_DMACAPABLE not yet implemented." +# undef CONFIG_STM32_DMACAPABLE #endif /**************************************************************************** @@ -319,7 +319,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, struct stm32_gpdma_cfg_s *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h5/stm32_dts.c b/arch/arm/src/stm32h5/stm32_dts.c index efcf5da4795f5..a6d9d63134ac5 100644 --- a/arch/arm/src/stm32h5/stm32_dts.c +++ b/arch/arm/src/stm32h5/stm32_dts.c @@ -59,7 +59,7 @@ static int stm32_dts_set_interval (struct sensor_lowerhalf_s *lower, struct file *filep, uint32_t *period_us); -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 static ssize_t stm32_dts_fetch (struct sensor_lowerhalf_s *lower, struct file *filep, char *buffer, size_t buflen); @@ -75,7 +75,7 @@ static int stm32_dts_isr (int irq, void *context, void *arg); * Pre-processor Definitions ****************************************************************************/ -#if CONFIG_STM32H5_DTS_TRIGGER != 0 +#if CONFIG_STM32_DTS_TRIGGER != 0 # error "Hardware triggers not implemented. Need LP Timers first." #endif @@ -112,7 +112,7 @@ static const struct sensor_ops_s g_dts_ops = .activate = stm32_dts_activate, .set_interval = stm32_dts_set_interval, .batch = NULL, -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 .fetch = stm32_dts_fetch, #else .fetch = NULL, @@ -230,7 +230,7 @@ static void dts_configure_cfgr1(void) { /* Compute PCLK prescaler <= 1MHz */ -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) uint32_t div = (STM32_PCLK1_FREQUENCY + 1000000 - 1) / 1000000; if (div > 127) @@ -245,13 +245,13 @@ static void dts_configure_cfgr1(void) uint32_t cfgr1 = DTS_CFGR1_TS1_EN - | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32H5_DTS_SMP_TIME) -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) + | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32_DTS_SMP_TIME) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) | DTS_CFGR1_HSREF_CLK_DIV_RATIO(div) #else | DTS_CFGR1_REFCLK_SEL #endif - | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32H5_DTS_TRIGGER); + | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32_DTS_TRIGGER); putreg32(cfgr1, STM32_DTS_CFGR1); } @@ -295,7 +295,7 @@ static void dts_get_cfg_data(void) { uint32_t cfgr1 = getreg32(STM32_DTS_CFGR1); -#if defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if defined(CONFIG_STM32_DTS_REFCLK_LSE) g_dts_cfg.lse = true; #else g_dts_cfg.lse = false; @@ -324,23 +324,23 @@ static void dts_configure_interrupts(struct sensor_lowerhalf_s *lower) { uint32_t itenr = 0; -#ifdef CONFIG_STM32H5_DTS_ITEN_ITEF +#ifdef CONFIG_STM32_DTS_ITEN_ITEF itenr |= DTS_ITENR_ITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITLF +#ifdef CONFIG_STM32_DTS_ITEN_ITLF itenr |= DTS_ITENR_ITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITHF +#ifdef CONFIG_STM32_DTS_ITEN_ITHF itenr |= DTS_ITENR_ITHEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITEF +#ifdef CONFIG_STM32_DTS_AITEN_AITEF itenr |= DTS_ITENR_AITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITLF +#ifdef CONFIG_STM32_DTS_AITEN_AITLF itenr |= DTS_ITENR_AITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITHF +#ifdef CONFIG_STM32_DTS_AITEN_AITHF itenr |= DTS_ITENR_AITHEN; #endif @@ -392,7 +392,7 @@ static int stm32_dts_activate(struct sensor_lowerhalf_s *lower, return OK; } -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 /**************************************************************************** * Name: stm32_dts_fetch * diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 4dbcee14fb69b..0ef2f2eb4b9da 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -66,12 +66,12 @@ #include -/* STM32H5_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H5 Ethernet support is enabled in the configuration. */ -#if STM32H5_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ /* Configuration ************************************************************/ -#if STM32H5_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -93,85 +93,85 @@ /* Select work queue */ -# if defined(CONFIG_STM32H5_ETHMAC_HPWORK) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_STM32H5_ETHMAC_LPWORK) +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) # define ETHWORK LPWORK # else # define ETHWORK LPWORK # endif #endif -#ifndef CONFIG_STM32H5_PHYADDR -# error "CONFIG_STM32H5_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H5_MII) && !defined(CONFIG_STM32H5_RMII) -# warning "Neither CONFIG_STM32H5_MII nor CONFIG_STM32H5_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H5_MII) && defined(CONFIG_STM32H5_RMII) -# error "Both CONFIG_STM32H5_MII and CONFIG_STM32H5_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H5_MII -# if !defined(CONFIG_STM32H5_MII_MCO1) && !defined(CONFIG_STM32H5_MII_MCO2) && \ - !defined(CONFIG_STM32H5_MII_EXTCLK) -# warning "Neither CONFIG_STM32H5_MII_MCO1, CONFIG_STM32H5_MII_MCO2, nor CONFIG_STM32H5_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_MII_MCO1) && defined(CONFIG_STM32H5_MII_MCO2) -# error "Both CONFIG_STM32H5_MII_MCO1 and CONFIG_STM32H5_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_RMII -# if !defined(CONFIG_STM32H5_RMII_MCO1) && !defined(CONFIG_STM32H5_RMII_MCO2) && \ - !defined(CONFIG_STM32H5_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H5_RMII_MCO1, CONFIG_STM32H5_RMII_MCO2, nor CONFIG_STM32H5_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_RMII_MCO1) && defined(CONFIG_STM32H5_RMII_MCO2) -# error "Both CONFIG_STM32H5_RMII_MCO1 and CONFIG_STM32H5_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_AUTONEG -# ifndef CONFIG_STM32H5_PHYSR -# error "CONFIG_STM32H5_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H5_PHYSR_ALTMODE -# error "CONFIG_STM32H5_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10HD -# error "CONFIG_STM32H5_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100HD -# error "CONFIG_STM32H5_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10FD -# error "CONFIG_STM32H5_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100FD -# error "CONFIG_STM32H5_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H5_PHYSR_SPEED -# error "CONFIG_STM32H5_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100MBPS -# error "CONFIG_STM32H5_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_MODE -# error "CONFIG_STM32H5_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H5_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP -# warning "CONFIG_STM32H5_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* Add 4 to the configured buffer size to account for the 2 byte checksum @@ -182,8 +182,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32H5_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32H5_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -200,16 +200,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H5_ETH_NRXDESC -# define CONFIG_STM32H5_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H5_ETH_NTXDESC -# define CONFIG_STM32H5_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H5_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -227,21 +227,21 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H5_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H5_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H5_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -332,7 +332,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H5_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -347,7 +347,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -653,7 +653,7 @@ aligned_data(ARMV8M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -661,7 +661,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -733,7 +733,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -745,17 +745,17 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(void); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -785,7 +785,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -857,7 +857,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -884,7 +884,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1026,10 +1026,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC + - CONFIG_STM32H5_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1113,7 +1113,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL; #else txdesc->des3 = ETH_TDES3_RD_FD; @@ -1207,7 +1207,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = (ETH_TDES3_RD_OWN | ETH_TDES3_RD_LD | ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL); #else @@ -1259,7 +1259,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H5_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1325,7 +1325,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1398,7 +1398,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1524,10 +1524,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC + - CONFIG_STM32H5_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1678,8 +1678,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H5_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H5_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -1724,7 +1724,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) ninfo("rxhead: %p rxcurr: %p segments: %d\n", priv->rxhead, priv->rxcurr, priv->segments); -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* Check if any errors are reported in the frame. * If hardware checksum is enabled, check if: * - RDES1 is valid @@ -2796,7 +2796,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2832,7 +2832,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2885,7 +2885,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2918,7 +2918,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2926,7 +2926,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H5_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2962,7 +2962,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -2992,7 +2992,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H5_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3026,7 +3026,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3224,7 +3224,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3246,7 +3246,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * Register 16 */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3280,7 +3280,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump() { uint16_t phyval; @@ -3289,7 +3289,7 @@ static void stm32_phyregdump() for (i = 0; i < 0x20; i++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, i, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3320,7 +3320,7 @@ static void stm32_phyregdump() static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3342,7 +3342,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_RESET, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET, MII_MCR_RESET); if (ret < 0) { @@ -3355,7 +3355,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) { up_mdelay(10); to -= 10; - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MCR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MCR, &phyval); } while (phyval & MII_MCR_RESET && to > 0); @@ -3369,7 +3369,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("Phy reset in %d ms\n", PHY_RESET_DELAY - to); } -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(); #endif @@ -3385,12 +3385,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3412,7 +3412,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_ANENABLE, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE, MII_MCR_ANENABLE); if (ret < 0) { @@ -3424,7 +3424,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3446,7 +3446,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, CONFIG_STM32H5_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3455,38 +3455,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H5_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H5_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H5_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H5_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H5_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3499,13 +3499,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H5_PHYSR_MODE) == - CONFIG_STM32H5_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H5_PHYSR_SPEED) == CONFIG_STM32H5_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3514,14 +3514,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3532,10 +3532,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3563,7 +3563,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII #pragma message "If TrustZone is enabled, MII will fail to select." static inline void stm32_selectmii(void) { @@ -3590,7 +3590,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII #pragma message "If TrustZone is enabled, RMII will fail to select." static inline void stm32_selectrmii(void) { @@ -3623,17 +3623,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H5_MII) || defined(CONFIG_STM32H5_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H5_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H5_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3648,7 +3648,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3656,7 +3656,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3664,7 +3664,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3695,7 +3695,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H5_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3710,7 +3710,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3718,7 +3718,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3726,7 +3726,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3749,7 +3749,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4088,7 +4088,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4111,24 +4111,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H5_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4181,7 +4181,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H5_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4242,7 +4242,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4268,7 +4268,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H5_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4283,11 +4283,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H5_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H5_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.h b/arch/arm/src/stm32h5/stm32_ethernet.h index 66107aa0181a4..284d011894d1e 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/stm32_ethernet.h @@ -29,7 +29,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H5_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -65,7 +65,7 @@ extern "C" * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -75,7 +75,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H5_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -90,7 +90,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -100,5 +100,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H5_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 622c809eafa38..639f0e7e1d921 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -75,7 +75,7 @@ # define STM32_CANRAM1_BASE (STM32_FDCAN_SRAM_BASE + 0x0000) # define STM32_CANRAM2_BASE (STM32_FDCAN_SRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4)) -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -90,7 +90,7 @@ # define FDCAN1_TXEVENTFIFO_WORDS (6) # define FDCAN1_TXFIFIOQ_WORDS (54) # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 # define FDCAN2_STDFILTER_SIZE (28) # define FDCAN2_EXTFILTER_SIZE (8) # define FDCAN2_RXFIFO0_SIZE (3) @@ -108,18 +108,18 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING -# define FDCAN1_NTSEG1 (CONFIG_STM32H5_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32H5_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32H5_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -134,13 +134,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32H5_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32H5_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32H5_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 @@ -174,22 +174,22 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* FDCAN2 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING -# define FDCAN2_NTSEG1 (CONFIG_STM32H5_FDCAN2_NTSEG1 - 1) -# define FDCAN2_NTSEG2 (CONFIG_STM32H5_FDCAN2_NTSEG2 - 1) +# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) +# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) # define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_BITRATE)) - 1)) -# define FDCAN2_NSJW (CONFIG_STM32H5_FDCAN2_NSJW - 1) + CONFIG_STM32_FDCAN2_BITRATE)) - 1)) +# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) # if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN2 NTSEG1 @@ -204,13 +204,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN2_FD_BRS -# define FDCAN2_DTSEG1 (CONFIG_STM32H5_FDCAN2_DTSEG1 - 1) -# define FDCAN2_DTSEG2 (CONFIG_STM32H5_FDCAN2_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN2_FD_BRS +# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) +# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) # define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_DBITRATE)) - 1)) -# define FDCAN2_DSJW (CONFIG_STM32H5_FDCAN2_DSJW - 1) + CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) +# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) # else # define FDCAN2_DTSEG1 1 # define FDCAN2_DTSEG2 1 @@ -245,7 +245,7 @@ # define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) # define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /* Interrupts ***************************************************************/ @@ -325,13 +325,13 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32H5_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif -#undef STM32H5_FDCAN_LOOPBACK -#if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \ - defined(CONFIG_STM32H5_FDCAN2_LOOPBACK) -# define STM32H5_FDCAN_LOOPBACK 1 +#undef STM32_FDCAN_LOOPBACK +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN2_LOOPBACK) +# define STM32_FDCAN_LOOPBACK 1 #endif /**************************************************************************** @@ -403,7 +403,7 @@ struct stm32_config_s uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ uint8_t txeventesize; /* TXevent element size (words) */ uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK bool loopback; /* True: Loopback mode */ #endif @@ -435,7 +435,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -460,7 +460,7 @@ struct fdcan_bitseg static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -537,7 +537,7 @@ static const struct can_ops_s g_fdcanops = .co_txempty = fdcan_txempty, }; -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -547,11 +547,11 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32H5_FDCAN1_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN1_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN1_DBITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, +#if defined(CONFIG_STM32_FDCAN1_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN1_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -564,14 +564,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_IT0, .irq1 = STM32_IRQ_FDCAN1_IT1, -#if defined(CONFIG_STM32H5_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -587,7 +587,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -609,9 +609,9 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; static struct can_dev_s g_fdcan1dev; -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* FDCAN2 message RAM allocation */ /* FDCAN2 constant configuration */ @@ -621,11 +621,11 @@ static const struct stm32_config_s g_fdcan2const = .rxpinset = GPIO_FDCAN2_RX, .txpinset = GPIO_FDCAN2_TX, .base = STM32_FDCAN2_BASE, - .baud = CONFIG_STM32H5_FDCAN2_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN2_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN2_DBITRATE, + .baud = CONFIG_STM32_FDCAN2_BITRATE, +#if defined(CONFIG_STM32_FDCAN2_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN2_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | @@ -638,14 +638,14 @@ static const struct stm32_config_s g_fdcan2const = .port = 2, .irq0 = STM32_IRQ_FDCAN2_IT0, .irq1 = STM32_IRQ_FDCAN2_IT1, -#if defined(CONFIG_STM32H5_FDCAN2_CLASSIC) +#if defined(CONFIG_STM32_FDCAN2_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN2_FD) +#elif defined(CONFIG_STM32_FDCAN2_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN2_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -661,7 +661,7 @@ static const struct stm32_config_s g_fdcan2const = .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN2_LOOPBACK +#ifdef CONFIG_STM32_FDCAN2_LOOPBACK .loopback = true, #endif @@ -683,7 +683,7 @@ static const struct stm32_config_s g_fdcan2const = static struct stm32_fdcan_s g_fdcan2priv; static struct can_dev_s g_fdcan2dev; -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /**************************************************************************** * Private Functions @@ -703,7 +703,7 @@ static struct can_dev_s g_fdcan2dev; * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -783,7 +783,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -823,7 +823,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -869,7 +869,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -912,7 +912,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -961,7 +961,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -2406,7 +2406,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) { struct stm32_fdcan_s *priv = dev->cd_priv; uint32_t regval = 0; -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE int tffl = 0; bool empty = false; #endif @@ -2426,7 +2426,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) /* Tx FIFO Free Level */ -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; empty = (tffl >= priv->config->ntxfifoq); return empty; @@ -3275,14 +3275,14 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; #endif fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK /* Is loopback mode selected for this peripheral? */ if (config->loopback) @@ -3461,7 +3461,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -3506,7 +3506,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ @@ -3514,13 +3514,13 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan1dev; priv = &g_fdcan1priv; config = &g_fdcan1const; -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING auto_bit_timing = false; #endif } else #endif -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 if (port == FDCAN2) { /* Select the FDCAN2 device structure */ @@ -3528,7 +3528,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan2dev; priv = &g_fdcan2priv; config = &g_fdcan2const; -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING auto_bit_timing = false; #endif } diff --git a/arch/arm/src/stm32h5/stm32_fdcan.h b/arch/arm/src/stm32h5/stm32_fdcan.h index 5f770fc7a8166..04207ad79856e 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.h +++ b/arch/arm/src/stm32h5/stm32_fdcan.h @@ -64,7 +64,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /**************************************************************************** * Name: stm32_fdcaninitialize @@ -83,7 +83,7 @@ extern "C" struct can_dev_s *stm32_fdcaninitialize(int port); #endif -#ifdef CONFIG_STM32H5_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /**************************************************************************** * Name: stm32_fdcansockinitialize diff --git a/arch/arm/src/stm32h5/stm32_flash.c b/arch/arm/src/stm32h5/stm32_flash.c index e9325741b6623..feac762f1654f 100644 --- a/arch/arm/src/stm32h5/stm32_flash.c +++ b/arch/arm/src/stm32h5/stm32_flash.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) +#if defined(CONFIG_STM32_STM32H563XX) # include "stm32h563xx_flash.c" #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c index 7664d245c9e4f..334a5faf38ae4 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ b/arch/arm/src/stm32h5/stm32_gpio.c @@ -52,30 +52,30 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 STM32_GPIOA_BASE, #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 STM32_GPIOB_BASE, #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 STM32_GPIOC_BASE, #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 STM32_GPIOD_BASE, #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 STM32_GPIOE_BASE, #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 STM32_GPIOF_BASE, #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 STM32_GPIOG_BASE, #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 STM32_GPIOH_BASE, #endif }; @@ -139,7 +139,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -350,7 +350,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -390,7 +390,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h index 9b3552cedc838..ec2caefa30533 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ b/arch/arm/src/stm32h5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32H5 chip" @@ -242,7 +242,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index 7ad06b8491272..a24ef8a795024 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -37,7 +37,7 @@ * Public Functions ****************************************************************************/ -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Name: stm32h5_enable_hsi48 * @@ -168,4 +168,4 @@ void stm32h5_disable_hsi48(void) putreg32(regval, STM32_CRS_CR); } -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index 458a27f6aaa48..fd4579d47a8c6 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); void stm32h5_disable_hsi48(void); -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/stm32h5/stm32_i2c.c index 7b43fa8ed93f5..ba1587d5587b9 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/stm32h5/stm32_i2c.c @@ -158,28 +158,28 @@ * * One of: * - * CONFIG_STM32H5_STM32H5XXXXX + * CONFIG_STM32_STM32H5XXXXX * * and one or more interfaces: * - * CONFIG_STM32H5_I2C1 - * CONFIG_STM32H5_I2C2 - * CONFIG_STM32H5_I2C3 - * CONFIG_STM32H5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -227,8 +227,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H5_I2C1) || defined(CONFIG_STM32H5_I2C2) || \ - defined(CONFIG_STM32H5_I2C3) || defined(CONFIG_STM32H5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -246,25 +246,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H5_I2CTIMEOSEC) && !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 -# define CONFIG_STM32H5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H5_I2CTIMEOSEC) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H5_I2CTIMEOTICKS -# define CONFIG_STM32H5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -443,9 +443,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -485,7 +485,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -523,7 +523,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -561,7 +561,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -599,7 +599,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -731,7 +731,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -748,7 +748,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -804,12 +804,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -847,10 +847,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -988,10 +988,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -1283,82 +1283,82 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C1_ANFOFF; - dnf = CONFIG_STM32H5_I2C1_DNF; -# ifdef CONFIG_STM32H5_I2C1_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C1_RISE; - tf_max = CONFIG_STM32H5_I2C1_FALL; + anfoff = CONFIG_STM32_I2C1_ANFOFF; + dnf = CONFIG_STM32_I2C1_DNF; +# ifdef CONFIG_STM32_I2C1_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C1_RISE; + tf_max = CONFIG_STM32_I2C1_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C2_ANFOFF; - dnf = CONFIG_STM32H5_I2C2_DNF; -# ifdef CONFIG_STM32H5_I2C2_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C2_RISE; - tf_max = CONFIG_STM32H5_I2C2_FALL; + anfoff = CONFIG_STM32_I2C2_ANFOFF; + dnf = CONFIG_STM32_I2C2_DNF; +# ifdef CONFIG_STM32_I2C2_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C2_RISE; + tf_max = CONFIG_STM32_I2C2_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C3_ANFOFF; - dnf = CONFIG_STM32H5_I2C3_DNF; -# ifdef CONFIG_STM32H5_I2C3_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C3_RISE; - tf_max = CONFIG_STM32H5_I2C3_FALL; + anfoff = CONFIG_STM32_I2C3_ANFOFF; + dnf = CONFIG_STM32_I2C3_DNF; +# ifdef CONFIG_STM32_I2C3_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C3_RISE; + tf_max = CONFIG_STM32_I2C3_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C4_ANFOFF; - dnf = CONFIG_STM32H5_I2C4_DNF; -# ifdef CONFIG_STM32H5_I2C4_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C4_RISE; - tf_max = CONFIG_STM32H5_I2C4_FALL; + anfoff = CONFIG_STM32_I2C4_ANFOFF; + dnf = CONFIG_STM32_I2C4_DNF; +# ifdef CONFIG_STM32_I2C4_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C4_RISE; + tf_max = CONFIG_STM32_I2C4_FALL; rf_override = true; # endif break; @@ -2387,17 +2387,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_RCCPCLK1); @@ -2408,17 +2408,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_PCLK1); @@ -2429,17 +2429,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_PCLK3); @@ -2450,17 +2450,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_PCLK3); @@ -3016,22 +3016,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3117,5 +3117,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H5_I2C1 || CONFIG_STM32H5_I2C2 || \ - * CONFIG_STM32H5_I2C3 || CONFIG_STM32H5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.h b/arch/arm/src/stm32h5/stm32_i2c.h index ceb6a7091cd61..87c3f6a1b027a 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.h +++ b/arch/arm/src/stm32h5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO -# if CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H5_I2C_DYNTIMEO because of CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h5/stm32_icache.c b/arch/arm/src/stm32h5/stm32_icache.c index 8cd9c0483eec4..2aa578d6723c0 100644 --- a/arch/arm/src/stm32h5/stm32_icache.c +++ b/arch/arm/src/stm32h5/stm32_icache.c @@ -40,8 +40,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H5_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ - defined(CONFIG_STM32H5_ICACHE_ERR_INT)) +#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32_ICACHE_INV_INT) ||\ + defined(CONFIG_STM32_ICACHE_ERR_INT)) /**************************************************************************** * Private Types @@ -82,51 +82,51 @@ static struct stm32_icache_s icache1 = .lock = SP_UNLOCKED, }; -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 static struct stm32_icache_region region0 = { .num = 0, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION0_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION0_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION0_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION0_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION0_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION0_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION0_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION0_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION0_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION0_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 static struct stm32_icache_region region1 = { .num = 1, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION1_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION1_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION1_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION1_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION1_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION1_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION1_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION1_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION1_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION1_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 static struct stm32_icache_region region2 = { .num = 2, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION2_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION2_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION2_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION2_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION2_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION2_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION2_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION2_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION2_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION2_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 static struct stm32_icache_region region3 = { .num = 3, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION3_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION3_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION3_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION3_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION3_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION3_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION3_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION3_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION3_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION3_HBURST, }; #endif @@ -235,7 +235,7 @@ void stm32_icache_initialize(void) /* Set associativity */ -#ifdef CONFIG_STM32H5_ICACHE_DIRECT +#ifdef CONFIG_STM32_ICACHE_DIRECT regval = getreg32(STM32_ICACHE_CR); regval &= ~(ICACHE_CR_WAYSEL); putreg32(regval, STM32_ICACHE_CR); @@ -246,27 +246,27 @@ void stm32_icache_initialize(void) * Reset Monitors on Initialization */ -#ifdef CONFIG_STM32H5_ICACHE_MONITOR_EN +#ifdef CONFIG_STM32_ICACHE_MONITOR_EN stm32_icache_enable_monitors(); stm32_icache_reset_monitors(); #endif /* Set up region configuration registers */ -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 stm32_icache_setup_region(region0); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 stm32_icache_setup_region(region1); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 stm32_icache_setup_region(region2); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 stm32_icache_setup_region(region3); #endif -#if STM32H5_ICACHE_INTERRUPT +#if STM32_ICACHE_INTERRUPT /* Attach ISR */ int ret; @@ -278,10 +278,10 @@ void stm32_icache_initialize(void) if (ret == OK) { regval = 0; -# ifdef CONFIG_STM32H5_ICACHE_INV_INT +# ifdef CONFIG_STM32_ICACHE_INV_INT regval |= ICACHE_IER_BSYENDIE; # endif -# ifdef CONFIG_STM32H5_ICACHE_ERR_INT +# ifdef CONFIG_STM32_ICACHE_ERR_INT regval |= ICACHE_IER_ERRIE; # endif stm32_icache_set_ier(regval); @@ -358,7 +358,7 @@ void stm32_invalidate_icache(void) regval |= ICACHE_CR_CACHEINV; putreg32(regval, STM32_ICACHE_CR); -#if defined(CONFIG_STM32H5_ICACHE_INV_INT) +#if defined(CONFIG_STM32_ICACHE_INV_INT) stm32_icache_invf_interrupt(); #else stm32_icache_invf_poll(); diff --git a/arch/arm/src/stm32h5/stm32_idle.c b/arch/arm/src/stm32h5/stm32_idle.c index fdde8d81b1fa0..5cc08c4759b40 100644 --- a/arch/arm/src/stm32h5/stm32_idle.c +++ b/arch/arm/src/stm32h5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32h5/stm32_lowputc.c b/arch/arm/src/stm32h5/stm32_lowputc.c index 7de76e7300c85..16a0a6131663a 100644 --- a/arch/arm/src/stm32h5/stm32_lowputc.c +++ b/arch/arm/src/stm32h5/stm32_lowputc.c @@ -46,260 +46,260 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_LPUART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB3ENR -# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32H5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB3ENR +# define STM32_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART1_TX -# define STM32H5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART2_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART2EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART2_TX -# define STM32H5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART3_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART3EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART3_TX -# define STM32H5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART4_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART4EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART4_TX -# define STM32H5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART5_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART5EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART5_TX -# define STM32H5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART6_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART6EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART6_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART6_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART6_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART6_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART6_TX -# define STM32H5_CONSOLE_RX GPIO_USART6_RX +# define STM32_CONSOLE_BASE STM32_USART6_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART6EN +# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32_CONSOLE_TX GPIO_USART6_TX +# define STM32_CONSOLE_RX GPIO_USART6_RX # ifdef CONFIG_USART6_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR # if (CONFIG_USART6_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART7_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART7EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART7_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART7_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART7_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART7_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART7_TX -# define STM32H5_CONSOLE_RX GPIO_UART7_RX +# define STM32_CONSOLE_BASE STM32_UART7_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN +# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32_CONSOLE_TX GPIO_UART7_TX +# define STM32_CONSOLE_RX GPIO_UART7_RX # ifdef CONFIG_UART7_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR # if (CONFIG_UART7_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART8_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART8EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART8_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART8_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART8_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART8_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART8_TX -# define STM32H5_CONSOLE_RX GPIO_UART8_RX +# define STM32_CONSOLE_BASE STM32_UART8_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN +# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32_CONSOLE_TX GPIO_UART8_TX +# define STM32_CONSOLE_RX GPIO_UART8_RX # ifdef CONFIG_UART8_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR # if (CONFIG_UART8_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART9_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART9_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART9EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART9_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART9_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART9_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART9_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART9_TX -# define STM32H5_CONSOLE_RX GPIO_UART9_RX +# define STM32_CONSOLE_BASE STM32_UART9_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART9EN +# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART9_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP +# define STM32_CONSOLE_TX GPIO_UART9_TX +# define STM32_CONSOLE_RX GPIO_UART9_RX # ifdef CONFIG_UART9_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR # if (CONFIG_UART9_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART10_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART10_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART10EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART10_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART10_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART10_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART10_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART10_TX -# define STM32H5_CONSOLE_RX GPIO_USART10_RX +# define STM32_CONSOLE_BASE STM32_USART10_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART10EN +# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART10_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP +# define STM32_CONSOLE_TX GPIO_USART10_TX +# define STM32_CONSOLE_RX GPIO_USART10_RX # ifdef CONFIG_USART10_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR # if (CONFIG_USART10_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART11_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART11_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART11EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART11_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART11_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART11_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART11_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART11_TX -# define STM32H5_CONSOLE_RX GPIO_USART11_RX +# define STM32_CONSOLE_BASE STM32_USART11_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART11EN +# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART11_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP +# define STM32_CONSOLE_TX GPIO_USART11_TX +# define STM32_CONSOLE_RX GPIO_USART11_RX # ifdef CONFIG_USART11_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR # if (CONFIG_USART11_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART12_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART12_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART12EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART12_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART12_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART12_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART12_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART12_TX -# define STM32H5_CONSOLE_RX GPIO_UART12_RX +# define STM32_CONSOLE_BASE STM32_UART12_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART12EN +# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART12_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP +# define STM32_CONSOLE_TX GPIO_UART12_TX +# define STM32_CONSOLE_RX GPIO_UART12_RX # ifdef CONFIG_UART12_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR # if (CONFIG_UART12_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32H5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32H5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -307,15 +307,15 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32H5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32H5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 # endif -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE # define USART_CR1_CLRBITS \ (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ @@ -333,7 +333,7 @@ /* CR2 settings */ -# if STM32H5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -362,7 +362,7 @@ # undef USE_OVER8 /* Calculate USART BAUD rate divider */ -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) @@ -388,19 +388,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32H5_USARTDIV8 \ - (((STM32H5_APBCLOCK << 1) + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) -# define STM32H5_USARTDIV16 \ - ((STM32H5_APBCLOCK + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32H5_USARTDIV8 > 2000 -# define STM32H5_BRR_VALUE STM32H5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32H5_BRR_VALUE \ - ((STM32H5_USARTDIV8 & 0xfff0) | ((STM32H5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif #endif /* HAVE_CONSOLE */ @@ -442,22 +442,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32H5_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32H5_CONSOLE_RS485_DIR - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -483,7 +483,7 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB clock */ - modifyreg32(STM32H5_CONSOLE_APBREG, 0, STM32H5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -492,17 +492,17 @@ void stm32_lowsetup(void) * stm32_rcc.c */ -#ifdef STM32H5_CONSOLE_TX - stm32_configgpio(STM32H5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32H5_CONSOLE_RX - stm32_configgpio(STM32H5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_configgpio(STM32H5_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -510,42 +510,42 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32H5_BRR_VALUE, - STM32H5_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32h5/stm32_lse.c b/arch/arm/src/stm32h5/stm32_lse.c index d5c0db5e0f12e..7bc65aa3a06a9 100644 --- a/arch/arm/src/stm32h5/stm32_lse.c +++ b/arch/arm/src/stm32h5/stm32_lse.c @@ -41,9 +41,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -79,7 +79,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -105,19 +105,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -154,7 +154,7 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32h5/stm32_pulsecount.c b/arch/arm/src/stm32h5/stm32_pulsecount.c index 7bae9cc8cb7f2..d002444cd7a5a 100644 --- a/arch/arm/src/stm32h5/stm32_pulsecount.c +++ b/arch/arm/src/stm32h5/stm32_pulsecount.c @@ -182,10 +182,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -212,107 +212,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H5_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1_UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H5_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8_UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -323,7 +323,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -331,7 +331,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1321,21 +1321,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1408,7 +1408,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1417,7 +1417,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1600,7 +1600,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1609,7 +1609,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1761,7 +1761,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1771,7 +1771,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index eadb42917b1a6..1caf1ddc04bb3 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -159,9 +159,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined(CONFIG_STM32H5_TIM8_PWM) || \ - defined(CONFIG_STM32H5_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ - defined(CONFIG_STM32H5_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -169,16 +169,16 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H5_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32H5_TIM1_BREAK1) || defined(CONFIG_STM32H5_TIM1_BREAK2) || \ - defined(CONFIG_STM32H5_TIM8_BREAK1) || defined(CONFIG_STM32H5_TIM8_BREAK2) || \ - defined(CONFIG_STM32H5_TIM15_BREAK1) || defined(CONFIG_STM32H5_TIM16_BREAK1) || \ - defined(CONFIG_STM32H5_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -241,7 +241,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -314,10 +314,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -354,7 +354,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -377,138 +377,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM1_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1POL, - .idle = CONFIG_STM32H5_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1NPOL, - .idle = CONFIG_STM32H5_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM1_CH2MODE, -#ifdef CONFIG_STM32H5_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2POL, - .idle = CONFIG_STM32H5_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2NPOL, - .idle = CONFIG_STM32H5_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM1_CH3MODE, -#ifdef CONFIG_STM32H5_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3POL, - .idle = CONFIG_STM32H5_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3NPOL, - .idle = CONFIG_STM32H5_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM1_CH4MODE, -#ifdef CONFIG_STM32H5_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH4POL, - .idle = CONFIG_STM32H5_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM1_CH5MODE, -#ifdef CONFIG_STM32H5_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH5POL, - .idle = CONFIG_STM32H5_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM1_CH6MODE, -#ifdef CONFIG_STM32H5_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH6POL, - .idle = CONFIG_STM32H5_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -519,18 +519,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H5_TIM1_MODE, - .lock = CONFIG_STM32H5_TIM1_LOCK, - .t_dts = CONFIG_STM32H5_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -538,72 +538,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM2_CH1MODE, -#ifdef CONFIG_STM32H5_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH1POL, - .idle = CONFIG_STM32H5_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM2_CH2MODE, -#ifdef CONFIG_STM32H5_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH2POL, - .idle = CONFIG_STM32H5_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM2_CH3MODE, -#ifdef CONFIG_STM32H5_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH3POL, - .idle = CONFIG_STM32H5_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM2_CH4MODE, -#ifdef CONFIG_STM32H5_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH4POL, - .idle = CONFIG_STM32H5_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -615,14 +615,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H5_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -634,72 +634,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H5_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM3_CH1MODE, -#ifdef CONFIG_STM32H5_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH1POL, - .idle = CONFIG_STM32H5_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM3_CH2MODE, -#ifdef CONFIG_STM32H5_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH2POL, - .idle = CONFIG_STM32H5_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM3_CH3MODE, -#ifdef CONFIG_STM32H5_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH3POL, - .idle = CONFIG_STM32H5_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM3_CH4MODE, -#ifdef CONFIG_STM32H5_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH4POL, - .idle = CONFIG_STM32H5_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -711,14 +711,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H5_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -730,72 +730,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H5_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM4_CH1MODE, -#ifdef CONFIG_STM32H5_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH1POL, - .idle = CONFIG_STM32H5_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM4_CH2MODE, -#ifdef CONFIG_STM32H5_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH2POL, - .idle = CONFIG_STM32H5_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM4_CH3MODE, -#ifdef CONFIG_STM32H5_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH3POL, - .idle = CONFIG_STM32H5_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM4_CH4MODE, -#ifdef CONFIG_STM32H5_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH4POL, - .idle = CONFIG_STM32H5_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -807,14 +807,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H5_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -826,71 +826,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H5_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM5_CH1MODE, -#ifdef CONFIG_STM32H5_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH1POL, - .idle = CONFIG_STM32H5_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM5_CH2MODE, -#ifdef CONFIG_STM32H5_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH2POL, - .idle = CONFIG_STM32H5_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM5_CH3MODE, -#ifdef CONFIG_STM32H5_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH3POL, - .idle = CONFIG_STM32H5_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM5_CH4MODE, -#ifdef CONFIG_STM32H5_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH4POL, - .idle = CONFIG_STM32H5_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -901,14 +901,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H5_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -920,140 +920,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H5_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32H5_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H5_TIM8_BRK2POL, - .flt2 = CONFIG_STM32H5_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1POL, - .idle = CONFIG_STM32H5_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1NPOL, - .idle = CONFIG_STM32H5_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM8_CH2MODE, -#ifdef CONFIG_STM32H5_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2POL, - .idle = CONFIG_STM32H5_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2NPOL, - .idle = CONFIG_STM32H5_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM8_CH3MODE, -#ifdef CONFIG_STM32H5_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3POL, - .idle = CONFIG_STM32H5_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3NPOL, - .idle = CONFIG_STM32H5_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM8_CH4MODE, -#ifdef CONFIG_STM32H5_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH4POL, - .idle = CONFIG_STM32H5_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM8_CH5MODE, -#ifdef CONFIG_STM32H5_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH5POL, - .idle = CONFIG_STM32H5_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM8_CH6MODE, -#ifdef CONFIG_STM32H5_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH6POL, - .idle = CONFIG_STM32H5_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1064,18 +1064,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H5_TIM8_MODE, - .lock = CONFIG_STM32H5_TIM8_LOCK, - .t_dts = CONFIG_STM32H5_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1083,40 +1083,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM12_CH1MODE, -#ifdef CONFIG_STM32H5_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH1POL, - .idle = CONFIG_STM32H5_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM12_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH2POL, - .idle = CONFIG_STM32H5_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1128,7 +1128,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1147,24 +1147,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H5_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM13_CH1MODE, -#ifdef CONFIG_STM32H5_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM13_CH1POL, - .idle = CONFIG_STM32H5_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1176,7 +1176,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1195,24 +1195,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H5_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM14_CH1MODE, -#ifdef CONFIG_STM32H5_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM14_CH1POL, - .idle = CONFIG_STM32H5_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1224,7 +1224,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1243,58 +1243,58 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H5_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1POL, - .idle = CONFIG_STM32H5_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1NPOL, - .idle = CONFIG_STM32H5_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM15_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH2POL, - .idle = CONFIG_STM32H5_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1306,7 +1306,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1314,10 +1314,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM15_LOCK, - .t_dts = CONFIG_STM32H5_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1325,43 +1325,43 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H5_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1POL, - .idle = CONFIG_STM32H5_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1NPOL, - .idle = CONFIG_STM32H5_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1372,7 +1372,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1380,10 +1380,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM16_LOCK, - .t_dts = CONFIG_STM32H5_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1391,43 +1391,43 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H5_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H5_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H5_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1POL, - .idle = CONFIG_STM32H5_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1NPOL, - .idle = CONFIG_STM32H5_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1438,7 +1438,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1446,10 +1446,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM17_LOCK, - .t_dts = CONFIG_STM32H5_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1457,7 +1457,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H5_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1792,7 +1792,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1849,7 +1849,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2577,7 +2577,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3130,7 +3130,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3139,7 +3139,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3148,7 +3148,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3157,7 +3157,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3166,7 +3166,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3175,7 +3175,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3184,7 +3184,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3193,7 +3193,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3202,7 +3202,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3211,7 +3211,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3220,7 +3220,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3229,7 +3229,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3527,7 +3527,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3536,7 +3536,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3545,7 +3545,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3554,7 +3554,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3563,7 +3563,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3572,7 +3572,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3581,7 +3581,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3590,7 +3590,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3599,7 +3599,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3608,7 +3608,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3617,7 +3617,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3626,7 +3626,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3743,7 +3743,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3754,7 +3754,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3762,7 +3762,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3770,7 +3770,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3778,7 +3778,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3786,7 +3786,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3797,7 +3797,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3805,7 +3805,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3813,7 +3813,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3821,7 +3821,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3829,7 +3829,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3837,7 +3837,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index 149de56fec9cd..138d2ad573b13 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H5_TIM5 -# undef CONFIG_STM32H5_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H5_TIM12 -# undef CONFIG_STM32H5_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H5_TIM13 -# undef CONFIG_STM32H5_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H5_TIM14 -# undef CONFIG_STM32H5_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H5_TIM16 -# undef CONFIG_STM32H5_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H5_TIM17 -# undef CONFIG_STM32H5_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32H5_TIM6_PWM -#undef CONFIG_STM32H5_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H5_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H5_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32H5_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H5_TIM1_PWM -# if !defined(CONFIG_STM32H5_TIM1_CHANNEL) -# error "CONFIG_STM32H5_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM1_CHANNEL == 1 -# define CONFIG_STM32H5_TIM1_CHANNEL1 1 -# define CONFIG_STM32H5_TIM1_CH1MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 2 -# define CONFIG_STM32H5_TIM1_CHANNEL2 1 -# define CONFIG_STM32H5_TIM1_CH2MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 3 -# define CONFIG_STM32H5_TIM1_CHANNEL3 1 -# define CONFIG_STM32H5_TIM1_CH3MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 4 -# define CONFIG_STM32H5_TIM1_CHANNEL4 1 -# define CONFIG_STM32H5_TIM1_CH4MODE CONFIG_STM32H5_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM2_PWM -# if !defined(CONFIG_STM32H5_TIM2_CHANNEL) -# error "CONFIG_STM32H5_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM2_CHANNEL == 1 -# define CONFIG_STM32H5_TIM2_CHANNEL1 1 -# define CONFIG_STM32H5_TIM2_CH1MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 2 -# define CONFIG_STM32H5_TIM2_CHANNEL2 1 -# define CONFIG_STM32H5_TIM2_CH2MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 3 -# define CONFIG_STM32H5_TIM2_CHANNEL3 1 -# define CONFIG_STM32H5_TIM2_CH3MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 4 -# define CONFIG_STM32H5_TIM2_CHANNEL4 1 -# define CONFIG_STM32H5_TIM2_CH4MODE CONFIG_STM32H5_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM3_PWM -# if !defined(CONFIG_STM32H5_TIM3_CHANNEL) -# error "CONFIG_STM32H5_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM3_CHANNEL == 1 -# define CONFIG_STM32H5_TIM3_CHANNEL1 1 -# define CONFIG_STM32H5_TIM3_CH1MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 2 -# define CONFIG_STM32H5_TIM3_CHANNEL2 1 -# define CONFIG_STM32H5_TIM3_CH2MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 3 -# define CONFIG_STM32H5_TIM3_CHANNEL3 1 -# define CONFIG_STM32H5_TIM3_CH3MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 4 -# define CONFIG_STM32H5_TIM3_CHANNEL4 1 -# define CONFIG_STM32H5_TIM3_CH4MODE CONFIG_STM32H5_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM4_PWM -# if !defined(CONFIG_STM32H5_TIM4_CHANNEL) -# error "CONFIG_STM32H5_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM4_CHANNEL == 1 -# define CONFIG_STM32H5_TIM4_CHANNEL1 1 -# define CONFIG_STM32H5_TIM4_CH1MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 2 -# define CONFIG_STM32H5_TIM4_CHANNEL2 1 -# define CONFIG_STM32H5_TIM4_CH2MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 3 -# define CONFIG_STM32H5_TIM4_CHANNEL3 1 -# define CONFIG_STM32H5_TIM4_CH3MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 4 -# define CONFIG_STM32H5_TIM4_CHANNEL4 1 -# define CONFIG_STM32H5_TIM4_CH4MODE CONFIG_STM32H5_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM5_PWM -# if !defined(CONFIG_STM32H5_TIM5_CHANNEL) -# error "CONFIG_STM32H5_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM5_CHANNEL == 1 -# define CONFIG_STM32H5_TIM5_CHANNEL1 1 -# define CONFIG_STM32H5_TIM5_CH1MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 2 -# define CONFIG_STM32H5_TIM5_CHANNEL2 1 -# define CONFIG_STM32H5_TIM5_CH2MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 3 -# define CONFIG_STM32H5_TIM5_CHANNEL3 1 -# define CONFIG_STM32H5_TIM5_CH3MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 4 -# define CONFIG_STM32H5_TIM5_CHANNEL4 1 -# define CONFIG_STM32H5_TIM5_CH4MODE CONFIG_STM32H5_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM8_PWM -# if !defined(CONFIG_STM32H5_TIM8_CHANNEL) -# error "CONFIG_STM32H5_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM8_CHANNEL == 1 -# define CONFIG_STM32H5_TIM8_CHANNEL1 1 -# define CONFIG_STM32H5_TIM8_CH1MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 2 -# define CONFIG_STM32H5_TIM8_CHANNEL2 1 -# define CONFIG_STM32H5_TIM8_CH2MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 3 -# define CONFIG_STM32H5_TIM8_CHANNEL3 1 -# define CONFIG_STM32H5_TIM8_CH3MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 4 -# define CONFIG_STM32H5_TIM8_CHANNEL4 1 -# define CONFIG_STM32H5_TIM8_CH4MODE CONFIG_STM32H5_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM12_PWM -# if !defined(CONFIG_STM32H5_TIM12_CHANNEL) -# error "CONFIG_STM32H5_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM12_CHANNEL == 1 -# define CONFIG_STM32H5_TIM12_CHANNEL1 1 -# define CONFIG_STM32H5_TIM12_CH1MODE CONFIG_STM32H5_TIM12_CHMODE -# elif CONFIG_STM32H5_TIM12_CHANNEL == 2 -# define CONFIG_STM32H5_TIM12_CHANNEL2 1 -# define CONFIG_STM32H5_TIM12_CH2MODE CONFIG_STM32H5_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM13_PWM -# if !defined(CONFIG_STM32H5_TIM13_CHANNEL) -# error "CONFIG_STM32H5_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM13_CHANNEL == 1 -# define CONFIG_STM32H5_TIM13_CHANNEL1 1 -# define CONFIG_STM32H5_TIM13_CH1MODE CONFIG_STM32H5_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM14_PWM -# if !defined(CONFIG_STM32H5_TIM14_CHANNEL) -# error "CONFIG_STM32H5_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM14_CHANNEL == 1 -# define CONFIG_STM32H5_TIM14_CHANNEL1 1 -# define CONFIG_STM32H5_TIM14_CH1MODE CONFIG_STM32H5_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM15_PWM -# if !defined(CONFIG_STM32H5_TIM15_CHANNEL) -# error "CONFIG_STM32H5_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM15_CHANNEL == 1 -# define CONFIG_STM32H5_TIM15_CHANNEL1 1 -# define CONFIG_STM32H5_TIM15_CH1MODE CONFIG_STM32H5_TIM15_CHMODE -# elif CONFIG_STM32H5_TIM15_CHANNEL == 2 -# define CONFIG_STM32H5_TIM15_CHANNEL2 1 -# define CONFIG_STM32H5_TIM15_CH2MODE CONFIG_STM32H5_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM16_PWM -# if !defined(CONFIG_STM32H5_TIM16_CHANNEL) -# error "CONFIG_STM32H5_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM16_CHANNEL == 1 -# define CONFIG_STM32H5_TIM16_CHANNEL1 1 -# define CONFIG_STM32H5_TIM16_CH1MODE CONFIG_STM32H5_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM17_PWM -# if !defined(CONFIG_STM32H5_TIM17_CHANNEL) -# error "CONFIG_STM32H5_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM17_CHANNEL == 1 -# define CONFIG_STM32H5_TIM17_CHANNEL1 1 -# define CONFIG_STM32H5_TIM17_CH1MODE CONFIG_STM32H5_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H5_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H5_TIM1_CH1NOUT) || defined(CONFIG_STM32H5_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM8_CH1NOUT) || defined(CONFIG_STM32H5_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.c b/arch/arm/src/stm32h5/stm32_qspi.c index 2a15d2d19d91d..fa0448187bd4c 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.c +++ b/arch/arm/src/stm32h5/stm32_qspi.c @@ -55,11 +55,11 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA #include "stm32_dma.h" #endif -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H5_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -83,7 +83,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) && defined(CONFIG_STM32H5_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -95,7 +95,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -107,26 +107,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H5_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H5_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H5_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H5_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -144,11 +144,11 @@ * QUADSPI clock defaults to HCLK. */ -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) # error your board.h needs to define STM32_RCC_CCIPR4_OCTOSPI1SEL #endif -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_QSPI_FREQUENCY) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_QSPI_FREQUENCY) # error your board.h needs to defined STM32_QSPI_FREQUENCY #else # define QSPI_CLK_FREQUENCY STM32_QSPI_FREQUENCY @@ -183,14 +183,14 @@ struct stm32_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -200,11 +200,11 @@ struct stm32_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -240,7 +240,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -253,7 +253,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -280,16 +280,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H5_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); @@ -299,8 +299,8 @@ static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H5_QSPI_DMATHRESHOLD -# define CONFIG_STM32H5_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -354,13 +354,13 @@ static struct stm32_qspidev_s g_qspi0dev = }, .base = STM32_OCTOSPI1_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_OCTOSPI1, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -386,7 +386,7 @@ static struct stm32_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -438,7 +438,7 @@ static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -461,7 +461,7 @@ static inline void qspi_putreg(struct stm32_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -583,7 +583,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -797,7 +797,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -936,7 +936,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1075,7 +1075,7 @@ static void qspi_ccrconfig(struct stm32_qspidev_s *priv, } } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1298,7 +1298,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1571,7 +1571,7 @@ static int qspi_memory_dma(struct stm32_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2017,7 +2017,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2198,7 +2198,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2257,11 +2257,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H5_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2423,18 +2423,18 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_MSEL | QSPI_CR_DMM); -#if defined(CONFIG_STM32H5_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_MSEL; #endif -#if defined(CONFIG_STM32H5_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DMM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H5_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2460,10 +2460,10 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) QSPI_DCR1_CSHT_MASK | QSPI_DCR1_DEVSIZE_MASK); - regval |= ((CONFIG_STM32H5_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); - if (0 != CONFIG_STM32H5_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H5_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2569,7 +2569,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2583,7 +2583,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2609,7 +2609,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2617,12 +2617,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2688,7 +2688,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2707,7 +2707,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2753,4 +2753,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.h b/arch/arm/src/stm32h5/stm32_qspi.h index e052df4c1d7c3..91485bfa9ba0a 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.h +++ b/arch/arm/src/stm32h5/stm32_qspi.h @@ -33,7 +33,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -125,5 +125,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.c b/arch/arm/src/stm32h5/stm32_rcc.c index e54cd1f2ce227..fa541ee24a138 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.c +++ b/arch/arm/src/stm32h5/stm32_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -66,7 +66,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -101,7 +101,7 @@ static const uint32_t drives[4] = * ****************************************************************************/ -#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -111,14 +111,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32h5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32H5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32H5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -136,14 +136,14 @@ static inline void rcc_resetbkp(void) /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32H5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); @@ -166,7 +166,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -189,7 +189,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -223,7 +223,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -238,7 +238,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.h b/arch/arm/src/stm32h5/stm32_rcc.h index 49ad30b7f13dc..8e0f56fb786af 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.h +++ b/arch/arm/src/stm32h5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_rcc.h" #else # error "Unsupported STM32H5 chip" @@ -126,7 +126,7 @@ static inline void stm32_mco2config(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -149,7 +149,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,7 +164,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -181,7 +181,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 4d2e94ad5774e..b327ff266f548 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -84,7 +84,7 @@ /* Verify that DMA has been enabled and the DMA channel has been defined. */ -#if !defined(CONFIG_STM32H5_DMA1) && !defined(CONFIG_STM32H5_DMA2) +#if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # error STM32H5 Serial DMA requires one of DMA1 or DMA2 to be enabled #endif @@ -110,19 +110,19 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif #endif /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -142,7 +142,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -331,7 +331,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -339,7 +339,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -347,7 +347,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -355,7 +355,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -363,7 +363,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -371,7 +371,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -379,7 +379,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; # ifdef CONFIG_USART6_RXDMA @@ -403,7 +403,7 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static char g_usart10rxbuffer[CONFIG_USART10_RXBUFSIZE]; static char g_usart10txbuffer[CONFIG_USART10_TXBUFSIZE]; # ifdef CONFIG_USART10_RXDMA @@ -411,7 +411,7 @@ static char g_usart10rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static char g_usart11rxbuffer[CONFIG_USART11_RXBUFSIZE]; static char g_usart11txbuffer[CONFIG_USART11_TXBUFSIZE]; # ifdef CONFIG_USART11_RXDMA @@ -429,7 +429,7 @@ static char g_uart12rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -504,7 +504,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -581,7 +581,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -658,7 +658,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -735,7 +735,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -812,7 +812,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -889,7 +889,7 @@ static struct stm32_serial_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static struct stm32_serial_s g_usart6priv = { .dev = @@ -966,7 +966,7 @@ static struct stm32_serial_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static struct stm32_serial_s g_uart7priv = { .dev = @@ -1043,7 +1043,7 @@ static struct stm32_serial_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static struct stm32_serial_s g_uart8priv = { .dev = @@ -1120,7 +1120,7 @@ static struct stm32_serial_s g_uart8priv = /* This describes the state of the STM32 UART9 port. */ -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER static struct stm32_serial_s g_uart9priv = { .dev = @@ -1197,7 +1197,7 @@ static struct stm32_serial_s g_uart9priv = /* This describes the state of the STM32 USART10 port. */ -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER static struct stm32_serial_s g_usart10priv = { .dev = @@ -1274,7 +1274,7 @@ static struct stm32_serial_s g_usart10priv = /* This describes the state of the STM32 USART11 port. */ -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER static struct stm32_serial_s g_usart11priv = { .dev = @@ -1351,7 +1351,7 @@ static struct stm32_serial_s g_usart11priv = /* This describes the state of the STM32 UART12 port. */ -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static struct stm32_serial_s g_uart12priv = { .dev = @@ -1429,45 +1429,45 @@ static struct stm32_serial_s g_uart12priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER [6] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER [7] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER [8] = &g_uart8priv, #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER [9] = &g_uart9priv, #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER [10] = &g_usart10priv, #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER [11] = &g_usart11priv, #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER [12] = &g_uart12priv, #endif }; @@ -1652,7 +1652,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 if (priv->islpuart == true) { /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ @@ -1738,7 +1738,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) priv->baud; } else -#endif /* CONFIG_STM32H5_LPUART1 */ +#endif /* CONFIG_STM32_LPUART1 */ { uint32_t usartdiv8; @@ -1847,7 +1847,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -2012,7 +2012,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -2051,80 +2051,80 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB3ENR_LPUART1EN ; regaddr = STM32_RCC_APB3ENR; break; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN ; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER case STM32_USART6_BASE: rcc_en = RCC_APB1LENR_USART6EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifdef CONFIG_STM32_UART9_SERIALDRIVER case STM32_UART9_BASE: rcc_en = RCC_APB1HENR_UART9EN; regaddr = STM32_RCC_APB1HENR; break; #endif -#ifdef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifdef CONFIG_STM32_USART10_SERIALDRIVER case STM32_USART10_BASE: rcc_en = RCC_APB1LENR_USART10EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifdef CONFIG_STM32_USART11_SERIALDRIVER case STM32_USART11_BASE: rcc_en = RCC_APB1LENR_USART11EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER case STM32_UART12_BASE: rcc_en = RCC_APB1HENR_UART12EN; regaddr = STM32_RCC_APB1HENR; @@ -2193,7 +2193,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2584,8 +2584,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2834,7 +2834,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2912,7 +2912,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2963,7 +2963,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -3100,8 +3100,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H5_USART_BREAKS -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3343,7 +3343,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3699,7 +3699,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3930,7 +3930,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -4000,7 +4000,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -4049,7 +4049,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -4069,7 +4069,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -4078,7 +4078,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h5/stm32_spi.c b/arch/arm/src/stm32h5/stm32_spi.c index 3a66be2eb1d9c..42ce61211f7a9 100644 --- a/arch/arm/src/stm32h5/stm32_spi.c +++ b/arch/arm/src/stm32h5/stm32_spi.c @@ -72,19 +72,19 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32_dma.h" #endif -#if defined(CONFIG_STM32H5_STM32H50XXX) +#if defined(CONFIG_STM32_STM32H50XXX) # define SPI_MAX_KER_CK 250000000 #else # define SPI_MAX_KER_CK 125000000 #endif -#if defined(CONFIG_STM32H5_SPI1) || defined(CONFIG_STM32H5_SPI2) || \ - defined(CONFIG_STM32H5_SPI3) || defined(CONFIG_STM32H5_SPI4) || \ - defined(CONFIG_STM32H5_SPI5) || defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -94,18 +94,18 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H5_SPI_INTERRUPTS) && defined(CONFIG_STM32H5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -142,39 +142,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H5_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,7 +182,7 @@ /* Kernel clock configuration */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -195,7 +195,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI2) +#if defined(CONFIG_STM32_SPI2) # ifndef STM32_SPI2_FREQUENCY # error Must define STM32_SPI2_FREQUENCY in board.h # else @@ -208,7 +208,7 @@ # endif #endif /* SPI2 */ -#if defined(CONFIG_STM32H5_SPI3) +#if defined(CONFIG_STM32_SPI3) # ifndef STM32_SPI3_FREQUENCY # error Must define STM32_SPI3_FREQUENCY in board.h # else @@ -221,7 +221,7 @@ # endif #endif /* SPI3 */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -234,7 +234,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI5) +#if defined(CONFIG_STM32_SPI5) # ifndef STM32_SPI5_FREQUENCY # error Must define STM32_SPI5_FREQUENCY in board.h # else @@ -247,7 +247,7 @@ # endif #endif /* SPI5 */ -#if defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI6) # ifndef STM32_SPI6_FREQUENCY # error Must define STM32_SPI6_FREQUENCY in board.h # else @@ -278,7 +278,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -328,7 +328,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -394,7 +394,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -443,7 +443,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = STM32_SPI1_FREQUENCY, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -458,15 +458,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI1_COMMTYPE - .config = CONFIG_STM32H5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -515,7 +515,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = STM32_SPI2_FREQUENCY, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -530,15 +530,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI2_COMMTYPE - .config = CONFIG_STM32H5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -587,7 +587,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = STM32_SPI3_FREQUENCY, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -602,15 +602,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI3_COMMTYPE - .config = CONFIG_STM32H5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -659,7 +659,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = STM32_SPI4_FREQUENCY, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H5_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -674,15 +674,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI4_COMMTYPE - .config = CONFIG_STM32H5_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -731,7 +731,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = STM32_SPI5_FREQUENCY, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H5_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -746,15 +746,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI5_COMMTYPE - .config = CONFIG_STM32H5_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -804,7 +804,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = STM32_SPI6_FREQUENCY, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H5_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -819,13 +819,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI6_COMMTYPE - .config = CONFIG_STM32H5_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1147,7 +1147,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1164,7 +1164,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1204,7 +1204,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1253,7 +1253,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1268,7 +1268,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1288,7 +1288,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1350,7 +1350,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1410,7 +1410,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1434,7 +1434,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1991,9 +1991,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H5_SPI_DMA) || defined(CONFIG_STM32H5_DMACAPABLE) || \ - defined(CONFIG_STM32H5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2082,8 +2082,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H5_SPI_DMA || CONFIG_STM32H5_DMACAPABLE || - * CONFIG_STM32H5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2107,7 +2107,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2125,12 +2125,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2194,7 +2194,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2324,7 +2324,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2345,7 +2345,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2579,7 +2579,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2661,7 +2661,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2686,7 +2686,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2711,7 +2711,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2736,7 +2736,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2761,7 +2761,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2786,7 +2786,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2819,6 +2819,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H5_SPI1 || CONFIG_STM32H5_SPI2 || CONFIG_STM32H5_SPI3 || - * CONFIG_STM32H5_SPI4 || CONFIG_STM32H5_SPI5 || CONFIG_STM32H5_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h5/stm32_spi.h b/arch/arm/src/stm32h5/stm32_spi.h index e1f25c88e4904..42f7ea39e5d2a 100644 --- a/arch/arm/src/stm32h5/stm32_spi.h +++ b/arch/arm/src/stm32h5/stm32_spi.h @@ -112,42 +112,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -175,32 +175,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index 812f82951edbb..62acdd78f69f7 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -83,10 +83,10 @@ */ #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define SRAM3_START STM32_SRAM3_BASE -#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE) +#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -176,7 +176,7 @@ void __start(void) *dest++ = *src++; } -#ifdef CONFIG_STM32H5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* NOTE: this is optional because this may be inappropriate, especially * if the memory is being used for it's battery backed purpose. In that * case, the first-time initialization needs to be performed by the board @@ -190,7 +190,7 @@ void __start(void) } #endif -#ifdef CONFIG_STM32H5_SRAM3_INIT +#ifdef CONFIG_STM32_SRAM3_INIT for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; ) { *dest++ = 0; @@ -225,7 +225,7 @@ void __start(void) stm32_board_initialize(); showprogress('C'); -#ifdef CONFIG_STM32H5_ICACHE +#ifdef CONFIG_STM32_ICACHE stm32_enable_icache(); #endif showprogress('G'); diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c index 0bb2b40fefe31..555afe3c72d74 100644 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ b/arch/arm/src/stm32h5/stm32_tim.c @@ -53,96 +53,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H5_TIMn is defined then the CONFIG_STM32H5_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32H5_TIMn is - * defined then CONFIG_STM32H5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32H5_TIMn is defined - * then CONFIG_STM32H5_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32H5_TIMn is defined then - * CONFIG_STM32H5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined (CONFIG_STM32H5_TIM1_ADC) || \ - defined(CONFIG_STM32H5_TIM1_DAC) || defined(CONFIG_STM32H5_TIM1_QE) -# undef CONFIG_STM32H5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H5_TIM2_PWM) || defined (CONFIG_STM32H5_TIM2_ADC) || \ - defined(CONFIG_STM32H5_TIM2_DAC) || defined(CONFIG_STM32H5_TIM2_QE) -# undef CONFIG_STM32H5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H5_TIM3_PWM) || defined (CONFIG_STM32H5_TIM3_ADC) || \ - defined(CONFIG_STM32H5_TIM3_DAC) || defined(CONFIG_STM32H5_TIM3_QE) -# undef CONFIG_STM32H5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H5_TIM4_PWM) || defined (CONFIG_STM32H5_TIM4_ADC) || \ - defined(CONFIG_STM32H5_TIM4_DAC) || defined(CONFIG_STM32H5_TIM4_QE) -# undef CONFIG_STM32H5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H5_TIM5_PWM) || defined (CONFIG_STM32H5_TIM5_ADC) || \ - defined(CONFIG_STM32H5_TIM5_DAC) || defined(CONFIG_STM32H5_TIM5_QE) -# undef CONFIG_STM32H5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32H5_TIM6_ADC) || \ - defined(CONFIG_STM32H5_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) -# undef CONFIG_STM32H5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \ - defined(CONFIG_STM32H5_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) -# undef CONFIG_STM32H5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H5_TIM8_PWM) || defined (CONFIG_STM32H5_TIM8_ADC) || \ - defined(CONFIG_STM32H5_TIM8_DAC) || defined(CONFIG_STM32H5_TIM8_QE) -# undef CONFIG_STM32H5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H5_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ - defined(CONFIG_STM32H5_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) -# undef CONFIG_STM32H5_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H5_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ - defined(CONFIG_STM32H5_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) -# undef CONFIG_STM32H5_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H5_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ - defined(CONFIG_STM32H5_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) -# undef CONFIG_STM32H5_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H5_TIM15_PWM) || defined (CONFIG_STM32H5_TIM15_ADC) || \ - defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE) -# undef CONFIG_STM32H5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H5_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ - defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE) -# undef CONFIG_STM32H5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H5_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ - defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE) -# undef CONFIG_STM32H5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -307,7 +307,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -315,7 +315,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -324,7 +324,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -333,7 +333,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -342,7 +342,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -351,7 +351,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -360,7 +360,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -369,7 +369,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -378,7 +378,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -387,7 +387,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -396,7 +396,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -405,7 +405,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -414,7 +414,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -423,7 +423,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -514,12 +514,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -621,72 +621,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -740,72 +740,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1011,7 +1011,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1044,7 +1044,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1073,7 +1073,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1102,7 +1102,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1131,7 +1131,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1160,7 +1160,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1194,7 +1194,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1213,7 +1213,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1227,7 +1227,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1242,7 +1242,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1261,7 +1261,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1275,7 +1275,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1359,85 +1359,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1469,72 +1469,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1550,4 +1550,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c index b31f6771216e3..d0a77244157be 100644 --- a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -473,75 +473,75 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32h5/stm32_timerisr.c b/arch/arm/src/stm32h5/stm32_timerisr.c index 448f063b87f2f..d985e469cfc66 100644 --- a/arch/arm/src/stm32h5/stm32_timerisr.c +++ b/arch/arm/src/stm32h5/stm32_timerisr.c @@ -58,9 +58,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32H5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32h5/stm32_uart.h b/arch/arm/src/stm32h5/stm32_uart.h index 93914500e7668..04680b4789b82 100644 --- a/arch/arm/src/stm32h5/stm32_uart.h +++ b/arch/arm/src/stm32h5/stm32_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32H5_STM32_UART_H -#define __ARCH_ARM_STC_STM32H5_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32H5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32H5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32H5 chip" @@ -46,116 +46,116 @@ * device. */ -#if !defined(CONFIG_STM32H5_HAVE_UART12) -# undef CONFIG_STM32H5_UART12 +#if !defined(CONFIG_STM32_HAVE_UART12) +# undef CONFIG_STM32_UART12 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART11) -# undef CONFIG_STM32H5_USART11 +#if !defined(CONFIG_STM32_HAVE_USART11) +# undef CONFIG_STM32_USART11 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART10) -# undef CONFIG_STM32H5_USART10 +#if !defined(CONFIG_STM32_HAVE_USART10) +# undef CONFIG_STM32_USART10 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART9) -# undef CONFIG_STM32H5_UART9 +#if !defined(CONFIG_STM32_HAVE_UART9) +# undef CONFIG_STM32_UART9 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART8) -# undef CONFIG_STM32H5_UART8 +#if !defined(CONFIG_STM32_HAVE_UART8) +# undef CONFIG_STM32_UART8 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART7) -# undef CONFIG_STM32H5_UART7 +#if !defined(CONFIG_STM32_HAVE_UART7) +# undef CONFIG_STM32_UART7 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART6) -# undef CONFIG_STM32H5_USART6 +#if !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART5) -# undef CONFIG_STM32H5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART4) -# undef CONFIG_STM32H5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART3) -# undef CONFIG_STM32H5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART2) -# undef CONFIG_STM32H5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART1) -# undef CONFIG_STM32H5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32H5_HAVE_LPUART1) -# undef CONFIG_STM32H5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32H5_LPUART1) -# undef CONFIG_STM32H5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32H5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART1) -# undef CONFIG_STM32H5_USART1_SERIALDRIVER -# undef CONFIG_STM32H5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART2) -# undef CONFIG_STM32H5_USART2_SERIALDRIVER -# undef CONFIG_STM32H5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART3) -# undef CONFIG_STM32H5_USART3_SERIALDRIVER -# undef CONFIG_STM32H5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART4) -# undef CONFIG_STM32H5_UART4_SERIALDRIVER -# undef CONFIG_STM32H5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART5) -# undef CONFIG_STM32H5_UART5_SERIALDRIVER -# undef CONFIG_STM32H5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART6) -# undef CONFIG_STM32H5_USART6_SERIALDRIVER -# undef CONFIG_STM32H5_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART7) -# undef CONFIG_STM32H5_UART7_SERIALDRIVER -# undef CONFIG_STM32H5_UART7_1WIREDRIVER +#if !defined(CONFIG_STM32_UART7) +# undef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_STM32_UART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART8) -# undef CONFIG_STM32H5_UART8_SERIALDRIVER -# undef CONFIG_STM32H5_UART8_1WIREDRIVER +#if !defined(CONFIG_STM32_UART8) +# undef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_STM32_UART8_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART9) -# undef CONFIG_STM32H5_UART9_SERIALDRIVER -# undef CONFIG_STM32H5_UART9_1WIREDRIVER +#if !defined(CONFIG_STM32_UART9) +# undef CONFIG_STM32_UART9_SERIALDRIVER +# undef CONFIG_STM32_UART9_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART10) -# undef CONFIG_STM32H5_USART10_SERIALDRIVER -# undef CONFIG_STM32H5_USART10_1WIREDRIVER +#if !defined(CONFIG_STM32_USART10) +# undef CONFIG_STM32_USART10_SERIALDRIVER +# undef CONFIG_STM32_USART10_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART11) -# undef CONFIG_STM32H5_USART11_SERIALDRIVER -# undef CONFIG_STM32H5_USART11_1WIREDRIVER +#if !defined(CONFIG_STM32_USART11) +# undef CONFIG_STM32_USART11_SERIALDRIVER +# undef CONFIG_STM32_USART11_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART12) -# undef CONFIG_STM32H5_UART12_SERIALDRIVER -# undef CONFIG_STM32H5_UART12_1WIREDRIVER +#if !defined(CONFIG_STM32_UART12) +# undef CONFIG_STM32_UART12_SERIALDRIVER +# undef CONFIG_STM32_UART12_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H5_LPUART1) || defined(CONFIG_STM32H5_USART1) || \ - defined(CONFIG_STM32H5_USART2) || defined(CONFIG_STM32H5_USART3) || \ - defined(CONFIG_STM32H5_UART4) || defined(CONFIG_STM32H5_UART5) || \ - defined(CONFIG_STM32H5_USART6) || defined(CONFIG_STM32H5_UART7) || \ - defined(CONFIG_STM32H5_UART8) || defined(CONFIG_STM32H5_UART9) || \ - defined(CONFIG_STM32H5_USART10) || defined(CONFIG_STM32H5_USART11) || \ - defined(CONFIG_STM32H5_USART12) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \ + defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \ + defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \ + defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \ + defined(CONFIG_STM32_USART12) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,7 +170,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -185,7 +185,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -200,7 +200,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -215,7 +215,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -230,7 +230,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -245,7 +245,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -260,7 +260,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART7_SERIALDRIVER) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -275,7 +275,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 8 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART8_SERIALDRIVER) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -290,7 +290,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 9 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART9_SERIALDRIVER) +#elif defined(CONFIG_UART9_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART9_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -305,7 +305,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 10 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART10_SERIALDRIVER) +#elif defined(CONFIG_USART10_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART10_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -320,7 +320,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 11 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART11_SERIALDRIVER) +#elif defined(CONFIG_USART11_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART11_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -335,7 +335,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 12 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART12_SERIALDRIVER) +#elif defined(CONFIG_UART12_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART12_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -381,55 +381,55 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif -#ifndef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifndef CONFIG_STM32_UART7_SERIALDRIVER # undef CONFIG_UART7_RXDMA #endif -#ifndef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifndef CONFIG_STM32_UART8_SERIALDRIVER # undef CONFIG_UART8_RXDMA #endif -#ifndef CONFIG_STM32H5_UART9_SERIALDRIVER +#ifndef CONFIG_STM32_UART9_SERIALDRIVER # undef CONFIG_UART9_RXDMA #endif -#ifndef CONFIG_STM32H5_USART10_SERIALDRIVER +#ifndef CONFIG_STM32_USART10_SERIALDRIVER # undef CONFIG_USART10_RXDMA #endif -#ifndef CONFIG_STM32H5_USART11_SERIALDRIVER +#ifndef CONFIG_STM32_USART11_SERIALDRIVER # undef CONFIG_USART11_RXDMA #endif -#ifndef CONFIG_STM32H5_UART12_SERIALDRIVER +#ifndef CONFIG_STM32_UART12_SERIALDRIVER # undef CONFIG_UART12_RXDMA #endif @@ -480,31 +480,31 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) +#elif defined(CONFIG_STM32_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) +#elif defined(CONFIG_STM32_USART10_SERIALDRIVER) && !defined(CONFIG_USART10_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) +#elif defined(CONFIG_STM32_USART11_SERIALDRIVER) && !defined(CONFIG_USART11_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) +#elif defined(CONFIG_STM32_UART12_SERIALDRIVER) && !defined(CONFIG_UART12_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -572,4 +572,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32H5_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32H5_STM32_UART_H */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 46fb168b718d3..9261419bff7fb 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -62,7 +62,7 @@ #include "hardware/stm32h5xxx_pwr.h" #include "stm32_usbdrdhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_USBFS_HOST) /**************************************************************************** * Pre-processor Definitions @@ -70,42 +70,42 @@ /* Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif -#ifndef CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT -# define CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT 5000 +#ifndef CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT +# define CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT 5000 #endif /* Hardware definitions */ -#define STM32H5_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS -#define STM32H5_EP0_MAX_PACKET_SIZE 64 -#define STM32H5_RETRY_COUNT 3 /* Control transfer retries */ +#define STM32_NHOST_CHANNELS CONFIG_STM32_USBDRD_NCHANNELS +#define STM32_EP0_MAX_PACKET_SIZE 64 +#define STM32_RETRY_COUNT 3 /* Control transfer retries */ /* PMA Buffer allocation (fixed-size bitmap allocator) */ -#define STM32H5_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ -#define STM32H5_PMA_NBUFFERS 30 /* Total allocatable buffers */ -#define STM32H5_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ -#define STM32H5_PMA_BUFFER_BIT(bn) (1U << (bn)) -#define STM32H5_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32H5_PMA_BUFFER_SIZE)) -#define STM32H5_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ +#define STM32_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ +#define STM32_PMA_NBUFFERS 30 /* Total allocatable buffers */ +#define STM32_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ +#define STM32_PMA_BUFFER_BIT(bn) (1U << (bn)) +#define STM32_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32_PMA_BUFFER_SIZE)) +#define STM32_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ /* Delays */ -#define STM32H5_DATANAK_DELAY SEC2TICK(5) -#define STM32H5_RESET_DELAY 100 /* ms */ +#define STM32_DATANAK_DELAY SEC2TICK(5) +#define STM32_RESET_DELAY 100 /* ms */ /* USB DRD base addresses */ -#define STM32H5_USBDRD_BASE STM32_USB_FS_BASE -#define STM32H5_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE +#define STM32_USBDRD_BASE STM32_USB_FS_BASE +#define STM32_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE /* Register access helpers */ @@ -115,7 +115,7 @@ /* Channel register access */ -#define STM32H5_USB_CHEP(n) (STM32H5_USBDRD_BASE + ((n) << 2)) +#define STM32_USB_CHEP(n) (STM32_USBDRD_BASE + ((n) << 2)) /* Host channel data PID values */ @@ -227,7 +227,7 @@ struct stm32_usbhost_s /* Host channels */ - struct stm32_chan_s chan[STM32H5_NHOST_CHANNELS]; + struct stm32_chan_s chan[STM32_NHOST_CHANNELS]; /* PMA allocation */ @@ -416,7 +416,7 @@ static void stm32_pma_write(const uint8_t *buffer, uint16_t pmaaddr, uint32_t count; uint32_t remaining; - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; /* Number of 32-bit words */ remaining = nbytes & 0x03; /* Remaining bytes */ @@ -466,7 +466,7 @@ static void stm32_pma_read(uint8_t *buffer, uint16_t pmaaddr, UP_DSB(); - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; remaining = nbytes & 0x03; @@ -508,9 +508,9 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) flags = enter_critical_section(); - for (bufndx = 0; bufndx < STM32H5_PMA_NBUFFERS; bufndx++) + for (bufndx = 0; bufndx < STM32_PMA_NBUFFERS; bufndx++) { - uint32_t bit = STM32H5_PMA_BUFFER_BIT(bufndx); + uint32_t bit = STM32_PMA_BUFFER_BIT(bufndx); if ((priv->pma_bufavail & bit) != 0) { priv->pma_bufavail &= ~bit; /* Mark allocated */ @@ -524,12 +524,12 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) if (bufno >= 0) { uinfo("PMA buffer allocated: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } else { uerr("ERROR: PMA buffer allocation failed, all %d buffers in use\n", - STM32H5_PMA_NBUFFERS); + STM32_PMA_NBUFFERS); } return bufno; @@ -548,14 +548,14 @@ static void stm32_pma_free_buffer(struct stm32_usbhost_s *priv, { irqstate_t flags; - DEBUGASSERT(bufno < STM32H5_PMA_NBUFFERS); + DEBUGASSERT(bufno < STM32_PMA_NBUFFERS); flags = enter_critical_section(); - priv->pma_bufavail |= STM32H5_PMA_BUFFER_BIT(bufno); /* Mark available */ + priv->pma_bufavail |= STM32_PMA_BUFFER_BIT(bufno); /* Mark available */ leave_critical_section(flags); uinfo("PMA buffer freed: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } /**************************************************************************** @@ -570,7 +570,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (!priv->chan[chidx].inuse) { @@ -582,7 +582,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) priv->chan[chidx].inuse = true; priv->chan[chidx].pmabufno = (uint8_t)bufno; - priv->chan[chidx].pmaaddr = STM32H5_PMA_BUFNO2ADDR(bufno); + priv->chan[chidx].pmaaddr = STM32_PMA_BUFNO2ADDR(bufno); uinfo("Channel allocated: chidx=%d\n", chidx); return chidx; } @@ -604,18 +604,18 @@ static inline void stm32_chan_free(struct stm32_usbhost_s *priv, { struct stm32_chan_s *chan; - DEBUGASSERT((unsigned)chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; /* Free PMA buffer if allocated */ - if (chan->pmabufno != STM32H5_PMA_BUFFER_NONE) + if (chan->pmabufno != STM32_PMA_BUFFER_NONE) { stm32_set_chep_rx_status(priv, chidx, USB_CHEP_RX_STRX_DIS); stm32_set_chep_tx_status(priv, chidx, USB_CHEP_TX_STTX_DIS); stm32_pma_free_buffer(priv, chan->pmabufno); - chan->pmabufno = STM32H5_PMA_BUFFER_NONE; + chan->pmabufno = STM32_PMA_BUFFER_NONE; chan->pmaaddr = 0; uinfo("Channel freed: chidx=%d\n", chidx); } @@ -639,7 +639,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_TX_DTOGMASK; if (status & USB_CHEP_TX_DTOG1) { @@ -651,7 +651,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_TX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -671,7 +671,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_RX_DTOGMASK; if (status & USB_CHEP_RX_DTOG1) { @@ -683,7 +683,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_RX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -701,7 +701,7 @@ static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) /* Free all host channels */ - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (priv->chan[chidx].inuse) { @@ -748,7 +748,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Read current register value and mask toggleable bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CH_T_MASK; + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CH_T_MASK; /* Set endpoint type */ @@ -772,7 +772,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Write the channel register with VT bits preserved */ - stm32_putreg(STM32H5_USB_CHEP(chidx), + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -944,7 +944,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -956,7 +956,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1092,7 +1092,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval |= (nblocks << USB_PMA_RXBD_NUM_BLOCK_SHIFT); } - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); *pbd = bdval; @@ -1104,7 +1104,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, /* Clear data toggle if starting new transfer */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_RX) != 0) { if (!chan->indata1) @@ -1113,7 +1113,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1124,7 +1124,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1146,7 +1146,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval = chan->pmaaddr; /* chan->pmaaddr is already 4 byte aligned */ bdval |= ((uint32_t)len << USB_PMA_TXBD_COUNT_SHIFT); - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_TXBD_OFFSET(chidx)); *pbd = bdval; @@ -1154,8 +1154,8 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, if (chan->pid == HC_PID_SETUP) { - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; - stm32_putreg(STM32H5_USB_CHEP(chidx), + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_SETUP | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -1164,7 +1164,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, * hardware auto-toggles after successful transmit) */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_TX) != 0) { if (!chan->outdata1) @@ -1173,7 +1173,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1184,7 +1184,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1225,7 +1225,7 @@ static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1257,7 +1257,7 @@ static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->outndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1289,7 +1289,7 @@ static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, } stm32_transfer_start(priv, ep0->inndx); - return stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + return stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); } /**************************************************************************** @@ -1321,7 +1321,7 @@ static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; @@ -1359,7 +1359,7 @@ static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, stm32_transfer_start(priv, chidx); - ret = stm32_chan_wait(priv, chan, CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT); + ret = stm32_chan_wait(priv, chan, CONFIG_STM32_USBDRD_TRANSFER_TIMEOUT); if (ret < 0) { return ret; @@ -1460,13 +1460,13 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t rx_status = chepval & USB_CHEP_RX_STRX_MASK; bool wakeup = false; if ((chepval & USB_CHEP_ERRRX) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uerr("ERRRX chidx=%d chepval=0x%08x rx_status=%d nak=%d\n", chidx, (unsigned int)chepval, (int)((chepval & USB_CHEP_RX_STRX_MASK) >> @@ -1479,7 +1479,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK) & ~USB_CHEP_ERRRX) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1500,7 +1500,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) uint16_t count; bool transfer_complete; - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); count = (*pbd >> USB_PMA_RXBD_COUNT_SHIFT) & 0x3ff; @@ -1546,10 +1546,10 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); /* More data expected - reactivate channel for next packet */ @@ -1598,9 +1598,9 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -1620,7 +1620,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t tx_status = chepval & USB_CHEP_TX_STTX_MASK; bool wakeup = false; @@ -1630,10 +1630,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) * write 1 to VTRX/VTTX to preserve */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_ERRTX) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1699,10 +1699,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) if ((chepval & USB_CHEP_NAK) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_NAK) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); } if (!chan->waiter && !chan->callback) @@ -1728,9 +1728,9 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) /* Clear VTTX by writing 0 to it */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffffff7f & USB_CHEP_REG_MASK)) | USB_CHEP_VTRX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -2132,11 +2132,11 @@ static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /* A single channel is represent by an index in the range of 0 to - * STM32H5_NHOST_CHANNELS. Otherwise, the ep must be a pointer to + * STM32_NHOST_CHANNELS. Otherwise, the ep must be a pointer to * an allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32H5_NHOST_CHANNELS) + if ((uintptr_t)ep < STM32_NHOST_CHANNELS) { /* Halt the channel and mark the channel available */ @@ -2176,14 +2176,14 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, DEBUGASSERT(drvr && buffer && maxlen); - alloc = kmm_malloc(CONFIG_STM32H5_USBDRD_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_USBDRD_DESCSIZE); if (!alloc) { return -ENOMEM; } *buffer = alloc; - *maxlen = CONFIG_STM32H5_USBDRD_DESCSIZE; + *maxlen = CONFIG_STM32_USBDRD_DESCSIZE; return OK; } @@ -2275,7 +2275,7 @@ static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2351,7 +2351,7 @@ static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2409,7 +2409,7 @@ static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, ssize_t nbytes; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2461,7 +2461,7 @@ static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, struct stm32_chan_s *chan; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2499,7 +2499,7 @@ static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) struct stm32_chan_s *chan; irqstate_t flags; - DEBUGASSERT(priv && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; @@ -2595,7 +2595,7 @@ static void stm32_portreset(struct stm32_usbhost_s *priv) /* Wait for reset */ - nxsched_usleep(STM32H5_RESET_DELAY * 1000); + nxsched_usleep(STM32_RESET_DELAY * 1000); /* Release reset */ @@ -2722,15 +2722,15 @@ static void stm32_sw_initialize(struct stm32_usbhost_s *priv) /* Initialize PMA allocation - all buffers available */ - priv->pma_bufavail = STM32H5_PMA_BUFFER_ALLSET; + priv->pma_bufavail = STM32_PMA_BUFFER_ALLSET; /* Initialize channels */ - for (i = 0; i < STM32H5_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { priv->chan[i].chidx = i; priv->chan[i].inuse = false; - priv->chan[i].pmabufno = STM32H5_PMA_BUFFER_NONE; + priv->chan[i].pmabufno = STM32_PMA_BUFFER_NONE; nxsem_init(&priv->chan[i].waitsem, 0, 0); } } @@ -2890,4 +2890,4 @@ void stm32_usbhost_vbusdrive(int port, bool enable) uinfo("VBUS drive port=%d enable=%d (default - no-op)\n", port, enable); } -#endif /* CONFIG_USBHOST && CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_USBFS_HOST */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.h b/arch/arm/src/stm32h5/stm32_usbdrdhost.h index f96b56e0cb7f7..7821a258a7cfe 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.h +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.h @@ -39,20 +39,20 @@ /* Pre-requisites */ -#if !defined(CONFIG_STM32H5_USBFS_HOST) -# error "CONFIG_STM32H5_USBFS_HOST is required" +#if !defined(CONFIG_STM32_USBFS_HOST) +# error "CONFIG_STM32_USBFS_HOST is required" #endif /* USB DRD Host Driver Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif /* Default descriptor buffer size */ -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h5/stm32_usbfs.c b/arch/arm/src/stm32h5/stm32_usbfs.c index 2b44b01426674..c4a69deb44128 100644 --- a/arch/arm/src/stm32h5/stm32_usbfs.c +++ b/arch/arm/src/stm32h5/stm32_usbfs.c @@ -49,7 +49,7 @@ #include "stm32_gpio.h" #include "stm32_usbfs.h" -#if defined(CONFIG_STM32H5_USBFS) +#if defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32H5_USBFS_REGDEBUG +# undef CONFIG_STM32_USBFS_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -345,7 +345,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); @@ -609,7 +609,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -668,7 +668,7 @@ static uint32_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -685,7 +685,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -723,7 +723,7 @@ static void stm32_dumpep(int epno) * Name: stm32_checksetup ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); @@ -3950,4 +3950,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_STM32H5_USBFS */ +#endif /* CONFIG_STM32_USBFS */ diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 3b2aebdcaff4d..5519cb02ab731 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -58,45 +58,45 @@ #define FLASH_BLOCK_SIZE _K(8) #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_I) -# define CONFIG_STM32H5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H5_FLASH_CONFIG_C -# undef CONFIG_STM32H5_FLASH_CONFIG_E -# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) -# define CONFIG_STM32H5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) -# define CONFIG_STM32H5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32H5_FLASH_CONFIG_I) +#if defined(CONFIG_STM32_FLASH_CONFIG_I) # define H5_FLASH_BANK_NBLOCKS 128 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define H5_FLASH_BANK_NBLOCKS 64 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define H5_FLASH_BANK_NBLOCKS 32 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define H5_FLASH_BANK_NBLOCKS 16 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B) +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) # define H5_FLASH_BANK_NBLOCKS 8 #else -# warning "No valid STM32H5_FLASH_CONFIG_x defined." +# warning "No valid STM32_FLASH_CONFIG_x defined." #endif #define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS) diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 62f94162fbb88..1682747b2fc47 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -33,7 +33,7 @@ #include "stm32_pwr.h" #include "stm32_flash.h" #include "stm32_rcc.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions @@ -58,19 +58,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) -# if defined(STM32H5_CLKUSB_SEL) -# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if defined(STM32_CLKUSB_SEL) +# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif -# if defined(STM32H5_CLKRNG_SEL) -# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +# if defined(STM32_CLKRNG_SEL) +# if (STM32_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif #endif @@ -101,49 +101,49 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_GPDMA2EN; #endif -#ifdef CONFIG_STM32H5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32H5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32H5_CORDIC +#ifdef CONFIG_STM32_CORDIC /* CORDIC clock enable */ regval |= RCC_AHB1ENR_CORDICEN; #endif -#ifdef CONFIG_STM32H5_FMAC +#ifdef CONFIG_STM32_FMAC /* FMAC clock enable */ regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32H5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG /* RAMCFG clock enable */ regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32H5_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* ETH clock enable */ regval |= RCC_AHB1ENR_ETHEN; @@ -157,24 +157,24 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_ETHRXEN; #endif -#ifdef CONFIG_STM32H5_TZSC1 +#ifdef CONFIG_STM32_TZSC1 regval |= RCC_AHB1ENR_TZSC1EN; #endif -#ifdef CONFIG_STM32H5_BKPRAM +#ifdef CONFIG_STM32_BKPRAM /* BKPRAM clock enable */ regval |= RCC_AHB1ENR_BKPRAMEN; #endif -#ifdef CONFIG_STM32H5_DCACHE +#ifdef CONFIG_STM32_DCACHE /* DCACHE clock enable */ regval |= RCC_AHB1ENR_DCACHEEN; #endif -#ifdef CONFIG_STM32H5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 /* ETH clock enable */ regval |= RCC_AHB1ENR_SRAM1EN; @@ -203,91 +203,91 @@ static inline void rcc_enableahb2(void) /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#if defined(CONFIG_STM32H5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32H5_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC1 clock enable */ regval |= RCC_AHB2ENR_DAC1EN; #endif -#ifdef CONFIG_STM32H5_DCMI_PSSI +#ifdef CONFIG_STM32_DCMI_PSSI /* Digital Camera Interface clock enable */ regval |= RCC_AHB2ENR_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32H5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32H5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32H5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H5_PKA +#ifdef CONFIG_STM32_PKA /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32H5_SAES +#ifdef CONFIG_STM32_SAES /* Secure AES coprocessor clock enable */ regval |= RCC_AHB2ENR_SAESEN; #endif -#ifdef CONFIG_STM32H5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM2EN; #endif -#ifdef CONFIG_STM32H5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM3EN; @@ -314,31 +314,31 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1EN /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB4ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB4ENR_FMCEN; #endif -#ifdef CONFIG_STM32H5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB4ENR_OSPI1EN; @@ -365,62 +365,62 @@ static inline void rcc_enableapb1l(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Bit 14: SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Bit 15: SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H5_USART2 +#ifdef CONFIG_STM32_USART2 /* Bit 17: USART2 clock enable */ regval |= RCC_APB1LENR_USART2EN; #endif -#ifdef CONFIG_STM32H5_USART3 +#ifdef CONFIG_STM32_USART3 /* Bit 18: USART3 clock enable */ regval |= RCC_APB1LENR_USART3EN; #endif -#ifdef CONFIG_STM32H5_UART4 +#ifdef CONFIG_STM32_UART4 /* Bit 19: UART4 clock enable */ regval |= RCC_APB1LENR_UART4EN; #endif -#ifdef CONFIG_STM32H5_UART5 +#ifdef CONFIG_STM32_UART5 /* Bit 20: UART5 clock enable */ regval |= RCC_APB1LENR_UART5EN; #endif -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Bit 21: I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Bit 22: I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H5_I3C1 +#ifdef CONFIG_STM32_I3C1 /* Bit 23: I3C1 clock enable */ regval |= RCC_APB1LENR_I3C1EN; #endif -#ifdef STM32H5_USE_HSI48 - if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Bit 24: CRS clock enable */ @@ -428,37 +428,37 @@ static inline void rcc_enableapb1l(void) } #endif -#ifdef CONFIG_STM32H5_USART6 +#ifdef CONFIG_STM32_USART6 /* Bit 25: USART6 clock enable */ regval |= RCC_APB1LENR_USART6EN; #endif -#ifdef CONFIG_STM32H5_USART10 +#ifdef CONFIG_STM32_USART10 /* Bit 26: USART10 clock enable */ regval |= RCC_APB1LENR_USART10EN; #endif -#ifdef CONFIG_STM32H5_USART11 +#ifdef CONFIG_STM32_USART11 /* Bit 27: USART11 clock enable */ regval |= RCC_APB1LENR_USART11EN; #endif -#ifdef CONFIG_STM32H5_CEC +#ifdef CONFIG_STM32_CEC /* Bit 28: CEC clock enable */ regval |= RCC_APB1LENR_CECEN; #endif -#ifdef CONFIG_STM32H5_UART7 +#ifdef CONFIG_STM32_UART7 /* Bit 30: UART7 clock enable */ regval |= RCC_APB1LENR_UART7EN; #endif -#ifdef CONFIG_STM32H5_UART8 +#ifdef CONFIG_STM32_UART8 /* Bit 31: UART8 clock enable */ regval |= RCC_APB1LENR_UART8EN; @@ -485,37 +485,37 @@ static inline void rcc_enableapb1h(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H5_UART9 +#ifdef CONFIG_STM32_UART9 /* Bit 0: UART9 clock enable */ regval |= RCC_APB1HENR_UART9EN; #endif -#ifdef CONFIG_STM32H5_UART12 +#ifdef CONFIG_STM32_UART12 /* Bit 1: UART12 clock enable */ regval |= RCC_APB1HENR_UART12EN; #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* Bit 3: DTS clock enable */ regval |= RCC_APB1HENR_DTSEN; #endif -#ifdef CONFIG_STM32H5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Bit 5: Low-power Timer 2 clock enable */ regval |= RCC_APB1HENR_LPTIM2EN; #endif -#ifdef CONFIG_STM32H5_FDCAN +#ifdef CONFIG_STM32_FDCAN /* Bit 9: FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; #endif -#ifdef CONFIG_STM32H5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* Bit 23: UCPD1 clock enable */ regval |= RCC_APB1HENR_UCPD1EN; @@ -544,43 +544,43 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32H5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32H5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_USBFS_HOST) /* USB clock enable */ regval |= RCC_APB2ENR_USBEN; @@ -607,79 +607,79 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32H5_ETHMAC) +#if defined(CONFIG_STM32_SBS) || defined(CONFIG_STM32_ETHMAC) /* Bit 1: SBS clock enable */ regval |= RCC_APB3ENR_SBSEN; #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 /* Bit 5: SPI5 clock enable */ regval |= RCC_APB3ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Bit 6: LPUART1 clock enable */ regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Bit 7: I2C3 clock enable */ regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* Bit 8: I2C4 clock enable */ regval |= RCC_APB3ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H5_I3C2 +#ifdef CONFIG_STM32_I3C2 /* Bit 9: I3C2 clock enable */ regval |= RCC_APB3ENR_I3C2EN; #endif -#ifdef CONFIG_STM32H5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Bit 11: LPTIM1 clock enable */ regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32H5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Bit 12: LPTIM3 clock enable */ regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32H5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 /* Bit 13: LPTIM4 clock enable */ regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32H5_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 /* Bit 14: LPTIM5 clock enable */ regval |= RCC_APB3ENR_LPTIM5EN; #endif -#ifdef CONFIG_STM32H5_LPTIM6 +#ifdef CONFIG_STM32_LPTIM6 /* Bit 15: LPTIM6 clock enable */ regval |= RCC_APB3ENR_LPTIM6EN; #endif -#ifdef CONFIG_STM32H5_VREF +#ifdef CONFIG_STM32_VREF /* Bit 20: VREF clock enable */ regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32H5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB /* Bit 21: RTCABP clock enable */ regval |= RCC_APB3ENR_RTCAPBEN; @@ -842,10 +842,10 @@ void stm32_rcc_enableperipherals(void) rcc_enableapb2(); rcc_enableapb3(); -#ifdef STM32H5_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32H5_HSI48_SYNCSRC); + stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -859,7 +859,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -995,7 +995,7 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR2); -#ifdef CONFIG_STM32H5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR1); @@ -1096,15 +1096,15 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ - defined(STM32H5_USE_LSCO_LSI) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(STM32_USE_LSCO_LSI) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(STM32_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) +#if defined(STM32_USE_LSE) || defined(STM32_USE_LSCO_LSE) /* Low speed external clock source LSE */ stm32_rcc_enablelse(); @@ -1203,19 +1203,19 @@ void stm32_stdclockconfig(void) /* Configure USB source clock */ -#if defined(STM32H5_CLKUSB_SEL) +#if defined(STM32_CLKUSB_SEL) regval = getreg32(STM32_RCC_CCIPR4); regval &= ~RCC_CCIPR4_USBSEL_MASK; - regval |= STM32H5_CLKUSB_SEL; + regval |= STM32_CLKUSB_SEL; putreg32(regval, STM32_RCC_CCIPR4); #endif /* Configure RNG source clock */ -#if defined(STM32H5_CLKRNG_SEL) +#if defined(STM32_CLKRNG_SEL) regval = getreg32(STM32_RCC_CCIPR5); regval &= ~RCC_CCIPR5_RNGSEL_MASK; - regval |= STM32H5_CLKRNG_SEL; + regval |= STM32_CLKRNG_SEL; putreg32(regval, STM32_RCC_CCIPR5); #endif } diff --git a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h index 74973a4004ac4..5ac1b4a0481f9 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h @@ -203,15 +203,15 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_dmamux.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h index f22c76cd15616..a65c24307614b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h @@ -33,11 +33,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -680,5 +680,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_exti.h b/arch/arm/src/stm32h7/hardware/stm32_exti.h index e197f4b6c4279..bd5bf31c73e70 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32h7/hardware/stm32_exti.h @@ -35,11 +35,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -243,5 +243,5 @@ #define EXTI_EVENT_ETHWKUP 86 /* Ethernet wakeup */ #define EXTI_EVENT_HSECSS 87 /* HSECSS interrupt */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_flash.h b/arch/arm/src/stm32h7/hardware/stm32_flash.h index 399694f63f7f9..b24ccc58f7034 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h7/hardware/stm32_flash.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7b3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_flash.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_gpio.h b/arch/arm/src/stm32h7/hardware/stm32_gpio.h index 83c989afaa2d0..68f682e41c96e 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32_gpio.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_gpio.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h index 7b7efcd854908..e9b47c456897b 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_i2c.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h index 18c199495ab38..85b3d880ebd12 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_memorymap.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h index db27991f33da4..409bca7898397 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pinmap.h" #else # error "Unsupported STM32 H7 Pin map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pwr.h b/arch/arm/src/stm32h7/hardware/stm32_pwr.h index 88f257e9a5805..a3fe24507b801 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pwr.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pwr.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index dcc4e882cdf55..a66957eac8941 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 984f782d6129c..67ef3c5d180ed 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_rcc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h index 28bcba80b9ae9..b5d9bd019441a 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x3xx_sdmmc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h index 44bae2e58fa5e..f342cc3ea35bc 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_spi.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h index a48b13ff5d240..3403a0f6fd06d 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_syscfg.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_uart.h b/arch/arm/src/stm32h7/hardware/stm32_uart.h index 9bc1408a9b43c..0e6820748e30f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32_uart.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_uart.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index e052e88da4538..310899214c38f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -30,11 +30,11 @@ #include #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -68,7 +68,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -81,7 +81,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -94,7 +94,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -107,7 +107,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -146,7 +146,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -159,7 +159,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -172,7 +172,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -185,7 +185,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -390,5 +390,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index bd2e35904070d..944b1f0ef2cd2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 215c7be0ed876..96eb849ca33b1 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -63,9 +63,9 @@ #define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */ #define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ # define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 46b114c3e67d8..3974629f51694 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -31,11 +31,11 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -1538,5 +1538,5 @@ #define GPIO_UART8_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN1) #define GPIO_UART8_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8) -#endif /* CONFIG_STM32H7_STM32H7X0XX CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X0XX CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 977f1c4135021..6643ce2452f14 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -131,10 +131,10 @@ #define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */ #define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */ -#ifndef CONFIG_STM32H7_HAVE_SMPS +#ifndef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */ #endif -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */ # define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */ # define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 8124fbd9c7b71..308dc30f621db 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -827,10 +827,10 @@ /* RCC Global Control register */ #define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ #endif -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ # define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index 2e00669d7d456..2cfb71ca647a5 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -29,11 +29,11 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -79,7 +79,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -96,7 +96,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -113,7 +113,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -130,7 +130,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -147,7 +147,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) @@ -466,5 +466,5 @@ /* TODO: SPI/I2S configuration register */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h index e259beff596ff..e5c6fe8e3cedf 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h @@ -56,7 +56,7 @@ #define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2)) #define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */ #endif #define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */ @@ -92,7 +92,7 @@ #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET) #define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET) -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET) #endif #define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET) @@ -220,7 +220,7 @@ /* User register 1 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */ # define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index e5785ef1c16eb..84a46958e43ae 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -31,11 +31,11 @@ #include "chip.h" #include "hardware/stm32_memorymap.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -74,7 +74,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -90,7 +90,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -106,7 +106,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -122,7 +122,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -137,7 +137,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -152,7 +152,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -167,7 +167,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -415,5 +415,5 @@ # define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */ diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index af06b0b83bf86..7f74f83a65f7f 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -77,8 +77,8 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -92,9 +92,9 @@ /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32H7_DMA1) && !defined(CONFIG_STM32H7_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32H7 ADC DMA support requires CONFIG_STM32H7_DMA1 or CONFIG_STM32H7_DMA2" +# error "STM32H7 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -191,7 +191,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H7_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -254,10 +254,10 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, /* ADC Interrupt Handler */ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); #endif @@ -289,11 +289,11 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = @@ -305,19 +305,19 @@ static struct stm32_dev_s g_adcpriv1 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -339,11 +339,11 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = @@ -355,19 +355,19 @@ static struct stm32_dev_s g_adcpriv2 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -389,11 +389,11 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = @@ -405,19 +405,19 @@ static struct stm32_dev_s g_adcpriv3 = .mbase = STM32_ADC3_BASE, .initialized = false, #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .trcc_enr = ADC3_TIMER_RCC_ENR, .trcc_en = ADC3_TIMER_RCC_EN, .extsel = ADC3_EXTSEL_VALUE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -1381,7 +1381,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1880,7 +1880,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2163,13 +2163,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2178,7 +2178,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2203,7 +2203,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -2313,19 +2313,19 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; break; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: ainfo("ADC3 selected\n"); dev = &g_adcdev3; @@ -2341,10 +2341,10 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H7_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H7_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2361,5 +2361,5 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index df7e5132e0590..67b693fb307d7 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -39,87 +39,87 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32H7_TIMn is defined then - * CONFIG_STM32H7_TIMn_ADC must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1,2,3,6 and 15 may be * used on STM32H7X3, while STM32H7X6 adds support for timers 4 and 8 as * well. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_ADC -# undef CONFIG_STM32H7_TIM1_ADC1 -# undef CONFIG_STM32H7_TIM1_ADC2 -# undef CONFIG_STM32H7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_ADC -# undef CONFIG_STM32H7_TIM2_ADC1 -# undef CONFIG_STM32H7_TIM2_ADC2 -# undef CONFIG_STM32H7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_ADC -# undef CONFIG_STM32H7_TIM3_ADC1 -# undef CONFIG_STM32H7_TIM3_ADC2 -# undef CONFIG_STM32H7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_ADC -# undef CONFIG_STM32H7_TIM4_ADC1 -# undef CONFIG_STM32H7_TIM4_ADC2 -# undef CONFIG_STM32H7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM6 -# undef CONFIG_STM32H7_TIM6_ADC -# undef CONFIG_STM32H7_TIM6_ADC1 -# undef CONFIG_STM32H7_TIM6_ADC2 -# undef CONFIG_STM32H7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_ADC -# undef CONFIG_STM32H7_TIM8_ADC1 -# undef CONFIG_STM32H7_TIM8_ADC2 -# undef CONFIG_STM32H7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_ADC -# undef CONFIG_STM32H7_TIM15_ADC1 -# undef CONFIG_STM32H7_TIM15_ADC2 -# undef CONFIG_STM32H7_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -127,24 +127,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H7_ADC1_DMA) || defined(CONFIG_STM32H7_ADC2_DMA) || \ - defined(CONFIG_STM32H7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32H7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -154,43 +154,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -201,52 +201,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC1_TIMTRIG -# error "CONFIG_STM32H7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -257,52 +257,52 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC2_TIMTRIG -# error "CONFIG_STM32H7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC3) +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC3) +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -313,11 +313,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC3_TIMTRIG -# error "CONFIG_STM32H7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -455,315 +455,315 @@ #define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 #define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#if defined(CONFIG_STM32H7_TIM1_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -810,5 +810,5 @@ struct adc_dev_s *stm32h7_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index cec7d503b3ba2..824be376db5d6 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -47,17 +47,17 @@ #include "hardware/stm32_memorymap.h" #include "stm32_mpuinit.h" -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 # include "stm32_dtcm.h" #endif -#include "stm32_fmc.h" +#include "stm32_fmc_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - !defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + !defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support disabled */ @@ -84,7 +84,7 @@ * - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system * heap. Note that DTCM has a number of limitations, for example DMA * transfers to/from DTCM are limited. - * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. + * Define CONFIG_STM32_DTCMEXCLUDE to exclude the DTCM from heap. * +1 to CONFIG_MM_REGIONS if you want to use DTCM. * * - External SDRAM can be connected to the FMC peripheral. Initialization @@ -111,39 +111,39 @@ /* Set the start and end of the SRAMs */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) -#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#elif defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support enabled */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) /* Exclude SRAM123 */ # undef SRAM123_START # undef SRAM123_END -#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) +#elif defined(CONFIG_ARCH_CHIP_STM32_CORTEXM4) /* Configuration for M4 core support enabled */ # define SRAM_START STM32_SRAM123_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM123_SIZE - \ - STM32H7_SRAM3_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM123_SIZE - \ + STM32_SRAM3_SIZE) #endif #undef HAVE_SRAM4 -#if !defined(CONFIG_STM32H7_SRAM4EXCLUDE) +#if !defined(CONFIG_STM32_SRAM4EXCLUDE) # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) -# define SRAM4_END ((uint32_t)(SRAM4_START + STM32H7_SRAM4_SIZE)) +# define SRAM4_END ((uint32_t)(SRAM4_START + STM32_SRAM4_SIZE)) # define SRAM4_HEAP_START ((uint32_t)_sram4_heap_start) #endif @@ -158,7 +158,7 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32H7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif @@ -410,7 +410,7 @@ void arm_addregion(void) } #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC stm32_fmc_init(); #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index a4666960d318f..37dc0b741b2ff 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -50,14 +50,14 @@ #include "mpu.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32H7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_BKPSRAM) -#error Driver Requires CONFIG_STM32H7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -151,7 +151,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32H7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -168,7 +168,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32H7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -591,7 +591,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32H7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -688,9 +688,9 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) * after reset due to the ECC behavior. */ - avail = STM32H7_BBSRAM_SIZE; + avail = STM32_BBSRAM_SIZE; - for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -793,9 +793,9 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) */ # if defined(CONFIG_BUILD_PROTECTED) - mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); # else - mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_user_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); mpu_control(true, true, true); # endif #endif @@ -855,7 +855,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -873,7 +873,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32H7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index c9d41f73cc23f..23c01b59c8ba8 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -25,7 +25,7 @@ /**************************************************************************** * The purpose of this driver is to add battery backup file to the file - * system. There can be CONFIG_STM32H7_BBRSRAM_COUNT files defined. + * system. There can be CONFIG_STM32_BBRSRAM_COUNT files defined. * These files are of fixed size up to the maximum of the backing 4K SRAM. * * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature @@ -46,17 +46,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H7_BBSRAM_SIZE 4096 +#define STM32_BBSRAM_SIZE 4096 -#if !defined(CONFIG_STM32H7_BBSRAM_FILES) -# define CONFIG_STM32H7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -107,8 +107,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES - * CONFIG_STM32H7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -126,7 +126,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: -* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL +* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * @@ -137,7 +137,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * *****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32h7/stm32_capture.c b/arch/arm/src/stm32h7/stm32_capture.c index ec1c3e0dfd7d8..32ef41e9d9cac 100644 --- a/arch/arm/src/stm32h7/stm32_capture.c +++ b/arch/arm/src/stm32h7/stm32_capture.c @@ -49,7 +49,7 @@ /* Sanity checks ************************************************************/ -#if !defined(CONFIG_STM32H7_STM32H7X3XX) +#if !defined(CONFIG_STM32_STM32H7X3XX) # warning "This driver is for STM32H7X3XX devices" #endif @@ -59,7 +59,7 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIMX_CAP) +#if defined(CONFIG_STM32_TIMX_CAP) /* Check if any channel is enabled. * This is done to simplify the logic below. @@ -102,25 +102,25 @@ /* Check if we have any advanced timers */ -#if defined(CONFIG_STM32H7_TIM1_CAP) || defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) # define USE_ADVANCED_TIM 1 #endif /* Check if we have any general purpose timers */ -#if defined(CONFIG_STM32H7_TIM2_CAP) || defined(CONFIG_STM32H7_TIM3_CAP) || \ - defined(CONFIG_STM32H7_TIM4_CAP) || defined(CONFIG_STM32H7_TIM5_CAP) || \ - defined(CONFIG_STM32H7_TIM12_CAP) || defined(CONFIG_STM32H7_TIM13_CAP) || \ - defined(CONFIG_STM32H7_TIM14_CAP) || defined(CONFIG_STM32H7_TIM15_CAP) || \ - defined(CONFIG_STM32H7_TIM16_CAP) || defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) || defined(CONFIG_STM32_TIM15_CAP) || \ + defined(CONFIG_STM32_TIM16_CAP) || defined(CONFIG_STM32_TIM17_CAP) # define USE_GENERAL_TIM 1 #endif /* Check if we have any low-power timers */ -#if defined(CONFIG_STM32H7_LPTIM1_CAP) || defined(CONFIG_STM32H7_LPTIM2_CAP) || \ - defined(CONFIG_STM32H7_LPTIM3_CAP) || defined(CONFIG_STM32H7_LPTIM4_CAP) || \ - defined(CONFIG_STM32H7_LPTIM5_CAP) +#if defined(CONFIG_STM32_LPTIM1_CAP) || defined(CONFIG_STM32_LPTIM2_CAP) || \ + defined(CONFIG_STM32_LPTIM3_CAP) || defined(CONFIG_STM32_LPTIM4_CAP) || \ + defined(CONFIG_STM32_LPTIM5_CAP) # define USE_LOWPOWER_TIM 1 #endif @@ -237,7 +237,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -265,7 +265,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -293,7 +293,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -321,7 +321,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -349,7 +349,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -379,7 +379,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -407,7 +407,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -435,7 +435,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -463,7 +463,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -491,7 +491,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -519,7 +519,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -547,7 +547,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -589,31 +589,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, { /* APB2 Timers */ -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case STM32_TIM15_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case STM32_TIM16_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case STM32_TIM17_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM17EN; @@ -622,50 +622,50 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB1L Timers */ -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM5EN; break; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM1_CAP +#ifdef CONFIG_STM32_LPTIM1_CAP case STM32_LPTIM1_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_LPTIM1EN; @@ -674,25 +674,25 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB4 Timers */ -#ifdef CONFIG_STM32H7_LPTIM2_CAP +#ifdef CONFIG_STM32_LPTIM2_CAP case STM32_LPTIM2_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM2EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3_CAP +#ifdef CONFIG_STM32_LPTIM3_CAP case STM32_LPTIM3_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM3EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4_CAP +#ifdef CONFIG_STM32_LPTIM4_CAP case STM32_LPTIM4_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM4EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5_CAP +#ifdef CONFIG_STM32_LPTIM5_CAP case STM32_LPTIM5_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM5EN; @@ -744,62 +744,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -1350,7 +1350,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1362,7 +1362,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1374,7 +1374,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1386,7 +1386,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1398,7 +1398,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1412,7 +1412,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1424,7 +1424,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1436,7 +1436,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1448,7 +1448,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1460,7 +1460,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1472,7 +1472,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1484,7 +1484,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1496,7 +1496,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static const struct stm32_cap_priv_s stm32_tim15_priv = { .ops = &stm32_cap_ops, @@ -1508,7 +1508,7 @@ static const struct stm32_cap_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static const struct stm32_cap_priv_s stm32_tim16_priv = { .ops = &stm32_cap_ops, @@ -1520,7 +1520,7 @@ static const struct stm32_cap_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static const struct stm32_cap_priv_s stm32_tim17_priv = { .ops = &stm32_cap_ops, @@ -1536,54 +1536,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1640,4 +1640,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 6bdf846cfb081..0b08b7b8d9d4e 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -37,7 +37,7 @@ #include -#include "stm32_capture.h" +#include "stm32_capture_m3m4_v1.h" #if defined(CONFIG_CAPTURE) @@ -47,35 +47,35 @@ /* 32-Bit Timers ************************************************************/ -#define STM32H7_TIM2_RES 32 -#define STM32H7_TIM5_RES 32 +#define STM32_TIM2_RES 32 +#define STM32_TIM5_RES 32 /* 16-Bit Timers ************************************************************/ /* Advanced-Control Timers */ -#define STM32H7_TIM1_RES 16 -#define STM32H7_TIM8_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM8_RES 16 /* General-Purpose Timers */ -#define STM32H7_TIM3_RES 16 -#define STM32H7_TIM4_RES 16 -#define STM32H7_TIM12_RES 16 -#define STM32H7_TIM13_RES 16 -#define STM32H7_TIM14_RES 16 -#define STM32H7_TIM15_RES 16 -#define STM32H7_TIM16_RES 16 -#define STM32H7_TIM17_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /* Basic Timers */ -#define STM32H7_TIM6_RES 16 -#define STM32H7_TIM7_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 /* Low-Power Timers */ -#define STM32H7_LPTIM1_RES 16 -#define STM32H7_LPTIM2_RES 16 -#define STM32H7_LPTIM3_RES 16 -#define STM32H7_LPTIM4_RES 16 -#define STM32H7_LPTIM5_RES 16 +#define STM32_LPTIM1_RES 16 +#define STM32_LPTIM2_RES 16 +#define STM32_LPTIM3_RES 16 +#define STM32_LPTIM4_RES 16 +#define STM32_LPTIM5_RES 16 /**************************************************************************** * Private Types @@ -125,123 +125,123 @@ static const struct cap_ops_s g_cap_ops = .getfreq = stm32_getfreq, }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM1_RES, - .channel = CONFIG_STM32H7_TIM1_CHANNEL, - .clock = CONFIG_STM32H7_TIM1_CLOCK, + .resolution = STM32_TIM1_RES, + .channel = CONFIG_STM32_TIM1_CHANNEL, + .clock = CONFIG_STM32_TIM1_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM2_RES, - .channel = CONFIG_STM32H7_TIM2_CHANNEL, - .clock = CONFIG_STM32H7_TIM2_CLOCK, + .resolution = STM32_TIM2_RES, + .channel = CONFIG_STM32_TIM2_CHANNEL, + .clock = CONFIG_STM32_TIM2_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM3_RES, - .channel = CONFIG_STM32H7_TIM3_CHANNEL, - .clock = CONFIG_STM32H7_TIM3_CLOCK, + .resolution = STM32_TIM3_RES, + .channel = CONFIG_STM32_TIM3_CHANNEL, + .clock = CONFIG_STM32_TIM3_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM4_RES, - .channel = CONFIG_STM32H7_TIM4_CHANNEL, - .clock = CONFIG_STM32H7_TIM4_CLOCK, + .resolution = STM32_TIM4_RES, + .channel = CONFIG_STM32_TIM4_CHANNEL, + .clock = CONFIG_STM32_TIM4_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM5_RES, - .channel = CONFIG_STM32H7_TIM5_CHANNEL, - .clock = CONFIG_STM32H7_TIM5_CLOCK, + .resolution = STM32_TIM5_RES, + .channel = CONFIG_STM32_TIM5_CHANNEL, + .clock = CONFIG_STM32_TIM5_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM8_RES, - .channel = CONFIG_STM32H7_TIM8_CHANNEL, - .clock = CONFIG_STM32H7_TIM8_CLOCK, + .resolution = STM32_TIM8_RES, + .channel = CONFIG_STM32_TIM8_CHANNEL, + .clock = CONFIG_STM32_TIM8_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM12_RES, - .channel = CONFIG_STM32H7_TIM12_CHANNEL, - .clock = CONFIG_STM32H7_TIM12_CLOCK, + .resolution = STM32_TIM12_RES, + .channel = CONFIG_STM32_TIM12_CHANNEL, + .clock = CONFIG_STM32_TIM12_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM13_RES, - .channel = CONFIG_STM32H7_TIM13_CHANNEL, - .clock = CONFIG_STM32H7_TIM13_CLOCK, + .resolution = STM32_TIM13_RES, + .channel = CONFIG_STM32_TIM13_CHANNEL, + .clock = CONFIG_STM32_TIM13_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM14_RES, - .channel = CONFIG_STM32H7_TIM14_CHANNEL, - .clock = CONFIG_STM32H7_TIM14_CLOCK, + .resolution = STM32_TIM14_RES, + .channel = CONFIG_STM32_TIM14_CHANNEL, + .clock = CONFIG_STM32_TIM14_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM15_RES, - .channel = CONFIG_STM32H7_TIM15_CHANNEL, - .clock = CONFIG_STM32H7_TIM15_CLOCK, + .resolution = STM32_TIM15_RES, + .channel = CONFIG_STM32_TIM15_CHANNEL, + .clock = CONFIG_STM32_TIM15_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM16_RES, - .channel = CONFIG_STM32H7_TIM16_CHANNEL, - .clock = CONFIG_STM32H7_TIM16_CLOCK, + .resolution = STM32_TIM16_RES, + .channel = CONFIG_STM32_TIM16_CHANNEL, + .clock = CONFIG_STM32_TIM16_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM17_RES, - .channel = CONFIG_STM32H7_TIM17_CHANNEL, - .clock = CONFIG_STM32H7_TIM17_CLOCK, + .resolution = STM32_TIM17_RES, + .channel = CONFIG_STM32_TIM17_CHANNEL, + .clock = CONFIG_STM32_TIM17_CLOCK, }; #endif @@ -504,62 +504,62 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: lower = &g_cap1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: lower = &g_cap2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: lower = &g_cap3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: lower = &g_cap4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: lower = &g_cap5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: lower = &g_cap8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: lower = &g_cap12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: lower = &g_cap13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: lower = &g_cap14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case 15: lower = &g_cap15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case 16: lower = &g_cap16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case 17: lower = &g_cap17_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c index adbecb87cea63..5ea0a3f87e783 100644 --- a/arch/arm/src/stm32h7/stm32_dma.c +++ b/arch/arm/src/stm32h7/stm32_dma.c @@ -51,22 +51,22 @@ #define DMAMUX_NUM 2 #define DMA_CONTROLLERS 4 -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA # define MDMA_NCHAN 16 #else # define MDMA_NCHAN 0 #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NSTREAMS 8 #else # define DMA1_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NSTREAMS 8 #else # define DMA2_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA # define BDMA_NCHAN 8 #else # define BDMA_NCHAN 0 @@ -185,7 +185,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA static void stm32_mdma_disable(DMA_CHANNEL dmachan); static int stm32_mdma_interrupt(int irq, void *context, void *arg); static void stm32_mdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -193,7 +193,7 @@ static void stm32_mdma_free(DMA_HANDLE handle); static void stm32_mdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_mdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -201,7 +201,7 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_sdma_disable(DMA_CHANNEL dmachan); static int stm32_sdma_interrupt(int irq, void *context, void *arg); static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -209,7 +209,7 @@ static void stm32_sdma_free(DMA_HANDLE handle); static void stm32_sdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_sdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -217,7 +217,7 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA static void stm32_bdma_disable(DMA_CHANNEL dmachan); static int stm32_bdma_interrupt(int irq, void *context, void *arg); static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -225,7 +225,7 @@ static void stm32_bdma_free(DMA_HANDLE handle); static void stm32_bdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_bdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -265,7 +265,7 @@ static inline void dmachan_modifyreg32(DMA_CHANNEL dmachan, struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* 0 - MDMA */ { @@ -275,7 +275,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_mdma_free, .dma_start = stm32_mdma_start, .dma_residual = stm32_mdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_mdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -288,7 +288,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 1 - DMA1 */ { @@ -298,7 +298,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -311,7 +311,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 2 - DMA2 */ { @@ -321,7 +321,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -334,7 +334,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* 3 - BDMA */ { @@ -344,7 +344,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_bdma_free, .dma_start = stm32_bdma_start, .dma_residual = stm32_bdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_bdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -427,7 +427,7 @@ struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA */ { @@ -559,7 +559,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -627,7 +627,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -695,7 +695,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA */ { @@ -920,7 +920,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * Master DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /**************************************************************************** * Name: stm32_mdma_disable @@ -1028,7 +1028,7 @@ static size_t stm32_mdma_residual(DMA_HANDLE handle) * Name: stm32_mdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1084,13 +1084,13 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ /**************************************************************************** * Standard DMA functions ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_sdma_disable @@ -1158,7 +1158,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) /* Get the stream and the controller that generated the interrupt */ -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) { stream = irq - STM32_IRQ_DMA1S0; @@ -1171,7 +1171,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) } else #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -1258,7 +1258,7 @@ static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_sdma_capable(cfg)); #endif @@ -1530,7 +1530,7 @@ static size_t stm32_sdma_residual(DMA_HANDLE handle) * Name: stm32_sdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1604,7 +1604,7 @@ static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1766,13 +1766,13 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_DMA1 || CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Basic DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /**************************************************************************** * Name: stm32_bdma_channel_disable @@ -1898,7 +1898,7 @@ static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_bdma_capable(cfg)); #endif @@ -2106,7 +2106,7 @@ static size_t stm32_bdma_residual(DMA_HANDLE handle) * Name: stm32_bdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -2177,7 +2177,7 @@ static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -2253,7 +2253,7 @@ static void stm32_bdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ /**************************************************************************** * Name: stm32_dmamux_dump @@ -2341,30 +2341,30 @@ void weak_function arm_dma_initialize(void) #ifdef CONFIG_ARCH_IRQPRIO switch (controller) { -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) case DMA1: case DMA2: { up_prioritize_irq(dmachan->irq, CONFIG_DMA_PRI); break; } -#endif /* CONFIG_STM32H7_DMA1 && CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_DMA2 */ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA case MDMA: { up_prioritize_irq(dmachan->irq, CONFIG_MDMA_PRI); break; } -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA case BDMA: { up_prioritize_irq(dmachan->irq, CONFIG_BDMA_PRI); break; } -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ default: { @@ -2666,7 +2666,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h index d8cfdc3524ed2..39b440be58eed 100644 --- a/arch/arm/src/stm32h7/stm32_dma.h +++ b/arch/arm/src/stm32h7/stm32_dma.h @@ -194,7 +194,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * Name: stm32_dmacapable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h7/stm32_dtcm.h b/arch/arm/src/stm32h7/stm32_dtcm.h index aba82326484b1..c55ded32e5700 100644 --- a/arch/arm/src/stm32h7/stm32_dtcm.h +++ b/arch/arm/src/stm32h7/stm32_dtcm.h @@ -50,7 +50,7 @@ * heap. */ -#ifndef CONFIG_STM32H7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 5288a3f2206ec..77092120e0659 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -40,7 +40,7 @@ /* Check CM4 core configuration */ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # if defined(CONFIG_ARMV7M_DCACHE) || defined(CONFIG_ARMV7M_DTCM) || \ defined(CONFIG_ARMV7M_ICACHE) # error Invalid configuration for CM4 core @@ -51,9 +51,9 @@ * Private Functions ****************************************************************************/ -#if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \ - defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) +#if (defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \ + defined(CONFIG_ARCH_CHIP_STM32_CORTEXM4) /**************************************************************************** * Name: stm32_cm4_boot @@ -77,7 +77,7 @@ static bool stm32_cm4_boot(void) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /**************************************************************************** * Name: stm32_cm4_busywait_lock_sem @@ -104,8 +104,8 @@ static void stm32_cpu2sem_wait(void) } #endif -#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_cm7_take_sem @@ -133,8 +133,8 @@ static void stm32_cpu2sem_take(void) * Public Functions ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32h7_start_cm4 @@ -162,7 +162,7 @@ void stm32h7_start_cm4(void) stm32_cpu2sem_take(); } -#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4 +#ifdef CONFIG_STM32_CORTEXM7_BOOTM4 else { /* CM4 not started at boot - force CM4 boot */ @@ -175,7 +175,7 @@ void stm32h7_start_cm4(void) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /**************************************************************************** * Name: stm32h7_waitfor_cm7 * diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index ab0524de3bf03..f8f84deddfc32 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -50,8 +50,8 @@ extern "C" #define EXTERN extern #endif -#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32h7_start_cm4 @@ -64,7 +64,7 @@ extern "C" void stm32h7_start_cm4(void); #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /**************************************************************************** * Name: stm32h7_waitfor_cm7 * diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 2787c840596ba..2ae195bf09bd5 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -68,12 +68,12 @@ #include -/* STM32H7_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if +/* STM32_NETHERNET determines the number of physical interfaces that can + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -81,7 +81,7 @@ /* Configuration ************************************************************/ -#if STM32H7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -95,9 +95,9 @@ /* Select work queue */ -# if defined(CONFIG_STM32H7_ETHMAC_HPWORK) +# if defined(CONFIG_STM32_ETHMAC_HPWORK) # define ETHWORK HPWORK -# elif defined(CONFIG_STM32H7_ETHMAC_LPWORK) +# elif defined(CONFIG_STM32_ETHMAC_LPWORK) # define ETHWORK LPWORK # else # define ETHWORK LPWORK @@ -105,136 +105,136 @@ #endif #if defined(CONFIG_ETH0_PHY_AM79C874) -# define STM32H7_PHYID1 MII_PHYID1_AM79C874 -# define STM32H7_PHYID2 MII_PHYID2_AM79C874 +# define STM32_PHYID1 MII_PHYID1_AM79C874 +# define STM32_PHYID2 MII_PHYID2_AM79C874 #elif defined(CONFIG_ETH0_PHY_AR8031) -# define STM32H7_PHYID1 MII_PHYID1_AR8031 -# define STM32H7_PHYID2 MII_PHYID2_AR8031 +# define STM32_PHYID1 MII_PHYID1_AR8031 +# define STM32_PHYID2 MII_PHYID2_AR8031 #elif defined(CONFIG_ETH0_PHY_KS8721) -# define STM32H7_PHYID1 MII_PHYID1_KS8721 -# define STM32H7_PHYID2 MII_PHYID2_KS8721 +# define STM32_PHYID1 MII_PHYID1_KS8721 +# define STM32_PHYID2 MII_PHYID2_KS8721 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8041 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8041 +# define STM32_PHYID1 MII_PHYID1_KSZ8041 +# define STM32_PHYID2 MII_PHYID2_KSZ8041 #elif defined(CONFIG_ETH0_PHY_KSZ8051) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8051 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8051 +# define STM32_PHYID1 MII_PHYID1_KSZ8051 +# define STM32_PHYID2 MII_PHYID2_KSZ8051 #elif defined(CONFIG_ETH0_PHY_KSZ8061) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8061 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8061 +# define STM32_PHYID1 MII_PHYID1_KSZ8061 +# define STM32_PHYID2 MII_PHYID2_KSZ8061 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8081 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8081 +# define STM32_PHYID1 MII_PHYID1_KSZ8081 +# define STM32_PHYID2 MII_PHYID2_KSZ8081 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define STM32H7_PHYID1 MII_PHYID1_DP83848C -# define STM32H7_PHYID2 MII_PHYID2_DP83848C +# define STM32_PHYID1 MII_PHYID1_DP83848C +# define STM32_PHYID2 MII_PHYID2_DP83848C #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define STM32H7_PHYID1 MII_PHYID1_DP83825I -# define STM32H7_PHYID2 MII_PHYID2_DP83825I +# define STM32_PHYID1 MII_PHYID1_DP83825I +# define STM32_PHYID2 MII_PHYID2_DP83825I #elif defined(CONFIG_ETH0_PHY_TJA1100) -# define STM32H7_PHYID1 MII_PHYID1_TJA1100 -# define STM32H7_PHYID2 MII_PHYID2_TJA1100 +# define STM32_PHYID1 MII_PHYID1_TJA1100 +# define STM32_PHYID2 MII_PHYID2_TJA1100 #elif defined(CONFIG_ETH0_PHY_TJA1101) -# define STM32H7_PHYID1 MII_PHYID1_TJA1101 -# define STM32H7_PHYID2 MII_PHYID2_TJA1101 +# define STM32_PHYID1 MII_PHYID1_TJA1101 +# define STM32_PHYID2 MII_PHYID2_TJA1101 #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define STM32H7_PHYID1 MII_PHYID1_TJA1103 -# define STM32H7_PHYID2 MII_PHYID2_TJA1103 +# define STM32_PHYID1 MII_PHYID1_TJA1103 +# define STM32_PHYID2 MII_PHYID2_TJA1103 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define STM32H7_PHYID1 MII_PHYID1_LAN8720 -# define STM32H7_PHYID2 MII_PHYID2_LAN8720 +# define STM32_PHYID1 MII_PHYID1_LAN8720 +# define STM32_PHYID2 MII_PHYID2_LAN8720 #elif defined(CONFIG_ETH0_PHY_LAN8740) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740 -# define STM32H7_PHYID2 MII_PHYID2_LAN8740 +# define STM32_PHYID1 MII_PHYID1_LAN8740 +# define STM32_PHYID2 MII_PHYID2_LAN8740 #elif defined(CONFIG_ETH0_PHY_LAN8740A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740A -# define STM32H7_PHYID2 MII_PHYID2_LAN8740A +# define STM32_PHYID1 MII_PHYID1_LAN8740A +# define STM32_PHYID2 MII_PHYID2_LAN8740A #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8742A -# define STM32H7_PHYID2 MII_PHYID2_LAN8742A +# define STM32_PHYID1 MII_PHYID1_LAN8742A +# define STM32_PHYID2 MII_PHYID2_LAN8742A #elif defined(CONFIG_ETH0_PHY_DM9161) -# define STM32H7_PHYID1 MII_PHYID1_DM9161 -# define STM32H7_PHYID2 MII_PHYID2_DM9161 +# define STM32_PHYID1 MII_PHYID1_DM9161 +# define STM32_PHYID2 MII_PHYID2_DM9161 #elif defined(CONFIG_ETH0_PHY_YT8512) -# define STM32H7_PHYID1 MII_PHYID1_YT8512 -# define STM32H7_PHYID2 MII_PHYID2_YT8512 +# define STM32_PHYID1 MII_PHYID1_YT8512 +# define STM32_PHYID2 MII_PHYID2_YT8512 #else # warning "No PHY specified!" #endif -#ifndef CONFIG_STM32H7_PHYADDR -# error "CONFIG_STM32H7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H7_MII) && !defined(CONFIG_STM32H7_RMII) -# warning "Neither CONFIG_STM32H7_MII nor CONFIG_STM32H7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H7_MII) && defined(CONFIG_STM32H7_RMII) -# error "Both CONFIG_STM32H7_MII and CONFIG_STM32H7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H7_MII -# if !defined(CONFIG_STM32H7_MII_MCO1) && !defined(CONFIG_STM32H7_MII_MCO2) && \ - !defined(CONFIG_STM32H7_MII_EXTCLK) -# warning "Neither CONFIG_STM32H7_MII_MCO1, CONFIG_STM32H7_MII_MCO2, nor CONFIG_STM32H7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_MII_MCO1) && defined(CONFIG_STM32H7_MII_MCO2) -# error "Both CONFIG_STM32H7_MII_MCO1 and CONFIG_STM32H7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_RMII -# if !defined(CONFIG_STM32H7_RMII_MCO1) && !defined(CONFIG_STM32H7_RMII_MCO2) && \ - !defined(CONFIG_STM32H7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H7_RMII_MCO1, CONFIG_STM32H7_RMII_MCO2, nor CONFIG_STM32H7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_RMII_MCO1) && defined(CONFIG_STM32H7_RMII_MCO2) -# error "Both CONFIG_STM32H7_RMII_MCO1 and CONFIG_STM32H7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_AUTONEG -# ifndef CONFIG_STM32H7_PHYSR -# error "CONFIG_STM32H7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H7_PHYSR_ALTMODE -# error "CONFIG_STM32H7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10HD -# error "CONFIG_STM32H7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100HD -# error "CONFIG_STM32H7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10FD -# error "CONFIG_STM32H7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100FD -# error "CONFIG_STM32H7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H7_PHYSR_SPEED -# error "CONFIG_STM32H7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100MBPS -# error "CONFIG_STM32H7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_MODE -# error "CONFIG_STM32H7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP -# warning "CONFIG_STM32H7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif -#undef CONFIG_STM32H7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -244,8 +244,8 @@ #define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15) -#ifdef CONFIG_STM32H7_ETH_BUFSIZE -# define ETH_BUFSIZE CONFIG_STM32H7_ETH_BUFSIZE +#ifdef CONFIG_STM32_ETH_BUFSIZE +# define ETH_BUFSIZE CONFIG_STM32_ETH_BUFSIZE #else # define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE #endif @@ -262,16 +262,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H7_ETH_NRXDESC -# define CONFIG_STM32H7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H7_ETH_NTXDESC -# define CONFIG_STM32H7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -289,21 +289,21 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -394,7 +394,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H7_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -409,7 +409,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -558,10 +558,10 @@ #define MTLRXQOMR_SET_MASK \ ((0x7 << ETH_MTLRXQOMR_RQS_SHIFT) | ETH_MTLRXQOMR_RTC_64) -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* TODO */ -# error CONFIG_STM32H7_ETH_HWCHECKSUM not supported +# error CONFIG_STM32_ETH_HWCHECKSUM not supported #endif /* Clear the DMAMR bits that will be setup during MAC initialization (or that @@ -723,7 +723,7 @@ aligned_data(ARMV7M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -731,7 +731,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -803,7 +803,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -812,17 +812,17 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv); static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -852,7 +852,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -924,7 +924,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -951,7 +951,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1093,10 +1093,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC + - CONFIG_STM32H7_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1313,7 +1313,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1379,7 +1379,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1452,7 +1452,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1578,10 +1578,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC + - CONFIG_STM32H7_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1732,8 +1732,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -2831,7 +2831,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2867,7 +2867,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2920,7 +2920,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2953,7 +2953,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2961,7 +2961,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H7_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2997,7 +2997,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -3027,7 +3027,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3062,7 +3062,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3119,7 +3119,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3142,7 +3142,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, 16, &phyval); + CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3176,7 +3176,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv) { uint16_t phyval; @@ -3186,7 +3186,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) for (i = 0; i < 0x20; i++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, i, &phyval); + CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3217,7 +3217,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3240,7 +3240,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_RESET); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3254,7 +3254,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) to -= 10; phyval = 0xffff; ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, &phyval); + CONFIG_STM32_PHYADDR, MII_MCR, &phyval); ninfo("MII_MCR: phyval: %u ret: %d\n", phyval, ret); } @@ -3271,7 +3271,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) } ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { @@ -3279,17 +3279,17 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if (phyval != STM32H7_PHYID1) + if (phyval != STM32_PHYID1) { nerr("ERROR: Incorrect PHYID1: %u expected: %u\n", - phyval, STM32H7_PHYID1); + phyval, STM32_PHYID1); return -ENXIO; } ninfo("MII_PHYID1: phyval: %u ret: %d\n", phyval, ret); ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID2, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID2, &phyval); if (ret < 0) { @@ -3297,16 +3297,16 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if ((phyval & 0xfff0) != (STM32H7_PHYID2 & 0xfff0)) + if ((phyval & 0xfff0) != (STM32_PHYID2 & 0xfff0)) { nerr("ERROR: Incorrect PHYID2: %u expected: %u\n", - phyval, STM32H7_PHYID2); + phyval, STM32_PHYID2); return -ENXIO; } ninfo("MII_PHYID2: phyval: %u ret: %d\n", phyval, ret); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(priv); #endif @@ -3322,13 +3322,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3352,7 +3352,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3364,7 +3364,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3387,7 +3387,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, CONFIG_STM32H7_PHYSR, &phyval); + CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3396,38 +3396,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H7_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3440,13 +3440,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == - CONFIG_STM32H7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H7_PHYSR_SPEED) == CONFIG_STM32H7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3455,14 +3455,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3473,10 +3473,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3504,7 +3504,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3530,7 +3530,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3562,17 +3562,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H7_MII) || defined(CONFIG_STM32H7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H7_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3587,7 +3587,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3595,7 +3595,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3603,7 +3603,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3634,7 +3634,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3649,7 +3649,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3657,7 +3657,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3665,7 +3665,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3688,7 +3688,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4027,7 +4027,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4050,24 +4050,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H7_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4120,7 +4120,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4135,7 +4135,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4190,7 +4190,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4216,7 +4216,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4231,11 +4231,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 6f7026bacacad..347beebab6677 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H7_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/stm32_exti_gpio.c b/arch/arm/src/stm32h7/stm32_exti_gpio.c index 4b27006a665d3..74c8e812fc432 100644 --- a/arch/arm/src/stm32h7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32h7/stm32_exti_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Types @@ -378,4 +378,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index 459f0204a8b90..15eecf55a7ec6 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -90,9 +90,9 @@ * critical Rx/Tx transactions on the CAN bus. */ -# if defined(CONFIG_STM32H7_FDCAN_HPWORK) +# if defined(CONFIG_STM32_FDCAN_HPWORK) # define CANWORK HPWORK -# elif defined(CONFIG_STM32H7_FDCAN_LPWORK) +# elif defined(CONFIG_STM32_FDCAN_LPWORK) # define CANWORK LPWORK # else # define CANWORK LPWORK @@ -326,7 +326,7 @@ struct fdcan_message_ram /* FDCAN device structures **************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static const struct fdcan_config_s stm32_fdcan0_config = { .tx_pin = GPIO_CAN1_TX, @@ -339,7 +339,7 @@ static const struct fdcan_config_s stm32_fdcan0_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static const struct fdcan_config_s stm32_fdcan1_config = { .tx_pin = GPIO_CAN2_TX, @@ -352,7 +352,7 @@ static const struct fdcan_config_s stm32_fdcan1_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static const struct fdcan_config_s stm32_fdcan2_config = { .tx_pin = GPIO_CAN3_TX, @@ -411,15 +411,15 @@ struct fdcan_driver_s * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static struct fdcan_driver_s g_fdcan0; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static struct fdcan_driver_s g_fdcan1; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static struct fdcan_driver_s g_fdcan2; #endif @@ -437,7 +437,7 @@ static int fdcan_txpoll(struct net_driver_s *dev); /* Helper functions */ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv); #endif @@ -511,7 +511,7 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable); * Dump common register values to the console for debugging purposes. ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv) { printf("-------------- FDCAN Reg Dump ----------------\n"); @@ -685,7 +685,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -1803,7 +1803,7 @@ static int fdcan_ifup(struct net_driver_s *dev) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2092,7 +2092,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG const struct fdcan_bitseg *tim = &priv->arbi_timing; ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2116,7 +2116,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG tim = &priv->data_timing; ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2136,14 +2136,14 @@ int fdcan_initialize(struct fdcan_driver_s *priv) /* Operation Configuration */ -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK +#ifdef CONFIG_STM32_FDCAN_LOOPBACK /* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST); modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK); #endif -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK_INTERNAL +#ifdef CONFIG_STM32_FDCAN_LOOPBACK_INTERNAL /* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON); @@ -2331,7 +2331,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */ putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2339,7 +2339,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2395,7 +2395,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_RX_FIFO0; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]); #endif priv->rx[i].header.w1 = 0x0; @@ -2411,7 +2411,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_TX_FIFO; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]); #endif priv->tx[i].header.w1 = 0x0; @@ -2458,7 +2458,7 @@ int stm32_fdcansockinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 case 0: priv = &g_fdcan0; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2477,7 +2477,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 case 1: priv = &g_fdcan1; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2496,7 +2496,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 case 2: priv = &g_fdcan2; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2579,7 +2579,7 @@ int stm32_fdcansockinitialize(int intf) netdev_register(&priv->dev, NET_LL_CAN); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2600,15 +2600,15 @@ int stm32_fdcansockinitialize(int intf) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 stm32_fdcansockinitialize(2); #endif } diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.h b/arch/arm/src/stm32h7/stm32_fdcan_sock.h index 0c92ea109aebd..f5f66c31090de 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.h +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.h @@ -31,7 +31,7 @@ #include "hardware/stm32_fdcan.h" -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /**************************************************************************** * Pre-processor Definitions @@ -105,5 +105,5 @@ int stm32_fdcansockinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_FDCAN */ +#endif /* CONFIG_STM32_FDCAN */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */ diff --git a/arch/arm/src/stm32h7/stm32_flash.c b/arch/arm/src/stm32h7/stm32_flash.c index 3a963bbc22bd4..c9afb10a3626d 100644 --- a/arch/arm/src/stm32h7/stm32_flash.c +++ b/arch/arm/src/stm32h7/stm32_flash.c @@ -26,15 +26,15 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7b3xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h743xx_flash.c" #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 841f2e6452567..1b790354b1801 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H7_FMC) +#if defined(CONFIG_STM32_FMC) #include "stm32.h" @@ -41,7 +41,7 @@ /**************************************************************************** * To use FMC, you must first enable it in configuration: * - * CONFIG_STM32H7_FMC=y + * CONFIG_STM32_FMC=y * * FMC is statically configured at startup. Its configuration is adjusted * using BOARD_XXX macros described below, which should be declared @@ -549,4 +549,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(cmd, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32H7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8f59ef8b8a8c9..77bcccbc4ea66 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Data @@ -62,47 +62,47 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32H7_NGPIO > 5 -# if defined(CONFIG_STM32H7_HAVE_GPIOF) +#if STM32_NGPIO > 5 +# if defined(CONFIG_STM32_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 6 -# if defined(CONFIG_STM32H7_HAVE_GPIOG) +#if STM32_NGPIO > 6 +# if defined(CONFIG_STM32_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -163,7 +163,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -443,7 +443,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -485,7 +485,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -526,7 +526,7 @@ bool stm32_gpioread(uint32_t pinset) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void) { /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit @@ -543,4 +543,4 @@ void stm32_iocompensation(void) } #endif -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 02a644c3290bf..18ce28cc321ea 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -184,37 +184,37 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ #endif @@ -262,7 +262,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes @@ -350,7 +350,7 @@ bool stm32_gpioread(uint32_t pinset); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void); #endif diff --git a/arch/arm/src/stm32h7/stm32_hsem.c b/arch/arm/src/stm32h7/stm32_hsem.c index 480223220f3fc..401591f477a51 100644 --- a/arch/arm/src/stm32h7/stm32_hsem.c +++ b/arch/arm/src/stm32h7/stm32_hsem.c @@ -234,7 +234,7 @@ bool stm32_hsem_take(uint8_t id) /* Take semaphore */ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 return (getreg32(STM32_HSEM_RLRX(id)) == ((HSEM_COREID_CPU1 << HSEM_SEMX_COREID_SHIFT) | HSEM_SEMX_LOCK)); #else @@ -253,7 +253,7 @@ bool stm32_hsem_take(uint8_t id) void stm32_hsem_free(uint8_t id) { -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 putreg32((HSEM_COREID_CPU1 << HSEM_CR_COREID_SHIFT) , STM32_HSEM_RX(id)); #else putreg32((HSEM_COREID_CPU2 << HSEM_CR_COREID_SHIFT) , STM32_HSEM_RX(id)); @@ -278,7 +278,7 @@ void stm32_hsem_init(void) /* Set block id */ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 dev->block = 0; dev->irq = STM32_IRQ_HSEM0; #else diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 9b7cdc9df2f87..e01dd136a21bc 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -156,28 +156,28 @@ * * One of: * - * CONFIG_STM32H7_STM32H7X3XX + * CONFIG_STM32_STM32H7X3XX * * and one or more interfaces: * - * CONFIG_STM32H7_I2C1 - * CONFIG_STM32H7_I2C2 - * CONFIG_STM32H7_I2C3 - * CONFIG_STM32H7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -225,8 +225,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) || defined(CONFIG_STM32H7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -234,14 +234,14 @@ #undef INVALID_CLOCK_SOURCE -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) # if STM32_RCC_D2CCIP2R_I2C123SRC != RCC_D2CCIP2R_I2C123SEL_HSI # warning "Clock Source STM32_RCC_D2CCIP2R_I2C123SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_D3CCIPR_I2C4SRC != RCC_D3CCIPR_I2C4SEL_HSI # warning "Clock Source STM32_RCC_D3CCIPR_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -258,25 +258,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H7_I2CTIMEOSEC) && !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 -# define CONFIG_STM32H7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H7_I2CTIMEOSEC) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H7_I2CTIMEOTICKS -# define CONFIG_STM32H7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -446,9 +446,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -524,7 +524,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -596,7 +596,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -726,7 +726,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -743,7 +743,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -799,12 +799,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -842,10 +842,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2715,22 +2715,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2816,5 +2816,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H7_I2C1 || CONFIG_STM32H7_I2C2 || \ - * CONFIG_STM32H7_I2C3 || CONFIG_STM32H7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h7/stm32_i2c.h b/arch/arm/src/stm32h7/stm32_i2c.h index ae507efe60351..78dc96b1ba537 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.h +++ b/arch/arm/src/stm32h7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO -# if CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H7_I2C_DYNTIMEO because of CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_irq.c b/arch/arm/src/stm32h7/stm32_irq.c index 2bcf4b9cc7e68..37da642357f29 100644 --- a/arch/arm/src/stm32h7/stm32_irq.c +++ b/arch/arm/src/stm32h7/stm32_irq.c @@ -40,7 +40,7 @@ #include "ram_vectors.h" #include "arm_internal.h" -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ # include "stm32_gpio.h" #endif @@ -404,7 +404,7 @@ void up_irqinitialize(void) * GPIO pins. */ -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ stm32_gpioirqinitialize(); #endif @@ -448,7 +448,7 @@ void up_disable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ @@ -495,7 +495,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } } -#ifdef CONFIG_STM32H7_GPIO_IRQ +#ifdef CONFIG_STM32_GPIO_IRQ else { /* Maybe it is a (derived) GPIO IRQ */ diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index 13150c3943150..299b40ae68e4a 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -41,7 +41,7 @@ #include "stm32_rcc.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -69,12 +69,12 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_IWDG_DEFTIMOUT -# define CONFIG_STM32H7_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32H7_IWDG_REGDEBUG +# undef CONFIG_STM32_IWDG_REGDEBUG #endif /* REVISIT: It appears that you can only setup the prescaler and reload @@ -83,19 +83,19 @@ * is started, then refuse any further attempts to change timeout. */ -#define CONFIG_STM32H7_IWDG_ONETIMESETUP 1 +#define CONFIG_STM32_IWDG_ONETIMESETUP 1 /* REVISIT: Another possibility is that we CAN change the prescaler and * reload values after starting the timer. This option is untested but the * implementation place conditioned on the following: */ -#undef CONFIG_STM32H7_IWDG_DEFERREDSETUP +#undef CONFIG_STM32_IWDG_DEFERREDSETUP /* But you can only try one at a time */ -#if defined(CONFIG_STM32H7_IWDG_ONETIMESETUP) && defined(CONFIG_STM32H7_IWDG_DEFERREDSETUP) -# error "Both CONFIG_STM32H7_IWDG_ONETIMESETUP and CONFIG_STM32H7_IWDG_DEFERREDSETUP are defined" +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) && defined(CONFIG_STM32_IWDG_DEFERREDSETUP) +# error "Both CONFIG_STM32_IWDG_ONETIMESETUP and CONFIG_STM32_IWDG_DEFERREDSETUP are defined" #endif /**************************************************************************** @@ -124,7 +124,7 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -177,7 +177,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -240,7 +240,7 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -280,7 +280,7 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) * be necessary. */ -#ifndef CONFIG_STM32H7_IWDG_ONETIMESETUP +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); #endif @@ -335,7 +335,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) * starting the watchdog timer. */ -#if defined(CONFIG_STM32H7_IWDG_ONETIMESETUP) || defined(CONFIG_STM32H7_IWDG_DEFERREDSETUP) +#if defined(CONFIG_STM32_IWDG_ONETIMESETUP) || defined(CONFIG_STM32_IWDG_DEFERREDSETUP) stm32_setprescaler(priv); #endif @@ -512,7 +512,7 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, * to zero. */ -#ifdef CONFIG_STM32H7_IWDG_ONETIMESETUP +#ifdef CONFIG_STM32_IWDG_ONETIMESETUP if (priv->started) { wdwarn("WARNING: Timer is already started\n"); @@ -597,12 +597,12 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, * to zero. */ -#ifndef CONFIG_STM32H7_IWDG_ONETIMESETUP - /* If CONFIG_STM32H7_IWDG_DEFERREDSETUP is selected, then perform the +#ifndef CONFIG_STM32_IWDG_ONETIMESETUP + /* If CONFIG_STM32_IWDG_DEFERREDSETUP is selected, then perform the * register configuration only if the timer has been started. */ -#ifdef CONFIG_STM32H7_IWDG_DEFERREDSETUP +#ifdef CONFIG_STM32_IWDG_DEFERREDSETUP if (priv->started) #endif { @@ -670,7 +670,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32H7_IWDG_DEFTIMOUT); + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -681,9 +681,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB4_FZ1); cr |= DBGMCU_APB4_WDGLSD1; @@ -692,4 +692,4 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32h7/stm32_lptim.c b/arch/arm/src/stm32h7/stm32_lptim.c index daa7bc8029f3f..958243f7631c5 100644 --- a/arch/arm/src/stm32h7/stm32_lptim.c +++ b/arch/arm/src/stm32h7/stm32_lptim.c @@ -43,9 +43,9 @@ #include "stm32_gpio.h" #include "stm32_lptim.h" -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) || \ - defined(CONFIG_STM32H7_LPTIM3) || defined(CONFIG_STM32H7_LPTIM4) || \ - defined(CONFIG_STM32H7_LPTIM5) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ + defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ + defined(CONFIG_STM32_LPTIM5) /**************************************************************************** * Private Function prototypes @@ -103,35 +103,35 @@ static const struct stm32_lptim_ops_s stm32_lptim_ops = .ackint = &stm32_lptim_ackint }; -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 struct stm32_lptim_dev_s stm32_lptim1_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 struct stm32_lptim_dev_s stm32_lptim2_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM2_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 struct stm32_lptim_dev_s stm32_lptim3_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM3_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 struct stm32_lptim_dev_s stm32_lptim4_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM4_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 struct stm32_lptim_dev_s stm32_lptim5_priv = { .ops = &stm32_lptim_ops, @@ -205,7 +205,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, { switch (dev->base) { -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM1_BASE: case STM32_LPTIM2_BASE: if (input == 0) @@ -221,7 +221,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, LPTIM_CFGR2_IN1SEL_MASK, mux); @@ -301,27 +301,27 @@ static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: vectorno = STM32_IRQ_LPTIM1; break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: vectorno = STM32_IRQ_LPTIM2; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: vectorno = STM32_IRQ_LPTIM3; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: vectorno = STM32_IRQ_LPTIM4; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: vectorno = STM32_IRQ_LPTIM5; break; @@ -391,31 +391,31 @@ struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) switch (lptimer) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case 1: dev = &stm32_lptim1_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_LPTIM1EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case 2: dev = &stm32_lptim2_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM2EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case 3: dev = &stm32_lptim3_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM3EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case 4: dev = &stm32_lptim4_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM4EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case 5: dev = &stm32_lptim5_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM5EN); @@ -436,27 +436,27 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1LLPENR, RCC_APB1LENR_LPTIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM5EN, 0); break; @@ -468,4 +468,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_LPTIM1 || ... || CONFIG_STM32H7_LPTIM5) */ +#endif /* defined(CONFIG_STM32_LPTIM1 || ... || CONFIG_STM32_LPTIM5) */ diff --git a/arch/arm/src/stm32h7/stm32_lse.c b/arch/arm/src/stm32h7/stm32_lse.c index e55b9936798be..0fdfaf611c744 100644 --- a/arch/arm/src/stm32h7/stm32_lse.c +++ b/arch/arm/src/stm32h7/stm32_lse.c @@ -42,16 +42,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -96,7 +96,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif const uint32_t *drives = drives_rev_y; @@ -131,18 +131,18 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable off */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -170,7 +170,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -179,13 +179,13 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives_rev_y) / sizeof(drives_rev_y[0])); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 79f6ac0f0de04..3f0578227a0eb 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -127,8 +127,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32H7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -136,23 +136,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32H7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -163,24 +163,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32H7_LTDC_L2 -# if defined(CONFIG_STM32H7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -188,7 +188,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -208,43 +208,43 @@ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT * 2) #else #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifndef CONFIG_STM32H7_LTDC_L2_WIDTH -# define CONFIG_STM32H7_LTDC_L2_WIDTH STM32_LTDC_WIDTH +#ifdef CONFIG_STM32_LTDC_L2 +# ifndef CONFIG_STM32_LTDC_L2_WIDTH +# define CONFIG_STM32_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif -# if CONFIG_STM32H7_LTDC_L2_WIDTH > STM32_LTDC_WIDTH +# if CONFIG_STM32_LTDC_L2_WIDTH > STM32_LTDC_WIDTH # error Width of Layer 2 exceeds the width of the display # endif -# ifndef CONFIG_STM32H7_LTDC_L2_HEIGHT -# define CONFIG_STM32H7_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT +# ifndef CONFIG_STM32_LTDC_L2_HEIGHT +# define CONFIG_STM32_LTDC_L2_HEIGHT STM32_LTDC_HEIGHT # endif -# if CONFIG_STM32H7_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT +# if CONFIG_STM32_LTDC_L2_HEIGHT > STM32_LTDC_HEIGHT # error Height of Layer 2 exceeds the height of the display # endif # if STM32_LTDC_L2_BPP == 8 -# define STM32_LTDC_L2_STRIDE (CONFIG_STM32H7_LTDC_L2_WIDTH) +# define STM32_LTDC_L2_STRIDE (CONFIG_STM32_LTDC_L2_WIDTH) # elif STM32_LTDC_L2_BPP == 16 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 16 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 16 + 7) / 8) # elif STM32_LTDC_L2_BPP == 24 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 24 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 24 + 7) / 8) # elif STM32_LTDC_L2_BPP == 32 -# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32H7_LTDC_L2_WIDTH * 32 + 7) / 8) +# define STM32_LTDC_L2_STRIDE ((CONFIG_STM32_LTDC_L2_WIDTH * 32 + 7) / 8) # else # error Undefined or unrecognized base resolution # endif # define STM32_LTDC_L2_FBSIZE (STM32_LTDC_L2_STRIDE * \ - CONFIG_STM32H7_LTDC_L2_HEIGHT) + CONFIG_STM32_LTDC_L2_HEIGHT) #else # define STM32_LTDC_L2_FBSIZE (0) @@ -258,7 +258,7 @@ /* Debug option */ -#ifdef CONFIG_STM32H7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -273,10 +273,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32H7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32H7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -289,7 +289,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -299,7 +299,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -307,27 +307,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32H7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32H7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32H7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32H7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32H7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -335,63 +335,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32H7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32H7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32H7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32H7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32H7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32H7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32H7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32H7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32H7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32H7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32H7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32H7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifdef CONFIG_STM32H7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32H7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -425,28 +425,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32H7_DMA2D -# if defined(CONFIG_STM32H7_LTDC_L1_L8) || \ - defined(CONFIG_STM32H7_LTDC_L2_L8) -# if !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32H7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32H7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -454,12 +454,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32H7_FB_CMAP -# if defined(CONFIG_STM32H7_DMA2D) && !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -467,7 +467,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -475,7 +475,7 @@ # endif #endif -#ifndef CONFIG_STM32H7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -512,9 +512,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -522,9 +522,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -532,34 +532,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -585,7 +585,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -618,7 +618,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -643,7 +643,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -651,7 +651,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -699,7 +699,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -708,7 +708,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -731,7 +731,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -746,7 +746,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, static int stm32_waitforvsync(struct fb_vtable_s *vtable); #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo); #endif @@ -806,16 +806,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC semaphore that enforces mutually exclusive access */ @@ -847,12 +847,12 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) , .pandisplay = stm32_pandisplay #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -873,7 +873,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -901,7 +901,7 @@ static struct stm32_ltdcdev_s g_vtable = .display = 0, .bpp = STM32_LTDC_L1_BPP, .xres_virtual = STM32_LTDC_WIDTH, -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) .yres_virtual = STM32_LTDC_HEIGHT * 2, #else .yres_virtual = STM32_LTDC_HEIGHT, @@ -919,9 +919,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -929,7 +929,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -965,7 +965,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -977,7 +977,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -1009,7 +1009,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1031,7 +1031,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1041,7 +1041,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1051,7 +1051,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1061,7 +1061,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1071,7 +1071,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1081,7 +1081,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1091,7 +1091,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1101,7 +1101,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1111,7 +1111,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1121,7 +1121,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1133,7 +1133,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1143,7 +1143,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1153,7 +1153,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1163,7 +1163,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1173,7 +1173,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1183,7 +1183,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1193,7 +1193,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1203,7 +1203,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1213,7 +1213,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1223,7 +1223,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1233,22 +1233,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1501,7 +1501,7 @@ static int stm32_ltdcirq(int irq, void *context, void *arg) putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); priv->error = OK; -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) fb_remove_paninfo(&g_vtable.vtable, FB_NO_OVERLAY); #endif } @@ -1681,7 +1681,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32H7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1953,7 +1953,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -2023,7 +2023,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { uint32_t regval; @@ -2127,7 +2127,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2136,7 +2136,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2176,7 +2176,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2187,7 +2187,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2247,7 +2247,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2287,7 +2287,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2323,7 +2323,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2410,7 +2410,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2440,7 +2440,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2530,7 +2530,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2542,7 +2542,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2570,7 +2570,7 @@ static int stm32_waitforvsync(struct fb_vtable_s *vtable) * Description: * Entrypoint ioctl FBIOPAN_DISPLAY ****************************************************************************/ -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo) { @@ -2647,7 +2647,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2694,14 +2694,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2709,7 +2709,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxsem_wait(layer->lock); -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2729,7 +2729,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxsem_post(layer->lock); return ret; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2757,7 +2757,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2817,7 +2817,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2851,7 +2851,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; @@ -2885,7 +2885,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2944,7 +2944,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3055,7 +3055,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3071,31 +3071,31 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ -#ifdef CONFIG_STM32H7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT stm32_backlight(true); #endif @@ -3181,10 +3181,10 @@ void stm32_ltdcuninitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32H7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32h7/stm32_ltdc.h b/arch/arm/src/stm32h7/stm32_ltdc.h index 53a73da7d08bb..93d0ed6531edb 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.h +++ b/arch/arm/src/stm32h7/stm32_ltdc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H +#define __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H /**************************************************************************** * Included Files @@ -99,4 +99,4 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); #ifdef CONFIG_STM32F7_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32h7/stm32_mdio.c b/arch/arm/src/stm32h7/stm32_mdio.c index d524b27ce1f6e..412aedcb915d5 100644 --- a/arch/arm/src/stm32h7/stm32_mdio.c +++ b/arch/arm/src/stm32h7/stm32_mdio.c @@ -30,7 +30,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 91d78295bb85c..a141895b21020 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -44,9 +44,9 @@ ****************************************************************************/ #ifdef CONFIG_RPTUN -# ifdef CONFIG_STM32H7_SHMEM_SRAM3 +# ifdef CONFIG_STM32_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE -# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE +# define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else # error missing shmem MPU configuration # endif diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/stm32h7/stm32_oneshot.c index 078d6efe50236..e1fc56718ec77 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/stm32h7/stm32_oneshot.c @@ -39,7 +39,7 @@ #include "stm32_oneshot.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32H7_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32H7_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32H7_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -401,4 +401,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h index 412f901e16b4b..f16523985ff1f 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ b/arch/arm/src/stm32h7/stm32_oneshot.h @@ -36,22 +36,22 @@ #include "stm32_tim.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32H7_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -193,5 +193,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 131be78c428de..a847ccf74c0eb 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -37,21 +37,21 @@ #include "stm32_rcc.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ - !defined(CONFIG_STM32H7_HSI48) + !defined(CONFIG_STM32_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ - enabled. Enable STM32H7_HSI48 + enabled. Enable STM32_HSI48 #endif -#if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS) && !defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) # error OTG HS selected but no ULPI enabled #endif -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) && \ - !defined(CONFIG_STM32H7_SYSCFG_IOCOMPENSATION) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) && \ + !defined(CONFIG_STM32_SYSCFG_IOCOMPENSATION) # error External ULPI needs IOCOMPENSATION enabled #endif @@ -126,7 +126,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller); struct usbdev_s; void stm32_usbsuspend(struct usbdev_s *dev, bool resume); -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * @@ -145,5 +145,5 @@ void stm32_usbulpireset(struct usbdev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 22e1774b527f7..d185b987a03fc 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -53,8 +53,8 @@ #include "stm32_otg.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32H7_OTGFS) || \ - defined(CONFIG_STM32H7_OTGHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGHS)) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* OTG device selection *****************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -70,7 +70,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE # define GPIO_OTG_DM GPIO_OTGHS_DM @@ -82,7 +82,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) && defined(CONFIG_STM32_OTGHS_USBDEV) # error Only one USBDEV role supported #endif @@ -552,7 +552,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -879,7 +879,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -942,7 +942,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2138,8 +2138,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -3447,7 +3447,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= OTG_GUSBCFG_TRDT(9); #else regval |= OTG_GUSBCFG_TRDT(6); @@ -5289,9 +5289,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Full speed serial transceiver select */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5299,9 +5299,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GUSBCFG); #endif -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* ULPI Full speed mode */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5343,9 +5343,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Enable USB FS transceiver */ regval |= OTG_GCCFG_PWRDWN; @@ -5360,8 +5360,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GCCFG); up_mdelay(20); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable delay to default timing, necessary for some ULPI PHYs such * as such as USB334x */ @@ -5404,10 +5404,10 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) regval |= OTG_DCFG_DSPD_FSHS; -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) regval |= OTG_DCFG_DSPD_HS; #else regval |= OTG_DCFG_DSPD_FS; @@ -5550,8 +5550,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must * be done because if both the ULPI and the FS PHY clock enable bits * are set at the same time, the ARM never awakens from WFI due to @@ -5636,7 +5636,7 @@ void arm_usbinitialize(void) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5660,8 +5660,8 @@ void arm_usbinitialize(void) * current detection. */ -#if !(defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)) +#if !(defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI)) /* Configure OTG alternate function pins */ stm32_configgpio(GPIO_OTG_DM); @@ -5674,7 +5674,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5866,7 +5866,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) stm32_pullup(&priv->usbdev, true); -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -5938,4 +5938,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32H7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGDEV */ diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 095f220418301..a192ab25ea6da 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* OTG host selection *******************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -76,7 +76,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_HOST) +#elif defined(CONFIG_STM32_OTGHS_HOST) # error OTGHS HOST role not supported yet # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE @@ -89,7 +89,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_HOST) # error Only one HOST role supported #endif @@ -100,61 +100,61 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 - * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32H7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32H7_SYSCFG -# error "CONFIG_STM32H7_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32H7_OTG_RXFIFO_SIZE -# define CONFIG_STM32H7_OTG_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTG_RXFIFO_SIZE +# define CONFIG_STM32_OTG_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32H7_OTG_NPTXFIFO_SIZE -# define CONFIG_STM32H7_OTG_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32_OTG_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32H7_OTG_PTXFIFO_SIZE -# define CONFIG_STM32H7_OTG_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTG_PTXFIFO_SIZE +# define CONFIG_STM32_OTG_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32H7_OTG_DESCSIZE -# define CONFIG_STM32H7_OTG_DESCSIZE 128 +#ifndef CONFIG_STM32_OTG_DESCSIZE +# define CONFIG_STM32_OTG_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32H7_USBHOST_REGDEBUG -# undef CONFIG_STM32H7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -299,7 +299,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -312,7 +312,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -407,7 +407,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); @@ -523,7 +523,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -538,7 +538,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -602,7 +602,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -624,7 +624,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -3013,7 +3013,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3581,7 +3581,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR if ((pending & OTG_GINT_SOF) != 0) { usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); @@ -3747,7 +3747,7 @@ static inline void stm32_hostinit_enable(void) * OTG_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32H7_OTG_SOFINTR +#ifdef CONFIG_STM32_OTG_SOFINTR regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); #else @@ -4274,7 +4274,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32H7_OTG_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTG_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4283,7 +4283,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32H7_OTG_DESCSIZE; + *maxlen = CONFIG_STM32_OTG_DESCSIZE; return OK; } @@ -5150,21 +5150,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32H7_OTG_RXFIFO_SIZE); - offset = CONFIG_STM32H7_OTG_RXFIFO_SIZE; + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32_OTG_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32H7_OTG_NPTXFIFO_SIZE << + (CONFIG_STM32_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); - offset += CONFIG_STM32H7_OTG_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTG_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32H7_OTG_PTXFIFO_SIZE << + (CONFIG_STM32_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTG_HPTXFSIZ, regval); @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5458,7 +5458,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5484,4 +5484,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32h7/stm32_pulsecount.c b/arch/arm/src/stm32h7/stm32_pulsecount.c index f0a5189aba06b..b963fbf02cd4c 100644 --- a/arch/arm/src/stm32h7/stm32_pulsecount.c +++ b/arch/arm/src/stm32h7/stm32_pulsecount.c @@ -83,7 +83,7 @@ /* Advanced timer support */ -# if defined(CONFIG_STM32H7_TIM1_PULSECOUNT) || defined(CONFIG_STM32H7_TIM8_PULSECOUNT) +# if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) # endif /* Synchronisation support */ @@ -191,10 +191,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -221,107 +221,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -332,7 +332,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -340,7 +340,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1332,21 +1332,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1419,7 +1419,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1428,7 +1428,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1611,7 +1611,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1620,7 +1620,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1782,7 +1782,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1792,7 +1792,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index d2dc3b4f06e8d..70b434b741b99 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -49,7 +49,7 @@ * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -171,16 +171,16 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32H7_TIM1_BREAK1) || defined(CONFIG_STM32H7_TIM1_BREAK2) || \ - defined(CONFIG_STM32H7_TIM8_BREAK1) || defined(CONFIG_STM32H7_TIM8_BREAK2) || \ - defined(CONFIG_STM32H7_TIM15_BREAK1) || defined(CONFIG_STM32H7_TIM16_BREAK1) || \ - defined(CONFIG_STM32H7_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -243,7 +243,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -316,10 +316,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -356,7 +356,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -379,138 +379,138 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32H7_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H7_TIM1_BRK2POL, - .flt2 = CONFIG_STM32H7_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1POL, - .idle = CONFIG_STM32H7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1NPOL, - .idle = CONFIG_STM32H7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM1_CH2MODE, -#ifdef CONFIG_STM32H7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2POL, - .idle = CONFIG_STM32H7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2NPOL, - .idle = CONFIG_STM32H7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM1_CH3MODE, -#ifdef CONFIG_STM32H7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3POL, - .idle = CONFIG_STM32H7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3NPOL, - .idle = CONFIG_STM32H7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM1_CH4MODE, -#ifdef CONFIG_STM32H7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH4POL, - .idle = CONFIG_STM32H7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM1_CH5MODE, -#ifdef CONFIG_STM32H7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH5POL, - .idle = CONFIG_STM32H7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM1_CH6MODE, -#ifdef CONFIG_STM32H7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH6POL, - .idle = CONFIG_STM32H7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -521,18 +521,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H7_TIM1_MODE, - .lock = CONFIG_STM32H7_TIM1_LOCK, - .t_dts = CONFIG_STM32H7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -540,72 +540,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM2_CH1MODE, -#ifdef CONFIG_STM32H7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH1POL, - .idle = CONFIG_STM32H7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM2_CH2MODE, -#ifdef CONFIG_STM32H7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH2POL, - .idle = CONFIG_STM32H7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM2_CH3MODE, -#ifdef CONFIG_STM32H7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH3POL, - .idle = CONFIG_STM32H7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM2_CH4MODE, -#ifdef CONFIG_STM32H7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH4POL, - .idle = CONFIG_STM32H7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -617,14 +617,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -636,72 +636,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM3_CH1MODE, -#ifdef CONFIG_STM32H7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH1POL, - .idle = CONFIG_STM32H7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM3_CH2MODE, -#ifdef CONFIG_STM32H7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH2POL, - .idle = CONFIG_STM32H7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM3_CH3MODE, -#ifdef CONFIG_STM32H7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH3POL, - .idle = CONFIG_STM32H7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM3_CH4MODE, -#ifdef CONFIG_STM32H7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH4POL, - .idle = CONFIG_STM32H7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -713,14 +713,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -732,72 +732,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM4_CH1MODE, -#ifdef CONFIG_STM32H7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH1POL, - .idle = CONFIG_STM32H7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM4_CH2MODE, -#ifdef CONFIG_STM32H7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH2POL, - .idle = CONFIG_STM32H7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM4_CH3MODE, -#ifdef CONFIG_STM32H7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH3POL, - .idle = CONFIG_STM32H7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM4_CH4MODE, -#ifdef CONFIG_STM32H7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH4POL, - .idle = CONFIG_STM32H7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -809,14 +809,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -828,71 +828,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM5_CH1MODE, -#ifdef CONFIG_STM32H7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH1POL, - .idle = CONFIG_STM32H7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM5_CH2MODE, -#ifdef CONFIG_STM32H7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH2POL, - .idle = CONFIG_STM32H7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM5_CH3MODE, -#ifdef CONFIG_STM32H7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH3POL, - .idle = CONFIG_STM32H7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM5_CH4MODE, -#ifdef CONFIG_STM32H7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH4POL, - .idle = CONFIG_STM32H7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -903,14 +903,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -922,140 +922,140 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32H7_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32H7_TIM8_BRK2POL, - .flt2 = CONFIG_STM32H7_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1POL, - .idle = CONFIG_STM32H7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1NPOL, - .idle = CONFIG_STM32H7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM8_CH2MODE, -#ifdef CONFIG_STM32H7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2POL, - .idle = CONFIG_STM32H7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2NPOL, - .idle = CONFIG_STM32H7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM8_CH3MODE, -#ifdef CONFIG_STM32H7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3POL, - .idle = CONFIG_STM32H7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3NPOL, - .idle = CONFIG_STM32H7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM8_CH4MODE, -#ifdef CONFIG_STM32H7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH4POL, - .idle = CONFIG_STM32H7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM8_CH5MODE, -#ifdef CONFIG_STM32H7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH5POL, - .idle = CONFIG_STM32H7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM8_CH6MODE, -#ifdef CONFIG_STM32H7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH6POL, - .idle = CONFIG_STM32H7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1066,18 +1066,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H7_TIM8_MODE, - .lock = CONFIG_STM32H7_TIM8_LOCK, - .t_dts = CONFIG_STM32H7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1085,40 +1085,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM12_CH1MODE, -#ifdef CONFIG_STM32H7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH1POL, - .idle = CONFIG_STM32H7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM12_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH2POL, - .idle = CONFIG_STM32H7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1130,7 +1130,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1149,24 +1149,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM13_CH1MODE, -#ifdef CONFIG_STM32H7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM13_CH1POL, - .idle = CONFIG_STM32H7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1178,7 +1178,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1197,24 +1197,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM14_CH1MODE, -#ifdef CONFIG_STM32H7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM14_CH1POL, - .idle = CONFIG_STM32H7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1226,7 +1226,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1245,58 +1245,58 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1POL, - .idle = CONFIG_STM32H7_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1NPOL, - .idle = CONFIG_STM32H7_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM15_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH2POL, - .idle = CONFIG_STM32H7_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1308,7 +1308,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1316,10 +1316,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM15_LOCK, - .t_dts = CONFIG_STM32H7_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1327,43 +1327,43 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H7_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1POL, - .idle = CONFIG_STM32H7_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1NPOL, - .idle = CONFIG_STM32H7_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1374,7 +1374,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1382,10 +1382,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM16_LOCK, - .t_dts = CONFIG_STM32H7_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1393,43 +1393,43 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H7_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32H7_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32H7_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1POL, - .idle = CONFIG_STM32H7_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1NPOL, - .idle = CONFIG_STM32H7_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1440,7 +1440,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1448,10 +1448,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM17_LOCK, - .t_dts = CONFIG_STM32H7_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1459,7 +1459,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H7_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1796,7 +1796,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1853,7 +1853,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2581,7 +2581,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3134,7 +3134,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3143,7 +3143,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3152,7 +3152,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3161,7 +3161,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3170,7 +3170,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3179,7 +3179,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3188,7 +3188,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3197,7 +3197,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3206,7 +3206,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3215,7 +3215,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3224,7 +3224,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3233,7 +3233,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3531,7 +3531,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3540,7 +3540,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3549,7 +3549,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3558,7 +3558,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3567,7 +3567,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3576,7 +3576,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3585,7 +3585,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3594,7 +3594,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3603,7 +3603,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3612,7 +3612,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3621,7 +3621,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3630,7 +3630,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3747,7 +3747,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3758,7 +3758,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3766,7 +3766,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3774,7 +3774,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3782,7 +3782,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3790,7 +3790,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3801,7 +3801,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3809,7 +3809,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3817,7 +3817,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3825,7 +3825,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3833,7 +3833,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3841,7 +3841,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; @@ -3861,4 +3861,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index bc6002af3bf19..de9b791109a56 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -52,89 +52,89 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. - * If CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM must + * If CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must * also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H7_TIM12 -# undef CONFIG_STM32H7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H7_TIM13 -# undef CONFIG_STM32H7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H7_TIM14 -# undef CONFIG_STM32H7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H7_TIM16 -# undef CONFIG_STM32H7_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H7_TIM17 -# undef CONFIG_STM32H7_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses */ -#undef CONFIG_STM32H7_TIM6_PWM -#undef CONFIG_STM32H7_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,64 +269,64 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32H7_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H7_TIM1_PWM -# if !defined(CONFIG_STM32H7_TIM1_CHANNEL) -# error "CONFIG_STM32H7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM1_CHANNEL == 1 -# define CONFIG_STM32H7_TIM1_CHANNEL1 1 -# define CONFIG_STM32H7_TIM1_CH1MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 2 -# define CONFIG_STM32H7_TIM1_CHANNEL2 1 -# define CONFIG_STM32H7_TIM1_CH2MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 3 -# define CONFIG_STM32H7_TIM1_CHANNEL3 1 -# define CONFIG_STM32H7_TIM1_CH3MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 4 -# define CONFIG_STM32H7_TIM1_CHANNEL4 1 -# define CONFIG_STM32H7_TIM1_CH4MODE CONFIG_STM32H7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM2_PWM -# if !defined(CONFIG_STM32H7_TIM2_CHANNEL) -# error "CONFIG_STM32H7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM2_CHANNEL == 1 -# define CONFIG_STM32H7_TIM2_CHANNEL1 1 -# define CONFIG_STM32H7_TIM2_CH1MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 2 -# define CONFIG_STM32H7_TIM2_CHANNEL2 1 -# define CONFIG_STM32H7_TIM2_CH2MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 3 -# define CONFIG_STM32H7_TIM2_CHANNEL3 1 -# define CONFIG_STM32H7_TIM2_CH3MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 4 -# define CONFIG_STM32H7_TIM2_CHANNEL4 1 -# define CONFIG_STM32H7_TIM2_CH4MODE CONFIG_STM32H7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM3_PWM -# if !defined(CONFIG_STM32H7_TIM3_CHANNEL) -# error "CONFIG_STM32H7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM3_CHANNEL == 1 -# define CONFIG_STM32H7_TIM3_CHANNEL1 1 -# define CONFIG_STM32H7_TIM3_CH1MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 2 -# define CONFIG_STM32H7_TIM3_CHANNEL2 1 -# define CONFIG_STM32H7_TIM3_CH2MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 3 -# define CONFIG_STM32H7_TIM3_CHANNEL3 1 -# define CONFIG_STM32H7_TIM3_CH3MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 4 -# define CONFIG_STM32H7_TIM3_CHANNEL4 1 -# define CONFIG_STM32H7_TIM3_CH4MODE CONFIG_STM32H7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM4_PWM -# if !defined(CONFIG_STM32H7_TIM4_CHANNEL) -# error "CONFIG_STM32H7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM4_CHANNEL == 1 -# define CONFIG_STM32H7_TIM4_CHANNEL1 1 -# define CONFIG_STM32H7_TIM4_CH1MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 2 -# define CONFIG_STM32H7_TIM4_CHANNEL2 1 -# define CONFIG_STM32H7_TIM4_CH2MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 3 -# define CONFIG_STM32H7_TIM4_CHANNEL3 1 -# define CONFIG_STM32H7_TIM4_CH3MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 4 -# define CONFIG_STM32H7_TIM4_CHANNEL4 1 -# define CONFIG_STM32H7_TIM4_CH4MODE CONFIG_STM32H7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM5_PWM -# if !defined(CONFIG_STM32H7_TIM5_CHANNEL) -# error "CONFIG_STM32H7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM5_CHANNEL == 1 -# define CONFIG_STM32H7_TIM5_CHANNEL1 1 -# define CONFIG_STM32H7_TIM5_CH1MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 2 -# define CONFIG_STM32H7_TIM5_CHANNEL2 1 -# define CONFIG_STM32H7_TIM5_CH2MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 3 -# define CONFIG_STM32H7_TIM5_CHANNEL3 1 -# define CONFIG_STM32H7_TIM5_CH3MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 4 -# define CONFIG_STM32H7_TIM5_CHANNEL4 1 -# define CONFIG_STM32H7_TIM5_CH4MODE CONFIG_STM32H7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM8_PWM -# if !defined(CONFIG_STM32H7_TIM8_CHANNEL) -# error "CONFIG_STM32H7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM8_CHANNEL == 1 -# define CONFIG_STM32H7_TIM8_CHANNEL1 1 -# define CONFIG_STM32H7_TIM8_CH1MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 2 -# define CONFIG_STM32H7_TIM8_CHANNEL2 1 -# define CONFIG_STM32H7_TIM8_CH2MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 3 -# define CONFIG_STM32H7_TIM8_CHANNEL3 1 -# define CONFIG_STM32H7_TIM8_CH3MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 4 -# define CONFIG_STM32H7_TIM8_CHANNEL4 1 -# define CONFIG_STM32H7_TIM8_CH4MODE CONFIG_STM32H7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM12_PWM -# if !defined(CONFIG_STM32H7_TIM12_CHANNEL) -# error "CONFIG_STM32H7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM12_CHANNEL == 1 -# define CONFIG_STM32H7_TIM12_CHANNEL1 1 -# define CONFIG_STM32H7_TIM12_CH1MODE CONFIG_STM32H7_TIM12_CHMODE -# elif CONFIG_STM32H7_TIM12_CHANNEL == 2 -# define CONFIG_STM32H7_TIM12_CHANNEL2 1 -# define CONFIG_STM32H7_TIM12_CH2MODE CONFIG_STM32H7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM13_PWM -# if !defined(CONFIG_STM32H7_TIM13_CHANNEL) -# error "CONFIG_STM32H7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM13_CHANNEL == 1 -# define CONFIG_STM32H7_TIM13_CHANNEL1 1 -# define CONFIG_STM32H7_TIM13_CH1MODE CONFIG_STM32H7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM14_PWM -# if !defined(CONFIG_STM32H7_TIM14_CHANNEL) -# error "CONFIG_STM32H7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM14_CHANNEL == 1 -# define CONFIG_STM32H7_TIM14_CHANNEL1 1 -# define CONFIG_STM32H7_TIM14_CH1MODE CONFIG_STM32H7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM15_PWM -# if !defined(CONFIG_STM32H7_TIM15_CHANNEL) -# error "CONFIG_STM32H7_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM15_CHANNEL == 1 -# define CONFIG_STM32H7_TIM15_CHANNEL1 1 -# define CONFIG_STM32H7_TIM15_CH1MODE CONFIG_STM32H7_TIM15_CHMODE -# elif CONFIG_STM32H7_TIM15_CHANNEL == 2 -# define CONFIG_STM32H7_TIM15_CHANNEL2 1 -# define CONFIG_STM32H7_TIM15_CH2MODE CONFIG_STM32H7_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM16_PWM -# if !defined(CONFIG_STM32H7_TIM16_CHANNEL) -# error "CONFIG_STM32H7_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM16_CHANNEL == 1 -# define CONFIG_STM32H7_TIM16_CHANNEL1 1 -# define CONFIG_STM32H7_TIM16_CH1MODE CONFIG_STM32H7_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM17_PWM -# if !defined(CONFIG_STM32H7_TIM17_CHANNEL) -# error "CONFIG_STM32H7_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM17_CHANNEL == 1 -# define CONFIG_STM32H7_TIM17_CHANNEL1 1 -# define CONFIG_STM32H7_TIM17_CH1MODE CONFIG_STM32H7_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index c1d97009676e4..287ca4b42ea5c 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -37,7 +37,7 @@ #include "stm32_pwr.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_PWR) +#if defined(CONFIG_STM32_PWR) #define BREG_WAIT_USTIMEOUT 1000 /* uS to wait for regulator to come ready */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c index 406ec36796b64..d3d29deb35cb7 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ b/arch/arm/src/stm32h7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32H7_TIM2_QE) || defined(CONFIG_STM32H7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM3_QE) || \ - defined(CONFIG_STM32H7_TIM4_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32H7_QENCODER_FILTER -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32H7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32H7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32H7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32H7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32H7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32H7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -944,37 +944,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h index a8b93505d59b6..6ad6f0f392eb3 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ b/arch/arm/src/stm32h7/stm32_qencoder.h @@ -38,42 +38,42 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32H7_TIMn is defined - * then the CONFIG_STM32H7_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder * (at least for the STM32 H7) */ -#undef CONFIG_STM32H7_TIM6_QE -#undef CONFIG_STM32H7_TIM7_QE -#undef CONFIG_STM32H7_TIM9_QE -#undef CONFIG_STM32H7_TIM10_QE -#undef CONFIG_STM32H7_TIM11_QE -#undef CONFIG_STM32H7_TIM12_QE -#undef CONFIG_STM32H7_TIM13_QE -#undef CONFIG_STM32H7_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index bb985448e65ef..f9885a4331392 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -81,7 +81,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) && defined(CONFIG_STM32H7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -93,7 +93,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -105,26 +105,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -189,14 +189,14 @@ struct stm32h7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -206,11 +206,11 @@ struct stm32h7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32h7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -247,7 +247,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -287,16 +287,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32h7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32h7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); @@ -306,8 +306,8 @@ static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H7_QSPI_DMATHRESHOLD -# define CONFIG_STM32H7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -361,13 +361,13 @@ static struct stm32h7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -393,7 +393,7 @@ static struct stm32h7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -445,7 +445,7 @@ static inline uint32_t qspi_getreg(struct stm32h7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -468,7 +468,7 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -649,7 +649,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -867,7 +867,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1010,7 +1010,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1135,7 +1135,7 @@ static void qspi_ccrconfig(struct stm32h7_qspidev_s *priv, } } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1358,7 +1358,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1631,7 +1631,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2065,7 +2065,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2246,7 +2246,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2307,11 +2307,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2473,18 +2473,18 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32H7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32H7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H7_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2505,10 +2505,10 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32H7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32H7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2618,7 +2618,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2632,7 +2632,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2658,7 +2658,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2666,12 +2666,12 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2737,7 +2737,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2756,7 +2756,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2802,4 +2802,4 @@ void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 93f03807023dd..98da12b1e5368 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index 668be18c4dd26..d8611b0f388bf 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -59,15 +59,15 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x7xx_rcc.c" #else # error "Unsupported STM32 H7 chip" @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be * enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * @@ -100,19 +100,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, void stm32_clockconfig(void) { -#ifndef CONFIG_STM32H7_BYPASS_CLOCKCONFIG +#ifndef CONFIG_STM32_BYPASS_CLOCKCONFIG /* Make sure that we are starting in the reset state */ rcc_reset(); -# if defined(CONFIG_STM32H7_PWR) +# if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); # endif -# if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +# if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -127,13 +127,13 @@ void stm32_clockconfig(void) stm32_stdclockconfig(); # endif -#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */ +#endif /* !CONFIG_STM32_BYPASS_CLOCKCONFIG */ /* Enable peripheral clocking */ rcc_enableperipherals(); -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -153,7 +153,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be * enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * @@ -168,7 +168,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h index 786bb7064db3e..a39962ef5753a 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.h +++ b/arch/arm/src/stm32h7/stm32_rcc.h @@ -124,7 +124,7 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be * enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * @@ -157,7 +157,7 @@ void stm32_stdclockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -174,7 +174,7 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be + * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be * enabled by an externally provided, board-specific function called * stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32h7/stm32_rng.c b/arch/arm/src/stm32h7/stm32_rng.c index 0e6e67df1c5ae..df53d7f73436d 100644 --- a/arch/arm/src/stm32h7/stm32_rng.c +++ b/arch/arm/src/stm32h7/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32H7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32H7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 648af00143d79..14a1a225df4a0 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_OPENAMP_CACHE) # error CONFIG_OPENAMP_CACHE must be set # endif @@ -60,7 +60,7 @@ #define VRING_NR (8) /* Number of descriptors */ #define VRING_SIZE (512) /* Size of one descriptor */ -#ifdef CONFIG_STM32H7_SHMEM_SRAM3 +#ifdef CONFIG_STM32_SHMEM_SRAM3 /* Use 32kB of the SRAM3 as a shared memory */ # define VRING_SHMEM STM32_SRAM3_BASE @@ -119,7 +119,7 @@ static int stm32_rptun_register_callback(struct rptun_dev_s *dev, rptun_callback_t callback, void *arg); -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 static void stm32_rptun_reset(struct rptun_dev_s *dev, int value); static void stm32_rptun_panic(struct rptun_dev_s *dev); #endif @@ -138,13 +138,13 @@ static const struct rptun_ops_s g_stm32_rptun_ops = .stop = stm32_rptun_stop, .notify = stm32_rptun_notify, .register_callback = stm32_rptun_register_callback, -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 .reset = stm32_rptun_reset, .panic = stm32_rptun_panic #endif }; -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /* Allocate shared memory on the CM7 core side */ static struct stm32_rptun_shmem_s g_shmem __attribute__((section(".shmem"))); @@ -185,7 +185,7 @@ stm32_rptun_get_resource(struct rptun_dev_s *dev) return &priv->shmem->rsc.rsc_tbl_hdr; } -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 priv->shmem = &g_shmem; #else priv->shmem = (struct stm32_rptun_shmem_s *)VRING_SHMEM; @@ -297,7 +297,7 @@ static int stm32_rptun_stop(struct rptun_dev_s *dev) static int stm32_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid) { -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /* Notify slave that RX is ready */ stm32_hsem_signal(RPTUN_HSEM_CHAN_SLAVE_RX); @@ -327,7 +327,7 @@ static int stm32_rptun_register_callback(struct rptun_dev_s *dev, return 0; } -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /**************************************************************************** * Name: stm32_rptun_reset ****************************************************************************/ @@ -352,7 +352,7 @@ static void stm32_rptun_panic(struct rptun_dev_s *dev) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /**************************************************************************** * Name: stm32_hsem_master_callback ****************************************************************************/ @@ -480,7 +480,7 @@ int stm32_rptun_init(const char *cpuname) stm32_hsem_init(); -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /* The CM7 core always master */ memset(&g_shmem, 0, sizeof(struct stm32_rptun_shmem_s)); @@ -491,7 +491,7 @@ int stm32_rptun_init(const char *cpuname) /* Configure HSEM */ -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 stm32_rptun_hsem_cm7(dev); #else stm32_rptun_hsem_cm4(dev); diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index ed25043062d6e..4bfbe237a917e 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32H7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32H7_PWR -# error "CONFIG_STM32H7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32H7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32H7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32H7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.h b/arch/arm/src/stm32h7/stm32_rtc.h index e3b3f69096c21..82290558797f4 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.h +++ b/arch/arm/src/stm32h7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32H7_RTC_MAGIC) -# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32H7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_REG) -# define CONFIG_STM32H7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32H7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32H7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 414e6c5dbdda7..2aca3035cd277 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32H7_SDMMC1) || defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -101,14 +101,14 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA. + * CONFIG_STM32_SDMMC_IDMA - Enable SDMMC IDMA. * DMA support for SDMMC. If disabled, the SDMMC will work in * interrupt mode and still use the IDMA to a local buffer for data * lengths less the 32 bytes due to the FIFO limitations. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * CONFIG_SDMMC1/2_SDIO_MODE * Build ins additional support needed only for SDIO cards (vs. SD memory @@ -125,19 +125,19 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32H7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) # warning "Large Non-DMA transfer may result in RX overrun failures" -#elif defined(CONFIG_STM32H7_SDMMC1) +#elif defined(CONFIG_STM32_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE -# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE) +# define SRAM4_END (SRAM4_START + STM32_SRAM4_SIZE) #endif #if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) @@ -150,7 +150,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32H7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -316,7 +316,7 @@ /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_AFTER_SETUP 1 # define SAMPLENDX_END_TRANSFER 2 @@ -381,7 +381,7 @@ struct stm32_dev_s uint32_t blocksize; /* Current block size */ uint32_t receivecnt; /* Real count to receive */ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) struct work_s cbfifo; /* Monitor for Lame FIFO */ #endif uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA and support un-alinged buffers */ @@ -389,7 +389,7 @@ struct stm32_dev_s bool unaligned_rx; /* read buffer is not cache-line or 32 bit aligned */ /* Input dma buffer for unaligned transfers */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); #endif @@ -397,7 +397,7 @@ struct stm32_dev_s /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) struct stm32_sdioregs_s { uint8_t power; @@ -434,7 +434,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* Debug Helpers ************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -456,7 +456,7 @@ static uint8_t stm32_log2(uint16_t value); static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, bool receive); static void stm32_datadisable(struct stm32_dev_s *priv); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv); #else @@ -499,7 +499,7 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); static void stm32_blocksetup(struct sdio_dev_s *dev, unsigned int blocksize, unsigned int nblocks); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(struct sdio_dev_s *dev, @@ -527,7 +527,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -546,7 +546,7 @@ static void stm32_default(struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -562,7 +562,7 @@ struct stm32_dev_s g_sdmmcdev1 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -582,7 +582,7 @@ struct stm32_dev_s g_sdmmcdev1 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -601,7 +601,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif }; #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -617,7 +617,7 @@ struct stm32_dev_s g_sdmmcdev2 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -637,7 +637,7 @@ struct stm32_dev_s g_sdmmcdev2 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -658,7 +658,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -899,7 +899,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -915,7 +915,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -938,7 +938,7 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; @@ -954,7 +954,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -985,7 +985,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) @@ -1002,7 +1002,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], @@ -1104,7 +1104,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, { DEBUGASSERT((dlen % priv->blocksize) == 0); -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) /* If this is an unaligned receive, then receive one block at a * time to the internal buffer */ @@ -1202,7 +1202,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sendfifo(struct stm32_dev_s *priv) { union @@ -1267,7 +1267,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_recvfifo(struct stm32_dev_s *priv) { union @@ -1328,7 +1328,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined (CONFIG_STM32H7_SDMMC_IDMA) +#if defined (CONFIG_STM32_SDMMC_IDMA) static void stm32_recvdma(struct stm32_dev_s *priv) { uint32_t dctrl; @@ -1547,7 +1547,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sdmmc_fifo_monitor(void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1643,7 +1643,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* Is the RX FIFO half full or more? Is so then we must be * processing a receive transaction. */ @@ -1689,7 +1689,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * half-full interrupt will be received. */ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* If the transfer would not trigger fifo half full * we used IDMA to manage the lame fifo @@ -1909,7 +1909,7 @@ static void stm32_reset(struct sdio_dev_s *dev) flags = enter_critical_section(); -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { regaddress = STM32_RCC_AHB3RSTR; @@ -1917,7 +1917,7 @@ static void stm32_reset(struct sdio_dev_s *dev) } #endif -#if defined CONFIG_STM32H7_SDMMC2 +#if defined CONFIG_STM32_SDMMC2 if (priv->base == STM32_SDMMC2_BASE) { regaddress = STM32_RCC_AHB2RSTR; @@ -1998,7 +1998,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_DMABEFOREWRITE; -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2305,7 +2305,7 @@ static void stm32_blocksetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes) { @@ -2381,7 +2381,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_sendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t nbytes) { @@ -3065,7 +3065,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3074,7 +3074,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* IDMA must be possible to the buffer */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { /* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. */ @@ -3134,7 +3134,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3239,7 +3239,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3423,7 +3423,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (slotno == 0) { /* Select SDMMC 1 */ @@ -3456,7 +3456,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ @@ -3629,4 +3629,4 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, } #endif -#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 7860667a24507..cf668117e809e 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -65,7 +65,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -81,11 +81,11 @@ # if !defined(DMAMAP_USART1_RX) # error "USART1 DMA map not defined (DMAMAP_USART1_RX)" # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -93,11 +93,11 @@ # if !defined(DMAMAP_USART2_RX) # error "USART2 DMA map not defined (DMAMAP_USART2_RX)" # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -105,11 +105,11 @@ # if !defined(DMAMAP_USART3_RX) # error "USART3 DMA map not defined (DMAMAP_USART3_RX)" # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -117,11 +117,11 @@ # if !defined(DMAMAP_UART4_RX) # error "UART4 DMA map not defined (DMAMAP_UART4_RX)" # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -129,11 +129,11 @@ # if !defined(DMAMAP_UART5_RX) # error "UART5 DMA map not defined (DMAMAP_UART5_RX)" # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -141,11 +141,11 @@ # if !defined(DMAMAP_USART6_RX) # error "USART6 DMA map not defined (DMAMAP_USART6_RX)" # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -153,11 +153,11 @@ # if !defined(DMAMAP_UART7_RX) # error "UART7 DMA map not defined (DMAMAP_UART7_RX)" # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -165,11 +165,11 @@ # if !defined(DMAMAP_UART8_RX) # error "UART8 DMA map not defined (DMAMAP_UART8_RX)" # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -205,14 +205,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -247,11 +247,11 @@ # if !defined(DMAMAP_USART1_TX) # error "USART1 DMA map not defined (DMAMAP_USART1_TX)" # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -259,11 +259,11 @@ # if !defined(DMAMAP_USART2_TX) # error "USART2 DMA map not defined (DMAMAP_USART2_TX)" # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -271,11 +271,11 @@ # if !defined(DMAMAP_USART3_TX) # error "USART3 DMA map not defined (DMAMAP_USART3_TX)" # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -283,11 +283,11 @@ # if !defined(DMAMAP_UART4_TX) # error "UART4 DMA map not defined (DMAMAP_UART4_TX)" # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -295,11 +295,11 @@ # if !defined(DMAMAP_UART5_TX) # error "UART5 DMA map not defined (DMAMAP_UART5_TX)" # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -307,11 +307,11 @@ # if !defined(DMAMAP_USART6_TX) # error "USART6 DMA map not defined (DMAMAP_USART6_TX)" # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -319,11 +319,11 @@ # if !defined(DMAMAP_UART7_TX) # error "UART7 DMA map not defined (DMAMAP_UART7_TX)" # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -331,11 +331,11 @@ # if !defined(DMAMAP_UART8_TX) # error "UART8 DMA map not defined (DMAMAP_UART8_TX)" # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif #endif @@ -371,7 +371,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -475,8 +475,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # warning stm32h7 serial power managemnt was taken from stm32f7 and is untested! @@ -501,7 +501,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -511,13 +511,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32H7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -560,7 +560,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32H7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -868,49 +868,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -918,7 +918,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -988,7 +988,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -1058,7 +1058,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -1128,7 +1128,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1198,7 +1198,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1268,7 +1268,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1338,7 +1338,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1408,7 +1408,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1480,28 +1480,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1797,7 +1797,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1952,7 +1952,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -1990,49 +1990,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; @@ -2104,7 +2104,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2477,8 +2477,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Get the masked USART status word. */ @@ -2592,14 +2592,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2622,7 +2622,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2689,7 +2689,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2740,7 +2740,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2877,8 +2877,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H7_USART_BREAKS -# ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3088,7 +3088,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3761,7 +3761,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3911,7 +3911,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3940,7 +3940,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 329abb73f25ad..7ca1e8103082b 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -75,9 +75,9 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI5) || defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -87,19 +87,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,39 +137,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -180,8 +180,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL2 @@ -194,7 +194,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4) || defined(CONFIG_STM32H7_SPI5) +#if defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_PLL2 @@ -207,7 +207,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI6) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # elif STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PLL2 @@ -238,7 +238,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -288,7 +288,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -354,7 +354,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -403,7 +403,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H7_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -418,15 +418,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI1_COMMTYPE - .config = CONFIG_STM32H7_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -475,7 +475,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H7_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -490,15 +490,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI2_COMMTYPE - .config = CONFIG_STM32H7_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -547,7 +547,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H7_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -562,15 +562,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI3_COMMTYPE - .config = CONFIG_STM32H7_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -619,7 +619,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H7_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -634,15 +634,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI4_COMMTYPE - .config = CONFIG_STM32H7_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -691,7 +691,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H7_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -706,15 +706,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI5_COMMTYPE - .config = CONFIG_STM32H7_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -764,7 +764,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = SPI6_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H7_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -779,13 +779,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI6_COMMTYPE - .config = CONFIG_STM32H7_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1107,7 +1107,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1124,7 +1124,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1164,7 +1164,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1213,7 +1213,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1228,7 +1228,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1248,7 +1248,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1310,7 +1310,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1370,7 +1370,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1394,7 +1394,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1929,9 +1929,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SPI_DMA) || defined(CONFIG_STM32H7_DMACAPABLE) || \ - defined(CONFIG_STM32H7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2020,8 +2020,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H7_SPI_DMA || CONFIG_STM32H7_DMACAPABLE || - * CONFIG_STM32H7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2045,7 +2045,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2063,12 +2063,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2132,7 +2132,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2264,7 +2264,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2285,7 +2285,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2519,7 +2519,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2601,7 +2601,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2626,7 +2626,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2651,7 +2651,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2676,7 +2676,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2701,7 +2701,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2726,7 +2726,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2759,6 +2759,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1 || CONFIG_STM32H7_SPI2 || CONFIG_STM32H7_SPI3 || - * CONFIG_STM32H7_SPI4 || CONFIG_STM32H7_SPI5 || CONFIG_STM32H7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index a9b0532e0757e..663a2eac486db 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -114,42 +114,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -177,32 +177,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index efa9fc5641162..1231ffb3c11e0 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -52,12 +52,12 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1_SLAVE) || \ - defined(CONFIG_STM32H7_SPI2_SLAVE) || \ - defined(CONFIG_STM32H7_SPI3_SLAVE) || \ - defined(CONFIG_STM32H7_SPI4_SLAVE) || \ - defined(CONFIG_STM32H7_SPI5_SLAVE) || \ - defined(CONFIG_STM32H7_SPI6_SLAVE) +#if defined(CONFIG_STM32_SPI1_SLAVE) || \ + defined(CONFIG_STM32_SPI2_SLAVE) || \ + defined(CONFIG_STM32_SPI3_SLAVE) || \ + defined(CONFIG_STM32_SPI4_SLAVE) || \ + defined(CONFIG_STM32_SPI5_SLAVE) || \ + defined(CONFIG_STM32_SPI6_SLAVE) /**************************************************************************** * Pre-processor Definitions @@ -67,19 +67,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -113,8 +113,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1_SLAVE) || defined(CONFIG_STM32H7_SPI2_SLAVE) || \ - defined(CONFIG_STM32H7_SPI3_SLAVE) +#if defined(CONFIG_STM32_SPI1_SLAVE) || defined(CONFIG_STM32_SPI2_SLAVE) || \ + defined(CONFIG_STM32_SPI3_SLAVE) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # else @@ -125,7 +125,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4_SLAVE) || defined(CONFIG_STM32H7_SPI5_SLAVE) +#if defined(CONFIG_STM32_SPI4_SLAVE) || defined(CONFIG_STM32_SPI5_SLAVE) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # else @@ -136,7 +136,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6_SLAVE) +#if defined(CONFIG_STM32_SPI6_SLAVE) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # else @@ -147,9 +147,9 @@ # endif #endif /* SPI6 */ -#if defined (CONFIG_STM32H7_SPI_SLAVE_QSIZE) -# if CONFIG_STM32H7_SPI_SLAVE_QSIZE > 65535 -# error CONFIG_STM32H7_SPI_SLAVE_QSIZE too large +#if defined (CONFIG_STM32_SPI_SLAVE_QSIZE) +# if CONFIG_STM32_SPI_SLAVE_QSIZE > 65535 +# error CONFIG_STM32_SPI_SLAVE_QSIZE too large # endif #endif @@ -157,7 +157,7 @@ * support is in place */ -#if defined (CONFIG_STM32H7_SPI6_SLAVE) +#if defined (CONFIG_STM32_SPI6_SLAVE) # error SPI6 slave not supported yet #endif @@ -187,7 +187,7 @@ struct stm32_spidev_s uint32_t spiclock; /* Clocking for the SPI module */ uint8_t irq; /* SPI IRQ number */ uint32_t nss_pin; /* Chip select pin configuration */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the TX DMA */ uint32_t rxch; /* The RX DMA channel number */ @@ -221,7 +221,7 @@ struct stm32_spidev_s /* Input queue */ uint16_t ihead; /* Location of next unread value */ -#ifndef CONFIG_STM32H7_SPI_DMA +#ifndef CONFIG_STM32_SPI_DMA uint16_t itail; /* Index of next free memory pointer */ #endif uint8_t *inq; @@ -250,7 +250,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, @@ -311,7 +311,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #define SPI_SLAVE_OUTQ(x) spi##x##_outq #define SPI_SLAVE_INQ(x) spi##x##_inq -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #define SPI_SLAVE_INIT_DMA(x) \ .rxch = DMAMAP_SPI##x##_RX, \ .txch = DMAMAP_SPI##x##_TX, \ @@ -340,78 +340,78 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = .initialized = false, \ .lock = NXMUTEX_INITIALIZER, \ SPI_SLAVE_INIT_PM_PREPARE \ - .config = CONFIG_STM32H7_SPI##x##_COMMTYPE, \ + .config = CONFIG_STM32_SPI##x##_COMMTYPE, \ } -#ifdef CONFIG_STM32H7_SPI1_SLAVE +#ifdef CONFIG_STM32_SPI1_SLAVE static -uint8_t SPI_SLAVE_OUTQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(1)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(1)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi1ctrlr = SPI_SLAVE_INIT(1); #endif -#ifdef CONFIG_STM32H7_SPI2_SLAVE +#ifdef CONFIG_STM32_SPI2_SLAVE static -uint8_t SPI_SLAVE_OUTQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(2)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(2)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi2ctrlr = SPI_SLAVE_INIT(2); #endif -#ifdef CONFIG_STM32H7_SPI3_SLAVE +#ifdef CONFIG_STM32_SPI3_SLAVE static -uint8_t SPI_SLAVE_OUTQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(3)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(3)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi3ctrlr = SPI_SLAVE_INIT(3); #endif -#ifdef CONFIG_STM32H7_SPI4_SLAVE +#ifdef CONFIG_STM32_SPI4_SLAVE static -uint8_t SPI_SLAVE_OUTQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(4)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(4)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi4ctrlr = SPI_SLAVE_INIT(4); #endif -#ifdef CONFIG_STM32H7_SPI5_SLAVE +#ifdef CONFIG_STM32_SPI5_SLAVE static -uint8_t SPI_SLAVE_OUTQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(5)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(5)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi5ctrlr = SPI_SLAVE_INIT(5); #endif -#ifdef CONFIG_STM32H7_SPI6_SLAVE +#ifdef CONFIG_STM32_SPI6_SLAVE /* TODO: these needs to be located in SRAM3 for SPI6 */ static -uint8_t SPI_SLAVE_OUTQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_OUTQ(6)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static -uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32H7_SPI_SLAVE_QSIZE)] +uint8_t SPI_SLAVE_INQ(6)[DMA_ALIGN_UP(CONFIG_STM32_SPI_SLAVE_QSIZE)] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct stm32_spidev_s g_spi6ctrlr = SPI_SLAVE_INIT(6); @@ -706,7 +706,7 @@ static inline bool spi_9to16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -726,7 +726,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -746,7 +746,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) { stm32_dmacfg_t dmacfg; @@ -779,7 +779,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) dmacfg.paddr = priv->spibase + STM32_SPI_RXDR_OFFSET; dmacfg.maddr = (uint32_t)priv->inq; - dmacfg.ndata = CONFIG_STM32H7_SPI_SLAVE_QSIZE; + dmacfg.ndata = CONFIG_STM32_SPI_SLAVE_QSIZE; dmacfg.cfg1 = priv->rxccr; dmacfg.cfg2 = 0; @@ -795,7 +795,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) { /* TODO: set up dma to transfer out the new data from priv->outq, @@ -850,7 +850,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -875,7 +875,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1129,7 +1129,7 @@ static void spi_bind(struct spi_slave_ctrlr_s *ctrlr, /* invalidate the whole rx buffer */ up_flush_dcache((uintptr_t)priv->inq, - (uintptr_t)priv->inq + CONFIG_STM32H7_SPI_SLAVE_QSIZE); + (uintptr_t)priv->inq + CONFIG_STM32_SPI_SLAVE_QSIZE); /* Bind the SPI slave device interface instance to the SPI slave * controller interface. @@ -1223,7 +1223,7 @@ static int spi_nssinterrupt(int irq, void *context, void *arg) spi_enable(priv, false); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Setup DMAs */ @@ -1363,7 +1363,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return; @@ -1377,9 +1377,9 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) /* Flush the input buffers */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->ihead = - CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); + CONFIG_STM32_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else priv->ihead = 0; priv->itail = 0; @@ -1415,11 +1415,11 @@ static inline int spi_rx_buffer_free(uint8_t *ptr, int start, int end) * returns garbage */ - if (end >= CONFIG_STM32H7_SPI_SLAVE_QSIZE) + if (end >= CONFIG_STM32_SPI_SLAVE_QSIZE) { end = 0; up_invalidate_dcache((uintptr_t)&ptr[start], - (uintptr_t)&ptr[CONFIG_STM32H7_SPI_SLAVE_QSIZE]); + (uintptr_t)&ptr[CONFIG_STM32_SPI_SLAVE_QSIZE]); } else { @@ -1452,9 +1452,9 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) uint16_t bytes_left; DEBUGASSERT(priv != NULL && priv->dev != NULL); - DEBUGASSERT(priv->ihead < CONFIG_STM32H7_SPI_SLAVE_QSIZE); + DEBUGASSERT(priv->ihead < CONFIG_STM32_SPI_SLAVE_QSIZE); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return 0; @@ -1465,8 +1465,8 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) spi_lock(ctrlr, true); -#ifdef CONFIG_STM32H7_SPI_DMA - itail = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); +#ifdef CONFIG_STM32_SPI_DMA + itail = CONFIG_STM32_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else #error Support only simplex mode rx with dma #endif @@ -1480,7 +1480,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) priv->ihead += SPIS_DEV_RECEIVE(priv->dev, (const uint16_t *)&priv->inq[ihead], - CONFIG_STM32H7_SPI_SLAVE_QSIZE - + CONFIG_STM32_SPI_SLAVE_QSIZE - ihead); /* Invalidate dcache and wrap around the priv->ihead */ @@ -1505,7 +1505,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) /* Calculate the number of bytes left in the buffer */ bytes_left = itail < priv->ihead - ? CONFIG_STM32H7_SPI_SLAVE_QSIZE - priv->ihead + itail + ? CONFIG_STM32_SPI_SLAVE_QSIZE - priv->ihead + itail : itail - priv->ihead; spi_lock(ctrlr, false); @@ -1657,7 +1657,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* DMA will be started in the interrupt handler, synchronized to the master * nss */ @@ -1735,7 +1735,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1_SLAVE +#ifdef CONFIG_STM32_SPI1_SLAVE if (bus == 1) { SPI_SLAVE_INIT_BUS(1); @@ -1743,7 +1743,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI2_SLAVE +#ifdef CONFIG_STM32_SPI2_SLAVE if (bus == 2) { SPI_SLAVE_INIT_BUS(2); @@ -1751,7 +1751,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI3_SLAVE +#ifdef CONFIG_STM32_SPI3_SLAVE if (bus == 3) { SPI_SLAVE_INIT_BUS(3); @@ -1759,7 +1759,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI4_SLAVE +#ifdef CONFIG_STM32_SPI4_SLAVE if (bus == 4) { SPI_SLAVE_INIT_BUS(4); @@ -1767,7 +1767,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI5_SLAVE +#ifdef CONFIG_STM32_SPI5_SLAVE if (bus == 5) { SPI_SLAVE_INIT_BUS(5); @@ -1775,7 +1775,7 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) else #endif -#ifdef CONFIG_STM32H7_SPI6_SLAVE +#ifdef CONFIG_STM32_SPI6_SLAVE if (bus == 6) { SPI_SLAVE_INIT_BUS(6); @@ -1796,4 +1796,4 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) return (struct spi_slave_ctrlr_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1..6_SLAVE */ +#endif /* CONFIG_STM32_SPI1..6_SLAVE */ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 88d53cf8bb778..9e123c3e2adc3 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -47,7 +47,7 @@ #include "stm32_lowputc.h" #include "stm32_start.h" -#ifdef CONFIG_ARCH_STM32H7_DUALCORE +#ifdef CONFIG_ARCH_STM32_DUALCORE # include "stm32_dualcore.h" #endif @@ -117,7 +117,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE; void __start(void) noinstrument_function; #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /**************************************************************************** * Name: stm32_tcmenable * @@ -192,7 +192,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /* Wait for CM7 initialization done */ stm32h7_waitfor_cm7(); @@ -251,7 +251,7 @@ void __start(void) stm32_lowsetup(); showprogress('A'); -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /* Enable/disable tightly coupled memories */ stm32_tcmenable(); @@ -262,7 +262,7 @@ void __start(void) stm32_boardinitialize(); showprogress('B'); -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 /* Enable I- and D-Caches */ up_enable_icache(); @@ -303,9 +303,9 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \ - defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) +#if defined(CONFIG_ARCH_STM32_DUALCORE) && \ + defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Start CM4 core after clock configuration is done */ diff --git a/arch/arm/src/stm32h7/stm32_tickless.c b/arch/arm/src/stm32h7/stm32_tickless.c index 1de1d5abf738a..7fb140248cb55 100644 --- a/arch/arm/src/stm32h7/stm32_tickless.c +++ b/arch/arm/src/stm32h7/stm32_tickless.c @@ -89,23 +89,23 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32H7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if (CONFIG_STM32H7_TICKLESS_TIMER == 6) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 7) +#if (CONFIG_STM32_TICKLESS_TIMER == 6) || \ + (CONFIG_STM32_TICKLESS_TIMER == 7) # error Basic timers not supported by the tickless driver #endif -#if CONFIG_STM32H7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -413,50 +413,50 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32H7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM1STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM2STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM3STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM4STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM5STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM8STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; @@ -464,7 +464,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; @@ -473,7 +473,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; @@ -481,40 +481,40 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM12STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM13STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM14STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM15STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM16STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM17STOP); @@ -528,8 +528,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32H7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32H7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1001,10 +1001,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1021,7 +1021,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1042,7 +1042,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c index 4b04b9a9f24f2..4fe8974731987 100644 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ b/arch/arm/src/stm32h7/stm32_tim.c @@ -53,96 +53,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32H7_TIMn is - * defined then CONFIG_STM32H7_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32H7_TIMn is defined - * then CONFIG_STM32H7_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32H7_TIMn is defined then - * CONFIG_STM32H7_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H7_TIM1_PWM) || defined (CONFIG_STM32H7_TIM1_ADC) || \ - defined(CONFIG_STM32H7_TIM1_DAC) || defined(CONFIG_STM32H7_TIM1_QE) -# undef CONFIG_STM32H7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H7_TIM2_PWM) || defined (CONFIG_STM32H7_TIM2_ADC) || \ - defined(CONFIG_STM32H7_TIM2_DAC) || defined(CONFIG_STM32H7_TIM2_QE) -# undef CONFIG_STM32H7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) || defined (CONFIG_STM32H7_TIM3_ADC) || \ - defined(CONFIG_STM32H7_TIM3_DAC) || defined(CONFIG_STM32H7_TIM3_QE) -# undef CONFIG_STM32H7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H7_TIM4_PWM) || defined (CONFIG_STM32H7_TIM4_ADC) || \ - defined(CONFIG_STM32H7_TIM4_DAC) || defined(CONFIG_STM32H7_TIM4_QE) -# undef CONFIG_STM32H7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H7_TIM5_PWM) || defined (CONFIG_STM32H7_TIM5_ADC) || \ - defined(CONFIG_STM32H7_TIM5_DAC) || defined(CONFIG_STM32H7_TIM5_QE) -# undef CONFIG_STM32H7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32H7_TIM6_ADC) || \ - defined(CONFIG_STM32H7_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) -# undef CONFIG_STM32H7_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \ - defined(CONFIG_STM32H7_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) -# undef CONFIG_STM32H7_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H7_TIM8_PWM) || defined (CONFIG_STM32H7_TIM8_ADC) || \ - defined(CONFIG_STM32H7_TIM8_DAC) || defined(CONFIG_STM32H7_TIM8_QE) -# undef CONFIG_STM32H7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H7_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ - defined(CONFIG_STM32H7_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) -# undef CONFIG_STM32H7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H7_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ - defined(CONFIG_STM32H7_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) -# undef CONFIG_STM32H7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H7_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ - defined(CONFIG_STM32H7_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) -# undef CONFIG_STM32H7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H7_TIM15_PWM) || defined (CONFIG_STM32H7_TIM15_ADC) || \ - defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE) -# undef CONFIG_STM32H7_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H7_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ - defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE) -# undef CONFIG_STM32H7_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H7_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ - defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE) -# undef CONFIG_STM32H7_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM12) || defined(CONFIG_STM32H7_TIM13) || \ - defined(CONFIG_STM32H7_TIM14) || defined(CONFIG_STM32H7_TIM15) || \ - defined(CONFIG_STM32H7_TIM16) || defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -312,7 +312,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -320,7 +320,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -329,7 +329,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -338,7 +338,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -347,7 +347,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -356,7 +356,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -365,7 +365,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -374,7 +374,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -383,7 +383,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -392,7 +392,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -401,7 +401,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -410,7 +410,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -419,7 +419,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -428,7 +428,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -519,12 +519,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -626,72 +626,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -745,72 +745,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1016,7 +1016,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1049,7 +1049,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1078,7 +1078,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1107,7 +1107,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1136,7 +1136,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1165,7 +1165,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1199,7 +1199,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1232,7 +1232,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1247,7 +1247,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1266,7 +1266,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1280,7 +1280,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1364,85 +1364,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1474,72 +1474,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1555,4 +1555,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c index 895e54e7a2f9a..cc5e18737e5a7 100644 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM9) || defined(CONFIG_STM32H7_TIM10) || \ - defined(CONFIG_STM32H7_TIM11) || defined(CONFIG_STM32H7_TIM12) || \ - defined(CONFIG_STM32H7_TIM13) || defined(CONFIG_STM32H7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -473,72 +473,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_timerisr.c b/arch/arm/src/stm32h7/stm32_timerisr.c index b2f37b5f58043..e5bd4cf05153c 100644 --- a/arch/arm/src/stm32h7/stm32_timerisr.c +++ b/arch/arm/src/stm32h7/stm32_timerisr.c @@ -66,14 +66,14 @@ * 224-1). */ -#undef CONFIG_STM32H7_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 /* REVISIT: * It looks like SYSTICK for H7 is always clocked from CPUCLK and doesn't * depend on the SYSTICK_CTRL_CLKSOURCE bit settings. */ -#ifdef CONFIG_STM32H7_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define STM32_SYSTICK_CLOCK (STM32_HCLK_FREQUENCY / 8) #else # define STM32_SYSTICK_CLOCK (STM32_CPUCLK_FREQUENCY) @@ -155,7 +155,7 @@ void up_timer_initialize(void) */ regval = (NVIC_SYSTICK_CTRL_TICKINT | NVIC_SYSTICK_CTRL_ENABLE); -#ifndef CONFIG_STM32H7_SYSTICK_HCLKd8 +#ifndef CONFIG_STM32_SYSTICK_HCLKd8 regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index 92234cb4c4556..8748d83c3430a 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -40,44 +40,44 @@ * device. */ -#if STM32H7_NUART < 4 -# undef CONFIG_STM32H7_UART8 +#if STM32_NUART < 4 +# undef CONFIG_STM32_UART8 #endif -#if STM32H7_NUART < 3 -# undef CONFIG_STM32H7_UART7 +#if STM32_NUART < 3 +# undef CONFIG_STM32_UART7 #endif -#if STM32H7_NUART < 2 -# undef CONFIG_STM32H7_UART5 +#if STM32_NUART < 2 +# undef CONFIG_STM32_UART5 #endif -#if STM32H7_NUART < 1 -# undef CONFIG_STM32H7_UART4 +#if STM32_NUART < 1 +# undef CONFIG_STM32_UART4 #endif -#if STM32H7_NUSART < 4 -# undef CONFIG_STM32H7_USART6 +#if STM32_NUSART < 4 +# undef CONFIG_STM32_USART6 #endif -#if STM32H7_NUSART < 3 -# undef CONFIG_STM32H7_USART3 +#if STM32_NUSART < 3 +# undef CONFIG_STM32_USART3 #endif -#if STM32H7_NUSART < 2 -# undef CONFIG_STM32H7_USART2 +#if STM32_NUSART < 2 +# undef CONFIG_STM32_USART2 #endif -#if STM32H7_NUSART < 1 -# undef CONFIG_STM32H7_USART1 +#if STM32_NUSART < 1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \ - defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \ - defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \ - defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -296,42 +296,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif @@ -343,28 +343,28 @@ /* No DMA ops */ #undef SERIAL_HAVE_NODMA_OPS -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) && \ +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ !defined(CONFIG_USART1_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) && \ +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ !defined(CONFIG_USART2_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) && \ +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ !defined(CONFIG_USART3_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) && \ +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ !defined(CONFIG_UART4_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) && \ +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ !defined(CONFIG_UART5_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) && \ +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ !defined(CONFIG_USART6_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) && \ +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ !defined(CONFIG_UART7_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) && \ +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ !defined(CONFIG_UART8_TXDMA) # define SERIAL_HAVE_NODMA_OPS #endif diff --git a/arch/arm/src/stm32h7/stm32_usbhost.h b/arch/arm/src/stm32h7/stm32_usbhost.h index 031b66ad22906..065e980ffcbbd 100644 --- a/arch/arm/src/stm32h7/stm32_usbhost.h +++ b/arch/arm/src/stm32h7/stm32_usbhost.h @@ -28,23 +28,23 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32H7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32H7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * CONFIG_STM32_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit * words. Default 96 (384 bytes) - * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32h7/stm32_wdg.h b/arch/arm/src/stm32h7/stm32_wdg.h index f869669264aea..f5f5183766126 100644 --- a/arch/arm/src/stm32h7/stm32_wdg.h +++ b/arch/arm/src/stm32h7/stm32_wdg.h @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 4e96d10a3d3c2..7f254cf0c2166 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_WWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) /**************************************************************************** * Pre-processor Definitions @@ -66,12 +66,12 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_WWDG_DEFTIMOUT -# define CONFIG_STM32H7_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32H7_WWDG_REGDEBUG +# undef CONFIG_STM32_WWDG_REGDEBUG #endif /**************************************************************************** @@ -100,7 +100,7 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -161,7 +161,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -224,7 +224,7 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG_REGDEBUG +#ifdef CONFIG_STM32_WWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -772,7 +772,7 @@ void stm32_wwdginitialize(const char *devpath) */ stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32H7_WWDG_DEFTIMOUT); + CONFIG_STM32_WWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -783,9 +783,9 @@ void stm32_wwdginitialize(const char *devpath) * on the WWDG1 STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB3_FZ1); cr |= DBGMCU_APB3_WWDG1STOP; @@ -794,4 +794,4 @@ void stm32_wwdginitialize(const char *devpath) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_WWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index 1d68c42c78622..70a22bfb4ce10 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -69,10 +69,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32H7_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32H74xxE have 512Kb of FLASH * Parts STM32H74xxG have 1024Kb of FLASH @@ -85,49 +85,49 @@ #define FLASH_SECTOR_SIZE _K(128) #define FLASH_PAGE_SIZE 32 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_B +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_B # warning "Flash size not defined defaulting to 128KiB (B)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_B) -# define CONFIG_STM32H7_FLASH_CONFIG_B +# define CONFIG_STM32_FLASH_CONFIG_B -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_B) +#if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NBLOCKS 1 # define STM32_FLASH_SIZE _K(1 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 8 # define STM32_FLASH_SIZE _K(8 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 16 # define STM32_FLASH_SIZE _K(16 * 128) @@ -135,10 +135,10 @@ #endif -#ifndef CONFIG_STM32H7_FLASH_CR_PSIZE +#ifndef CONFIG_STM32_FLASH_CR_PSIZE #define FLASH_CR_PSIZE FLASH_CR_PSIZE_X64 #else -#define FLASH_CR_PSIZE (CONFIG_STM32H7_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) +#define FLASH_CR_PSIZE (CONFIG_STM32_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) #endif #define FLASH_KEY1 0x45670123 diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index c76b4e307a3bb..d0cc1d55394a0 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -69,10 +69,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32H7_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32H7x3xG have 1024Kb of FLASH * Parts STM32H7x3xI have 2048Kb of FLASH @@ -86,38 +86,38 @@ #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_G # warning "Flash size not defined defaulting to 1024KiB (G)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#if defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 128 # define STM32_FLASH_SIZE _K(128 * 8) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 256 # define STM32_FLASH_SIZE _K(256 * 8) diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index a1ce272975bf0..d8d998f713d74 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -146,23 +146,23 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ STM32_PWR_CR3_SMPSEXTHP | \ STM32_PWR_CR3_SMPSLEVEL_MASK) -# if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY) +# if defined(CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_SDEN -# elif defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# elif defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_BYPASS # else # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_LDOEN # endif #else # define STM32_PWR_CR3_MASK 0xffffffff -# if defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# if defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_SCUEN) # else # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN) @@ -192,7 +192,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -250,32 +250,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS +# ifndef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; @@ -286,7 +286,7 @@ static inline void rcc_enableahb1(void) # endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -314,13 +314,13 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -353,25 +353,25 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#if defined(CONFIG_STM32H7_LTDC) && defined(CONFIG_STM32H7_DMA2D) +#if defined(CONFIG_STM32_LTDC) && defined(CONFIG_STM32_DMA2D) /* Enable DMA2D */ regval |= RCC_AHB3ENR_DMA2DEN; @@ -400,7 +400,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -408,60 +408,60 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32H7_HSEM +#ifdef CONFIG_STM32_HSEM /* HSEM clock enable */ regval |= RCC_AHB4ENR_HSEMEN; @@ -488,31 +488,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -522,7 +522,7 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /* FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; @@ -549,31 +549,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -600,13 +600,13 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB3ENR_LTDCEN; #endif -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG /* RM0433 Rev 8 * Reference manual - STM32H742, STM32H743/753 and STM32H750 Value line @@ -651,19 +651,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -762,7 +762,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -776,7 +776,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -832,7 +832,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -963,7 +963,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1105,13 +1105,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2a03208623676..526dc538e4a9a 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -139,7 +139,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ @@ -179,7 +179,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -237,32 +237,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGHS +# if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); @@ -273,7 +273,7 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -301,13 +301,13 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -334,19 +334,19 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; @@ -375,7 +375,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -383,54 +383,54 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; @@ -457,31 +457,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -516,31 +516,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -590,19 +590,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -696,7 +696,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -710,7 +710,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -766,7 +766,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -897,7 +897,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1038,13 +1038,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h index fb3a0d2202743..b1b27fca0dc7c 100644 --- a/arch/arm/src/stm32l4/chip.h +++ b/arch/arm/src/stm32l4/chip.h @@ -49,7 +49,7 @@ * arch/stm32l4/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32L4 */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index c78b9f598df27..6c57bb1f099dd 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H /**************************************************************************** * Included Files @@ -41,136 +41,136 @@ * offset 0x0100 for slave. */ -#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ -#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ -#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ -#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ -#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET) - -#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET) -#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET) -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET) +#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -226,23 +226,23 @@ # define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ # define ADC_CFGR_EXTSEL_T2CC4 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC4 event */ # define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ # endif # define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ # define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ # endif # define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ # define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ # define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ # endif # define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ # define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */ # endif #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ @@ -286,10 +286,12 @@ # define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */ # define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */ # define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */ + #define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ #define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) # define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT) - /* Value = 0..8 */ + /* Value = 0..8 */ + #define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */ #define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */ @@ -539,7 +541,7 @@ #define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ #define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ # define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ # define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ @@ -555,7 +557,7 @@ /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ # define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) # define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ @@ -603,11 +605,11 @@ /* Common regular data register for dual mode */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ # define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) # define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ # define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h index ac0338cd867f9..b79de2c9eaf0b 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_can.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H /**************************************************************************** * Included Files @@ -54,61 +54,61 @@ /* CAN control and status registers */ -#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ -#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) -#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ -#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) -#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) -#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) -#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) -#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) -#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) -#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) -#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) -#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ /* CAN filter registers */ -#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ /* There are 14 filter banks on the device. Each filter bank is * composed of two 32-bit registers, CAN_FiR: @@ -119,63 +119,63 @@ * ... */ -#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) +#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) /* Register Addresses *******************************************************/ -#if STM32L4_NCAN > 0 -# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) -# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET) -# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET) -# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m)) -# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET) -# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET) -# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET) -# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET) -# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET) - -# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m)) -# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET) -# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET) -# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET) - -# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m)) -# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET) -# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET) -# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET) - -# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m)) -# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET) -# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET) -# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET) - -# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m)) -# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET) -# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET) -# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET) - -# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m)) -# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET) -# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET) - -# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m)) -# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET) -# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET) - -# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m)) -# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET) -# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET) - -# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m)) -# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET) -# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET) - -# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET) -# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET) -# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET) -# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET) -# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET) -# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i)) +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m)) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) + +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) + +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) + +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) + +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) + +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) + +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) + +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) + +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) + +# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ********************************************/ @@ -410,4 +410,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h index 4c9694ab78d14..f626c0dfb5ef4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H /**************************************************************************** * Pre-processor Definitions @@ -29,15 +29,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2) -#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ -#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ +#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2) +#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ +#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ /* Register Addresses *******************************************************/ -#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n)) -#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET) -#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET) +#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n)) +#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET) +#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -58,7 +58,7 @@ # define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */ # define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */ # define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMSEL_INMESEL (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: Selected by INMESEL */ #else # define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ @@ -68,7 +68,7 @@ #define COMP_CSR_INPSEL_MASK (3 << COMP_CSR_INPSEL_SHIFT) # define COMP_CSR_INPSEL_PIN1 (0 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */ # define COMP_CSR_INPSEL_PIN2 (1 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 2: COMP1=PB2; COMP2=PB6 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INPSEL_PIN3 (2 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 3: COMP1=PA1; COMP2=PA3 */ #endif @@ -101,7 +101,7 @@ #define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler bridge enable */ #define COMP_CSR_SCALEN (1 << 23) /* Bit 23: Voltage scaler enable bit */ /* Bit 24: Reserved */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMESEL_SHIFT (25) /* Bits 25-26: Input minus extended selection bits */ # define COMP_CSR_INMESEL_MASK (3 << COMP_CSR_INMESEL_SHIFT) # define COMP_CSR_INMESEL_PIN2 (0 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ @@ -109,10 +109,12 @@ # define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */ # define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */ #endif - /* Bits 27-29: Reserved */ + +/* Bits 27-29: Reserved */ + #define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */ #define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */ # define COMP_CSR_LOCK_RW (0) # define COMP_CSR_LOCK_RO COMP_CSR_LOCK_MASK -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 5ff70d77eaabc..38a33c17a4a7b 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET) -#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET) -#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET) -#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -100,4 +100,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h index d8d613212dae1..02030bcd91ae2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H /**************************************************************************** * Included Files @@ -36,51 +36,51 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* New registers not in STM32L1: */ -#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ -#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ -#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ -#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ -#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ -#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ +#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ +#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ +#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ +#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ +#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ +#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ /* Register Addresses *******************************************************/ -#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET) -#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET) -#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET) -#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET) -#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET) -#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET) -#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET) -#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET) -#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET) -#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET) -#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET) -#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET) -#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET) -#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET) -#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET) -#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET) -#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET) -#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET) -#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET) -#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET) +#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) +#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) +#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) +#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET) +#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET) +#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET) +#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET) +#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET) +#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -336,4 +336,4 @@ #define DAC_SHRR_TREFRESH2_SHIFT (16) /* Bits 16-23: DAC channel 2 refresh time */ #define DAC_SHRR_TREFRESH2_MASK (0xff << DAC_SHRR_TREFRESH2_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index 85546d55bc89a..0393e70882e28 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H /**************************************************************************** * Included Files @@ -41,134 +41,134 @@ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ -#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ -#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ -#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ -# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ -# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ -# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ +#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) + +#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ +#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ +#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ +#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ +# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ +# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ +# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ #endif -#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ -#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ -#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ -#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ -# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ -# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ -# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ +#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) + +#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ +#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ +#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ +#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ +# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ +# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ +# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ #endif -#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) + +#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ #endif -#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) - -#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ -#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ -#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ -#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ -# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ -# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ -# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ +#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) + +#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ +#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ +#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ +#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ +# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ +# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ +# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ #endif -#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ - -#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ -#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ -#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ -#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ -#ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ -# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ -# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ -# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ +#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ + +#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ +#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ +#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ +#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ +#ifndef CONFIG_STM32_STM32L4X3 +# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ +# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ +# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ +# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ #endif -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ - -# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ -# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ -# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ -# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ -# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ -# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ -# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ -# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ + +# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ +# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ +# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ +# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ +# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ +# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ +# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ +# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ -#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ -#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ -#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ -#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ -#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ -#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ -#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ -#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ -#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ -#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ -#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ -#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ -#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ -#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ +#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ +#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ +#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ +#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ +#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ +#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ +#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ +#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ +#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ +#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ +#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ +#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ +#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ +#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ +#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ /* Register Addresses *******************************************************/ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y)) -#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET) +#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y)) +#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET) -#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y)) -#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y)) -#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y) -#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y)) -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y)) +#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y)) +#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y)) +#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y) +#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y)) +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y)) #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x)) -#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x)) -#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x)) -#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x)) -#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x)) -#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x)) +#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x)) +#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x)) +#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x)) +#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x)) +#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x)) +#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x)) +#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x)) +#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x)) +#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x)) +#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x)) +#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x)) /* Register Bitfield Definitions ********************************************/ @@ -289,17 +289,17 @@ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO (0x00 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO2 (0x01 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO2 event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 8 TRGO event */ # else # define DFSDM_FLTCR1_JEXTSEL_T3TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 3 TRGO event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO2 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 8 TRGO2 event */ # else # define DFSDM_FLTCR1_JEXTSEL_T16CC1 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 16 CC1 (or OC1) event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T4TRGO (0x04 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0100: Timer 4 TRGO event */ # endif # define DFSDM_FLTCR1_JEXTSEL_T6TRGO (0x05 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0101: Timer 6 TRGO event */ @@ -413,8 +413,8 @@ /* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */ # define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT) #endif @@ -471,4 +471,4 @@ #define DFSDM_CNVTIMR_CNVCNT_SHIFT (4) /* Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK */ #define DFSDM_CNVTIMR_CNVCNT_MASK (~0xfu) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h index f6295dc9c42fd..a7585f24b27c4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -34,44 +34,44 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NEXTI1 31 -#define STM32L4_EXTI1_MASK 0xffffffff -#define STM32L4_NEXTI2 9 -#define STM32L4_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff -#define STM32L4_EXTI1_BIT(n) (1 << (n)) -#define STM32L4_EXTI2_BIT(n) (1 << (n)) +#define STM32_EXTI1_BIT(n) (1 << (n)) +#define STM32_EXTI2_BIT(n) (1 << (n)) /* Register Offsets *********************************************************/ -#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ -#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ +#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ +#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ -#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */ +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ /* Register Addresses *******************************************************/ -#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET) -#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET) +#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) +#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) -#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) -#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -105,62 +105,62 @@ /* Interrupt mask register */ -#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_IMR1_MASK STM32_EXTI1_MASK -#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_IMR2_MASK STM32_EXTI2_MASK /* Event mask register */ -#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_EMR1_MASK STM32_EXTI1_MASK -#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_EMR2_MASK STM32_EXTI2_MASK /* Rising Trigger selection register */ -#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_RTSR1_MASK STM32_EXTI1_MASK -#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_RTSR2_MASK STM32_EXTI2_MASK /* Falling Trigger selection register */ -#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR1_MASK STM32_EXTI1_MASK -#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR2_MASK STM32_EXTI2_MASK /* Software interrupt event register */ -#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK +#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER1_MASK STM32_EXTI1_MASK -#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK +#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER2_MASK STM32_EXTI2_MASK /* Pending register */ -#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR1_MASK STM32L4_EXTI1_MASK +#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR1_MASK STM32_EXTI1_MASK -#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR2_MASK STM32L4_EXTI2_MASK +#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR2_MASK STM32_EXTI2_MASK -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 8af1c073dc256..f338d5cb69269 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H /**************************************************************************** * Included Files @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with - * CONFIG_STM32L4_FLASH_OVERRIDE_x. For example: + * CONFIG_STM32_FLASH_OVERRIDE_x. For example: * * Parts STM32L4xxE have 512Kb of FLASH * Parts STM32L4xxG have 1024Kb of FLASH @@ -47,10 +47,10 @@ * The STM32L4x5/STM32L4x6 devices have two banks, but on 512 and 256 Kb * devices an option byte is available to map all pages to the first bank. * - * The STM32L43x/44x/45x/46x chips (CONFIG_STM32L4_STM32L4X3) have a + * The STM32L43x/44x/45x/46x chips (CONFIG_STM32_STM32L4X3) have a * single bank only. * - * STM32L4+ devices (CONFIG_STM32L4_STM32L4XR) have single and dual bank + * STM32L4+ devices (CONFIG_STM32_STM32L4XR) have single and dual bank * operating modes. * * The STM32L4R/Sxx devices have 1 Mb or 2 Mb of flash @@ -69,123 +69,123 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_I) -# define CONFIG_STM32L4_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L4_FLASH_CONFIG_8 -# undef CONFIG_STM32L4_FLASH_CONFIG_B -# undef CONFIG_STM32L4_FLASH_CONFIG_C -# undef CONFIG_STM32L4_FLASH_CONFIG_E -# undef CONFIG_STM32L4_FLASH_CONFIG_G -# undef CONFIG_STM32L4_FLASH_CONFIG_I -# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) -# define CONFIG_STM32L4_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) -# define CONFIG_STM32L4_FLASH_CONFIG_B -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) -# define CONFIG_STM32L4_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) -# define CONFIG_STM32L4_FLASH_CONFIG_E -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) -# define CONFIG_STM32L4_FLASH_CONFIG_G -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) -# define CONFIG_STM32L4_FLASH_CONFIG_I +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */ -# define STM32L4_FLASH_NPAGES 32 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */ -# define STM32L4_FLASH_NPAGES 64 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L4_FLASH_NPAGES 128 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L4_FLASH_NPAGES 256 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 4096 +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L4_FLASH_PAGESIZE -# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L4_FLASH_ACR_OFFSET 0x0000 -#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L4_FLASH_KEYR_OFFSET 0x0008 -#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32L4_FLASH_SR_OFFSET 0x0010 -#define STM32L4_FLASH_CR_OFFSET 0x0014 -#define STM32L4_FLASH_ECCR_OFFSET 0x0018 -#define STM32L4_FLASH_OPTR_OFFSET 0x0020 -#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024 -#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028 -#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c -#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030 -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044 -# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048 -# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c -# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR_OFFSET 0x0130 +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_CFGR_OFFSET 0x0130 #endif /* Register Addresses *******************************************************/ -#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET) -#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET) -#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET) -#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET) -#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET) -#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET) -#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET) -#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET) -#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET) -#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET) -#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET) -#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET) -# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET) -# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET) -# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) #endif -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET) +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -224,7 +224,7 @@ #define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ #define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ #define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) # define FLASH_SR_PEMPTY (1 << 17) /* Bit 17: Program empty */ #endif @@ -238,8 +238,8 @@ #define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT) #define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */ # define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */ #endif @@ -257,8 +257,8 @@ #define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */ #define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */ #endif #define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */ @@ -275,19 +275,19 @@ #define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/ #define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */ # define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */ #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_DBANK (1 << 22) /* Bit 22: Dual bank mode for 2MB devices */ #endif #define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */ #define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */ #define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */ # define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */ #endif @@ -307,8 +307,8 @@ /* Flash Configuration Register (CFGR) */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_CFGR_LVEN (1 << 0) /* Bit 0: Low voltage enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h index 8938d7d983c51..ca1b423d48d16 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ /* Register Addresses *******************************************************/ -#if STM32L4_NPORTS > 0 -# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 1 -# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 2 -# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 3 -# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 4 -# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 5 -# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 6 -# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 7 -# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 8 -# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -382,4 +382,4 @@ #define GPIO_ASCR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h index 9ec04ef430a84..0b8bb0a43c7bb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H /**************************************************************************** * Pre-processor Definitions @@ -29,74 +29,74 @@ /* Register Offsets *********************************************************/ -#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NI2C > 0 -# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 1 -# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 2 -# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 3 -# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 3 +# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -249,4 +249,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h index 1da51068e5564..bdd2b5f5aa31c 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h @@ -36,8 +36,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H /**************************************************************************** * Pre-processor Definitions @@ -47,36 +47,36 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ -#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ -#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ -#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ -#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ -#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ -#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ -#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ +#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ /* Register Addresses *******************************************************/ /* Low-Power Timers - LPTIM1 and LPTIM2 */ -#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) - -#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) +#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) + +#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -134,4 +134,4 @@ #define LPTIM_ISR_UP (1 << 5) /* Bit 5: Counter direction change down to up */ #define LPTIM_ISR_DOWN (1 << 6) /* Bit 6: Counter direction change up to down */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index 0cb4e62cac313..6c374c5295c1a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,60 +29,60 @@ /* STM32L4XXX Address Blocks ************************************************/ -#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ -#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ -#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ -#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ -#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ - /* 0xc0000000-0xdfffffff: 512Mb (not used) */ -#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ - -#define STM32L4_REGION_MASK 0xf0000000 -#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE) -#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1) +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ +#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ +#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ +#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ + /* 0xc0000000-0xdfffffff: 512Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ + +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ -#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ - /* 0x10010000-0x1ffeffff: Reserved */ -#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ -#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ -#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ - /* 0x1fff7400-0x1fff77ff: Reserved */ -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ - /* 0x1ff00010-0x1ff00fff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ - /* 0x1ff01010-0x1ff01fff: Reserved */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ + /* 0x1fff7400-0x1fff77ff: Reserved */ +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ + /* 0x1ff00010-0x1ff00fff: Reserved */ +# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ + /* 0x1ff01010-0x1ff01fff: Reserved */ #else -# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ - /* 0x1fff7810-0x1ffff7ff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ - /* 0x1ffff810-0x1fffffff: Reserved */ +# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ + /* 0x1fff7810-0x1ffff7ff: Reserved */ +# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ + /* 0x1ffff810-0x1fffffff: Reserved */ #endif /* System Memory Addresses **************************************************/ -#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: LQFP64 * 1: WLCSP64 @@ -105,123 +105,123 @@ /* 0x2001c000-0x2001ffff: * 16Kb aliased by bit-banding */ -#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ - /* 0x40016400-0x4001ffff: Reserved */ -#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ - /* 0x50060c00-0x5fffffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ + /* 0x40016400-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ + /* 0x50060c00-0x5fffffff: Reserved */ /* FSMC/QSPI Base Addresses *************************************************/ -#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32L4_LPTIM2_BASE 0x40009400 -#define STM32L4_SWPMI1_BASE 0x40008800 -#define STM32L4_I2C4_BASE 0x40008400 -#define STM32L4_LPUART1_BASE 0x40008000 -#define STM32L4_LPTIM1_BASE 0x40007c00 -#define STM32L4_OPAMP_BASE 0x40007800 -#define STM32L4_DAC_BASE 0x40007400 -#define STM32L4_PWR_BASE 0x40007000 -#if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_USB_SRAM_BASE 0x40006c00 -# define STM32L4_USB_FS_BASE 0x40006800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_SWPMI1_BASE 0x40008800 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#if defined(CONFIG_STM32_STM32L4X3) +# define STM32_USB_SRAM_BASE 0x40006c00 +# define STM32_USB_FS_BASE 0x40006800 #else -# define STM32L4_CAN2_BASE 0x40006800 +# define STM32_CAN2_BASE 0x40006800 #endif -#define STM32L4_CAN1_BASE 0x40006400 -#define STM32L4_CRS_BASE 0x40006000 -#define STM32L4_I2C3_BASE 0x40005c00 -#define STM32L4_I2C2_BASE 0x40005800 -#define STM32L4_I2C1_BASE 0x40005400 -#define STM32L4_UART5_BASE 0x40005000 -#define STM32L4_UART4_BASE 0x40004c00 -#define STM32L4_USART3_BASE 0x40004800 -#define STM32L4_USART2_BASE 0x40004400 -#define STM32L4_SPI3_BASE 0x40003c00 -#define STM32L4_SPI2_BASE 0x40003800 -#define STM32L4_IWDG_BASE 0x40003000 -#define STM32L4_WWDG_BASE 0x40002c00 -#define STM32L4_RTC_BASE 0x40002800 -#define STM32L4_LCD_BASE 0x40002400 -#define STM32L4_TIM7_BASE 0x40001400 -#define STM32L4_TIM6_BASE 0x40001000 -#define STM32L4_TIM5_BASE 0x40000c00 -#define STM32L4_TIM4_BASE 0x40000800 -#define STM32L4_TIM3_BASE 0x40000400 -#define STM32L4_TIM2_BASE 0x40000000 +#define STM32_CAN1_BASE 0x40006400 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004c00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_LCD_BASE 0x40002400 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L4_DSI_BASE 0x40016c00 -#define STM32L4_LTDC_BASE 0x40016800 -#define STM32L4_DFSDM_BASE 0x40016000 -#define STM32L4_SAI2_BASE 0x40015800 -#define STM32L4_SAI1_BASE 0x40015400 -#define STM32L4_TIM17_BASE 0x40014800 -#define STM32L4_TIM16_BASE 0x40014400 -#define STM32L4_TIM15_BASE 0x40014000 -#define STM32L4_USART1_BASE 0x40013800 -#define STM32L4_TIM8_BASE 0x40013400 -#define STM32L4_SPI1_BASE 0x40013000 -#define STM32L4_TIM1_BASE 0x40012c00 -#ifndef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x40012800 +#define STM32_DSI_BASE 0x40016c00 +#define STM32_LTDC_BASE 0x40016800 +#define STM32_DFSDM_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012c00 +#ifndef CONFIG_STM32_STM32L4XR +# define STM32_SDMMC1_BASE 0x40012800 #endif -#define STM32L4_FIREWALL_BASE 0x40011c00 -#define STM32L4_EXTI_BASE 0x40010400 -#define STM32L4_COMP_BASE 0x40010200 -#define STM32L4_VREFBUF_BASE 0x40010030 -#define STM32L4_SYSCFG_BASE 0x40010000 +#define STM32_FIREWALL_BASE 0x40011c00 +#define STM32_EXTI_BASE 0x40010400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L4_GFXMMU_BASE 0x4002c000 -#define STM32L4_DMA2D_BASE 0x4002b000 -#define STM32L4_TSC_BASE 0x40024000 -#define STM32L4_CRC_BASE 0x40023000 -#define STM32L4_FLASHIF_BASE 0x40022000 -#define STM32L4_RCC_BASE 0x40021000 -#define STM32L4_DMAMUX1_BASE 0x40020800 -#define STM32L4_DMA2_BASE 0x40020400 -#define STM32L4_DMA1_BASE 0x40020000 +#define STM32_GFXMMU_BASE 0x4002c000 +#define STM32_DMA2D_BASE 0x4002b000 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x50062400 +#ifdef CONFIG_STM32_STM32L4XR +# define STM32_SDMMC1_BASE 0x50062400 #endif -#define STM32L4_OCTOSPIIOM_BASE 0x50061c00 -#define STM32L4_RNG_BASE 0x50060800 -#define STM32L4_HASH_BASE 0x50060400 -#define STM32L4_AES_BASE 0x50060000 -#define STM32L4_DCMI_BASE 0x50050000 -#define STM32L4_ADC_BASE 0x50040000 -# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */ -# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */ -# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */ -# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */ -#define STM32L4_OTGFS_BASE 0x50000000 -#define STM32L4_GPIOI_BASE 0x48002000 -#define STM32L4_GPIOH_BASE 0x48001c00 -#define STM32L4_GPIOG_BASE 0x48001800 -#define STM32L4_GPIOF_BASE 0x48001400 -#define STM32L4_GPIOE_BASE 0x48001000 -#define STM32L4_GPIOD_BASE 0x48000c00 -#define STM32L4_GPIOC_BASE 0x48000800 -#define STM32L4_GPIOB_BASE 0x48000400 -#define STM32L4_GPIOA_BASE 0x48000000 +#define STM32_OCTOSPIIOM_BASE 0x50061c00 +#define STM32_RNG_BASE 0x50060800 +#define STM32_HASH_BASE 0x50060400 +#define STM32_AES_BASE 0x50060000 +#define STM32_DCMI_BASE 0x50050000 +#define STM32_ADC_BASE 0x50040000 +# define STM32_ADC1_BASE 0x50040000 /* ADC1 */ +# define STM32_ADC2_BASE 0x50040100 /* ADC2 */ +# define STM32_ADC3_BASE 0x50040200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x50040300 /* Common */ +#define STM32_OTGFS_BASE 0x50000000 +#define STM32_GPIOI_BASE 0x48002000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_GPIOG_BASE 0x48001800 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* Cortex-M4 Base Addresses *************************************************/ @@ -229,7 +229,7 @@ * this address range */ -#define STM32L4_SCS_BASE 0xe000e000 -#define STM32L4_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h index c8e33f62f181f..57bf610937565 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,16 +30,16 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_pinmap.h" #else # error "Unsupported STM32 L4 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index ab598f0c70ac6..3031f5fcf8d55 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,64 +36,64 @@ /* Register Offsets *********************************************************/ -#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ -#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ +#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET) -#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET) -#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET) -#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET) -#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET) -#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET) -#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET) -#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET) -#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET) -#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET) -#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET) -#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET) -#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET) -#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET) -#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET) -#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET) -#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET) -#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET) -#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET) -#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET) -#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET) -#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET) -#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET) -#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET) -#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET) +#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET) +#if defined(CONFIG_STM32_STM32L4XR) +# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -107,7 +107,7 @@ # define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */ # define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */ # define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR1_RRSTP (1 << 4) /* Bit 4: SRAM3 retention in Stop 2 mode */ #endif #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */ @@ -133,12 +133,12 @@ # define PWR_CR2_PLS_EXT (7 << PWR_CR2_PLS_SHIFT) /* 111: External input analog voltage PVD_IN */ #define PWR_CR2_PVME1 (1 << 4) /* Bit 4: Peripheral voltage monitoring 1 enable (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_PVME2 (1 << 5) /* Bit 5: Peripheral voltage monitoring 2 enable (VDDIO2 vs 0.9V) */ #endif #define PWR_CR2_PVME3 (1 << 6) /* Bit 6: Peripheral voltage monitoring 3 enable (VDDA vs 1.62V) */ #define PWR_CR2_PVME4 (1 << 7) /* Bit 7: Peripheral voltage monitoring 4 enable (VDDA vs 2.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_IOSV (1 << 9) /* Bit 9: VDDIO2 Independent I/Os supply valid */ #endif #define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB USB supply valid */ @@ -152,7 +152,7 @@ #define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */ #define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */ #define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR3_DSIPDEN (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */ #endif #define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */ @@ -187,7 +187,7 @@ #define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */ #define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */ #define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: Peripheral voltage monitoring output 1 (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_SR2_PVMO2 (1 << 13) /* Bit 13: Peripheral voltage monitoring output 2 (VDDIO2 vs 0.9V) */ #endif #define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: Peripheral voltage monitoring output 3 (VDDA vs 1.62V) */ @@ -208,8 +208,8 @@ /* Power control register 5 */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */ #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h index 3a1b8214d2c86..80d7a52e1e59d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H /**************************************************************************** * Included Files @@ -38,40 +38,40 @@ /* General Characteristics **************************************************/ -#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ -#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ -#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ -#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ -#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ -#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ -#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ +#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ +#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ +#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ +#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ +#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ +#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ +#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ +#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ /* QSPI register addresses **************************************************/ -#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */ -#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */ -#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */ -#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */ -#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */ -#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */ +#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ +#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */ +#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ +#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */ +#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ +#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */ +#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */ +#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ +#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ /* QSPI register bit definitions ********************************************/ @@ -221,4 +221,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h index 387776eb2ab50..b7aafe108ca18 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H /**************************************************************************** * Included Files @@ -36,15 +36,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ /* Register Addresses *******************************************************/ -#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET) -#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET) -#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET) +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -61,4 +61,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h index d2f1ad30b0863..c0f47afb6f680 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,117 +29,117 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ -#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ -#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ -#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ -#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ -#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ -#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ -#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ -#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ -#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ -#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ -#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ -#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ /* Register Addresses *******************************************************/ -#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET) -#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET) -#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET) -#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET) -#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET) -#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET) -#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET) -#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET) -#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET) -#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET) -#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET) -#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET) -#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET) -#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET) -#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET) -#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET) -#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET) -#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET) -#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET) - -#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n)) -#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET) -#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET) -#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET) -#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET) -#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET) -#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET) -#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET) -#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET) -#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET) -#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET) -#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET) -#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET) -#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET) -#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET) -#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET) -#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET) -#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET) -#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET) -#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET) -#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET) -#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET) -#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET) -#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET) -#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET) -#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET) -#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET) -#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET) -#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET) -#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET) -#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET) -#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET) -#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET) - -# define STM32L4_RTC_BKCOUNT 32 +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) + +# define STM32_RTC_BKCOUNT 32 /* Register Bitfield Definitions ********************************************/ @@ -388,4 +388,4 @@ #define RTC_OR_ALARMTYPE (1 << 0) /* Bit 0: RTC alarm type on PC13, pushpull/OD */ #define RTC_OR_OUTRMP (1 << 1) /* Bit 1: remap output to PB2 */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index ea33be29c5270..3dc1e420552eb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H /**************************************************************************** * Included Files @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32L4_SAI_A_OFFSET 0x0004 -#define STM32L4_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET) - -#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET) - -#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET) - -#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET) - -#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET) + +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET) + +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) + +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) + +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET) + +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -259,4 +259,4 @@ /* SAI Data Register (32-bit data) */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SAI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h index 00cebe249dd8b..7749c402716d3 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SDMMC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SDMMC_H /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h index 6098c3949d376..060a9978451c4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H /**************************************************************************** * Included Files @@ -36,48 +36,48 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32L4_SPI_CLK_MAX 40000000UL +#define STM32_SPI_CLK_MAX 40000000UL /* Register Offsets *********************************************************/ -#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L4_NSPI > 0 -# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 1 -# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 2 -# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -162,4 +162,4 @@ # define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h index a038906b332e7..23e4bf662da76 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -30,16 +30,16 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_syscfg.h" #else # error "Unsupported STM32 L4 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index b643e79014eef..0baadf3c961d4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L4_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L4_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L4_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L4_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L4_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L4_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L4_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L4_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L4_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L4_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L4_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L4_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L4_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L4_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L4_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L4_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_TIM1_CR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM1_CR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM1_SMCR (STM32L4_TIM1_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM1_DIER (STM32L4_TIM1_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM1_SR (STM32L4_TIM1_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM1_EGR (STM32L4_TIM1_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM1_CCMR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM1_CCMR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM1_CCER (STM32L4_TIM1_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM1_CNT (STM32L4_TIM1_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM1_PSC (STM32L4_TIM1_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM1_ARR (STM32L4_TIM1_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM1_RCR (STM32L4_TIM1_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM1_CCR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM1_CCR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM1_CCR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM1_CCR4 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM1_BDTR (STM32L4_TIM1_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM1_DCR (STM32L4_TIM1_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM1_DMAR (STM32L4_TIM1_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM1_OR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM1_CCMR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM1_CCR5 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM1_CCR6 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM1_OR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM1_OR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR3_OFFSET) - -#define STM32L4_TIM8_CR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM8_CR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM8_SMCR (STM32L4_TIM8_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM8_DIER (STM32L4_TIM8_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM8_SR (STM32L4_TIM8_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM8_EGR (STM32L4_TIM8_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM8_CCMR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM8_CCMR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM8_CCER (STM32L4_TIM8_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM8_CNT (STM32L4_TIM8_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM8_PSC (STM32L4_TIM8_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM8_ARR (STM32L4_TIM8_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM8_RCR (STM32L4_TIM8_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM8_CCR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM8_CCR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM8_CCR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM8_CCR4 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM8_BDTR (STM32L4_TIM8_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM8_DCR (STM32L4_TIM8_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM8_DMAR (STM32L4_TIM8_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM8_OR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM8_CCMR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM8_CCR5 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM8_CCR6 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM2_CR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM2_SMCR (STM32L4_TIM2_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM2_DIER (STM32L4_TIM2_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM2_SR (STM32L4_TIM2_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM2_EGR (STM32L4_TIM2_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM2_CCMR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM2_CCMR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM2_CCER (STM32L4_TIM2_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM2_CNT (STM32L4_TIM2_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM2_PSC (STM32L4_TIM2_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM2_ARR (STM32L4_TIM2_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM2_CCR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM2_CCR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM2_CCR3 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM2_CCR4 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM2_DCR (STM32L4_TIM2_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM2_DMAR (STM32L4_TIM2_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM2_OR (STM32L4_TIM2_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM3_CR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM3_CR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM3_SMCR (STM32L4_TIM3_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM3_DIER (STM32L4_TIM3_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM3_SR (STM32L4_TIM3_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM3_EGR (STM32L4_TIM3_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM3_CCMR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM3_CCMR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM3_CCER (STM32L4_TIM3_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM3_CNT (STM32L4_TIM3_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM3_PSC (STM32L4_TIM3_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM3_ARR (STM32L4_TIM3_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM3_CCR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM3_CCR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM3_CCR3 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM3_CCR4 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM3_DCR (STM32L4_TIM3_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM3_DMAR (STM32L4_TIM3_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM4_CR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM4_CR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM4_SMCR (STM32L4_TIM4_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM4_DIER (STM32L4_TIM4_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM4_SR (STM32L4_TIM4_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM4_EGR (STM32L4_TIM4_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM4_CCMR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM4_CCMR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM4_CCER (STM32L4_TIM4_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM4_CNT (STM32L4_TIM4_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM4_PSC (STM32L4_TIM4_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM4_ARR (STM32L4_TIM4_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM4_CCR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM4_CCR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM4_CCR3 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM4_CCR4 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM4_DCR (STM32L4_TIM4_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM4_DMAR (STM32L4_TIM4_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM5_CR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM5_CR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM5_SMCR (STM32L4_TIM5_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM5_DIER (STM32L4_TIM5_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM5_SR (STM32L4_TIM5_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM5_EGR (STM32L4_TIM5_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM5_CCMR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM5_CCMR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM5_CCER (STM32L4_TIM5_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM5_CNT (STM32L4_TIM5_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM5_PSC (STM32L4_TIM5_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM5_ARR (STM32L4_TIM5_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM5_CCR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM5_CCR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM5_CCR3 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM5_CCR4 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM5_DCR (STM32L4_TIM5_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM5_DMAR (STM32L4_TIM5_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM5_OR (STM32L4_TIM5_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM15_CR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM15_CR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM15_SMCR (STM32L4_TIM15_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM15_DIER (STM32L4_TIM15_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM15_SR (STM32L4_TIM15_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM15_EGR (STM32L4_TIM15_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM15_CCMR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM15_CCER (STM32L4_TIM15_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM15_CNT (STM32L4_TIM15_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM15_PSC (STM32L4_TIM15_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM15_ARR (STM32L4_TIM15_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM15_RCR (STM32L4_TIM15_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM15_CCR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM15_CCR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM15_BDTR (STM32L4_TIM15_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM15_DCR (STM32L4_TIM15_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM15_DMAR (STM32L4_TIM15_BASE+STM32L4_GTIM_DMAR_OFFSET) - -#define STM32L4_TIM16_CR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM16_CR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM16_DIER (STM32L4_TIM16_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM16_ARR (STM32L4_TIM16_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM16_RCR (STM32L4_TIM16_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM16_CCR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM16_BDTR (STM32L4_TIM16_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM16_DCR (STM32L4_TIM16_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM16_DMAR (STM32L4_TIM16_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM16_OR (STM32L4_TIM16_BASE+STM32L4_GTIM_OR_OFFSET) - -#define STM32L4_TIM17_CR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM17_CR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM17_DIER (STM32L4_TIM17_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM17_ARR (STM32L4_TIM17_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM17_RCR (STM32L4_TIM17_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM17_CCR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM17_BDTR (STM32L4_TIM17_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM17_DCR (STM32L4_TIM17_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM17_DMAR (STM32L4_TIM17_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_TIM6_CR1 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM6_CR2 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM6_DIER (STM32L4_TIM6_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM6_SR (STM32L4_TIM6_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM6_EGR (STM32L4_TIM6_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM6_CNT (STM32L4_TIM6_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM6_PSC (STM32L4_TIM6_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM6_ARR (STM32L4_TIM6_BASE+STM32L4_BTIM_ARR_OFFSET) - -#define STM32L4_TIM7_CR1 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM7_CR2 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM7_DIER (STM32L4_TIM7_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM7_SR (STM32L4_TIM7_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM7_EGR (STM32L4_TIM7_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM7_CNT (STM32L4_TIM7_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -1124,4 +1124,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index c904dba002a48..cf3135593e540 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,88 +37,88 @@ /* Register Offsets *********************************************************/ -#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NUSART > 0 -# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 1 -# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 2 -# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 3 -# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 4 -# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -308,4 +308,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index acea9cc7e31e9..3a5a79c698a8e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32L4_STM32L4X2) +#if defined(CONFIG_STM32_STM32L4X2) /**************************************************************************** * Pre-processor Definitions @@ -40,71 +40,71 @@ /* Endpoint Registers */ -#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ -#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ /* Common Registers */ -#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Addresses *******************************************************/ /* Endpoint Registers */ -#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n)) -#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET) -#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET) -#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET) -#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET) -#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET) -#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET) -#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET) -#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET) +#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET) /* Common Registers */ -#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET) -#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET) -#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET) -#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET) -#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET) -#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET) -#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET) +#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET) /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o)) -#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Bitfield Definitions ********************************************/ @@ -251,5 +251,5 @@ #define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ -#endif /* CONFIG_STM32L4_STM32L4X2 */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H */ +#endif /* CONFIG_STM32_STM32L4X2 */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h index 335086592073e..b286b92dce290 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H /**************************************************************************** * Included Files @@ -37,27 +37,27 @@ /* Register Offsets *********************************************************/ -#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ -#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ /* Register Addresses *******************************************************/ -#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET) -#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET) -#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET) -#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET) -#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET) +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET) -#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET) -#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET) +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -138,4 +138,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h index bc4070f7dfcb0..587031ae9344a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,145 +306,145 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h index 153953e705af3..7aa56323221ea 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index 73fcb283519c8..38db3afd93887 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -791,5 +791,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h index 968eddee74915..17502c2562f14 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -169,5 +169,5 @@ #define SYSCFG_SKR_SHIFT 0 #define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h index b56cb00fc7035..0ff70f0abf297 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,167 +306,167 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h index 6ca4fea84720a..df83782f5a863 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h index 9ca5ed2dbecc6..7e78f15e1711e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ @@ -741,7 +741,7 @@ #define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 #define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */ #define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT) - /* Bits 24-31: Reserved, must be kept at reset value */ + /* Bits 24-31: Reserved, must be kept at reset value */ /* Device IN endpoint common interrupt mask register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index 218ac07c4bb84..5d81e280f129d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -37,69 +37,69 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -721,5 +721,5 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h index c092d69675ac4..40983ec429787 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -163,5 +163,5 @@ #define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */ #define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h index 34509ed7668fe..f8dc5a363257e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h @@ -81,14 +81,14 @@ #define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ #endif #define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */ /* Debug MCU APB1 freeze register 2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 SMBUS timeout mode stopped when Core is halted */ #endif #define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h index 48c9a9d1d99d5..f0dbeddab006f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ - -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ + +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -276,21 +276,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) - -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) + +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -305,186 +305,186 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* HASH */ -#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6) +#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32_DMA2_CHAN7, 6) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) - -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) - -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) - -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) - -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) - -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) - -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) - -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) - -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) - -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) - -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) + +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) + +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) + +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) + +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) + +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) + +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) + +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) + +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) + +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) + +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h index 4272f345b7604..6428f606e4b1a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -81,7 +81,7 @@ /* Volatile Data Segment Start Address */ #define FIREWALL_VDSADD_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT) #else # define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT) @@ -90,7 +90,7 @@ /* Volatile Data Segment Length */ #define FIREWALL_VDSLENG_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT) #else # define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h index 12288d4b39f99..c92296e69f669 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 991c15297562a..29a19f63a1457 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -712,7 +712,7 @@ #define RCC_CCIPR_CLK48SEL_SHIFT (26) #define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT) -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define RCC_CCIPR_CLK48SEL_HSI48 (0 << RCC_CCIPR_CLK48SEL_SHIFT) #else # define RCC_CCIPR_CLK48SEL_NONE (0 << RCC_CCIPR_CLK48SEL_SHIFT) @@ -807,5 +807,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h index 1bf04c71f6e05..bc0ff376cfbaa 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -179,5 +179,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h index 8229ac0413c8d..5f32ee5ef75d1 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 - -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) - -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) - -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) - -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) - -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) - -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) - -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h index c0572faa6bccd..19a79a36e07e7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0) -#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1) -#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2) -#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3) -#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4) -#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5) -#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6) -#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7) -#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8) -#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9) -#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10) -#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11) -#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12) -#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0) -#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1) -#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2) -#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3) -#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ /* Register Addresses *******************************************************/ -#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET) -#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET) -#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET) -#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET) -#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET) -#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET) -#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET) -#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET) -#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET) -#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET) -#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET) -#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET) -#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET) -#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET) - -#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET) -#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET) - -#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET) -#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET) -#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET) -#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET) - -#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET) -#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h index 9c2f082d507b5..d6b0830307809 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index c2bc0db32bc09..467ee101d5a83 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -860,5 +860,5 @@ # define RCC_CCIPR2_SAI2SEL_SAI2_EXT (3 << RCC_CCIPR2_SAI2SEL_SHIFT) # define RCC_CCIPR2_SAI2SEL_HSI (4 << RCC_CCIPR2_SAI2SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h index d95a8e753639d..b24b23bc0fcf4 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -181,5 +181,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/stm32l4.h b/arch/arm/src/stm32l4/stm32l4.h index 8aeee5c68619b..d4a19deccdf58 100644 --- a/arch/arm/src/stm32l4/stm32l4.h +++ b/arch/arm/src/stm32l4/stm32l4.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_H +#define __ARCH_ARM_SRC_STM32L4_STM32_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 21f9264bc5289..863ae59a689a1 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -172,14 +172,14 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, /* 1-Wire device structures */ -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire1_config = { - .usartbase = STM32L4_USART1_BASE, - .apbclock = STM32L4_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, }; static struct stm32_1wire_priv_s stm32_1wire1_priv = @@ -196,14 +196,14 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire2_config = { - .usartbase = STM32L4_USART2_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, }; static struct stm32_1wire_priv_s stm32_1wire2_priv = @@ -220,14 +220,14 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire3_config = { - .usartbase = STM32L4_USART3_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, }; static struct stm32_1wire_priv_s stm32_1wire3_priv = @@ -244,14 +244,14 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire4_config = { - .usartbase = STM32L4_UART4_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, }; static struct stm32_1wire_priv_s stm32_1wire4_priv = @@ -268,14 +268,14 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire5_config = { - .usartbase = STM32L4_UART5_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, }; static struct stm32_1wire_priv_s stm32_1wire5_priv = @@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) { - return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff; + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; } /**************************************************************************** @@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) { - stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); } /**************************************************************************** @@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) * for baud changing. */ - cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); enabled = cr1 & USART_CR1_UE; if (enabled) { cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); } /* In case of oversampling by 8, the equation is: @@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) cr1 |= USART_CR1_OVER8; } - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); if (enabled) { - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); } } @@ -463,38 +463,38 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, default: return; -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER - case STM32L4_USART1_BASE: +#ifdef CONFIG_STM32_USART1_1WIREDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER - case STM32L4_USART2_BASE: +#ifdef CONFIG_STM32_USART2_1WIREDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER - case STM32L4_USART3_BASE: +#ifdef CONFIG_STM32_USART3_1WIREDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER - case STM32L4_UART4_BASE: +#ifdef CONFIG_STM32_UART4_1WIREDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER - case STM32L4_UART5_BASE: +#ifdef CONFIG_STM32_UART5_1WIREDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) * Set LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 * Clear TE, REm, all interrupt enable bits, PCE, PS and M * Set RXNEIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 * Clear CTSE, RTSE, and all interrupt enable bits * Set ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Set baud rate */ @@ -569,9 +569,9 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Enable Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure pins for USART use */ @@ -608,21 +608,21 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Disable RXNEIE, Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Clear LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Clear ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Disable USART APB1/2 clock */ @@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) /* Get the masked USART status word. */ - sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET); + sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); /* Receive loop */ @@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); if (priv->msgs != NULL) @@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_ISR_LBDF) != 0) { - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF); + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); if (priv->msgs != NULL) { @@ -1150,31 +1150,31 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) switch (port) { -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER case 1: priv = &stm32_1wire1_priv; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER case 2: priv = &stm32_1wire2_priv; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER case 3: priv = &stm32_1wire3_priv; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER case 4: priv = &stm32_1wire4_priv; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER case 5: priv = &stm32_1wire5_priv; break; diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h index b196230e6557d..e033594d51305 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ b/arch/arm/src/stm32l4/stm32l4_1wire.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -71,4 +71,4 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port); int stm32l4_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index d6f484eed911f..e2e7583df0619 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -56,16 +56,16 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# if defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) +# if defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) # error "Using non-existent ADC" # endif #endif @@ -81,23 +81,23 @@ /* RCC reset ****************************************************************/ -#define STM32L4_RCC_RSTR STM32L4_RCC_AHB2RSTR +#define STM32_RCC_RSTR STM32_RCC_AHB2RSTR #define RCC_RSTR_ADC1RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC2RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC3RST RCC_AHB2RSTR_ADCRST /* ADC interrupts ***********************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1 +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) +# define STM32_IRQ_ADC12 STM32_IRQ_ADC1 #endif /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32L4 ADC DMA support requires CONFIG_STM32L4_DMA1 or CONFIG_STM32L4_DMA2" +# error "STM32L4 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -110,10 +110,10 @@ /* Sample time default configuration */ -#ifndef CONFIG_STM32L4_ADC_SMPR +#ifndef CONFIG_STM32_ADC_SMPR # define ADC_SMPR_DEFAULT ADC_SMPR_640p5 #else -# define ADC_SMPR_DEFAULT CONFIG_STM32L4_ADC_SMPR +# define ADC_SMPR_DEFAULT CONFIG_STM32_ADC_SMPR #endif #define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \ @@ -161,10 +161,10 @@ struct stm32_dev_s { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -219,7 +219,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32L4_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -280,12 +280,12 @@ static int adc_timinit(struct stm32_dev_s *priv); #ifdef ADC_HAVE_DMA static void adc_dma_cfg(struct stm32_dev_s *priv); static void adc_dma_start(struct adc_dev_s *dev); -# ifndef CONFIG_STM32L4_ADC_NOIRQ +# ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); # endif #endif -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset); #endif @@ -303,7 +303,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e state); #endif -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static void adc_llops_intack(struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(struct stm32_adc_dev_s *dev, @@ -339,19 +339,19 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -# if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +# if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); # endif -# if defined(CONFIG_STM32L4_ADC3) +# if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); # endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -381,7 +381,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -408,31 +408,31 @@ static const struct stm32_adc_ops_s g_adc_llops = # endif .dump_regs = adc_llops_dumpregs }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC1 state */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, #endif - .base = STM32L4_ADC1_BASE, + .base = STM32_ADC1_BASE, #if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG) .extcfg = ADC1_EXTCFG_VALUE, #endif @@ -443,14 +443,14 @@ static struct stm32_dev_s g_adcpriv1 = .channel = ADC1_TIMER_CHANNEL, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC1_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -472,27 +472,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 2, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, #endif - .base = STM32L4_ADC2_BASE, + .base = STM32_ADC2_BASE, #if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG) .extcfg = ADC2_EXTCFG_VALUE, #endif @@ -503,14 +503,14 @@ static struct stm32_dev_s g_adcpriv2 = .channel = ADC2_TIMER_CHANNEL, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC2_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -532,27 +532,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC3, +#ifndef CONFIG_STM32_ADC_NOIRQ + .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 3, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC3_RESOLUTION, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, #endif - .base = STM32L4_ADC3_BASE, + .base = STM32_ADC3_BASE, #if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG) .extcfg = ADC3_EXTCFG_VALUE, #endif @@ -563,14 +563,14 @@ static struct stm32_dev_s g_adcpriv3 = .channel = ADC3_TIMER_CHANNEL, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC3_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -771,38 +771,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -830,14 +830,14 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -870,7 +870,7 @@ static int adc_timinit(struct stm32_dev_s *priv) uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; uint32_t channel = priv->channel - 1; /* If the timer base address is zero, then this ADC was not configured to @@ -955,30 +955,30 @@ static int adc_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* Handle channel specific setup */ /* Assume that channel is disabled and polarity is active high */ - ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer_val = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -995,41 +995,41 @@ static int adc_timinit(struct stm32_dev_s *priv) if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = tim_getreg(priv, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; tim_putreg(priv, ccmr_offset, ccmr_orig); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer_val); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer_val); switch (channel) { case 0: /* TIMx CC1 */ { - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; case 1: /* TIMx CC2 */ { - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; case 2: /* TIMx CC3 */ { - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; case 3: /* TIMx CC4 */ { - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -1063,7 +1063,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, container_of(cb, struct stm32_dev_s, pm_callback); uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if ((state >= PM_IDLE) && (regval & ADC_CR_ADSTART)) { return -EBUSY; @@ -1087,16 +1087,16 @@ static void adc_wdog_enable(struct stm32_dev_s *priv) /* Initialize the Analog watchdog enable */ - regval = adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CFGR_OFFSET); regval |= ADC_CFGR_AWD1EN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD; - adc_putreg(priv, STM32L4_ADC_CFGR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CFGR_OFFSET, regval); /* Switch to analog watchdog interrupt */ - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); regval |= ADC_INT_AWD1; regval &= ~ADC_INT_EOC; - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1119,7 +1119,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) ainfo("enable: %d\n", enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if (enable) { /* Start conversion of regular channels */ @@ -1133,7 +1133,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) regval |= ADC_CR_ADSTP; } - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); } #ifdef ADC_HAVE_INJECTED @@ -1162,11 +1162,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Start the conversion of regular channels */ - adc_modifyreg(priv, STM32L4_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); } else { - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Is a conversion ongoing? */ @@ -1174,11 +1174,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Stop the conversion */ - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); /* Wait for the conversion to stop */ - while ((adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_JADSTP) != 0); } } @@ -1216,7 +1216,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the AHB2 reset register */ - regval = getreg32(STM32L4_RCC_AHB2RSTR); + regval = getreg32(STM32_RCC_AHB2RSTR); if (reset) { regval |= RCC_AHB2RSTR_ADCRST; @@ -1226,7 +1226,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_AHB2RSTR_ADCRST; } - putreg32(regval, STM32L4_RCC_AHB2RSTR); + putreg32(regval, STM32_RCC_AHB2RSTR); leave_critical_section(flags); } @@ -1247,13 +1247,13 @@ static void adc_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Exit deep power down mode and enable voltage regulator */ regval &= ~ADC_CR_DEEPPWD; regval |= ADC_CR_ADVREGEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for voltage regulator to power up */ @@ -1264,11 +1264,11 @@ static void adc_enable(struct stm32_dev_s *priv) */ regval |= ADC_CR_ADCAL; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for calibration to complete */ - while (adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & ADC_CR_ADCAL); + while (adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL); /* Enable ADC * Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle @@ -1277,13 +1277,13 @@ static void adc_enable(struct stm32_dev_s *priv) * ARM instructions. */ - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); regval |= ADC_CR_ADEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for hardware to be ready for conversions */ - while (!(adc_getreg(priv, STM32L4_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); + while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); } /**************************************************************************** @@ -1298,7 +1298,7 @@ static void adc_enable(struct stm32_dev_s *priv) static int adc_bind(struct adc_dev_s *dev, const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1353,8 +1353,8 @@ static void adc_reset(struct adc_dev_s *dev) static int adc_setup(struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32L4_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ - !defined(CONFIG_STM32L4_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ + !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; @@ -1364,7 +1364,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1400,7 +1400,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Set CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); /* Configuration of the channel conversions */ @@ -1432,7 +1432,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_internal(priv, &setbits); - stm32_modifyreg32(STM32L4_ADC_CCR, clrbits, setbits); + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); #ifdef ADC_HAVE_DMA if (priv->hasdma) @@ -1479,7 +1479,7 @@ static int adc_setup(struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32L4_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ if (priv->cchannels > 0) @@ -1496,7 +1496,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1536,7 +1536,7 @@ static int adc_setup(struct adc_dev_s *dev) static void adc_shutdown(struct adc_dev_s *dev) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1569,7 +1569,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); if (enable) { /* Enable end of conversion interrupt */ @@ -1592,7 +1592,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) regval &= ~ADC_INT_MASK; } - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1615,7 +1615,7 @@ static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) /* Modify appropriate register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, res << ADC_CFGR_RES_SHIFT); errout: @@ -1635,8 +1635,8 @@ static void adc_sample_time_set(struct adc_dev_s *dev) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - adc_putreg(priv, STM32L4_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); - adc_putreg(priv, STM32L4_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); } /**************************************************************************** @@ -1673,7 +1673,7 @@ static int adc_extsel_set(struct stm32_dev_s *priv, uint32_t extcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } return OK; @@ -1714,7 +1714,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); } return OK; @@ -1731,25 +1731,25 @@ static void adc_dumpregs(struct stm32_dev_s *priv) ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_ISR_OFFSET), - adc_getreg(priv, STM32L4_ADC_IER_OFFSET), - adc_getreg(priv, STM32L4_ADC_CR_OFFSET), - adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 " SQR3: 0x%08" PRIx32 " SQR4: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SQR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR3_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR4_OFFSET)); + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SMPR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SMPR2_OFFSET)); + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); #ifdef ADC_HAVE_INJECTED ainfo("JSQR: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_JSQR_OFFSET)); + adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); #endif } @@ -1801,12 +1801,12 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) break; case 17: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC1_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC1_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_TSEN; #endif break; case 18: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC2_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC2_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_VBATEN; #endif break; @@ -1824,7 +1824,7 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) * Name: adc_offset_set ****************************************************************************/ -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset) @@ -1841,7 +1841,7 @@ static int adc_offset_set(struct stm32_dev_s *priv, goto errout; } - reg = STM32L4_ADC_OFR1_OFFSET + i * 4; + reg = STM32_ADC_OFR1_OFFSET + i * 4; regval = ADC_OFR_OFFSETY_EN; adc_putreg(priv, reg, regval); @@ -1893,28 +1893,28 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); + STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT | adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); #ifdef ADC_HAVE_DFSDM if (priv->hasdfsdm) @@ -1966,7 +1966,7 @@ static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); return OK; } @@ -2026,7 +2026,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new upper threshold greater than lower threshold */ @@ -2041,7 +2041,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_HT_MASK; regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2051,7 +2051,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new lower threshold less than upper threshold */ @@ -2066,7 +2066,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_LT_MASK; regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2074,7 +2074,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) } break; - case ANIOC_STM32L4_TRIGGER_REG: + case ANIOC_STM32_TRIGGER_REG: /* Start regular conversion if regular channels configured */ @@ -2086,7 +2086,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) break; #ifdef ADC_HAVE_INJECTED - case ANIOC_STM32L4_TRIGGER_INJ: + case ANIOC_STM32_TRIGGER_INJ: /* Start injected conversion if injected channels configured */ @@ -2107,7 +2107,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2133,7 +2133,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) if ((adcisr & ADC_INT_AWD1) != 0) { - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; awarn("WARNING: Analog Watchdog, " @@ -2158,7 +2158,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; /* Verify that the upper-half driver has bound its callback functions */ @@ -2198,7 +2198,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) { for (i = 0; i < priv->cjchannels; i++) { - value = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * i)) & + value = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * i)) & ADC_JDR_MASK; if (priv->cb != NULL) @@ -2225,14 +2225,14 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32L4_ADC1 - regval = getreg32(STM32L4_ADC1_ISR); +#ifdef CONFIG_STM32_ADC1 + regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2240,12 +2240,12 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC1_ISR); + putreg32(regval, STM32_ADC1_ISR); } #endif -#ifdef CONFIG_STM32L4_ADC2 - regval = getreg32(STM32L4_ADC2_ISR); +#ifdef CONFIG_STM32_ADC2 + regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2253,7 +2253,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC2_ISR); + putreg32(regval, STM32_ADC2_ISR); } #endif @@ -2273,13 +2273,13 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_ADC3_ISR); + regval = getreg32(STM32_ADC3_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2287,13 +2287,13 @@ static int adc3_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC3_ISR); + putreg32(regval, STM32_ADC3_ISR); } return OK; } #endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ #ifdef ADC_HAVE_DMA /**************************************************************************** @@ -2339,7 +2339,7 @@ static void adc_dma_cfg(struct stm32_dev_s *priv) /* Modify CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } /**************************************************************************** @@ -2360,9 +2360,9 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32l4_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); @@ -2388,7 +2388,7 @@ static void adc_dma_start(struct adc_dev_s *dev) * ****************************************************************************/ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -2418,13 +2418,13 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, /* Restart DMA for the next conversion series */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); } #endif #endif /* ADC_HAVE_DMA */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2437,7 +2437,7 @@ static void adc_llops_intack(struct stm32_adc_dev_s *dev, /* Clear pending interrupts */ - adc_putreg(priv, STM32L4_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); } /**************************************************************************** @@ -2451,7 +2451,7 @@ static void adc_llops_inten(struct stm32_adc_dev_s *dev, /* Enable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); } /**************************************************************************** @@ -2465,7 +2465,7 @@ static void adc_llops_intdis(struct stm32_adc_dev_s *dev, /* Disable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); } /**************************************************************************** @@ -2478,7 +2478,7 @@ static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) uint32_t regval; uint32_t pending; - regval = adc_getreg(priv, STM32L4_ADC_ISR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); pending = regval & ADC_ISR_ALLINTS; return pending; @@ -2492,7 +2492,7 @@ static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - return adc_getreg(priv, STM32L4_ADC_DR_OFFSET) & ADC_DR_MASK; + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_MASK; } /**************************************************************************** @@ -2545,7 +2545,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2578,7 +2578,7 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, dev->dma = stm32l4_dmachannel(dev->dmachan); stm32l4_dmasetup(dev->dma, - dev->base + STM32L4_ADC_DR_OFFSET, + dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2639,7 +2639,7 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, goto errout; } - regval = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * chan)) & + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * chan)) & ADC_JDR_MASK; errout: @@ -2671,7 +2671,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -2686,7 +2686,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * The logic allow initialize ADC regular and injected channels. * * The number of injected channels for given ADC is selected from Kconfig - * with CONFIG_STM32L4_ADCx_INJECTED_CHAN definitions + * with CONFIG_STM32_ADCx_INJECTED_CHAN definitions * * The number of regular channels is obtained from the equation: * @@ -2710,9 +2710,9 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * chanlist[channels] -> ADC_JSQR_ISQy * * where: - * y = CONFIG_STM32L4_ADCx_INJECTED_CHAN, and y > 0 + * y = CONFIG_STM32_ADCx_INJECTED_CHAN, and y > 0 * - * If CONFIG_STM32L4_ADCx_INJECTED_CHAN = 0, then all channels from + * If CONFIG_STM32_ADCx_INJECTED_CHAN = 0, then all channels from * chanlist are regular channels. * * Input Parameters: @@ -2739,11 +2739,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); - cjchannels = CONFIG_STM32L4_ADC1_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC1_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2758,11 +2758,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, break; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); - cjchannels = CONFIG_STM32L4_ADC2_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC2_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2777,11 +2777,11 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, break; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); - cjchannels = CONFIG_STM32L4_ADC3_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC3_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2805,10 +2805,10 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, priv = (struct stm32_dev_s *)dev->ad_priv; - DEBUGASSERT(crchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); - if (crchannels > CONFIG_STM32L4_ADC_MAX_SAMPLES) + DEBUGASSERT(crchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (crchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - crchannels = CONFIG_STM32L4_ADC_MAX_SAMPLES; + crchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = crchannels; @@ -2824,7 +2824,7 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ priv->cb = NULL; #endif @@ -2839,5 +2839,5 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index b2f2c16b7f997..a1c34e43980b0 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_ADC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_ADC_H /**************************************************************************** * Included Files @@ -40,100 +40,100 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is * intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on * STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_ADC -# undef CONFIG_STM32L4_TIM1_ADC1 -# undef CONFIG_STM32L4_TIM1_ADC2 -# undef CONFIG_STM32L4_TIM1_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_ADC -# undef CONFIG_STM32L4_TIM2_ADC1 -# undef CONFIG_STM32L4_TIM2_ADC2 -# undef CONFIG_STM32L4_TIM2_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_ADC -# undef CONFIG_STM32L4_TIM3_ADC1 -# undef CONFIG_STM32L4_TIM3_ADC2 -# undef CONFIG_STM32L4_TIM3_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_ADC -# undef CONFIG_STM32L4_TIM4_ADC1 -# undef CONFIG_STM32L4_TIM4_ADC2 -# undef CONFIG_STM32L4_TIM4_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_ADC -# undef CONFIG_STM32L4_TIM6_ADC1 -# undef CONFIG_STM32L4_TIM6_ADC2 -# undef CONFIG_STM32L4_TIM6_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_ADC -# undef CONFIG_STM32L4_TIM8_ADC1 -# undef CONFIG_STM32L4_TIM8_ADC2 -# undef CONFIG_STM32L4_TIM8_ADC3 -#endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_ADC -# undef CONFIG_STM32L4_TIM15_ADC1 -# undef CONFIG_STM32L4_TIM15_ADC2 -# undef CONFIG_STM32L4_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 +#endif +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 +#endif +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 +#endif +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 +#endif +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 +#endif +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 +#endif +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32L4_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32L4_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -141,24 +141,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32L4_ADC1_DMA) || defined(CONFIG_STM32L4_ADC2_DMA) || \ - defined(CONFIG_STM32L4_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -166,9 +166,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32L4_ADC1) && (CONFIG_STM32L4_ADC1_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC2) && (CONFIG_STM32L4_ADC2_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC3) && (CONFIG_STM32L4_ADC3_INJ_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJ_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -176,149 +176,149 @@ * information about the timer. */ -#if defined(CONFIG_STM32L4_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC1) +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC1) +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC1) +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC1) +# define ADC1_TIMER_BASE STM32_TIM4_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC1) +# define ADC1_TIMER_BASE STM32_TIM6_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC1) +# define ADC1_TIMER_BASE STM32_TIM8_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC1_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC1_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC1_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC1_JEXTTRIG == 0)) # error "ADC1 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC2) +# define ADC2_TIMER_BASE STM32_TIM1_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC2) +# define ADC2_TIMER_BASE STM32_TIM2_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC2) +# define ADC2_TIMER_BASE STM32_TIM3_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC2) +# define ADC2_TIMER_BASE STM32_TIM4_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC2) +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC2) +# define ADC2_TIMER_BASE STM32_TIM8_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC2_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC2_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC2_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC2_JEXTTRIG == 0)) # error "ADC2 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC3) +# define ADC3_TIMER_BASE STM32_TIM1_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC3) +# define ADC3_TIMER_BASE STM32_TIM2_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC3) +# define ADC3_TIMER_BASE STM32_TIM3_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC3) +# define ADC3_TIMER_BASE STM32_TIM4_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC3) +# define ADC3_TIMER_BASE STM32_TIM6_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC3) +# define ADC3_TIMER_BASE STM32_TIM8_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC3_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC3_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC3_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC3_JEXTTRIG == 0)) # error "ADC3 External trigger must be enabled" # endif #endif @@ -332,18 +332,18 @@ /* EXTSEL configuration *****************************************************/ -/* If external trigger is enabled, (CONFIG_STM32L4_ADC1_EXTTRIG > 0), +/* If external trigger is enabled, (CONFIG_STM32_ADC1_EXTTRIG > 0), * ADCx_EXTSEL_VALUE is set based on trigger polarity and event number. No * effort is made to check if the configuration is valid. */ -#ifdef CONFIG_STM32L4_ADC1_EXTTRIG -# if CONFIG_STM32L4_ADC1_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_EXTTRIG +# if CONFIG_STM32_ADC1_EXTTRIG > 0 # define ADC1_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC1_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC1_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */ +#endif /* CONFIG_STM32_ADC1_EXTTRIG */ #ifdef ADC1_EXTCFG_VALUE # define ADC1_HAVE_EXTCFG 1 @@ -351,13 +351,13 @@ # undef ADC1_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC2_EXTTRIG -# if CONFIG_STM32L4_ADC2_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_EXTTRIG +# if CONFIG_STM32_ADC2_EXTTRIG > 0 # define ADC2_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC2_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC2_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */ +#endif /* CONFIG_STM32_ADC2_EXTTRIG */ #ifdef ADC2_EXTCFG_VALUE # define ADC2_HAVE_EXTCFG 1 @@ -365,13 +365,13 @@ # undef ADC2_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC3_EXTTRIG -# if CONFIG_STM32L4_ADC3_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_EXTTRIG +# if CONFIG_STM32_ADC3_EXTTRIG > 0 # define ADC3_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC3_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC3_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */ +#endif /* CONFIG_STM32_ADC3_EXTTRIG */ #ifdef ADC3_EXTCFG_VALUE # define ADC3_HAVE_EXTCFG 1 @@ -386,37 +386,37 @@ /* JEXTSEL configuration ****************************************************/ -#ifdef CONFIG_STM32L4_ADC1_JEXTTRIG -# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_JEXTTRIG +# if CONFIG_STM32_ADC1_JEXTTRIG > 0 # define ADC1_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC1_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC1_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC1_JEXTTRIG */ #ifdef ADC1_JEXTCFG_VALUE # define ADC1_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC2_JEXTTRIG -# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_JEXTTRIG +# if CONFIG_STM32_ADC2_JEXTTRIG > 0 # define ADC2_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC2_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC2_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC2_JEXTTRIG */ #ifdef ADC2_JEXTCFG_VALUE # define ADC2_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC3_JEXTTRIG -# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_JEXTTRIG +# if CONFIG_STM32_ADC3_JEXTTRIG > 0 # define ADC3_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC3_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC3_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC3_JEXTTRIG */ #ifdef ADC3_JEXTCFG_VALUE # define ADC3_HAVE_JEXTCFG 1 @@ -483,19 +483,19 @@ /* IOCTL Commands *********************************************************** * - * Cmd: ANIOC_STM32L4_TRIGGER_REG Arg: - * Cmd: ANIOC_STM32L4_TRIGGER_INJ Arg: + * Cmd: ANIOC_STM32_TRIGGER_REG Arg: + * Cmd: ANIOC_STM32_TRIGGER_INJ Arg: * */ -#define ANIOC_STM32L4_TRIGGER_REG _ANIOC(AN_STM32L4_FIRST + 0) -#define ANIOC_STM32L4_TRIGGER_INJ _ANIOC(AN_STM32L4_FIRST + 1) +#define ANIOC_STM32_TRIGGER_REG _ANIOC(AN_STM32_FIRST + 0) +#define ANIOC_STM32_TRIGGER_INJ _ANIOC(AN_STM32_FIRST + 1) /**************************************************************************** * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -584,7 +584,7 @@ struct stm32_adc_ops_s void (*dump_regs)(struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -625,5 +625,5 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ \ No newline at end of file +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_ADC_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 1edbe3d122a38..cf4e6c70c16da 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L4_FSMC=y : Enables the FSMC - * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L4_FSMC -# undef CONFIG_STM32L4_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32L4[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L4_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L4_SRAM3_SIZE -# define SRAM3_START STM32L4_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -116,15 +116,15 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ - defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ - defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -133,10 +133,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32L4_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32L4_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -313,7 +313,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L4_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -332,7 +332,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L4_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -352,7 +352,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32L4_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 71e397a63254b..4c8316306d6b7 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -44,7 +44,7 @@ #include "stm32l4.h" #include "stm32l4_can.h" -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /**************************************************************************** * Pre-processor Definitions @@ -62,10 +62,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32L4_CAN_TSEG1 + CONFIG_STM32L4_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32L4_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /**************************************************************************** @@ -97,7 +97,7 @@ static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, uint32_t value); static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, const char *msg); static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, @@ -175,20 +175,20 @@ static const struct can_ops_s g_canops = .co_txempty = stm32l4can_txempty, }; -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32l4_can_s g_can1priv = { .port = 1, .canrx = { - STM32L4_IRQ_CAN1RX0, - STM32L4_IRQ_CAN1RX1, + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, }, - .cantx = STM32L4_IRQ_CAN1TX, + .cantx = STM32_IRQ_CAN1TX, .filter = 0, - .base = STM32L4_CAN1_BASE, - .fbase = STM32L4_CAN1_BASE, - .baud = CONFIG_STM32L4_CAN1_BAUD, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -217,7 +217,7 @@ static struct can_dev_s g_can1dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32l4can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -313,7 +313,7 @@ static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -365,7 +365,7 @@ static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, const char *msg) { @@ -381,18 +381,18 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, /* CAN control and status registers */ caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_MCR_OFFSET), - getreg32(priv->base + STM32L4_CAN_MSR_OFFSET), - getreg32(priv->base + STM32L4_CAN_TSR_OFFSET)); + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RF1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_IER_OFFSET), - getreg32(priv->base + STM32L4_CAN_ESR_OFFSET), - getreg32(priv->base + STM32L4_CAN_BTR_OFFSET)); + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); } #endif @@ -410,7 +410,7 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, const char *msg) { @@ -427,38 +427,38 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH2R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); } #endif @@ -476,7 +476,7 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, const char *msg) { @@ -494,17 +494,17 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_FMR_OFFSET), - getreg32(priv->base + STM32L4_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FA1R_OFFSET)); + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); for (i = 0; i < CAN_NFILTERS; i++) { caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 2))); + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } } #endif @@ -535,7 +535,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR1 register needed to reset this CAN device */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR1_CAN1RST; @@ -555,12 +555,12 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Reset the CAN */ - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); regval &= ~regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); } @@ -714,7 +714,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) /* Enable/disable the FIFO 0/1 message pending interrupt */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); if (enable) { regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; @@ -724,7 +724,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } /**************************************************************************** @@ -752,9 +752,9 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) if (!enable) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval &= ~CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } } @@ -806,7 +806,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t brp; DEBUGASSERT(bt != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1; bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> @@ -815,7 +815,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, CAN_BTR_TS2_SHIFT) + 1; brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1; - bt->bt_baud = STM32L4_PCLK1_FREQUENCY / + bt->bt_baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); ret = OK; } @@ -848,18 +848,18 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); /* Extract bit timing data. * tmp is in clocks per bit time. */ - tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud; + tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; /* This value is dynamic as requested by user */ @@ -904,12 +904,12 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); if (ret >= 0) { - priv->baud = STM32L4_PCLK1_FREQUENCY / + priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } @@ -934,7 +934,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); @@ -961,7 +961,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); if (bm->bm_loopback) { @@ -989,7 +989,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); } @@ -1078,7 +1078,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_NART; @@ -1088,7 +1088,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_NART; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_ABOM; @@ -1112,7 +1112,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_ABOM; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1185,7 +1185,7 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Select one empty transmit mailbox */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0) { txmb = 0; @@ -1206,10 +1206,10 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the ID, standard 11-bit or extended 29-bit. */ @@ -1233,15 +1233,15 @@ static int stm32l4can_send(struct can_dev_s *dev, regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); #endif #endif - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the DLC */ dlc = msg->cm_hdr.ch_dlc; - regval = stm32l4can_getreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32l4can_putreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); /* Set up the data fields */ @@ -1272,7 +1272,7 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDLR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); regval = 0; if (dlc > 4) @@ -1299,19 +1299,19 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDHR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval |= CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); /* Request transmission */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); stm32l4can_dumpmbregs(priv, "After send"); return OK; @@ -1338,7 +1338,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev) /* Return true if any mailbox is available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) != 0; @@ -1369,7 +1369,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) /* Return true if all mailboxes are available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES; @@ -1406,7 +1406,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Verify that a message is pending in the FIFO */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; if (npending < 1) { @@ -1425,7 +1425,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the CAN identifier. */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); #ifdef CONFIG_CAN_EXTID if ((regval & CAN_RIR_IDE) != 0) @@ -1462,18 +1462,18 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the DLC */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; /* Save the message data */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; @@ -1488,9 +1488,9 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) #ifndef CONFIG_CAN_EXTID errout: #endif - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); regval |= CAN_RFR_RFOM; - stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval); + stm32l4can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); return ret; } @@ -1560,7 +1560,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) /* Get the transmit status */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); /* Check for RQCP0: Request completed mailbox 0 */ @@ -1570,7 +1570,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST0 and TERR0) for Mailbox 0. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); /* Check for errors */ @@ -1590,7 +1590,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST1 and TERR1) for Mailbox 1. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); /* Check for errors */ @@ -1610,7 +1610,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST2 and TERR2) for Mailbox 2. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); /* Check for errors */ @@ -1690,7 +1690,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) uint32_t ts2; caninfo("CAN%d PCLK1: %d baud: %d\n", - priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud); + priv->port, STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1708,7 +1708,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 */ - tmp = STM32L4_PCLK1_FREQUENCY / priv->baud; + tmp = STM32_PCLK1_FREQUENCY / priv->baud; if (tmp < CAN_BIT_QUANTA) { /* At the smallest brp value (1), there are already too few bit times @@ -1729,15 +1729,15 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32L4_CAN_TSEG1, - * ts2 is CONFIG_STM32L4_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32L4_CAN_TSEG1; - ts2 = CONFIG_STM32L4_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -1762,7 +1762,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) tmp |= CAN_BTR_LBKM; #endif - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); return OK; } @@ -1791,15 +1791,15 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) /* Enter initialization mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval |= CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until initialization mode is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) != 0) { /* We are in initialization mode */ @@ -1840,15 +1840,15 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) /* Exit Initialization mode, enter Normal mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until the initialization mode exit is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) == 0) { /* We are out of initialization mode */ @@ -1893,9 +1893,9 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) /* Exit from sleep mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_SLEEP; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); ret = stm32l4can_enterinitmode(priv); if (ret != 0) @@ -1913,10 +1913,10 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * - Transmit FIFO priority */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Configure bit timing. */ @@ -1975,52 +1975,52 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) /* Enter filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval |= CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); /* Disable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Select the 32-bit scale for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FS1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FS1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); /* There are 14 or 28 filter banks (depending) on the device. * Each filter bank is composed of two 32-bit registers, CAN_FiR: */ - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); /* Set Id/Mask mode for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FM1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FM1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FM1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); /* Assign FIFO 0 for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FFA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FFA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); /* Enable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Exit filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= ~CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); return OK; } @@ -2148,7 +2148,7 @@ struct can_dev_s *stm32l4can_initialize(int port) * by stm32l4_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2172,4 +2172,4 @@ struct can_dev_s *stm32l4can_initialize(int port) return dev; } -#endif /* CONFIG_CAN && (CONFIG_STM32L4_CAN1 || CONFIG_STM32L4_CAN2) */ +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 8328d9a13fb9c..eae9f677c9f0a 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_CAN_H +#define __ARCH_ARM_SRC_STM32L4_STM32_CAN_H /**************************************************************************** * Included Files @@ -42,39 +42,39 @@ /* Up to 1 CAN interfaces are supported */ -#if STM32L4_NCAN < 1 -# undef CONFIG_STM32L4_CAN1 +#if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 #endif -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /* CAN BAUD */ -#if defined(CONFIG_STM32L4_CAN1) && !defined(CONFIG_STM32L4_CAN1_BAUD) -# error "CONFIG_STM32L4_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32L4_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32L4_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32L4_CAN_TSEG1 -# define CONFIG_STM32L4_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32L4_CAN_TSEG1 < 1 || CONFIG_STM32L4_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32L4_CAN_TSEG1 is out of range" +#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32L4_CAN_TSEG2 -# define CONFIG_STM32L4_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32L4_CAN_TSEG2 < 1 || CONFIG_STM32L4_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32L4_CAN_TSEG2 is out of range" +#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif /**************************************************************************** @@ -123,5 +123,5 @@ struct can_dev_s *stm32l4can_initialize(int port); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_CAN && CONFIG_STM32L4_CAN1 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H */ +#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_CAN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 6bc365394b3f1..5ec7986aa9c54 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -53,12 +53,12 @@ #include -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#ifdef CONFIG_STM32L4_COMP +#ifdef CONFIG_STM32_COMP /**************************************************************************** * Private Function Prototypes @@ -104,12 +104,12 @@ static struct stm32l4_comp_config_s g_comp1priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_2, - .inm = STM32L4_COMP_INM_VREF, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_2, + .inm = STM32_COMP_INM_VREF, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP1_CSR, + .csr = STM32_COMP1_CSR, }; static struct comp_dev_s g_comp1dev = @@ -126,12 +126,12 @@ static struct stm32l4_comp_config_s g_comp2priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_1, - .inm = STM32L4_COMP_INM_DAC_1, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_1, + .inm = STM32_COMP_INM_DAC_1, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP2_CSR, + .csr = STM32_COMP2_CSR, }; static struct comp_dev_s g_comp2dev = @@ -324,7 +324,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); - ainfo("isr: %d\n", (cfg->csr == STM32L4_COMP1_CSR ? 0 : 1)); + ainfo("isr: %d\n", (cfg->csr == STM32_COMP1_CSR ? 0 : 1)); cfg->interrupt.cb->au_notify(dev, comp_read(dev)); @@ -356,28 +356,28 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) int cmp; cfg = dev->ad_priv; - cmp = cfg->csr == STM32L4_COMP1_CSR ? STM32L4_COMP1 : STM32L4_COMP2; + cmp = cfg->csr == STM32_COMP1_CSR ? STM32_COMP1 : STM32_COMP2; /* Input plus */ mask |= COMP_CSR_INPSEL_MASK; switch (cfg->inp) { - case STM32L4_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : + case STM32_COMP_INP_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; - case STM32L4_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : + case STM32_COMP_INP_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; -#if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : +#if defined(CONFIG_STM32_STM32L4X3) + case STM32_COMP_INP_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -392,49 +392,49 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_INMSEL_MASK; switch (cfg->inm) { - case STM32L4_COMP_INM_1_4_VREF: + case STM32_COMP_INM_1_4_VREF: regval |= COMP_CSR_INMSEL_25PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_1_2_VREF: + case STM32_COMP_INM_1_2_VREF: regval |= COMP_CSR_INMSEL_50PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_3_4_VREF: + case STM32_COMP_INM_3_4_VREF: regval |= COMP_CSR_INMSEL_75PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_VREF: + case STM32_COMP_INM_VREF: regval |= COMP_CSR_INMSEL_VREF; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= COMP_CSR_SCALEN; break; - case STM32L4_COMP_INM_DAC_1: + case STM32_COMP_INM_DAC_1: regval |= COMP_CSR_INMSEL_DAC1; break; - case STM32L4_COMP_INM_DAC_2: + case STM32_COMP_INM_DAC_2: regval |= COMP_CSR_INMSEL_DAC2; break; - case STM32L4_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : + case STM32_COMP_INM_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; - case STM32L4_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : + case STM32_COMP_INM_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) regval |= COMP_CSR_INMSEL_PIN2; #else regval |= COMP_CSR_INMSEL_INMESEL; @@ -443,25 +443,25 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) #endif break; -#if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : +#if defined(CONFIG_STM32_STM32L4X3) + case STM32_COMP_INM_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN3; break; - case STM32L4_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : + case STM32_COMP_INM_PIN_4: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN4; break; - case STM32L4_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : + case STM32_COMP_INM_PIN_5: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -478,19 +478,19 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_HYST_MASK; switch (cfg->hyst) { - case STM32L4_COMP_HYST_NONE: + case STM32_COMP_HYST_NONE: regval |= COMP_CSR_HYST_NONE; break; - case STM32L4_COMP_HYST_LOW: + case STM32_COMP_HYST_LOW: regval |= COMP_CSR_HYST_LOW; break; - case STM32L4_COMP_HYST_MEDIUM: + case STM32_COMP_HYST_MEDIUM: regval |= COMP_CSR_HYST_MEDIUM; break; - case STM32L4_COMP_HYST_HIGH: + case STM32_COMP_HYST_HIGH: regval |= COMP_CSR_HYST_HIGH; break; @@ -503,15 +503,15 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_PWRMODE_MASK; switch (cfg->speed) { - case STM32L4_COMP_SPEED_HIGH: + case STM32_COMP_SPEED_HIGH: regval |= COMP_CSR_PWRMODE_HIGH; break; - case STM32L4_COMP_SPEED_MEDIUM: + case STM32_COMP_SPEED_MEDIUM: regval |= COMP_CSR_PWRMODE_MEDIUM; break; - case STM32L4_COMP_SPEED_LOW: + case STM32_COMP_SPEED_LOW: regval |= COMP_CSR_PWRMODE_LOW; break; @@ -609,4 +609,4 @@ struct comp_dev_s * return dev; } -#endif /* CONFIG_STM32L4_COMP */ +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index d862d14a9eef6..ac63ae218f3a2 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -33,8 +33,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_COMP_H +#define __ARCH_ARM_SRC_STM32L4_STM32_COMP_H /**************************************************************************** * Included Files @@ -50,41 +50,41 @@ * Public Types ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /* Comparators */ enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ - STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ - STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ - STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ - STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ + STM32_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ + STM32_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ }; #else @@ -93,31 +93,31 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ }; #endif @@ -125,19 +125,19 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_hyst_e { - STM32L4_COMP_HYST_NONE, - STM32L4_COMP_HYST_LOW, - STM32L4_COMP_HYST_MEDIUM, - STM32L4_COMP_HYST_HIGH + STM32_COMP_HYST_NONE, + STM32_COMP_HYST_LOW, + STM32_COMP_HYST_MEDIUM, + STM32_COMP_HYST_HIGH }; /* Power/Speed Modes */ enum stm32l4_comp_speed_e { - STM32L4_COMP_SPEED_HIGH, - STM32L4_COMP_SPEED_MEDIUM, - STM32L4_COMP_SPEED_LOW + STM32_COMP_SPEED_HIGH, + STM32_COMP_SPEED_MEDIUM, + STM32_COMP_SPEED_LOW }; /* Comparator configuration *************************************************/ @@ -201,4 +201,4 @@ comp_dev_s *stm32l4_compinitialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_COMP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_COMP_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index a2c59beca1726..f3f139f6101cd 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -55,25 +55,25 @@ /* Up to 1 DAC interface for up to 2 channels are supported */ -#if STM32L4_NDAC > 2 +#if STM32_NDAC > 2 # warning "Extra DAC channels. Only DAC1 and DAC2 are supported" #endif -#if STM32L4_NDAC < 2 -# undef CONFIG_STM32L4_DAC2 -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY +#if STM32_NDAC < 2 +# undef CONFIG_STM32_DAC2 +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY #endif -#if STM32L4_NDAC < 1 -# undef CONFIG_STM32L4_DAC1 -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY +#if STM32_NDAC < 1 +# undef CONFIG_STM32_DAC1 +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY #endif -#if defined(CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DMA configuration. */ @@ -83,63 +83,63 @@ * supported by the driver. */ -#ifdef CONFIG_STM32L4_DAC1_DMA -# if !defined(CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC1_DMA +# if !defined(CONFIG_STM32_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC1_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC1_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC1_TIMER" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC1_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC1_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC1_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER +# if !defined(CONFIG_STM32_DAC1_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC1_TIMER" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC1_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC1_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC1_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER # endif #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if !defined(CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC2_DMA +# if !defined(CONFIG_STM32_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC2_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC2_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC2_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC2_TIMER" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC2_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC2_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC2_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER +# if !defined(CONFIG_STM32_DAC2_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC2_TIMER" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC2_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC2_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC2_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER # endif #endif /* Select DMA channels, favor DMA1 if configured. */ #undef HAVE_DMA -#ifdef CONFIG_STM32L4_DAC1_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC1_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMAMAP_DAC1_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMAMAP_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMACHAN_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMACHAN_DAC1_2 # else # error "No DMA channel for DAC1" # endif # define HAVE_DMA #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC2_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMAMAP_DAC2_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMAMAP_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMACHAN_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMACHAN_DAC2_2 # else # error "No DMA channel for DAC2" @@ -171,113 +171,113 @@ #undef NEED_TIM2 #undef NEED_TIM4 -#ifdef CONFIG_STM32L4_DAC1_DMA -# if CONFIG_STM32L4_DAC1_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC1" +#ifdef CONFIG_STM32_DAC1_DMA +# if CONFIG_STM32_DAC1_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC1" # endif # define NEED_TIM6 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1_TIMER_BASE STM32L4_TIM6_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM6_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC1" # endif # define NEED_TIM8 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1_TIMER_BASE STM32L4_TIM8_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM8_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC1" # endif # define NEED_TIM7 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1_TIMER_BASE STM32L4_TIM7_BASE -# elif CONFIG_STM32L4_DAC1_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM7_BASE +# elif CONFIG_STM32_DAC1_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC1" # endif # define NEED_TIM5 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1_TIMER_BASE STM32L4_TIM5_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM5_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC1" # endif # define NEED_TIM2 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1_TIMER_BASE STM32L4_TIM2_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC1" +# define DAC1_TIMER_BASE STM32_TIM2_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC1_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC1" # endif # define NEED_TIM4 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1_TIMER_BASE STM32L4_TIM4_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM4_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC1_TIMER" +# error "Unsupported CONFIG_STM32_DAC1_TIMER" # endif #else # define DAC1_TSEL_VALUE DAC_CR_TSEL_SW #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if CONFIG_STM32L4_DAC2_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC2" +#ifdef CONFIG_STM32_DAC2_DMA +# if CONFIG_STM32_DAC2_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC2_TIMER_BASE STM32L4_TIM6_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM6_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC2_TIMER_BASE STM32L4_TIM8_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM8_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC2_TIMER_BASE STM32L4_TIM7_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM7_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC2_TIMER_BASE STM32L4_TIM5_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM5_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC2_TIMER_BASE STM32L4_TIM2_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC2" +# define DAC2_TIMER_BASE STM32_TIM2_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY +# elif CONFIG_STM32_DAC2_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC2_TIMER_BASE STM32L4_TIM4_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM4_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC2_TIMER" +# error "Unsupported CONFIG_STM32_DAC2_TIMER" # endif #else # define DAC2_TSEL_VALUE DAC_CR_TSEL_SW #endif /* Calculate timer divider values based upon DACn_TIMER_PCLK_FREQUENCY and - * CONFIG_STM32L4_DACn_TIMER_FREQUENCY. + * CONFIG_STM32_DACn_TIMER_FREQUENCY. */ #warning "Missing Logic" @@ -307,7 +307,7 @@ struct stm32_dac_s struct stm32_chan_s { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS const struct stm32_dac_ops_s *llops; /* Low-level DAC ops */ #endif uint8_t inuse : 1; /* True, the driver is in use and not available */ @@ -365,7 +365,7 @@ static int dac_timinit(struct stm32_chan_s *chan); static int dac_chaninit(struct stm32_chan_s *chan); static void dac_blockinit(void); -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled); static void dac_llops_writedro(struct stm32_dac_dev_s *dev, uint16_t data); #ifdef HAVE_DMA @@ -373,7 +373,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev); static void dac_llops_stopdma(struct stm32_dac_dev_s *dev); #endif static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev); -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Private Data @@ -391,7 +391,7 @@ static const struct dac_ops_s g_dacops = /* Publicly visible DAC lower-half operations */ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static const struct stm32_dac_ops_s g_dac_llops = { .enable = dac_llops_enable, @@ -402,37 +402,37 @@ static const struct stm32_dac_ops_s g_dac_llops = #endif .dump_regs = dac_llops_dumpregs }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 /* Channel 1 */ -#ifdef CONFIG_STM32L4_DAC1_DMA -uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC1_DMA +uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32_DAC1_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac1priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 0, -#ifdef CONFIG_STM32L4_DAC1_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC1_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC1_OUT, #endif - .dro = STM32L4_DAC_DHR12R1, - .cr = STM32L4_DAC_CR, -#ifdef CONFIG_STM32L4_DAC1_DMA + .dro = STM32_DAC_DHR12R1, + .cr = STM32_DAC_CR, +#ifdef CONFIG_STM32_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE, + .buffer_len = CONFIG_STM32_DAC1_DMA_BUFFER_SIZE, .dmabuffer = stm32l4_dac1_dmabuffer, - .timer = CONFIG_STM32L4_DAC1_TIMER, + .timer = CONFIG_STM32_DAC1_TIMER, .tsel = DAC1_TSEL_VALUE, .tbase = DAC1_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC1_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC1_TIMER_FREQUENCY, #endif }; @@ -442,37 +442,37 @@ static struct dac_dev_s g_dac1dev = .ad_priv = &g_dac1priv, }; -#endif /* CONFIG_STM32L4_DAC1 */ +#endif /* CONFIG_STM32_DAC1 */ -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 /* Channel 2 */ -#ifdef CONFIG_STM32L4_DAC2_DMA -uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC2_DMA +uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32_DAC2_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac2priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 1, -#ifdef CONFIG_STM32L4_DAC2_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC2_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC2_OUT, #endif - .dro = STM32L4_DAC_DHR12R2, - .cr = STM32L4_DAC_CR, -#ifdef CONFIG_STM32L4_DAC2_DMA + .dro = STM32_DAC_DHR12R2, + .cr = STM32_DAC_CR, +#ifdef CONFIG_STM32_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE, + .buffer_len = CONFIG_STM32_DAC2_DMA_BUFFER_SIZE, .dmabuffer = stm32l4_dac2_dmabuffer, - .timer = CONFIG_STM32L4_DAC2_TIMER, + .timer = CONFIG_STM32_DAC2_TIMER, .tsel = DAC2_TSEL_VALUE, .tbase = DAC2_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC2_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC2_TIMER_FREQUENCY, #endif }; @@ -482,7 +482,7 @@ static struct dac_dev_s g_dac2dev = .ad_priv = &g_dac2priv, }; -#endif /* CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC2 */ static struct stm32_dac_s g_dacblock; @@ -507,7 +507,7 @@ static struct stm32_dac_s g_dacblock; static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) { - return getreg32(STM32L4_DAC_BASE + offset); + return getreg32(STM32_DAC_BASE + offset); } /**************************************************************************** @@ -532,7 +532,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC[1]_CR control register. If + /* DAC channels 1 and 2 share the STM32_DAC[1]_CR control register. If * future chips have DAC channel 3 (and perhaps channel 4) they likely have * their own register like in STM32. In either case, bit 0 of the interface * number provides the correct shift. @@ -567,7 +567,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC_MCR control register. + /* DAC channels 1 and 2 share the STM32_DAC_MCR control register. * Bit 0 of the interface number provides the correct shift. * * Bit 0 = 0: Shift = 0 @@ -575,7 +575,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, */ shift = (chan->intf & 1) << 4; - modifyreg32(STM32L4_DAC_MCR, clearbits << shift, setbits << shift); + modifyreg32(STM32_DAC_MCR, clearbits << shift, setbits << shift); } /**************************************************************************** @@ -588,10 +588,10 @@ static void dac_dumpregs(struct stm32_chan_s *priv) ainfo("CR: 0x%08" PRIx32 " SWTRGR: 0x%08" PRIx32 "SR: 0x%08" PRIx32 " MCR: 0x%08" PRIx32 "\n", - dac_getreg(priv, STM32L4_DAC_CR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SWTRIGR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SR_OFFSET), - dac_getreg(priv, STM32L4_DAC_MCR_OFFSET)); + dac_getreg(priv, STM32_DAC_CR_OFFSET), + dac_getreg(priv, STM32_DAC_SWTRIGR_OFFSET), + dac_getreg(priv, STM32_DAC_SR_OFFSET), + dac_getreg(priv, STM32_DAC_MCR_OFFSET)); } /**************************************************************************** @@ -755,12 +755,12 @@ static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, switch (chan->intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: dev = &g_dac2dev; break; @@ -867,7 +867,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Reset counters (generate an update) */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); #endif return OK; } @@ -923,7 +923,7 @@ static int dac_timinit(struct stm32_chan_s *chan) * default) will be enabled */ - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; switch (chan->timer) { @@ -965,7 +965,7 @@ static int dac_timinit(struct stm32_chan_s *chan) #endif #ifdef NEED_TIM8 case 8: - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; pclk = BOARD_TIM8_FREQUENCY; break; @@ -1036,26 +1036,26 @@ static int dac_timinit(struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif @@ -1200,14 +1200,14 @@ static void dac_blockinit(void) /* Put the entire DAC block in reset state */ flags = enter_critical_section(); - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); /* Take the DAC out of reset state */ regval &= ~RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); /* Mark the DAC block as initialized */ @@ -1215,7 +1215,7 @@ static void dac_blockinit(void) g_dacblock.init = 1; } -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /**************************************************************************** * Name: dac_llops_enable @@ -1286,7 +1286,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) /* Reset counters (generate an update) */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); } /**************************************************************************** @@ -1319,7 +1319,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) dac_dumpregs(priv); } -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Functions @@ -1351,13 +1351,13 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: ainfo("DAC1-1 Selected\n"); dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: ainfo("DAC1-2 Selected\n"); dev = &g_dac2dev; @@ -1385,5 +1385,5 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf) return dev; } -#endif /* CONFIG_STM32L4_DAC1 || CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC1 || CONFIG_STM32_DAC2 */ #endif /* CONFIG_DAC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h index 6bf30f75ab4e1..5069f40a91b9b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/stm32l4_dac.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DAC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DAC_H /**************************************************************************** * Included Files @@ -41,43 +41,43 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic DAC outputs. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DAC must also be defined to indicate that timer "n" + * to control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_DAC +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DAC #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_DAC +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_DAC #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_DAC +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DAC #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_DAC +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DAC #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_DAC +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_DAC #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_DAC +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DAC #endif -#ifndef CONFIG_STM32L4_TIM7 -# undef CONFIG_STM32L4_TIM7_DAC +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DAC #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_DAC +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DAC #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_DAC +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_DAC #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_DAC +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_DAC #endif -#ifndef CONFIG_STM32L4_TIM17 -# undef CONFIG_STM32L4_TIM17_DAC +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_DAC #endif /* Low-level ops helpers ****************************************************/ @@ -97,7 +97,7 @@ * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" DAC driver structure. @@ -137,16 +137,16 @@ struct stm32_dac_ops_s void (*dump_regs)(struct stm32_dac_dev_s *dev); }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1_DMA +#ifdef CONFIG_STM32_DAC1_DMA extern uint16_t stm32l4_dac1_dmabuffer[]; #endif -#ifdef CONFIG_STM32L4_DAC2_DMA +#ifdef CONFIG_STM32_DAC2_DMA extern uint16_t stm32l4_dac2_dmabuffer[]; #endif @@ -186,4 +186,4 @@ struct dac_dev_s *stm32l4_dacinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DAC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DAC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h index 5e460f90603ce..d4bc258925698 100644 --- a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h +++ b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -31,16 +31,16 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dbgmcu.h" #else # error "Unsupported STM32L4 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 0c4d0c9534494..026cf0ae95fab 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -53,7 +53,7 @@ /* The peripheral must be enabled */ -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /**************************************************************************** * Pre-processor Definitions @@ -61,35 +61,35 @@ /* Sanity checking **********************************************************/ -#if !defined(CONFIG_STM32L4_DFSDM1_FLT0) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT1) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT2) && !defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if !defined(CONFIG_STM32_DFSDM1_FLT0) && \ + !defined(CONFIG_STM32_DFSDM1_FLT1) && \ + !defined(CONFIG_STM32_DFSDM1_FLT2) && !defined(CONFIG_STM32_DFSDM1_FLT3) # error "At least one DFSDM filter must be defined" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) -# if defined(CONFIG_STM32L4_DFSDM1_FLT2) || defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_STM32L4X3) +# if defined(CONFIG_STM32_DFSDM1_FLT2) || defined(CONFIG_STM32_DFSDM1_FLT3) # error "Non-existent DFSDM filter defined" # endif #endif /* Abbreviated register access **********************************************/ -#define CHCFGR1_OFFSET(priv) STM32L4_DFSDM_CHCFGR1_OFFSET((priv)->current) -#define CHCFGR2_OFFSET(priv) STM32L4_DFSDM_CHCFGR2_OFFSET((priv)->current) - -#define FLTCR1_OFFSET(priv) STM32L4_DFSDM_FLTCR1_OFFSET((priv)->intf) -#define FLTCR2_OFFSET(priv) STM32L4_DFSDM_FLTCR2_OFFSET((priv)->intf) -#define FLTISR_OFFSET(priv) STM32L4_DFSDM_FLTISR_OFFSET((priv)->intf) -#define FLTICR_OFFSET(priv) STM32L4_DFSDM_FLTICR_OFFSET((priv)->intf) -#define FLTFCR_OFFSET(priv) STM32L4_DFSDM_FLTFCR_OFFSET((priv)->intf) -#define FLTRDATAR_OFFSET(priv) STM32L4_DFSDM_FLTRDATAR_OFFSET((priv)->intf) -#define FLTAWHTR_OFFSET(priv) STM32L4_DFSDM_FLTAWHTR_OFFSET((priv)->intf) -#define FLTAWLTR_OFFSET(priv) STM32L4_DFSDM_FLTAWLTR_OFFSET((priv)->intf) -#define FLTAWSR_OFFSET(priv) STM32L4_DFSDM_FLTAWSR_OFFSET((priv)->intf) -#define FLTAWCFR_OFFSET(priv) STM32L4_DFSDM_FLTAWCFR_OFFSET((priv)->intf) -#define FLTEXMAX_OFFSET(priv) STM32L4_DFSDM_FLTEXMAX_OFFSET((priv)->intf) -#define FLTEXMIN_OFFSET(priv) STM32L4_DFSDM_FLTEXMIN_OFFSET((priv)->intf) +#define CHCFGR1_OFFSET(priv) STM32_DFSDM_CHCFGR1_OFFSET((priv)->current) +#define CHCFGR2_OFFSET(priv) STM32_DFSDM_CHCFGR2_OFFSET((priv)->current) + +#define FLTCR1_OFFSET(priv) STM32_DFSDM_FLTCR1_OFFSET((priv)->intf) +#define FLTCR2_OFFSET(priv) STM32_DFSDM_FLTCR2_OFFSET((priv)->intf) +#define FLTISR_OFFSET(priv) STM32_DFSDM_FLTISR_OFFSET((priv)->intf) +#define FLTICR_OFFSET(priv) STM32_DFSDM_FLTICR_OFFSET((priv)->intf) +#define FLTFCR_OFFSET(priv) STM32_DFSDM_FLTFCR_OFFSET((priv)->intf) +#define FLTRDATAR_OFFSET(priv) STM32_DFSDM_FLTRDATAR_OFFSET((priv)->intf) +#define FLTAWHTR_OFFSET(priv) STM32_DFSDM_FLTAWHTR_OFFSET((priv)->intf) +#define FLTAWLTR_OFFSET(priv) STM32_DFSDM_FLTAWLTR_OFFSET((priv)->intf) +#define FLTAWSR_OFFSET(priv) STM32_DFSDM_FLTAWSR_OFFSET((priv)->intf) +#define FLTAWCFR_OFFSET(priv) STM32_DFSDM_FLTAWCFR_OFFSET((priv)->intf) +#define FLTEXMAX_OFFSET(priv) STM32_DFSDM_FLTEXMAX_OFFSET((priv)->intf) +#define FLTEXMIN_OFFSET(priv) STM32_DFSDM_FLTEXMIN_OFFSET((priv)->intf) /* DFSDM Filter interrupts **************************************************/ @@ -122,7 +122,7 @@ * without, although there is a risk of overrun. */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define DFSDM_MAX_CHANNELS 4 # define DFSDM_MAX_FILTERS 2 #else @@ -131,8 +131,8 @@ #endif #ifdef DFSDM_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error "STM32L4 DFSDM DMA support requires CONFIG_STM32L4_DMA1" +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error "STM32L4 DFSDM DMA support requires CONFIG_STM32_DMA1" # endif #endif @@ -232,16 +232,16 @@ static void dfsdm_startconv(struct stm32_dev_s *priv, bool enable); /* Interrupt Handler */ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg); #endif @@ -274,19 +274,19 @@ static const struct adc_ops_s g_adcops = /* DFSDM FLT0 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static struct stm32_dev_s g_dfsdmpriv0 = { - .irq = STM32L4_IRQ_DFSDM0, + .irq = STM32_IRQ_DFSDM0, .isr = dfsdm_flt0_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM0, @@ -303,19 +303,19 @@ static struct adc_dev_s g_dfsdmdev0 = /* DFSDM FLT1 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static struct stm32_dev_s g_dfsdmpriv1 = { - .irq = STM32L4_IRQ_DFSDM1, + .irq = STM32_IRQ_DFSDM1, .isr = dfsdm_flt1_interrupt, .intf = 1, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM1, @@ -332,19 +332,19 @@ static struct adc_dev_s g_dfsdmdev1 = /* DFSDM FLT2 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static struct stm32_dev_s g_dfsdmpriv2 = { - .irq = STM32L4_IRQ_DFSDM2, + .irq = STM32_IRQ_DFSDM2, .isr = dfsdm_flt2_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM2, @@ -361,19 +361,19 @@ static struct adc_dev_s g_dfsdmdev2 = /* DFSDM FLT3 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static struct stm32_dev_s g_dfsdmpriv3 = { - .irq = STM32L4_IRQ_DFSDM3, + .irq = STM32_IRQ_DFSDM3, .isr = dfsdm_flt3_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER - .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, + .trigger = CONFIG_STM32_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, .extsel = DFSDM_JEXTSEL_VALUE, .pclck = DFSDM_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY, #endif #ifdef DFSDM_HAVE_DMA .dmachan = DMACHAN_DFSDM3, @@ -548,38 +548,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -607,13 +607,13 @@ static void dfsdm_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -747,24 +747,24 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ @@ -788,7 +788,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -808,7 +808,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -828,7 +828,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -848,7 +848,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -866,7 +866,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -878,15 +878,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - ccer = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~ccenable; - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - cr2 = tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET); + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); /* Reset the Output Compare Mode Bits and set the select output compare * mode @@ -912,7 +912,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. @@ -937,15 +937,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Save the modified register values */ - tim_putreg(priv, STM32L4_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32L4_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, egr); + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Enable the timer counter */ @@ -1050,7 +1050,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the APB2 reset register */ - regval = getreg32(STM32L4_RCC_APB2RSTR); + regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { regval |= RCC_APB2RSTR_DFSDMRST; @@ -1060,7 +1060,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_APB2RSTR_DFSDMRST; } - putreg32(regval, STM32L4_RCC_APB2RSTR); + putreg32(regval, STM32_RCC_APB2RSTR); leave_critical_section(flags); } @@ -1079,12 +1079,12 @@ static void dfsdm_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = dfsdm_getreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET); + regval = dfsdm_getreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET); /* Enable DFSMDM */ regval |= DFSDM_CH0CFGR1_DFSDMEN; - dfsdm_putreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET, regval); + dfsdm_putreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET, regval); } /**************************************************************************** @@ -1582,13 +1582,13 @@ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t isr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(0)); + regval = getreg32(STM32_DFSDM_FLTISR(0)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1607,13 +1607,13 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(1)); + regval = getreg32(STM32_DFSDM_FLTISR(1)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1632,13 +1632,13 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(2)); + regval = getreg32(STM32_DFSDM_FLTISR(2)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1657,13 +1657,13 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(3)); + regval = getreg32(STM32_DFSDM_FLTISR(3)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1761,25 +1761,25 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, switch (intf) { -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) case 0: ainfo("DFSDM FLT0 selected\n"); dev = &g_dfsdmdev0; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) case 1: ainfo("DFSDM FLT1 selected\n"); dev = &g_dfsdmdev1; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) case 2: ainfo("DFSDM FLT2 selected\n"); dev = &g_dfsdmdev2; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) case 3: ainfo("DFSDM FLT3 selected\n"); dev = &g_dfsdmdev3; @@ -1818,5 +1818,5 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, return dev; } -#endif /* CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_STM32_DFSDM */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 6039443f5ab53..cf3236ff97202 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H /**************************************************************************** * Included Files @@ -39,49 +39,49 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DFSDM must also be defined to indicate that timer "n" + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DFSDM must also be defined to indicate that timer "n" * is intended to be used for that purpose. Timers 1,3,6 and 16 may be used * on STM32L4X3, while STM32L4X6 adds support for timers 4,7 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_DFSDM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_DFSDM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_DFSDM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_DFSDM +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM7 -# undef CONFIG_STM32L4_TIM7_DFSDM +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_DFSDM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_DFSDM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_DFSDM #endif -#if defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_STM32_DFSDM) /* DMA support */ #undef DFSDM_HAVE_DMA -#if defined(CONFIG_STM32L4_DFSDM1_DMA) +#if defined(CONFIG_STM32_DFSDM1_DMA) # define DFSDM_HAVE_DMA 1 #endif /* ADC output to DFSDM support */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif @@ -89,44 +89,44 @@ * information about the timer. */ -#if defined(CONFIG_STM32L4_TIM1_DFSDM) +#if defined(CONFIG_STM32_TIM1_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32L4_TIM3_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM1_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +#elif defined(CONFIG_STM32_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32L4_TIM4_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM3_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +#elif defined(CONFIG_STM32_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32L4_TIM6_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM4_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +#elif defined(CONFIG_STM32_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32L4_TIM7_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM6_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +#elif defined(CONFIG_STM32_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#elif defined(CONFIG_STM32L4_TIM8_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM7_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +#elif defined(CONFIG_STM32_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#elif defined(CONFIG_STM32L4_TIM16_DFSDM) +# define DFSDM_TIMER_BASE STM32_TIM8_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +#elif defined(CONFIG_STM32_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM16_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN #else # undef DFSDM_HAVE_TIMER #endif #ifdef DFSDM_HAVE_TIMER -# ifndef CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_DFSDM_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY +# error "CONFIG_STM32_DFSDM_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32L4_DFSDM_TIMTRIG -# error "CONFIG_STM32L4_DFSDM_TIMTRIG not defined" +# ifndef CONFIG_STM32_DFSDM_TIMTRIG +# error "CONFIG_STM32_DFSDM_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -184,107 +184,107 @@ #define DFSDM_JEXTSEL_T16CC4 DFSDM_FLTCR1_JEXTSEL_T16CC4 #define DFSDM_JEXTSEL_T16TRGO DFSDM_FLTCR1_JEXTSEL_T16TRGO -#if defined(CONFIG_STM32L4_TIM1_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 5 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T1TRGO2 # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM3_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T3TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM4_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T4TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM6_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T6TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM7_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM7_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T7TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM8_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 5 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 5 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T8TRGO2 # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32L4_TIM16_DFSDM) -# if CONFIG_STM32L4_DFSDM_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM16_DFSDM) +# if CONFIG_STM32_DFSDM_TIMTRIG == 0 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC1 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 1 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 1 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC2 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 2 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 2 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC3 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 3 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 3 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16CC4 -# elif CONFIG_STM32L4_DFSDM_TIMTRIG == 4 +# elif CONFIG_STM32_DFSDM_TIMTRIG == 4 # define DFSDM_JEXTSEL_VALUE DFSDM_JEXTSEL_T16TRGO # else -# error "CONFIG_STM32L4_DFSDM_TIMTRIG is out of range" +# error "CONFIG_STM32_DFSDM_TIMTRIG is out of range" # endif #endif @@ -331,5 +331,5 @@ struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_DFSDM */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H */ +#endif /* CONFIG_STM32_DFSDM */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 026c03f7bcb10..01ed7e75475ab 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -44,74 +44,74 @@ typedef void (*boot_call_t)(void); * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) static inline void rcc_reset(void) { uint32_t regval; /* Enable the MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); - while (!(getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY)); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY)); /* Set MSI to 4MHz */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSIRGSEL; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset enable bits for other clocks than MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_HSIASFS | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); - putreg32(0, STM32L4_RCC_PLLSAI1CFG); - putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); - putreg32(0, STM32L4_RCC_PLLSAI2CFG); - putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI2CFG); + putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } static inline void apb_reset(void) { - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR1); - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR2); - putreg32(0xffffffff, STM32L4_RCC_APB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB1RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB3RSTR); - - putreg32(0, STM32L4_RCC_APB1RSTR1); - putreg32(0, STM32L4_RCC_APB1RSTR2); - putreg32(0, STM32L4_RCC_APB2RSTR); - putreg32(0, STM32L4_RCC_AHB1RSTR); - putreg32(0, STM32L4_RCC_AHB2RSTR); - putreg32(0, STM32L4_RCC_AHB3RSTR); + putreg32(0xffffffff, STM32_RCC_APB1RSTR1); + putreg32(0xffffffff, STM32_RCC_APB1RSTR2); + putreg32(0xffffffff, STM32_RCC_APB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB1RSTR); + putreg32(0xffffffff, STM32_RCC_AHB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB3RSTR); + + putreg32(0, STM32_RCC_APB1RSTR1); + putreg32(0, STM32_RCC_APB1RSTR2); + putreg32(0, STM32_RCC_APB2RSTR); + putreg32(0, STM32_RCC_AHB1RSTR); + putreg32(0, STM32_RCC_AHB2RSTR); + putreg32(0, STM32_RCC_AHB3RSTR); } #endif @@ -127,7 +127,7 @@ static inline void apb_reset(void) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) void stm32l4_dfumode(void) { uint32_t regval; @@ -144,10 +144,10 @@ void stm32l4_dfumode(void) /* remap ROM at address zero */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); regval |= RCC_APB2ENR_SYSCFGEN; - putreg32(regval, STM32L4_RCC_APB2ENR); - putreg32(SYSCFG_MEMRMP_SYSTEM, STM32L4_SYSCFG_MEMRMP); + putreg32(regval, STM32_RCC_APB2ENR); + putreg32(SYSCFG_MEMRMP_SYSTEM, STM32_SYSCFG_MEMRMP); /* set stack pointer and program-counter to ROM values */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.h b/arch/arm/src/stm32l4/stm32l4_dfumode.h index 67cd03b0db0af..0c72fbb761a93 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.h +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H /**************************************************************************** * Included Files @@ -41,8 +41,8 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) void stm32l4_dfumode(void) noreturn_function; #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dma.c b/arch/arm/src/stm32l4/stm32l4_dma.c index 5c2b8826acb28..c0e9bf79add9b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.c +++ b/arch/arm/src/stm32l4/stm32l4_dma.c @@ -35,10 +35,10 @@ * family. */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) #include "stm32l4x6xx_dma.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) #include "stm32l4xrxx_dma.c" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 5044edb200b5d..111c5e460bf2c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32L4_STM32_DMA_H /**************************************************************************** * Included Files @@ -34,13 +34,13 @@ /* Include the correct DMA register definitions for this STM32 family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dma.h" # include "hardware/stm32l4xrxx_dmamux.h" #else @@ -90,7 +90,7 @@ struct stm32l4_dmaregs_s uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32L4_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -126,8 +126,8 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Name: stm32l4_dmachannel @@ -168,7 +168,7 @@ extern "C" DMA_HANDLE stm32l4_dmachannel(unsigned int chan); -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Name: stm32_dmachannel @@ -291,7 +291,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32l4_dmacapable(maddr, count, ccr) (true) @@ -338,4 +338,4 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DMA_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index a9f32ad8a822f..48d4cace76373 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L4_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L4_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L4_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L4_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L4_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L4_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L4_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L4_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L4_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L4_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L4_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L4_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L4_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L4_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_MODER_OFFSET), - getreg32(base + STM32L4_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L4_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L4_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04x\n", - getreg32(base + STM32L4_GPIO_IDR_OFFSET), - getreg32(base + STM32L4_GPIO_ODR_OFFSET), - getreg32(base + STM32L4_GPIO_BSRR_OFFSET), - getreg32(base + STM32L4_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_AFRH_OFFSET), - getreg32(base + STM32L4_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 212fab58d3139..5d793625bfdd8 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H /**************************************************************************** * Included Files @@ -141,7 +141,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_COMP +#ifdef CONFIG_STM32_COMP int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c67451e4437d3..2ad3d44cde555 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -73,7 +73,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32L4_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_ALARM, risingedge ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_ALARM, fallingedge ? EXTI1_RTC_ALARM : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_ALARM, event ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_ALARM, func ? EXTI1_RTC_ALARM : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index b3b39ce340fa9..89cf9899ee9d7 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -64,14 +64,14 @@ struct comp_callback_s /* Interrupt handlers attached to the COMP EXTI lines */ -static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM]; +static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM]; /* Comparator EXTI lines */ -static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = +static const uint32_t g_comp_lines[STM32_COMP_NUM] = { -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) EXTI1_COMP1, EXTI1_COMP2 #else @@ -92,15 +92,15 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) /* Examine the state of each comparator line and dispatch interrupts */ - pr = getreg32(STM32L4_EXTI1_PR); - for (i = 0; i < STM32L4_COMP_NUM; i++) + pr = getreg32(STM32_EXTI1_PR); + for (i = 0; i < STM32_COMP_NUM; i++) { ln = g_comp_lines[i]; if ((pr & ln) != 0) { /* Clear the pending interrupt */ - putreg32(ln, STM32L4_EXTI1_PR); + putreg32(ln, STM32_EXTI1_PR); if (g_comp_handlers[i].callback != NULL) { xcpt_t callback = g_comp_handlers[i].callback; @@ -152,25 +152,25 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr, NULL); - up_enable_irq(STM32L4_IRQ_COMP); + irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL); + up_enable_irq(STM32_IRQ_COMP); } else { - up_disable_irq(STM32L4_IRQ_COMP); + up_disable_irq(STM32_IRQ_COMP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, risingedge ? + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : ln, risingedge ? ln : 0); - modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ? + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : ln, fallingedge ? ln : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); - modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); + modifyreg32(STM32_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); + modifyreg32(STM32_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); /* Get the previous IRQ handler and save the new IRQ handler. */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 2b02e9d15aa0c..767bffb83caab 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32L4_EXTI1_PR); + putreg32(0x0001, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32L4_EXTI1_PR); + putreg32(0x0002, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32L4_EXTI1_PR); + putreg32(0x0004, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32L4_EXTI1_PR); + putreg32(0x0008, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32L4_EXTI1_PR); + putreg32(0x0010, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32L4_EXTI1_PR); + pr = getreg32(STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32L4_EXTI1_PR); + putreg32(mask, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -257,7 +257,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32L4_EXTI1_BIT(pin); + uint32_t exti = STM32_EXTI1_BIT(pin); int irq; xcpt_t handler; int nshared; @@ -267,7 +267,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32L4_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32L4_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32l4_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32L4_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32l4_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index b18efc39ef771..854df35b91382 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -71,7 +71,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_PVD_LINE, STM32L4_EXTI1_PR); + putreg32(EXTI1_PVD_LINE, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -116,29 +116,29 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); - up_enable_irq(STM32L4_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32L4_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_PVD_LINE, risingedge ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_PVD_LINE, fallingedge ? EXTI1_PVD_LINE : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_PVD_LINE, event ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_PVD_LINE, func ? EXTI1_PVD_LINE : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h index a9d6b3f0ec0d0..23fc5e227e285 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef STM32L4_EXTI_PWR_H_ -#define STM32L4_EXTI_PWR_H_ +#ifndef __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H +#define __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H /**************************************************************************** * Included Files @@ -55,4 +55,4 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -#endif /* STM32L4_EXTI_PWR_H_ */ +#endif /* __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 24f4e00b3055c..2bcf7b22ef38f 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -73,7 +73,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_WAKEUP, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_WAKEUP, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32L4_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_WAKEUP, risingedge ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_WAKEUP, fallingedge ? EXTI1_RTC_WAKEUP : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_WAKEUP, event ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_WAKEUP, func ? EXTI1_RTC_WAKEUP : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index 56b92cf9b0821..c4597da0e98a5 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -67,34 +67,34 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) * data must be in SRAM1 */ - if ((setup->codestart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->codestart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } - if ((setup->nvdatastart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->nvdatastart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } /* Define address and length registers */ - modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, + modifyreg32(STM32_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, setup->codestart); - modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, + modifyreg32(STM32_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, setup->codelen); - modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, + modifyreg32(STM32_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, setup->nvdatastart); - modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, + modifyreg32(STM32_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, setup->nvdatalen); - modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, + modifyreg32(STM32_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, setup->datastart); - modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, + modifyreg32(STM32_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, setup->datalen); /* Define access options */ - reg = getreg32(STM32L4_FIREWALL_CR); + reg = getreg32(STM32_FIREWALL_CR); if (setup->datashared) { reg |= FIREWALL_CR_VDS; @@ -105,13 +105,13 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) reg |= FIREWALL_CR_VDE; } - putreg32(reg, STM32L4_FIREWALL_CR); + putreg32(reg, STM32_FIREWALL_CR); /* Enable firewall */ - reg = getreg32(STM32L4_SYSCFG_CFGR1); + reg = getreg32(STM32_SYSCFG_CFGR1); reg &= ~SYSCFG_CFGR1_FWDIS; - putreg32(reg, STM32L4_SYSCFG_CFGR1); + putreg32(reg, STM32_SYSCFG_CFGR1); /* Now protected code can only be accessed by jumping to the FW gate */ diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 6e69bddca2e51..e0a8f8c9160dd 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H +#define __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H /**************************************************************************** * Included Files @@ -36,13 +36,13 @@ * family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_firewall.h" #else # error "Unsupported STM32L4 chip" @@ -103,4 +103,4 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FIREWALL_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FIREWALL_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index dc6983cd00f53..da4869d2f7065 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -50,12 +50,12 @@ #include "stm32l4_flash.h" #include "arm_internal.h" -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -70,7 +70,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -78,7 +78,7 @@ #elif FLASH_PAGE_SIZE == 4096 # define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ #else -# error Unsupported STM32L4_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -104,35 +104,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L4_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32L4_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L4_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L4_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -149,54 +149,54 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); -#if defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) if (page <= 0xff) { /* Select bank 1 */ - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); } else { /* Select bank 2 */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); } #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) static void data_cache_disable(void) { - modifyreg32(STM32L4_FLASH_ACR, FLASH_ACR_DCEN, 0); + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); } static void data_cache_enable(void) { /* Reset data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCRST); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); /* Enable data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCEN); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); } -#endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ +#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ /**************************************************************************** * Public Functions @@ -274,20 +274,20 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L4_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L4_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } @@ -300,42 +300,42 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L4_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L4_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L4_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L4_FLASH_PAGESIZE + STM32L4_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L4_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -347,7 +347,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32L4_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -385,7 +385,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -419,12 +419,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L4_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L4_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -494,11 +494,11 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_disable(); #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -506,14 +506,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } /* Verify */ - if (getreg32(STM32L4_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -527,10 +527,10 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif @@ -547,8 +547,8 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif } @@ -560,9 +560,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32L4_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32L4_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h index 89cf22190fa85..8cc8497d964a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/stm32l4_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H /**************************************************************************** * Included Files @@ -56,4 +56,4 @@ int stm32l4_flash_unlock(void); uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 433a55288f29c..250cc27375d2c 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -37,7 +37,7 @@ #include "stm32l4_freerun.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions @@ -69,7 +69,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); return OK; } @@ -117,7 +117,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, return -EBUSY; } - STM32L4_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. @@ -128,17 +128,17 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32L4_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); /* Set timer period */ - STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX); + STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); /* Start the counter */ - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP); - STM32L4_TIM_ACKINT(freerun->tch, 0); - STM32L4_TIM_ENABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + STM32_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ENABLEINT(freerun->tch, 0); return OK; } @@ -184,9 +184,9 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32L4_TIM_GETCOUNTER(freerun->tch); - pending = STM32L4_TIM_CHECKINT(freerun->tch, 0); - verify = STM32L4_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -194,7 +194,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, if (pending) { - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -260,9 +260,9 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32L4_TIM_DISABLEINT(freerun->tch, 0); - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ @@ -272,4 +272,4 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32L4_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index 21ce87d262809..efbd2aa9a2dfa 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H +#define __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types @@ -140,5 +140,5 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun); } #endif -#endif /* CONFIG_STM32L4_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ +#endif /* CONFIG_STM32_FREERUN */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 1cf19f3dac6cb..a1ac054547d59 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -54,34 +54,34 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L4_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L4_NPORTS > 0 - STM32L4_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L4_NPORTS > 1 - STM32L4_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L4_NPORTS > 2 - STM32L4_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L4_NPORTS > 3 - STM32L4_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L4_NPORTS > 4 - STM32L4_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L4_NPORTS > 5 - STM32L4_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L4_NPORTS > 6 - STM32L4_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L4_NPORTS > 7 - STM32L4_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif -#if STM32L4_NPORTS > 8 - STM32L4_GPIOI_BASE, +#if STM32_NPORTS > 8 + STM32_GPIOI_BASE, #endif }; @@ -144,7 +144,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L4_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -202,10 +202,10 @@ int stm32l4_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L4_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -228,10 +228,10 @@ int stm32l4_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L4_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -246,12 +246,12 @@ int stm32l4_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L4_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L4_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -289,14 +289,14 @@ int stm32l4_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L4_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L4_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -309,7 +309,7 @@ int stm32l4_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -331,7 +331,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32L4_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -344,18 +344,18 @@ int stm32l4_configgpio(uint32_t cfgset) * (RM0351 Rev 7, p521) */ -#if defined(CONFIG_STM32L4_STM32L471XX) || \ - defined(CONFIG_STM32L4_STM32L475XX) || \ - defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32_STM32L471XX) || \ + defined(CONFIG_STM32_STM32L475XX) || \ + defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) if (pinmode == GPIO_MODER_ANALOG) { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); } else { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); } #endif @@ -412,7 +412,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -433,7 +433,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -452,7 +452,7 @@ bool stm32l4_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -461,7 +461,7 @@ bool stm32l4_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 2df58191ee1c9..d88b79e7cd268 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,8 +39,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_gpio.h" #else # error "Unsupported STM32L4 chip" @@ -244,7 +244,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes @@ -366,4 +366,4 @@ void stm32l4_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index 75ab0311ff4b5..e34c588f6a156 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -80,13 +80,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * enabled. */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -100,7 +100,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -119,7 +119,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) break; } - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -127,9 +127,9 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -152,17 +152,17 @@ void stm32l4_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index 4028f5a2bbc82..e9ac08187bfb8 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H +#define __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H /**************************************************************************** * Included Files @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32L4_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); void stm32l4_disable_hsi48(void); -#endif /* CONFIG_STM32L4_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 15dfac9e14ee0..2efbd6c775331 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -171,28 +171,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32L4_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32L4_I2C1 - * CONFIG_STM32L4_I2C2 - * CONFIG_STM32L4_I2C3 - * CONFIG_STM32L4_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32L4_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32L4_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32L4_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32L4_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32L4_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -272,8 +272,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C2) || \ - defined(CONFIG_STM32L4_I2C3) || defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -285,25 +285,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32L4_I2CTIMEOSEC) && !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 -# define CONFIG_STM32L4_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32L4_I2CTIMEOSEC) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32L4_I2CTIMEOTICKS -# define CONFIG_STM32L4_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32L4_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32L4_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32L4_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -471,9 +471,9 @@ static inline void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32L4_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv); static inline @@ -517,17 +517,17 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = { - .base = STM32L4_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C1EV, - .er_irq = STM32L4_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -553,17 +553,17 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = { - .base = STM32L4_I2C2_BASE, + .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C2EV, - .er_irq = STM32L4_IRQ_I2C2ER + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER #endif }; @@ -589,17 +589,17 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = { - .base = STM32L4_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C3EV, - .er_irq = STM32L4_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -625,17 +625,17 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = { - .base = STM32L4_I2C4_BASE, + .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, .reset_bit = RCC_APB1RSTR2_I2C4RST, .scl_pin = GPIO_I2C4_SCL, .sda_pin = GPIO_I2C4_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C4EV, - .er_irq = STM32L4_IRQ_I2C4ER + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER #endif }; @@ -758,7 +758,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -775,7 +775,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -791,7 +791,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -823,7 +823,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -833,12 +833,12 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32l4_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32L4_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -861,7 +861,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -877,10 +877,10 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32l4_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -930,7 +930,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } @@ -945,7 +945,7 @@ static inline void stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -959,7 +959,7 @@ stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, static inline void stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -972,7 +972,7 @@ stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -986,7 +986,7 @@ stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -1000,7 +1000,7 @@ stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -1023,10 +1023,10 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1253,20 +1253,20 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, /* I2C peripheral must be disabled to update clocking configuration */ pe = (stm32l4_i2c_getreg32(priv, - STM32L4_I2C_CR1_OFFSET) & I2C_CR1_PE); + STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000) +#if defined(STM32_I2C_USE_HSI16) || (STM32_PCLK1_FREQUENCY == 16000000) i2cclk_mhz = 16; -#elif STM32L4_PCLK1_FREQUENCY == 48000000 +#elif STM32_PCLK1_FREQUENCY == 48000000 i2cclk_mhz = 48; -#elif STM32L4_PCLK1_FREQUENCY == 80000000 +#elif STM32_PCLK1_FREQUENCY == 80000000 i2cclk_mhz = 80; -#elif STM32L4_PCLK1_FREQUENCY == 120000000 +#elif STM32_PCLK1_FREQUENCY == 120000000 i2cclk_mhz = 120; #else # warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone. @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32L4_I2C_TIMINGR_OFFSET, timingr); + stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1605,7 +1605,7 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1626,7 +1626,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1641,7 +1641,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) static inline uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32L4_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1655,7 +1655,7 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1684,7 +1684,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1853,7 +1853,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32L4_I2C_TXDR_OFFSET, *priv->ptr); + stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32L4_I2C_RXDR_OFFSET); + *priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1949,7 +1949,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Unsupported state */ stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2193,7 +2193,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -2216,7 +2216,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,7 +2281,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -2319,19 +2319,19 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) +#ifdef CONFIG_STM32_I2C4 + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR2, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR2, priv->config->reset_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); } /* Configure pins */ @@ -2368,7 +2368,7 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2385,7 +2385,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32L4_I2C_CR1_OFFSET, 0); + stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2404,15 +2404,15 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) +#ifdef CONFIG_STM32_I2C4 + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); } return OK; @@ -2493,8 +2493,8 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, waitrc = stm32l4_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2909,22 +2909,22 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c1_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c2_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c3_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c4_priv; break; @@ -3010,4 +3010,4 @@ int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32L4_I2C1 || CONFIG_STM32L4_I2C2 || CONFIG_STM32L4_I2C3 || CONFIG_STM32L4_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h index 9381a169230a7..41110fa84cdf3 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/stm32l4_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32L4_STM32_I2C_H /**************************************************************************** * Included Files @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO -# if CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32L4_I2C_DYNTIMEO because of CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif @@ -88,4 +88,4 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port); int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_I2C_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 9ab0ccdf05984..65971927574f7 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 3cbb653dd08db..77c20d24e4a8b 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -204,13 +204,13 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L4_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -220,19 +220,19 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L4_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L4_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L4_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L4_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -262,7 +262,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -316,13 +316,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L4_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L4_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -332,23 +332,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L4_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L4_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L4_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L4_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL); #endif stm32l4_dumpnvic("initial", NR_IRQS); @@ -384,7 +384,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -419,7 +419,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -462,10 +462,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L4_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L4_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -478,7 +478,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L4_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 2c0894c78bee7..382b272da6c2f 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -42,7 +42,7 @@ #include "stm32l4_dbgmcu.h" #include "stm32l4_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32L4_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ * 1000 * 4095 / Fmin = 34,944 MSec */ -#define IWDG_FMIN (STM32L4_LSI_FREQUENCY / 256) +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) #define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) /* Configuration ************************************************************/ -#ifndef CONFIG_STM32L4_IWDG_DEFTIMOUT -# define CONFIG_STM32L4_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT #endif #ifndef CONFIG_DEBUG_WATCHDOG_INFO -# undef CONFIG_STM32L4_IWDG_REGDEBUG +# undef CONFIG_STM32_IWDG_REGDEBUG #endif /**************************************************************************** @@ -104,7 +104,7 @@ struct stm32l4_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint16_t val, uint32_t addr); #else @@ -158,7 +158,7 @@ static struct stm32l4_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32l4_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -221,7 +221,7 @@ static uint16_t stm32l4_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static void stm32l4_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR); + stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32L4_IWDG_RLR); + stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,7 +289,7 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -629,7 +629,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32l4_rcc_enablelsi(); - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR)); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the @@ -637,7 +637,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32l4_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32L4_IWDG_DEFTIMOUT); + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -648,9 +648,9 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr; @@ -661,4 +661,4 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32L4_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 56a8fc0391182..440c185a92cb9 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_LPUART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR2 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L4_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK2_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB2ENR -# define STM32L4_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART1_TX -# define STM32L4_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART2_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART2_TX -# define STM32L4_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART3_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART3_TX -# define STM32L4_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART4_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART4_TX -# define STM32L4_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART5_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART5_TX -# define STM32L4_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L4_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L4_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L4_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L4_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L4_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -234,19 +234,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L4_USARTDIV8 \ - (((STM32L4_APBCLOCK << 1) + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) -# define STM32L4_USARTDIV16 \ - ((STM32L4_APBCLOCK + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L4_USARTDIV8 > 100 -# define STM32L4_BRR_VALUE STM32L4_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L4_BRR_VALUE \ - ((STM32L4_USARTDIV8 & 0xfff0) | ((STM32L4_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -288,22 +288,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L4_CONSOLE_BASE + STM32L4_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L4_CONSOLE_RS485_DIR - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -329,7 +329,7 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L4_CONSOLE_APBREG, 0, STM32L4_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -338,17 +338,17 @@ void stm32l4_lowsetup(void) * stm32l4_rcc.c */ -#ifdef STM32L4_CONSOLE_TX - stm32l4_configgpio(STM32L4_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l4_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L4_CONSOLE_RX - stm32l4_configgpio(STM32L4_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l4_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32L4_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -356,42 +356,42 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L4_BRR_VALUE, - STM32L4_CONSOLE_BASE + STM32L4_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.h b/arch/arm/src/stm32l4/stm32l4_lowputc.h index b28b6d975794e..72d8b26d92438 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.h +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32l4_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 0426016bd4464..9c1678d8d91a9 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -84,7 +84,7 @@ #include "stm32l4_lptim.h" #include "stm32l4_rcc.h" -#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) /**************************************************************************** * Private Types @@ -150,23 +150,23 @@ static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = .getperiod = &stm32l4_lptim_getperiod }; -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM1_BASE, - .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM1_BASE, + .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ }; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM2_BASE, - .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM2_BASE, + .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -182,11 +182,11 @@ static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) { switch (timer) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case 1: return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case 2: return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; #endif @@ -217,14 +217,14 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); break; #endif @@ -245,14 +245,14 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); break; #endif @@ -273,16 +273,16 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); - modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); - modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); break; #endif } @@ -300,12 +300,12 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL && cfg != NULL); - channel &= STM32L4_LPTIM_CH_MASK; + channel &= STM32_LPTIM_CH_MASK; switch (((struct stm32l4_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: +#if defined(CONFIG_STM32_LPTIM1) + case STM32_LPTIM1_BASE: switch (channel) { # if defined(GPIO_LPTIM1_OUT_1) @@ -327,10 +327,10 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM1 */ +#endif /* CONFIG_STM32_LPTIM1 */ -#if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: +#if defined(CONFIG_STM32_LPTIM2) + case STM32_LPTIM2_BASE: switch (channel) { # if defined(GPIO_LPTIM2_OUT_1) @@ -352,7 +352,7 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM2 */ default: return ERROR; @@ -369,24 +369,24 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, stm32l4_lptim_mode_t mode) { const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + - STM32L4_LPTIM_CR_OFFSET; + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); /* Mode */ - switch (mode & STM32L4_LPTIM_MODE_MASK) + switch (mode & STM32_LPTIM_MODE_MASK) { - case STM32L4_LPTIM_MODE_DISABLED: + case STM32_LPTIM_MODE_DISABLED: modifyreg32(addr, LPTIM_CR_ENABLE, 0); break; - case STM32L4_LPTIM_MODE_SINGLE: + case STM32_LPTIM_MODE_SINGLE: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); break; - case STM32L4_LPTIM_MODE_CONTINUOUS: + case STM32_LPTIM_MODE_CONTINUOUS: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); break; @@ -469,7 +469,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); stm32l4_lptim_enable(dev); @@ -519,9 +519,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, DEBUGASSERT(dev != NULL); - if (clksrc == STM32L4_LPTIM_CLK_EXT) + if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -531,13 +531,13 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; break; #endif @@ -547,61 +547,61 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (clksrc) { - case STM32L4_LPTIM_CLK_PCLK: + case STM32_LPTIM_CLK_PCLK: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; break; #endif } break; - case STM32L4_LPTIM_CLK_HSI: + case STM32_LPTIM_CLK_HSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSI: + case STM32_LPTIM_CLK_LSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSE: + case STM32_LPTIM_CLK_LSE: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: +#ifdef CONFIG_STM32_LPTIM1 + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: +#ifdef CONFIG_STM32_LPTIM2 + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; break; #endif @@ -611,9 +611,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, break; } - modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits); + modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -632,7 +632,7 @@ static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -645,7 +645,7 @@ static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -657,14 +657,14 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL); - if (cntmode == STM32L4_LPTIM_COUNT_CLOCK) + if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } - else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG) + else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -686,20 +686,20 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, switch (polarity) { - case STM32L4_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_RISING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; - case STM32L4_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_FALLING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; - case STM32L4_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_BOTH: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -725,9 +725,9 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) do { counter1 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); counter2 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); } while (counter1 != counter2); @@ -757,7 +757,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ if (((struct stm32l4_lptim_priv_s *)dev)->mode != - STM32L4_LPTIM_MODE_UNUSED) + STM32_LPTIM_MODE_UNUSED) { return NULL; } @@ -772,7 +772,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } @@ -791,9 +791,9 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } -#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM1 || CONFIG_STM32_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index 1f57f6ac9eda1..7746869fcd21a 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -68,8 +68,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H /**************************************************************************** * Included Files @@ -86,14 +86,14 @@ /* Helpers ******************************************************************/ -#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) -#define STM32L4_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) -#define STM32L4_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) -#define STM32L4_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) +#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) +#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) +#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) /**************************************************************************** * Public Types @@ -121,14 +121,14 @@ struct stm32l4_lptim_dev_s typedef enum { - STM32L4_LPTIM_MODE_UNUSED = -1, + STM32_LPTIM_MODE_UNUSED = -1, /* MODES */ - STM32L4_LPTIM_MODE_DISABLED = 0x0000, - STM32L4_LPTIM_MODE_SINGLE = 0x0001, - STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, - STM32L4_LPTIM_MODE_MASK = 0x000f, + STM32_LPTIM_MODE_DISABLED = 0x0000, + STM32_LPTIM_MODE_SINGLE = 0x0001, + STM32_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32_LPTIM_MODE_MASK = 0x000f, } stm32l4_lptim_mode_t; /* LPTIM Clock Source */ @@ -137,11 +137,11 @@ typedef enum { /* Clock Sources */ - STM32L4_LPTIM_CLK_PCLK = 0x0000, - STM32L4_LPTIM_CLK_LSI = 0x0001, - STM32L4_LPTIM_CLK_HSI = 0x0002, - STM32L4_LPTIM_CLK_LSE = 0x0003, - STM32L4_LPTIM_CLK_EXT = 0x0004, + STM32_LPTIM_CLK_PCLK = 0x0000, + STM32_LPTIM_CLK_LSI = 0x0001, + STM32_LPTIM_CLK_HSI = 0x0002, + STM32_LPTIM_CLK_LSE = 0x0003, + STM32_LPTIM_CLK_EXT = 0x0004, } stm32l4_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -150,8 +150,8 @@ typedef enum { /* Modes */ - STM32L4_LPTIM_COUNT_CLOCK = 0x0000, - STM32L4_LPTIM_COUNT_EXTTRIG = 0x0001, + STM32_LPTIM_COUNT_CLOCK = 0x0000, + STM32_LPTIM_COUNT_EXTTRIG = 0x0001, } stm32l4_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -160,24 +160,24 @@ typedef enum { /* MODES */ - STM32L4_LPTIM_CLKPOL_RISING = 0x0000, - STM32L4_LPTIM_CLKPOL_FALLING = 0x0001, - STM32L4_LPTIM_CLKPOL_BOTH = 0x0002, + STM32_LPTIM_CLKPOL_RISING = 0x0000, + STM32_LPTIM_CLKPOL_FALLING = 0x0001, + STM32_LPTIM_CLKPOL_BOTH = 0x0002, } stm32l4_lptim_clkpol_t; /* LPTIM Channel Modes */ typedef enum { - STM32L4_LPTIM_CH_DISABLED = 0x0000, + STM32_LPTIM_CH_DISABLED = 0x0000, /* CHANNELS */ - STM32L4_LPTIM_CH_CHINVALID = 0x0000, - STM32L4_LPTIM_CH_CH1 = 0x0001, - STM32L4_LPTIM_CH_CH2 = 0x0002, - STM32L4_LPTIM_CH_CH3 = 0x0003, - STM32L4_LPTIM_CH_MASK = 0x000f, + STM32_LPTIM_CH_CHINVALID = 0x0000, + STM32_LPTIM_CH_CH1 = 0x0001, + STM32_LPTIM_CH_CH2 = 0x0002, + STM32_LPTIM_CH_CH3 = 0x0003, + STM32_LPTIM_CH_MASK = 0x000f, } stm32l4_lptim_channel_t; /* LPTIM Operations */ @@ -218,4 +218,4 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_LPTIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_LPTIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 19914bc5b05ab..57adca45b1e66 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -35,16 +35,16 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -68,7 +68,7 @@ void stm32l4_rcc_enablelse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32L4_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -86,37 +86,37 @@ void stm32l4_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32l4_waste(); } -#if defined(CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32L4 only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index fb26a31ba160f..2897d3646bac1 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -46,11 +46,11 @@ void stm32l4_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l4_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.h b/arch/arm/src/stm32l4/stm32l4_mpuinit.h index 986554b2ba8ea..4d2952498e2ce 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.h +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32l4_mpu_uheap(uintptr_t start, size_t size); # define stm32l4_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 0b70b905db882..a8b676a8c8aa7 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -39,7 +39,7 @@ #include "stm32l4_oneshot.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; +static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -86,10 +86,10 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, 0); /* The timer is no longer running */ @@ -117,19 +117,19 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32L4_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) { -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32L4_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -200,7 +200,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, return -EBUSY; } - STM32L4_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -302,19 +302,19 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32L4_TIM_ACKINT(oneshot->tch, 0); - STM32L4_TIM_ENABLEINT(oneshot->tch, 0); + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_ENABLEINT(oneshot->tch, 0); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -389,14 +389,14 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32L4_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; @@ -457,4 +457,4 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32L4_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 0a7d2ff34d526..96787cc6cec8a 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H /**************************************************************************** * Included Files @@ -36,22 +36,22 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32L4_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32L4_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32l4_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -194,5 +194,5 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32L4_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ +#endif /* CONFIG_STM32_ONESHOT */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index bce7dcc074286..880e430899a77 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H +#define __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H /**************************************************************************** * Included Files @@ -33,11 +33,11 @@ #include "stm32l4.h" -#if defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_STM32_OTGFS) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -49,7 +49,7 @@ /* Number of endpoints */ -#define STM32L4_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ /**************************************************************************** * Public Functions Prototypes @@ -116,5 +116,5 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ +#endif /* CONFIG_STM32_OTGFS */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index cfaf97f447309..cb6dd29bc7d08 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -50,7 +50,7 @@ #include "stm32l4_otgfs.h" #include "stm32l4_pwr.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32L4_OTGFS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) /**************************************************************************** * Pre-processor Definitions @@ -58,8 +58,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif #ifndef CONFIG_USBDEV_EP0_MAXSIZE @@ -115,8 +115,8 @@ */ #if CONFIG_USBDEV_EP1_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 1 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 1 # undef CONFIG_USBDEV_EP2_TXFIFO_SIZE # define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE @@ -126,8 +126,8 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP2_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 2 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 2 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE # define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE @@ -135,20 +135,20 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP3_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 3 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 3 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE # define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP4_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 4 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 4 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP5_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 5 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 5 #endif /* Sanity check on allocations specified. */ @@ -168,48 +168,48 @@ * boundaries; FIFO sizes must be provided in units of 32-bit words. */ -#define STM32L4_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32L4_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) -#define STM32L4_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP0_TXFIFO_WORDS < 16 || STM32L4_EP0_TXFIFO_WORDS > 256 +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 # error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP1_TXFIFO_BYTES != 0 && STM32L4_EP1_TXFIFO_WORDS < 16 +#if STM32_EP1_TXFIFO_BYTES != 0 && STM32_EP1_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP2_TXFIFO_BYTES != 0 && STM32L4_EP2_TXFIFO_WORDS < 16 +#if STM32_EP2_TXFIFO_BYTES != 0 && STM32_EP2_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP3_TXFIFO_BYTES != 0 && STM32L4_EP3_TXFIFO_WORDS < 16 +#if STM32_EP3_TXFIFO_BYTES != 0 && STM32_EP3_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP4_TXFIFO_BYTES != 0 && STM32L4_EP4_TXFIFO_WORDS < 16 +#if STM32_EP4_TXFIFO_BYTES != 0 && STM32_EP4_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP4_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP5_TXFIFO_BYTES != 0 && STM32L4_EP5_TXFIFO_WORDS < 16 +#if STM32_EP5_TXFIFO_BYTES != 0 && STM32_EP5_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range" #endif @@ -238,95 +238,95 @@ /* Trace error codes */ -#define STM32L4_TRACEERR_ALLOCFAIL 0x01 -#define STM32L4_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32L4_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32L4_TRACEERR_BADEPNO 0x04 -#define STM32L4_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32L4_TRACEERR_BADGETCONFIG 0x06 -#define STM32L4_TRACEERR_BADGETSETDESC 0x07 -#define STM32L4_TRACEERR_BADGETSTATUS 0x08 -#define STM32L4_TRACEERR_BADSETADDRESS 0x09 -#define STM32L4_TRACEERR_BADSETCONFIG 0x0a -#define STM32L4_TRACEERR_BADSETFEATURE 0x0b -#define STM32L4_TRACEERR_BADTESTMODE 0x0c -#define STM32L4_TRACEERR_BINDFAILED 0x0d -#define STM32L4_TRACEERR_DISPATCHSTALL 0x0e -#define STM32L4_TRACEERR_DRIVER 0x0f -#define STM32L4_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32L4_TRACEERR_EP0NOSETUP 0x11 -#define STM32L4_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32L4_TRACEERR_EPINNULLPACKET 0x13 -#define STM32L4_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32L4_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32L4_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32L4_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32L4_TRACEERR_INVALIDPARMS 0x18 -#define STM32L4_TRACEERR_IRQREGISTRATION 0x19 -#define STM32L4_TRACEERR_NOEP 0x1a -#define STM32L4_TRACEERR_NOTCONFIGURED 0x1b -#define STM32L4_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32L4_TRACEERR_EPINREQEMPTY 0x1d -#define STM32L4_TRACEERR_NOOUTSETUP 0x1e -#define STM32L4_TRACEERR_POLLTIMEOUT 0x1f +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f /* Trace interrupt codes */ -#define STM32L4_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32L4_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ - -#define STM32L4_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32L4_TRACEINTID_EPIN (10 + 1) -#define STM32L4_TRACEINTID_MISMATCH (10 + 2) -#define STM32L4_TRACEINTID_WAKEUP (10 + 3) -#define STM32L4_TRACEINTID_SUSPEND (10 + 4) -#define STM32L4_TRACEINTID_SOF (10 + 5) -#define STM32L4_TRACEINTID_RXFIFO (10 + 6) -#define STM32L4_TRACEINTID_DEVRESET (10 + 7) -#define STM32L4_TRACEINTID_ENUMDNE (10 + 8) -#define STM32L4_TRACEINTID_IISOIXFR (10 + 9) -#define STM32L4_TRACEINTID_IISOOXFR (10 + 10) -#define STM32L4_TRACEINTID_SRQ (10 + 11) -#define STM32L4_TRACEINTID_OTG (10 + 12) - -#define STM32L4_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32L4_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32L4_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32L4_TRACEINTID_DISPATCH (40 + 3) - -#define STM32L4_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32L4_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32L4_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32L4_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32L4_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32L4_TRACEINTID_SETFEATURE (50 + 5) -#define STM32L4_TRACEINTID_SETADDRESS (50 + 6) -#define STM32L4_TRACEINTID_GETSETDESC (50 + 7) -#define STM32L4_TRACEINTID_GETCONFIG (50 + 8) -#define STM32L4_TRACEINTID_SETCONFIG (50 + 9) -#define STM32L4_TRACEINTID_GETSETIF (50 + 10) -#define STM32L4_TRACEINTID_SYNCHFRAME (50 + 11) - -#define STM32L4_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32L4_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32L4_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32L4_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32L4_TRACEINTID_EPIN_TXFE (70 + 4) - -#define STM32L4_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ - -#define STM32L4_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32L4_TRACEINTID_OUTRECVD (90 + 1) -#define STM32L4_TRACEINTID_OUTDONE (90 + 2) -#define STM32L4_TRACEINTID_SETUPDONE (90 + 3) -#define STM32L4_TRACEINTID_SETUPRECVD (90 + 4) +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) /* Endpoints ****************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ -#define STM32L4_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32L4_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) /* Endpoint 0 */ @@ -336,16 +336,16 @@ * This is a bitmap, and the first endpoint (0) is reserved. */ -#define STM32L4_EP_AVAILABLE (((1 << STM32L4_NENDPOINTS) - 1) & ~1) +#define STM32_EP_AVAILABLE (((1 << STM32_NENDPOINTS) - 1) & ~1) /* Maximum packet sizes for full speed endpoints */ -#define STM32L4_MAXPACKET (64) /* Max packet size (1-64) */ +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 -#define STM32L4_FLUSH_DELAY 200000 +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 /* Request queue operations *************************************************/ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32L4_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32L4_NENDPOINTS]; + struct stm32l4_ep_s epin[STM32_NENDPOINTS]; + struct stm32l4_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -548,7 +548,7 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint32_t val, uint32_t addr); #else @@ -789,37 +789,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPNO), - TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADTESTMODE), - TRACE_STR(STM32L4_TRACEERR_BINDFAILED), - TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32L4_TRACEERR_DRIVER), - TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32L4_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32L4_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32L4_TRACEERR_NOEP), - TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32L4_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32L4_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32L4_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32L4_TRACEERR_POLLTIMEOUT), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -831,48 +831,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32L4_TRACEINTID_USB), - TRACE_STR(STM32L4_TRACEINTID_INTPENDING), - TRACE_STR(STM32L4_TRACEINTID_EPOUT), - TRACE_STR(STM32L4_TRACEINTID_EPIN), - TRACE_STR(STM32L4_TRACEINTID_MISMATCH), - TRACE_STR(STM32L4_TRACEINTID_WAKEUP), - TRACE_STR(STM32L4_TRACEINTID_SUSPEND), - TRACE_STR(STM32L4_TRACEINTID_SOF), - TRACE_STR(STM32L4_TRACEINTID_RXFIFO), - TRACE_STR(STM32L4_TRACEINTID_DEVRESET), - TRACE_STR(STM32L4_TRACEINTID_ENUMDNE), - TRACE_STR(STM32L4_TRACEINTID_IISOIXFR), - TRACE_STR(STM32L4_TRACEINTID_IISOOXFR), - TRACE_STR(STM32L4_TRACEINTID_SRQ), - TRACE_STR(STM32L4_TRACEINTID_OTG), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32L4_TRACEINTID_DISPATCH), - TRACE_STR(STM32L4_TRACEINTID_GETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETADDRESS), - TRACE_STR(STM32L4_TRACEINTID_GETSETDESC), - TRACE_STR(STM32L4_TRACEINTID_GETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_SETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_GETSETIF), - TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32L4_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32L4_TRACEINTID_OUTNAK), - TRACE_STR(STM32L4_TRACEINTID_OUTRECVD), - TRACE_STR(STM32L4_TRACEINTID_OUTDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPRECVD), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -893,7 +893,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32l4_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -956,7 +956,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32l4_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -1068,7 +1068,7 @@ static void stm32l4_ep0in_activate(void) /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,13 +1083,13 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -1109,13 +1109,13 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** @@ -1140,7 +1140,7 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); /* Then transfer each word to the TxFIFO */ @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32L4_OTGFS_DSTS); + uint32_t status = stm32l4_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,7 +1254,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the @@ -1308,7 +1308,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINREQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); /* There is no TX transfer in progress and no new pending TX * requests to send. To stop transmitting any data on a particular @@ -1316,7 +1316,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * bit, the following field must be programmed. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1419,7 +1419,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * n: n words available */ - regaddr = STM32L4_OTGFS_DTXFSTS(privep->epphy); + regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); /* Check for space in the TxFIFO. If space in the TxFIFO is not * available, then set up an interrupt to resume the transfer when @@ -1429,23 +1429,23 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, regval = stm32l4_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32L4_OTG_DIEPTXF(privep->epphy)); + regval = stm32l4_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1519,7 +1519,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits and write 4 x 8-bits at time * (to avoid unaligned accesses) @@ -1565,7 +1565,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits at time */ @@ -1607,7 +1607,7 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * should not happen. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); privep->active = false; return; } @@ -1681,7 +1681,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * does not become constipated. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOOUTSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); stm32l4_rxfifo_discard(privep, bcnt); privep->active = false; } @@ -1732,7 +1732,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* Discard the data in the RxFIFO */ @@ -1814,7 +1814,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* There are no read requests to be setup. Configure the @@ -1823,7 +1823,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * NAK after a transfer is completed until SNAK is cleared). */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1842,7 +1842,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_req_complete(privep, OK); } @@ -1870,7 +1870,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ - regaddr = STM32L4_OTGFS_DOEPTSIZ(privep->epphy); + regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); @@ -1879,7 +1879,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then enable the transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must @@ -2021,7 +2021,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { return NULL; } @@ -2057,7 +2057,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { int ret = -EIO; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -2070,7 +2070,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->stalled = true; } @@ -2093,9 +2093,9 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ @@ -2112,17 +2112,17 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Mark all endpoints as available */ - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Disable all end point interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS ; i++) + for (i = 0; i < STM32_NENDPOINTS ; i++) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ @@ -2143,22 +2143,22 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ @@ -2212,7 +2212,7 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADTESTMODE), testmode); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); priv->dotest = false; priv->testmode = OTGFS_TESTMODE_DISABLED; priv->stalled = true; @@ -2249,7 +2249,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); if (!priv->addressed || ctrlreq->len != 2 || USB_REQ_ISOUT(ctrlreq->type) || @@ -2264,12 +2264,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_ENDPOINT: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_EPGETSTATUS), 0); + STM32_TRACEINTID_EPGETSTATUS), 0); privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), 0); + STM32_TRACEERR_BADEPGETSTATUS), 0); priv->stalled = true; } else @@ -2294,7 +2294,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if (ctrlreq->index == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), 0); + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup and self-powered */ @@ -2309,7 +2309,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), 0); + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = true; } } @@ -2318,7 +2318,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_IFGETSTATUS), 0); + STM32_TRACEINTID_IFGETSTATUS), 0); priv->ep0data[0] = 0; priv->ep0data[1] = 0; @@ -2329,7 +2329,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, default: { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADGETSTATUS), 0); + STM32_TRACEERR_BADGETSTATUS), 0); priv->stalled = true; } break; @@ -2346,7 +2346,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2373,7 +2373,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->stalled = true; } } @@ -2387,7 +2387,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2419,13 +2419,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } @@ -2439,7 +2439,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2457,7 +2457,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->stalled = true; } } @@ -2478,7 +2478,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { @@ -2486,7 +2486,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); priv->stalled = true; } } @@ -2500,7 +2500,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2512,7 +2512,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->stalled = true; } } @@ -2526,7 +2526,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2559,7 +2559,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->stalled = true; } } @@ -2580,7 +2580,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); stm32l4_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2593,13 +2593,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = true; } break; @@ -2623,7 +2623,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->ep0state != EP0STATE_SETUP_READY) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0NOSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); return; } @@ -2673,7 +2673,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); stm32l4_ep0_stall(priv); } @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); + regval &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,10 +2777,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTUNEXPECTED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), (uint16_t)regval); epno = 0; @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(epno)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,8 +2811,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32L4_OTGFS_DOEPMSK); + doepint = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32l4_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. * This interrupt is triggered when stm32l4_rxinterrupt() removes @@ -2823,13 +2823,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_XFRC, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ @@ -2844,13 +2844,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_EPDISD, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2858,7 +2858,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_SETUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup @@ -2872,7 +2872,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } stm32l4_putreg(OTGFS_DOEPINT_SETUP, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } } @@ -2892,10 +2892,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) static inline void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + uint32_t regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + daint &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,8 +3022,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINUNEXPECTED), + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); daint &= OTGFS_DAINT_IEP_MASK; @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(epno)); + epno, stm32l4_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32L4_OTGFS_DIEPMSK); + mask = stm32l4_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + empty = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32l4_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3086,7 +3086,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), (uint16_t)diepint); /* It is possible that logic may be waiting for a the @@ -3096,9 +3096,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); stm32l4_putreg(OTGFS_DIEPINT_XFRC, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ @@ -3109,9 +3109,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TOC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32L4_OTGFS_DIEPINT(epno)); + stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3123,11 +3123,11 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_ITTXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); stm32l4_epin_request(priv, &priv->epin[epno]); stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } /* IN endpoint NAK effective (ignored as this used only in polled @@ -3136,10 +3136,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_INEPNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_INEPNE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3149,10 +3149,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_EPDISD, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3160,7 +3160,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); /* If we were waiting for TxFIFO to become empty, the we might @@ -3176,7 +3176,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ @@ -3186,7 +3186,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the pending TxFIFO empty interrupt */ stm32l4_putreg(OTGFS_DIEPINT_TXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } } @@ -3210,16 +3210,16 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3305,23 +3305,23 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + regval = stm32l4_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; - /* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP + /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP * register happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c * All of which provide out of range indexes for epout[epphy] */ - if (epphy < STM32L4_NENDPOINTS) + if (epphy < STM32_NENDPOINTS) { privep = &priv->epout[epphy]; @@ -3338,7 +3338,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTNAK: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); } break; @@ -3351,7 +3351,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT; @@ -3375,7 +3375,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); } break; @@ -3392,7 +3392,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); /* On the L4 This event does not occur on the next SETUP @@ -3412,7 +3412,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { uint16_t datlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); /* Read EP0 setup data. NOTE: If multiple SETUP packets are @@ -3459,7 +3459,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT); } @@ -3489,10 +3489,10 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) * PHY interface. */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** @@ -3515,7 +3515,7 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * transfers. */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous IN endpoint? */ @@ -3538,9 +3538,9 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3599,7 +3599,7 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * DOEPCTLx:EPENA = 1 */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous OUT endpoint? */ @@ -3622,9 +3622,9 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3684,7 +3684,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Check for session end detected */ - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGINT); + regval = stm32l4_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,7 +3692,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(regval, STM32_OTGFS_GOTGINT); } #endif @@ -3717,11 +3717,11 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t reserved; - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), priv->ep0state); /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,16 +3733,16 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), - STM32L4_OTGFS_GINTSTS); + STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and * unmasked) interrupts to be processes. @@ -3753,7 +3753,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) break; } - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an @@ -3762,7 +3762,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); stm32l4_epout_interrupt(priv); } @@ -3773,7 +3773,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); stm32l4_epin_interrupt(priv); } @@ -3783,7 +3783,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_DEBUG_FEATURES if ((regval & OTGFS_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); } #endif @@ -3792,7 +3792,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); stm32l4_resumeinterrupt(priv); } @@ -3801,7 +3801,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); stm32l4_suspendinterrupt(priv); } @@ -3811,7 +3811,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & OTGFS_GINT_SOF) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); } @@ -3823,7 +3823,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); stm32l4_rxinterrupt(priv); } @@ -3832,13 +3832,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVRESET), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); /* Perform the device reset */ stm32l4_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3846,7 +3846,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); stm32l4_enuminterrupt(priv); } @@ -3860,7 +3860,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTGFS_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); stm32l4_isocininterrupt(priv); } @@ -3877,7 +3877,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); stm32l4_isocoutinterrupt(priv); } @@ -3888,7 +3888,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_VBUSSENSING if ((regval & OTGFS_GINT_SRQ) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); stm32l4_sessioninterrupt(priv); } @@ -3897,14 +3897,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OTG) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); stm32l4_otginterrupt(priv); } #endif } - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3927,14 +3927,14 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + while ((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,7 +3954,7 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32L4_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32l4_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } @@ -3972,9 +3972,9 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -4042,7 +4042,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { @@ -4066,9 +4066,9 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4138,7 +4138,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4164,9 +4164,9 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4264,7 +4264,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) * int DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); @@ -4275,7 +4275,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,7 +4285,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32L4_OTGFS_DOEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. @@ -4295,9 +4295,9 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ @@ -4326,7 +4326,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * hardware. Trying to disable again will just hang in the wait. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4342,11 +4342,11 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32L4_OTGFS_DIEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4356,7 +4356,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * NAK mode */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ @@ -4369,7 +4369,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4379,7 +4379,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * endpoint is completely disabled. */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ @@ -4392,9 +4392,9 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ @@ -4417,7 +4417,7 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4457,7 +4457,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -4468,7 +4468,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -4492,7 +4492,7 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -4566,7 +4566,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -4579,7 +4579,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); return -ESHUTDOWN; } @@ -4658,7 +4658,7 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4704,7 +4704,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * in the DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); stm32l4_putreg(regval, regaddr); @@ -4714,7 +4714,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4742,7 +4742,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; stm32l4_putreg(regval, regaddr); @@ -4769,7 +4769,7 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) /* Get the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* Then stall the endpoint */ @@ -4830,7 +4830,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); stallbit = OTGFS_DIEPCTL_STALL; data0bit = OTGFS_DIEPCTL_SD0PID; } @@ -4838,7 +4838,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); stallbit = OTGFS_DOEPCTL_STALL; data0bit = OTGFS_DOEPCTL_SD0PID; } @@ -4966,9 +4966,9 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * by the hardware. */ - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); return NULL; } @@ -4988,7 +4988,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * endpoints. */ - for (epno = 1; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 1; epno < STM32_NENDPOINTS; epno++) { uint8_t bit = 1 << epno; if ((epavail & bit) != 0) @@ -5007,7 +5007,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, /* We should not get here */ } - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); leave_critical_section(flags); return NULL; } @@ -5055,7 +5055,7 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5124,7 +5124,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_FEATURES if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -5148,7 +5148,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,7 +5166,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } @@ -5186,10 +5186,10 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5257,13 +5257,13 @@ static int stm32l4_rxfifo_flush(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5296,12 +5296,12 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Initialize the IN endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5319,7 +5319,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYIN2LOG(i); + privep->ep.eplog = STM32_EPPHYIN2LOG(i); /* Control until endpoint is activated */ @@ -5329,7 +5329,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) /* Initialize the OUT endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5346,7 +5346,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYOUT2LOG(i); + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); /* Control until endpoint is activated */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32L4_OTGFS_GAHBCFG); + stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5390,10 +5390,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32L4_OTGFS_GRSTCTL); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,101 +5426,101 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG); + stm32l4_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL); + regval = stm32l4_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL); + stm32l4_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32L4_RXFIFO_WORDS, STM32L4_OTGFS_GRXFSIZ); + stm32l4_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); -#if STM32L4_NENDPOINTS > 0 +#if STM32_NENDPOINTS > 0 /* EP0 TX */ - address = STM32L4_RXFIFO_WORDS; + address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | - (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); + (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif -#if STM32L4_NENDPOINTS > 1 +#if STM32_NENDPOINTS > 1 /* EP1 TX */ - address += STM32L4_EP0_TXFIFO_WORDS; + address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(1)); + (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif -#if STM32L4_NENDPOINTS > 2 +#if STM32_NENDPOINTS > 2 /* EP2 TX */ - address += STM32L4_EP1_TXFIFO_WORDS; + address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(2)); + (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif -#if STM32L4_NENDPOINTS > 3 +#if STM32_NENDPOINTS > 3 /* EP3 TX */ - address += STM32L4_EP2_TXFIFO_WORDS; + address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(3)); + (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif -#if STM32L4_NENDPOINTS > 4 +#if STM32_NENDPOINTS > 4 /* EP4 TX */ - address += STM32L4_EP3_TXFIFO_WORDS; + address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(4)); + (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif -#if STM32L4_NENDPOINTS > 5 +#if STM32_NENDPOINTS > 5 /* EP5 TX */ - address += STM32L4_EP4_TXFIFO_WORDS; + address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5)); + (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ @@ -5530,17 +5530,17 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5622,7 +5622,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) */ stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, - STM32L4_OTGFS_GAHBCFG); + STM32_OTGFS_GAHBCFG); } /**************************************************************************** @@ -5687,7 +5687,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT stm32l4_configgpio(GPIO_OTGFS_SOF); #endif @@ -5703,7 +5703,7 @@ void arm_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5724,7 +5724,7 @@ void arm_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return; errout: @@ -5752,7 +5752,7 @@ void arm_usbuninitialize(void) if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -5764,22 +5764,22 @@ void arm_usbuninitialize(void) /* Disable and detach IRQs */ - up_disable_irq(STM32L4_IRQ_OTGFS); - irq_detach(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); + irq_detach(STM32_IRQ_OTGFS); /* Disable all endpoint interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ @@ -5819,13 +5819,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -5839,14 +5839,14 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); priv->driver = NULL; } else { /* Enable USB controller interrupts */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set * the RS bit to enable the controller. It kind of makes sense @@ -5891,7 +5891,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -5911,7 +5911,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts */ flags = enter_critical_section(); - up_disable_irq(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); /* Disconnect device */ @@ -5925,4 +5925,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32L4_OTGFSDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGFSDEV */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index fa712e9494478..f40c03d08b326 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32l4_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -69,82 +69,82 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: + * CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: * 128 - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. - * CONFIG_STM32L4_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_RXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTGFS_RXFIFO_SIZE +# define CONFIG_STM32_OTGFS_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_NPTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_PTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32L4_OTGFS_DESCSIZE -# define CONFIG_STM32L4_OTGFS_DESCSIZE 128 +#ifndef CONFIG_STM32_OTGFS_DESCSIZE +# define CONFIG_STM32_OTGFS_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG */ #ifndef CONFIG_DEBUG -# undef CONFIG_STM32L4_USBHOST_REGDEBUG -# undef CONFIG_STM32L4_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ /* Hardware capabilities */ -#define STM32L4_NHOST_CHANNELS 8 /* Number of host channels */ -#define STM32L4_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32L4_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32L4_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ -#define STM32L4_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ -#define STM32L4_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32L4_RETRY_COUNT 3 /* Number of ctrl transfer retries */ +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 /* In loop counts */ -#define STM32L4_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32L4_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32L4_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ /**************************************************************************** * Private Types @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32L4_MAX_TX_FIFOS]; + struct stm32l4_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -269,7 +269,7 @@ struct stm32l4_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32l4_getreg(uint32_t addr); @@ -282,7 +282,7 @@ static void stm32l4_putreg(uint32_t addr, uint32_t value); static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32l4_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32l4_pktdump(m,b,n) @@ -380,7 +380,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv); #endif static inline void @@ -504,7 +504,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) { lldbg("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -519,7 +519,7 @@ static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -583,7 +583,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32l4_getreg(uint32_t addr) { /* Read the value from the register */ @@ -605,7 +605,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32l4_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -659,7 +659,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) /* Search the table of channels */ - for (chidx = 0; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { /* Is this channel available? */ @@ -687,7 +687,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) { - DEBUGASSERT((unsigned)chidx < STM32L4_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ @@ -712,7 +712,7 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) /* Free all host channels */ - for (chidx = 2; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { stm32l4_chan_free(priv, chidx); } @@ -736,7 +736,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32L4_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32l4_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,7 +876,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,13 +957,13 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + intmsk = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), intmsk); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** @@ -1193,7 +1193,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1218,7 +1218,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1413,10 +1413,10 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * packets that can be transferred (this should not happen). */ - if (npackets > STM32L4_MAX_PKTCOUNT) + if (npackets > STM32_MAX_PKTCOUNT) { - npackets = STM32L4_MAX_PKTCOUNT; - chan->buflen = STM32L4_MAX_PKTCOUNT * maxpacket; + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); } } @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32L4_OTGFS_HCTSIZ(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32L4_OTGFS_HFNUM) & 1) == 0) + if ((stm32l4_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1572,7 +1572,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, static inline uint16_t stm32l4_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32L4_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32l4_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif @@ -1647,7 +1647,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_SETUP_DELAY); + while (elapsed < STM32_SETUP_DELAY); return -ETIMEDOUT; } @@ -1893,7 +1893,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, */ clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32L4_DATANAK_DELAY) + if (elapsed >= STM32_DATANAK_DELAY) { /* Timeout out... break out returning the NAK as * as a failure. @@ -2247,7 +2247,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32L4_DATANAK_DELAY || /* Timeout has elapsed OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ chan->xfrd > 0) /* Data has been partially * transferred */ { @@ -2419,7 +2419,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, /* Get the address of the Tx FIFO associated with this channel */ - fifo = STM32L4_OTGFS_DFIFO_HCH(chidx); + fifo = STM32_OTGFS_DFIFO_HCH(chidx); /* Transfer all of the data into the Tx FIFO */ @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,7 +2489,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is @@ -2517,7 +2517,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2531,7 +2531,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2556,15 +2556,15 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * logic as each packet was received. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2633,7 +2633,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2671,10 +2671,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else @@ -2685,7 +2685,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2751,7 +2751,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2772,7 +2772,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,7 +2781,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. @@ -2800,7 +2800,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2815,7 +2815,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2829,7 +2829,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2845,7 +2845,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,7 +2913,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ @@ -3009,7 +3009,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3018,7 +3018,7 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + intmsk = stm32l4_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + grxsts = stm32l4_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3077,7 +3077,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Transfer the packet from the Rx FIFO into the user buffer */ dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32L4_OTGFS_DFIFO_HCH(0); + fifo = STM32_OTGFS_DFIFO_HCH(0); bcnt32 = (bcnt + 3) >> 2; for (i = 0; i < bcnt32; i++) @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32L4_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32l4_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,7 +3121,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3319,12 +3319,12 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) int i = 0; /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32L4_NHOST_CHANNELS-1), corresponds to + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32L4_OTGFS_HAINT); - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + haint = stm32l4_getreg(STM32_OTGFS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(i)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32L4_OTGFS_HPRT); + hprt = stm32l4_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3425,7 +3425,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32L4_OTGFS_HCFG); + hcfg = stm32l4_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 6000); + stm32l4_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,7 +3449,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3459,7 +3459,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 48000); + stm32l4_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,7 +3472,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3484,7 +3484,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32L4_OTGFS_HPRT, newhprt); + stm32l4_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** @@ -3503,7 +3503,7 @@ static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** @@ -3522,13 +3522,13 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(0)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(0), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + pending = stm32l4_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3580,7 +3580,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR if ((pending & OTGFS_GINT_SOF) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); @@ -3669,9 +3669,9 @@ static void stm32l4_gint_enable(void) /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } static void stm32l4_gint_disable(void) @@ -3680,9 +3680,9 @@ static void stm32l4_gint_disable(void) /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** @@ -3705,19 +3705,19 @@ static inline void stm32l4_hostinit_enable(void) /* Disable all interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, 0); + stm32l4_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GOTGINT, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xbfffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3746,14 +3746,14 @@ static inline void stm32l4_hostinit_enable(void) * OTGFS_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR regval |= (OTGFS_GINT_SOF | OTGFS_GINT_RXFLVL | OTGFS_GINT_IISOOXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #else regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3972,7 +3972,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Get the current device speed */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -4205,11 +4205,11 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ret = nxmutex_lock(&priv->lock); /* A single channel is represent by an index in the range of 0 to - * STM32L4_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an * allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32L4_MAX_TX_FIFOS) + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) { /* Halt the channel and mark the channel available */ @@ -4277,7 +4277,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32L4_OTGFS_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTGFS_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4286,7 +4286,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32L4_OTGFS_DESCSIZE; + *maxlen = CONFIG_STM32_OTGFS_DESCSIZE; return OK; } @@ -4480,7 +4480,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4526,7 +4526,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4569,7 +4569,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4619,7 +4619,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4678,7 +4678,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4750,7 +4750,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4804,7 +4804,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) uvdbg("chidx: %u: %d\n", chidx); - DEBUGASSERT(priv && chidx < STM32L4_MAX_TX_FIFOS); + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; /* We need to disable interrupts to avoid race conditions with the @@ -4976,16 +4976,16 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, regval); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5051,13 +5051,13 @@ static void stm32l4_flush_rxfifo(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5094,20 +5094,20 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); @@ -5138,14 +5138,14 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32L4_OTGFS_PCGCCTL, 0); + stm32l4_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ @@ -5153,9 +5153,9 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,23 +5163,23 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32L4_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); - offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; + stm32l4_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); + offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HNPTXFSIZ, regval); - offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; + stm32l4_putreg(STM32_OTGFS_HNPTXFSIZ, regval); + offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HPTXFSIZ, regval); + stm32l4_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5192,10 +5192,10 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear all pending HC Interrupts */ - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32L4_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(i), 0); + stm32l4_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG @@ -5275,11 +5275,11 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32L4_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); /* Initialize each channel */ - for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++) + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { struct stm32l4_chan_s *chan = &priv->chan[i]; @@ -5311,18 +5311,18 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5352,10 +5352,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifndef CONFIG_USBDEV_VBUSSENSING regval |= OTGFS_GCCFG_NOVBUSSENS; #endif -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32L4_OTGFS_GCCFG, regval); + stm32l4_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,10 +5364,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ @@ -5457,7 +5457,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT stm32l4_configgpio(GPIO_OTGFS_SOF); #endif @@ -5467,7 +5467,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5479,8 +5479,8 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable interrupts at the interrupt controller */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h index d8f276e282a03..466571b6330d4 100644 --- a/arch/arm/src/stm32l4/stm32l4_pm.h +++ b/arch/arm/src/stm32l4/stm32l4_pm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PM_H /**************************************************************************** * Included Files @@ -148,4 +148,4 @@ int stm32l4_pmlpr(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index 100de46b5d0af..d43ae86f66ffb 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -75,7 +75,7 @@ int stm32l4_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ @@ -83,27 +83,27 @@ int stm32l4_pmlpr(void) regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index da50343ec3956..0866f7a2f5a53 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -79,15 +79,15 @@ int stm32l4_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32L4_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index 8718d575322f4..f116c76968fbd 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -114,7 +114,7 @@ int stm32l4_pmstop(bool lpds) * register 1. */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -124,7 +124,7 @@ int stm32l4_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1LPR; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -149,8 +149,8 @@ int stm32l4_pmstop2(void) { uint32_t regval; - regval = getreg32(STM32L4_PWR_CR1); -#ifdef CONFIG_STM32L4_SRAM3_HEAP + regval = getreg32(STM32_PWR_CR1); +#ifdef CONFIG_STM32_SRAM3_HEAP /* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */ regval |= PWR_CR1_RRSTP; @@ -160,7 +160,7 @@ int stm32l4_pmstop2(void) regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 08807a2334e21..4c4a4d4691e20 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -46,7 +46,7 @@ * intended for use with the pulsecount upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PULSECOUNT) || defined(CONFIG_STM32L4_TIM8_PULSECOUNT) +#if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) /**************************************************************************** * Pre-processor Definitions @@ -159,10 +159,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -189,107 +189,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32l4_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM1UP, - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM1UP, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32l4_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM8UP, - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, + .irq = STM32_IRQ_TIM8UP, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -300,7 +300,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32l4_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -308,7 +308,7 @@ static struct stm32l4_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32l4_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -407,30 +407,30 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } #endif @@ -450,25 +450,25 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, { case 1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } case 2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } case 3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } case 4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } @@ -520,7 +520,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, /* Get the reload values */ - reload = pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); /* Duty cycle: * @@ -617,8 +617,8 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, /* Set the reload and prescaler values */ - pulsecount_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32L4_GTIM_PSC_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; @@ -638,7 +638,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Set up the advanced timer CR1 register. */ - cr1 = pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Pulsecount always uses edge-aligned up-counting mode. */ @@ -653,7 +653,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Write CR1 */ - pulsecount_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); return OK; } @@ -689,14 +689,14 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 1: case 2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } case 3: case 4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } @@ -773,8 +773,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Get current registers state */ - cr2 = pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx | IDLE | advanced timers | CR2 register * | CCxP | POL | all pulsecount timers | CCER register @@ -807,8 +807,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Write registers */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -838,7 +838,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Get current register state */ - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ @@ -865,7 +865,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Write register */ - pulsecount_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -881,11 +881,11 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, if (enable) { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } else { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } } @@ -933,7 +933,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) /* Disable the timer until we get it configured */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); /* Get configured outputs */ @@ -1015,8 +1015,8 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, /* Disable all interrupts and DMA requests, clear all pending status */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Set timer frequency */ @@ -1051,14 +1051,14 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, */ priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Now set the value of the RCR that will be loaded on the next * update event. @@ -1066,7 +1066,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, priv->count = info->count; priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1076,11 +1076,11 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Get configured outputs */ @@ -1105,12 +1105,12 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Clear all pending interrupts and enable the update interrupt. */ - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); /* And enable timer interrupts at the NVIC */ @@ -1144,12 +1144,12 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) /* Verify that this is an update interrupt. Nothing else is expected. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_SR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - pulsecount_putreg(priv, STM32L4_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); /* Calculate the new count by subtracting the number of pulses * since the last interrupt. @@ -1161,9 +1161,9 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * quickly as possible. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); regval &= ~ATIM_BDTR_MOE; - pulsecount_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, regval); + pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); /* Disable first interrupts, stop and reset the timer */ @@ -1194,7 +1194,7 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) priv->prev = priv->curr; priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32L4_ATIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1224,21 +1224,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1308,19 +1308,19 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -1482,15 +1482,15 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1506,8 +1506,8 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pulsecount_start() can be called. @@ -1624,7 +1624,7 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1634,7 +1634,7 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; @@ -1654,4 +1654,4 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) return (struct pulsecount_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT || CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT || CONFIG_STM32_TIM8_PULSECOUNT */ diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.h b/arch/arm/src/stm32l4/stm32l4_pulsecount.h index 8d1a95c595ba9..81eddce243644 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.h +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H /**************************************************************************** * Included Files @@ -36,4 +36,4 @@ struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 46d0aff819376..4468b2b603094 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -46,12 +46,12 @@ * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /**************************************************************************** * Pre-processor Definitions @@ -91,9 +91,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -101,7 +101,7 @@ /* Low power Timer support */ -#if defined(CONFIG_STM32L4_LPTIM1_PWM) || defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) || defined(CONFIG_STM32_LPTIM2_PWM) # define HAVE_LPTIM #else # undef HAVE_LPTIM @@ -109,16 +109,16 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32L4_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif /* Break support */ -#if defined(CONFIG_STM32L4_TIM1_BREAK1) || defined(CONFIG_STM32L4_TIM1_BREAK2) || \ - defined(CONFIG_STM32L4_TIM8_BREAK1) || defined(CONFIG_STM32L4_TIM8_BREAK2) || \ - defined(CONFIG_STM32L4_TIM15_BREAK1) || defined(CONFIG_STM32L4_TIM16_BREAK1) || \ - defined(CONFIG_STM32L4_TIM17_BREAK1) +#if defined(CONFIG_STM32_TIM1_BREAK1) || defined(CONFIG_STM32_TIM1_BREAK2) || \ + defined(CONFIG_STM32_TIM8_BREAK1) || defined(CONFIG_STM32_TIM8_BREAK2) || \ + defined(CONFIG_STM32_TIM15_BREAK1) || defined(CONFIG_STM32_TIM16_BREAK1) || \ + defined(CONFIG_STM32_TIM17_BREAK1) # defined HAVE_BREAK #endif @@ -165,7 +165,7 @@ struct stm32l4_pwmchan_s struct stm32l4_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32l4_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32l4_pwmchan_s *channels; /* Channels configuration */ @@ -226,7 +226,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr); static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode); -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr); @@ -237,10 +237,10 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev); static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency); static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state); -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -273,7 +273,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32l4_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -296,138 +296,138 @@ static const struct stm32l4_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32l4_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM1_BREAK1 +#ifdef CONFIG_STM32_TIM1_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM1_BRK1POL, + .pol1 = CONFIG_STM32_TIM1_BRK1POL, #endif -#ifdef CONFIG_STM32L4_TIM1_BREAK2 +#ifdef CONFIG_STM32_TIM1_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32L4_TIM1_BRK2POL, - .flt2 = CONFIG_STM32L4_TIM1_BRK2FLT, + .pol2 = CONFIG_STM32_TIM1_BRK2POL, + .flt2 = CONFIG_STM32_TIM1_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1POL, - .idle = CONFIG_STM32L4_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1NPOL, - .idle = CONFIG_STM32L4_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM1_CH2MODE, -#ifdef CONFIG_STM32L4_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2POL, - .idle = CONFIG_STM32L4_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2NPOL, - .idle = CONFIG_STM32L4_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM1_CH3MODE, -#ifdef CONFIG_STM32L4_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3POL, - .idle = CONFIG_STM32L4_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3NPOL, - .idle = CONFIG_STM32L4_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM1_CH4MODE, -#ifdef CONFIG_STM32L4_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH4POL, - .idle = CONFIG_STM32L4_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM1_CH5MODE, -#ifdef CONFIG_STM32L4_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH5POL, - .idle = CONFIG_STM32L4_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM1_CH6MODE, -#ifdef CONFIG_STM32L4_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH6POL, - .idle = CONFIG_STM32L4_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -438,91 +438,91 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = static struct stm32l4_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32L4_TIM1_MODE, - .lock = CONFIG_STM32L4_TIM1_LOCK, - .t_dts = CONFIG_STM32L4_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM1_TRGO) - .trgo = STM32L4_TIM1_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, #endif - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32l4_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM2_CH1MODE, -#ifdef CONFIG_STM32L4_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH1POL, - .idle = CONFIG_STM32L4_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM2_CH2MODE, -#ifdef CONFIG_STM32L4_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH2POL, - .idle = CONFIG_STM32L4_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM2_CH3MODE, -#ifdef CONFIG_STM32L4_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH3POL, - .idle = CONFIG_STM32L4_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM2_CH4MODE, -#ifdef CONFIG_STM32L4_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH4POL, - .idle = CONFIG_STM32L4_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -534,92 +534,92 @@ static struct stm32l4_pwmchan_s g_pwm2channels[] = static struct stm32l4_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32L4_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM2_TRGO) - .trgo = STM32L4_TIM2_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, #endif - .base = STM32L4_TIM2_BASE, - .pclk = STM32L4_APB1_TIM2_CLKIN, + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32l4_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM3_CH1MODE, -#ifdef CONFIG_STM32L4_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH1POL, - .idle = CONFIG_STM32L4_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM3_CH2MODE, -#ifdef CONFIG_STM32L4_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH2POL, - .idle = CONFIG_STM32L4_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM3_CH3MODE, -#ifdef CONFIG_STM32L4_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH3POL, - .idle = CONFIG_STM32L4_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM3_CH4MODE, -#ifdef CONFIG_STM32L4_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH4POL, - .idle = CONFIG_STM32L4_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -631,91 +631,91 @@ static struct stm32l4_pwmchan_s g_pwm3channels[] = static struct stm32l4_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32L4_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM3_TRGO) - .trgo = STM32L4_TIM3_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, #endif - .base = STM32L4_TIM3_BASE, - .pclk = STM32L4_APB1_TIM3_CLKIN, + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32l4_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM4_CH1MODE, -#ifdef CONFIG_STM32L4_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH1POL, - .idle = CONFIG_STM32L4_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM4_CH2MODE, -#ifdef CONFIG_STM32L4_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH2POL, - .idle = CONFIG_STM32L4_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM4_CH3MODE, -#ifdef CONFIG_STM32L4_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH3POL, - .idle = CONFIG_STM32L4_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM4_CH4MODE, -#ifdef CONFIG_STM32L4_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH4POL, - .idle = CONFIG_STM32L4_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -727,90 +727,90 @@ static struct stm32l4_pwmchan_s g_pwm4channels[] = static struct stm32l4_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32L4_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM4_TRGO) - .trgo = STM32L4_TIM4_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, #endif - .base = STM32L4_TIM4_BASE, - .pclk = STM32L4_APB1_TIM4_CLKIN, + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32l4_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM5_CH1MODE, -#ifdef CONFIG_STM32L4_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH1POL, - .idle = CONFIG_STM32L4_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM5_CH2MODE, -#ifdef CONFIG_STM32L4_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH2POL, - .idle = CONFIG_STM32L4_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM5_CH3MODE, -#ifdef CONFIG_STM32L4_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH3POL, - .idle = CONFIG_STM32L4_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM5_CH4MODE, -#ifdef CONFIG_STM32L4_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH4POL, - .idle = CONFIG_STM32L4_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -821,159 +821,159 @@ static struct stm32l4_pwmchan_s g_pwm5channels[] = static struct stm32l4_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32L4_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM5_TRGO) - .trgo = STM32L4_TIM5_TRGO +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO #endif - .base = STM32L4_TIM5_BASE, - .pclk = STM32L4_APB1_TIM5_CLKIN, + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32l4_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM8_BREAK1 +#ifdef CONFIG_STM32_TIM8_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM8_BRK1POL, + .pol1 = CONFIG_STM32_TIM8_BRK1POL, #endif -#ifdef CONFIG_STM32L4_TIM8_BREAK2 +#ifdef CONFIG_STM32_TIM8_BREAK2 .en2 = 1, - .pol2 = CONFIG_STM32L4_TIM8_BRK2POL, - .flt2 = CONFIG_STM32L4_TIM8_BRK2FLT, + .pol2 = CONFIG_STM32_TIM8_BRK2POL, + .flt2 = CONFIG_STM32_TIM8_BRK2FLT, #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1POL, - .idle = CONFIG_STM32L4_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1NPOL, - .idle = CONFIG_STM32L4_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM8_CH2MODE, -#ifdef CONFIG_STM32L4_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2POL, - .idle = CONFIG_STM32L4_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2NPOL, - .idle = CONFIG_STM32L4_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM8_CH3MODE, -#ifdef CONFIG_STM32L4_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3POL, - .idle = CONFIG_STM32L4_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3NPOL, - .idle = CONFIG_STM32L4_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM8_CH4MODE, -#ifdef CONFIG_STM32L4_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH4POL, - .idle = CONFIG_STM32L4_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM8_CH5MODE, -#ifdef CONFIG_STM32L4_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH5POL, - .idle = CONFIG_STM32L4_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM8_CH6MODE, -#ifdef CONFIG_STM32L4_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH6POL, - .idle = CONFIG_STM32L4_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -984,77 +984,77 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = static struct stm32l4_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32L4_TIM8_MODE, - .lock = CONFIG_STM32L4_TIM8_LOCK, - .t_dts = CONFIG_STM32L4_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM8_TRGO) - .trgo = STM32L4_TIM8_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, #endif - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32l4_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM15_BREAK1 +#ifdef CONFIG_STM32_TIM15_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM15_BRK1POL, + .pol1 = CONFIG_STM32_TIM15_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1POL, - .idle = CONFIG_STM32L4_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1NPOL, - .idle = CONFIG_STM32L4_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM15_CH2MODE, -#ifdef CONFIG_STM32L4_TIM15_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM15_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH2POL, - .idle = CONFIG_STM32L4_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1066,62 +1066,62 @@ static struct stm32l4_pwmchan_s g_pwm15channels[] = static struct stm32l4_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, .chan_num = PWM_TIM15_NCHANNELS, .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM15_LOCK, - .t_dts = CONFIG_STM32L4_TIM15_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM15_TRGO) - .trgo = STM32L4_TIM15_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, #endif - .base = STM32L4_TIM15_BASE, - .pclk = STM32L4_APB2_TIM15_CLKIN, + .base = STM32_TIM15_BASE, + .pclk = STM32_APB2_TIM15_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32l4_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM16_BREAK1 +#ifdef CONFIG_STM32_TIM16_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM16_BRK1POL, + .pol1 = CONFIG_STM32_TIM16_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM16_CH1POL, - .idle = CONFIG_STM32L4_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM16_CH1NPOL, - .idle = CONFIG_STM32L4_TIM16_CH1NIDLE, + .pol = CONFIG_STM32_TIM16_CH1NPOL, + .idle = CONFIG_STM32_TIM16_CH1NIDLE, .pincfg = PWM_TIM16_CH2CFG, } #endif @@ -1132,62 +1132,62 @@ static struct stm32l4_pwmchan_s g_pwm16channels[] = static struct stm32l4_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, .chan_num = PWM_TIM16_NCHANNELS, .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM16_LOCK, - .t_dts = CONFIG_STM32L4_TIM16_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ #endif - .base = STM32L4_TIM16_BASE, - .pclk = STM32L4_APB2_TIM16_CLKIN, + .base = STM32_TIM16_BASE, + .pclk = STM32_APB2_TIM16_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32l4_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { -#ifdef CONFIG_STM32L4_TIM17_BREAK1 +#ifdef CONFIG_STM32_TIM17_BREAK1 .en1 = 1, - .pol1 = CONFIG_STM32L4_TIM17_BRK1POL, + .pol1 = CONFIG_STM32_TIM17_BRK1POL, #endif /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM17_CH1POL, - .idle = CONFIG_STM32L4_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM17_CH1NPOL, - .idle = CONFIG_STM32L4_TIM17_CH1NIDLE, + .pol = CONFIG_STM32_TIM17_CH1NPOL, + .idle = CONFIG_STM32_TIM17_CH1NIDLE, .pincfg = PWM_TIM17_CH2CFG, } #endif @@ -1198,42 +1198,42 @@ static struct stm32l4_pwmchan_s g_pwm17channels[] = static struct stm32l4_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, .chan_num = PWM_TIM17_NCHANNELS, .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, - .mode = STM32L4_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM17_LOCK, - .t_dts = CONFIG_STM32L4_TIM17_TDTS, + .mode = STM32_TIMMODE_COUNTUP, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ #endif - .base = STM32L4_TIM17_BASE, - .pclk = STM32L4_APB2_TIM17_CLKIN, + .base = STM32_TIM17_BASE, + .pclk = STM32_APB2_TIM17_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM static struct stm32l4_pwmchan_s g_pwmlp1channels[] = { /* LPTIM1 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CH1OUT .out1 = { .in_use = 1, - .pol = 0, /* REVISIT: Configure using CONFIG_STM32L4_LPTIM1_CH1POL, */ + .pol = 0, /* REVISIT: Configure using CONFIG_STM32_LPTIM1_CH1POL, */ .idle = 0, /* No idle */ .pincfg = PWM_LPTIM1_CH1CFG, } @@ -1246,14 +1246,14 @@ static struct stm32l4_pwmchan_s g_pwmlp1channels[] = static struct stm32l4_pwmtimer_s g_pwmlp1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_LPTIM1_NCHANNELS, .channels = g_pwmlp1channels, .timtype = TIMTYPE_LPTIM1, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1262,34 +1262,34 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM1 */ #endif - .base = STM32L4_LPTIM1_BASE, -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .base = STM32_LPTIM1_BASE, +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) + .pclk = STM32_PCLK1_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) + .pclk = STM32_LSE_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) + .pclk = STM32_LSI_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) + .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM1_PWM */ +#endif /* CONFIG_STM32_LPTIM1_PWM */ -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM static struct stm32l4_pwmchan_s g_pwmlp2channels[] = { /* LPTIM2 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CH1OUT .out1 = { .in_use = 1, - .pol = 0, /* REVISIT: Configure using CONFIG_STM32L4_LPTIM2_CH1POL, */ + .pol = 0, /* REVISIT: Configure using CONFIG_STM32_LPTIM2_CH1POL, */ .idle = 0, /* No idle */ .pincfg = PWM_LPTIM2_CH1CFG, } @@ -1302,14 +1302,14 @@ static struct stm32l4_pwmchan_s g_pwmlp2channels[] = static struct stm32l4_pwmtimer_s g_pwmlp2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_LPTIM2_NCHANNELS, .channels = g_pwmlp2channels, .timtype = TIMTYPE_LPTIM2, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1318,18 +1318,18 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM2 */ #endif - .base = STM32L4_LPTIM2_BASE, -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .base = STM32_LPTIM2_BASE, +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) + .pclk = STM32_PCLK1_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) + .pclk = STM32_LSE_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) + .pclk = STM32_LSI_FREQUENCY, +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) + .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM2_PWM */ +#endif /* CONFIG_STM32_LPTIM2_PWM */ /**************************************************************************** * Private Functions @@ -1374,12 +1374,12 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1416,12 +1416,12 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1462,52 +1462,52 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, { pwminfo("%s:\n", msg); pwminfo(" CFGR: %04x CR: %04x CMP: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CMP_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CMP_OFFSET), + pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET)); pwminfo(" ISR: %04x CNT: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_ISR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CNT_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_ISR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CNT_OFFSET)); } else { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } } @@ -1528,7 +1528,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, { /* REVISIT: What about index? Is it necessary for LPTIM? */ - offset = STM32L4_LPTIM_CMP_OFFSET; + offset = STM32_LPTIM_CMP_OFFSET; pwm_putreg(priv, offset, ccr); return OK; @@ -1547,39 +1547,39 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1601,7 +1601,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; @@ -1609,39 +1609,39 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1656,7 +1656,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1670,11 +1670,11 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) if (priv->timtype == TIMTYPE_LOWPOWER) { - pwm_putreg(priv, STM32L4_LPTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_LPTIM_ARR_OFFSET, arr); } else { - pwm_putreg(priv, STM32L4_GTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); } return OK; @@ -1690,11 +1690,11 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) if (priv->timtype == TIMTYPE_LOWPOWER) { - return pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET); } else { - return pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); } } @@ -1730,6 +1730,11 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(channel == priv->channels[0].channel); + DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); +#endif + /* Get the reload values */ reload = pwm_arr_get(dev); @@ -1766,13 +1771,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } #ifdef HAVE_LPTIM } @@ -1782,13 +1787,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); } } #endif @@ -1849,9 +1854,9 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, * intended so multiply by x2 */ - if ((priv->mode == STM32L4_TIMMODE_CENTER1) || - (priv->mode == STM32L4_TIMMODE_CENTER2) || - (priv->mode == STM32L4_TIMMODE_CENTER3)) + if ((priv->mode == STM32_TIMMODE_CENTER1) || + (priv->mode == STM32_TIMMODE_CENTER2) || + (priv->mode == STM32_TIMMODE_CENTER3)) { frequency = frequency * 2; } @@ -1889,7 +1894,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the reload and prescaler values */ pwm_arr_update(dev, reload); - pwm_putreg(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; } @@ -1961,12 +1966,12 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the prescaler value */ - cfgr = pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET); + cfgr = pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET); cfgr &= ~LPTIM_CFGR_PRESC_MASK; cfgr |= (prescaler << LPTIM_CFGR_PRESC_SHIFT); - pwm_putreg(priv, STM32L4_LPTIM_CFGR_OFFSET, cfgr); + pwm_putreg(priv, STM32_LPTIM_CFGR_OFFSET, cfgr); return OK; } @@ -1994,7 +1999,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ - cr1 = pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Set the counter mode for the advanced timers (1,8) and most general * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 @@ -2016,31 +2021,31 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) switch (priv->mode) { - case STM32L4_TIMMODE_COUNTUP: + case STM32_TIMMODE_COUNTUP: { cr1 |= GTIM_CR1_EDGE; break; } - case STM32L4_TIMMODE_COUNTDOWN: + case STM32_TIMMODE_COUNTDOWN: { cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; break; } - case STM32L4_TIMMODE_CENTER1: + case STM32_TIMMODE_CENTER1: { cr1 |= GTIM_CR1_CENTER1; break; } - case STM32L4_TIMMODE_CENTER2: + case STM32_TIMMODE_CENTER2: { cr1 |= GTIM_CR1_CENTER2; break; } - case STM32L4_TIMMODE_CENTER3: + case STM32_TIMMODE_CENTER3: { cr1 |= GTIM_CR1_CENTER3; break; @@ -2064,7 +2069,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) /* Write CR1 */ - pwm_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); errout: return ret; @@ -2104,76 +2109,76 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, switch (mode) { - case STM32L4_CHANMODE_FRZN: + case STM32_CHANMODE_FRZN: { chanmode = GTIM_CCMR_MODE_FRZN; break; } - case STM32L4_CHANMODE_CHACT: + case STM32_CHANMODE_CHACT: { chanmode = GTIM_CCMR_MODE_CHACT; break; } - case STM32L4_CHANMODE_CHINACT: + case STM32_CHANMODE_CHINACT: { chanmode = GTIM_CCMR_MODE_CHINACT; break; } - case STM32L4_CHANMODE_OCREFTOG: + case STM32_CHANMODE_OCREFTOG: { chanmode = GTIM_CCMR_MODE_OCREFTOG; break; } - case STM32L4_CHANMODE_OCREFLO: + case STM32_CHANMODE_OCREFLO: { chanmode = GTIM_CCMR_MODE_OCREFLO; break; } - case STM32L4_CHANMODE_OCREFHI: + case STM32_CHANMODE_OCREFHI: { chanmode = GTIM_CCMR_MODE_OCREFHI; break; } - case STM32L4_CHANMODE_PWM1: + case STM32_CHANMODE_PWM1: { chanmode = GTIM_CCMR_MODE_PWM1; break; } - case STM32L4_CHANMODE_PWM2: + case STM32_CHANMODE_PWM2: { chanmode = GTIM_CCMR_MODE_PWM2; break; } - case STM32L4_CHANMODE_COMBINED1: + case STM32_CHANMODE_COMBINED1: { chanmode = ATIM_CCMR_MODE_COMBINED1; ocmbit = true; break; } - case STM32L4_CHANMODE_COMBINED2: + case STM32_CHANMODE_COMBINED2: { chanmode = ATIM_CCMR_MODE_COMBINED2; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC1: + case STM32_CHANMODE_ASYMMETRIC1: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC2: + case STM32_CHANMODE_ASYMMETRIC2: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; ocmbit = true; @@ -2194,24 +2199,24 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Get CCMR offset */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } - case STM32L4_PWM_CHAN5: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCMR3_OFFSET; + offset = STM32_ATIM_CCMR3_OFFSET; break; } @@ -2235,9 +2240,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Configure channel 1/3/5 */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN5: { /* Reset current channel 1/3/5 mode configuration */ @@ -2271,9 +2276,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, /* Configure channel 2/4/6 */ - case STM32L4_PWM_CHAN2: - case STM32L4_PWM_CHAN4: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: + case STM32_PWM_CHAN6: { /* Reset current channel 2/4/6 mode configuration */ @@ -2334,8 +2339,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Get current registers state */ - cr2 = pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register * | CCxP/CCxNP | POL | all PWM timers | CCER register @@ -2343,7 +2348,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure output polarity (all PWM timers) */ - if (priv->channels[channel - 1].out1.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG) { ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); } @@ -2358,7 +2363,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, { /* Configure output IDLE State */ - if (priv->channels[channel - 1].out1.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); } @@ -2370,7 +2375,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, #ifdef HAVE_PWM_COMPLEMENTARY /* Configure complementary output IDLE state */ - if (priv->channels[channel - 1].out2.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); } @@ -2381,7 +2386,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure complementary output polarity */ - if (priv->channels[channel - 1].out2.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG) { ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); } @@ -2417,8 +2422,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Write registers */ - pwm_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pwm_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -2448,23 +2453,23 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Get current register state */ - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ - regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ - regval |= ((outputs & STM32L4_PWM_OUT5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32L4_PWM_OUT6) ? ATIM_CCER_CC6E : 0); + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); if (state == true) { @@ -2481,12 +2486,12 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Write register */ - pwm_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -2508,7 +2513,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Get current register state */ - bdtr = pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); /* TODO: check if BDTR not locked */ @@ -2519,7 +2524,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Write BDTR register */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); errout: return ret; @@ -2538,7 +2543,7 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; - pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -2565,13 +2570,13 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { /* Reset MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } else { /* Set MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } return OK; @@ -2606,7 +2611,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out1.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1 << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -2614,7 +2619,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out2.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1N << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); } #endif } @@ -2644,7 +2649,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) * should be no basic timers in this context */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, priv->t_dts << GTIM_CR1_CKD_SHIFT); #ifdef HAVE_PWM_COMPLEMENTARY @@ -2664,7 +2669,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 1 polarity */ - bdtr |= (priv->brk.pol1 == STM32L4_POL_NEG ? ATIM_BDTR_BKP : 0); + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); } /* Configure Break 1 */ @@ -2677,7 +2682,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 2 polarity */ - bdtr |= (priv->brk.pol2 == STM32L4_POL_NEG ? ATIM_BDTR_BK2P : 0); + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); /* Configure BRK2 filter */ @@ -2699,7 +2704,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Write BDTR register at once */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); return OK; } @@ -2844,11 +2849,16 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; +#ifdef CONFIG_STM32_PWM_MULTICHAN int i = 0; int j = 0; +#endif +#ifdef CONFIG_STM32_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) +#endif { +#ifdef CONFIG_STM32_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -2881,6 +2891,10 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } +#else + duty = info->channels[0].duty; + channel = priv->channels[0].channel; +#endif /* Update duty cycle */ @@ -2889,7 +2903,9 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } +#ifdef CONFIG_STM32_PWM_MULTICHAN } +#endif } errout: @@ -2920,10 +2936,20 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); +#if defined(CONFIG_STM32_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); +#else + pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", + priv->timid, priv->channels[0].channel, + info->frequency, info->channels[0].duty); +#endif DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(info->channels[0].duty >= 0 && + info->channels[0].duty < uitoub16(100)); +#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -2956,7 +2982,7 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3018,10 +3044,20 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); +#if defined(CONFIG_STM32_PWM_MULTICHAN) pwminfo("LPTIM%u frequency: %u\n", priv->timid, info->frequency); +#else + pwminfo("LPTIM%u channel: %u frequency: %u duty: %08x\n", + priv->timid, priv->channels[0].channel, + info->frequency, info->channels[0].duty); +#endif DEBUGASSERT(info->frequency > 0); +#ifndef CONFIG_STM32_PWM_MULTICHAN + DEBUGASSERT(info->channels[0].duty >= 0 && + info->channels[0].duty < uitoub16(100)); +#endif /* Enable again, ARR and CMP need to be written while enabled */ @@ -3035,7 +3071,11 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, goto errout; } +#ifdef CONFIG_STM32_PWM_MULTICHAN ub16_t duty = info->channels[0].duty; +#else + ub16_t duty = info->channels[0].duty; +#endif /* Update duty cycle */ @@ -3047,9 +3087,9 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, /* Start counter */ - cr = pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET); + cr = pwm_getreg(priv, STM32_LPTIM_CR_OFFSET); cr |= LPTIM_CR_CNTSTRT; - pwm_putreg(priv, STM32L4_LPTIM_CR_OFFSET, cr); + pwm_putreg(priv, STM32_LPTIM_CR_OFFSET, cr); pwm_dumpregs(dev, "After starting"); @@ -3083,82 +3123,82 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM2EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM3EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM4EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM5EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; } #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; break; } @@ -3190,67 +3230,67 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: { -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) /* Enable APB clock for LPTIM1 */ if (on) { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); } clock_bits = RCC_CCIPR_LPTIM1SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM1SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM1SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM1SEL_HSI; #endif /* Choose which clock will be used for LPTIM1 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, clock_bits); break; } #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: { -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) /* Enable APB clock for LPTIM2 */ if (on) { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); } clock_bits = RCC_CCIPR_LPTIM2SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM2SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM2SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM2SEL_HSI; #endif /* Choose which clock will be used for LPTIM2 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, clock_bits); break; } @@ -3455,6 +3495,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { +#ifdef CONFIG_STM32_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -3474,6 +3515,10 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } +#else + ret = pwm_duty_update(dev, priv->channels[0].channel, + info->channels[0].duty); +#endif /* CONFIG_STM32_PWM_MULTICHAN */ } else { @@ -3541,51 +3586,51 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; break; #endif @@ -3597,15 +3642,15 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_LPTIM1RST; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR2; + regaddr = STM32_RCC_APB1RSTR2; resetbit = RCC_APB1RSTR2_LPTIM2RST; break; #endif @@ -3626,8 +3671,8 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pwm_start() can be called. @@ -3705,7 +3750,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: lower = &g_pwm1dev; @@ -3714,31 +3759,31 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: lower = &g_pwm2dev; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: lower = &g_pwm3dev; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: lower = &g_pwm4dev; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: lower = &g_pwm5dev; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: lower = &g_pwm8dev; @@ -3747,19 +3792,19 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: lower = &g_pwm15dev; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: lower = &g_pwm16dev; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: lower = &g_pwm17dev; break; @@ -3799,13 +3844,13 @@ struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: lower = &g_pwmlp1dev; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: lower = &g_pwmlp2dev; break; @@ -3820,4 +3865,4 @@ struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) } #endif /* HAVE_LPTIM */ -#endif /* CONFIG_STM32L4_TIMn_PWM, n = 1,...,17 */ +#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,17 */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 14c75affd5f17..a55d6e48a3be8 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PWM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PWM_H /* The STM32L4 does not have dedicated PWM hardware. Rather, pulsed output * control is a capability of the STM32L4 timers. The logic in this file @@ -50,72 +50,72 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM must also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must also * be defined to indicate that timer "n" is intended to be used for pulsed * output signal generation. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32L4_TIM17 -# undef CONFIG_STM32L4_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM1 -# undef CONFIG_STM32L4_LPTIM1_PWM +#ifndef CONFIG_STM32_LPTIM1 +# undef CONFIG_STM32_LPTIM1_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM2 -# undef CONFIG_STM32L4_LPTIM2_PWM +#ifndef CONFIG_STM32_LPTIM2 +# undef CONFIG_STM32_LPTIM2_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output * pulses. */ -#undef CONFIG_STM32L4_TIM6_PWM -#undef CONFIG_STM32L4_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /* PWM driver channels configuration */ -#ifdef CONFIG_STM32L4_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # else # define PWM_TIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 @@ -124,13 +124,13 @@ #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # else # define PWM_TIM1_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 @@ -139,13 +139,13 @@ #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # else # define PWM_TIM1_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 @@ -154,8 +154,8 @@ #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # define PWM_TIM1_CH4CFG 0 @@ -167,8 +167,8 @@ #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # else # define PWM_TIM2_CH1CFG 0 @@ -177,8 +177,8 @@ #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # else # define PWM_TIM2_CH2CFG 0 @@ -187,8 +187,8 @@ #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # else # define PWM_TIM2_CH3CFG 0 @@ -197,8 +197,8 @@ #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # define PWM_TIM2_CH4CFG 0 @@ -210,8 +210,8 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # else # define PWM_TIM3_CH1CFG 0 @@ -220,8 +220,8 @@ #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # else # define PWM_TIM3_CH2CFG 0 @@ -230,8 +230,8 @@ #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # else # define PWM_TIM3_CH3CFG 0 @@ -240,8 +240,8 @@ #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # define PWM_TIM3_CH4CFG 0 @@ -253,8 +253,8 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT # else # define PWM_TIM4_CH1CFG 0 @@ -263,8 +263,8 @@ #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT # else # define PWM_TIM4_CH2CFG 0 @@ -273,8 +273,8 @@ #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT # else # define PWM_TIM4_CH3CFG 0 @@ -283,8 +283,8 @@ #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else # define PWM_TIM4_CH4CFG 0 @@ -296,8 +296,8 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT # else # define PWM_TIM5_CH1CFG 0 @@ -306,8 +306,8 @@ #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT # else # define PWM_TIM5_CH2CFG 0 @@ -316,8 +316,8 @@ #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT # else # define PWM_TIM5_CH3CFG 0 @@ -326,8 +326,8 @@ #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else # define PWM_TIM5_CH4CFG 0 @@ -339,13 +339,13 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # else # define PWM_TIM8_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT # else # define PWM_TIM8_CH1NCFG 0 @@ -354,13 +354,13 @@ #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # else # define PWM_TIM8_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH2NOUT +# ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT # else # define PWM_TIM8_CH2NCFG 0 @@ -369,13 +369,13 @@ #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # else # define PWM_TIM8_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH3NOUT +# ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT # else # define PWM_TIM8_CH3NCFG 0 @@ -384,8 +384,8 @@ #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else # define PWM_TIM8_CH4CFG 0 @@ -397,13 +397,13 @@ #define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # else # define PWM_TIM15_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM15_CH1NOUT +# ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT # else # define PWM_TIM15_CH1NCFG 0 @@ -412,8 +412,8 @@ #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else # define PWM_TIM15_CH2CFG 0 @@ -424,13 +424,13 @@ #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # else # define PWM_TIM16_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM16_CH1NOUT +# ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT # else # define PWM_TIM16_CH1NCFG 0 @@ -441,13 +441,13 @@ #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # else # define PWM_TIM17_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM17_CH1NOUT +# ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT # else # define PWM_TIM17_CH1NCFG 0 @@ -458,13 +458,13 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # else # define PWM_LPTIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM1_CH1NOUT +# ifdef CONFIG_STM32_LPTIM1_CH1NOUT # define PWM_LPTIM1_CH1NCFG GPIO_LPTIM1_CH1NOUT # else # define PWM_LPTIM1_CH1NCFG 0 @@ -475,13 +475,13 @@ #endif #define PWM_LPTIM1_NCHANNELS PWM_LPTIM1_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # else # define PWM_LPTIM2_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM2_CH1NOUT +# ifdef CONFIG_STM32_LPTIM2_CH1NOUT # define PWM_LPTIM2_CH1NCFG GPIO_LPTIM2_CH1NOUT # else # define PWM_LPTIM2_CH1NCFG 0 @@ -492,12 +492,12 @@ #endif #define PWM_LPTIM2_NCHANNELS PWM_LPTIM2_CHANNEL1 -#else /* !CONFIG_STM32L4_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32L4_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -510,250 +510,250 @@ * Only one output channel per timer. */ -#ifdef CONFIG_STM32L4_TIM1_PWM -# if !defined(CONFIG_STM32L4_TIM1_CHANNEL) -# error "CONFIG_STM32L4_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM1_CHANNEL == 1 -# define CONFIG_STM32L4_TIM1_CHANNEL1 1 -# define CONFIG_STM32L4_TIM1_CH1MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 2 -# define CONFIG_STM32L4_TIM1_CHANNEL2 1 -# define CONFIG_STM32L4_TIM1_CH2MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 3 -# define CONFIG_STM32L4_TIM1_CHANNEL3 1 -# define CONFIG_STM32L4_TIM1_CH3MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 4 -# define CONFIG_STM32L4_TIM1_CHANNEL4 1 -# define CONFIG_STM32L4_TIM1_CH4MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # endif # else -# error "Unsupported value of CONFIG_STM32L4_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM2_PWM -# if !defined(CONFIG_STM32L4_TIM2_CHANNEL) -# error "CONFIG_STM32L4_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM2_CHANNEL == 1 -# define CONFIG_STM32L4_TIM2_CHANNEL1 1 -# define CONFIG_STM32L4_TIM2_CH1MODE CONFIG_STM32L4_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 2 -# define CONFIG_STM32L4_TIM2_CHANNEL2 1 -# define CONFIG_STM32L4_TIM2_CH2MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 3 -# define CONFIG_STM32L4_TIM2_CHANNEL3 1 -# define CONFIG_STM32L4_TIM2_CH3MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 4 -# define CONFIG_STM32L4_TIM2_CHANNEL4 1 -# define CONFIG_STM32L4_TIM2_CH4MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM3_PWM -# if !defined(CONFIG_STM32L4_TIM3_CHANNEL) -# error "CONFIG_STM32L4_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM3_CHANNEL == 1 -# define CONFIG_STM32L4_TIM3_CHANNEL1 1 -# define CONFIG_STM32L4_TIM3_CH1MODE CONFIG_STM32L4_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 2 -# define CONFIG_STM32L4_TIM3_CHANNEL2 1 -# define CONFIG_STM32L4_TIM3_CH2MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 3 -# define CONFIG_STM32L4_TIM3_CHANNEL3 1 -# define CONFIG_STM32L4_TIM3_CH3MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 4 -# define CONFIG_STM32L4_TIM3_CHANNEL4 1 -# define CONFIG_STM32L4_TIM3_CH4MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM4_PWM -# if !defined(CONFIG_STM32L4_TIM4_CHANNEL) -# error "CONFIG_STM32L4_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM4_CHANNEL == 1 -# define CONFIG_STM32L4_TIM4_CHANNEL1 1 -# define CONFIG_STM32L4_TIM4_CH1MODE CONFIG_STM32L4_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 2 -# define CONFIG_STM32L4_TIM4_CHANNEL2 1 -# define CONFIG_STM32L4_TIM4_CH2MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 3 -# define CONFIG_STM32L4_TIM4_CHANNEL3 1 -# define CONFIG_STM32L4_TIM4_CH3MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 4 -# define CONFIG_STM32L4_TIM4_CHANNEL4 1 -# define CONFIG_STM32L4_TIM4_CH4MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM5_PWM -# if !defined(CONFIG_STM32L4_TIM5_CHANNEL) -# error "CONFIG_STM32L4_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM5_CHANNEL == 1 -# define CONFIG_STM32L4_TIM5_CHANNEL1 1 -# define CONFIG_STM32L4_TIM5_CH1MODE CONFIG_STM32L4_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 2 -# define CONFIG_STM32L4_TIM5_CHANNEL2 1 -# define CONFIG_STM32L4_TIM5_CH2MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 3 -# define CONFIG_STM32L4_TIM5_CHANNEL3 1 -# define CONFIG_STM32L4_TIM5_CH3MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 4 -# define CONFIG_STM32L4_TIM5_CHANNEL4 1 -# define CONFIG_STM32L4_TIM5_CH4MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM8_PWM -# if !defined(CONFIG_STM32L4_TIM8_CHANNEL) -# error "CONFIG_STM32L4_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM8_CHANNEL == 1 -# define CONFIG_STM32L4_TIM8_CHANNEL1 1 -# define CONFIG_STM32L4_TIM8_CH1MODE CONFIG_STM32L4_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 2 -# define CONFIG_STM32L4_TIM8_CHANNEL2 1 -# define CONFIG_STM32L4_TIM8_CH2MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # define PWM_TIM8_CH2NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 3 -# define CONFIG_STM32L4_TIM8_CHANNEL3 1 -# define CONFIG_STM32L4_TIM8_CH3MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # define PWM_TIM8_CH3NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 4 -# define CONFIG_STM32L4_TIM8_CHANNEL4 1 -# define CONFIG_STM32L4_TIM8_CH4MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM15_PWM -# if !defined(CONFIG_STM32L4_TIM15_CHANNEL) -# error "CONFIG_STM32L4_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM15_CHANNEL == 1 -# define CONFIG_STM32L4_TIM15_CHANNEL1 1 -# define CONFIG_STM32L4_TIM15_CH1MODE CONFIG_STM32L4_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM15_CHANNEL == 2 -# define CONFIG_STM32L4_TIM15_CHANNEL2 1 -# define CONFIG_STM32L4_TIM15_CH2MODE CONFIG_STM32L4_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM16_PWM -# if !defined(CONFIG_STM32L4_TIM16_CHANNEL) -# error "CONFIG_STM32L4_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM16_CHANNEL == 1 -# define CONFIG_STM32L4_TIM16_CHANNEL1 1 -# define CONFIG_STM32L4_TIM16_CH1MODE CONFIG_STM32L4_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # define PWM_TIM16_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM17_PWM -# if !defined(CONFIG_STM32L4_TIM17_CHANNEL) -# error "CONFIG_STM32L4_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM17_CHANNEL == 1 -# define CONFIG_STM32L4_TIM17_CHANNEL1 1 -# define CONFIG_STM32L4_TIM17_CH1MODE CONFIG_STM32L4_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # define PWM_TIM17_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM1_PWM -# if !defined(CONFIG_STM32L4_LPTIM1_CHANNEL) -# error "CONFIG_STM32L4_LPTIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM1_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM1_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM1_PWM +# if !defined(CONFIG_STM32_LPTIM1_CHANNEL) +# error "CONFIG_STM32_LPTIM1_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM1_CHANNEL == 1 +# define CONFIG_STM32_LPTIM1_CHANNEL1 1 # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM1_CHANNEL" # endif # define PWM_LPTIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM -# if !defined(CONFIG_STM32L4_LPTIM2_CHANNEL) -# error "CONFIG_STM32L4_LPTIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM2_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM2_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM2_PWM +# if !defined(CONFIG_STM32_LPTIM2_CHANNEL) +# error "CONFIG_STM32_LPTIM2_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM2_CHANNEL == 1 +# define CONFIG_STM32_LPTIM2_CHANNEL1 1 # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM2_CHANNEL" # endif # define PWM_LPTIM2_NCHANNELS 1 #endif @@ -762,27 +762,27 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32L4_TIM1_CH1NOUT) || defined(CONFIG_STM32L4_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM8_CH1NOUT) || defined(CONFIG_STM32L4_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM1_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM1_CH1NOUT) # define HAVE_LPTIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM2_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM2_CH1NOUT) # define HAVE_LPTIM2_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -794,7 +794,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops * access can be found in stm32l4_pwm_dev_s @@ -826,7 +826,7 @@ (dev)->llops->freq_update((struct pwm_lowerhalf_s *)dev, freq) #define PWM_TIM_ENABLE(dev, state) \ (dev)->llops->tim_enable((struct pwm_lowerhalf_s *)dev, state) -#ifdef CONFIG_DEBUG_STM32L4_PWM_INFO +#ifdef CONFIG_DEBUG_STM32_PWM_INFO # define PWM_DUMP_REGS(dev, msg) \ (dev)->llops->dump_regs((struct pwm_lowerhalf_s *)dev, msg) #else @@ -844,85 +844,85 @@ enum stm32l4_timmode_e { - STM32L4_TIMMODE_COUNTUP = 0, - STM32L4_TIMMODE_COUNTDOWN = 1, - STM32L4_TIMMODE_CENTER1 = 2, - STM32L4_TIMMODE_CENTER2 = 3, - STM32L4_TIMMODE_CENTER3 = 4, + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, }; /* Timer output polarity */ enum stm32l4_pwm_pol_e { - STM32L4_POL_POS = 0, - STM32L4_POL_NEG = 1, + STM32_POL_POS = 0, + STM32_POL_NEG = 1, }; /* Timer output IDLE state */ enum stm32l4_pwm_idle_e { - STM32L4_IDLE_INACTIVE = 0, - STM32L4_IDLE_ACTIVE = 1 + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 }; /* PWM channel mode */ enum stm32l4_chanmode_e { - STM32L4_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ - STM32L4_CHANMODE_CHACT = 1, /* OCxREF active on match */ - STM32L4_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ - STM32L4_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ - STM32L4_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ - STM32L4_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ - STM32L4_CHANMODE_PWM1 = 6, /* PWM mode 1 */ - STM32L4_CHANMODE_PWM2 = 7, /* PWM mode 2 */ - STM32L4_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ - STM32L4_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ - STM32L4_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ - STM32L4_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ }; /* PWM timer channel */ enum stm32l4_pwm_chan_e { - STM32L4_PWM_CHAN1 = 1, - STM32L4_PWM_CHAN2 = 2, - STM32L4_PWM_CHAN3 = 3, - STM32L4_PWM_CHAN4 = 4, - STM32L4_PWM_CHAN5 = 5, - STM32L4_PWM_CHAN6 = 6, + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, }; /* PWM timer channel output */ enum stm32l4_pwm_output_e { - STM32L4_PWM_OUT1 = (1 << 0), - STM32L4_PWM_OUT1N = (1 << 1), - STM32L4_PWM_OUT2 = (1 << 2), - STM32L4_PWM_OUT2N = (1 << 3), - STM32L4_PWM_OUT3 = (1 << 4), - STM32L4_PWM_OUT3N = (1 << 5), - STM32L4_PWM_OUT4 = (1 << 6), + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), /* 1 << 7 reserved - no complementary output for CH4 */ /* Only available inside micro */ - STM32L4_PWM_OUT5 = (1 << 8), + STM32_PWM_OUT5 = (1 << 8), /* 1 << 9 reserved - no complementary output for CH5 */ - STM32L4_PWM_OUT6 = (1 << 10), + STM32_PWM_OUT6 = (1 << 10), /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1008,7 +1008,7 @@ struct stm32l4_pwm_ops_s #endif }; -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1073,5 +1073,5 @@ struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_TIMx_PWM */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H */ +#endif /* CONFIG_STM32_TIMx_PWM */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PWM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index cd78d8d6d436d..6ace61ca5aaf2 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l4_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l4_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l4_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l4_pwr_enableusv(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -221,14 +221,14 @@ bool stm32l4_pwr_enableusv(bool set) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32l4_pwr_enable_pvme2(bool set) { uint32_t regval; bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -238,7 +238,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,14 +248,14 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -283,7 +283,7 @@ bool stm32l4_pwr_get_pvmo2(void) uint32_t regval; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -293,7 +293,7 @@ bool stm32l4_pwr_get_pvmo2(void) /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_SR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { @@ -325,7 +325,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -335,7 +335,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,14 +345,14 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -392,7 +392,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -404,5 +404,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 0208128cae8f4..84c1232980bbd 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L4_STM32_PWR_H /**************************************************************************** * Included Files @@ -121,7 +121,7 @@ bool stm32l4_pwr_enableusv(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32l4_pwr_enable_pvme2(bool set); #endif @@ -137,7 +137,7 @@ bool stm32l4_pwr_enable_pvme2(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32l4_pwr_get_pvmo2(void); #endif @@ -156,7 +156,7 @@ bool stm32l4_pwr_get_pvmo2(void); * True: The bit was previously set. ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32l4_pwr_vddio2_valid(bool set); #endif @@ -187,4 +187,4 @@ void stm32_pwr_setvos(int vos); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 7f12c3b3990b8..71580be5e2b90 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -62,14 +62,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32L4_TIM2_QE) || defined(CONFIG_STM32L4_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM3_QE) || \ - defined(CONFIG_STM32L4_TIM4_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -91,65 +91,65 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32L4_QENCODER_FILTER -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32L4_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32L4_QENCODER_ICF -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -271,16 +271,16 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32l4_qeconfig_s g_tim1config = { .timid = 1, - .irq = STM32L4_IRQ_TIM1UP, + .irq = STM32_IRQ_TIM1UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif - .base = STM32L4_TIM1_BASE, - .psc = CONFIG_STM32L4_TIM1_QEPSC, + .base = STM32_TIM1_BASE, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -295,16 +295,16 @@ static struct stm32l4_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32l4_qeconfig_s g_tim2config = { .timid = 2, - .irq = STM32L4_IRQ_TIM2, + .irq = STM32_IRQ_TIM2, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM2_BITWIDTH, #endif - .base = STM32L4_TIM2_BASE, - .psc = CONFIG_STM32L4_TIM2_QEPSC, + .base = STM32_TIM2_BASE, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -319,16 +319,16 @@ static struct stm32l4_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32l4_qeconfig_s g_tim3config = { .timid = 3, - .irq = STM32L4_IRQ_TIM3, + .irq = STM32_IRQ_TIM3, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM3_BITWIDTH, #endif - .base = STM32L4_TIM3_BASE, - .psc = CONFIG_STM32L4_TIM3_QEPSC, + .base = STM32_TIM3_BASE, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -343,16 +343,16 @@ static struct stm32l4_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32l4_qeconfig_s g_tim4config = { .timid = 4, - .irq = STM32L4_IRQ_TIM4, + .irq = STM32_IRQ_TIM4, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM4_BITWIDTH, #endif - .base = STM32L4_TIM4_BASE, - .psc = CONFIG_STM32L4_TIM4_QEPSC, + .base = STM32_TIM4_BASE, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -367,16 +367,16 @@ static struct stm32l4_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32l4_qeconfig_s g_tim5config = { .timid = 5, - .irq = STM32L4_IRQ_TIM5, + .irq = STM32_IRQ_TIM5, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM5_BITWIDTH, #endif - .base = STM32L4_TIM5_BASE, - .psc = CONFIG_STM32L4_TIM5_QEPSC, + .base = STM32_TIM5_BASE, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -391,16 +391,16 @@ static struct stm32l4_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32l4_qeconfig_s g_tim8config = { .timid = 8, - .irq = STM32L4_IRQ_TIM8UP, + .irq = STM32_IRQ_TIM8UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM8_BITWIDTH, #endif - .base = STM32L4_TIM8_BASE, - .psc = CONFIG_STM32L4_TIM8_QEPSC, + .base = STM32_TIM8_BASE, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -531,43 +531,43 @@ static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET)); + stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) + stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -584,27 +584,27 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -737,14 +737,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ stm32l4_putreg16(priv, - STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,7 +752,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ @@ -761,27 +761,27 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -790,34 +790,34 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,22 +886,22 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); stm32l4_dumpregs(priv, "After setup"); @@ -943,46 +943,46 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ switch (priv->config->timid) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1010,14 +1010,14 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); return OK; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,7 +1062,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,7 +1099,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h index 9d88bdb8323c9..4f7d006c436ad 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H +#define __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H /**************************************************************************** * Included Files @@ -38,41 +38,41 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32L4_TIMn is defined - * then the CONFIG_STM32L4_TIMn_QE must also be defined to indicate that + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined + * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder */ -#undef CONFIG_STM32L4_TIM6_QE -#undef CONFIG_STM32L4_TIM7_QE -#undef CONFIG_STM32L4_TIM9_QE -#undef CONFIG_STM32L4_TIM10_QE -#undef CONFIG_STM32L4_TIM11_QE -#undef CONFIG_STM32L4_TIM12_QE -#undef CONFIG_STM32L4_TIM13_QE -#undef CONFIG_STM32L4_TIM14_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM9_QE +#undef CONFIG_STM32_TIM10_QE +#undef CONFIG_STM32_TIM11_QE +#undef CONFIG_STM32_TIM12_QE +#undef CONFIG_STM32_TIM13_QE +#undef CONFIG_STM32_TIM14_QE /**************************************************************************** * Included Files @@ -98,4 +98,4 @@ int stm32l4_qeinitialize(const char *devpath, int tim); #endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 954f8b460cec1..990eeb37ad345 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -56,7 +56,7 @@ #include "hardware/stm32l4_qspi.h" #include "hardware/stm32l4_pinmap.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32L4_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(STM32L4_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) +#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,23 +92,23 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# if defined(CONFIG_STM32L4_QSPI_DMA_CHAN_1_5) +# if defined(CONFIG_STM32_QSPI_DMA_CHAN_1_5) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_1 -# elif defined(CONFIG_STM32L4_QSPI_DMA_CHAN_2_7) +# elif defined(CONFIG_STM32_QSPI_DMA_CHAN_2_7) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_2 # else # error QSPI DMA channel must be specified via DMACHAN_QUADSPI in your board.h # endif -# if defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_CCR_PRILO -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIHI -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_CCR_PRIMED @@ -120,8 +120,8 @@ # error your board.h needs to define the value of BOARD_AHB_FREQUENCY #endif -#if !defined(CONFIG_STM32L4_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32L4_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32L4_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -162,14 +162,14 @@ struct stm32l4_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -179,11 +179,11 @@ struct stm32l4_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32l4_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -220,7 +220,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -233,7 +233,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -260,16 +260,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32L4_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32l4_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv); @@ -279,8 +279,8 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32L4_QSPI_DMATHRESHOLD -# define CONFIG_STM32L4_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -332,15 +332,15 @@ static struct stm32l4_qspidev_s g_qspi0dev = { .ops = &g_qspi0ops, }, - .base = STM32L4_QSPI_BASE, + .base = STM32_QSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, - .irq = STM32L4_IRQ_QUADSPI, + .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -366,7 +366,7 @@ static struct stm32l4_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -418,7 +418,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -441,7 +441,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -478,7 +478,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) * output. */ - regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */ spiinfo("CR:%08" PRIx32 "\n", regval); spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n" " FTHRES: %d\n" @@ -499,14 +499,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CR_PMM) ? 1 : 0, (regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ spiinfo("DCR:%08" PRIx32 "\n", regval); spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n", (regval & QSPI_DCR_CKMODE) ? 1 : 0, (regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT, (regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ spiinfo("CCR:%08" PRIx32 "\n", regval); spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n" " ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n" @@ -523,7 +523,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CCR_SIOO) ? 1 : 0, (regval & QSPI_CCR_DDRM) ? 1 : 0); - regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */ + regval = getreg32(priv->base + STM32_QUADSPI_SR_OFFSET); /* Status Register */ spiinfo("SR:%08" PRIx32 "\n", regval); spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n", (regval & QSPI_SR_TEF) ? 1 : 0, @@ -537,19 +537,19 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) #else spiinfo(" CR:%08" PRIx32 " DCR:%08" PRIx32 " CCR:%08" PRIx32 " SR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET), /* Control Register */ - getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET)); /* Status Register */ + getreg32(priv->base + STM32_QUADSPI_CR_OFFSET), /* Control Register */ + getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_SR_OFFSET)); /* Status Register */ spiinfo(" DLR:%08" PRIx32 " ABR:%08" PRIx32 " PSMKR:%08" PRIx32 " PSMAR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_DLR_OFFSET), /* Data Length Register */ - getreg32(priv->base + STM32L4_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ + getreg32(priv->base + STM32_QUADSPI_DLR_OFFSET), /* Data Length Register */ + getreg32(priv->base + STM32_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ + getreg32(priv->base + STM32_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ + getreg32(priv->base + STM32_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ spiinfo(" PIR:%08" PRIx32 " LPTR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ - getreg32(priv->base + STM32L4_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ + getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ + getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ UNUSED(regval); #endif } @@ -561,27 +561,27 @@ static void qspi_dumpgpioconfig(const char *msg) uint32_t regval; spiinfo("%s:\n", msg); - regval = getreg32(STM32L4_GPIOE_MODER); + regval = getreg32(STM32_GPIOE_MODER); spiinfo("E_MODER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OTYPER); + regval = getreg32(STM32_GPIOE_OTYPER); spiinfo("E_OTYPER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OSPEED); + regval = getreg32(STM32_GPIOE_OSPEED); spiinfo("E_OSPEED:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_PUPDR); + regval = getreg32(STM32_GPIOE_PUPDR); spiinfo("E_PUPDR:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRL); + regval = getreg32(STM32_GPIOE_AFRL); spiinfo("E_AFRL:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRH); + regval = getreg32(STM32_GPIOE_AFRH); spiinfo("E_AFRH:%08" PRIx32 "\n", regval); } #endif -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -787,7 +787,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -918,7 +918,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -951,12 +951,12 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, if (polarity) { - while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } else { - while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } } @@ -979,9 +979,9 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) { uint32_t regval; - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_ABORT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /**************************************************************************** @@ -1010,14 +1010,14 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET); + qspi_putreg(priv, xctn->datasize - 1, STM32_QUADSPI_DLR_OFFSET); } /* If we have alternate bytes, stick them in now */ if (CCR_ABMODE_NONE != xctn->altbytesmode) { - qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET); + qspi_putreg(priv, xctn->altbytes, STM32_QUADSPI_ABR_OFFSET); } /* Build the CCR value and set it */ @@ -1033,17 +1033,17 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, QSPI_CCR_FMODE(fctn) | (xctn->isddr ? QSPI_CCR_SIOO : 0) | (xctn->issioo ? QSPI_CCR_DDRM : 0); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* If we have and need and address, set that now, too */ if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, xctn->addr, STM32_QUADSPI_AR_OFFSET); } } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1068,22 +1068,22 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Let's find out what is going on */ - status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET); - cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + status = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET); + cr = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); /* Is it 'FIFO Threshold'? */ if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE)) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR) { /* Write data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Read data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1131,27 +1131,27 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer * complete Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Do the last bit of read if needed */ if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); /* Read any remaining data */ while (((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) & + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1189,7 +1189,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32_QUADSPI_FCR); /* If 'automatic poll mode stop' is activated, we're done */ @@ -1197,9 +1197,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set success status */ @@ -1223,14 +1223,14 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32_QUADSPI_FCR); /* Disable all the QSPI Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set error status; 'transfer error' means that, in 'indirect mode', * an invalid address is attempted to be accessed. 'Invalid' is @@ -1251,7 +1251,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); /* XXX this interrupt simply means that, in 'memory mapped mode', * the QSPI memory has not been accessed for a while, and the @@ -1269,7 +1269,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1426,16 +1426,16 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, - STM32L4_QUADSPI_DR_OFFSET), + STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); qspi_dma_sample(priv, DMA_AFTER_SETUP); /* Enable the memory transfer */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command info */ @@ -1481,9 +1481,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, if (ret < 0) { DEBUGPANIC(); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); return ret; } @@ -1512,9 +1512,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, stm32l4_dmastop(priv->dmach); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Complain if the DMA fails */ @@ -1527,7 +1527,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } #endif -#if !defined(STM32L4_QSPI_INTERRUPTS) +#if !defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -1548,12 +1548,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *dest = (uint8_t *)xctn->buffer; uint32_t addrval; uint32_t regval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); if (dest != NULL) { /* Counter of remaining data */ @@ -1562,14 +1562,14 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Ensure CCR register specifies indirect read */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CCR_OFFSET); regval &= ~QSPI_CCR_FMODE_MASK; regval |= QSPI_CCR_FMODE(CCR_FMODE_INDRD); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Transfer loop */ @@ -1589,7 +1589,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the busy flag, and ditch any extra bytes in * fifo @@ -1626,7 +1626,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *src = (uint8_t *)xctn->buffer; if (src != NULL) @@ -1652,7 +1652,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the Busy flag */ @@ -1765,7 +1765,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * prescaler = STL32L4_QSPI_CLOCK / frequency * * Where prescaler can have the range 1 to 256 and the - * STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1. + * STM32_QUADSPI_CR_OFFSET register field holds prescaler - 1. * NOTE that a "ceiling" type of calculation is performed. * 'frequency' is treated as a not-to-exceed value. */ @@ -1785,10 +1785,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) /* Save the new prescaler value (minus one) */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK); regval |= (prescaler - 1) << QSPI_CR_PRESCALER_SHIFT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Calculate the new actual frequency */ @@ -1850,7 +1850,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) * 3 1 1 */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR); regval &= ~(QSPI_DCR_CKMODE); switch (mode) @@ -1870,7 +1870,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) return; } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR); spiinfo("DCR=%08" PRIx32 "\n", regval); /* Save the mode so that subsequent re-configurations will be faster */ @@ -1957,9 +1957,9 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -1983,16 +1983,16 @@ static int qspi_command(struct qspi_dev_s *dev, * Complete' interrupts. */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2002,15 +2002,15 @@ static int qspi_command(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer * Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } } else @@ -2023,9 +2023,9 @@ static int qspi_command(struct qspi_dev_s *dev, /* Enable 'Transfer Error' and 'Transfer Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2139,9 +2139,9 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2163,16 +2163,16 @@ static int qspi_memory(struct qspi_dev_s *dev, * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2182,15 +2182,15 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* Wait for the interrupt routine to finish it's magic */ @@ -2202,11 +2202,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32L4_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2356,7 +2356,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval = 0; regval &= ~(QSPI_CR_EN); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2364,16 +2364,16 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Disable all interrupt sources for starters */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2381,21 +2381,21 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Configure QSPI Clock Prescaler and Sample Shift */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK | QSPI_CR_SSHIFT); regval |= (0x01 << QSPI_CR_PRESCALER_SHIFT); regval |= (0x00); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32L4_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32L4_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while (!(nsize & 0x80000000)) { @@ -2406,13 +2406,13 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT); } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET); /* Enable QSPI */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_EN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2467,18 +2467,18 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Enable clocking to the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); regval |= RCC_AHB3ENR_QSPIEN; - putreg32(regval, STM32L4_RCC_AHB3ENR); - regval = getreg32(STM32L4_RCC_AHB3ENR); + putreg32(regval, STM32_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); /* Reset the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3RSTR); + regval = getreg32(STM32_RCC_AHB3RSTR); regval |= RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); regval &= ~RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); /* Configure multiplexed pins as connected on the board. */ @@ -2501,7 +2501,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) { /* Now perform one time initialization */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2515,7 +2515,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } #endif -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2541,7 +2541,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2549,12 +2549,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32l4_dmafree(priv->dmach); @@ -2614,32 +2614,32 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * CS if memory is not accessed for a while) */ - qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET); + qspi_putreg(priv, lpto, STM32_QUADSPI_LPTR_OFFSET); /* Clear Timeout interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); #endif } else { - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_TCEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* create a transaction object */ qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2685,4 +2685,4 @@ void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32L4_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index f2e7fd119a9c9..7c3b5a8fa2d36 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H /**************************************************************************** * Included Files @@ -34,7 +34,7 @@ #include "chip.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -126,5 +126,5 @@ void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_QSPI */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H */ +#endif /* CONFIG_STM32_QSPI */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index f59a6be1753c8..190d532fdc46c 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -43,13 +43,13 @@ /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "stm32l4x3xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "stm32l4x5xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "stm32l4x6xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "stm32l4xrxx_rcc.c" #else # error "Unsupported STM32L4 chip" @@ -98,7 +98,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L4_PWR) && defined(CONFIG_STM32L4_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -108,14 +108,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l4_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L4_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -128,19 +128,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L4_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l4_pwr_enablebkp(false); @@ -163,7 +163,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l4_board_clockconfig(). * @@ -185,7 +185,7 @@ void stm32l4_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -220,7 +220,7 @@ void stm32l4_clockconfig(void) * stm32l4_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l4_board_clockconfig(). * @@ -235,7 +235,7 @@ void stm32l4_clockconfig(void) #ifdef CONFIG_PM void stm32l4_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 29c8257c00bbc..2850bfc0e78ce 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_RCC_H /**************************************************************************** * Included Files @@ -32,13 +32,13 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_rcc.h" #else # error "Unsupported STM32L4 chip" @@ -88,10 +88,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCO_MASK); regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -107,7 +107,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l4_board_clockconfig(). * @@ -130,7 +130,7 @@ void stm32l4_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32l4_board_clockconfig(void); #endif @@ -147,7 +147,7 @@ void stm32l4_board_clockconfig(void); * stm32l4_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l4_board_clockconfig(). * @@ -204,4 +204,4 @@ void stm32l4_rcc_disablelsi(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 142890ddad972..9a81038f86e59 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32l4_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -93,7 +93,7 @@ static int stm32l4_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -113,24 +113,24 @@ static void stm32l4_rngenable(void) /* Enable generation and interrupts */ - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval |= RNG_CR_RNGEN; regval |= RNG_CR_IE; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); - up_enable_irq(STM32L4_IRQ_RNG); + up_enable_irq(STM32_IRQ_RNG); } static void stm32l4_rngdisable(void) { uint32_t regval; - up_disable_irq(STM32L4_IRQ_RNG); + up_disable_irq(STM32_IRQ_RNG); - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval &= ~RNG_CR_IE; regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); } static int stm32l4_rnginterrupt(int irq, void *context, void *arg) @@ -138,12 +138,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) uint32_t rngsr; uint32_t data; - rngsr = getreg32(STM32L4_RNG_SR); + rngsr = getreg32(STM32_RNG_SR); if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */ { /* Clear it, we will try again. */ - putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR); + putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR); return OK; } @@ -153,12 +153,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) /* Clear seed error, then disable/enable the rng and try again. */ - putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR); - crval = getreg32(STM32L4_RNG_CR); + putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR); + crval = getreg32(STM32_RNG_CR); crval &= ~RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); crval |= RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); return OK; } @@ -169,7 +169,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) return OK; } - data = getreg32(STM32L4_RNG_DR); + data = getreg32(STM32_RNG_DR); /* As required by the FIPS PUB (Federal Information Processing Standard * Publication) 140-2, the first random number generated after setting the @@ -315,4 +315,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32L4_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 17cd5e349f3a4..7f9c1a687584d 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -46,7 +46,7 @@ #include "stm32l4_exti.h" #include "stm32l4_rtc.h" -#ifdef CONFIG_STM32L4_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -67,8 +67,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32L4_PWR -# error "CONFIG_STM32L4_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -142,23 +142,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32L4_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_WUTR)); - - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBSSR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -220,8 +220,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(0xca, STM32L4_RTC_WPR); - putreg32(0x53, STM32L4_RTC_WPR); + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); } /**************************************************************************** @@ -242,7 +242,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32L4_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -272,16 +272,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -316,21 +316,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32L4_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -360,9 +360,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -434,13 +434,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); #endif } @@ -478,10 +478,10 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -500,17 +500,17 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -529,9 +529,9 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -574,7 +574,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -600,7 +600,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -639,12 +639,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -656,13 +656,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32L4_RTC_ALRMAR); - putreg32(0, STM32L4_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -682,12 +682,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -699,13 +699,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32L4_RTC_ALRMBR); - putreg32(0, STM32L4_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -869,14 +869,14 @@ int up_rtc_initialize(void) stm32l4_pwr_enablebkp(true); -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#if defined(CONFIG_STM32_RTC_HSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -884,7 +884,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -912,13 +912,13 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32L4_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -930,21 +930,21 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) + STM32_RTC_PRER); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); -#else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ + STM32_RTC_PRER); +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1021,7 +1021,7 @@ int up_rtc_initialize(void) int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1038,18 +1038,18 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32L4_RTC_DR); - tr = getreg32(STM32L4_RTC_TR); -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32L4_RTC_SSR); - tmp = getreg32(STM32L4_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32L4_RTC_DR); + tmp = getreg32(STM32_RTC_DR); if (tmp == dr) { break; @@ -1102,13 +1102,13 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32L4_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1182,8 +1182,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32L4_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1255,8 +1255,8 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32L4_RTC_TR); - putreg32(dr, STM32L4_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1452,7 +1452,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1462,8 +1462,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMAR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(-1, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1483,7 +1483,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1493,8 +1493,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMBR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(-1, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1541,7 +1541,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32L4_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1550,7 +1550,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32L4_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1588,9 +1588,9 @@ static int stm32l4_rtc_wakeup_handler(int irq, void *context, stm32l4_pwr_enablebkp(true); - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32l4_pwr_enablebkp(false); @@ -1636,10 +1636,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1669,13 +1669,13 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32L4_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1713,9 +1713,9 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1724,7 +1724,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1748,7 +1748,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32L4_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1769,17 +1769,17 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32L4_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1811,9 +1811,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1822,7 +1822,7 @@ int stm32l4_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1834,9 +1834,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32L4_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32L4_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); @@ -1844,4 +1844,4 @@ int stm32l4_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32L4_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index b89807b7c0768..d1ae9b632da95 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -24,8 +24,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32L4_STM32_RTC_H #include #include @@ -38,24 +38,24 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32L4_RTC_MAGIC) -# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32L4_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_REG) -# define CONFIG_STM32L4_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -156,7 +156,7 @@ bool stm32l4_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif @@ -313,4 +313,4 @@ struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_RTC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index bac80beef62f9..27e3aaabfc0ec 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32L4_NALARMS]; + struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 5344b764b36ae..c8123ca729af8 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -63,7 +63,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sai.h" -#ifdef CONFIG_STM32L4_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -81,37 +81,37 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32L4_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32L4_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif -#ifndef CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE -# define CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE (48000) +#ifndef CONFIG_STM32_SAI_DEFAULT_SAMPLERATE +# define CONFIG_STM32_SAI_DEFAULT_SAMPLERATE (48000) #endif -#ifndef CONFIG_STM32L4_SAI_DEFAULT_DATALEN -# define CONFIG_STM32L4_SAI_DEFAULT_DATALEN (16) +#ifndef CONFIG_STM32_SAI_DEFAULT_DATALEN +# define CONFIG_STM32_SAI_DEFAULT_DATALEN (16) #endif -#ifndef CONFIG_STM32L4_SAI_MAXINFLIGHT -# define CONFIG_STM32L4_SAI_MAXINFLIGHT (16) +#ifndef CONFIG_STM32_SAI_MAXINFLIGHT +# define CONFIG_STM32_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ -# if defined(CONFIG_STM32L4_SAI_DMAPRIO) -# define SAI_DMA_PRIO CONFIG_STM32L4_SAI_DMAPRIO +# if defined(CONFIG_STM32_SAI_DMAPRIO) +# define SAI_DMA_PRIO CONFIG_STM32_SAI_DMAPRIO # else # define SAI_DMA_PRIO DMA_CCR_PRIMED # endif # if (SAI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SAI_DMAPRIO" +# error "Illegal value for CONFIG_STM32_SAI_DMAPRIO" # endif /* DMA channel configuration */ @@ -149,7 +149,7 @@ struct stm32l4_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -168,7 +168,7 @@ struct stm32l4_sai_s sem_t bufsem; /* Buffer wait semaphore */ struct sai_buffer_s *freelist; /* A list a free buffer containers */ - struct sai_buffer_s containers[CONFIG_STM32L4_SAI_MAXINFLIGHT]; + struct sai_buffer_s containers[CONFIG_STM32_SAI_MAXINFLIGHT]; }; /**************************************************************************** @@ -191,7 +191,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32l4_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -229,89 +229,89 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32L4_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32l4_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32L4_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32l4_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A + .frequency = STM32_SAI1_FREQUENCY, +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif /* SAI2 state */ -#ifdef CONFIG_STM32L4_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32l4_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif -#ifdef CONFIG_STM32L4_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32l4_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A + .frequency = STM32_SAI2_FREQUENCY, +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif - .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, - .samplerate = CONFIG_STM32L4_SAI_DEFAULT_SAMPLERATE, - .bufsem = SEM_INITIALIZER(CONFIG_STM32L4_SAI_MAXINFLIGHT), + .datalen = CONFIG_STM32_SAI_DEFAULT_DATALEN, + .samplerate = CONFIG_STM32_SAI_DEFAULT_SAMPLERATE, + .bufsem = SEM_INITIALIZER(CONFIG_STM32_SAI_MAXINFLIGHT), }; #endif @@ -433,14 +433,14 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_CR1_OFFSET), - sai_getreg(priv, STM32L4_SAI_CR2_OFFSET), - sai_getreg(priv, STM32L4_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32L4_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_IM_OFFSET), - sai_getreg(priv, STM32L4_SAI_SR_OFFSET), - sai_getreg(priv, STM32L4_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); } #endif @@ -474,7 +474,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) mckdiv = priv->frequency / (priv->samplerate * 2 * 256); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -500,7 +500,7 @@ static void sai_timeout(wdparm_t arg) struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32l4_dmastop(priv->dma); @@ -530,7 +530,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32l4_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32L4_SAI_DR_OFFSET, + stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -634,7 +634,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -702,7 +702,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -814,7 +814,7 @@ static void sai_schedule(struct stm32l4_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; @@ -901,9 +901,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -981,7 +981,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1005,7 +1005,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1086,7 +1086,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1110,7 +1110,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1232,7 +1232,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv) int i; priv->freelist = NULL; - for (i = 0; i < CONFIG_STM32L4_SAI_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_SAI_MAXINFLIGHT; i++) { sai_buf_free(priv, &priv->containers[i]); } @@ -1267,29 +1267,29 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) /* Configure the data width */ sai_datawidth((struct i2s_dev_s *)priv, - CONFIG_STM32L4_SAI_DEFAULT_DATALEN); + CONFIG_STM32_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32l4_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32L4_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32L4_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); @@ -1324,14 +1324,14 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) switch (intf) { -#ifdef CONFIG_STM32L4_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); priv = &g_sai1a_priv; stm32l4_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32l4_configgpio(GPIO_SAI1_FS_A); stm32l4_configgpio(GPIO_SAI1_SCK_A); stm32l4_configgpio(GPIO_SAI1_MCLK_A); @@ -1340,14 +1340,14 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); priv = &g_sai1b_priv; stm32l4_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32l4_configgpio(GPIO_SAI1_FS_B); stm32l4_configgpio(GPIO_SAI1_SCK_B); stm32l4_configgpio(GPIO_SAI1_MCLK_B); @@ -1356,14 +1356,14 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); priv = &g_sai2a_priv; stm32l4_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32l4_configgpio(GPIO_SAI2_FS_A); stm32l4_configgpio(GPIO_SAI2_SCK_A); stm32l4_configgpio(GPIO_SAI2_MCLK_A); @@ -1372,14 +1372,14 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); priv = &g_sai2b_priv; stm32l4_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32l4_configgpio(GPIO_SAI2_FS_B); stm32l4_configgpio(GPIO_SAI2_SCK_B); stm32l4_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32l4/stm32l4_sai.h b/arch/arm/src/stm32l4/stm32l4_sai.h index 69c305ba8b12b..08f8863b80274 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/stm32l4_sai.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_SAI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_SAI_H /**************************************************************************** * Included Files @@ -92,4 +92,4 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_SAI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_SAI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 49e54607c3400..85e2e8ea1fc9d 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -50,7 +50,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sdmmc.h" -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32L4_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -71,27 +71,27 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32L4_SDMMC_DMA - Enable SDMMC. This is a marginally + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally * optional. For most usages, SDMMC will cause data overruns if used * without DMA. NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32L4_SDMMC_DMA is enabled. - * CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level * debug output. This also requires CONFIG_DEBUG_FS and * CONFIG_DEBUG_INFO */ -#ifndef CONFIG_STM32L4_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error "CONFIG_STM32L4_SDMMC_DMA support requires CONFIG_STM32L4_DMA2" +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32L4_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -99,34 +99,34 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32L4_SDMMC1 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC1_DMAPRIO -# define CONFIG_STM32L4_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif #endif -#ifdef CONFIG_STM32L4_SDMMC2 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC2_DMAPRIO -# define CONFIG_STM32L4_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32L4_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif /* Friendly CLKCR bit re-definitions ****************************************/ @@ -288,8 +288,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -321,7 +321,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -351,7 +351,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -360,7 +360,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -377,7 +377,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -400,7 +400,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -415,7 +415,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -490,7 +490,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -510,7 +510,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -546,7 +546,7 @@ struct stm32_dev_s g_sdmmcdev1 = .registercallback = stm32_registercallback, #endif #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -561,18 +561,18 @@ struct stm32_dev_s g_sdmmcdev1 = #endif #endif }, - .base = STM32L4_SDMMC1_BASE, - .nirq = STM32L4_IRQ_SDMMC1, + .base = STM32_SDMMC1_BASE, + .nirq = STM32_IRQ_SDMMC1, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -620,8 +620,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC2_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; @@ -629,7 +629,7 @@ struct stm32_dev_s g_sdmmcdev2 = /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -779,7 +779,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, @@ -847,7 +847,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, @@ -863,7 +863,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -887,12 +887,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -911,7 +911,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -941,12 +941,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -965,13 +965,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -984,7 +984,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1002,7 +1002,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1361,7 +1361,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1453,7 +1453,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1492,7 +1492,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1684,7 +1684,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1700,7 +1700,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ #endif @@ -1739,7 +1739,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2010,7 +2010,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2065,7 +2065,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2119,7 +2119,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2644,7 +2644,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2741,7 +2741,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32L4_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -2777,7 +2777,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -2848,7 +2848,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3028,18 +3028,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; #endif @@ -3068,14 +3068,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == 1) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; #endif @@ -3110,7 +3110,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32l4_dmachannel(dmachan); @@ -3211,4 +3211,4 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32L4_SDMMC1 || CONFIG_STM32L4_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index bf78be0ddf899..6b4b700cb3ec8 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -79,14 +79,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32L4_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32L4_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -113,7 +113,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L4_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -146,11 +146,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -182,8 +182,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L4_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L4_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -197,7 +197,7 @@ * See stm32l4serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -391,7 +391,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -399,7 +399,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -407,7 +407,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -415,7 +415,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -423,7 +423,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -431,7 +431,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -441,7 +441,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 LPUART1 port. */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32l4_serial_s g_lpuart1priv = { .dev = @@ -467,13 +467,13 @@ static struct stm32l4_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L4_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -503,7 +503,7 @@ static struct stm32l4_serial_s g_lpuart1priv = /* This describes the state of the STM32 USART1 port. */ -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32l4_serial_s g_usart1priv = { .dev = @@ -529,13 +529,13 @@ static struct stm32l4_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L4_PCLK2_FREQUENCY, - .usartbase = STM32L4_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -565,7 +565,7 @@ static struct stm32l4_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32l4_serial_s g_usart2priv = { .dev = @@ -591,13 +591,13 @@ static struct stm32l4_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -627,7 +627,7 @@ static struct stm32l4_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32l4_serial_s g_usart3priv = { .dev = @@ -653,13 +653,13 @@ static struct stm32l4_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -689,7 +689,7 @@ static struct stm32l4_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32l4_serial_s g_uart4priv = { .dev = @@ -715,7 +715,7 @@ static struct stm32l4_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -728,8 +728,8 @@ static struct stm32l4_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -751,7 +751,7 @@ static struct stm32l4_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32l4_serial_s g_uart5priv = { .dev = @@ -777,7 +777,7 @@ static struct stm32l4_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -790,8 +790,8 @@ static struct stm32l4_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -814,24 +814,24 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l4_serial_s * -const g_uart_devs[STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -891,15 +891,15 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * enable/usage table above) */ - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - cr3 = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1035,8 +1035,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - brr = stm32l4serial_getreg(priv, STM32L4_USART_BRR_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32l4serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -1062,8 +1062,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -1076,7 +1076,7 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) { uint32_t brr; @@ -1099,7 +1099,7 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -1121,8 +1121,8 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L4_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { stm32l4serial_setbaud_lpuart(priv); } @@ -1134,7 +1134,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1172,11 +1172,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1184,14 +1184,14 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1205,7 +1205,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1250,7 +1250,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + while ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1356,7 +1356,7 @@ static void stm32l4serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -1395,40 +1395,40 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - case STM32L4_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L4_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER - case STM32L4_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER - case STM32L4_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER - case STM32L4_USART3_BASE: +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER - case STM32L4_UART4_BASE: +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER - case STM32L4_UART5_BASE: +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1494,7 +1494,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L4_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1515,7 +1515,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1526,26 +1526,26 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1553,9 +1553,9 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1608,7 +1608,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1619,7 +1619,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1633,9 +1633,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1693,9 +1693,9 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1844,8 +1844,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L4_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L4_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1859,7 +1859,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1931,7 +1931,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1991,7 +1991,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L4_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2002,19 +2002,19 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -2050,17 +2050,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L4_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2071,17 +2071,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2101,17 +2101,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L4_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2122,17 +2122,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2143,11 +2143,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2248,8 +2248,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L4_USART_BREAKS -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2304,8 +2304,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2317,8 +2317,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2354,7 +2354,7 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l4serial_getreg(priv, STM32L4_USART_RDR_OFFSET); + rdr = stm32l4serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2444,7 +2444,7 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2480,7 +2480,7 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32l4_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2607,7 +2607,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2618,7 +2618,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2787,7 +2787,7 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)ch); + stm32l4serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2836,7 +2836,7 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2875,7 +2875,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) { struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2918,11 +2918,11 @@ static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -3058,7 +3058,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -3128,7 +3128,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3177,7 +3177,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3197,7 +3197,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -3206,7 +3206,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index b53213580ea0b..347ad4f26aff6 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -80,8 +80,8 @@ #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -91,19 +91,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L4_SPI_INTERRUPTS) && defined(CONFIG_STM32L4_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,10 +137,10 @@ struct stm32l4_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -185,7 +185,7 @@ static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32l4_spidev_s *priv); static int spi_dmatxwait(struct stm32l4_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv); @@ -247,7 +247,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -285,12 +285,12 @@ static struct stm32l4_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L4_SPI1_BASE, - .spiclock = STM32L4_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,7 +305,7 @@ static struct stm32l4_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -343,12 +343,12 @@ static struct stm32l4_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L4_SPI2_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,7 +361,7 @@ static struct stm32l4_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -399,12 +399,12 @@ static struct stm32l4_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L4_SPI3_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI3, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L4_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L4_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -635,7 +635,7 @@ static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32l4_spidev_s *priv) { int ret; @@ -668,7 +668,7 @@ static int spi_dmarxwait(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32l4_spidev_s *priv) { int ret; @@ -701,7 +701,7 @@ static int spi_dmatxwait(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -716,7 +716,7 @@ static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -731,7 +731,7 @@ static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; @@ -751,7 +751,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; @@ -771,7 +771,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -822,7 +822,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, const void *txbuffer, const void *txdummy, @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -874,7 +874,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) { priv->rxresult = 0; @@ -890,7 +890,7 @@ static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) { priv->txresult = 0; @@ -985,11 +985,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L4_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L4_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L4_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1055,9 +1055,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1127,9 +1127,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1193,9 +1193,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1248,9 +1248,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1316,7 +1316,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L4_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1354,8 +1354,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_SPI_DMA) || defined(CONFIG_STM32L4_DMACAPABLE) -#if !defined(CONFIG_STM32L4_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1438,7 +1438,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L4_SPI_DMA || CONFIG_STM32L4_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1461,14 +1461,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32l4_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1530,7 +1530,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L4_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1551,7 +1551,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1738,11 +1738,11 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1754,9 +1754,9 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L4_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32l4_dmachannel() * will block and wait until the channel becomes available. WARNING: If @@ -1769,13 +1769,13 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) priv->txdma = stm32l4_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1810,7 +1810,7 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1835,7 +1835,7 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1860,7 +1860,7 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1893,4 +1893,4 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h index b946487353f4e..e296a7e82c4c7 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/stm32l4_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L4_STM32_SPI_H /**************************************************************************** * Included Files @@ -104,21 +104,21 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l4_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,19 +146,19 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l4_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); @@ -171,4 +171,4 @@ int stm32l4_spi3register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 64aacd7fc9a01..edea1f411ea56 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -60,8 +60,8 @@ * the stack + 4; */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -129,7 +129,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L4_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32l4/stm32l4_start.h b/arch/arm/src/stm32l4/stm32l4_start.h index 60f19e7a16a18..33ba733a4fc3c 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.h +++ b/arch/arm/src/stm32l4/stm32l4_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_START_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_START_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_START_H +#define __ARCH_ARM_SRC_STM32L4_STM32_START_H /**************************************************************************** * Included Files @@ -44,4 +44,4 @@ void stm32l4_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_START_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_START_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index dba5a51fd3f9f..d1e9d16c35a95 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -87,20 +87,20 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_ONESHOT -# error CONFIG_STM32L4_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_ONESHOT +# error CONFIG_STM32_ONESHOT must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_FREERUN -# error CONFIG_STM32L4_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_FREERUN +# error CONFIG_STM32_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_FREERUN -# error CONFIG_STM32L4_TICKLESS_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_FREERUN +# error CONFIG_STM32_TICKLESS_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_ONESHOT -# error CONFIG_STM32L4_TICKLESS_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_ONESHOT +# error CONFIG_STM32_TICKLESS_ONESHOT must be selected for the Tickless OS option #endif /**************************************************************************** @@ -186,7 +186,7 @@ void up_timer_initialize(void) /* Initialize the one-shot timer */ ret = stm32l4_oneshot_initialize(&g_tickless.oneshot, - CONFIG_STM32L4_TICKLESS_ONESHOT, + CONFIG_STM32_TICKLESS_ONESHOT, CONFIG_USEC_PER_TICK); if (ret < 0) { @@ -220,7 +220,7 @@ void up_timer_initialize(void) /* Initialize the free-running timer */ ret = stm32l4_freerun_initialize(&g_tickless.freerun, - CONFIG_STM32L4_TICKLESS_FREERUN, + CONFIG_STM32_TICKLESS_FREERUN, CONFIG_USEC_PER_TICK); if (ret < 0) { diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 6facb4e747f88..4f085abbcf87c 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -53,137 +53,137 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32L4_TIMn is - * defined then CONFIG_STM32L4_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32L4_TIMn is defined then - * CONFIG_STM32L4_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined (CONFIG_STM32L4_TIM1_ADC) || \ - defined(CONFIG_STM32L4_TIM1_DAC) || defined(CONFIG_STM32L4_TIM1_QE) -# undef CONFIG_STM32L4_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) || defined (CONFIG_STM32L4_TIM2_ADC) || \ - defined(CONFIG_STM32L4_TIM2_DAC) || defined(CONFIG_STM32L4_TIM2_QE) -# undef CONFIG_STM32L4_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) || defined (CONFIG_STM32L4_TIM3_ADC) || \ - defined(CONFIG_STM32L4_TIM3_DAC) || defined(CONFIG_STM32L4_TIM3_QE) -# undef CONFIG_STM32L4_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) || defined (CONFIG_STM32L4_TIM4_ADC) || \ - defined(CONFIG_STM32L4_TIM4_DAC) || defined(CONFIG_STM32L4_TIM4_QE) -# undef CONFIG_STM32L4_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) || defined (CONFIG_STM32L4_TIM5_ADC) || \ - defined(CONFIG_STM32L4_TIM5_DAC) || defined(CONFIG_STM32L4_TIM5_QE) -# undef CONFIG_STM32L4_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32L4_TIM6_ADC) || \ - defined(CONFIG_STM32L4_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE) -# undef CONFIG_STM32L4_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32L4_TIM7_PWM) || defined (CONFIG_STM32L4_TIM7_ADC) || \ - defined(CONFIG_STM32L4_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE) -# undef CONFIG_STM32L4_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) || defined (CONFIG_STM32L4_TIM8_ADC) || \ - defined(CONFIG_STM32L4_TIM8_DAC) || defined(CONFIG_STM32L4_TIM8_QE) -# undef CONFIG_STM32L4_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) || defined (CONFIG_STM32L4_TIM15_ADC) || \ - defined(CONFIG_STM32L4_TIM15_DAC) || defined(CONFIG_STM32L4_TIM15_QE) -# undef CONFIG_STM32L4_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \ - defined(CONFIG_STM32L4_TIM16_DAC) || defined(CONFIG_STM32L4_TIM16_QE) -# undef CONFIG_STM32L4_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \ - defined(CONFIG_STM32L4_TIM17_DAC) || defined(CONFIG_STM32L4_TIM17_QE) -# undef CONFIG_STM32L4_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L4_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -194,12 +194,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -305,101 +305,101 @@ static const struct stm32l4_tim_ops_s stm32l4_tim_ops = .dump_regs = stm32l4_tim_dumpregs, }; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32l4_tim_priv_s stm32l4_tim1_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32l4_tim_priv_s stm32l4_tim2_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32l4_tim_priv_s stm32l4_tim3_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32l4_tim_priv_s stm32l4_tim4_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32l4_tim_priv_s stm32l4_tim5_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32l4_tim_priv_s stm32l4_tim6_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32l4_tim_priv_s stm32l4_tim7_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32l4_tim_priv_s stm32l4_tim8_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32l4_tim_priv_s stm32l4_tim15_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32l4_tim_priv_s stm32l4_tim16_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32l4_tim_priv_s stm32l4_tim17_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -487,9 +487,9 @@ static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_EGR_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32L4_GTIM_EGR_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -498,11 +498,11 @@ static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -511,9 +511,9 @@ static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -527,7 +527,7 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l4_tim_disable(dev); } @@ -547,7 +547,7 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, * Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L4_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l4_configgpio(cfg); } @@ -567,42 +567,42 @@ static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); - if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) + if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } @@ -621,13 +621,13 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -636,21 +636,21 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L4_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L4_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L4_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val &= ~GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: @@ -659,7 +659,7 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, break; - case STM32L4_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -668,15 +668,15 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L4_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM8_BASE) + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l4_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -713,67 +713,67 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -838,8 +838,8 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32L4_GTIM_ARR_OFFSET, reload); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32l4_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -872,67 +872,67 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -963,7 +963,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } @@ -986,65 +986,65 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -1054,7 +1054,7 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -1066,7 +1066,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32L4_GTIM_ARR_OFFSET, period); + stm32l4_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -1076,7 +1076,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32L4_GTIM_ARR_OFFSET); + return stm32l4_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -1086,20 +1086,20 @@ static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32L4_GTIM_CNT_OFFSET); + uint32_t counter = stm32l4_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L4_TIM2) || defined(CONFIG_STM32L4_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -1123,7 +1123,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); + ccer_val = stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1144,13 +1144,13 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -1159,12 +1159,12 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L4_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L4_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L4_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -1176,7 +1176,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L4_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -1191,21 +1191,21 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32L4_GTIM_CCER_OFFSET, ccer_val); + stm32l4_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1237,8 +1237,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1270,8 +1270,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1303,8 +1303,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1335,8 +1335,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1368,8 +1368,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1401,8 +1401,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1434,8 +1434,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1467,8 +1467,8 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR1_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR2_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR3_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR4_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1554,16 +1554,16 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR1_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR2_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR3_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR4_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1583,67 +1583,67 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - vectorno = STM32L4_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - vectorno = STM32L4_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - vectorno = STM32L4_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - vectorno = STM32L4_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - vectorno = STM32L4_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - vectorno = STM32L4_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - vectorno = STM32L4_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - vectorno = STM32L4_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - vectorno = STM32L4_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - vectorno = STM32L4_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - vectorno = STM32L4_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1676,7 +1676,7 @@ static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1687,7 +1687,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1696,7 +1696,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32L4_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l4_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1706,7 +1706,7 @@ static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET); + uint16_t regval = stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1726,79 +1726,79 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,7 +1808,7 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32L4_TIM_MODE_UNUSED) + if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1833,68 +1833,68 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1904,9 +1904,9 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_UNUSED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32L4_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 06a800a351951..698aa71e9a797 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L4_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,24 +38,24 @@ /* Helpers ******************************************************************/ -#define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L4_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L4_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L4_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L4_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L4_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L4_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32L4_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32L4_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -83,34 +83,34 @@ struct stm32l4_tim_dev_s enum stm32l4_tim_mode_e { - STM32L4_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L4_TIM_MODE_MASK = 0x0310, - STM32L4_TIM_MODE_DISABLED = 0x0000, - STM32L4_TIM_MODE_UP = 0x0100, - STM32L4_TIM_MODE_DOWN = 0x0110, - STM32L4_TIM_MODE_UPDOWN = 0x0200, - STM32L4_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L4_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L4_TIM_MODE_CK_EXT = 0x0800, - STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L4_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L4_TIM_MODE_CK_CH1 = 0x0001, - STM32L4_TIM_MODE_CK_CH2 = 0x0002, - STM32L4_TIM_MODE_CK_CH3 = 0x0003, - STM32L4_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -120,32 +120,32 @@ enum stm32l4_tim_mode_e enum stm32l4_tim_channel_e { - STM32L4_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L4_TIM_CH_POLARITY_POS = 0x00, - STM32L4_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L4_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32L4_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L4_TIM_CH_INCAPTURE = 0x10, - STM32L4_TIM_CH_INPWM = 0x20 - STM32L4_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; @@ -228,4 +228,4 @@ int stm32l4_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 0f2d6376b29e5..fcdfdb7656c8c 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -60,28 +60,28 @@ #include "stm32l4_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_TIM1_RES 16 -#define STM32L4_TIM2_RES 32 -#define STM32L4_TIM3_RES 16 -#define STM32L4_TIM4_RES 16 -#define STM32L4_TIM5_RES 32 -#define STM32L4_TIM6_RES 16 -#define STM32L4_TIM7_RES 16 -#define STM32L4_TIM8_RES 16 -#define STM32L4_TIM15_RES 16 -#define STM32L4_TIM16_RES 16 -#define STM32L4_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -137,91 +137,91 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -247,13 +247,13 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) (struct stm32l4_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32L4_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L4_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -286,12 +286,12 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -325,9 +325,9 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -382,8 +382,8 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L4_TIM_GETCLOCK(priv->tim); - period = STM32L4_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -399,7 +399,7 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L4_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -436,13 +436,13 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L4_TIM_SETCLOCK(priv->tim, freq); - STM32L4_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L4_TIM_SETCLOCK(priv->tim, 1000000); - STM32L4_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -482,13 +482,13 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -522,66 +522,66 @@ int stm32l4_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index 1a37a689243e4..71e0c36f6125e 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -54,13 +54,13 @@ * register. */ -#undef CONFIG_STM32L4_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ +#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */ /* And I don't know now to re-configure it yet */ -#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -120,7 +120,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); /* Enable SysTick interrupts */ @@ -143,5 +143,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L4_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 4aa9468634648..94aaa33934608 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32L4_STM32L4_UART_H -#define __ARCH_ARM_STC_STM32L4_STM32L4_UART_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L4_STM32_UART_H /**************************************************************************** * Included Files @@ -32,8 +32,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_uart.h" #else # error "Unsupported STM32L4 chip" @@ -47,63 +47,63 @@ * the device. */ -#if !defined(CONFIG_STM32L4_HAVE_UART5) -# undef CONFIG_STM32L4_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L4_HAVE_UART4) -# undef CONFIG_STM32L4_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART3) -# undef CONFIG_STM32L4_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART2) -# undef CONFIG_STM32L4_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART1) -# undef CONFIG_STM32L4_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L4_HAVE_LPUART1) -# undef CONFIG_STM32L4_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L4_LPUART1) -# undef CONFIG_STM32L4_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L4_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART1) -# undef CONFIG_STM32L4_USART1_SERIALDRIVER -# undef CONFIG_STM32L4_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART2) -# undef CONFIG_STM32L4_USART2_SERIALDRIVER -# undef CONFIG_STM32L4_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART3) -# undef CONFIG_STM32L4_USART3_SERIALDRIVER -# undef CONFIG_STM32L4_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART4) -# undef CONFIG_STM32L4_UART4_SERIALDRIVER -# undef CONFIG_STM32L4_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART5) -# undef CONFIG_STM32L4_UART5_SERIALDRIVER -# undef CONFIG_STM32L4_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L4_LPUART1) || defined(CONFIG_STM32L4_USART1) || \ - defined(CONFIG_STM32L4_USART2) || defined(CONFIG_STM32L4_USART3) || \ - defined(CONFIG_STM32L4_UART4) || defined(CONFIG_STM32L4_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -111,7 +111,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -119,7 +119,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -135,7 +135,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -143,7 +143,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -177,27 +177,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -230,17 +230,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -304,4 +304,4 @@ void stm32l4_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32L4_STM32L4_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_UART_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c index ef9d52da06400..eb955770cb610 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32l4_memorymap.h" #include "stm32l4_uid.h" -#ifdef STM32L4_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32l4_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L4_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32L4_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h index a9b1cf4027f6b..935c67074bcbf 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.h +++ b/arch/arm/src/stm32l4/stm32l4_uid.h @@ -35,8 +35,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_UID_H +#define __ARCH_ARM_SRC_STM32L4_STM32_UID_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ void stm32l4_get_uniqueid(uint8_t uniqueid[12]); -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_UID_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index f3424f388a3e5..fd08208479c4a 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -49,7 +49,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USBFS) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,22 +70,22 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32L4_USBDEV_REGDEBUG +# undef CONFIG_STM32_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ -#define STM32L4_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) /* Endpoint identifiers. The STM32L4 supports up to 16 mono-directional or 8 * bidirectional endpoints. However, when you take into account PMA buffer * usage (see below) and the fact that EP0 is bidirectional, then there is * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32L4_NENDPOINTS to be 8, however, because that is how many + * define STM32_NENDPOINTS to be 8, however, because that is how many * endpoint register sets there are. */ -#define STM32L4_NENDPOINTS (8) +#define STM32_NENDPOINTS (8) #define EP0 (0) #define EP1 (1) #define EP2 (2) @@ -95,47 +95,47 @@ #define EP6 (6) #define EP7 (7) -#define STM32L4_ENDP_BIT(ep) (1 << (ep)) -#define STM32L4_ENDP_ALLSET 0xff +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff /* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ -#define STM32L4_MAXPACKET_SHIFT (6) -#define STM32L4_MAXPACKET_SIZE (1 << (STM32L4_MAXPACKET_SHIFT)) -#define STM32L4_MAXPACKET_MASK (STM32L4_MAXPACKET_SIZE-1) +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) -#define STM32L4_EP0MAXPACKET STM32L4_MAXPACKET_SIZE +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE /* Buffer descriptor table. * The buffer table is positioned at the beginning of the 1024-byte - * USB memory. We will use the first STM32L4_NENDPOINTS*8 bytes for + * USB memory. We will use the first STM32_NENDPOINTS*8 bytes for * the buffer table. That is exactly 64 bytes, leaving 15*64 bytes for * endpoint buffers. */ -#define STM32L4_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB * RAM */ -#define STM32L4_DESC_SIZE (8) /* Each descriptor is 4*2=8 +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 * bytes in size */ -#define STM32L4_BTABLE_SIZE (STM32L4_NENDPOINTS*STM32L4_DESC_SIZE) +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) /* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), * then we have space for only 7 buffers; endpoint 0 will require two * buffers, leaving 5 for other endpoints. */ -#define STM32L4_BUFFER_START STM32L4_BTABLE_SIZE -#define STM32L4_EP0_RXADDR STM32L4_BUFFER_START -#define STM32L4_EP0_TXADDR (STM32L4_EP0_RXADDR+STM32L4_EP0MAXPACKET) +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) -#define STM32L4_BUFFER_EP0 0x03 -#define STM32L4_NBUFFERS 7 -#define STM32L4_BUFFER_BIT(bn) (1 << (bn)) -#define STM32L4_BUFFER_ALLSET 0x7f -#define STM32L4_BUFNO2BUF(bn) (STM32L4_BUFFER_START+((bn)<ep.eplog)); /* Save the result in the request structure */ @@ -1333,7 +1333,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, * requests to send. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); return -ENOENT; } @@ -1449,7 +1449,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUTDATA), readlen); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); stm32l4_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ @@ -1482,7 +1482,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, * soon. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTQEMPTY), epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); return -ENOENT; } @@ -1493,7 +1493,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_reqcomplete(privep, OK); return OK; } @@ -1556,7 +1556,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { int ret; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1567,7 +1567,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1584,7 +1584,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32L4_USB_EPR(epno)); + epr = stm32l4_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1594,7 +1594,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); /* Handle read requests. First check if a read request is available to * accept the host data. @@ -1618,7 +1618,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if (stm32l4_rqempty(privep)) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions @@ -1648,7 +1648,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear interrupt status */ stm32l4_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ @@ -1678,7 +1678,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set address in every allocated endpoint */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { if (stm32l4_epreserved(priv, epno)) { @@ -1688,7 +1688,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32L4_USB_DADDR); + stm32l4_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** @@ -1755,7 +1755,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUT), len.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); /* At this point priv->ctrl is the setup packet. */ @@ -1772,7 +1772,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_NOSTDREQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); /* Let the class implementation handle all non-standar requests */ @@ -1795,12 +1795,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } else @@ -1810,12 +1810,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno); - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), + STM32_TRACEERR_BADEPGETSTATUS), epno); priv->ep0state = EP0STATE_STALLED; } @@ -1855,7 +1855,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (index.w == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ @@ -1869,7 +1869,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1878,7 +1878,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IFGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ @@ -1887,7 +1887,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } break; @@ -1904,7 +1904,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) @@ -1921,7 +1921,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Endpoint recipient */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1930,7 +1930,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1946,7 +1946,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type); if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) @@ -1970,7 +1970,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Handler recipient=endpoint */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1979,7 +1979,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1994,13 +1994,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPSETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -2026,7 +2026,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type); /* The request seems valid... @@ -2046,7 +2046,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2061,7 +2061,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2075,7 +2075,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) @@ -2089,7 +2089,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2112,7 +2112,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); stm32l4_dispatchrequest(priv); handled = true; @@ -2127,13 +2127,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); priv->ep0state = EP0STATE_STALLED; } @@ -2288,7 +2288,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 IN: device-to-host (DIR=0) */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0IN), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2296,7 +2296,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32L4_USB_EPR(EP0)); + epr = stm32l4_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2304,7 +2304,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0INDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2315,7 +2315,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0setup(priv); } @@ -2326,7 +2326,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0OUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0out(priv); } @@ -2335,14 +2335,14 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0BADCTR), epr); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); return; /* Does this ever happen? */ } } /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2359,7 +2359,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if (priv->ep0state == EP0STATE_STALLED) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); priv->rxstatus = USB_EPR_STATRX_STALL; priv->txstatus = USB_EPR_STATTX_STALL; @@ -2394,9 +2394,9 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32L4_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32l4_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32L4_USB_ISTR); + stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2430,9 +2430,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) */ struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32L4_USB_ISTR); + uint16_t istr = stm32l4_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USBINTERRUPT), istr); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); /* Handle Reset interrupts. When this event occurs, the peripheral is left * in the same conditions it is left by the system reset (but with the @@ -2443,8 +2443,8 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RESET), istr); + stm32l4_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. @@ -2464,9 +2464,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WKUP), - stm32l4_getreg(STM32L4_USB_FNR)); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32l4_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ @@ -2480,28 +2480,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSP), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); stm32l4_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ESOF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); stm32l4_esofpoll(priv); } @@ -2509,13 +2509,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Low priority endpoint correct transfer interrupt */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_USBCTR), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); stm32l4_lptransfer(priv); } out: - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32L4_USB_EP0R)); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), + stm32l4_getreg(STM32_USB_EP0R)); return OK; } @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2567,15 +2567,15 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) */ stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,9 +2586,9 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend @@ -2616,9 +2616,9 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ @@ -2626,7 +2626,7 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32L4_CNTR_SETUP, STM32L4_USB_CNTR); + stm32l4_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,9 +2666,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable @@ -2677,7 +2677,7 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2711,9 +2711,9 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) * (skipping EP0) */ - for (epndx = 1; epndx < STM32L4_NENDPOINTS; epndx++) + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - uint8_t bit = STM32L4_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2741,7 +2741,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); leave_critical_section(flags); } @@ -2752,7 +2752,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, static inline bool stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) { - return ((priv->epavail & STM32L4_ENDP_BIT(epno)) == 0); + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** @@ -2766,11 +2766,11 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) int bufndx; flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32L4_NBUFFERS; bufndx++) + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) { /* Check if this buffer is available */ - uint8_t bit = STM32L4_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2796,7 +2796,7 @@ static inline void stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(privep->bufno); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); leave_critical_section(flags); } @@ -2821,7 +2821,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !desc) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p desc=%p\n", ep, desc); return -EINVAL; } @@ -2855,7 +2855,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPTYPE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } @@ -2865,12 +2865,12 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Get the address of the PMA buffer allocated for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32L4_BUFNO2BUF(privep->bufno); + pma = STM32_BUFNO2BUF(privep->bufno); /* Get the maxpacket size of the endpoint. */ maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32L4_MAXPACKET_SIZE); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); ep->maxpacket = maxpacket; /* Get the subset matching the requested direction */ @@ -2918,7 +2918,7 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p\n", ep); return -EINVAL; } @@ -2953,7 +2953,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -2963,7 +2963,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -2983,7 +2983,7 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3009,7 +3009,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -3022,7 +3022,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; @@ -3123,7 +3123,7 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3151,7 +3151,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3180,7 +3180,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (status == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPDISABLED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); if (epno == 0) { @@ -3291,14 +3291,14 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, { struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; struct stm32l4_ep_s *privep = NULL; - uint8_t epset = STM32L4_ENDP_ALLSET; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -3319,9 +3319,9 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * by the hardware. */ - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), (uint16_t)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3330,7 +3330,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * the IN/OUT pair for this logical address. */ - epset = STM32L4_ENDP_BIT(epno); + epset = STM32_ENDP_BIT(epno); } /* Check if the selected endpoint number is available */ @@ -3338,7 +3338,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, privep = stm32l4_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPRESERVE), (uint16_t)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } @@ -3348,7 +3348,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, bufno = stm32l4_epallocpma(priv); if (bufno < 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPBUFFER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } @@ -3373,7 +3373,7 @@ static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_USB if (!dev || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3405,14 +3405,14 @@ static int stm32l4_getframe(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32L4_USB_FNR); + fnr = stm32l4_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } @@ -3430,7 +3430,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3450,7 +3450,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } @@ -3468,7 +3468,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_USB_BCDR); + regval = stm32l4_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32L4_USB_BCDR); + stm32l4_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3526,7 +3526,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3542,7 +3542,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Reset endpoints */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { struct stm32l4_ep_s *privep = &priv->eplist[epno]; @@ -3578,24 +3578,24 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32L4_USB_CNTR); + stm32l4_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32L4_BTABLE_ADDRESS & 0xfff8, STM32L4_USB_BTABLE); + stm32l4_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32L4_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32L4_EP0_TXADDR); + stm32l4_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32l4_seteptxaddr(EP0, STM32_EP0_TXADDR); stm32l4_clrstatusout(EP0); stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); @@ -3605,12 +3605,12 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32L4_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32L4_CNTR_SETUP)); + stm32l4_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); stm32l4_dumpep(EP0); } @@ -3626,7 +3626,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. @@ -3642,12 +3642,12 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32L4_ENDP_ALLSET & ~STM32L4_ENDP_BIT(EP0); - priv->bufavail = STM32L4_BUFFER_ALLSET & ~STM32L4_BUFFER_EP0; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; /* Initialize the endpoint list */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -3664,13 +3664,13 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * packet size can be selected when the endpoint is configured. */ - priv->eplist[epno].ep.maxpacket = STM32L4_MAXPACKET_SIZE; + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; } /* Select a smaller endpoint size for EP0 */ -#if STM32L4_EP0MAXPACKET < STM32L4_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32L4_EP0MAXPACKET; +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; #endif /* Configure the USB controller. USB uses the following GPIO pins: @@ -3691,7 +3691,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } @@ -3705,11 +3705,11 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ @@ -3717,7 +3717,7 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3757,10 +3757,10 @@ void arm_usbinitialize(void) * driver is bound. */ - if (irq_attach(STM32L4_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32L4_IRQ_USB_FS); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB_FS); arm_usbuninitialize(); } } @@ -3788,12 +3788,12 @@ void arm_usbuninitialize(void) /* Disable and detach the USB IRQ */ - up_disable_irq(STM32L4_IRQ_USB_FS); - irq_detach(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); + irq_detach(STM32_IRQ_USB_FS); if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -3833,13 +3833,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3853,7 +3853,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); } else { @@ -3865,7 +3865,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* Enable USB controller interrupt at the NVIC */ - up_enable_irq(STM32L4_IRQ_USB_FS); + up_enable_irq(STM32_IRQ_USB_FS); /* Enable pull-up to connect the device. * The host should enumerate us some time after this @@ -3904,7 +3904,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3922,7 +3922,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupt (but keep attached) */ - up_disable_irq(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up * in the reset state (this is probably not necessary, the stm32l4_reset() @@ -3939,4 +3939,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32L4_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.h b/arch/arm/src/stm32l4/stm32l4_usbdev.h index 97492ddf7d73b..e20b4be89ca85 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H +#define __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -68,4 +68,4 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index f0446e960db93..98d04ef5a5377 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H +#define __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H /**************************************************************************** * Included Files @@ -34,11 +34,11 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -134,21 +134,21 @@ enum usbhost_trace1codes_e * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. */ @@ -204,5 +204,5 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS && CONFIG_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H */ +#endif /* CONFIG_STM32_OTGFS && CONFIG_USBHOST */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.h b/arch/arm/src/stm32l4/stm32l4_userspace.h index f965dc09ffd8d..df0479c82b519 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.h +++ b/arch/arm/src/stm32l4/stm32l4_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ void stm32l4_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h index bc24eff6c3990..f0c9df7cd3fbe 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ b/arch/arm/src/stm32l4/stm32l4_waste.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H /* Waste CPU Time */ @@ -63,4 +63,4 @@ void stm32l4_waste(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WASTE_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index 1e2a8e1dbdd3f..e09421158406a 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32_WDG_H +#define __ARCH_ARM_SRC_STM32L4_STM32_WDG_H /**************************************************************************** * Included Files @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG +#ifdef CONFIG_STM32_IWDG void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_WWDG +#ifdef CONFIG_STM32_WWDG void stm32l4_wwdginitialize(const char *devpath); #endif @@ -103,4 +103,4 @@ void stm32l4_wwdginitialize(const char *devpath); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_WDG_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32_WDG_H */ diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 31e48e84d61aa..6c9d589242d2e 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,33 +128,33 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -173,50 +173,50 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif /* These chips have no GPIOF, GPIOG or GPIOI */ -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -235,15 +235,15 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -262,100 +262,100 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR1_USBFSEN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -369,55 +369,55 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -436,9 +436,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -446,61 +446,61 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -520,47 +520,47 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -572,20 +572,20 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -600,18 +600,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32l4_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -619,7 +619,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -628,17 +628,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -649,10 +649,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -660,7 +660,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -668,12 +668,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -681,7 +681,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -705,154 +705,154 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -861,35 +861,35 @@ static void stm32l4_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -914,14 +914,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -939,10 +939,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index b6c1903edd909..9eae8bc68ff38 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -74,33 +74,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -119,33 +119,33 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -164,55 +164,55 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -231,21 +231,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -264,99 +264,99 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; @@ -368,49 +368,49 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -429,9 +429,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -439,79 +439,79 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -531,53 +531,53 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -590,18 +590,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32l4_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -609,7 +609,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -618,17 +618,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -639,10 +639,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -650,7 +650,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -658,12 +658,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -671,7 +671,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -695,154 +695,154 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -851,35 +851,35 @@ static void stm32l4_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -904,14 +904,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 355b3929c1ddc..565ddbf5a61bd 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -48,7 +48,7 @@ ****************************************************************************/ #define DMA1_NCHANNELS 7 -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NCHANNELS 7 # define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) #else @@ -86,88 +86,88 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 { .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -226,17 +226,17 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan)); } @@ -256,19 +256,19 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the channel structure from the interrupt number */ - if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - chndx = irq - STM32L4_IRQ_DMA1CH1; + chndx = irq - STM32_IRQ_DMA1CH1; } else -#if STM32L4_NDMA > 1 - if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - chndx = irq - STM32L4_IRQ_DMA2CH1 + DMA1_NCHANNELS; + chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - chndx = irq - STM32L4_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; + chndx = irq - STM32_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; } #endif else @@ -280,7 +280,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); /* Invoke the callback */ @@ -293,7 +293,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -457,28 +457,28 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * disabled. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -486,7 +486,7 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * interrupt after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -494,14 +494,14 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* define peripheral indicated in dmach->function */ - regval = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); regval &= ~(0x0f << (dmach->chan << 2)); regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32L4_DMA_CSELR_OFFSET, regval); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); } /**************************************************************************** @@ -534,7 +534,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -567,7 +567,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -604,7 +604,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - return dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -621,7 +621,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; @@ -667,22 +667,22 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) /* Verify that the transfer is to a memory region that supports DMA. */ - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_FSMC_BANK4: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -715,12 +715,12 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET); - regs->cselr = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); - regs->ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); leave_critical_section(flags); } #endif @@ -745,16 +745,16 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, dmainfo("DMA Registers: %s\n", msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 1673c9a2abd16..8b5984d6294ca 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,39 +128,39 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -179,76 +179,76 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -267,21 +267,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -300,118 +300,118 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN 2 clock enable */ regval |= RCC_APB1ENR1_CAN2EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -425,55 +425,55 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -492,9 +492,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -502,79 +502,79 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -594,66 +594,66 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -668,7 +668,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32l4_stdclockconfig(void) { uint32_t regval; @@ -683,29 +683,29 @@ static void stm32l4_stdclockconfig(void) * and freq */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Wait until the requested number of wait states is set */ - while ((getreg32(STM32L4_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != + while ((getreg32(STM32_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != FLASH_ACR_LATENCY_4) { } /* Proceed to clock configuration */ -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -713,7 +713,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -722,17 +722,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -743,18 +743,18 @@ static void stm32l4_stdclockconfig(void) /* Choose MSI frequency */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); + putreg32(regval, STM32_RCC_CR); if (!(regval & RCC_CR_MSION)) { /* Enable MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -762,7 +762,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -771,12 +771,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -784,7 +784,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -804,7 +804,7 @@ static void stm32l4_stdclockconfig(void) if (timeout > 0) { - if (STM32L4_SYSCLK_FREQUENCY > 24000000ul) + if (STM32_SYSCLK_FREQUENCY > 24000000ul) { /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. @@ -828,192 +828,192 @@ static void stm32l4_stdclockconfig(void) /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif /* Use the main PLL as SYSCLK, so enable it first */ - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif /* Select the system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL regval |= RCC_CFGR_SW_PLL; -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI regval |= RCC_CFGR_SW_MSI; -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI regval |= RCC_CFGR_SW_HSI; -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE regval |= RCC_CFGR_SW_HSE; #endif - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != -#ifndef STM32L4_BOARD_NOPLL + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != +#ifndef STM32_BOARD_NOPLL RCC_CFGR_SWS_PLL -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI RCC_CFGR_SWS_MSI -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI RCC_CFGR_SWS_HSI -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE RCC_CFGR_SWS_HSE #endif ) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Enable wake-up to HSI from Stop modes */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval |= RCC_CFGR_STOPWUCK_HSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -1038,14 +1038,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -1063,10 +1063,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 38ecf403e11ac..0627df9e053bc 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -45,23 +45,23 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_DMAMUX -# error "Configuration error, CONFIG_STM32L4_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif -#ifndef CONFIG_STM32L4_DMAMUX1 -# error "Configuration error, CONFIG_STM32L4_DMAMUX1 not defined!" +#ifndef CONFIG_STM32_DMAMUX1 +# error "Configuration error, CONFIG_STM32_DMAMUX1 not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -166,7 +166,7 @@ struct stm32l4_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32l4_dma12_disable(DMA_CHANNEL dmachan); static int stm32l4_dma12_interrupt(int irq, void *context, void *arg); static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -212,7 +212,7 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -232,7 +232,7 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -260,7 +260,7 @@ static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32L4_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -271,7 +271,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32L4_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -281,7 +281,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32L4_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -293,123 +293,123 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { .ctrl = DMA1, .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { .ctrl = DMA2, .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -571,7 +571,7 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32l4_dma12_disable @@ -589,17 +589,17 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -623,22 +623,22 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32L4_DMA1 - else if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32L4_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32L4_DMA2 - else if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32L4_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32L4_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -654,7 +654,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -667,7 +667,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -696,7 +696,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -704,28 +704,28 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -733,7 +733,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -741,7 +741,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -769,7 +769,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -803,7 +803,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -816,7 +816,7 @@ static size_t stm32l4_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -831,11 +831,11 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -864,19 +864,19 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -885,7 +885,7 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32L4_DMA1 || CONFIG_STM32L4_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32l4_dmamux_sample @@ -895,13 +895,13 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32l4_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -915,20 +915,20 @@ static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1186,7 +1186,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1231,7 +1231,7 @@ void stm32l4_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1277,7 +1277,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; @@ -1322,23 +1322,23 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_QSPI_BANK: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_SRAM3_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 0add98c900356..e420f09624e04 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,45 +128,45 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -185,82 +185,82 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -279,15 +279,15 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,106 +306,106 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -419,49 +419,49 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -480,9 +480,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -490,73 +490,73 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -576,54 +576,54 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* Some peripherals have their clock selection in CCIPR2 register. */ - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); -#if defined(STM32L4_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; @@ -631,7 +631,7 @@ static inline void rcc_enableccip(void) #endif #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SAI1 as DFSDM audio clock source. */ regval &= ~RCC_CCIPR2_ADFSDMSEL_MASK; @@ -642,7 +642,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR2_DFSDMSEL_PCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); } /**************************************************************************** @@ -655,18 +655,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32l4_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -674,7 +674,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -683,17 +683,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -705,10 +705,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -716,7 +716,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -724,12 +724,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -737,7 +737,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -760,9 +760,9 @@ static void stm32l4_stdclockconfig(void) #warning todo: regulator voltage according to clock freq /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Switch to Range 1 boost mode to support system frequencies up to * 120 MHz. @@ -772,147 +772,147 @@ static void stm32l4_stdclockconfig(void) * Range 2 is not supported. */ -#if STM32L4_SYSCLK_FREQUENCY > 80000000 || \ +#if STM32_SYSCLK_FREQUENCY > 80000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 80000000) - regval = getreg32(STM32L4_PWR_CR5); + regval = getreg32(STM32_PWR_CR5); regval &= ~PWR_CR5_R1MODE; - putreg32(regval, STM32L4_PWR_CR5); + putreg32(regval, STM32_PWR_CR5); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -927,34 +927,34 @@ static void stm32l4_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -969,14 +969,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -994,10 +994,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l5/chip.h b/arch/arm/src/stm32l5/chip.h index a8a0ea513909d..33c22b102cab3 100644 --- a/arch/arm/src/stm32l5/chip.h +++ b/arch/arm/src/stm32l5/chip.h @@ -48,6 +48,6 @@ * arch/stm32l5/chip.h header file. */ -#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS +#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS #endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index 9f1f886562999..64d4f7215e239 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -37,89 +37,89 @@ /* Register Offsets *********************************************************/ -#define STM32L5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L5_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L5_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L5_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L5_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ -#define STM32L5_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ -#define STM32L5_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ -#define STM32L5_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ -#define STM32L5_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ -#define STM32L5_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ -#define STM32L5_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ -#define STM32L5_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ -#define STM32L5_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ +#define STM32_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ +#define STM32_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ +#define STM32_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ +#define STM32_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ +#define STM32_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ +#define STM32_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ +#define STM32_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ /* Register Addresses *******************************************************/ -#define STM32L5_RCC_CR (STM32L5_RCC_BASE + STM32L5_RCC_CR_OFFSET) -#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE + STM32L5_RCC_ICSCR_OFFSET) -#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE + STM32L5_RCC_CFGR_OFFSET) -#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLCFG_OFFSET) -#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI1CFG_OFFSET) -#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI2CFG_OFFSET) -#define STM32L5_RCC_CIER (STM32L5_RCC_BASE + STM32L5_RCC_CIER_OFFSET) -#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE + STM32L5_RCC_CIFR_OFFSET) -#define STM32L5_RCC_CICR (STM32L5_RCC_BASE + STM32L5_RCC_CICR_OFFSET) -#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1RSTR_OFFSET) -#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2RSTR_OFFSET) -#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3RSTR_OFFSET) -#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR1_OFFSET) -#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR2_OFFSET) -#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_APB2RSTR_OFFSET) -#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1ENR_OFFSET) -#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2ENR_OFFSET) -#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3ENR_OFFSET) -#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR1_OFFSET) -#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR2_OFFSET) -#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2ENR_OFFSET) -#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SMENR_OFFSET) -#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SMENR_OFFSET) -#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SMENR_OFFSET) -#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR1_OFFSET) -#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR2_OFFSET) -#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SMENR_OFFSET) -#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR_OFFSET) -#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE + STM32L5_RCC_BDCR_OFFSET) -#define STM32L5_RCC_CSR (STM32L5_RCC_BASE + STM32L5_RCC_CSR_OFFSET) -#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE + STM32L5_RCC_CRRCR_OFFSET) -#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR2_OFFSET) -#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE + STM32L5_RCC_SECCFGR_OFFSET) -#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE + STM32L5_RCC_SECSR_OFFSET) -#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SECSR_OFFSET) -#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SECSR_OFFSET) -#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SECSR_OFFSET) -#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR1_OFFSET) -#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR2_OFFSET) -#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SECSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_SECSR (STM32_RCC_BASE + STM32_RCC_SECSR_OFFSET) +#define STM32_RCC_AHB1SECSR (STM32_RCC_BASE + STM32_RCC_AHB1SECSR_OFFSET) +#define STM32_RCC_AHB2SECSR (STM32_RCC_BASE + STM32_RCC_AHB2SECSR_OFFSET) +#define STM32_RCC_AHB3SECSR (STM32_RCC_BASE + STM32_RCC_AHB3SECSR_OFFSET) +#define STM32_RCC_APB1SECSR1 (STM32_RCC_BASE + STM32_RCC_APB1SECSR1_OFFSET) +#define STM32_RCC_APB1SECSR2 (STM32_RCC_BASE + STM32_RCC_APB1SECSR2_OFFSET) +#define STM32_RCC_APB2SECSR (STM32_RCC_BASE + STM32_RCC_APB2SECSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -865,5 +865,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h index db365f949741f..9d900a32adf54 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -38,31 +38,31 @@ /* Register Offsets *********************************************************/ -#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SECCFGR_OFFSET) -#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR1_OFFSET) -#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_FPUIMR_OFFSET) -#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CNSLCKR_OFFSET) -#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CSLCKR_OFFSET) -#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR2_OFFSET) -#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SCSR_OFFSET) -#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SKR_OFFSET) -#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR_OFFSET) -#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR2_OFFSET) -#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -133,5 +133,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h index b321ad3f4cc7f..c7ecf0f23cb58 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -36,55 +36,55 @@ /* Register Offsets *********************************************************/ -#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ -#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ -#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ -#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ +#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ +#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ +#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ +#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ +#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ +#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ +#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ /* Register Addresses *******************************************************/ -#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR1_OFFSET) -#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR1_OFFSET) -#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER1_OFFSET) -#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR1_OFFSET) -#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR1_OFFSET) -#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR1_OFFSET) -#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR1_OFFSET) -#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR2_OFFSET) -#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR2_OFFSET) -#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER2_OFFSET) -#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR2_OFFSET) -#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR2_OFFSET) -#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR2_OFFSET) -#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR2_OFFSET) -#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR1_OFFSET) -#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR2_OFFSET) -#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR3_OFFSET) -#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR4_OFFSET) -#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE + STM32L5_EXTI_LOCKR_OFFSET) -#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR1_OFFSET) -#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR1_OFFSET) -#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR2_OFFSET) -#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) +#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) +#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) +#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) +#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) +#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) +#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) +#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) +#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) +#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) +#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) +#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) +#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) +#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -118,4 +118,4 @@ #define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */ #define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index 3f9c343e0e7f7..a5618fbecc200 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H /**************************************************************************** * Included Files @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32L5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32L552xC and STM32L562xC have 256Kb of FLASH * Parts STM32L552xE and STM32L562xE have 512Kb of FLASH @@ -46,114 +46,114 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_E) -# define CONFIG_STM32L5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L5_FLASH_CONFIG_C -# undef CONFIG_STM32L5_FLASH_CONFIG_E -# if defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) -# define CONFIG_STM32L5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) -# define CONFIG_STM32L5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L5_FLASH_NPAGES 64 -# define STM32L5_FLASH_PAGESIZE 4096 -#elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L5_FLASH_NPAGES 128 -# define STM32L5_FLASH_PAGESIZE 4096 +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 4096 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L5_FLASH_PAGESIZE -# define STM32L5_FLASH_SIZE (STM32L5_FLASH_NPAGES * STM32L5_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L5_FLASH_ACR_OFFSET 0x0000 -#define STM32L5_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L5_FLASH_NSKEYR_OFFSET 0x0008 -#define STM32L5_FLASH_SECKEYR_OFFSET 0x000c -#define STM32L5_FLASH_OPTKEYR_OFFSET 0x0010 -#define STM32L5_FLASH_LVEKEYR_OFFSET 0x0014 -#define STM32L5_FLASH_NSSR_OFFSET 0x0020 -#define STM32L5_FLASH_SECSR_OFFSET 0x0024 -#define STM32L5_FLASH_NSCR_OFFSET 0x0028 -#define STM32L5_FLASH_SECCR_OFFSET 0x002c -#define STM32L5_FLASH_ECCR_OFFSET 0x0030 -#define STM32L5_FLASH_OPTR_OFFSET 0x0040 -#define STM32L5_FLASH_NSBOOTADDR0R_OFFSET 0x0044 -#define STM32L5_FLASH_NSBOOTADDR1R_OFFSET 0x0048 -#define STM32L5_FLASH_SECBOOTADDR0R_OFFSET 0x004c -#define STM32L5_FLASH_SECWM1R1_OFFSET 0x0050 -#define STM32L5_FLASH_SECWM1R2_OFFSET 0x0054 -#define STM32L5_FLASH_WRP1AR_OFFSET 0x0058 -#define STM32L5_FLASH_WRP1BR_OFFSET 0x005c -#define STM32L5_FLASH_SECWM2R1_OFFSET 0x0060 -#define STM32L5_FLASH_SECWM2R2_OFFSET 0x0064 -#define STM32L5_FLASH_WRP2AR_OFFSET 0x0068 -#define STM32L5_FLASH_WRP2BR_OFFSET 0x006c -#define STM32L5_FLASH_SECBB1R1_OFFSET 0x0080 -#define STM32L5_FLASH_SECBB1R2_OFFSET 0x0084 -#define STM32L5_FLASH_SECBB1R3_OFFSET 0x0088 -#define STM32L5_FLASH_SECBB1R4_OFFSET 0x008c -#define STM32L5_FLASH_SECBB2R1_OFFSET 0x00a0 -#define STM32L5_FLASH_SECBB2R2_OFFSET 0x00a4 -#define STM32L5_FLASH_SECBB2R3_OFFSET 0x00a8 -#define STM32L5_FLASH_SECBB2R4_OFFSET 0x00ac -#define STM32L5_FLASH_SECHDPCR_OFFSET 0x00c0 -#define STM32L5_FLASH_PRIVCFGR_OFFSET 0x00c4 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_NSKEYR_OFFSET 0x0008 +#define STM32_FLASH_SECKEYR_OFFSET 0x000c +#define STM32_FLASH_OPTKEYR_OFFSET 0x0010 +#define STM32_FLASH_LVEKEYR_OFFSET 0x0014 +#define STM32_FLASH_NSSR_OFFSET 0x0020 +#define STM32_FLASH_SECSR_OFFSET 0x0024 +#define STM32_FLASH_NSCR_OFFSET 0x0028 +#define STM32_FLASH_SECCR_OFFSET 0x002c +#define STM32_FLASH_ECCR_OFFSET 0x0030 +#define STM32_FLASH_OPTR_OFFSET 0x0040 +#define STM32_FLASH_NSBOOTADDR0R_OFFSET 0x0044 +#define STM32_FLASH_NSBOOTADDR1R_OFFSET 0x0048 +#define STM32_FLASH_SECBOOTADDR0R_OFFSET 0x004c +#define STM32_FLASH_SECWM1R1_OFFSET 0x0050 +#define STM32_FLASH_SECWM1R2_OFFSET 0x0054 +#define STM32_FLASH_WRP1AR_OFFSET 0x0058 +#define STM32_FLASH_WRP1BR_OFFSET 0x005c +#define STM32_FLASH_SECWM2R1_OFFSET 0x0060 +#define STM32_FLASH_SECWM2R2_OFFSET 0x0064 +#define STM32_FLASH_WRP2AR_OFFSET 0x0068 +#define STM32_FLASH_WRP2BR_OFFSET 0x006c +#define STM32_FLASH_SECBB1R1_OFFSET 0x0080 +#define STM32_FLASH_SECBB1R2_OFFSET 0x0084 +#define STM32_FLASH_SECBB1R3_OFFSET 0x0088 +#define STM32_FLASH_SECBB1R4_OFFSET 0x008c +#define STM32_FLASH_SECBB2R1_OFFSET 0x00a0 +#define STM32_FLASH_SECBB2R2_OFFSET 0x00a4 +#define STM32_FLASH_SECBB2R3_OFFSET 0x00a8 +#define STM32_FLASH_SECBB2R4_OFFSET 0x00ac +#define STM32_FLASH_SECHDPCR_OFFSET 0x00c0 +#define STM32_FLASH_PRIVCFGR_OFFSET 0x00c4 /* Register Addresses *******************************************************/ -#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ACR_OFFSET) -#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PDKEYR_OFFSET) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSKEYR_OFFSET) -#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECKEYR_OFFSET) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTKEYR_OFFSET) -#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_LVEKEYR_OFFSET) -#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSSR_OFFSET) -#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECSR_OFFSET) -#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSCR_OFFSET) -#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECCR_OFFSET) -#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ECCR_OFFSET) -#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTR_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR1R_OFFSET) -#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R1_OFFSET) -#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R2_OFFSET) -#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1AR_OFFSET) -#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1BR_OFFSET) -#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R1_OFFSET) -#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R2_OFFSET) -#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2AR_OFFSET) -#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2BR_OFFSET) -#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R1_OFFSET) -#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R2_OFFSET) -#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R3_OFFSET) -#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R4_OFFSET) -#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R1_OFFSET) -#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R2_OFFSET) -#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R3_OFFSET) -#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R4_OFFSET) -#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECHDPCR_OFFSET) -#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PRIVCFGR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET) +#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_LVEKEYR (STM32_FLASHIF_BASE + STM32_FLASH_LVEKEYR_OFFSET) +#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET) +#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET) +#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET) +#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_NSBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR0R_OFFSET) +#define STM32_FLASH_NSBOOTADDR1R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR1R_OFFSET) +#define STM32_FLASH_SECBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTADDR0R_OFFSET) +#define STM32_FLASH_SECWM1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R1_OFFSET) +#define STM32_FLASH_SECWM1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R2_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_SECWM2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R1_OFFSET) +#define STM32_FLASH_SECWM2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R2_OFFSET) +#define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2AR_OFFSET) +#define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_SECBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R1_OFFSET) +#define STM32_FLASH_SECBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R2_OFFSET) +#define STM32_FLASH_SECBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R3_OFFSET) +#define STM32_FLASH_SECBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R4_OFFSET) +#define STM32_FLASH_SECBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R1_OFFSET) +#define STM32_FLASH_SECBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R2_OFFSET) +#define STM32_FLASH_SECBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R3_OFFSET) +#define STM32_FLASH_SECBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R4_OFFSET) +#define STM32_FLASH_SECHDPCR (STM32_FLASHIF_BASE + STM32_FLASH_SECHDPCR_OFFSET) +#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -259,4 +259,4 @@ #define FLASH_OPTR_RDP_NSDBG (0x55 << FLASH_OPTR_RDP_SHIFT) #define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h index 0037ae1ad08d3..d5b62cbf07ade 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ /* Register Addresses *******************************************************/ -#if STM32L5_NPORTS > 0 -# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 1 -# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 2 -# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 3 -# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 4 -# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 5 -# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 6 -# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 7 -# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 8 -# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -386,4 +386,4 @@ #define GPIO_SECCFGR_SET(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h index 4fefb89201fed..302e8426cb9b6 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,127 +29,127 @@ /* STM32L5XXX Address Blocks ************************************************/ -#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ -#define STM32L5_REGION_MASK 0xF0000000 -#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE) -#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1) +#define STM32_REGION_MASK 0xF0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ -#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ -#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ +#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ -#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ -#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ +#define STM32_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ +#define STM32_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ /* Peripheral Base Addresses ************************************************/ -#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ -#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ -#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ -#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ -#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ +#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ +#define STM32_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32L5_UCPD1_BASE 0x4000DC00 -#define STM32L5_USB_SRAM_BASE 0x4000D800 -#define STM32L5_USB_FS_BASE 0x4000D400 -#define STM32L5_FDCAN_RAM_BASE 0x4000AC00 -#define STM32L5_FDCAN1_BASE 0x4000A400 -#define STM32L5_LPTIM3_BASE 0x40009800 -#define STM32L5_LPTIM2_BASE 0x40009400 -#define STM32L5_I2C4_BASE 0x40008400 -#define STM32L5_LPUART1_BASE 0x40008000 -#define STM32L5_LPTIM1_BASE 0x40007C00 -#define STM32L5_OPAMP_BASE 0x40007800 -#define STM32L5_DAC_BASE 0x40007400 -#define STM32L5_PWR_BASE 0x40007000 -#define STM32L5_CRS_BASE 0x40006000 -#define STM32L5_I2C3_BASE 0x40005C00 -#define STM32L5_I2C2_BASE 0x40005800 -#define STM32L5_I2C1_BASE 0x40005400 -#define STM32L5_UART5_BASE 0x40005000 -#define STM32L5_UART4_BASE 0x40004C00 -#define STM32L5_USART3_BASE 0x40004800 -#define STM32L5_USART2_BASE 0x40004400 -#define STM32L5_SPI3_BASE 0x40003C00 -#define STM32L5_SPI2_BASE 0x40003800 -#define STM32L5_TAMP_BASE 0x40003400 -#define STM32L5_IWDG_BASE 0x40003000 -#define STM32L5_WWDG_BASE 0x40002C00 -#define STM32L5_RTC_BASE 0x40002800 -#define STM32L5_TIM7_BASE 0x40001400 -#define STM32L5_TIM6_BASE 0x40001000 -#define STM32L5_TIM5_BASE 0x40000C00 -#define STM32L5_TIM4_BASE 0x40000800 -#define STM32L5_TIM3_BASE 0x40000400 -#define STM32L5_TIM2_BASE 0x40000000 +#define STM32_UCPD1_BASE 0x4000DC00 +#define STM32_USB_SRAM_BASE 0x4000D800 +#define STM32_USB_FS_BASE 0x4000D400 +#define STM32_FDCAN_RAM_BASE 0x4000AC00 +#define STM32_FDCAN1_BASE 0x4000A400 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004C00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003C00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_TAMP_BASE 0x40003400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000C00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L5_DFSDM1_BASE 0x40016000 -#define STM32L5_SAI2_BASE 0x40015800 -#define STM32L5_SAI1_BASE 0x40015400 -#define STM32L5_TIM17_BASE 0x40014800 -#define STM32L5_TIM16_BASE 0x40014400 -#define STM32L5_TIM15_BASE 0x40014000 -#define STM32L5_USART1_BASE 0x40013800 -#define STM32L5_TIM8_BASE 0x40013400 -#define STM32L5_SPI1_BASE 0x40013000 -#define STM32L5_TIM1_BASE 0x40012C00 -#define STM32L5_COMP_BASE 0x40010200 -#define STM32L5_VREFBUF_BASE 0x40010100 -#define STM32L5_SYSCFG_BASE 0x40010000 +#define STM32_DFSDM1_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010100 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L5_GTZC_BASE 0x40032400 -#define STM32L5_ICACHE_BASE 0x40030400 -#define STM32L5_EXTI_BASE 0x4002F400 -#define STM32L5_TSC_BASE 0x40024000 -#define STM32L5_CRC_BASE 0x40023000 -#define STM32L5_FLASHIF_BASE 0x40022000 -#define STM32L5_RCC_BASE 0x40021000 -#define STM32L5_DMAMUX1_BASE 0x40020800 -#define STM32L5_DMA2_BASE 0x40020400 -#define STM32L5_DMA1_BASE 0x40020000 +#define STM32_GTZC_BASE 0x40032400 +#define STM32_ICACHE_BASE 0x40030400 +#define STM32_EXTI_BASE 0x4002F400 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_SDMMC1_BASE 0x420C8000 -#define STM32L5_OTFDEC1_BASE 0x420C5000 -#define STM32L5_PKA_BASE 0x420C2000 -#define STM32L5_RNG_BASE 0x420C0800 -#define STM32L5_HASH_BASE 0x420C0400 -#define STM32L5_AES_BASE 0x420C0000 -#define STM32L5_ADC_BASE 0x42028000 -#define STM32L5_GPIOH_BASE 0x42021C00 -#define STM32L5_GPIOG_BASE 0x42021800 -#define STM32L5_GPIOF_BASE 0x42021400 -#define STM32L5_GPIOE_BASE 0x42021000 -#define STM32L5_GPIOD_BASE 0x42020c00 -#define STM32L5_GPIOC_BASE 0x42020800 -#define STM32L5_GPIOB_BASE 0x42020400 -#define STM32L5_GPIOA_BASE 0x42020000 +#define STM32_SDMMC1_BASE 0x420C8000 +#define STM32_OTFDEC1_BASE 0x420C5000 +#define STM32_PKA_BASE 0x420C2000 +#define STM32_RNG_BASE 0x420C0800 +#define STM32_HASH_BASE 0x420C0400 +#define STM32_AES_BASE 0x420C0000 +#define STM32_ADC_BASE 0x42028000 +#define STM32_GPIOH_BASE 0x42021C00 +#define STM32_GPIOG_BASE 0x42021800 +#define STM32_GPIOF_BASE 0x42021400 +#define STM32_GPIOE_BASE 0x42021000 +#define STM32_GPIOD_BASE 0x42020c00 +#define STM32_GPIOC_BASE 0x42020800 +#define STM32_GPIOB_BASE 0x42020400 +#define STM32_GPIOA_BASE 0x42020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_OCTOSPI1_BASE 0x44021000 -#define STM32L5_FMC_BASE 0x44020000 +#define STM32_OCTOSPI1_BASE 0x44021000 +#define STM32_FMC_BASE 0x44020000 -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h index ee73d99996329..6b5c68f40679b 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_pinmap.h" #else # error "Unsupported STM32 L5 pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h index 44cbde1b5985e..f00af0dd57705 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,59 +36,59 @@ /* Register Offsets *********************************************************/ -#define STM32L5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L5_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L5_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L5_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L5_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L5_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L5_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L5_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L5_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L5_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ -#define STM32L5_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ +#define STM32_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ /* Register Addresses *******************************************************/ -#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE + STM32L5_PWR_CR1_OFFSET) -#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE + STM32L5_PWR_CR2_OFFSET) -#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE + STM32L5_PWR_CR3_OFFSET) -#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE + STM32L5_PWR_CR4_OFFSET) -#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE + STM32L5_PWR_SR1_OFFSET) -#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE + STM32L5_PWR_SR2_OFFSET) -#define STM32L5_PWR_SCR (STM32L5_PWR_BASE + STM32L5_PWR_SCR_OFFSET) -#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE + STM32L5_PWR_PUCRA_OFFSET) -#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE + STM32L5_PWR_PDCRA_OFFSET) -#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE + STM32L5_PWR_PUCRB_OFFSET) -#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE + STM32L5_PWR_PDCRB_OFFSET) -#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE + STM32L5_PWR_PUCRC_OFFSET) -#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE + STM32L5_PWR_PDCRC_OFFSET) -#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE + STM32L5_PWR_PUCRD_OFFSET) -#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE + STM32L5_PWR_PDCRD_OFFSET) -#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE + STM32L5_PWR_PUCRE_OFFSET) -#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE + STM32L5_PWR_PDCRE_OFFSET) -#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE + STM32L5_PWR_PUCRF_OFFSET) -#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE + STM32L5_PWR_PDCRF_OFFSET) -#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE + STM32L5_PWR_PUCRG_OFFSET) -#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE + STM32L5_PWR_PDCRG_OFFSET) -#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE + STM32L5_PWR_PUCRH_OFFSET) -#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE + STM32L5_PWR_PDCRH_OFFSET) -#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE + STM32L5_PWR_SECCFGR_OFFSET) -#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE + STM32L5_PWR_PRIVCFGR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -214,4 +214,4 @@ #define PWR_PRIVCFGR_PRIV (1 << 0) /* Bit 0: Privilege protection */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index 91b92dc5a6a65..5f7f9e8abe2be 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H /**************************************************************************** * Included Files @@ -36,52 +36,52 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SPI_CLK_MAX 55000000UL +#if defined(CONFIG_STM32_STM32L562XX) +# define STM32_SPI_CLK_MAX 55000000UL #else # error "Unsupported STM32 L5 chip" #endif /* Register Offsets *********************************************************/ -#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L5_NSPI > 0 -# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 1 -# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 2 -# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -164,4 +164,4 @@ # define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h index c7ad32505500f..dfd8a438db582 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_syscfg.h" #else # error "Unsupported STM32 L5 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 1e99dba009a77..c490bd032aba2 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR3_OFFSET) - -#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE + STM32L5_GTIM_DMAR_OFFSET) - -#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE + STM32L5_GTIM_OR_OFFSET) - -#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE + STM32L5_BTIM_ARR_OFFSET) - -#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE + STM32L5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -1059,4 +1059,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h index b987bc439211e..14113ce50dbe8 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,94 +37,94 @@ /* Register Offsets *********************************************************/ -#define STM32L5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32L5_USART_PRESC_OFFSET 0x002c /* Prescaler register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ /* Register Addresses *******************************************************/ -#if STM32L5_NUSART > 0 -# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART1_BRR (STM32L5_USART1_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART1_RQR (STM32L5_USART1_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART1_ISR (STM32L5_USART1_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART1_ICR (STM32L5_USART1_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART1_RDR (STM32L5_USART1_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART1_TDR (STM32L5_USART1_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 1 -# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART2_BRR (STM32L5_USART2_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART2_RQR (STM32L5_USART2_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART2_ISR (STM32L5_USART2_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART2_ICR (STM32L5_USART2_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART2_RDR (STM32L5_USART2_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART2_TDR (STM32L5_USART2_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 2 -# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART3_BRR (STM32L5_USART3_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART3_RQR (STM32L5_USART3_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART3_ISR (STM32L5_USART3_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART3_ICR (STM32L5_USART3_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART3_RDR (STM32L5_USART3_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART3_TDR (STM32L5_USART3_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 3 -# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART4_BRR (STM32L5_UART4_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART4_RQR (STM32L5_UART4_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART4_ISR (STM32L5_UART4_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART4_ICR (STM32L5_UART4_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART4_RDR (STM32L5_UART4_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART4_TDR (STM32L5_UART4_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 4 -# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART5_BRR (STM32L5_UART5_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART5_RQR (STM32L5_UART5_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART5_ISR (STM32L5_UART5_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART5_ICR (STM32L5_UART5_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART5_RDR (STM32L5_UART5_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART5_TDR (STM32L5_UART5_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -306,4 +306,4 @@ * Public Data ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32l5/stm32l5.h b/arch/arm/src/stm32l5/stm32l5.h index 7cedda9b78c90..4dacd389b6bc3 100644 --- a/arch/arm/src/stm32l5/stm32l5.h +++ b/arch/arm/src/stm32l5/stm32l5.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_H +#define __ARCH_ARM_SRC_STM32L5_STM32_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ #include "stm32l5_uart.h" #include "stm32l5_lowputc.h" -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_H */ diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index b1f582519e6ec..92cabb9d701e6 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -56,13 +56,13 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32L5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32L5_USE_CLK48) -# if STM32L5_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -90,51 +90,51 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L5_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32L5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L5_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L5_GTZCEN +#ifdef CONFIG_STM32_GTZCEN /* TSC clock enable */ regval |= RCC_AHB1ENR_GTZEN; #endif - putreg32(regval, STM32L5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -153,79 +153,79 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); #endif -#if defined(CONFIG_STM32L5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32L5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L5_PKAEN +#ifdef CONFIG_STM32_PKAEN /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32L5_OTFDEC1EN +#ifdef CONFIG_STM32_OTFDEC1EN /* On-the-fly-decryption module clock enable */ regval |= RCC_AHB2ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32L5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1EN /* SDMMC1 clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -244,21 +244,21 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32L5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB3ENR_OSPI1EN; #endif - putreg32(regval, STM32L5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -277,112 +277,112 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L5_RTC +#ifdef CONFIG_STM32_RTC /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#ifdef CONFIG_STM32L5_WWDGEN +#ifdef CONFIG_STM32_WWDGEN /* Windowed Watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L5_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L5_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L5_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32L5_USE_HSI48 - if (STM32L5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -396,73 +396,73 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC1 interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L5_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32L5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; #endif -#ifdef CONFIG_STM32L5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32L5_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR2_USBFSEN; #endif -#ifdef CONFIG_STM32L5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* UCPD1 clock enable */ regval |= RCC_APB1ENR2_UCPD1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -481,9 +481,9 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -491,67 +491,67 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -598,18 +598,18 @@ void stm32l5_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32l5_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32L5_BOARD_USEHSI) || defined(STM32L5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -617,7 +617,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -626,17 +626,17 @@ void stm32l5_stdclockconfig(void) } #endif -#if defined(STM32L5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -647,9 +647,9 @@ void stm32l5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L5_RCC_CR); - regval |= (STM32L5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -657,7 +657,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -665,12 +665,12 @@ void stm32l5_stdclockconfig(void) } } -#elif defined(STM32L5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -678,7 +678,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32L5_BOARD_USEHSI, STM32L5_BOARD_USEMSI, STM32L5_BOARD_USEHSE defined +# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -708,14 +708,14 @@ void stm32l5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32L5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32L5_SYSCLK_FREQUENCY > 80000000) + if (STM32_SYSCLK_FREQUENCY > 80000000) { regval |= PWR_CR1_VOS_RANGE0; } - else if (STM32L5_SYSCLK_FREQUENCY > 26000000) + else if (STM32_SYSCLK_FREQUENCY > 26000000) { regval |= PWR_CR1_VOS_RANGE1; } @@ -724,157 +724,157 @@ void stm32l5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE0; } - putreg32(regval, STM32L5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32L5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L5_RCC_CFGR_HPRE; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L5_RCC_CFGR_PPRE2; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L5_RCC_CFGR_PPRE1; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32L5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32L5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L5_PLLCFG_PLLM | STM32L5_PLLCFG_PLLN | - STM32L5_PLLCFG_PLLP | STM32L5_PLLCFG_PLLQ | - STM32L5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32L5_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L5_PLLSAI1CFG_PLLN | STM32L5_PLLSAI1CFG_PLLP - | STM32L5_PLLSAI1CFG_PLLQ | STM32L5_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L5_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif -#ifdef CONFIG_STM32L5_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L5_PLLSAI2CFG_PLLN | STM32L5_PLLSAI2CFG_PLLP | - STM32L5_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L5_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -882,29 +882,29 @@ void stm32l5_stdclockconfig(void) /* Enable FLASH 5 wait states */ regval = FLASH_ACR_LATENCY_5; - putreg32(regval, STM32L5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l5_rcc_enablelsi(); #endif -#if defined(STM32L5_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -929,14 +929,14 @@ void stm32l5_stdclockconfig(void) stm32l5_rcc_enablelse(); -# if defined(STM32L5_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L5_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 8809fc4a2004f..556a9bf5ae5bc 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L5_FSMC=y : Enables the FSMC - * CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L5_FSMC -# undef CONFIG_STM32L5_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32L5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L5_SRAM3_SIZE -# define SRAM3_START STM32L5_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L5_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -116,15 +116,15 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ - defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -133,10 +133,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32L5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32L5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -312,7 +312,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -332,7 +332,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -352,7 +352,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32L5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h index a6b73b00ad561..ef826e158781e 100644 --- a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h +++ b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -31,10 +31,10 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_dbgmcu.h" #else # error "Unsupported STM32L5 chip" #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index 0c79a6cc60d49..f5dc0ed6ce791 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L5_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L5_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L5_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L5_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L5_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L5_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L5_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L5_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L5_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L5_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L5_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L5_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L5_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l5_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L5_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_MODER_OFFSET), - getreg32(base + STM32L5_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L5_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L5_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_IDR_OFFSET), - getreg32(base + STM32L5_GPIO_ODR_OFFSET), - getreg32(base + STM32L5_GPIO_BSRR_OFFSET), - getreg32(base + STM32L5_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_AFRH_OFFSET), - getreg32(base + STM32L5_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index 7093f76a75edc..bc1ad7da345d4 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H /**************************************************************************** * Included Files @@ -141,7 +141,7 @@ int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_COMP +#ifdef CONFIG_STM32_COMP int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index cc632e2df5ad9..67a6a051e235a 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -72,13 +72,13 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) int ret = OK; int exti; - exti = irq - STM32L5_IRQ_EXTI0; + exti = irq - STM32_IRQ_EXTI0; DEBUGASSERT((exti >= 0) && (exti <= 15)); /* Clear the pending interrupt for both rising and falling edges. */ - putreg32(0x0001 << exti, STM32L5_EXTI_RPR1); - putreg32(0x0001 << exti, STM32L5_EXTI_FPR1); + putreg32(0x0001 << exti, STM32_EXTI_RPR1); + putreg32(0x0001 << exti, STM32_EXTI_FPR1); /* And dispatch the interrupt to the handler */ @@ -125,7 +125,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = 1 << pin; - int irq = STM32L5_IRQ_EXTI0 + pin; + int irq = STM32_IRQ_EXTI0 + pin; g_gpio_handlers[pin].callback = func; g_gpio_handlers[pin].arg = arg; @@ -155,19 +155,19 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L5_EXTI_EMR1, + modifyreg32(STM32_EXTI_EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L5_EXTI_IMR1, + modifyreg32(STM32_EXTI_IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 62f7f86370582..8fdf84590a73c 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -50,11 +50,11 @@ #include "stm32l5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32L5_STM32L562XX) +#if !defined(CONFIG_STM32_STM32L562XX) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -69,7 +69,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -79,7 +79,7 @@ #elif FLASH_PAGE_SIZE == 8192 # define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */ #else -# error Unsupported STM32L5_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -105,35 +105,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L5_FLASH_NSKEYR); - putreg32(FLASH_KEY2, STM32L5_FLASH_NSKEYR); + putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR); + putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR); } } static void flash_lock(void) { - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -150,16 +150,16 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_START); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -214,20 +214,20 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%x\n", (unsigned)regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%x\n", (unsigned)regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } @@ -240,42 +240,42 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L5_FLASH_PAGESIZE + STM32L5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -285,7 +285,7 @@ bool up_progmem_isuniform(void) ssize_t up_progmem_eraseblock(size_t block) { - if (block >= STM32L5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -318,7 +318,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -351,12 +351,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -422,23 +422,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } /* Verify */ - if (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -446,13 +446,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -473,8 +473,8 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%x\n", ret, - (unsigned)getreg32(STM32L5_FLASH_NSSR)); - modifyreg32(STM32L5_FLASH_NSSR, 0, FLASH_SR_ALLERRS); + (unsigned)getreg32(STM32_FLASH_NSSR)); + modifyreg32(STM32_FLASH_NSSR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.h b/arch/arm/src/stm32l5/stm32l5_flash.h index 0a3f7076c9044..f78f510b04d3e 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/stm32l5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H /**************************************************************************** * Included Files @@ -56,4 +56,4 @@ void stm32l5_flash_unlock(void); uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 581a5b6bfc0fc..2d9afa34849a0 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -54,31 +54,31 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L5_NPORTS > 0 - STM32L5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L5_NPORTS > 1 - STM32L5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L5_NPORTS > 2 - STM32L5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L5_NPORTS > 3 - STM32L5_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L5_NPORTS > 4 - STM32L5_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L5_NPORTS > 5 - STM32L5_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L5_NPORTS > 6 - STM32L5_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L5_NPORTS > 7 - STM32L5_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif }; @@ -141,7 +141,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -190,10 +190,10 @@ int stm32l5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -216,10 +216,10 @@ int stm32l5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -234,12 +234,12 @@ int stm32l5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -277,14 +277,14 @@ int stm32l5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -297,7 +297,7 @@ int stm32l5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; @@ -352,7 +352,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -373,7 +373,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -392,7 +392,7 @@ bool stm32l5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -401,7 +401,7 @@ bool stm32l5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index e14436202a596..6e53d43b23bd6 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_gpio.h" #else # error "Unsupported STM32L5 chip" @@ -241,7 +241,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes @@ -362,4 +362,4 @@ void stm32l5_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_idle.c b/arch/arm/src/stm32l5/stm32l5_idle.c index 99d9448c1a0cf..2c259c32df53a 100644 --- a/arch/arm/src/stm32l5/stm32l5_idle.c +++ b/arch/arm/src/stm32l5/stm32l5_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 757b7315fff41..f42f2dda2ab8e 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -186,13 +186,13 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -202,19 +202,19 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -244,7 +244,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -298,14 +298,14 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif @@ -316,23 +316,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L5_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L5_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L5_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); #endif stm32l5_dumpnvic("initial", NR_IRQS); @@ -368,7 +368,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -403,7 +403,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -446,10 +446,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -462,7 +462,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index bcc1075c80ace..6229979f9a2e3 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_LPUART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR2 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK2_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB2ENR -# define STM32L5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART1_TX -# define STM32L5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART2_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART2_TX -# define STM32L5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART3_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART3_TX -# define STM32L5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART4_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART4_TX -# define STM32L5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART5_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART5_TX -# define STM32L5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -232,8 +232,8 @@ * LPUARTDIV must be in range [0x300, 0xFFFFF]. */ -# define STM32L5_BRR_VALUE \ - ((((uint64_t)STM32L5_APBCLOCK << 8) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_BRR_VALUE \ + ((((uint64_t)STM32_APBCLOCK << 8) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) # else @@ -249,19 +249,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L5_USARTDIV8 \ - (((STM32L5_APBCLOCK << 1) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) -# define STM32L5_USARTDIV16 \ - ((STM32L5_APBCLOCK + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L5_USARTDIV8 > 2000 -# define STM32L5_BRR_VALUE STM32L5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L5_BRR_VALUE \ - ((STM32L5_USARTDIV8 & 0xfff0) | ((STM32L5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -305,22 +305,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L5_CONSOLE_BASE + STM32L5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L5_CONSOLE_RS485_DIR - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -346,7 +346,7 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L5_CONSOLE_APBREG, 0, STM32L5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -355,17 +355,17 @@ void stm32l5_lowsetup(void) * stm32l5_rcc.c */ -#ifdef STM32L5_CONSOLE_TX - stm32l5_configgpio(STM32L5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L5_CONSOLE_RX - stm32l5_configgpio(STM32L5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32L5_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -373,42 +373,42 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L5_BRR_VALUE, - STM32L5_CONSOLE_BASE + STM32L5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.h b/arch/arm/src/stm32l5/stm32l5_lowputc.h index 29e808377c34e..316cd5a0ec427 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.h +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32l5_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index b990134a4f783..afe4793c6d942 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32l5_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -88,7 +88,7 @@ void stm32l5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -108,28 +108,28 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -138,7 +138,7 @@ void stm32l5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -148,7 +148,7 @@ void stm32l5_rcc_enablelse(void) } } -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -166,24 +166,24 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32L5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32l5_waste(); } } -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index 507e7a1a8b2d5..a47bd5ea1dd47 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -46,11 +46,11 @@ void stm32l5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.h b/arch/arm/src/stm32l5/stm32l5_mpuinit.h index 94ee60dc2855b..4e13d0640de32 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.h +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32l5_mpu_uheap(uintptr_t start, size_t size); # define stm32l5_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 925be6f7c9006..3b306923e8e67 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l5_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l5_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR1_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l5_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l5_pwr_enableusv(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -229,7 +229,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -239,7 +239,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,14 +249,14 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.h b/arch/arm/src/stm32l5/stm32l5_pwr.h index 611eaf8e001cb..3db2dd1f1d26f 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/stm32l5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32L5_STM32_PWR_H /**************************************************************************** * Included Files @@ -131,4 +131,4 @@ bool stm32l5_pwr_vddio2_valid(bool set); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_PWR_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index c2f6421d7cce5..a95f4c1f06a0e 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L5_PWR) && defined(CONFIG_STM32L5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l5_pwr_enablebkp(false); @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l5_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32l5_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32l5_clockconfig(void) * stm32l5_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l5_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32l5_clockconfig(void) #ifdef CONFIG_PM void stm32l5_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index b756d9656d02e..cafb7ec7e2cfa 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L5_STM32_RCC_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_rcc.h" #else # error "Unsupported STM32L5 chip" @@ -81,10 +81,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -100,7 +100,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l5_board_clockconfig(). * @@ -123,7 +123,7 @@ void stm32l5_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32l5_board_clockconfig(void); #endif @@ -138,7 +138,7 @@ void stm32l5_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32l5_stdclockconfig(void); #endif @@ -155,7 +155,7 @@ void stm32l5_stdclockconfig(void); * stm32l5_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32l5_board_clockconfig(). * @@ -224,4 +224,4 @@ void stm32l5_rcc_enableperipherals(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 514c57477d5d4..d7bdfff9d5d05 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L5_DMA1) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32L5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L5_DMA2) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32L5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32l5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32l5_serial_s g_lpuart1priv = { .dev = @@ -471,13 +471,13 @@ static struct stm32l5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -505,7 +505,7 @@ static struct stm32l5_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32l5_serial_s g_usart1priv = { .dev = @@ -531,13 +531,13 @@ static struct stm32l5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L5_PCLK2_FREQUENCY, - .usartbase = STM32L5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -567,7 +567,7 @@ static struct stm32l5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32l5_serial_s g_usart2priv = { .dev = @@ -593,13 +593,13 @@ static struct stm32l5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -629,7 +629,7 @@ static struct stm32l5_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32l5_serial_s g_usart3priv = { .dev = @@ -655,13 +655,13 @@ static struct stm32l5_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L5_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -691,7 +691,7 @@ static struct stm32l5_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32l5_serial_s g_uart4priv = { .dev = @@ -717,7 +717,7 @@ static struct stm32l5_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L5_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -730,8 +730,8 @@ static struct stm32l5_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -753,7 +753,7 @@ static struct stm32l5_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32l5_serial_s g_uart5priv = { .dev = @@ -779,7 +779,7 @@ static struct stm32l5_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L5_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -792,8 +792,8 @@ static struct stm32l5_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -816,24 +816,24 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l5_serial_s * const - g_uart_devs[STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -896,15 +896,15 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * above) */ - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - cr3 = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1021,21 +1021,21 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L5_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { /* LPUART BRR = 256 * fCK / baud */ brr = (((uint64_t)priv->apbclock << 8) + (priv->baud >> 1)) / priv->baud; - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } else #endif { usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { brr = (usartdiv8 + 1) >> 1; @@ -1048,13 +1048,13 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } /* Configure parity mode */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1092,11 +1092,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1104,14 +1104,14 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1125,7 +1125,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1170,7 +1170,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + while ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1276,7 +1276,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -1315,40 +1315,40 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - case STM32L5_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER - case STM32L5_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER - case STM32L5_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER - case STM32L5_USART3_BASE: +#ifdef CONFIG_STM32_USART3_SERIALDRIVER + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER - case STM32L5_UART4_BASE: +#ifdef CONFIG_STM32_UART4_SERIALDRIVER + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER - case STM32L5_UART5_BASE: +#ifdef CONFIG_STM32_UART5_SERIALDRIVER + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1414,7 +1414,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1435,7 +1435,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1446,26 +1446,26 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1473,9 +1473,9 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1528,7 +1528,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1539,7 +1539,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1553,9 +1553,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1613,9 +1613,9 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1765,8 +1765,8 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1780,7 +1780,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1847,7 +1847,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1909,7 +1909,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1920,19 +1920,19 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1977,17 +1977,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1998,17 +1998,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2028,17 +2028,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32L5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2049,17 +2049,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2070,11 +2070,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2175,8 +2175,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L5_USART_BREAKS -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2231,8 +2231,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2244,8 +2244,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2281,7 +2281,7 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l5serial_getreg(priv, STM32L5_USART_RDR_OFFSET); + rdr = stm32l5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2368,7 +2368,7 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2404,7 +2404,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32l5_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2531,7 +2531,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2542,7 +2542,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2711,7 +2711,7 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_TDR_OFFSET, (uint32_t)ch); + stm32l5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2756,7 +2756,7 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2796,7 +2796,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2838,11 +2838,11 @@ static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2978,7 +2978,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -3048,7 +3048,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3097,7 +3097,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3117,7 +3117,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ @@ -3126,7 +3126,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 80f3005edea37..234c245b5ba86 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -76,15 +76,15 @@ #include "chip.h" #include "stm32l5.h" #include "stm32l5_gpio.h" -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # include "stm32l5_dma.h" #endif #include "stm32l5_spi.h" #include -#if defined(CONFIG_STM32L5_SPI1) || defined(CONFIG_STM32L5_SPI2) || \ - defined(CONFIG_STM32L5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -94,19 +94,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L5_SPI_INTERRUPTS) && defined(CONFIG_STM32L5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -140,10 +140,10 @@ struct stm32l5_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -187,7 +187,7 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxwait(struct stm32l5_spidev_s *priv); static void spi_dmatxwait(struct stm32l5_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv); @@ -247,7 +247,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -285,12 +285,12 @@ static struct stm32l5_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L5_SPI1_BASE, - .spiclock = STM32L5_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,7 +305,7 @@ static struct stm32l5_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -343,12 +343,12 @@ static struct stm32l5_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L5_SPI2_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,7 +361,7 @@ static struct stm32l5_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -399,12 +399,12 @@ static struct stm32l5_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L5_SPI3_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI3, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L5_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -635,7 +635,7 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxwait(struct stm32l5_spidev_s *priv) { int ret; @@ -666,7 +666,7 @@ static void spi_dmarxwait(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxwait(struct stm32l5_spidev_s *priv) { int ret; @@ -697,7 +697,7 @@ static void spi_dmatxwait(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -712,7 +712,7 @@ static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -727,7 +727,7 @@ static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; @@ -747,7 +747,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; @@ -767,7 +767,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -818,7 +818,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -869,7 +869,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) { priv->rxresult = 0; @@ -885,7 +885,7 @@ static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) { priv->txresult = 0; @@ -983,11 +983,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L5_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L5_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L5_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1053,9 +1053,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1125,9 +1125,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster @@ -1192,9 +1192,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so the subsequence re-configurations will be * faster @@ -1247,9 +1247,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1315,7 +1315,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1353,8 +1353,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L5_SPI_DMA) || defined(CONFIG_STM32L5_DMACAPABLE) -#if !defined(CONFIG_STM32L5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1437,7 +1437,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L5_SPI_DMA || CONFIG_STM32L5_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1460,13 +1460,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; -#ifdef CONFIG_STM32L5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32l5_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1524,7 +1524,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1545,7 +1545,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1730,11 +1730,11 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1746,9 +1746,9 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. * NOTE: stm32l5_dmachannel() will always assign the DMA channel. * If the channel is not available, then stm32l5_dmachannel() will @@ -1763,13 +1763,13 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) priv->txdma = stm32l5_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1804,7 +1804,7 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1829,7 +1829,7 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1854,7 +1854,7 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1887,4 +1887,4 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L5_SPI1 || CONFIG_STM32L5_SPI2 || CONFIG_STM32L5_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index c13661243a8a1..184ff3caa5834 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32L5_STM32_SPI_H /**************************************************************************** * Included Files @@ -104,21 +104,21 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l5_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l5_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32l5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l5_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l5_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32l5_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l5_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32l5_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,19 +146,19 @@ int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l5_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l5_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); @@ -171,4 +171,4 @@ int stm32l5_spi3register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_SPI_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 94e500d149a16..467ec246fbae8 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -62,8 +62,8 @@ * 0x2003:ffff - End of internal SRAM2 */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32l5/stm32l5_start.h b/arch/arm/src/stm32l5/stm32l5_start.h index 11f34ab293a00..953989eeee368 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.h +++ b/arch/arm/src/stm32l5/stm32l5_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_START_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_START_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_START_H +#define __ARCH_ARM_SRC_STM32L5_STM32_START_H /**************************************************************************** * Included Files @@ -44,4 +44,4 @@ void stm32l5_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_START_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_START_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index a53bf043a3400..19c5ebbd5e0d0 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -54,137 +54,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32L5_TIMn is defined then the CONFIG_STM32L5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32L5_TIMn is - * defined then CONFIG_STM32L5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32L5_TIMn is defined then - * CONFIG_STM32L5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L5_TIM1_PWM) || defined (CONFIG_STM32L5_TIM1_ADC) || \ - defined(CONFIG_STM32L5_TIM1_DAC) || defined(CONFIG_STM32L5_TIM1_QE) -# undef CONFIG_STM32L5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L5_TIM2_PWM) || defined (CONFIG_STM32L5_TIM2_ADC) || \ - defined(CONFIG_STM32L5_TIM2_DAC) || defined(CONFIG_STM32L5_TIM2_QE) -# undef CONFIG_STM32L5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L5_TIM3_PWM) || defined (CONFIG_STM32L5_TIM3_ADC) || \ - defined(CONFIG_STM32L5_TIM3_DAC) || defined(CONFIG_STM32L5_TIM3_QE) -# undef CONFIG_STM32L5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L5_TIM4_PWM) || defined (CONFIG_STM32L5_TIM4_ADC) || \ - defined(CONFIG_STM32L5_TIM4_DAC) || defined(CONFIG_STM32L5_TIM4_QE) -# undef CONFIG_STM32L5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L5_TIM5_PWM) || defined (CONFIG_STM32L5_TIM5_ADC) || \ - defined(CONFIG_STM32L5_TIM5_DAC) || defined(CONFIG_STM32L5_TIM5_QE) -# undef CONFIG_STM32L5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32L5_TIM6_ADC) || \ - defined(CONFIG_STM32L5_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) -# undef CONFIG_STM32L5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \ - defined(CONFIG_STM32L5_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) -# undef CONFIG_STM32L5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L5_TIM8_PWM) || defined (CONFIG_STM32L5_TIM8_ADC) || \ - defined(CONFIG_STM32L5_TIM8_DAC) || defined(CONFIG_STM32L5_TIM8_QE) -# undef CONFIG_STM32L5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L5_TIM15_PWM) || defined (CONFIG_STM32L5_TIM15_ADC) || \ - defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE) -# undef CONFIG_STM32L5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L5_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ - defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE) -# undef CONFIG_STM32L5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L5_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ - defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE) -# undef CONFIG_STM32L5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,101 +301,101 @@ static const struct stm32l5_tim_ops_s stm32l5_tim_ops = .checkint = stm32l5_tim_checkint, }; -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32l5_tim_priv_s stm32l5_tim1_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32l5_tim_priv_s stm32l5_tim2_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32l5_tim_priv_s stm32l5_tim3_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32l5_tim_priv_s stm32l5_tim4_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32l5_tim_priv_s stm32l5_tim5_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32l5_tim_priv_s stm32l5_tim6_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32l5_tim_priv_s stm32l5_tim7_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32l5_tim_priv_s stm32l5_tim8_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32l5_tim_priv_s stm32l5_tim15_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32l5_tim_priv_s stm32l5_tim16_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32l5_tim_priv_s stm32l5_tim17_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_EGR_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32L5_GTIM_EGR_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_DISABLED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l5_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32l5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l5_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32L5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32L5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, break; - case STM32L5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM8_BASE) + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32L5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -654,67 +654,67 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32L5_GTIM_PSC_OFFSET, prescaler); + stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32l5_tim_enable(dev); return prescaler; @@ -769,65 +769,65 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32L5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32L5_GTIM_ARR_OFFSET, period); + stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32L5_GTIM_ARR_OFFSET); + return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,20 +869,20 @@ static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32L5_GTIM_CNT_OFFSET); + uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); + ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32L5_GTIM_CCER_OFFSET, ccer_val); + stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1020,8 +1020,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1053,8 +1053,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1086,8 +1086,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1118,8 +1118,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1151,8 +1151,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1184,8 +1184,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1217,8 +1217,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1250,8 +1250,8 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR1_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR2_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR3_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR4_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR1_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR2_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR3_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR4_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1366,67 +1366,67 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - vectorno = STM32L5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - vectorno = STM32L5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - vectorno = STM32L5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - vectorno = STM32L5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - vectorno = STM32L5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - vectorno = STM32L5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - vectorno = STM32L5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - vectorno = STM32L5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - vectorno = STM32L5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - vectorno = STM32L5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - vectorno = STM32L5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32L5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32L5_GTIM_SR_OFFSET); + uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1509,79 +1509,79 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32L5_TIM_MODE_UNUSED) + if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1616,68 +1616,68 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,9 +1687,9 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_UNUSED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32L5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index f114ff9c6183c..0a14ed05ff6ec 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32L5_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32L5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32l5_tim_dev_s enum stm32l5_tim_mode_e { - STM32L5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L5_TIM_MODE_MASK = 0x0310, - STM32L5_TIM_MODE_DISABLED = 0x0000, - STM32L5_TIM_MODE_UP = 0x0100, - STM32L5_TIM_MODE_DOWN = 0x0110, - STM32L5_TIM_MODE_UPDOWN = 0x0200, - STM32L5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L5_TIM_MODE_CK_EXT = 0x0800, - STM32L5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L5_TIM_MODE_CK_CH1 = 0x0001, - STM32L5_TIM_MODE_CK_CH2 = 0x0002, - STM32L5_TIM_MODE_CK_CH3 = 0x0003, - STM32L5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,30 +118,30 @@ enum stm32l5_tim_mode_e enum stm32l5_tim_channel_e { - STM32L5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L5_TIM_CH_POLARITY_POS = 0x00, - STM32L5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32L5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L5_TIM_CH_INCAPTURE = 0x10, - STM32L5_TIM_CH_INPWM = 0x20 - STM32L5_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; @@ -219,4 +219,4 @@ int stm32l5_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 0d21c17b04906..4e6bfd5907120 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32l5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32L5_TIM1_RES 16 -#define STM32L5_TIM2_RES 32 -#define STM32L5_TIM3_RES 16 -#define STM32L5_TIM4_RES 16 -#define STM32L5_TIM5_RES 32 -#define STM32L5_TIM6_RES 16 -#define STM32L5_TIM7_RES 16 -#define STM32L5_TIM8_RES 16 -#define STM32L5_TIM15_RES 16 -#define STM32L5_TIM16_RES 16 -#define STM32L5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -118,91 +118,91 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) (struct stm32l5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32L5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_DISABLED); - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L5_TIM_GETCLOCK(priv->tim); - period = STM32L5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L5_TIM_SETCLOCK(priv->tim, freq); - STM32L5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L5_TIM_SETCLOCK(priv->tim, 1000000); - STM32L5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -503,66 +503,66 @@ int stm32l5_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 4ee9481fb829d..70b0d18aed082 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -58,12 +58,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32L5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -146,5 +146,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index 07fb79ab2bc31..f2d168a426732 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32L5_STM32L5_UART_H -#define __ARCH_ARM_STC_STM32L5_STM32L5_UART_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32L5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_uart.h" #else # error "Unsupported STM32L5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32L5_HAVE_UART5) -# undef CONFIG_STM32L5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L5_HAVE_UART4) -# undef CONFIG_STM32L5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART3) -# undef CONFIG_STM32L5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART2) -# undef CONFIG_STM32L5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART1) -# undef CONFIG_STM32L5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L5_HAVE_LPUART1) -# undef CONFIG_STM32L5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L5_LPUART1) -# undef CONFIG_STM32L5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART1) -# undef CONFIG_STM32L5_USART1_SERIALDRIVER -# undef CONFIG_STM32L5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART2) -# undef CONFIG_STM32L5_USART2_SERIALDRIVER -# undef CONFIG_STM32L5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART3) -# undef CONFIG_STM32L5_USART3_SERIALDRIVER -# undef CONFIG_STM32L5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART4) -# undef CONFIG_STM32L5_UART4_SERIALDRIVER -# undef CONFIG_STM32L5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART5) -# undef CONFIG_STM32L5_UART5_SERIALDRIVER -# undef CONFIG_STM32L5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L5_LPUART1) || defined(CONFIG_STM32L5_USART1) || \ - defined(CONFIG_STM32L5_USART2) || defined(CONFIG_STM32L5_USART3) || \ - defined(CONFIG_STM32L5_UART4) || defined(CONFIG_STM32L5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -297,4 +297,4 @@ void stm32l5_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32L5_STM32L5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_UART_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index e8242cd559faf..1b354bc4b7b5b 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32l5_memorymap.h" #include "stm32l5_uid.h" -#ifdef STM32L5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32l5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32L5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h index 6113ef1edd0de..c6d67008c7268 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ b/arch/arm/src/stm32l5/stm32l5_uid.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_UID_H +#define __ARCH_ARM_SRC_STM32L5_STM32_UID_H /**************************************************************************** * Included Files @@ -35,4 +35,4 @@ void stm32l5_get_uniqueid(uint8_t uniqueid[12]); -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_UID_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.h b/arch/arm/src/stm32l5/stm32l5_userspace.h index 0e6d63d68a69e..70e0cd3a8164d 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.h +++ b/arch/arm/src/stm32l5/stm32l5_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ void stm32l5_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h index e9fe2209dfc37..48b31621409a5 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ b/arch/arm/src/stm32l5/stm32l5_waste.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H -#define __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H +#ifndef __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H /* Waste CPU Time */ @@ -63,4 +63,4 @@ void stm32l5_waste(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_WASTE_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.c b/arch/arm/src/stm32n6/stm32_gpio.c index 4127545303266..c22839ad7812a 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.c +++ b/arch/arm/src/stm32n6/stm32_gpio.c @@ -55,7 +55,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; * 8-11). Note that there is no GPIOI-M on this chip. */ -const uint32_t g_gpiobase[STM32N6_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { STM32_GPIOA_BASE, /* Port A - index 0 */ STM32_GPIOB_BASE, /* Port B - index 1 */ @@ -110,7 +110,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32N6_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -318,7 +318,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -358,7 +358,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.h b/arch/arm/src/stm32n6/stm32_gpio.h index 4c32f43d43c2d..64ad271b3f1a4 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.h +++ b/arch/arm/src/stm32n6/stm32_gpio.h @@ -243,7 +243,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32N6_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 220a34dc3acb6..75dc8c8c857bd 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -274,7 +274,7 @@ static struct stm32_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32N6_NUSART] = + g_uart_devs[STM32_NUSART] = { #ifdef CONFIG_STM32N6_USART1_SERIALDRIVER [0] = &g_usart1priv, @@ -639,7 +639,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1559,7 +1559,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1629,7 +1629,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -1694,7 +1694,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index 8d201546ad19a..9377ee243f208 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -35,39 +35,39 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32U5_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32U585 and STM32U575 have 2048Kb of FLASH */ #if defined(CONFIG_ARCH_CHIP_STM32U585AI) -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_E) -# define CONFIG_STM32U5_FLASH_OVERRIDE_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" # endif /* Override of the Flash has been chosen */ -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32U5_FLASH_CONFIG_C -# undef CONFIG_STM32U5_FLASH_CONFIG_E -# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) -# define CONFIG_STM32U5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) -# define CONFIG_STM32U5_FLASH_CONFIG_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif # endif /* Define the valid configuration */ -# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */ +# if defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2048 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 8192 # else @@ -79,7 +79,7 @@ # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif -#if defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U5A5XX) # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 8192 # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 616cb5e855e4a..fde84791f9b5f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -40,18 +40,18 @@ #define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32_REGION_MASK 0xF0000000 -#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE) -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1) +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ # define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ @@ -59,8 +59,8 @@ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ # define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h index b289ebb0c4288..fd74182601256 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_pinmap.h" #else # error "Unsupported STM32U5 pin map" diff --git a/arch/arm/src/stm32u5/hardware/stm32_spi.h b/arch/arm/src/stm32u5/hardware/stm32_spi.h index b13c066423465..79ff49f92d129 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) # include "hardware/stm32u5xx_spi.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h index 120cbc4f58ea2..e79236a1fce42 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_syscfg.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index d9adc748102f6..e180a60d773a3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32U5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32U5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32U5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32U5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32U5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32U5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32U5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32U5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32U5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32U5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32U5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32U5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32U5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32U5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32U5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32U5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32U5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32U5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32U5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32U5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32U5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32U5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32U5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_TIM1_CR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM1_CR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM1_SMCR (STM32U5_TIM1_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM1_DIER (STM32U5_TIM1_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM1_SR (STM32U5_TIM1_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM1_EGR (STM32U5_TIM1_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM1_CCMR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM1_CCMR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM1_CCER (STM32U5_TIM1_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM1_CNT (STM32U5_TIM1_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM1_PSC (STM32U5_TIM1_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM1_ARR (STM32U5_TIM1_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM1_RCR (STM32U5_TIM1_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM1_CCR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM1_CCR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM1_CCR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM1_CCR4 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM1_BDTR (STM32U5_TIM1_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM1_DCR (STM32U5_TIM1_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM1_DMAR (STM32U5_TIM1_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM1_OR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM1_CCMR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM1_CCR5 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM1_CCR6 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM1_OR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM1_OR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR3_OFFSET) - -#define STM32U5_TIM8_CR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM8_CR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM8_SMCR (STM32U5_TIM8_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM8_DIER (STM32U5_TIM8_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM8_SR (STM32U5_TIM8_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM8_EGR (STM32U5_TIM8_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM8_CCMR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM8_CCMR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM8_CCER (STM32U5_TIM8_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM8_CNT (STM32U5_TIM8_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM8_PSC (STM32U5_TIM8_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM8_ARR (STM32U5_TIM8_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM8_RCR (STM32U5_TIM8_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM8_CCR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM8_CCR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM8_CCR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM8_CCR4 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM8_BDTR (STM32U5_TIM8_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM8_DCR (STM32U5_TIM8_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM8_DMAR (STM32U5_TIM8_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM8_OR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM8_CCMR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM8_CCR5 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM8_CCR6 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM8_OR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM8_OR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) + +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_TIM2_CR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM2_CR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM2_SMCR (STM32U5_TIM2_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM2_DIER (STM32U5_TIM2_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM2_SR (STM32U5_TIM2_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM2_EGR (STM32U5_TIM2_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM2_CCMR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM2_CCMR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM2_CCER (STM32U5_TIM2_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM2_CNT (STM32U5_TIM2_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM2_PSC (STM32U5_TIM2_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM2_ARR (STM32U5_TIM2_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM2_CCR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM2_CCR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM2_CCR3 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM2_CCR4 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM2_DCR (STM32U5_TIM2_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM2_DMAR (STM32U5_TIM2_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM2_OR (STM32U5_TIM2_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM3_CR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM3_CR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM3_SMCR (STM32U5_TIM3_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM3_DIER (STM32U5_TIM3_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM3_SR (STM32U5_TIM3_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM3_EGR (STM32U5_TIM3_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM3_CCMR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM3_CCMR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM3_CCER (STM32U5_TIM3_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM3_CNT (STM32U5_TIM3_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM3_PSC (STM32U5_TIM3_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM3_ARR (STM32U5_TIM3_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM3_CCR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM3_CCR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM3_CCR3 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM3_CCR4 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM3_DCR (STM32U5_TIM3_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM3_DMAR (STM32U5_TIM3_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM4_CR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM4_CR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM4_SMCR (STM32U5_TIM4_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM4_DIER (STM32U5_TIM4_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM4_SR (STM32U5_TIM4_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM4_EGR (STM32U5_TIM4_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM4_CCMR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM4_CCMR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM4_CCER (STM32U5_TIM4_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM4_CNT (STM32U5_TIM4_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM4_PSC (STM32U5_TIM4_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM4_ARR (STM32U5_TIM4_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM4_CCR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM4_CCR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM4_CCR3 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM4_CCR4 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM4_DCR (STM32U5_TIM4_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM4_DMAR (STM32U5_TIM4_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM5_CR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM5_CR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM5_SMCR (STM32U5_TIM5_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM5_DIER (STM32U5_TIM5_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM5_SR (STM32U5_TIM5_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM5_EGR (STM32U5_TIM5_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM5_CCMR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM5_CCMR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM5_CCER (STM32U5_TIM5_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM5_CNT (STM32U5_TIM5_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM5_PSC (STM32U5_TIM5_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM5_ARR (STM32U5_TIM5_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM5_CCR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM5_CCR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM5_CCR3 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM5_CCR4 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM5_DCR (STM32U5_TIM5_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM5_DMAR (STM32U5_TIM5_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_OR (STM32U5_TIM5_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM15_CR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM15_CR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM15_SMCR (STM32U5_TIM15_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM15_DIER (STM32U5_TIM15_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM15_SR (STM32U5_TIM15_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM15_EGR (STM32U5_TIM15_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM15_CCMR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM15_CCER (STM32U5_TIM15_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM15_CNT (STM32U5_TIM15_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM15_PSC (STM32U5_TIM15_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM15_ARR (STM32U5_TIM15_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM15_RCR (STM32U5_TIM15_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM15_CCR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM15_CCR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM15_BDTR (STM32U5_TIM15_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM15_DCR (STM32U5_TIM15_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM15_DMAR (STM32U5_TIM15_BASE + STM32U5_GTIM_DMAR_OFFSET) - -#define STM32U5_TIM16_CR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM16_CR2 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM16_DIER (STM32U5_TIM16_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM16_SR (STM32U5_TIM16_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM16_EGR (STM32U5_TIM16_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM16_CCMR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM16_CCER (STM32U5_TIM16_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM16_CNT (STM32U5_TIM16_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM16_PSC (STM32U5_TIM16_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM16_ARR (STM32U5_TIM16_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM16_RCR (STM32U5_TIM16_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM16_CCR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM16_BDTR (STM32U5_TIM16_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM16_DCR (STM32U5_TIM16_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM16_DMAR (STM32U5_TIM16_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_OR (STM32U5_TIM16_BASE + STM32U5_GTIM_OR_OFFSET) - -#define STM32U5_TIM17_CR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM17_CR2 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM17_DIER (STM32U5_TIM17_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM17_SR (STM32U5_TIM17_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM17_EGR (STM32U5_TIM17_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM17_CCMR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM17_CCER (STM32U5_TIM17_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM17_CNT (STM32U5_TIM17_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM17_PSC (STM32U5_TIM17_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM17_ARR (STM32U5_TIM17_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM17_RCR (STM32U5_TIM17_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM17_CCR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM17_BDTR (STM32U5_TIM17_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM17_DCR (STM32U5_TIM17_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM17_DMAR (STM32U5_TIM17_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_TIM6_CR1 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM6_CR2 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM6_DIER (STM32U5_TIM6_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM6_SR (STM32U5_TIM6_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM6_EGR (STM32U5_TIM6_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM6_CNT (STM32U5_TIM6_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM6_PSC (STM32U5_TIM6_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM6_ARR (STM32U5_TIM6_BASE + STM32U5_BTIM_ARR_OFFSET) - -#define STM32U5_TIM7_CR1 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM7_CR2 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM7_DIER (STM32U5_TIM7_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM7_SR (STM32U5_TIM7_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM7_EGR (STM32U5_TIM7_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM7_CNT (STM32U5_TIM7_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM7_PSC (STM32U5_TIM7_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM7_ARR (STM32U5_TIM7_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) + +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index a106a9e574c6e..f78e13bfccdc5 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -29,10 +29,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -1254,5 +1254,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX */ +#endif /* CONFIG_STM32_STM32U5XX */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_RCC_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index e7d98a97aec2d..e79a2bf2daa90 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -29,10 +29,10 @@ #include -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -408,5 +408,5 @@ #define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT) /* Bits 16-31: read zero */ -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SPI_H */ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 56fc25f062412..3cb7aec33dcc3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ - defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#if defined(CONFIG_STM32_STM32U535XX) || defined(CONFIG_STM32_STM32U545XX) || \ + defined(CONFIG_STM32_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ + defined(CONFIG_STM32_STM32U59XX) || defined(CONFIG_STM32_STM32U59AXX) || \ + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -136,5 +136,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32U5_STM32U5XX ... */ +#endif /* CONFIG_STM32_STM32U5XX ... */ #endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32u5/stm32_allocateheap.c b/arch/arm/src/stm32u5/stm32_allocateheap.c index ee0220c16d893..96785ea2182d4 100644 --- a/arch/arm/src/stm32u5/stm32_allocateheap.c +++ b/arch/arm/src/stm32u5/stm32_allocateheap.c @@ -60,8 +60,8 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32U5_FSMC=y : Enables the FSMC - * CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -71,8 +71,8 @@ * include the additional regions. */ -#ifndef CONFIG_STM32U5_FSMC -# undef CONFIG_STM32U5_FSMC_SRAM +#ifndef CONFIG_STM32_FSMC +# undef CONFIG_STM32_FSMC_SRAM #endif /* STM32U5[7,8]6xx have 128 Kib in two banks, both accessible to DMA: @@ -121,17 +121,17 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ - defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ + defined(CONFIG_STM32_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -140,10 +140,10 @@ * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE). */ -#ifdef CONFIG_STM32U5_FSMC_SRAM +#ifdef CONFIG_STM32_FSMC_SRAM # if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE) # error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided" -# undef CONFIG_STM32U5_FSMC_SRAM +# undef CONFIG_STM32_FSMC_SRAM # endif #endif @@ -319,7 +319,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32U5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -339,7 +339,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32U5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -359,7 +359,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32U5_SRAM5_HEAP +#ifdef CONFIG_STM32_SRAM5_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -379,7 +379,7 @@ void arm_addregion(void) #endif /* SRAM5 */ -#ifdef CONFIG_STM32U5_FSMC_SRAM_HEAP +#ifdef CONFIG_STM32_FSMC_SRAM_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) /* Allow user-mode access to the FSMC SRAM user heap memory */ diff --git a/arch/arm/src/stm32u5/stm32_dbgmcu.h b/arch/arm/src/stm32u5/stm32_dbgmcu.h index 0db98b7196c33..7997e386cbcfa 100644 --- a/arch/arm/src/stm32u5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32u5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_dbgmcu.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_exti.h b/arch/arm/src/stm32u5/stm32_exti.h index dd31b1946ef91..6693179b0b535 100644 --- a/arch/arm/src/stm32u5/stm32_exti.h +++ b/arch/arm/src/stm32u5/stm32_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_flash.c b/arch/arm/src/stm32u5/stm32_flash.c index 586b315456178..526ba889c0599 100644 --- a/arch/arm/src/stm32u5/stm32_flash.c +++ b/arch/arm/src/stm32u5/stm32_flash.c @@ -50,13 +50,13 @@ #include "stm32_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32U5_STM32U585XX) -#elif !defined(CONFIG_STM32U5_STM32U5A5XX) +#if !defined(CONFIG_STM32_STM32U585XX) +#elif !defined(CONFIG_STM32_STM32U5A5XX) #else # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32u5/stm32_gpio.h b/arch/arm/src/stm32u5/stm32_gpio.h index ad41d5f41b571..5f37922b48239 100644 --- a/arch/arm/src/stm32u5/stm32_gpio.h +++ b/arch/arm/src/stm32u5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_i2c.c b/arch/arm/src/stm32u5/stm32_i2c.c index 5ce0991788563..2f99e55a86fff 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.c +++ b/arch/arm/src/stm32u5/stm32_i2c.c @@ -172,28 +172,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32U5_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32U5_I2C1 - * CONFIG_STM32U5_I2C2 - * CONFIG_STM32U5_I2C3 - * CONFIG_STM32U5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32U5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32U5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32U5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32U5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32U5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -273,8 +273,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32U5_I2C1) || defined(CONFIG_STM32U5_I2C2) || \ - defined(CONFIG_STM32U5_I2C3) || defined(CONFIG_STM32U5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -286,25 +286,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32U5_I2CTIMEOSEC) && !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 -# define CONFIG_STM32U5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32U5_I2CTIMEOSEC) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32U5_I2CTIMEOTICKS -# define CONFIG_STM32U5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32U5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32U5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32U5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -472,9 +472,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32U5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -518,7 +518,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -554,7 +554,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -590,7 +590,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -626,7 +626,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -759,7 +759,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -776,7 +776,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -834,12 +834,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32U5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -878,10 +878,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2367,7 +2367,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); @@ -2452,7 +2452,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); @@ -2957,22 +2957,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3058,4 +3058,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32U5_I2C1 || CONFIG_STM32U5_I2C2 || CONFIG_STM32U5_I2C3 || CONFIG_STM32U5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32u5/stm32_i2c.h b/arch/arm/src/stm32u5/stm32_i2c.h index 5f31f8995ac6e..f34cf0166eb29 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.h +++ b/arch/arm/src/stm32u5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO -# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32u5/stm32_idle.c b/arch/arm/src/stm32u5/stm32_idle.c index 08a5d61d44c8c..f84145eca7175 100644 --- a/arch/arm/src/stm32u5/stm32_idle.c +++ b/arch/arm/src/stm32u5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32u5/stm32_lse.c b/arch/arm/src/stm32u5/stm32_lse.c index 70438d4e8b0c3..ebac02e6c54fb 100644 --- a/arch/arm/src/stm32u5/stm32_lse.c +++ b/arch/arm/src/stm32u5/stm32_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index aa334d993051d..2e7ac13bb44c5 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32U5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32U5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32U5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index b788f167de9f0..ae75e4a235666 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_rcc.h" #else # error "Unsupported STM32U5 chip" @@ -97,7 +97,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -120,7 +120,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -135,7 +135,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -152,7 +152,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index a5aea799e9657..13d539fdb787d 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32U5_DMA1) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32U5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32U5_DMA2) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32U5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32U5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32U5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32U5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1125,7 +1125,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1329,37 +1329,37 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1428,7 +1428,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32U5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1779,8 +1779,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32U5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32U5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1923,7 +1923,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2001,7 +2001,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2052,7 +2052,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2189,8 +2189,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32U5_USART_BREAKS -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2418,7 +2418,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2770,7 +2770,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3111,7 +3111,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3140,7 +3140,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c index bf4ded9c9011f..82ceb35c60d81 100644 --- a/arch/arm/src/stm32u5/stm32_spi.c +++ b/arch/arm/src/stm32u5/stm32_spi.c @@ -74,8 +74,8 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32U5_SPI1) || defined(CONFIG_STM32U5_SPI2) || \ - defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32U5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32U5_SPI_INTERRUPTS) && defined(CONFIG_STM32U5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,21 +135,21 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,15 +160,15 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32U5_SPI1) +#if defined(CONFIG_STM32_SPI1) # define SPI1_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI2) +#if defined(CONFIG_STM32_SPI2) # define SPI2_KERNEL_CLOCK_FREQ STM32_PCLK1_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI3) # define SPI3_KERNEL_CLOCK_FREQ STM32_PCLK3_FREQUENCY #endif @@ -190,7 +190,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -240,7 +240,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -306,7 +306,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -355,7 +355,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI1_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32U5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -370,15 +370,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI1_COMMTYPE - .config = CONFIG_STM32U5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -427,7 +427,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI2_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32U5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -442,15 +442,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI2_COMMTYPE - .config = CONFIG_STM32U5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -499,7 +499,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI3_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32U5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -514,13 +514,13 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI3_COMMTYPE - .config = CONFIG_STM32U5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ /**************************************************************************** * Private Functions @@ -840,7 +840,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -857,7 +857,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -897,7 +897,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -946,7 +946,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -961,7 +961,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -981,7 +981,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1043,7 +1043,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1103,7 +1103,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1127,7 +1127,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1662,9 +1662,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32U5_SPI_DMA) || defined(CONFIG_STM32U5_DMACAPABLE) || \ - defined(CONFIG_STM32U5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32U5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1753,8 +1753,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32U5_SPI_DMA || CONFIG_STM32U5_DMACAPABLE || - * CONFIG_STM32U5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1778,7 +1778,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1796,12 +1796,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32U5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32U5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1865,7 +1865,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32U5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -1995,7 +1995,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32U5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2016,7 +2016,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2250,7 +2250,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2332,7 +2332,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2357,7 +2357,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2382,7 +2382,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2415,5 +2415,5 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32U5_SPI1 || CONFIG_STM32U5_SPI2 || CONFIG_STM32U5_SPI3 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32u5/stm32_spi.h b/arch/arm/src/stm32u5/stm32_spi.h index 9734b18924feb..485b6a5a9a1bb 100644 --- a/arch/arm/src/stm32u5/stm32_spi.h +++ b/arch/arm/src/stm32u5/stm32_spi.h @@ -114,21 +114,21 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -156,17 +156,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_start.c b/arch/arm/src/stm32u5/stm32_start.c index ee12901462fd9..87609e5c881d2 100644 --- a/arch/arm/src/stm32u5/stm32_start.c +++ b/arch/arm/src/stm32u5/stm32_start.c @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32U5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 5e15c461d1872..66879e72e8a2a 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -54,137 +54,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32U5_TIMn is defined then the CONFIG_STM32U5_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32U5_TIMn is - * defined then CONFIG_STM32U5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_DAC may also be defined to indicate that timer "n" + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" * is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32U5_TIMn is defined then - * CONFIG_STM32U5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32U5_TIM1_PWM) || defined (CONFIG_STM32U5_TIM1_ADC) || \ - defined(CONFIG_STM32U5_TIM1_DAC) || defined(CONFIG_STM32U5_TIM1_QE) -# undef CONFIG_STM32U5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32U5_TIM2_PWM) || defined (CONFIG_STM32U5_TIM2_ADC) || \ - defined(CONFIG_STM32U5_TIM2_DAC) || defined(CONFIG_STM32U5_TIM2_QE) -# undef CONFIG_STM32U5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32U5_TIM3_PWM) || defined (CONFIG_STM32U5_TIM3_ADC) || \ - defined(CONFIG_STM32U5_TIM3_DAC) || defined(CONFIG_STM32U5_TIM3_QE) -# undef CONFIG_STM32U5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32U5_TIM4_PWM) || defined (CONFIG_STM32U5_TIM4_ADC) || \ - defined(CONFIG_STM32U5_TIM4_DAC) || defined(CONFIG_STM32U5_TIM4_QE) -# undef CONFIG_STM32U5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32U5_TIM5_PWM) || defined (CONFIG_STM32U5_TIM5_ADC) || \ - defined(CONFIG_STM32U5_TIM5_DAC) || defined(CONFIG_STM32U5_TIM5_QE) -# undef CONFIG_STM32U5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32U5_TIM6_ADC) || \ - defined(CONFIG_STM32U5_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) -# undef CONFIG_STM32U5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32U5_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) -# undef CONFIG_STM32U5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32U5_TIM8_PWM) || defined (CONFIG_STM32U5_TIM8_ADC) || \ - defined(CONFIG_STM32U5_TIM8_DAC) || defined(CONFIG_STM32U5_TIM8_QE) -# undef CONFIG_STM32U5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32U5_TIM15_PWM) || defined (CONFIG_STM32U5_TIM15_ADC) || \ - defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) -# undef CONFIG_STM32U5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32U5_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ - defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) -# undef CONFIG_STM32U5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32U5_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ - defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) -# undef CONFIG_STM32U5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32U5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,101 +301,101 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -654,67 +654,67 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -769,65 +769,65 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,20 +869,20 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32U5_TIM2) || defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1020,8 +1020,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1053,8 +1053,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1086,8 +1086,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1118,8 +1118,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1151,8 +1151,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1184,8 +1184,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1217,8 +1217,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1250,8 +1250,8 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1366,67 +1366,67 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1509,79 +1509,79 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1616,68 +1616,68 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,9 +1687,9 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32U5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h index e043e98f0e0b3..f61751552dd49 100644 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ b/arch/arm/src/stm32u5/stm32_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32_tim_dev_s enum stm32_tim_mode_e { - STM32U5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32U5_TIM_MODE_MASK = 0x0310, - STM32U5_TIM_MODE_DISABLED = 0x0000, - STM32U5_TIM_MODE_UP = 0x0100, - STM32U5_TIM_MODE_DOWN = 0x0110, - STM32U5_TIM_MODE_UPDOWN = 0x0200, - STM32U5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32U5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32U5_TIM_MODE_CK_EXT = 0x0800, - STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32U5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32U5_TIM_MODE_CK_CH1 = 0x0001, - STM32U5_TIM_MODE_CK_CH2 = 0x0002, - STM32U5_TIM_MODE_CK_CH3 = 0x0003, - STM32U5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32_tim_mode_e enum stm32_tim_channel_e { - STM32U5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32U5_TIM_CH_POLARITY_POS = 0x00, - STM32U5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32U5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32U5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 92e5739a23329..a564a8af52538 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32U5_TIM1_RES 16 -#define STM32U5_TIM2_RES 32 -#define STM32U5_TIM3_RES 16 -#define STM32U5_TIM4_RES 16 -#define STM32U5_TIM5_RES 32 -#define STM32U5_TIM6_RES 16 -#define STM32U5_TIM7_RES 16 -#define STM32U5_TIM8_RES 16 -#define STM32U5_TIM15_RES 16 -#define STM32U5_TIM16_RES 16 -#define STM32U5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -118,91 +118,91 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32_timer_handler(int irq, void *context, void *arg) (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32U5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED); - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32U5_TIM_GETCLOCK(priv->tim); - period = STM32U5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32U5_TIM_SETCLOCK(priv->tim, freq); - STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32U5_TIM_SETCLOCK(priv->tim, 1000000); - STM32U5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32u5/stm32_timerisr.c b/arch/arm/src/stm32u5/stm32_timerisr.c index 5cd2f7175dddf..3c6aee942223a 100644 --- a/arch/arm/src/stm32u5/stm32_timerisr.c +++ b/arch/arm/src/stm32u5/stm32_timerisr.c @@ -58,9 +58,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32U5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -123,7 +123,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32u5/stm32_uart.h b/arch/arm/src/stm32u5/stm32_uart.h index 198ef1e36a050..0a06e0798d6ef 100644 --- a/arch/arm/src/stm32u5/stm32_uart.h +++ b/arch/arm/src/stm32u5/stm32_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32U5_STM32_UART_H -#define __ARCH_ARM_STC_STM32U5_STM32_UART_H +#ifndef __ARCH_ARM_SRC_STM32U5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32U5_STM32_UART_H /**************************************************************************** * Included Files @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32U5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32U5_HAVE_UART5) -# undef CONFIG_STM32U5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32U5_HAVE_UART4) -# undef CONFIG_STM32U5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART3) -# undef CONFIG_STM32U5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART2) -# undef CONFIG_STM32U5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART1) -# undef CONFIG_STM32U5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32U5_HAVE_LPUART1) -# undef CONFIG_STM32U5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32U5_LPUART1) -# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART1) -# undef CONFIG_STM32U5_USART1_SERIALDRIVER -# undef CONFIG_STM32U5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART2) -# undef CONFIG_STM32U5_USART2_SERIALDRIVER -# undef CONFIG_STM32U5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART3) -# undef CONFIG_STM32U5_USART3_SERIALDRIVER -# undef CONFIG_STM32U5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART4) -# undef CONFIG_STM32U5_UART4_SERIALDRIVER -# undef CONFIG_STM32U5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART5) -# undef CONFIG_STM32U5_UART5_SERIALDRIVER -# undef CONFIG_STM32U5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \ - defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \ - defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -297,4 +297,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32U5_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32U5_STM32_UART_H */ diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c index 55b3aa8e82a53..479826dafd2a5 100644 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ b/arch/arm/src/stm32u5/stm32_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32_memorymap.h" #include "stm32_uid.h" -#ifdef STM32U5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32U5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32u5/stm32u5xx_rcc.c b/arch/arm/src/stm32u5/stm32u5xx_rcc.c index 3fb5798bd7fca..b9017ae455ad1 100644 --- a/arch/arm/src/stm32u5/stm32u5xx_rcc.c +++ b/arch/arm/src/stm32u5/stm32u5xx_rcc.c @@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -92,55 +92,55 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32U5_GPDMA1 +#ifdef CONFIG_STM32_GPDMA1 regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32U5_CORDIC +#ifdef CONFIG_STM32_CORDIC regval |= RCC_AHB1ENR_CORDIC; #endif -#ifdef CONFIG_STM32U5_FMAC +#ifdef CONFIG_STM32_FMAC regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32U5_MDF1 +#ifdef CONFIG_STM32_MDF1 regval |= RCC_AHB1ENR_MDF1EN; #endif -#ifdef CONFIG_STM32U5_FLASH +#ifdef CONFIG_STM32_FLASH regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32U5_CRC +#ifdef CONFIG_STM32_CRC regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32U5_TSC +#ifdef CONFIG_STM32_TSC regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32U5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32U5_DMA2D +#ifdef CONFIG_STM32_DMA2D regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32U5_GTZC1 +#ifdef CONFIG_STM32_GTZC1 regval |= RCC_AHB1ENR_GTZC1EN; #endif -#ifdef CONFIG_STM32U5_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM regval |= RCC_AHB1ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32U5_DCACHE1 +#ifdef CONFIG_STM32_DCACHE1 regval |= RCC_AHB1ENR_DCACHE1EN; #endif -#ifdef CONFIG_STM32U5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 regval |= RCC_AHB1ENR_SRAM1EN; #endif @@ -194,67 +194,67 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32U5_ADC1) +#if defined(CONFIG_STM32_ADC1) regval |= RCC_AHB2ENR1_ADC1EN; #endif -#if defined(CONFIG_STM32U5_DCMI_PSSI) +#if defined(CONFIG_STM32_DCMI_PSSI) regval |= RCC_AHB2ENR1_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGPHYEN; #endif -#ifdef CONFIG_STM32U5_AES +#ifdef CONFIG_STM32_AES regval |= RCC_AHB2ENR1_AESEN; #endif -#ifdef CONFIG_STM32U5_HASH +#ifdef CONFIG_STM32_HASH regval |= RCC_AHB2ENR1_HASHEN #endif -#ifdef CONFIG_STM32U5_RNG +#ifdef CONFIG_STM32_RNG regval |= RCC_AHB2ENR1_RNGEN; #endif -#ifdef CONFIG_STM32U5_PKA +#ifdef CONFIG_STM32_PKA regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32U5_SAES +#ifdef CONFIG_STM32_SAES regval |= RCC_AHB2ENR1_SAES; #endif -#ifdef CONFIG_STM32U5_OCTOSPIM +#ifdef CONFIG_STM32_OCTOSPIM regval |= RCC_AHB2ENR1_OCTOSPIM; #endif -#ifdef CONFIG_STM32U5_OTFDEC1 +#ifdef CONFIG_STM32_OTFDEC1 regval |= RCC_AHB2ENR1_OTFDEC1; #endif -#ifdef CONFIG_STM32U5_OTFDEC2 +#ifdef CONFIG_STM32_OTFDEC2 regval |= RCC_AHB2ENR1_OTFDEC2; #endif -#ifdef CONFIG_STM32U5_SDMMC1EN +#ifdef CONFIG_STM32_SDMMC1EN regval |= RCC_AHB2ENR1_SDMMC1EN; #endif -#ifdef CONFIG_STM32U5_SDMMC2EN +#ifdef CONFIG_STM32_SDMMC2EN regval |= RCC_AHB2ENR1_SDMMC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 regval |= RCC_AHB2ENR1_SRAM2EN; #endif -#ifdef CONFIG_STM32U5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 regval |= RCC_AHB2ENR1_SRAM3EN; #endif @@ -262,19 +262,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR2); -#ifdef CONFIG_STM32U5_FSMC +#ifdef CONFIG_STM32_FSMC regval |= RCC_AHB2ENR2_FSMCEN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 regval |= RCC_AHB2ENR2_OCTOSPI1EN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI2 +#ifdef CONFIG_STM32_OCTOSPI2 regval |= RCC_AHB2ENR2_OCTOSPI2EN; #endif -#ifdef CONFIG_STM32U5_SRAM5 +#ifdef CONFIG_STM32_SRAM5 regval |= RCC_AHB2ENR2_SRAM5EN; #endif @@ -299,35 +299,35 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32U5_LPGPIO1 +#ifdef CONFIG_STM32_LPGPIO1 regval |= RCC_AHB3ENR_LPGPIO1EN; #endif -#ifdef CONFIG_STM32U5_PWR +#ifdef CONFIG_STM32_PWR regval |= RCC_AHB3ENR_PWREN; #endif -#ifdef CONFIG_STM32U5_ADC4 +#ifdef CONFIG_STM32_ADC4 regval |= RCC_AHB3ENR_ADC4EN; #endif -#ifdef CONFIG_STM32U5_DAC1 +#ifdef CONFIG_STM32_DAC1 regval |= RCC_AHB3ENR_DAC1EN; #endif -#ifdef CONFIG_STM32U5_LPDMA1 +#ifdef CONFIG_STM32_LPDMA1 regval |= RCC_AHB3ENR_LPDMA1EN; #endif -#ifdef CONFIG_STM32U5_ADF1 +#ifdef CONFIG_STM32_ADF1 regval |= RCC_AHB3ENR_ADF1EN; #endif -#ifdef CONFIG_STM32U5_GTZC2 +#ifdef CONFIG_STM32_GTZC2 regval |= RCC_AHB3ENR_GTZC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM4 +#ifdef CONFIG_STM32_SRAM4 regval |= RCC_AHB3ENR_SRAM4EN; #endif @@ -352,63 +352,63 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32U5_WWDG +#ifdef CONFIG_STM32_WWDG regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32U5_USART2 +#ifdef CONFIG_STM32_USART2 regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32U5_USART3 +#ifdef CONFIG_STM32_USART3 regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32U5_UART4 +#ifdef CONFIG_STM32_UART4 regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32U5_UART5 +#ifdef CONFIG_STM32_UART5 regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32U5_CRS +#ifdef CONFIG_STM32_CRS regval |= RCC_APB1ENR1_CRSEN; #endif @@ -418,19 +418,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32U5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32U5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32U5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 regval |= RCC_APB1ENR2_UCPD1EN; #endif @@ -455,39 +455,39 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32U5_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32U5_SAI1 +#ifdef CONFIG_STM32_SAI1 regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32U5_SAI2 +#ifdef CONFIG_STM32_SAI2 regval |= RCC_APB2ENR_SAI2EN; #endif @@ -512,47 +512,47 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32U5_SYSCFG +#ifdef CONFIG_STM32_SYSCFG regval |= RCC_APB3ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 regval |= RCC_APB3ENR_SPI3EN; #endif -#ifdef CONFIG_STM32U5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32U5_I2C3EN +#ifdef CONFIG_STM32_I2C3EN regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32U5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32U5_OPAMP +#ifdef CONFIG_STM32_OPAMP regval |= RCC_APB3ENR_OPAMPEN; #endif -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP regval |= RCC_APB3ENR_COMPEN; #endif -#ifdef CONFIG_STM32U5_VREF +#ifdef CONFIG_STM32_VREF regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32U5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB regval |= RCC_APB3ENR_RTCAPBEN; #endif @@ -604,7 +604,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -742,9 +742,9 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR3_PPRE3; putreg32(regval, STM32_RCC_CFGR3); -#ifdef CONFIG_STM32U5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK -# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK +# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32_RTC_HSECLOCK #endif @@ -799,7 +799,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32wb/chip.h b/arch/arm/src/stm32wb/chip.h index 1c263402e683c..cddd9871d0351 100644 --- a/arch/arm/src/stm32wb/chip.h +++ b/arch/arm/src/stm32wb/chip.h @@ -49,7 +49,7 @@ * arch/stm32wb/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WB_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WB */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h index fcac2dde6db3f..c47e5d34f5564 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32WB_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32WB_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32WB_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32WB_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_CRS_CR (STM32WB_CRS_BASE + STM32WB_CRS_CR_OFFSET) -#define STM32WB_CRS_CFGR (STM32WB_CRS_BASE + STM32WB_CRS_CFGR_OFFSET) -#define STM32WB_CRS_ISR (STM32WB_CRS_BASE + STM32WB_CRS_ISR_OFFSET) -#define STM32WB_CRS_ICR (STM32WB_CRS_BASE + STM32WB_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -102,4 +102,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h index dfd6e1050dbfe..83611ce75b246 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H /**************************************************************************** * Included Files @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32WB_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ - -#define STM32WB_DMACHAN_OFFSET(n) (0x0014 * (n)) -#define STM32WB_DMACHAN1_OFFSET 0x0000 -#define STM32WB_DMACHAN2_OFFSET 0x0014 -#define STM32WB_DMACHAN3_OFFSET 0x0028 -#define STM32WB_DMACHAN4_OFFSET 0x003c -#define STM32WB_DMACHAN5_OFFSET 0x0050 -#define STM32WB_DMACHAN6_OFFSET 0x0064 -#define STM32WB_DMACHAN7_OFFSET 0x0078 - -#define STM32WB_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32WB_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32WB_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32WB_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ - -#define STM32WB_DMA_CCR_OFFSET(n) (STM32WB_DMACHAN_CCR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CNDTR_OFFSET(n) (STM32WB_DMACHAN_CNDTR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CPAR_OFFSET(n) (STM32WB_DMACHAN_CPAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CMAR_OFFSET(n) (STM32WB_DMACHAN_CMAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) - -#define STM32WB_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32WB_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32WB_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32WB_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32WB_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32WB_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32WB_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ - -#define STM32WB_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32WB_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32WB_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32WB_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32WB_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32WB_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32WB_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ - -#define STM32WB_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32WB_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32WB_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32WB_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32WB_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32WB_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32WB_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ - -#define STM32WB_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32WB_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32WB_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32WB_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32WB_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32WB_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32WB_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ + +#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 + +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ + +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) + +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ + +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ + +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ + +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32WB_DMA1_ISRC (STM32WB_DMA1_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA1_IFCR (STM32WB_DMA1_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA1_CCR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA1_CCR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA1_CCR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA1_CCR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA1_CCR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA1_CCR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA1_CCR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA1_CCR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA1_CNDTR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA1_CNDTR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA1_CNDTR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA1_CNDTR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA1_CNDTR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA1_CNDTR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA1_CNDTR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA1_CNDTR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA1_CPAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA1_CPAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA1_CPAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA1_CPAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA1_CPAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA1_CPAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA1_CPAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA1_CPAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA1_CMAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA1_CMAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA1_CMAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA1_CMAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA1_CMAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA1_CMAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA1_CMAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA1_CMAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR7_OFFSET) - -#define STM32WB_DMA2_ISRC (STM32WB_DMA2_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA2_IFCR (STM32WB_DMA2_BASE + STM32WB_DMA_IFCR_OFFSET) - -#define STM32WB_DMA2_CCR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA2_CCR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA2_CCR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA2_CCR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA2_CCR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA2_CCR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA2_CCR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA2_CCR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR7_OFFSET) - -#define STM32WB_DMA2_CNDTR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA2_CNDTR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA2_CNDTR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA2_CNDTR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA2_CNDTR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA2_CNDTR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA2_CNDTR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA2_CNDTR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR7_OFFSET) - -#define STM32WB_DMA2_CPAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA2_CPAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA2_CPAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA2_CPAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA2_CPAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA2_CPAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA2_CPAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA2_CPAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR7_OFFSET) - -#define STM32WB_DMA2_CMAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA2_CMAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA2_CMAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA2_CMAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA2_CMAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA2_CMAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA2_CMAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA2_CMAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR7_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) + +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) + +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET) + +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET) + +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET) + +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -273,4 +273,4 @@ /* NOTE: DMA channel mapping is done through DMAMUX1. */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h index f4a8b5d47c9e2..ee482f157df13 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H /**************************************************************************** * Included Files @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32WB_DMAMUX_C0CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(0) -#define STM32WB_DMAMUX_C1CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(1) -#define STM32WB_DMAMUX_C2CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(2) -#define STM32WB_DMAMUX_C3CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(3) -#define STM32WB_DMAMUX_C4CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(4) -#define STM32WB_DMAMUX_C5CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(5) -#define STM32WB_DMAMUX_C6CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(6) -#define STM32WB_DMAMUX_C7CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(7) -#define STM32WB_DMAMUX_C8CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(8) -#define STM32WB_DMAMUX_C9CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(9) -#define STM32WB_DMAMUX_C10CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(10) -#define STM32WB_DMAMUX_C11CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(11) -#define STM32WB_DMAMUX_C12CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(12) -#define STM32WB_DMAMUX_C13CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32WB_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32WB_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ - -#define STM32WB_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32WB_DMAMUX_RG0CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(0) -#define STM32WB_DMAMUX_RG1CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(1) -#define STM32WB_DMAMUX_RG2CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(2) -#define STM32WB_DMAMUX_RG3CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(3) -#define STM32WB_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32WB_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3fc: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ + +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3fc: Reserved */ /* Register Addresses *******************************************************/ -#define STM32WB_DMAMUX1_CXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_C0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C0CR_OFFSET) -#define STM32WB_DMAMUX1_C1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C1CR_OFFSET) -#define STM32WB_DMAMUX1_C2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C2CR_OFFSET) -#define STM32WB_DMAMUX1_C3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C3CR_OFFSET) -#define STM32WB_DMAMUX1_C4CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C4CR_OFFSET) -#define STM32WB_DMAMUX1_C5CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C5CR_OFFSET) -#define STM32WB_DMAMUX1_C6CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C6CR_OFFSET) -#define STM32WB_DMAMUX1_C7CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C7CR_OFFSET) -#define STM32WB_DMAMUX1_C8CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C8CR_OFFSET) -#define STM32WB_DMAMUX1_C9CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C9CR_OFFSET) -#define STM32WB_DMAMUX1_C10CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C10CR_OFFSET) -#define STM32WB_DMAMUX1_C11CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C11CR_OFFSET) -#define STM32WB_DMAMUX1_C12CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C12CR_OFFSET) -#define STM32WB_DMAMUX1_C13CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C13CR_OFFSET) - -#define STM32WB_DMAMUX1_CSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CSR_OFFSET) -#define STM32WB_DMAMUX1_CFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CFR_OFFSET) - -#define STM32WB_DMAMUX1_RGXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_RG0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG0CR_OFFSET) -#define STM32WB_DMAMUX1_RG1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG1CR_OFFSET) -#define STM32WB_DMAMUX1_RG2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG2CR_OFFSET) -#define STM32WB_DMAMUX1_RG3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG3CR_OFFSET) - -#define STM32WB_DMAMUX1_RGSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGSR_OFFSET) -#define STM32WB_DMAMUX1_RGCFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) + +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) + +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) + +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -283,4 +284,4 @@ #define DMAMAP_AES2_OUT_0 DMAMAP_MAP(DMA1, DMAMUX1_AES2_OUT) #define DMAMAP_AES2_OUT_1 DMAMAP_MAP(DMA2, DMAMUX1_AES2_OUT) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h index 1169438501b3d..959c7e682c5b1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -36,41 +36,41 @@ /* Register Offsets *********************************************************/ -#define STM32WB_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ -#define STM32WB_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ -#define STM32WB_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ -#define STM32WB_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ -#define STM32WB_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ -#define STM32WB_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ -#define STM32WB_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ -#define STM32WB_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ -#define STM32WB_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ -#define STM32WB_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ /* Register Addresses *******************************************************/ -#define STM32WB_EXTI_RTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR1_OFFSET) -#define STM32WB_EXTI_FTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR1_OFFSET) -#define STM32WB_EXTI_SWIER1 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER1_OFFSET) -#define STM32WB_EXTI_PR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR1_OFFSET) -#define STM32WB_EXTI_RTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR2_OFFSET) -#define STM32WB_EXTI_FTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR2_OFFSET) -#define STM32WB_EXTI_SWIER2 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER2_OFFSET) -#define STM32WB_EXTI_PR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR2_OFFSET) -#define STM32WB_EXTI_C1IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR1_OFFSET) -#define STM32WB_EXTI_C1EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR1_OFFSET) -#define STM32WB_EXTI_C1IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR2_OFFSET) -#define STM32WB_EXTI_C1EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR2_OFFSET) -#define STM32WB_EXTI_C2IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR1_OFFSET) -#define STM32WB_EXTI_C2EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR1_OFFSET) -#define STM32WB_EXTI_C2IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR2_OFFSET) -#define STM32WB_EXTI_C2EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE + STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE + STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE + STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE + STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE + STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE + STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE + STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE + STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE + STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE + STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -167,4 +167,4 @@ #define EXTI_C2EMR2_EM(n) (1 << ((n) & 31)) /* CPU2 Event mask on line n = 40, 41 */ #define EXTI_C2EMR2_MASK 0x00000300 -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 8f2fe45b9dd27..74ead7ff2ba1b 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H /**************************************************************************** * Included Files @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32WB_FLASH_CONFIG_x selects the default FLASH size based on + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with - * CONFIG_STM32WB_FLASH_OVERRIDE_x + * CONFIG_STM32_FLASH_OVERRIDE_x * * Parts STM32WB3xxC have 256Kb of FLASH * Parts STM32WB5xxC have 256Kb of FLASH @@ -50,104 +50,104 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C_256) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E_512) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_Y_640) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G_1024) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C_256) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C_320) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E_512) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_Y_640) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G_1024) # error "Flash size not defined" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WB_FLASH_CONFIG_C_256 -# undef CONFIG_STM32WB_FLASH_CONFIG_C_320 -# undef CONFIG_STM32WB_FLASH_CONFIG_E_512 -# undef CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# undef CONFIG_STM32WB_FLASH_CONFIG_G_1024 -# if defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) -# define CONFIG_STM32WB_FLASH_CONFIG_C_256 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) -# define CONFIG_STM32WB_FLASH_CONFIG_C_320 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) -# define CONFIG_STM32WB_FLASH_CONFIG_E_512 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) -# define CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) -# define CONFIG_STM32WB_FLASH_CONFIG_G_1024 +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C_256 +# undef CONFIG_STM32_FLASH_CONFIG_C_320 +# undef CONFIG_STM32_FLASH_CONFIG_E_512 +# undef CONFIG_STM32_FLASH_CONFIG_Y_640 +# undef CONFIG_STM32_FLASH_CONFIG_G_1024 +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C_256) +# define CONFIG_STM32_FLASH_CONFIG_C_256 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) +# define CONFIG_STM32_FLASH_CONFIG_C_320 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E_512) +# define CONFIG_STM32_FLASH_CONFIG_E_512 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y_640) +# define CONFIG_STM32_FLASH_CONFIG_Y_640 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G_1024) +# define CONFIG_STM32_FLASH_CONFIG_G_1024 # endif #endif /* Define the valid configuration */ -#define STM32WB_FLASH_PAGESIZE 4096 - -#if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ -# define STM32WB_FLASH_NPAGES 64 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ -# define STM32WB_FLASH_NPAGES 80 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ -# define STM32WB_FLASH_NPAGES 128 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ -# define STM32WB_FLASH_NPAGES 160 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ -# define STM32WB_FLASH_NPAGES 256 +#define STM32_FLASH_PAGESIZE 4096 + +#if defined(CONFIG_STM32_FLASH_CONFIG_C_256) /* 256 kB */ +# define STM32_FLASH_NPAGES 64 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C_320) /* 320 kB */ +# define STM32_FLASH_NPAGES 80 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E_512) /* 512 kB */ +# define STM32_FLASH_NPAGES 128 +#elif defined(CONFIG_STM32_FLASH_CONFIG_Y_640) /* 640 kB */ +# define STM32_FLASH_NPAGES 160 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G_1024) /* 1 MB */ +# define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" #endif -#define STM32WB_FLASH_SIZE (STM32WB_FLASH_NPAGES * STM32WB_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WB_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ -#define STM32WB_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ -#define STM32WB_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ -#define STM32WB_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ -#define STM32WB_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ -#define STM32WB_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ -#define STM32WB_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ -#define STM32WB_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ -#define STM32WB_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ -#define STM32WB_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ -#define STM32WB_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ -#define STM32WB_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ -#define STM32WB_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ -#define STM32WB_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ -#define STM32WB_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ -#define STM32WB_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ -#define STM32WB_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ -#define STM32WB_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ -#define STM32WB_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ +#define STM32_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ +#define STM32_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ +#define STM32_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ +#define STM32_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ +#define STM32_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ +#define STM32_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ +#define STM32_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ +#define STM32_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ +#define STM32_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ +#define STM32_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ +#define STM32_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ +#define STM32_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ /* Register Addresses *******************************************************/ -#define STM32WB_FLASH_ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ACR_OFFSET) -#define STM32WB_FLASH_KEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_KEYR_OFFSET) -#define STM32WB_FLASH_OPTKEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTKEYR_OFFSET) -#define STM32WB_FLASH_SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SR_OFFSET) -#define STM32WB_FLASH_CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_CR_OFFSET) -#define STM32WB_FLASH_ECCR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ECCR_OFFSET) -#define STM32WB_FLASH_OPTR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTR_OFFSET) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1ASR_OFFSET) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1AER_OFFSET) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1AR_OFFSET) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1BR_OFFSET) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BSR_OFFSET) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BER_OFFSET) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_IPCCBR_OFFSET) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2ACR_OFFSET) -#define STM32WB_FLASH_C2SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2SR_OFFSET) -#define STM32WB_FLASH_C2CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2CR_OFFSET) -#define STM32WB_FLASH_SFR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SFR_OFFSET) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHREG_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHREG_BASE + STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHREG_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHREG_BASE + STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHREG_BASE + STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHREG_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHREG_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHREG_BASE + STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHREG_BASE + STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHREG_BASE + STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHREG_BASE + STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHREG_BASE + STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHREG_BASE + STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -358,4 +358,4 @@ # define FLASH_SRRVR_C2OPT_SRAM (0 << 31) /* 0: SBRV offset addresses SRAM1/2, starting from 0x20000000 */ # define FLASH_SRRVR_C2OPT_FLASH (1 << 31) /* 1: SBRV offset addresses Flash, starting from 0x08000000 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index cc3b862168732..f105f98b5aaab 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H /**************************************************************************** * Pre-processor Definitions @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) - -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) -# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) -# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) + +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) #endif -#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -318,4 +318,4 @@ #define GPIO_BRR_RESET(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index 0e86bb6467542..f5ee36a162cb5 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H /**************************************************************************** * Pre-processor Definitions @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) -#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) -#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) -#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) -#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) -#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) -#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) -#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) -#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) -#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) - -#ifdef CONFIG_STM32WB_HAVE_I2C3 -# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) -# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) -# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) -# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) -# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) -# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) -# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) -# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) -# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) -# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) +#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) + +#ifdef CONFIG_STM32_HAVE_I2C3 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -219,4 +219,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h index 6e1d597ff1c1b..949850d2eca05 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,25 +29,25 @@ /* Register Offsets *********************************************************/ -#define STM32WB_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ -#define STM32WB_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ -#define STM32WB_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ -#define STM32WB_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ -#define STM32WB_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ -#define STM32WB_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ -#define STM32WB_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ -#define STM32WB_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ +#define STM32_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ +#define STM32_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ +#define STM32_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ +#define STM32_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ +#define STM32_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ +#define STM32_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ +#define STM32_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ +#define STM32_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ /* Register Addresses *******************************************************/ -#define STM32WB_IPCC_C1CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1CR_OFFSET) -#define STM32WB_IPCC_C1MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1MR_OFFSET) -#define STM32WB_IPCC_C1SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1SCR_OFFSET) -#define STM32WB_IPCC_C1TOC2SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1TOC2SR_OFFSET) -#define STM32WB_IPCC_C2CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2CR_OFFSET) -#define STM32WB_IPCC_C2MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2MR_OFFSET) -#define STM32WB_IPCC_C2SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2SCR_OFFSET) -#define STM32WB_IPCC_C2TOC1SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2TOC1SR_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE + STM32_IPCC_C1CR_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE + STM32_IPCC_C1MR_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE + STM32_IPCC_C1SCR_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE + STM32_IPCC_C1TOC2SR_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE + STM32_IPCC_C2CR_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE + STM32_IPCC_C2MR_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE + STM32_IPCC_C2SCR_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE + STM32_IPCC_C2TOC1SR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -113,4 +113,4 @@ #define IPCC_C2TOC1SR_MASK (0x3f << IPCC_C2TOC1SR_SHIFT) #define IPCC_C2TOC1SR_BIT(n) (1 << (IPCC_C2TOC1SR_SHIFT + (n) - 1)) /* Channel n = 1..6 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h index 58d3d249b66be..03523f9b1206c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,33 +29,33 @@ /* STM32WBXXX Address Blocks ************************************************/ -#define STM32WB_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32WB_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ -#define STM32WB_PERIPH_BASE 0x40000000 /* Peripheral base address */ -#define STM32WB_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ +#define STM32_PERIPH_BASE 0x40000000 /* Peripheral base address */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ /* Code Base Addresses ******************************************************/ -#define STM32WB_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32WB_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ -#define STM32WB_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32WB_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ -#define STM32WB_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ -#define STM32WB_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ +#define STM32_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ +#define STM32_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ -#define STM32WB_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ -#define STM32WB_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ -#define STM32WB_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ +#define STM32_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ /* System Memory Addresses **************************************************/ -#define STM32WB_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WB_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32WB_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. 5 LSB corresponds to: * 0x11: WLCSP100 / UFBGA129 * 0x13: VFQFPN68 @@ -64,96 +64,96 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WB_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WB_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32WB_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ - /* 0x40015800-0x4001ffff: Reserved */ -#define STM32WB_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32WB_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ - /* 0x50060400-0x57ffffff: Reserved */ -#define STM32WB_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ - /* 0x58004400-0x5fffffff: Reserved */ -#define STM32WB_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ - /* 0x60002000-0x8fffffff: Reserved */ -#define STM32WB_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ + /* 0x40015800-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ + /* 0x50060400-0x57ffffff: Reserved */ +#define STM32_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ + /* 0x58004400-0x5fffffff: Reserved */ +#define STM32_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ + /* 0x60002000-0x8fffffff: Reserved */ +#define STM32_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32WB_TIM2_BASE 0x40000000 -#define STM32WB_LCD_BASE 0x40002400 -#define STM32WB_RTC_BASE 0x40002800 -#define STM32WB_WWDG_BASE 0x40002c00 -#define STM32WB_IWDG_BASE 0x40003000 -#define STM32WB_SPI2_BASE 0x40003800 -#define STM32WB_I2C1_BASE 0x40005400 -#define STM32WB_I2C3_BASE 0x40005c00 -#define STM32WB_CRS_BASE 0x40006000 -#define STM32WB_USB1_BASE 0x40006800 -#define STM32WB_USB1_PMAADDR 0x40006c00 -#define STM32WB_LPTIM1_BASE 0x40007c00 -#define STM32WB_LPUART1_BASE 0x40008000 -#define STM32WB_LPTIM2_BASE 0x40009400 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_LCD_BASE 0x40002400 +#define STM32_RTC_BASE 0x40002800 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_CRS_BASE 0x40006000 +#define STM32_USB1_BASE 0x40006800 +#define STM32_USB1_PMAADDR 0x40006c00 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM2_BASE 0x40009400 /* APB2 Base Addresses ******************************************************/ -#define STM32WB_SYSCFG_BASE 0x40010000 -#define STM32WB_VREFBUF_BASE 0x40010030 -#define STM32WB_COMP1_BASE 0x40010200 -#define STM32WB_COMP2_BASE 0x40010204 -#define STM32WB_TIM1_BASE 0x40012c00 -#define STM32WB_SPI1_BASE 0x40013000 -#define STM32WB_USART1_BASE 0x40013800 -#define STM32WB_TIM16_BASE 0x40014400 -#define STM32WB_TIM17_BASE 0x40014800 -#define STM32WB_SAI1_BASE 0x40015400 +#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_COMP1_BASE 0x40010200 +#define STM32_COMP2_BASE 0x40010204 +#define STM32_TIM1_BASE 0x40012c00 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_SAI1_BASE 0x40015400 /* AHB1 Base Addresses ******************************************************/ -#define STM32WB_DMA1_BASE 0x40020000 -#define STM32WB_DMA2_BASE 0x40020400 -#define STM32WB_DMAMUX1_BASE 0x40020800 -#define STM32WB_CRC_BASE 0x40023000 -#define STM32WB_TSC_BASE 0x40024000 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_CRC_BASE 0x40023000 +#define STM32_TSC_BASE 0x40024000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WB_GPIOA_BASE 0x48000000 -#define STM32WB_GPIOB_BASE 0x48000400 -#define STM32WB_GPIOC_BASE 0x48000800 -#define STM32WB_GPIOD_BASE 0x48000c00 -#define STM32WB_GPIOE_BASE 0x48001000 -#define STM32WB_GPIOH_BASE 0x48001c00 -#define STM32WB_ADC1_BASE 0x50040000 -#define STM32WB_AES1_BASE 0x50060000 +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_ADC1_BASE 0x50040000 +#define STM32_AES1_BASE 0x50060000 /* AHB4 Base Addresses ******************************************************/ -#define STM32WB_RCC_BASE 0x58000000 -#define STM32WB_PWR_BASE 0x58000400 -#define STM32WB_EXTI_BASE 0x58000800 -#define STM32WB_IPCC_BASE 0x58000c00 -#define STM32WB_RNG_BASE 0x58001000 -#define STM32WB_HSEM_BASE 0x58001400 -#define STM32WB_AES2_BASE 0x58001800 -#define STM32WB_PKA_BASE 0x58002000 -#define STM32WB_FLASHREG_BASE 0x58004000 +#define STM32_RCC_BASE 0x58000000 +#define STM32_PWR_BASE 0x58000400 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_IPCC_BASE 0x58000c00 +#define STM32_RNG_BASE 0x58001000 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_AES2_BASE 0x58001800 +#define STM32_PKA_BASE 0x58002000 +#define STM32_FLASHREG_BASE 0x58004000 /* APB3 Base Addresses ******************************************************/ -#define STM32WB_BLE_BASE 0x60000000 -#define STM32WB_RADIO_BASE 0x60000400 -#define STM32WB_802154_BASE 0x60001000 +#define STM32_BLE_BASE 0x60000000 +#define STM32_RADIO_BASE 0x60000400 +#define STM32_802154_BASE 0x60001000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WB_QSPI_BASE 0x90000000 -#define STM32WB_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ -#define STM32WB_QSPIREF_BASE 0xa0001000 +#define STM32_QSPI_BASE 0x90000000 +#define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ +#define STM32_QSPIREF_BASE 0xa0001000 /* Cortex-M4 Base Addresses *************************************************/ @@ -161,7 +161,7 @@ * this address range */ -#define STM32WB_SCS_BASE 0xe000e000 -#define STM32WB_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h index 5b364b571643f..ebe67f6d6bdf9 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -30,12 +30,12 @@ #include #include "chip.h" -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || \ - defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) || \ - defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || \ + defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) || \ + defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55) # include "hardware/stm32wbxx_pinmap.h" #else # error "Unsupported STM32WB Pin map" #endif -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h index 8e161735c05cf..6083a1c8a0b46 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,54 +36,54 @@ /* Register Offsets *********************************************************/ -#define STM32WB_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WB_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WB_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WB_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WB_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WB_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WB_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WB_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WB_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WB_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WB_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WB_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WB_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WB_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WB_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32WB_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32WB_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32WB_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WB_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WB_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ -#define STM32WB_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ -#define STM32WB_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_PWR_CR1 (STM32WB_PWR_BASE + STM32WB_PWR_CR1_OFFSET) -#define STM32WB_PWR_CR2 (STM32WB_PWR_BASE + STM32WB_PWR_CR2_OFFSET) -#define STM32WB_PWR_CR3 (STM32WB_PWR_BASE + STM32WB_PWR_CR3_OFFSET) -#define STM32WB_PWR_CR4 (STM32WB_PWR_BASE + STM32WB_PWR_CR4_OFFSET) -#define STM32WB_PWR_SR1 (STM32WB_PWR_BASE + STM32WB_PWR_SR1_OFFSET) -#define STM32WB_PWR_SR2 (STM32WB_PWR_BASE + STM32WB_PWR_SR2_OFFSET) -#define STM32WB_PWR_SCR (STM32WB_PWR_BASE + STM32WB_PWR_SCR_OFFSET) -#define STM32WB_PWR_CR5 (STM32WB_PWR_BASE + STM32WB_PWR_CR5_OFFSET) -#define STM32WB_PWR_PUCRA (STM32WB_PWR_BASE + STM32WB_PWR_PUCRA_OFFSET) -#define STM32WB_PWR_PDCRA (STM32WB_PWR_BASE + STM32WB_PWR_PDCRA_OFFSET) -#define STM32WB_PWR_PUCRB (STM32WB_PWR_BASE + STM32WB_PWR_PUCRB_OFFSET) -#define STM32WB_PWR_PDCRB (STM32WB_PWR_BASE + STM32WB_PWR_PDCRB_OFFSET) -#define STM32WB_PWR_PUCRC (STM32WB_PWR_BASE + STM32WB_PWR_PUCRC_OFFSET) -#define STM32WB_PWR_PDCRC (STM32WB_PWR_BASE + STM32WB_PWR_PDCRC_OFFSET) -#define STM32WB_PWR_PUCRD (STM32WB_PWR_BASE + STM32WB_PWR_PUCRD_OFFSET) -#define STM32WB_PWR_PDCRD (STM32WB_PWR_BASE + STM32WB_PWR_PDCRD_OFFSET) -#define STM32WB_PWR_PUCRE (STM32WB_PWR_BASE + STM32WB_PWR_PUCRE_OFFSET) -#define STM32WB_PWR_PDCRE (STM32WB_PWR_BASE + STM32WB_PWR_PDCRE_OFFSET) -#define STM32WB_PWR_PUCRH (STM32WB_PWR_BASE + STM32WB_PWR_PUCRH_OFFSET) -#define STM32WB_PWR_PDCRH (STM32WB_PWR_BASE + STM32WB_PWR_PDCRH_OFFSET) -#define STM32WB_PWR_C2CR1 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR1_OFFSET) -#define STM32WB_PWR_C2CR3 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR3_OFFSET) -#define STM32WB_PWR_EXTSCR (STM32WB_PWR_BASE + STM32WB_PWR_EXTSCR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE + STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE + STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE + STM32_PWR_EXTSCR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -323,4 +323,4 @@ #define PWR_EXTSCR_C1DS (1 << 14) /* Bit 14: CPU1 deepsleep mode */ #define PWR_EXTSCR_C2DS (1 << 15) /* Bit 15: CPU2 deepsleep mode */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h index 2f861e3fed2d2..3c22fdb4251ab 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -35,105 +35,105 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WB_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WB_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WB_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WB_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32WB_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WB_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WB_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WB_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ -#define STM32WB_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WB_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WB_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WB_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WB_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WB_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WB_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ -#define STM32WB_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ -#define STM32WB_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WB_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WB_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32WB_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ -#define STM32WB_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ -#define STM32WB_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ /* Register Addresses *******************************************************/ -#define STM32WB_RCC_CR (STM32WB_RCC_BASE + STM32WB_RCC_CR_OFFSET) -#define STM32WB_RCC_ICSCR (STM32WB_RCC_BASE + STM32WB_RCC_ICSCR_OFFSET) -#define STM32WB_RCC_CFGR (STM32WB_RCC_BASE + STM32WB_RCC_CFGR_OFFSET) -#define STM32WB_RCC_PLLCFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLCFG_OFFSET) -#define STM32WB_RCC_PLLSAI1CFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLSAI1CFG_OFFSET) -#define STM32WB_RCC_CIER (STM32WB_RCC_BASE + STM32WB_RCC_CIER_OFFSET) -#define STM32WB_RCC_CIFR (STM32WB_RCC_BASE + STM32WB_RCC_CIFR_OFFSET) -#define STM32WB_RCC_CICR (STM32WB_RCC_BASE + STM32WB_RCC_CICR_OFFSET) -#define STM32WB_RCC_SMPSCR (STM32WB_RCC_BASE + STM32WB_RCC_SMPSCR_OFFSET) -#define STM32WB_RCC_AHB1RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1RSTR_OFFSET) -#define STM32WB_RCC_AHB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2RSTR_OFFSET) -#define STM32WB_RCC_AHB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3RSTR_OFFSET) -#define STM32WB_RCC_APB1RSTR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR1_OFFSET) -#define STM32WB_RCC_APB1RSTR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR2_OFFSET) -#define STM32WB_RCC_APB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB2RSTR_OFFSET) -#define STM32WB_RCC_APB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB3RSTR_OFFSET) -#define STM32WB_RCC_AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1ENR_OFFSET) -#define STM32WB_RCC_AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2ENR_OFFSET) -#define STM32WB_RCC_AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3ENR_OFFSET) -#define STM32WB_RCC_APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR1_OFFSET) -#define STM32WB_RCC_APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR2_OFFSET) -#define STM32WB_RCC_APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2ENR_OFFSET) -#define STM32WB_RCC_AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1SMENR_OFFSET) -#define STM32WB_RCC_AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2SMENR_OFFSET) -#define STM32WB_RCC_AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3SMENR_OFFSET) -#define STM32WB_RCC_APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR1_OFFSET) -#define STM32WB_RCC_APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR2_OFFSET) -#define STM32WB_RCC_APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2SMENR_OFFSET) -#define STM32WB_RCC_CCIPR (STM32WB_RCC_BASE + STM32WB_RCC_CCIPR_OFFSET) -#define STM32WB_RCC_BDCR (STM32WB_RCC_BASE + STM32WB_RCC_BDCR_OFFSET) -#define STM32WB_RCC_CSR (STM32WB_RCC_BASE + STM32WB_RCC_CSR_OFFSET) -#define STM32WB_RCC_CRRCR (STM32WB_RCC_BASE + STM32WB_RCC_CRRCR_OFFSET) -#define STM32WB_RCC_HSECR (STM32WB_RCC_BASE + STM32WB_RCC_HSECR_OFFSET) -#define STM32WB_RCC_EXTCFGR (STM32WB_RCC_BASE + STM32WB_RCC_EXTCFGR_OFFSET) -#define STM32WB_RCC_C2AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1ENR_OFFSET) -#define STM32WB_RCC_C2AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2ENR_OFFSET) -#define STM32WB_RCC_C2AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3ENR_OFFSET) -#define STM32WB_RCC_C2APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR1_OFFSET) -#define STM32WB_RCC_C2APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR2_OFFSET) -#define STM32WB_RCC_C2APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2ENR_OFFSET) -#define STM32WB_RCC_C2APB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3ENR_OFFSET) -#define STM32WB_RCC_C2AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1SMENR_OFFSET) -#define STM32WB_RCC_C2AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2SMENR_OFFSET) -#define STM32WB_RCC_C2AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3SMENR_OFFSET) -#define STM32WB_RCC_C2APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR1_OFFSET) -#define STM32WB_RCC_C2APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR2_OFFSET) -#define STM32WB_RCC_C2APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2SMENR_OFFSET) -#define STM32WB_RCC_C2APB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_SMPSCR (STM32_RCC_BASE + STM32_RCC_SMPSCR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_HSECR (STM32_RCC_BASE + STM32_RCC_HSECR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -876,4 +876,4 @@ #define RCC_C2APB3ENR_BLEEN (1 << 0) /* Bit 0: CPU2 LPUART1 enable in sleep and stop modes */ #define RCC_C2APB3ENR_802EN (1 << 1) /* Bit 1: CPU2 LPTIM2 enable in sleep and stop modes */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h index b02dfbcd959b9..d204aae5ddc75 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H /**************************************************************************** * Pre-processor Definitions @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32WB_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32WB_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32WB_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32WB_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32WB_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32WB_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32WB_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32WB_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32WB_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32WB_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32WB_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32WB_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32WB_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32WB_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32WB_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32WB_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32WB_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32WB_RTC_OR_OFFSET 0x004c /* RTC option register */ - -#define STM32WB_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) -#define STM32WB_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32WB_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32WB_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32WB_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32WB_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32WB_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32WB_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32WB_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32WB_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32WB_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32WB_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32WB_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32WB_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32WB_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32WB_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32WB_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32WB_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32WB_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32WB_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32WB_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ /* Register Addresses *******************************************************/ -#define STM32WB_RTC_TR (STM32WB_RTC_BASE + STM32WB_RTC_TR_OFFSET) -#define STM32WB_RTC_DR (STM32WB_RTC_BASE + STM32WB_RTC_DR_OFFSET) -#define STM32WB_RTC_CR (STM32WB_RTC_BASE + STM32WB_RTC_CR_OFFSET) -#define STM32WB_RTC_ISR (STM32WB_RTC_BASE + STM32WB_RTC_ISR_OFFSET) -#define STM32WB_RTC_PRER (STM32WB_RTC_BASE + STM32WB_RTC_PRER_OFFSET) -#define STM32WB_RTC_WUTR (STM32WB_RTC_BASE + STM32WB_RTC_WUTR_OFFSET) -#define STM32WB_RTC_ALRMAR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMAR_OFFSET) -#define STM32WB_RTC_ALRMBR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBR_OFFSET) -#define STM32WB_RTC_WPR (STM32WB_RTC_BASE + STM32WB_RTC_WPR_OFFSET) -#define STM32WB_RTC_SSR (STM32WB_RTC_BASE + STM32WB_RTC_SSR_OFFSET) -#define STM32WB_RTC_SHIFTR (STM32WB_RTC_BASE + STM32WB_RTC_SHIFTR_OFFSET) -#define STM32WB_RTC_TSTR (STM32WB_RTC_BASE + STM32WB_RTC_TSTR_OFFSET) -#define STM32WB_RTC_TSDR (STM32WB_RTC_BASE + STM32WB_RTC_TSDR_OFFSET) -#define STM32WB_RTC_TSSSR (STM32WB_RTC_BASE + STM32WB_RTC_TSSSR_OFFSET) -#define STM32WB_RTC_CALR (STM32WB_RTC_BASE + STM32WB_RTC_CALR_OFFSET) -#define STM32WB_RTC_TAMPCR (STM32WB_RTC_BASE + STM32WB_RTC_TAMPCR_OFFSET) -#define STM32WB_RTC_ALRMASSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMASSR_OFFSET) -#define STM32WB_RTC_ALRMBSSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBSSR_OFFSET) -#define STM32WB_RTC_OR (STM32WB_RTC_BASE + STM32WB_RTC_OR_OFFSET) - -#define STM32WB_RTC_BKPR(n) (STM32WB_RTC_BASE + STM32WB_RTC_BKPR_OFFSET(n)) -#define STM32WB_RTC_BKP0R (STM32WB_RTC_BASE + STM32WB_RTC_BKP0R_OFFSET) -#define STM32WB_RTC_BKP1R (STM32WB_RTC_BASE + STM32WB_RTC_BKP1R_OFFSET) -#define STM32WB_RTC_BKP2R (STM32WB_RTC_BASE + STM32WB_RTC_BKP2R_OFFSET) -#define STM32WB_RTC_BKP3R (STM32WB_RTC_BASE + STM32WB_RTC_BKP3R_OFFSET) -#define STM32WB_RTC_BKP4R (STM32WB_RTC_BASE + STM32WB_RTC_BKP4R_OFFSET) -#define STM32WB_RTC_BKP5R (STM32WB_RTC_BASE + STM32WB_RTC_BKP5R_OFFSET) -#define STM32WB_RTC_BKP6R (STM32WB_RTC_BASE + STM32WB_RTC_BKP6R_OFFSET) -#define STM32WB_RTC_BKP7R (STM32WB_RTC_BASE + STM32WB_RTC_BKP7R_OFFSET) -#define STM32WB_RTC_BKP8R (STM32WB_RTC_BASE + STM32WB_RTC_BKP8R_OFFSET) -#define STM32WB_RTC_BKP9R (STM32WB_RTC_BASE + STM32WB_RTC_BKP9R_OFFSET) -#define STM32WB_RTC_BKP10R (STM32WB_RTC_BASE + STM32WB_RTC_BKP10R_OFFSET) -#define STM32WB_RTC_BKP11R (STM32WB_RTC_BASE + STM32WB_RTC_BKP11R_OFFSET) -#define STM32WB_RTC_BKP12R (STM32WB_RTC_BASE + STM32WB_RTC_BKP12R_OFFSET) -#define STM32WB_RTC_BKP13R (STM32WB_RTC_BASE + STM32WB_RTC_BKP13R_OFFSET) -#define STM32WB_RTC_BKP14R (STM32WB_RTC_BASE + STM32WB_RTC_BKP14R_OFFSET) -#define STM32WB_RTC_BKP15R (STM32WB_RTC_BASE + STM32WB_RTC_BKP15R_OFFSET) -#define STM32WB_RTC_BKP16R (STM32WB_RTC_BASE + STM32WB_RTC_BKP16R_OFFSET) -#define STM32WB_RTC_BKP17R (STM32WB_RTC_BASE + STM32WB_RTC_BKP17R_OFFSET) -#define STM32WB_RTC_BKP18R (STM32WB_RTC_BASE + STM32WB_RTC_BKP18R_OFFSET) -#define STM32WB_RTC_BKP19R (STM32WB_RTC_BASE + STM32WB_RTC_BKP19R_OFFSET) - -# define STM32WB_RTC_BKCOUNT 20 +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE + STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE + STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE + STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE + STM32_RTC_OR_OFFSET) + +#define STM32_RTC_BKPR(n) (STM32_RTC_BASE + STM32_RTC_BKPR_OFFSET(n)) +#define STM32_RTC_BKP0R (STM32_RTC_BASE + STM32_RTC_BKP0R_OFFSET) +#define STM32_RTC_BKP1R (STM32_RTC_BASE + STM32_RTC_BKP1R_OFFSET) +#define STM32_RTC_BKP2R (STM32_RTC_BASE + STM32_RTC_BKP2R_OFFSET) +#define STM32_RTC_BKP3R (STM32_RTC_BASE + STM32_RTC_BKP3R_OFFSET) +#define STM32_RTC_BKP4R (STM32_RTC_BASE + STM32_RTC_BKP4R_OFFSET) +#define STM32_RTC_BKP5R (STM32_RTC_BASE + STM32_RTC_BKP5R_OFFSET) +#define STM32_RTC_BKP6R (STM32_RTC_BASE + STM32_RTC_BKP6R_OFFSET) +#define STM32_RTC_BKP7R (STM32_RTC_BASE + STM32_RTC_BKP7R_OFFSET) +#define STM32_RTC_BKP8R (STM32_RTC_BASE + STM32_RTC_BKP8R_OFFSET) +#define STM32_RTC_BKP9R (STM32_RTC_BASE + STM32_RTC_BKP9R_OFFSET) +#define STM32_RTC_BKP10R (STM32_RTC_BASE + STM32_RTC_BKP10R_OFFSET) +#define STM32_RTC_BKP11R (STM32_RTC_BASE + STM32_RTC_BKP11R_OFFSET) +#define STM32_RTC_BKP12R (STM32_RTC_BASE + STM32_RTC_BKP12R_OFFSET) +#define STM32_RTC_BKP13R (STM32_RTC_BASE + STM32_RTC_BKP13R_OFFSET) +#define STM32_RTC_BKP14R (STM32_RTC_BASE + STM32_RTC_BKP14R_OFFSET) +#define STM32_RTC_BKP15R (STM32_RTC_BASE + STM32_RTC_BKP15R_OFFSET) +#define STM32_RTC_BKP16R (STM32_RTC_BASE + STM32_RTC_BKP16R_OFFSET) +#define STM32_RTC_BKP17R (STM32_RTC_BASE + STM32_RTC_BKP17R_OFFSET) +#define STM32_RTC_BKP18R (STM32_RTC_BASE + STM32_RTC_BKP18R_OFFSET) +#define STM32_RTC_BKP19R (STM32_RTC_BASE + STM32_RTC_BKP19R_OFFSET) + +# define STM32_RTC_BKCOUNT 20 /* Register Bitfield Definitions ********************************************/ @@ -387,4 +387,4 @@ # define RTC_OR_OUTRMP_PC13 (0 << 1) /* 0: Alarm/calibration output on PC13 */ # define RTC_OR_OUTRMP_PB2PC13 (1 << 1) /* 1: Alarm/calibration output on PB2 or PC13 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index 62851ed763479..f1d417c62db02 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H /**************************************************************************** * Included Files @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32WB_SPI_CLK_MAX 32000000ul +#define STM32_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) -#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) -#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) -#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) -#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) -#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) -#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) - -#if CONFIG_STM32WB_HAVE_SPI2 -# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) -# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) -# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) -# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) -# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) -# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) -# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) +#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) + +#if CONFIG_STM32_HAVE_SPI2 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -150,4 +150,4 @@ # define SPI_SR_FTLVL_HALF (0x2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (0x3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h index a4cfa546324b4..59ffc5b527b78 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -35,42 +35,42 @@ /* Register Offsets *********************************************************/ -#define STM32WB_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WB_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ -#define STM32WB_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WB_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WB_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WB_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WB_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WB_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ -#define STM32WB_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WB_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32WB_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ -#define STM32WB_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ -#define STM32WB_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ -#define STM32WB_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ -#define STM32WB_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ +#define STM32_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ /* Register Addresses *******************************************************/ -#define STM32WB_SYSCFG_MEMRMP (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_MEMRMP_OFFSET) -#define STM32WB_SYSCFG_CFGR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR(p) (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WB_SYSCFG_EXTICR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR2_OFFSET) -#define STM32WB_SYSCFG_EXTICR3 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR3_OFFSET) -#define STM32WB_SYSCFG_EXTICR4 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR4_OFFSET) -#define STM32WB_SYSCFG_SCSR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SCSR_OFFSET) -#define STM32WB_SYSCFG_CFGR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR2_OFFSET) -#define STM32WB_SYSCFG_SWPR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR1_OFFSET) -#define STM32WB_SYSCFG_SKR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SKR_OFFSET) -#define STM32WB_SYSCFG_SWPR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR1_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -226,4 +226,4 @@ #define SYSCFG_SIPCR_SPKA (1 << 2) /* Bit 2: PKA Security enable */ #define SYSCFG_SIPCR_SRNG (1 << 3) /* Bit 3: RNG Security enable */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h index 6e646a6dc2f75..e4936d2ac8bc0 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -29,150 +29,150 @@ /* Register Offsets *********************************************************/ -#define STM32WB_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WB_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WB_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32WB_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32WB_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32WB_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32WB_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32WB_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WB_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32WB_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32WB_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32WB_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32WB_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32WB_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32WB_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32WB_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32WB_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32WB_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WB_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32WB_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32WB_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32WB_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32WB_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32WB_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ +#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ +#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ +#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ +#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ +#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ +#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ +#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ +#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ +#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ +#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ +#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ +#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ +#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ +#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ +#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ +#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ +#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ +#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ +#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ +#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ +#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ /* Register Addresses *******************************************************/ /* Advanced Timer TIM1 */ -#define STM32WB_TIM1_CR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM1_CR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM1_SMCR (STM32WB_TIM1_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM1_DIER (STM32WB_TIM1_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM1_SR (STM32WB_TIM1_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM1_EGR (STM32WB_TIM1_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM1_CCMR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM1_CCMR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM1_CCER (STM32WB_TIM1_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM1_CNT (STM32WB_TIM1_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM1_PSC (STM32WB_TIM1_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM1_ARR (STM32WB_TIM1_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM1_RCR (STM32WB_TIM1_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM1_CCR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM1_CCR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM1_CCR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM1_CCR4 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM1_BDTR (STM32WB_TIM1_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM1_DCR (STM32WB_TIM1_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM1_DMAR (STM32WB_TIM1_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM1_OR1 (STM32WB_TIM1_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM1_CCMR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR3_OFFSET) -#define STM32WB_TIM1_CCR5 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR5_OFFSET) -#define STM32WB_TIM1_CCR6 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR6_OFFSET) -#define STM32WB_TIM1_AF1 (STM32WB_TIM1_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM1_AF2 (STM32WB_TIM1_BASE + STM32WB_TIM_AF2_OFFSET) -#define STM32WB_TIM1_TISEL (STM32WB_TIM1_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) +#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) +#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) /* General 32-bit Timer TIM2 */ -#define STM32WB_TIM2_CR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM2_CR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM2_SMCR (STM32WB_TIM2_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM2_DIER (STM32WB_TIM2_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM2_SR (STM32WB_TIM2_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM2_EGR (STM32WB_TIM2_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM2_CCMR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM2_CCMR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM2_CCER (STM32WB_TIM2_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM2_CNT (STM32WB_TIM2_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM2_PSC (STM32WB_TIM2_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM2_ARR (STM32WB_TIM2_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM2_CCR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM2_CCR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM2_CCR3 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM2_CCR4 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM2_DCR (STM32WB_TIM2_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM2_DMAR (STM32WB_TIM2_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM2_OR1 (STM32WB_TIM2_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM2_AF1 (STM32WB_TIM2_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM2_TISEL (STM32WB_TIM2_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) /* General Timers TIM16/TIM17 */ -#define STM32WB_TIM16_CR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM16_CR2 (STM32WB_TIM16_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM16_DIER (STM32WB_TIM16_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM16_SR (STM32WB_TIM16_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM16_EGR (STM32WB_TIM16_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM16_CCMR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM16_CCER (STM32WB_TIM16_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM16_CNT (STM32WB_TIM16_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM16_PSC (STM32WB_TIM16_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM16_ARR (STM32WB_TIM16_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM16_RCR (STM32WB_TIM16_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM16_CCR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM16_BDTR (STM32WB_TIM16_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM16_DCR (STM32WB_TIM16_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM16_DMAR (STM32WB_TIM16_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM16_OR1 (STM32WB_TIM16_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM16_AF1 (STM32WB_TIM16_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM16_TISEL (STM32WB_TIM16_BASE + STM32WB_TIM_TISEL_OFFSET) - -#define STM32WB_TIM17_CR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM17_CR2 (STM32WB_TIM17_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM17_DIER (STM32WB_TIM17_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM17_SR (STM32WB_TIM17_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM17_EGR (STM32WB_TIM17_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM17_CCMR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM17_CCER (STM32WB_TIM17_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM17_CNT (STM32WB_TIM17_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM17_PSC (STM32WB_TIM17_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM17_ARR (STM32WB_TIM17_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM17_RCR (STM32WB_TIM17_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM17_CCR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM17_BDTR (STM32WB_TIM17_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM17_DCR (STM32WB_TIM17_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM17_DMAR (STM32WB_TIM17_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM17_OR1 (STM32WB_TIM17_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM17_AF1 (STM32WB_TIM17_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM17_TISEL (STM32WB_TIM17_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) /* Register Value Constants *************************************************/ /* Digital Filter options */ -#define STM32WB_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32WB_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32WB_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32WB_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32WB_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32WB_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32WB_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32WB_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32WB_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32WB_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32WB_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32WB_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32WB_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32WB_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32WB_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32WB_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ +#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ +#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ +#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ +#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ +#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ +#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ +#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ +#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ +#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ +#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ +#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ +#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ +#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ +#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ +#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ +#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ /* Register Bitfield Definitions ********************************************/ @@ -397,7 +397,7 @@ #define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) @@ -450,7 +450,7 @@ #define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) @@ -920,7 +920,7 @@ #define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) @@ -931,7 +931,7 @@ #define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) @@ -942,7 +942,7 @@ #define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) @@ -953,7 +953,7 @@ #define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) @@ -964,7 +964,7 @@ #define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) @@ -975,7 +975,7 @@ #define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) @@ -986,7 +986,7 @@ #define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) @@ -997,7 +997,7 @@ #define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) @@ -1008,7 +1008,7 @@ #define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) @@ -1019,7 +1019,7 @@ #define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ /* Capture/compare enable register */ @@ -1178,11 +1178,11 @@ #define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ #define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ #define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ @@ -1384,4 +1384,4 @@ #define TIM17_TISEL_TI1SEL_MASK (0xf << TIM17_TISEL_TI1SEL_SHIFT) # define TIM17_TISEL_TI1SEL_CH1 (0x0 << TIM17_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h index 2ce1c1b6268bf..4cc8184015d2b 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,34 +37,34 @@ /* Register Offsets *********************************************************/ -#define STM32WB_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32WB_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32WB_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32WB_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ -#define STM32WB_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32WB_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32WB_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32WB_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32WB_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ -#define STM32WB_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32WB_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32WB_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ /* Register Addresses *******************************************************/ -#if STM32WB_NUSART > 0 -# define STM32WB_USART1_CR1 (STM32WB_USART1_BASE + STM32WB_USART_CR1_OFFSET) -# define STM32WB_USART1_CR2 (STM32WB_USART1_BASE + STM32WB_USART_CR2_OFFSET) -# define STM32WB_USART1_CR3 (STM32WB_USART1_BASE + STM32WB_USART_CR3_OFFSET) -# define STM32WB_USART1_BRR (STM32WB_USART1_BASE + STM32WB_USART_BRR_OFFSET) -# define STM32WB_USART1_GTPR (STM32WB_USART1_BASE + STM32WB_USART_GTPR_OFFSET) -# define STM32WB_USART1_RTOR (STM32WB_USART1_BASE + STM32WB_USART_RTOR_OFFSET) -# define STM32WB_USART1_RQR (STM32WB_USART1_BASE + STM32WB_USART_RQR_OFFSET) -# define STM32WB_USART1_ISR (STM32WB_USART1_BASE + STM32WB_USART_ISR_OFFSET) -# define STM32WB_USART1_ICR (STM32WB_USART1_BASE + STM32WB_USART_ICR_OFFSET) -# define STM32WB_USART1_RDR (STM32WB_USART1_BASE + STM32WB_USART_RDR_OFFSET) -# define STM32WB_USART1_TDR (STM32WB_USART1_BASE + STM32WB_USART_TDR_OFFSET) -# define STM32WB_USART1_PRESC (STM32WB_USART1_BASE + STM32WB_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -338,4 +338,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h index ab8255bba6bb9..d511cb6d39eea 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h @@ -58,11 +58,11 @@ /* ADC */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN4_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) -#elif defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#elif defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_ADC1_IN1_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) @@ -77,14 +77,14 @@ #define GPIO_ADC1_IN10_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC1_IN11_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_ADC1_IN12_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN15_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN16_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_ADC1_IN13_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) # define GPIO_ADC1_IN14_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) #endif @@ -95,7 +95,7 @@ /* Comparators */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) @@ -106,7 +106,7 @@ #define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN0) #define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN0) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_COMP1_INP_3 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) # define GPIO_COMP1_INM_5 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) # define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN10) @@ -124,11 +124,11 @@ #define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN7) #define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN5) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* I2C */ @@ -141,17 +141,17 @@ #define GPIO_I2C1_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN14) #define GPIO_I2C1_SMBA_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN5) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN4) #define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7) #define GPIO_I2C3_SMBA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN2) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_I2C3_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12) # define GPIO_I2C3_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11) # define GPIO_I2C3_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN14) @@ -161,7 +161,7 @@ # define GPIO_I2C3_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* JTAG/SWD */ @@ -169,14 +169,14 @@ #define GPIO_JTCK_SWCLK_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_NJTRST_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_JTDO_SWO_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3) # define GPIO_JTDI_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15) #endif /* QUADSPI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_QSPI_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2) #define GPIO_QSPI_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3) @@ -185,12 +185,12 @@ #define GPIO_QSPI_BK1_IO2_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN7) #define GPIO_QSPI_BK1_IO3_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_QSPI_NCS_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN11) # define GPIO_QSPI_CLK_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN10) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_QSPI_NCS_3 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN3) # define GPIO_QSPI_BK1_IO0_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN4) # define GPIO_QSPI_BK1_IO1_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN5) @@ -198,14 +198,14 @@ # define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN7) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* RTC */ #define GPIO_RTC_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN2) #define GPIO_RTC_TAMP2_0 (GPIO_PORTA | GPIO_PIN0) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_RTC_OUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13) # define GPIO_RTC_REFIN_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15) # define GPIO_RTC_TS_0 (GPIO_PORTC | GPIO_PIN13) @@ -215,7 +215,7 @@ /* SAI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_SAI1_EXTCLK_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN0) #define GPIO_SAI1_EXTCLK_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN2) @@ -239,7 +239,7 @@ #define GPIO_SAI1_PDMDI2_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN9) #define GPIO_SAI1_PDMDI2_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_SAI1_FS_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN12) # define GPIO_SAI1_SCK_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN10) # define GPIO_SAI1_SCK_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN13) @@ -249,7 +249,7 @@ # define GPIO_SAI1_PDMDI1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTC | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_SAI1_SD_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTD | GPIO_PIN6) # define GPIO_SAI1_MCLK_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTE | GPIO_PIN2) # define GPIO_SAI1_SCK_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTC | GPIO_PIN9) @@ -257,7 +257,7 @@ # define GPIO_SAI1_PDMDI1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN6) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* SPI */ @@ -272,19 +272,19 @@ #define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11) #define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN15) # define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN5) # define GPIO_SPI1_MOSI_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13) # define GPIO_SPI1_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN14) # define GPIO_SPI1_NSS_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6) #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) #define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) #define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) @@ -299,13 +299,13 @@ #define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14) #define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN2) -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_SPI2_SCK_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN3) # define GPIO_SPI2_MOSI_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN4) # define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB55) */ /* Timers */ @@ -326,11 +326,11 @@ #define GPIO_TIM1_CH4IN_0 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) #define GPIO_TIM1_CH4OUT_0 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TIM1_BKIN1_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TIM1_BKIN1_5 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) @@ -338,7 +338,7 @@ # define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN0) # define GPIO_TIM1_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN14) # define GPIO_TIM1_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN14) @@ -346,12 +346,12 @@ # define GPIO_TIM1_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_TIM1_CH3IN_2 (GPIO_ALT | GPIO_AF12 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) # define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32_IO_CONFIG_C_48E) # define GPIO_TIM1_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN14) # define GPIO_TIM1_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN14) #endif @@ -369,7 +369,7 @@ #define GPIO_TIM2_CH4IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN3) #define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_TIM2_ETR_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN15) # define GPIO_TIM2_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15) # define GPIO_TIM2_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) @@ -377,14 +377,14 @@ # define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10) # define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10) # define GPIO_TIM2_CH4IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN11) # define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32_IO_CONFIG_C_48E) # define GPIO_TIM2_CH1IN_4 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN15) # define GPIO_TIM2_CH1OUT_4 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15) # define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN12) @@ -393,8 +393,8 @@ # define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_TIM16_BKIN_0 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5) #define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) @@ -403,7 +403,7 @@ #define GPIO_TIM16_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN6) #define GPIO_TIM16_CH1N_0 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TIM16_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN0) # define GPIO_TIM16_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN0) #endif @@ -415,12 +415,12 @@ #define GPIO_TIM17_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) #define GPIO_TIM17_CH1N_0 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TIM17_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN1) # define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6) #define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) @@ -428,7 +428,7 @@ #define GPIO_LPTIM1_IN1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5) #define GPIO_LPTIM1_IN2_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_LPTIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3) # define GPIO_LPTIM1_IN1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0) # define GPIO_LPTIM1_OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1) @@ -440,12 +440,12 @@ #define GPIO_LPTIM2_OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8) #define GPIO_LPTIM2_IN1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN1) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_LPTIM2_ETR_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN3) # define GPIO_LPTIM2_IN1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN0) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_LPTIM2_ETR_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN11) # define GPIO_LPTIM2_OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN13) # define GPIO_LPTIM2_IN1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN12) @@ -453,22 +453,22 @@ /* Touch Screen Controller */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_SYNC_2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN2) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) || defined(CONFIG_STM32WB_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) || defined(CONFIG_STM32_IO_CONFIG_C_48E) # define GPIO_TSC_G1_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TSC_G1_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G1_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN14) # define GPIO_TSC_G1_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN15) #endif @@ -478,52 +478,52 @@ #define GPIO_TSC_G2_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN6) #define GPIO_TSC_G2_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN7) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_TSC_G3_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G3_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN10) # define GPIO_TSC_G3_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN11) # define GPIO_TSC_G3_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN12) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32_IO_CONFIG_C_48E) # define GPIO_TSC_G3_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) # define GPIO_TSC_G3_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN1) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G4_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN6) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G4_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN7) # define GPIO_TSC_G4_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN8) # define GPIO_TSC_G4_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G5_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN4) # define GPIO_TSC_G5_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN5) # define GPIO_TSC_G5_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN6) # define GPIO_TSC_G5_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN7) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G6_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN10) # define GPIO_TSC_G6_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN11) # define GPIO_TSC_G6_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN12) # define GPIO_TSC_G6_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN0) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN1) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2) #endif -#if defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB15) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN13) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN10) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN8) @@ -531,24 +531,24 @@ #define GPIO_TSC_G7_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN9) -#endif /* defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) */ /* IR interface (with timers 16 and 17) */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN13) # define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN9) #endif /* Trace port */ -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TRACED1_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) # define GPIO_TRACED3_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12) #endif -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_TRACECK_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2) # define GPIO_TRACED0_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN9) # define GPIO_TRACED2_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2) @@ -566,11 +566,11 @@ #define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN4) #define GPIO_USART1_RTS_DE_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12) -#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32_IO_CONFIG_C_49) # define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2) #define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5) @@ -579,7 +579,7 @@ #define GPIO_LPUART1_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6) #define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN1) -#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_LPUART1_TX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN11) # define GPIO_LPUART1_TX_4 (GPIO_ALT | GPIO_AF8 | GPIO_PORTC | GPIO_PIN1) # define GPIO_LPUART1_RX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN10) @@ -588,21 +588,21 @@ # define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* USB */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_USB_CRS_SYNC_0 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN10) #define GPIO_USB_DM_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) #define GPIO_USB_DP_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) #define GPIO_USB_NOE_1 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN13) -#if defined(CONFIG_STM32WB_IO_CONFIG_V) +#if defined(CONFIG_STM32_IO_CONFIG_V) # define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WBXX_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32wb.h index 25327d74d906e..8b54c5f9d2d6e 100644 --- a/arch/arm/src/stm32wb/stm32wb.h +++ b/arch/arm/src/stm32wb/stm32wb.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_H +#define __ARCH_ARM_SRC_STM32WB_STM32_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index 1192100de8fc2..23c485617ba6a 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -60,21 +60,21 @@ /* Set the range of system SRAM1 */ -#define SRAM1_START STM32WB_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32WB_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM1_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2a as well, requires a second memory region */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2B_HEAP +# define SRAM2B_START STM32_SRAM2B_BASE +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -82,25 +82,25 @@ * that we have been asked to add to the heap. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# if SRAM2A_END > STM32WB_SRAM2A_BASE + STM32WB_SRAM2A_SIZE +#ifdef CONFIG_STM32_SRAM2A_HEAP +# if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# if SRAM2B_END > STM32WB_SRAM2B_BASE + STM32WB_SRAM2B_SIZE +#ifdef CONFIG_STM32_SRAM2B_HEAP +# if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -283,7 +283,7 @@ void arm_addregion(void) * from the release notes for STM32WB coprocessor wireless binaries. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -301,9 +301,9 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START); -#endif /* CONFIG_STM32WB_SRAM2A_HEAP */ +#endif /* CONFIG_STM32_SRAM2A_HEAP */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -321,6 +321,6 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START); -#endif /* CONFIG_STM32WB_SRAM2B_HEAP */ +#endif /* CONFIG_STM32_SRAM2B_HEAP */ } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 4e5de9fc88a0e..32472809c6417 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,61 +45,61 @@ /* HCI event header fields helpers */ -#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32WB_BLE_PREP_WRITE_NUM \ - STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) +#define STM32_BLE_PREP_WRITE_NUM \ + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) -#define STM32WB_C2_MEM_BLOCK_NUM \ - STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ - CONFIG_STM32WB_BLE_MAX_CONN, \ - STM32WB_BLE_PREP_WRITE_NUM) +#define STM32_C2_MEM_BLOCK_NUM \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ + CONFIG_STM32_BLE_MAX_CONN, \ + STM32_BLE_PREP_WRITE_NUM) -#ifdef CONFIG_STM32WB_BLE_C2HOST -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST +#ifdef CONFIG_STM32_BLE_C2HOST +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif -#ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +#ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +#ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif -#ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +#ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +#ifdef CONFIG_STM32_BLE_POWER_CLASS_1 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32WB_BLE_INIT_OPTIONS \ - (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ - STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ - STM32WB_BLE_POWER_CLASS) +#define STM32_BLE_INIT_OPTIONS \ + (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ + STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ + STM32_BLE_POWER_CLASS) -#ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +#ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** @@ -200,21 +200,21 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) switch (evt->type) { - case STM32WB_MBOX_HCIEVT: + case STM32_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,29 +247,29 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32WB_MBOX_HCIACL: + case STM32_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32WB_MBOX_SYSEVT: + case STM32_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { stm32wb_blehci_bleinit(); } break; - case STM32WB_MBOX_SYSACK: + case STM32_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); @@ -299,26 +299,26 @@ static void stm32wb_blehci_bleinit(void) { .ble_buf = NULL, .ble_buf_size = 0, - .gatt_attr_num = CONFIG_STM32WB_BLE_GATT_MAX_ATTR_NUM, - .gatt_srv_num = CONFIG_STM32WB_BLE_GATT_MAX_SVC_NUM, - .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, - .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, - .dle_enable = CONFIG_STM32WB_BLE_DLE, - .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, - .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, - .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, - .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, - .ls_clock_source = CONFIG_STM32WB_BLE_LS_CLK_SRC, - .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, - .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, - .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, - .options = STM32WB_BLE_INIT_OPTIONS, + .gatt_attr_num = CONFIG_STM32_BLE_GATT_MAX_ATTR_NUM, + .gatt_srv_num = CONFIG_STM32_BLE_GATT_MAX_SVC_NUM, + .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, + .max_conn = CONFIG_STM32_BLE_MAX_CONN, + .dle_enable = CONFIG_STM32_BLE_DLE, + .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32_C2_MEM_BLOCK_NUM, + .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, + .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, + .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, + .ls_clock_source = CONFIG_STM32_BLE_LS_CLK_SRC, + .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, + .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, + .viterbi_enable = CONFIG_STM32_BLE_VITERBI, + .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, - .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, - .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, - .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, - .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI + .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, + .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, + .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, + .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.h b/arch/arm/src/stm32wb/stm32wb_blehci.h index a8d5f6229d50b..83525224e1098 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.h +++ b/arch/arm/src/stm32wb/stm32wb_blehci.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H /**************************************************************************** * Included Files @@ -67,4 +67,4 @@ void stm32wb_blehci_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_BLEHCI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_BLEHCI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index ae37c4e53e096..60509469bef54 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -42,19 +42,19 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32WB_DMAMUX -# error "Configuration error, CONFIG_STM32WB_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -159,7 +159,7 @@ struct stm32wb_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32wb_dma12_disable(DMA_CHANNEL dmachan); static int stm32wb_dma12_interrupt(int irq, void *context, void *arg); static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -205,7 +205,7 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -225,7 +225,7 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -253,7 +253,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32WB_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -264,7 +264,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32WB_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -274,7 +274,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32WB_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -286,123 +286,123 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { .ctrl = DMA1, .chan = 0, - .irq = STM32WB_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32WB_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32WB_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32WB_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32WB_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32WB_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32WB_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { .ctrl = DMA2, .chan = 0, - .irq = STM32WB_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32WB_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32WB_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32WB_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32WB_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32WB_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32WB_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -564,7 +564,7 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32wb_dma12_disable @@ -582,17 +582,17 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -616,22 +616,22 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32WB_DMA1 - else if (irq >= STM32WB_IRQ_DMA1CH1 && irq <= STM32WB_IRQ_DMA1CH7) +#ifdef CONFIG_STM32_DMA1 + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32WB_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32WB_DMA2 - else if (irq >= STM32WB_IRQ_DMA2CH1 && irq <= STM32WB_IRQ_DMA2CH5) +#ifdef CONFIG_STM32_DMA2 + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32WB_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32WB_IRQ_DMA2CH6 && irq <= STM32WB_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32WB_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -647,7 +647,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -660,7 +660,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -689,7 +689,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -697,28 +697,28 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -726,7 +726,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -734,7 +734,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -762,7 +762,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -796,7 +796,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -809,7 +809,7 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -824,11 +824,11 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -857,19 +857,19 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08x]: %08x\n", - dmabase + STM32WB_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -878,7 +878,7 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32wb_dmamux_sample @@ -888,13 +888,13 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32wb_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -908,20 +908,20 @@ static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1179,7 +1179,7 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1224,7 +1224,7 @@ void stm32wb_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1270,7 +1270,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; @@ -1315,23 +1315,23 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32WB_REGION_MASK) != (mend & STM32WB_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32WB_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32WB_PERIPH_BASE: - case STM32WB_FSMC_BASE: - case STM32WB_FSMC_BANK1: - case STM32WB_FSMC_BANK2: - case STM32WB_FSMC_BANK3: - case STM32WB_QSPI_BANK: - case STM32WB_SRAM_BASE: - case STM32WB_SRAM2_BASE: - case STM32WB_SRAM3_BASE: - case STM32WB_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index 6caff11690612..27474afce3cea 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_DMA_H +#define __ARCH_ARM_SRC_STM32WB_STM32_DMA_H /**************************************************************************** * Included Files @@ -78,7 +78,7 @@ struct stm32wb_dmaregs_s uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32WB_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -233,7 +233,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32wb_dmacapable(maddr, count, ccr) (true) @@ -280,4 +280,4 @@ void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_DMA_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index a0e29b306f188..b29a131b57feb 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -49,13 +49,13 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32WB_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) 'D', #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) 'E', #endif 'H' @@ -88,31 +88,31 @@ int stm32wb_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32WB_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32WB_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32WB_GPIO_MODER_OFFSET), - getreg32(base + STM32WB_GPIO_OTYPER_OFFSET), - getreg32(base + STM32WB_GPIO_OSPEED_OFFSET), - getreg32(base + STM32WB_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32WB_GPIO_IDR_OFFSET), - getreg32(base + STM32WB_GPIO_ODR_OFFSET), - getreg32(base + STM32WB_GPIO_BSRR_OFFSET), - getreg32(base + STM32WB_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32WB_GPIO_AFRH_OFFSET), - getreg32(base + STM32WB_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08x\n", - g_portchar[port], getreg32(STM32WB_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_exti.h b/arch/arm/src/stm32wb/stm32wb_exti.h index 4049422399141..5a9341ce6540a 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/stm32wb_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H /**************************************************************************** * Included Files @@ -128,4 +128,4 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index a0076663dba61..8a4b9cf1538fc 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -71,7 +71,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32WB_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCALARM), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCALARM), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCALARM) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 8ef567ccd1dc7..6d5afe56e694e 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -71,7 +71,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(0), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(0), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -92,7 +92,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(1), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(1), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -113,7 +113,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(2), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(2), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -134,7 +134,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(3), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(3), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -155,7 +155,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(4), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(4), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -179,7 +179,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WB_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -192,7 +192,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WB_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -265,7 +265,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WB_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -293,14 +293,14 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WB_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wb_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WB_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wb_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -351,19 +351,19 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(pin), risingedge ? EXTI_RTSR1_RT(pin) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(pin), fallingedge ? EXTI_FTSR1_FT(pin) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(pin), event ? EXTI_C1EMR1_EM(pin) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(pin), func ? EXTI_C1IMR1_IM(pin) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index d470837ff4d00..8caaed920191f 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -69,7 +69,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,29 +114,29 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); - up_enable_irq(STM32WB_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32WB_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_PVD), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_PVD), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_PVD) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_PVD), event ? EXTI_C1EMR1_EM(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_PVD), func ? EXTI_C1IMR1_IM(EXTI_EVT_PVD) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index eae587fda8e1b..0e44b3f4dcc2d 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -71,7 +71,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_RTC_WAKEUP, STM32WB_EXTI_PR1); + putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32WB_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 5d151d37c75dc..62efc7e11a941 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -48,7 +48,7 @@ #include "stm32wb_waste.h" #include "stm32wb_flash.h" -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -63,7 +63,7 @@ #define OPTBYTES_KEY1 0x08192a3b #define OPTBYTES_KEY2 0x4c5d6e7f -#define FLASH_PAGE_SIZE STM32WB_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ @@ -91,35 +91,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WB_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WB_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WB_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WB_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -136,17 +136,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_STRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -225,20 +225,20 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WB_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WB_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } @@ -251,42 +251,42 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WB_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WB_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WB_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WB_FLASH_PAGESIZE + STM32WB_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WB_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -298,7 +298,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WB_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -336,7 +336,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -369,12 +369,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WB_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WB_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -444,23 +444,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } /* Verify */ - if (getreg32(STM32WB_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -468,13 +468,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -494,9 +494,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WB_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WB_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.h b/arch/arm/src/stm32wb/stm32wb_flash.h index 36077d8b0f85c..2476cd597e2c0 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/stm32wb_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H /**************************************************************************** * Included Files @@ -57,4 +57,4 @@ int stm32wb_flash_unlock(void); uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index a4168046aa411..95ffa6455ef6a 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -37,7 +37,7 @@ #include "stm32wb_freerun.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions @@ -69,7 +69,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); return OK; } #endif /* CONFIG_CLOCK_TIMEKEEPING */ @@ -117,14 +117,14 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, return -EBUSY; } - STM32WB_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. */ freerun->chan = chan; - freerun->width = STM32WB_TIM_GETWIDTH(freerun->tch); + freerun->width = STM32_TIM_GETWIDTH(freerun->tch); #ifdef CONFIG_CLOCK_TIMEKEEPING freerun->counter_mask = 0xffffffff; @@ -135,21 +135,21 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); #endif /* Set timer period */ - STM32WB_TIM_SETPERIOD(freerun->tch, + STM32_TIM_SETPERIOD(freerun->tch, (uint32_t)((1ull << freerun->width) - 1)); /* Start the counter */ - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); #ifndef CONFIG_CLOCK_TIMEKEEPING - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); #endif return OK; @@ -198,9 +198,9 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32WB_TIM_GETCOUNTER(freerun->tch); - pending = STM32WB_TIM_CHECKINT(freerun->tch, 0); - verify = STM32WB_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -208,7 +208,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, if (pending) { - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -256,7 +256,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, uint64_t *counter) { - *counter = STM32WB_TIM_GETCOUNTER(freerun->tch); + *counter = STM32_TIM_GETCOUNTER(freerun->tch); return OK; } @@ -285,9 +285,9 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32WB_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ @@ -297,4 +297,4 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index ef95f59c32e5e..e545d8456dcde 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H +#define __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types @@ -158,5 +158,5 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun); } #endif -#endif /* CONFIG_STM32WB_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ +#endif /* CONFIG_STM32_FREERUN */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index d857d472a502c..433df3cea150c 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -52,14 +52,14 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WB_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { - STM32WB_GPIOA_BASE, - STM32WB_GPIOB_BASE, - STM32WB_GPIOC_BASE, - STM32WB_GPIOD_BASE, - STM32WB_GPIOE_BASE, - STM32WB_GPIOH_BASE + STM32_GPIOA_BASE, + STM32_GPIOB_BASE, + STM32_GPIOC_BASE, + STM32_GPIOD_BASE, + STM32_GPIOE_BASE, + STM32_GPIOH_BASE }; /**************************************************************************** @@ -119,7 +119,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WB_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -168,10 +168,10 @@ int stm32wb_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WB_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -194,10 +194,10 @@ int stm32wb_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WB_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -212,17 +212,17 @@ int stm32wb_configgpio(uint32_t cfgset) if (pin < 8) { - regval = getreg32(base + STM32WB_GPIO_AFRL_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRL_OFFSET); regval &= ~GPIO_AFRL_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRL_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRL_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRL_OFFSET); } else { - regval = getreg32(base + STM32WB_GPIO_AFRH_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRH_OFFSET); regval &= ~GPIO_AFRH_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRH_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRH_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRH_OFFSET); } /* Set speed (Only outputs and alternate function pins) */ @@ -254,14 +254,14 @@ int stm32wb_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WB_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WB_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -274,7 +274,7 @@ int stm32wb_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WB_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -291,7 +291,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WB_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -353,7 +353,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -374,7 +374,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WB_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -393,7 +393,7 @@ bool stm32wb_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -402,7 +402,7 @@ bool stm32wb_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WB_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index befb722c0eeb6..94b52f3358f5e 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H /**************************************************************************** * Included Files @@ -44,12 +44,12 @@ * Pre-Processor Declarations ****************************************************************************/ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 6 -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 5 +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_NPORTS 6 +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) +# define STM32_NPORTS 5 #else -# define STM32WB_NPORTS 4 +# define STM32_NPORTS 4 #endif /* Bit-encoded input to stm32wb_configgpio() */ @@ -195,11 +195,11 @@ # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTE (3 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (4 << GPIO_PORT_SHIFT) /* GPIOH */ #else @@ -250,7 +250,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WB_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes @@ -371,4 +371,4 @@ void stm32wb_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 3d7d6b8db1911..fe8718c1c2d3e 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -32,7 +32,7 @@ * Standard-mode (up to 100 kHz) * Fast-mode (up to 400 kHz) * Fast-mode+ (up to 1 MHz) - * Clock source selection is based on STM32WB_RCC_CCIPR register + * Clock source selection is based on STM32_RCC_CCIPR register * * - Multiple instances (shared bus) * - Interrupt based operation @@ -111,26 +111,26 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32WB_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32WB_I2C1 - * CONFIG_STM32WB_I2C3 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C3 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32WB_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32WB_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32WB_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32WB_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32WB_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -190,7 +190,7 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32WB_I2C1) || defined(CONFIG_STM32WB_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3) /**************************************************************************** * Pre-processor Definitions @@ -202,25 +202,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32WB_I2CTIMEOSEC) && !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 -# define CONFIG_STM32WB_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32WB_I2CTIMEOSEC) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32WB_I2CTIMEOTICKS -# define CONFIG_STM32WB_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32WB_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32WB_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32WB_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert an I2C pin to a GPIO output */ @@ -383,9 +383,9 @@ static inline void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv); static inline @@ -429,17 +429,17 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = { - .base = STM32WB_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C1EV, - .er_irq = STM32WB_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -465,17 +465,17 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = }; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = { - .base = STM32WB_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C3EV, - .er_irq = STM32WB_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -598,7 +598,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -615,7 +615,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -631,7 +631,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -663,7 +663,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -673,12 +673,12 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32wb_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32WB_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -701,7 +701,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -717,10 +717,10 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32wb_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -769,7 +769,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } @@ -785,7 +785,7 @@ static inline void stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -799,7 +799,7 @@ stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, static inline void stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -812,7 +812,7 @@ stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -826,7 +826,7 @@ stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -840,7 +840,7 @@ stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -863,10 +863,10 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -1076,14 +1076,14 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) switch (frequency) { case 100000ul: @@ -1104,7 +1104,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #else -#if STM32WB_PCLK1_FREQUENCY != 64000000ul +#if STM32_PCLK1_FREQUENCY != 64000000ul # error Unsupported I2C configuration. #endif @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32WB_I2C_TIMINGR_OFFSET, timingr); + stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1279,7 +1279,7 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1300,7 +1300,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1315,7 +1315,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) static inline uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32WB_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1329,7 +1329,7 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1357,7 +1357,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1526,7 +1526,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32WB_I2C_TXDR_OFFSET, *priv->ptr); + stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32WB_I2C_RXDR_OFFSET); + *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1622,7 +1622,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Unsupported state */ stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1866,7 +1866,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -1889,7 +1889,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,7 +1954,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -1992,9 +1992,9 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable power and reset the peripheral */ - modifyreg32(STM32WB_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); /* Configure pins */ @@ -2030,7 +2030,7 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2047,7 +2047,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32WB_I2C_CR1_OFFSET, 0); + stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2066,7 +2066,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) /* Disable clocking */ - modifyreg32(STM32WB_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); return OK; } @@ -2146,8 +2146,8 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, waitrc = stm32wb_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2561,12 +2561,12 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c1_priv; break; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c3_priv; break; @@ -2651,4 +2651,4 @@ int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) kmm_free(dev); return OK; } -#endif /* CONFIG_STM32WB_I2C1 || CONFIG_STM32WB_I2C3 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index 3c9ea624557c7..8d64fa09b8d46 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_I2C_H +#define __ARCH_ARM_SRC_STM32WB_STM32_I2C_H /**************************************************************************** * Included Files @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -# if CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32WB_I2C_DYNTIMEO because of CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif @@ -88,4 +88,4 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port); int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_I2C_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 977ff2970939a..24f9513b0ba31 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); __asm__ volatile ("wfi"); END_IDLE(); diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index a9999bdcd12c2..795ec398c46a6 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -53,27 +53,27 @@ void stm32wb_ipccreset(void) /* Disable CPU1 IPCC interrupts */ - putreg32(0x00000000, STM32WB_IPCC_C1CR); + putreg32(0x00000000, STM32_IPCC_C1CR); /* Clear CPU1 IPCC receive channel status */ - putreg32(IPCC_C1SCR_CLR_MASK, STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_CLR_MASK, STM32_IPCC_C1SCR); /* Clear CPU2 IPCC receive channel status */ - putreg32(IPCC_C2SCR_CLR_MASK, STM32WB_IPCC_C2SCR); + putreg32(IPCC_C2SCR_CLR_MASK, STM32_IPCC_C2SCR); /* Disable CPU1 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C1MR); + regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_MASK | IPCC_C1MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); /* Disable CPU2 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C2MR); + regval = getreg32(STM32_IPCC_C2MR); regval |= IPCC_C2MR_OM_MASK | IPCC_C2MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C2MR); + putreg32(regval, STM32_IPCC_C2MR); } /**************************************************************************** @@ -90,21 +90,21 @@ void stm32wb_ipccenable(void) /* CPU2 IPCC clock enable */ - regval = getreg32(STM32WB_RCC_C2AHB3ENR); + regval = getreg32(STM32_RCC_C2AHB3ENR); regval |= RCC_C2AHB3ENR_IPCCEN; - putreg32(regval, STM32WB_RCC_C2AHB3ENR); + putreg32(regval, STM32_RCC_C2AHB3ENR); /* Enable EXTI event request for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_C2EMR2); + regval = getreg32(STM32_EXTI_C2EMR2); regval |= EXTI_C2EMR2_EM(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_C2EMR2); + putreg32(regval, STM32_EXTI_C2EMR2); /* Enable EXTI rising edge trigger for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_RTSR2); + regval = getreg32(STM32_EXTI_RTSR2); regval |= EXTI_RTSR2_RT(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_RTSR2); + putreg32(regval, STM32_EXTI_RTSR2); /* Set the internal event flag and send an event to CPU2 */ @@ -116,7 +116,7 @@ void stm32wb_ipccenable(void) /* Boot CPU2 after reset or wakeup from stop or standby modes */ - regval = getreg32(STM32WB_PWR_CR4); + regval = getreg32(STM32_PWR_CR4); regval |= PWR_CR4_C2BOOT; - putreg32(regval, STM32WB_PWR_CR4); + putreg32(regval, STM32_PWR_CR4); } diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index 1d8ae70afa55b..49a66ea347975 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H /**************************************************************************** * Included Files @@ -88,7 +88,7 @@ void stm32wb_ipccenable(void); static inline bool stm32wb_ipcc_rxactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** @@ -101,7 +101,7 @@ static inline bool stm32wb_ipcc_rxactive(uint8_t chan) static inline bool stm32wb_ipcc_txactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** @@ -114,7 +114,7 @@ static inline bool stm32wb_ipcc_txactive(uint8_t chan) static inline void stm32wb_ipcc_settxactive(uint8_t chan) { - putreg32(IPCC_C1SCR_SET_BIT(chan), STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** @@ -127,9 +127,9 @@ static inline void stm32wb_ipcc_settxactive(uint8_t chan) static inline void stm32wb_ipcc_masktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -142,9 +142,9 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -157,9 +157,9 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) static inline void stm32wb_ipcc_maskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -172,9 +172,9 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } #undef EXTERN @@ -183,4 +183,4 @@ static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index 9b06b2bd709a4..f87503a7802f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -203,13 +203,13 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WB_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WB_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -219,19 +219,19 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WB_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WB_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WB_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WB_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -261,7 +261,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WB_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -319,13 +319,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WB_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WB_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WB_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -335,23 +335,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WB_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WB_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WB_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WB_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WB_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WB_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WB_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); #endif stm32wb_dumpnvic("initial", NR_IRQS); @@ -387,7 +387,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -422,7 +422,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -465,10 +465,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WB_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WB_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -481,7 +481,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WB_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index 7d73b1afd13c3..c8807a1f5bfb5 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -45,51 +45,51 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_LPUART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK1_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB1ENR2 -# define STM32WB_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WB_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_USART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK2_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB2ENR -# define STM32WB_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_USART1_TX -# define STM32WB_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WB_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WB_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -97,9 +97,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WB_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WB_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -115,7 +115,7 @@ /* CR2 settings */ -# if STM32WB_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -157,19 +157,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WB_USARTDIV8 \ - (((STM32WB_APBCLOCK << 1) + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) -# define STM32WB_USARTDIV16 \ - ((STM32WB_APBCLOCK + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32WB_USARTDIV8 > 100 -# define STM32WB_BRR_VALUE STM32WB_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WB_BRR_VALUE \ - ((STM32WB_USARTDIV8 & 0xfff0) | ((STM32WB_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -211,22 +211,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WB_CONSOLE_BASE + STM32WB_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WB_CONSOLE_RS485_DIR - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -252,7 +252,7 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WB_CONSOLE_APBREG, 0, STM32WB_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -261,17 +261,17 @@ void stm32wb_lowsetup(void) * stm32wb_rcc.c */ -#ifdef STM32WB_CONSOLE_TX - stm32wb_configgpio(STM32WB_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wb_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WB_CONSOLE_RX - stm32wb_configgpio(STM32WB_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wb_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32WB_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -279,42 +279,42 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WB_BRR_VALUE, - STM32WB_CONSOLE_BASE + STM32WB_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.h b/arch/arm/src/stm32wb/stm32wb_lowputc.h index 8a8ca85b3386d..c05e6f430003b 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.h +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32wb_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 86c2e298c686b..a4062bcd78faf 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -44,12 +44,12 @@ * the beginning of SRAM2a. */ -#define STM32WB_MBOX_SHARED_BASE STM32WB_SRAM2A_BASE +#define STM32_MBOX_SHARED_BASE STM32_SRAM2A_BASE /* Mailbox shared buffer fields */ #define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32WB_MBOX_SHARED_BASE) + (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) #define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) #define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) @@ -59,12 +59,12 @@ /* Mailbox buffer sizes */ -#define STM32WB_MBOX_CS_BUF_SIZE 16 -#define STM32WB_MBOX_CMDPKT_BUF_SIZE 268 -#define STM32WB_MBOX_ACLPKT_BUF_SIZE 264 +#define STM32_MBOX_CS_BUF_SIZE 16 +#define STM32_MBOX_CMDPKT_BUF_SIZE 268 +#define STM32_MBOX_ACLPKT_BUF_SIZE 264 -#define STM32WB_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32WB_MBOX_CMDPKT_BUF_SIZE) +#define STM32_MBOX_RX_BUF_SIZE \ + (CONFIG_STM32_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -150,21 +150,21 @@ struct stm32wb_mbox_shared_buffer_s aligned_data(4) struct stm32wb_mbox_mem_manager_table_s mm_table; aligned_data(4) stm32wb_mbox_list_t evtfree_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) stm32wb_mbox_list_t ble_evt_queue; #endif aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; -#ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_cs_buffer[STM32WB_MBOX_CS_BUF_SIZE]; +#ifdef CONFIG_STM32_BLE + aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif - aligned_data(4) uint8_t evtpool_buffer[STM32WB_MBOX_RX_BUF_SIZE]; - aligned_data(4) uint8_t sys_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t sys_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; -#ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_acl_buffer[STM32WB_MBOX_ACLPKT_BUF_SIZE]; + aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; + aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; +#ifdef CONFIG_STM32_BLE + aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; #endif }; @@ -204,12 +204,12 @@ static struct work_s g_tx_cmd_work; static stm32wb_mbox_list_t g_rx_evt_queue; static stm32wb_mbox_list_t g_tx_evtfree_queue; -static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] - [STM32WB_MBOX_CMDPKT_BUF_SIZE]; +static uint8_t g_free_buffers[CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN] + [STM32_MBOX_CMDPKT_BUF_SIZE]; static stm32wb_mbox_list_t g_free_buffers_pool; static struct stm32wb_mbox_channel_s g_syscmd_channel; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE static struct stm32wb_mbox_channel_s g_blecmd_channel; static struct stm32wb_mbox_channel_s g_bleacl_channel; #endif @@ -235,24 +235,24 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_SYSEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_SYSEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_BLEEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_BLEEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); } #endif @@ -265,7 +265,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Clear active statuses */ - putreg32(clrmask, STM32WB_IPCC_C1SCR); + putreg32(clrmask, STM32_IPCC_C1SCR); } /**************************************************************************** @@ -279,7 +279,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { - uint32_t c1mr = getreg32(STM32WB_IPCC_C1MR); + uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; /* TXF interrupt can be triggered by not masked channels and active status @@ -287,12 +287,12 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) * channels and rise other C1MR bits to highlight needed channels. */ - txfsrc = ~(c1mr | (getreg32(STM32WB_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) + txfsrc = ~(c1mr | (getreg32(STM32_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) & IPCC_C1MR_FM_MASK; /* Check if the release channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all released events (if any) into transmission mailbox */ @@ -303,17 +303,17 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } /* Check other channels, except the release channel */ - if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Check if the system channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_SYSCMD_CHANNEL)) { /* System channel works in 'half-duplex' mode and acks * immediately on each command before TXF, so it needs @@ -333,7 +333,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Mask triggered channels */ - putreg32(c1mr | txfsrc, STM32WB_IPCC_C1MR); + putreg32(c1mr | txfsrc, STM32_IPCC_C1MR); } /**************************************************************************** @@ -350,7 +350,7 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ @@ -363,13 +363,13 @@ static void stm32wb_mbox_txworker(void *arg) handled = stm32wb_mbox_txnext(&g_syscmd_channel); } -#ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLECMD_CHANNEL)) +#ifdef CONFIG_STM32_BLE + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLEACL_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_bleacl_channel); } @@ -467,7 +467,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, stm32wb_ipcc_settxactive(chan->ch_num); if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || - chan->ch_num == STM32WB_MBOX_SYSCMD_CHANNEL) + chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get * notified when channel gets ready to process a next one. @@ -512,7 +512,7 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) { chan->cmd_buf->type = pkt_buf->type; - if (chan->ch_num == STM32WB_MBOX_BLEACL_CHANNEL) + if (chan->ch_num == STM32_MBOX_BLEACL_CHANNEL) { memcpy(&chan->cmd_buf->acl_hdr, &pkt_buf->acl_hdr, sizeof(pkt_buf->acl_hdr) + pkt_buf->acl_hdr.len); @@ -562,7 +562,7 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ @@ -571,13 +571,13 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Start transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); @@ -600,7 +600,7 @@ static void stm32wb_mbox_acksyscmd(void) */ evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); - evt->type = STM32WB_MBOX_SYSACK; + evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); } @@ -628,7 +628,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.sys_evt_queue); stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.evtfree_buffer); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.ble_evt_queue); #endif @@ -648,12 +648,12 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) .evtfree_buffer; stm32wb_mbox_mm_table.sys_spare_buffer = &stm32wb_mbox_shared .sys_spare_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32wb_mbox_mm_table.ble_spare_buffer = &stm32wb_mbox_shared .ble_spare_buffer; #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32wb_mbox_ble_table.cmd_buffer = &stm32wb_mbox_shared.ble_cmd_buffer; stm32wb_mbox_ble_table.acl_buffer = &stm32wb_mbox_shared.ble_acl_buffer; stm32wb_mbox_ble_table.cs_buffer = &stm32wb_mbox_shared.ble_cs_buffer; @@ -662,22 +662,22 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) /* Init system channel data */ - g_syscmd_channel.ch_num = STM32WB_MBOX_SYSCMD_CHANNEL; + g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.sys_cmd_buffer; stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Init BLE command channel data */ - g_blecmd_channel.ch_num = STM32WB_MBOX_BLECMD_CHANNEL; + g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_cmd_buffer; stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ - g_bleacl_channel.ch_num = STM32WB_MBOX_BLEACL_CHANNEL; + g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_acl_buffer; stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); @@ -689,7 +689,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) stm32wb_mbox_list_initialize(&g_tx_evtfree_queue); stm32wb_mbox_list_initialize(&g_free_buffers_pool); - for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) + for (i = 0; i < CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN; i++) { stm32wb_mbox_list_add_tail(&g_free_buffers_pool, (stm32wb_mbox_list_t *)g_free_buffers[i]); @@ -715,21 +715,21 @@ void stm32wb_mboxenable(void) /* Setup RXO and TXF interrupts */ - irq_attach(STM32WB_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCRX); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32WB_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCTX); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + up_enable_irq(STM32_IRQ_IPCCTX); - regval = getreg32(STM32WB_IPCC_C1CR); + regval = getreg32(STM32_IPCC_C1CR); regval |= IPCC_C1CR_RXOIE | IPCC_C1CR_TXFIE; - putreg32(regval, STM32WB_IPCC_C1CR); + putreg32(regval, STM32_IPCC_C1CR); /* Unmask system channel RXO interrupt. Once CPU2 started we expect * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_SYSEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ @@ -747,11 +747,11 @@ void stm32wb_mboxenable(void) int stm32wb_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32WB_MBOX_SYSCMD, + return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /**************************************************************************** * Name: stm32wb_mbox_blecmd * @@ -763,7 +763,7 @@ int stm32wb_mbox_syscmd(void *data, size_t len) int stm32wb_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32WB_MBOX_HCICMD, + return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } @@ -778,7 +778,7 @@ int stm32wb_mbox_blecmd(void *data, size_t len) int stm32wb_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32WB_MBOX_HCIACL, + return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } @@ -800,7 +800,7 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Prepare command data */ - cmd->opcode = STM32WB_SHCI_BLE_INIT; + cmd->opcode = STM32_SHCI_BLE_INIT; cmd->param_len = sizeof(*cmd); memcpy(cmd + 1, params, sizeof(*params)); @@ -810,6 +810,6 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_BLEEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } -#endif /* CONFIG_STM32WB_BLE */ +#endif /* CONFIG_STM32_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index f67821fa5c566..26a78c8f1b492 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H /**************************************************************************** * Included Files @@ -42,34 +42,34 @@ /* Mailbox channels */ -#define STM32WB_MBOX_BLEEVT_CHANNEL 1 -#define STM32WB_MBOX_BLECMD_CHANNEL 1 -#define STM32WB_MBOX_SYSEVT_CHANNEL 2 -#define STM32WB_MBOX_SYSCMD_CHANNEL 2 -#define STM32WB_MBOX_EVT_RELEASE_CHANNEL 4 -#define STM32WB_MBOX_BLEACL_CHANNEL 6 +#define STM32_MBOX_BLEEVT_CHANNEL 1 +#define STM32_MBOX_BLECMD_CHANNEL 1 +#define STM32_MBOX_SYSEVT_CHANNEL 2 +#define STM32_MBOX_SYSCMD_CHANNEL 2 +#define STM32_MBOX_EVT_RELEASE_CHANNEL 4 +#define STM32_MBOX_BLEACL_CHANNEL 6 /* Mailbox packet types */ -#define STM32WB_MBOX_HCICMD 0x01 -#define STM32WB_MBOX_HCIACL 0x02 -#define STM32WB_MBOX_HCIEVT 0x04 -#define STM32WB_MBOX_SYSCMD 0x10 -#define STM32WB_MBOX_SYSEVT 0x12 -#define STM32WB_MBOX_SYSACK 0xe0 +#define STM32_MBOX_HCICMD 0x01 +#define STM32_MBOX_HCIACL 0x02 +#define STM32_MBOX_HCIEVT 0x04 +#define STM32_MBOX_SYSCMD 0x10 +#define STM32_MBOX_SYSEVT 0x12 +#define STM32_MBOX_SYSACK 0xe0 /* Mailbox configuration helpers */ -#define STM32WB_MBOX_BLE_ATT_DEFAULT_MTU 23 -#define STM32WB_MBOX_C2_MEM_BLOCK_SZ 32 +#define STM32_MBOX_BLE_ATT_DEFAULT_MTU 23 +#define STM32_MBOX_C2_MEM_BLOCK_SZ 32 #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) -#define STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ - (DIV_UP((max_mtu), STM32WB_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) +#define STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ + (DIV_UP((max_mtu), STM32_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) -#define STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ - ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32WB_MBOX_C2_MEM_BLOCK_SZ) + 2)) +#define STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ + ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32_MBOX_C2_MEM_BLOCK_SZ) + 2)) /**************************************************************************** * Public Types @@ -173,4 +173,4 @@ int stm32wb_mbox_bleacl(void *data, size_t len); void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_list.h b/arch/arm/src/stm32wb/stm32wb_mbox_list.h index 4208da7fbec04..f8bd643db4d85 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_list.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_list.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H /**************************************************************************** * Included Files @@ -143,4 +143,4 @@ static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, } } -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_LIST_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_LIST_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 68536c3cfcb96..4687fadbc63c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H /**************************************************************************** * Included Files @@ -37,87 +37,87 @@ /* SHCI event types *********************************************************/ -#define STM32WB_SHCI_ASYNC_EVT 0xff +#define STM32_SHCI_ASYNC_EVT 0xff /* SHCI async event subtypes */ -#define STM32WB_SHCI_ASYNC_EVT_C2RDY 0x9200 +#define STM32_SHCI_ASYNC_EVT_C2RDY 0x9200 /* SHCI system command acknowledgement events */ -#define STM32WB_SHCI_ACK_EVT_C2RDY 0x05 +#define STM32_SHCI_ACK_EVT_C2RDY 0x05 /* SHCI command opcodes *****************************************************/ -#define STM32WB_SHCI_OGF 0x3f -#define STM32WB_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) - -#define STM32WB_SHCI_FUS_GET_STATE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x52) -#define STM32WB_SHCI_FUS_FW_UPGRADE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x54) -#define STM32WB_SHCI_FUS_FW_DELETE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x55) -#define STM32WB_SHCI_FUS_UPDATE_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x56) -#define STM32WB_SHCI_FUS_LOCK_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x57) -#define STM32WB_SHCI_FUS_STORE_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x58) -#define STM32WB_SHCI_FUS_LOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x59) -#define STM32WB_SHCI_FUS_START_WS STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5a) -#define STM32WB_SHCI_FUS_LOCK_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5d) -#define STM32WB_SHCI_FUS_UNLOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5e) -#define STM32WB_SHCI_FUS_ANTIROLLBACK STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5f) -#define STM32WB_SHCI_BLE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x66) -#define STM32WB_SHCI_THREAD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x67) -#define STM32WB_SHCI_DEBUG_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x68) -#define STM32WB_SHCI_FLASH_ERASE_ACTIVITY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x69) -#define STM32WB_SHCI_CONCURRENT_SET_MODE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6a) -#define STM32WB_SHCI_FLASH_STORE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6b) -#define STM32WB_SHCI_FLASH_ERASE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6c) -#define STM32WB_SHCI_RADIO_ALLOW_LOW_POWER STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6d) -#define STM32WB_SHCI_MAC_802154_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6e) -#define STM32WB_SHCI_REINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6f) -#define STM32WB_SHCI_ZIGBEE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x70) -#define STM32WB_SHCI_LLD_TESTS_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x71) -#define STM32WB_SHCI_EXTPA_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x72) -#define STM32WB_SHCI_SET_FLASH_CONTROL STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x73) -#define STM32WB_SHCI_BLE_LLD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x74) -#define STM32WB_SHCI_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x75) -#define STM32WB_SHCI_GET_NEXT_BLE_EVT_TIME STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x76) -#define STM32WB_SHCI_ENABLE_NEXT_802154_NF STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x77) -#define STM32WB_SHCI_802_15_4_DEINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x78) +#define STM32_SHCI_OGF 0x3f +#define STM32_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) + +#define STM32_SHCI_FUS_GET_STATE STM32_SHCI_OP(STM32_SHCI_OGF, 0x52) +#define STM32_SHCI_FUS_FW_UPGRADE STM32_SHCI_OP(STM32_SHCI_OGF, 0x54) +#define STM32_SHCI_FUS_FW_DELETE STM32_SHCI_OP(STM32_SHCI_OGF, 0x55) +#define STM32_SHCI_FUS_UPDATE_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x56) +#define STM32_SHCI_FUS_LOCK_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x57) +#define STM32_SHCI_FUS_STORE_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x58) +#define STM32_SHCI_FUS_LOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x59) +#define STM32_SHCI_FUS_START_WS STM32_SHCI_OP(STM32_SHCI_OGF, 0x5a) +#define STM32_SHCI_FUS_LOCK_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5d) +#define STM32_SHCI_FUS_UNLOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5e) +#define STM32_SHCI_FUS_ANTIROLLBACK STM32_SHCI_OP(STM32_SHCI_OGF, 0x5f) +#define STM32_SHCI_BLE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x66) +#define STM32_SHCI_THREAD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x67) +#define STM32_SHCI_DEBUG_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x68) +#define STM32_SHCI_FLASH_ERASE_ACTIVITY STM32_SHCI_OP(STM32_SHCI_OGF, 0x69) +#define STM32_SHCI_CONCURRENT_SET_MODE STM32_SHCI_OP(STM32_SHCI_OGF, 0x6a) +#define STM32_SHCI_FLASH_STORE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6b) +#define STM32_SHCI_FLASH_ERASE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6c) +#define STM32_SHCI_RADIO_ALLOW_LOW_POWER STM32_SHCI_OP(STM32_SHCI_OGF, 0x6d) +#define STM32_SHCI_MAC_802154_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6e) +#define STM32_SHCI_REINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6f) +#define STM32_SHCI_ZIGBEE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x70) +#define STM32_SHCI_LLD_TESTS_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x71) +#define STM32_SHCI_EXTPA_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x72) +#define STM32_SHCI_SET_FLASH_CONTROL STM32_SHCI_OP(STM32_SHCI_OGF, 0x73) +#define STM32_SHCI_BLE_LLD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x74) +#define STM32_SHCI_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x75) +#define STM32_SHCI_GET_NEXT_BLE_EVT_TIME STM32_SHCI_OP(STM32_SHCI_OGF, 0x76) +#define STM32_SHCI_ENABLE_NEXT_802154_NF STM32_SHCI_OP(STM32_SHCI_OGF, 0x77) +#define STM32_SHCI_802_15_4_DEINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x78) /* Command params bitfield definitions **************************************/ /* BLE init command option flags */ -#define STM32WB_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ +#define STM32_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ -#define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ +#define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ +#define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ -#define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ +#define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ +#define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ /* BLE init command rx_model_config flags */ -#define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ +#define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ /**************************************************************************** * Public Types ****************************************************************************/ -/* STM32WB_SHCI_BLE_INIT command params */ +/* STM32_SHCI_BLE_INIT command params */ begin_packed_struct struct stm32wb_shci_ble_init_cfg_s { @@ -185,4 +185,4 @@ begin_packed_struct struct stm32wb_shci_ble_init_cfg_s uint8_t rx_model_config; /* RX model config flags */ } end_packed_struct; -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_SHCI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_SHCI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.h b/arch/arm/src/stm32wb/stm32wb_mpuinit.h index 1cc8d755c37aa..ae64e386983d1 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.h +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32wb_mpu_uheap(uintptr_t start, size_t size); # define stm32wb_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index ed0d899531cf0..f798cf7ddae73 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -39,7 +39,7 @@ #include "stm32wb_oneshot.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -86,10 +86,10 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); /* The timer is no longer running */ @@ -117,19 +117,19 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32WB_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) { -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32WB_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -200,7 +200,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, return -EBUSY; } - STM32WB_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -301,19 +301,19 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32WB_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32WB_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -388,14 +388,14 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32WB_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; @@ -456,4 +456,4 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 37d45ac8ed204..097b66c738e09 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H /**************************************************************************** * Included Files @@ -36,22 +36,22 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32WB_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32WB_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32wb_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -194,5 +194,5 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32WB_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ +#endif /* CONFIG_STM32_ONESHOT */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_pm.h b/arch/arm/src/stm32wb/stm32wb_pm.h index 3876288bc1a26..a984512594706 100644 --- a/arch/arm/src/stm32wb/stm32wb_pm.h +++ b/arch/arm/src/stm32wb/stm32wb_pm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_PM_H +#define __ARCH_ARM_SRC_STM32WB_STM32_PM_H /**************************************************************************** * Included Files @@ -148,4 +148,4 @@ int stm32wb_pmlpr(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_PM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_PM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index c81179f8c62b8..fa601b27961bb 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -60,34 +60,34 @@ int stm32wb_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index d1fd88ac03c50..657f4bf677926 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -63,15 +63,15 @@ int stm32wb_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32WB_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 683af0cd07a24..1cbd80f0e23b4 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -98,7 +98,7 @@ int stm32wb_pmstop(bool lpds) * register CR1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -108,7 +108,7 @@ int stm32wb_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -135,10 +135,10 @@ int stm32wb_pmstop2(void) /* Select Stop 2 mode in power control register 1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index c13ca0b14803a..62fe1b7be840b 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -41,18 +41,18 @@ static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WB_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WB_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WB_PWR_BASE + (uint32_t)offset, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -82,7 +82,7 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR1_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -132,7 +132,7 @@ bool stm32wb_pwr_enableusv(bool set) /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR2_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; @@ -183,7 +183,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -195,5 +195,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.h b/arch/arm/src/stm32wb/stm32wb_pwr.h index e9dea014de0de..26c5c3d57614d 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/stm32wb_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WB_STM32_PWR_H /**************************************************************************** * Included Files @@ -115,4 +115,4 @@ void stm32_pwr_setvos(int vos); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 9fd6f17b2a4b2..74c8e67fa0401 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,9 +61,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32WB_USE_CLK48) -# if STM32WB_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32WB_USE_HSI48 +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -89,47 +89,47 @@ static inline void rcc_reset(void) /* Enable the Multi-Speed Internal clock (MSI) @ 4MHz */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSION; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= RCC_CFGR_RESET_MASK; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_MSIPLLEN); - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset LSI1 and LSI2 bits */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~(RCC_CSR_LSI1ON | RCC_CSR_LSI2ON); - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); /* Reset HSI48ON bit */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~(RCC_CRRCR_HSI48ON); - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Reset PLLCFGR register */ - putreg32(RCC_PLLCFG_RESET, STM32WB_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset PLLSAI1CFG register */ - putreg32(RCC_PLLSAI1CFG_RESET, STM32WB_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_RESET, STM32_RCC_PLLSAI1CFG); /* Disable all interrupts */ - putreg32(0x00000000, STM32WB_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -148,39 +148,39 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WB_DMAMUX +#ifdef CONFIG_STM32_DMAMUX /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32WB_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32WB_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32WB_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -199,32 +199,32 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIO ports A-E, H */ regval |= (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) | RCC_AHB2ENR_GPIODEN #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) | RCC_AHB2ENR_GPIOEEN #endif | RCC_AHB2ENR_GPIOHEN); -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32WB_AES1 +#ifdef CONFIG_STM32_AES1 /* AES1 cryptographic accelerator clock enable */ regval |= RCC_AHB2ENR_AES1EN; #endif - putreg32(regval, STM32WB_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -243,51 +243,51 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WB_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif -#ifdef CONFIG_STM32WB_PKA +#ifdef CONFIG_STM32_PKA /* Public key accelerator clock enable */ regval |= RCC_AHB3ENR_PKAEN; #endif -#ifdef CONFIG_STM32WB_AES2 +#ifdef CONFIG_STM32_AES2 /* AES2 cryptographic accelerator clock enable */ regval |= RCC_AHB3ENR_AES2EN; #endif -#ifdef CONFIG_STM32WB_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB3ENR_RNGEN; #endif -#ifdef CONFIG_STM32WB_HSEM +#ifdef CONFIG_STM32_HSEM /* Hardware semaphore clock enable */ regval |= RCC_AHB3ENR_HSEMEN; #endif -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC /* Inter-processor communication controller clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif -#ifdef CONFIG_STM32WB_FLASH +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; #endif - putreg32(regval, STM32WB_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,52 +306,52 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WB_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WB_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#if defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_RTC) /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#if defined(CONFIG_STM32WB_WWDG) +#if defined(CONFIG_STM32_WWDG) /* Window watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32WB_USE_HSI48 - if (STM32WB_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -359,37 +359,37 @@ static inline void rcc_enableapb1(void) } #endif -#if defined(CONFIG_STM32WB_USB) +#if defined(CONFIG_STM32_USB) /* USB clock enable */ regval |= RCC_APB1ENR1_USBEN; #endif -#ifdef CONFIG_STM32WB_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WB_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WB_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WB_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -408,45 +408,45 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WB_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WB_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32WB_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif - putreg32(regval, STM32WB_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -466,26 +466,26 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WB_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WB_I2C_USE_HSI16) -#ifdef CONFIG_STM32WB_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI16; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI16; #endif -#endif /* STM32WB_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WB_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WB_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ @@ -493,14 +493,14 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_CLK48SEL_HSI48; #endif -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32WB_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -513,18 +513,18 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32wb_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; -#if defined(STM32WB_BOARD_USEHSI) || defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -532,7 +532,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -541,17 +541,17 @@ static void stm32wb_stdclockconfig(void) } #endif -#if defined(STM32WB_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -563,10 +563,10 @@ static void stm32wb_stdclockconfig(void) /* Setting MSIRANGE */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32WB_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WB_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -574,7 +574,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -582,12 +582,12 @@ static void stm32wb_stdclockconfig(void) } } -#elif defined(STM32WB_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -595,7 +595,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32WB_BOARD_USEHSI, STM32WB_BOARD_USEMSI, STM32WB_BOARD_USEHSE defined +# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -617,144 +617,144 @@ static void stm32wb_stdclockconfig(void) { /* Setup regulator voltage according to clock frequency */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; -#if STM32WB_SYSCLK_FREQUENCY > 16000000 || \ +#if STM32_SYSCLK_FREQUENCY > 16000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 16000000) regval |= PWR_CR1_VOS_RANGE1; #else regval |= PWR_CR1_VOS_RANGE2; #endif - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WB_RCC_CFGR_HPRE; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the CPU2 HCLK2 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_C2HPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_C2HPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_C2HPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the HCLK4 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_SHDHPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_SHDHPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_SHDHPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WB_RCC_CFGR_PPRE1; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WB_RCC_CFGR_PPRE2; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Configure Main PLL */ - regval = getreg32(STM32WB_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); regval &= ~(RCC_PLLCFG_PLLM_MASK | RCC_PLLCFG_PLLN_MASK); - regval |= (STM32WB_PLLCFG_PLLM | STM32WB_PLLCFG_PLLN); + regval |= (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN); /* Set the PLL dividers and multipliers to configure the main PLL */ regval &= ~(RCC_PLLCFG_PLLPEN | RCC_PLLCFG_PLLQEN | RCC_PLLCFG_PLLREN); -#ifdef STM32WB_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval &= ~RCC_PLLCFG_PLLP_MASK; - regval |= (RCC_PLLCFG_PLLPEN | STM32WB_PLLCFG_PLLP); + regval |= (RCC_PLLCFG_PLLPEN | STM32_PLLCFG_PLLP); #endif -#ifdef STM32WB_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval &= ~RCC_PLLCFG_PLLQ_MASK; - regval |= (RCC_PLLCFG_PLLQEN | STM32WB_PLLCFG_PLLQ); + regval |= (RCC_PLLCFG_PLLQEN | STM32_PLLCFG_PLLQ); #endif -#ifdef STM32WB_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval &= ~RCC_PLLCFG_PLLR_MASK; - regval |= (RCC_PLLCFG_PLLREN | STM32WB_PLLCFG_PLLR); + regval |= (RCC_PLLCFG_PLLREN | STM32_PLLCFG_PLLR); #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WB_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval &= ~RCC_PLLCFG_PLLSRC_MASK; -#ifdef STM32WB_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WB_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WB_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } -#ifdef CONFIG_STM32WB_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32WB_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); regval &= ~RCC_PLLSAI1CFG_PLLN_MASK; - regval |= STM32WB_PLLSAI1CFG_PLLN; + regval |= STM32_PLLSAI1CFG_PLLN; /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ regval &= ~(RCC_PLLSAI1CFG_PLLPEN | RCC_PLLSAI1CFG_PLLQEN | RCC_PLLSAI1CFG_PLLREN); -#ifdef STM32WB_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLP_MASK; - regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32WB_PLLSAI1CFG_PLLP); + regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32_PLLSAI1CFG_PLLP); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLQ_MASK; - regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32WB_PLLSAI1CFG_PLLQ); + regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32_PLLSAI1CFG_PLLQ); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLR_MASK; - regval |= (RCC_PLLSAI1CFG_PLLREN | STM32WB_PLLSAI1CFG_PLLR); + regval |= (RCC_PLLSAI1CFG_PLLREN | STM32_PLLSAI1CFG_PLLR); #endif - putreg32(regval, STM32WB_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif /* Configure FLASH wait states */ - regval = getreg32(STM32WB_FLASH_ACR); + regval = getreg32(STM32_FLASH_ACR); regval &= ~FLASH_ACR_LATENCY_MASK; #ifdef BOARD_FLASH_WAITSTATES regval |= FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); @@ -764,35 +764,35 @@ static void stm32wb_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32WB_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= FLASH_ACR_PRFTEN; #else regval &= ~FLASH_ACR_PRFTEN; #endif regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); - putreg32(regval, STM32WB_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32wb_rcc_enable_lsi(); #endif -#if defined(STM32WB_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -807,25 +807,25 @@ static void stm32wb_stdclockconfig(void) stm32wb_rcc_enable_lse(); -# if defined(STM32WB_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32WB_USE_LSE */ +#endif /* STM32_USE_LSE */ /* Select CPU2 RF wakeup clock source, no clock if not set */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~RCC_CSR_RFWKPSEL_MASK; -#if defined(STM32WB_BOARD_RFWKP_USELSE) +#if defined(STM32_BOARD_RFWKP_USELSE) regval |= RCC_CSR_RFWKPSEL_LSE; -#elif defined(STM32WB_BOARD_RFWKP_USEHSE) +#elif defined(STM32_BOARD_RFWKP_USEHSE) regval |= RCC_CSR_RFWKPSEL_HSE; #endif - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); } } #endif @@ -843,10 +843,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32WB_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32WB_HSI48_SYNCSRC); + stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -871,7 +871,7 @@ static inline void rcc_enableperipherals(void) * ****************************************************************************/ -#if defined(CONFIG_STM32WB_PWR) && defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -881,14 +881,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32wb_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WB_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WB_RTC_BKPR(i)); + bkregs[i] = getreg32(STM32_RTC_BKPR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -901,16 +901,16 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG != STM32WB_RTC_BKPR(i)) + if (RTC_MAGIC_REG != STM32_RTC_BKPR(i)) { - putreg32(bkregs[i], STM32WB_RTC_BKPR(i)); + putreg32(bkregs[i], STM32_RTC_BKPR(i)); } } @@ -930,7 +930,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wb_board_clockconfig(). * @@ -952,7 +952,7 @@ void stm32wb_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -987,7 +987,7 @@ void stm32wb_clockconfig(void) * stm32wb_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wb_board_clockconfig(). * @@ -1002,7 +1002,7 @@ void stm32wb_clockconfig(void) #ifdef CONFIG_PM void stm32wb_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index c770e462bd143..d82d0ffbf5bc0 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_RCC_H /**************************************************************************** * Included Files @@ -88,7 +88,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); /* Set MCO source */ @@ -99,7 +99,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) regval &= ~(RCC_CFGR_MCOPRE_MASK); regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -115,7 +115,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wb_board_clockconfig(). * @@ -138,7 +138,7 @@ void stm32wb_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32wb_board_clockconfig(void); #endif @@ -156,7 +156,7 @@ void stm32wb_board_clockconfig(void); * stm32wb_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wb_board_clockconfig(). * @@ -258,4 +258,4 @@ void stm32wb_rcc_disable_hsi48(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index e8d12b2d35282..abdb78b4b4430 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -77,13 +77,13 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * enabled. */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32WB_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -97,7 +97,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) break; } - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -124,9 +124,9 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -149,18 +149,18 @@ void stm32wb_rcc_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; regval |= CRS_CFGR_SYNCSRC_USBSOF; - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 4927de6dec4cd..7bc64fec90591 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -35,16 +35,16 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -68,7 +68,7 @@ void stm32wb_rcc_enable_lse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32WB_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -86,37 +86,37 @@ void stm32wb_rcc_enable_lse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32WB_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32wb_waste(); } -#if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32WB only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 32597118fbfd8..9fa23cfc73a8e 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -47,11 +47,11 @@ void stm32wb_rcc_enable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, 0, RCC_CSR_LSI1ON); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WB_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); } /**************************************************************************** @@ -68,7 +68,7 @@ void stm32wb_rcc_disable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, RCC_CSR_LSI1ON, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index f33974fdb4e94..11f9261e1847f 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -43,7 +43,7 @@ #include "stm32wb_rtc.h" #include "stm32wb_exti.h" -#ifdef CONFIG_STM32WB_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -64,8 +64,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32WB_PWR -# error "CONFIG_STM32WB_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -139,23 +139,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32WB_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBSSR)); - rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_OR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32_RTC_OR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -211,8 +211,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(RTC_WPR_KEY1, STM32WB_RTC_WPR); - putreg32(RTC_WPR_KEY2, STM32WB_RTC_WPR); + putreg32(RTC_WPR_KEY1, STM32_RTC_WPR); + putreg32(RTC_WPR_KEY2, STM32_RTC_WPR); } /**************************************************************************** @@ -233,7 +233,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32WB_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -263,16 +263,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -307,21 +307,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32WB_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -351,9 +351,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -425,13 +425,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); #endif } @@ -469,10 +469,10 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -491,17 +491,17 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -520,9 +520,9 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -565,7 +565,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -591,7 +591,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -630,12 +630,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -647,13 +647,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32WB_RTC_ALRMAR); - putreg32(0, STM32WB_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -673,12 +673,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -690,13 +690,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32WB_RTC_ALRMBR); - putreg32(0, STM32WB_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -860,14 +860,14 @@ int up_rtc_initialize(void) stm32wb_pwr_enablebkp(true); -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#if defined(CONFIG_STM32_RTC_HSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSICLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, +#elif defined(CONFIG_STM32_RTC_LSECLOCK) + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -875,7 +875,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -903,13 +903,13 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32WB_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -921,21 +921,21 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) + STM32_RTC_PRER); +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); -#else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ + STM32_RTC_PRER); +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1012,7 +1012,7 @@ int up_rtc_initialize(void) int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1029,18 +1029,18 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32WB_RTC_DR); - tr = getreg32(STM32WB_RTC_TR); -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32WB_RTC_SSR); - tmp = getreg32(STM32WB_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32WB_RTC_DR); + tmp = getreg32(STM32_RTC_DR); } while (tmp != dr); @@ -1089,13 +1089,13 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32WB_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1169,8 +1169,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32WB_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1242,8 +1242,8 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32WB_RTC_TR); - putreg32(dr, STM32WB_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1439,7 +1439,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1449,8 +1449,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMAR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1470,7 +1470,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1480,8 +1480,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMBR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1528,7 +1528,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32WB_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1537,7 +1537,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32WB_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1574,9 +1574,9 @@ static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) stm32wb_pwr_enablebkp(true); - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32wb_pwr_enablebkp(false); @@ -1622,10 +1622,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1655,13 +1655,13 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32WB_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1699,9 +1699,9 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1710,7 +1710,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1734,7 +1734,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32WB_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1755,17 +1755,17 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32WB_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1797,9 +1797,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1808,7 +1808,7 @@ int stm32wb_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1820,9 +1820,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32WB_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32WB_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); @@ -1830,4 +1830,4 @@ int stm32wb_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32WB_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 6868b14ddcf15..016bed990f953 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -24,8 +24,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32WB_STM32_RTC_H #include #include @@ -38,26 +38,26 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ -#if !defined(CONFIG_STM32WB_RTC_MAGIC) -# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32WB_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_REG) -# define CONFIG_STM32WB_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -158,7 +158,7 @@ bool stm32wb_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif @@ -314,4 +314,4 @@ struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_RTC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 009ead5cea0c2..16fc6ea85587c 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32WB_NALARMS]; + struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index e657d7435de58..9c548fb474f19 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -87,11 +87,11 @@ * The buffer size should be an even multiple of ARMV7M_DCACHE_LINESIZE. */ -# if !defined(CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -123,8 +123,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WB_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WB_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -141,7 +141,7 @@ * See stm32wb_serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -335,7 +335,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -343,7 +343,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -353,7 +353,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32wb_serial_s g_lpuart1priv = { .dev = @@ -379,13 +379,13 @@ static struct stm32wb_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WB_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WB_PCLK1_FREQUENCY, - .usartbase = STM32WB_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -415,7 +415,7 @@ static struct stm32wb_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32wb_serial_s g_usart1priv = { .dev = @@ -441,13 +441,13 @@ static struct stm32wb_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WB_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WB_PCLK2_FREQUENCY, - .usartbase = STM32WB_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -478,12 +478,12 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wb_serial_s * -const g_uart_devs[STM32WB_NLPUART + STM32WB_NUSART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif }; @@ -542,15 +542,15 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32WB_USART_BRR_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,8 +713,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -727,7 +727,7 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) { uint32_t brr; @@ -750,7 +750,7 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -771,8 +771,8 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32WB_LPUART1_BASE) +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + if (priv->usartbase == STM32_LPUART1_BASE) { stm32wb_serial_setbaud_lpuart(priv); } @@ -784,7 +784,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,14 +834,14 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -855,7 +855,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -900,7 +900,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1008,7 +1008,7 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -1044,16 +1044,16 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - case STM32WB_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WB_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER - case STM32WB_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WB_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif } @@ -1118,7 +1118,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WB_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,26 +1150,26 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1177,9 +1177,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1231,7 +1231,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1242,7 +1242,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1315,9 +1315,9 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1463,8 +1463,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WB_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WB_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1608,7 +1608,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1667,17 +1667,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WB_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,17 +1718,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WB_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1865,8 +1865,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WB_USART_BREAKS -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1970,7 +1970,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32WB_USART_RDR_OFFSET); + rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2058,7 +2058,7 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2093,7 +2093,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2219,7 +2219,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2230,7 +2230,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2396,7 +2396,7 @@ static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_TDR_OFFSET, (uint32_t)ch); + stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2444,7 +2444,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2482,7 +2482,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wb_serial_txready(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2655,7 +2655,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -2723,7 +2723,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2767,7 +2767,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2787,7 +2787,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -2796,7 +2796,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 7666a72f780c0..957840238ac9a 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -80,7 +80,7 @@ #include -#if defined(CONFIG_STM32WB_SPI1) || defined(CONFIG_STM32WB_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WB_SPI_INTERRUPTS) && defined(CONFIG_STM32WB_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -136,10 +136,10 @@ struct stm32wb_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -183,7 +183,7 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32wb_spidev_s *priv); static int spi_dmatxwait(struct stm32wb_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv); @@ -243,7 +243,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -281,12 +281,12 @@ static struct stm32wb_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32WB_SPI1_BASE, - .spiclock = STM32WB_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMAMAP_SPI1_RX, @@ -301,7 +301,7 @@ static struct stm32wb_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -339,12 +339,12 @@ static struct stm32wb_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32WB_SPI2_BASE, - .spiclock = STM32WB_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI2, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -462,11 +462,11 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -487,11 +487,11 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -514,11 +514,11 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32WB_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -541,11 +541,11 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32WB_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -575,7 +575,7 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32wb_spidev_s *priv) { int ret; @@ -608,7 +608,7 @@ static int spi_dmarxwait(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32wb_spidev_s *priv) { int ret; @@ -641,7 +641,7 @@ static int spi_dmatxwait(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -656,7 +656,7 @@ static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -671,7 +671,7 @@ static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; @@ -691,7 +691,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; @@ -711,7 +711,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -761,7 +761,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -812,7 +812,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) { priv->rxresult = 0; @@ -828,7 +828,7 @@ static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) { priv->txresult = 0; @@ -922,11 +922,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32WB_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32WB_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32WB_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -992,9 +992,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) actual = priv->spiclock >> 8; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1064,9 +1064,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1130,9 +1130,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1184,9 +1184,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1252,7 +1252,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32WB_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1290,8 +1290,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WB_SPI_DMA) || defined(CONFIG_STM32WB_DMACAPABLE) -#if !defined(CONFIG_STM32WB_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1374,7 +1374,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WB_SPI_DMA || CONFIG_STM32WB_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1397,14 +1397,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && !stm32wb_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && @@ -1466,7 +1466,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WB_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1487,7 +1487,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1670,11 +1670,11 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1686,9 +1686,9 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WB_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32wb_dmachannel() * will block and wait until the channel becomes available. WARNING: If @@ -1701,13 +1701,13 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) priv->txdma = stm32wb_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -1742,7 +1742,7 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1767,7 +1767,7 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1800,4 +1800,4 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WB_SPI1 || CONFIG_STM32WB_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index f7998c56b6e12..1f5d0ae1ee80e 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WB_STM32_SPI_H /**************************************************************************** * Included Files @@ -104,14 +104,14 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32wb_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32wb_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32wb_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid); @@ -139,12 +139,12 @@ int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32wb_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif @@ -156,4 +156,4 @@ int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 7ecd128a5c9d0..da2252328c9bf 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -63,14 +63,14 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2B_HEAP +# define SRAM2B_START STM32_SRAM2B_BASE +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* g_idle_topstack: _sbss is the start of the BSS region as defined by the @@ -148,14 +148,14 @@ void __start(void) * using this memory for, say, additional heap space, then this is handy. */ -#ifdef CONFIG_STM32WB_SRAM2A_INIT +#ifdef CONFIG_STM32_SRAM2A_INIT for (dest = (uint32_t *)SRAM2A_START; dest < (uint32_t *)SRAM2A_END; ) { *dest++ = 0; } #endif -#ifdef CONFIG_STM32WB_SRAM2B_INIT +#ifdef CONFIG_STM32_SRAM2B_INIT for (dest = (uint32_t *)SRAM2B_START; dest < (uint32_t *)SRAM2B_END; ) { *dest++ = 0; @@ -165,7 +165,7 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ stm32wb_clockconfig(); -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC stm32wb_ipccreset(); #endif arm_fpuconfig(); diff --git a/arch/arm/src/stm32wb/stm32wb_start.h b/arch/arm/src/stm32wb/stm32wb_start.h index e59d2843c56fd..6c4b5757c87fe 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.h +++ b/arch/arm/src/stm32wb/stm32wb_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_START_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_START_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_START_H +#define __ARCH_ARM_SRC_STM32WB_STM32_START_H /**************************************************************************** * Included Files @@ -44,4 +44,4 @@ void stm32wb_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_START_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_START_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index ef5e64b5f60da..4ef185247524c 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -84,12 +84,12 @@ #undef HAVE_32BIT_TICKLESS -#ifdef CONFIG_STM32WB_TICKLESS_TIMER -# if CONFIG_STM32WB_TICKLESS_TIMER == 2 +#ifdef CONFIG_STM32_TICKLESS_TIMER +# if CONFIG_STM32_TICKLESS_TIMER == 2 # define HAVE_32BIT_TICKLESS 1 # endif #else -# error "STM32WB_TICKLESS_TIMER must be defined for tickless configuration" +# error "STM32_TICKLESS_TIMER must be defined for tickless configuration" #endif /**************************************************************************** @@ -166,7 +166,7 @@ static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, static inline void stm32wb_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 0, 1 << channel); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** @@ -175,7 +175,7 @@ static inline void stm32wb_tickless_enableint(int channel) static inline void stm32wb_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 1 << channel, 0); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** @@ -184,7 +184,7 @@ static inline void stm32wb_tickless_disableint(int channel) static inline void stm32wb_tickless_ackint(int channel) { - stm32wb_putreg16(STM32WB_TIM_SR_OFFSET, ~(1 << channel)); + stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** @@ -193,7 +193,7 @@ static inline void stm32wb_tickless_ackint(int channel) static inline uint16_t stm32wb_tickless_getint(void) { - return stm32wb_getreg16(STM32WB_TIM_SR_OFFSET); + return stm32wb_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** @@ -205,7 +205,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; /* Further we use range as 0..3; if channel=0 it will also overflow here */ @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -231,14 +231,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } @@ -294,7 +294,7 @@ static void stm32wb_timing_handler(void) { g_tickless.overflow++; - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** @@ -360,29 +360,29 @@ static int stm32wb_tickless_handler(int irq, void *context, void *arg) void up_timer_initialize(void) { - switch (CONFIG_STM32WB_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: - g_tickless.base = STM32WB_TIM1_BASE; + g_tickless.base = STM32_TIM1_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: - g_tickless.base = STM32WB_TIM2_BASE; + g_tickless.base = STM32_TIM2_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: - g_tickless.base = STM32WB_TIM16_BASE; + g_tickless.base = STM32_TIM16_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: - g_tickless.base = STM32WB_TIM17_BASE; + g_tickless.base = STM32_TIM17_BASE; break; #endif @@ -393,8 +393,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32WB_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32WB_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -409,15 +409,15 @@ void up_timer_initialize(void) DEBUGPANIC(); } - STM32WB_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); + STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); /* Initialize interval to zero */ - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); /* Setup compare channel for the interval timing */ @@ -426,12 +426,12 @@ void up_timer_initialize(void) /* Set timer period */ #ifdef HAVE_32BIT_TICKLESS - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT32_MAX; #endif #else - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT16_MAX; #endif @@ -439,12 +439,12 @@ void up_timer_initialize(void) /* Initialize the counter */ - STM32WB_TIM_SETMODE(g_tickless.tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); /* Start the timer */ - STM32WB_TIM_ACKINT(g_tickless.tch, ~0); - STM32WB_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(g_tickless.tch, ~0); + STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); } /**************************************************************************** @@ -501,9 +501,9 @@ int up_timer_gettime(struct timespec *ts) flags = enter_critical_section(); overflow = g_tickless.overflow; - counter = STM32WB_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32WB_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); - verify = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + counter = STM32_TIM_GETCOUNTER(g_tickless.tch); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); + verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -511,7 +511,7 @@ int up_timer_gettime(struct timespec *ts) if (pending) { - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -576,7 +576,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_gettick(clock_t *ticks) { - *ticks = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); return OK; } @@ -681,7 +681,7 @@ int up_timer_cancel(struct timespec *ts) stm32wb_tickless_disableint(g_tickless.channel); - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; g_tickless.pending = false; @@ -807,7 +807,7 @@ int up_timer_start(const struct timespec *ts) */ period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); tmrinfo("usec=%llu period=%08llx\n", usec, period); @@ -822,7 +822,7 @@ int up_timer_start(const struct timespec *ts) g_tickless.period = (uint16_t)(period + count); #endif - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period); /* Enable interrupts. We should get the callback when the interrupt diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 9bc6340317bf0..f1bbe370e8034 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -52,63 +52,63 @@ * Such special purposes include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WB_TIMn is defined then the CONFIG_STM32WB_TIMn_PWM may also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also * be defined to indicate that the timer is intended to be used for pulsed * output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32WB_TIMn is - * defined then CONFIG_STM32WB_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32WB_TIMn is defined then - * CONFIG_STM32WB_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WB_TIM1_PWM) || defined (CONFIG_STM32WB_TIM1_ADC) || \ - defined(CONFIG_STM32WB_TIM1_QE) -# undef CONFIG_STM32WB_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WB_TIM2_PWM) || defined (CONFIG_STM32WB_TIM2_ADC) || \ - defined(CONFIG_STM32WB_TIM2_QE) -# undef CONFIG_STM32WB_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WB_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ - defined(CONFIG_STM32WB_TIM16_QE) -# undef CONFIG_STM32WB_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WB_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ - defined(CONFIG_STM32WB_TIM17_QE) -# undef CONFIG_STM32WB_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WB_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -119,8 +119,8 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -221,38 +221,38 @@ static const struct stm32wb_tim_ops_s stm32wb_tim_ops = .dump_regs = stm32wb_tim_dumpregs, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32wb_tim_priv_s stm32wb_tim1_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32wb_tim_priv_s stm32wb_tim2_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32wb_tim_priv_s stm32wb_tim16_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32wb_tim_priv_s stm32wb_tim17_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -340,9 +340,9 @@ static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_EGR_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32WB_TIM_EGR_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** @@ -351,11 +351,11 @@ static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -364,9 +364,9 @@ static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -380,7 +380,7 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_DISABLED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wb_tim_disable(dev); } @@ -393,7 +393,7 @@ static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_gpioconfig(uint32_t cfg, enum stm32wb_tim_channel_e mode) { - if (mode & STM32WB_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wb_configgpio(cfg); } @@ -413,42 +413,42 @@ static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DIER_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR2_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_ARR_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR4_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); - if (priv->base == STM32WB_TIM1_BASE) + if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } @@ -465,18 +465,18 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ -#if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) - if ((mode == STM32WB_TIM_MODE_DOWN || mode == STM32WB_TIM_MODE_UPDOWN)) +#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) + if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { -#if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM16_BASE) +#if defined(CONFIG_STM32_TIM16) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif -#if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM17_BASE) +#if defined(CONFIG_STM32_TIM17) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -486,22 +486,22 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WB_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WB_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WB_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) - case STM32WB_TIM_MODE_DOWN: +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) + case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; - case STM32WB_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; /* Our default: @@ -511,7 +511,7 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, break; #endif - case STM32WB_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; break; @@ -520,14 +520,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM1_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32WB_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -563,26 +563,26 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -647,8 +647,8 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32WB_TIM_ARR_OFFSET, reload); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -680,26 +680,26 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -730,7 +730,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } @@ -753,26 +753,26 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -782,7 +782,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } @@ -794,7 +794,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32WB_TIM_ARR_OFFSET, period); + stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** @@ -804,7 +804,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32WB_TIM_ARR_OFFSET); + return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** @@ -814,12 +814,12 @@ static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32WB_TIM_CNT_OFFSET); + uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) +#if defined(CONFIG_STM32_TIM2) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -836,8 +836,8 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) +#if defined(CONFIG_STM32_TIM2) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -859,7 +859,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -872,17 +872,17 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ - switch (mode & STM32WB_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WB_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WB_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); ccer_val |= GTIM_CCER_CCXE(channel); break; @@ -893,28 +893,28 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WB_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CCXP(channel); } if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -946,8 +946,8 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -979,8 +979,8 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -994,8 +994,8 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32WB_TIM_CCR1_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32WB_TIM_CCR2_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32WB_TIM_CCR3_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32WB_TIM_CCR4_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1063,16 +1063,16 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR1_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR2_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR3_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR4_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; @@ -1092,27 +1092,27 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - vectorno = STM32WB_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - vectorno = STM32WB_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - vectorno = STM32WB_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - vectorno = STM32WB_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1144,7 +1144,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, 0, source); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** @@ -1154,7 +1154,7 @@ static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, source, 0); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** @@ -1163,7 +1163,7 @@ static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32WB_TIM_SR_OFFSET, ~source); + stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -1172,7 +1172,7 @@ static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET); + uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1192,31 +1192,31 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; - modifyreg32(STM32WB_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,7 +1226,7 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32WB_TIM_MODE_UNUSED) + if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1251,27 +1251,27 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - modifyreg32(STM32WB_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1281,9 +1281,9 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_UNUSED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32WB_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index a1257fbee512b..742221eb57aff 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WB_STM32_TIM_H /**************************************************************************** * Included Files @@ -64,25 +64,25 @@ /* Helpers ******************************************************************/ -#define STM32WB_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WB_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32WB_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WB_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WB_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WB_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WB_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WB_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32WB_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WB_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WB_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WB_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WB_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WB_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WB_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WB_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32WB_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32WB_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32WB_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -110,34 +110,34 @@ struct stm32wb_tim_dev_s enum stm32wb_tim_mode_e { - STM32WB_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WB_TIM_MODE_MASK = 0x0310, - STM32WB_TIM_MODE_DISABLED = 0x0000, - STM32WB_TIM_MODE_UP = 0x0100, - STM32WB_TIM_MODE_DOWN = 0x0110, - STM32WB_TIM_MODE_UPDOWN = 0x0200, - STM32WB_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WB_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WB_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WB_TIM_MODE_CK_EXT = 0x0800, - STM32WB_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WB_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WB_TIM_MODE_CK_CH1 = 0x0001, - STM32WB_TIM_MODE_CK_CH2 = 0x0002, - STM32WB_TIM_MODE_CK_CH3 = 0x0003, - STM32WB_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -147,32 +147,32 @@ enum stm32wb_tim_mode_e enum stm32wb_tim_channel_e { - STM32WB_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WB_TIM_CH_POLARITY_POS = 0x00, - STM32WB_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WB_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WB_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32WB_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32WB_TIM_CH_INCAPTURE = 0x10, - STM32WB_TIM_CH_INPWM = 0x20 - STM32WB_TIM_CH_DRIVE_OC /* Open collector mode */ + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC /* Open collector mode */ #endif }; @@ -251,4 +251,4 @@ int stm32wb_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ef7af07926eb1..976cc1ba2f1c1 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -37,17 +37,17 @@ #include "stm32wb_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_TIM1_RES 16 -#define STM32WB_TIM2_RES 32 -#define STM32WB_TIM16_RES 16 -#define STM32WB_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -103,35 +103,35 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -156,13 +156,13 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WB_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WB_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -194,12 +194,12 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -232,9 +232,9 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -288,8 +288,8 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WB_TIM_GETCLOCK(priv->tim); - period = STM32WB_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -305,7 +305,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32WB_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -341,13 +341,13 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WB_TIM_SETCLOCK(priv->tim, freq); - STM32WB_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WB_TIM_SETCLOCK(priv->tim, 1000000); - STM32WB_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -386,13 +386,13 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -426,25 +426,25 @@ int stm32wb_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index c9dc2cc473866..00d539eec5548 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -56,12 +56,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WB_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -121,7 +121,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32WB_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); /* Enable SysTick interrupts */ @@ -144,5 +144,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WB_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index dc4e2dadff446..a6d2376bbb702 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32WB_STM32WB_UART_H -#define __ARCH_ARM_STC_STM32WB_STM32WB_UART_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WB_STM32_UART_H /**************************************************************************** * Included Files @@ -39,28 +39,28 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32WB_LPUART1) -# undef CONFIG_STM32WB_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WB_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WB_USART1) -# undef CONFIG_STM32WB_USART1_SERIALDRIVER -# undef CONFIG_STM32WB_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WB_LPUART1) || defined(CONFIG_STM32WB_USART1) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 @@ -82,11 +82,11 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif @@ -109,9 +109,9 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WB_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -173,4 +173,4 @@ void stm32wb_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32WB_STM32WB_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_UART_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 22e781f8c6f77..17a3808d3633d 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32wb_memorymap.h" #include "stm32wb_uid.h" -#ifdef STM32WB_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32wb_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WB_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32WB_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h index e1f01292df57e..3e2694302bad4 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ b/arch/arm/src/stm32wb/stm32wb_uid.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_UID_H +#define __ARCH_ARM_SRC_STM32WB_STM32_UID_H /**************************************************************************** * Included Files @@ -35,4 +35,4 @@ void stm32wb_get_uniqueid(uint8_t uniqueid[12]); -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_UID_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.h b/arch/arm/src/stm32wb/stm32wb_userspace.h index 4a428e9b7c892..b1141e5a61f65 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.h +++ b/arch/arm/src/stm32wb/stm32wb_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H -#define __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H +#define __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ void stm32wb_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h index 97660bf160892..4bdf7c664b3c6 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ b/arch/arm/src/stm32wb/stm32wb_waste.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H /* Waste CPU Time */ @@ -63,4 +63,4 @@ void stm32wb_waste(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_WASTE_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32wl5/chip.h b/arch/arm/src/stm32wl5/chip.h index b9f0208954f43..cfb6d0903edd9 100644 --- a/arch/arm/src/stm32wl5/chip.h +++ b/arch/arm/src/stm32wl5/chip.h @@ -49,7 +49,7 @@ * arch/stm32wl5/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WL5 */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h index 3a3b11d974c51..d1f8cb8e886b8 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_NEXTI1 31 -#define STM32WL5_EXTI1_MASK 0xffffffff -#define STM32WL5_NEXTI2 9 -#define STM32WL5_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff /* Register Offsets *********************************************************/ -#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ -#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ -#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ -#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ -#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ -#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ -#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ -#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ -#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ -#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ -#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ -#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ /* Register Addresses *******************************************************/ -#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET) -#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET) -#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET) -#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET) -#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET) -#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET) -#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET) -#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET) -#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET) -#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET) -#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET) -#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET) -#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET) -#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET) -#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET) -#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE+STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE+STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE+STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE+STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE+STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE+STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE+STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE+STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE+STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE+STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE+STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE+STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE+STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -190,4 +190,4 @@ #define EXTI_C2EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ #define EXTI_C2EMR2_MASK (0x00000300) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index 0f14d1b02ae4f..c47fa47585ced 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H /**************************************************************************** * Included Files @@ -35,10 +35,10 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT is set the - * CONFIG_STM32WL5_FLASH_CONFIG_x selects the default FLASH size based + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the + * CONFIG_STM32_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with - * CONFIG_STM32WL5_FLASH_OVERRIDE_x. For example: + * CONFIG_STM32_FLASH_OVERRIDE_x. For example: * * Parts STM32WL5xx8 have 64KiB of FLASH * Parts STM32WL5xxB have 128KiB of FLASH @@ -47,110 +47,110 @@ * STM32WL5xxx has only single bank flash and page size 2KiB */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_G) -# define CONFIG_STM32WL5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WL5_FLASH_CONFIG_8 -# undef CONFIG_STM32WL5_FLASH_CONFIG_B -# undef CONFIG_STM32WL5_FLASH_CONFIG_C -# undef CONFIG_STM32WL5_FLASH_CONFIG_E -# undef CONFIG_STM32WL5_FLASH_CONFIG_G -# if defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) -# define CONFIG_STM32WL5_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) -# define CONFIG_STM32WL5_FLASH_CONFIG_B -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) -# define CONFIG_STM32WL5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) -# define CONFIG_STM32WL5_FLASH_CONFIG_E -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) -# define CONFIG_STM32WL5_FLASH_CONFIG_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */ -# define STM32WL5_FLASH_NPAGES 32 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */ -# define STM32WL5_FLASH_NPAGES 64 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32WL5_FLASH_NPAGES 128 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32WL5_FLASH_NPAGES 256 -# define STM32WL5_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */ -# define STM32WL5_FLASH_NPAGES 512 -# define STM32WL5_FLASH_PAGESIZE 2048 +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #else # error "unknown flash configuration!" #endif -#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WL5_FLASH_ACR_OFFSET 0x0000 -#define STM32WL5_FLASH_ACR2_OFFSET 0x0004 -#define STM32WL5_FLASH_KEYR_OFFSET 0x0008 -#define STM32WL5_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32WL5_FLASH_SR_OFFSET 0x0010 -#define STM32WL5_FLASH_CR_OFFSET 0x0014 -#define STM32WL5_FLASH_ECCR_OFFSET 0x0018 -#define STM32WL5_FLASH_OPTR_OFFSET 0x0020 -#define STM32WL5_FLASH_PCROP1ASR_OFFSET 0x0024 -#define STM32WL5_FLASH_PCROP1AER_OFFSET 0x0028 -#define STM32WL5_FLASH_WRP1AR_OFFSET 0x002c -#define STM32WL5_FLASH_WRP1BR_OFFSET 0x0030 -#define STM32WL5_FLASH_PCROP1BSR_OFFSET 0x0034 -#define STM32WL5_FLASH_PCROP1BER_OFFSET 0x0038 -#define STM32WL5_FLASH_IPCCBR_OFFSET 0x003c -#define STM32WL5_FLASH_C2ACR_OFFSET 0x005c -#define STM32WL5_FLASH_C2SR_OFFSET 0x0060 -#define STM32WL5_FLASH_C2CR_OFFSET 0x0064 -#define STM32WL5_FLASH_SFR_OFFSET 0x0080 -#define STM32WL5_FLASH_SRRVR_OFFSET 0x0084 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_ACR2_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 +#define STM32_FLASH_IPCCBR_OFFSET 0x003c +#define STM32_FLASH_C2ACR_OFFSET 0x005c +#define STM32_FLASH_C2SR_OFFSET 0x0060 +#define STM32_FLASH_C2CR_OFFSET 0x0064 +#define STM32_FLASH_SFR_OFFSET 0x0080 +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_ACR2 (STM32_FLASHIF_BASE+STM32_FLASH_ACR2_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHIF_BASE+STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHIF_BASE+STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHIF_BASE+STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHIF_BASE+STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHIF_BASE+STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHIF_BASE+STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -301,4 +301,4 @@ #define FLASH_C2CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ #define FLASH_C2CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h index 9f76cb4efa0fc..780b84646d494 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files @@ -36,71 +36,71 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WL5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WL5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WL5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WL5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WL5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WL5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WL5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WL5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WL5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WL5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WL5_GPIOA_MODER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOA_OTYPER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOA_OSPEED (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOA_PUPDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOA_IDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOA_ODR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOA_BSRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOA_LCKR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOA_AFRL (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOA_AFRH (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOA_BRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOA_ASCR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOB_MODER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOB_OTYPER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOB_OSPEED (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOB_PUPDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOB_IDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOB_ODR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOB_BSRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOB_LCKR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOB_AFRL (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOB_AFRH (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOB_BRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOB_ASCR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOC_MODER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOC_OTYPER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOC_OSPEED (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOC_PUPDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOC_IDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOC_ODR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOC_BSRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOC_LCKR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOC_AFRL (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOC_AFRH (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOC_BRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOC_ASCR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ASCR_OFFSET) - -#define STM32WL5_GPIOH_MODER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOH_OTYPER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOH_OSPEED (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOH_PUPDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOH_IDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOH_ODR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOH_BSRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOH_LCKR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOH_AFRL (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOH_AFRH (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOH_BRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOH_ASCR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) + +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -298,4 +298,4 @@ #define GPIO_ASCR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h index 56632c5a9360a..d94f168008b0b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H /**************************************************************************** * Included Files @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_IPCC_CPU1_OFFSET 0x00 -#define STM32WL5_IPCC_CPU2_OFFSET 0x10 +#define STM32_IPCC_CPU1_OFFSET 0x00 +#define STM32_IPCC_CPU2_OFFSET 0x10 /* Register Offsets *********************************************************/ -#define STM32WL5_IPCC_CR_OFFSET 0x00 /* IPCC control register */ -#define STM32WL5_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ -#define STM32WL5_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ -#define STM32WL5_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ +#define STM32_IPCC_CR_OFFSET 0x00 /* IPCC control register */ +#define STM32_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ +#define STM32_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ +#define STM32_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ /* Register Addresses *******************************************************/ -#define STM32WL5_IPCC_C1CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1TOC2SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C2CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2TOC1SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU2_OFFSET) /* Register Bitfield Definitions ********************************************/ -#define STM32WL5_IPCC_TX_SHIFT (16) /* TX shift for all registers */ +#define STM32_IPCC_TX_SHIFT (16) /* TX shift for all registers */ /* IPCC control register */ -#define STM32WL5_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ -#define STM32WL5_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ +#define STM32_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ +#define STM32_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ /* IPCC mask register */ -#define STM32WL5_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ -#define STM32WL5_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ /* IPCC status set clear register */ -#define STM32WL5_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ -#define STM32WL5_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ /* IPCC processor to processor status register */ -#define STM32WL5_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ +#define STM32_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h index 89df326775bf3..4d336c7fe61d4 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -29,40 +29,40 @@ /* STM32WL5XXX Address Blocks ***********************************************/ -#define STM32WL5_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ -#define STM32WL5_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ -#define STM32WL5_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ - /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ -#define STM32WL5_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ + /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ -#define STM32WL5_REGION_MASK 0xf0000000 -#define STM32WL5_IS_SRAM(a) ((((uint32_t)(a)) & STM32WL5_REGION_MASK) == STM32WL5_SRAM_BASE) +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) /* Code Base Addresses ******************************************************/ -#define STM32WL5_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ - /* 0x0004 0000-0x07ff ffff: Reserved */ -#define STM32WL5_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ - /* 0x0804 0000-0x0fff ffff: Reserved */ -#define STM32WL5_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ - /* 0x1000 0000-0x1ffe 6fff: Reserved */ -#define STM32WL5_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ -#define STM32WL5_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ -#define STM32WL5_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ -#define STM32WL5_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ - /* 0x1fff 8000-0x1fff ffff: reserved */ -#define STM32WL5_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ + /* 0x0004 0000-0x07ff ffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ + /* 0x0804 0000-0x0fff ffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ + /* 0x1000 0000-0x1ffe 6fff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ +#define STM32_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ +#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ + /* 0x1fff 8000-0x1fff ffff: reserved */ +#define STM32_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32WL5_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: UFBGA73 * 2: WLCSP59 * 10: UFQFPN48 */ -#define STM32WL5_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WL5_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. @@ -70,92 +70,92 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WL5_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WL5_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ - /* 0x4000 B400-0x4000 ffff: Reserved */ -#define STM32WL5_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ - /* 0x4001 4c00-0x4001 ffff: Reserved */ -#define STM32WL5_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ - /* 0x4260 0000-0x47ff ffff: Reserved */ -#define STM32WL5_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ - /* 0x4800 2000-0x57ff ffff: Reserved */ -#define STM32WL5_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ - /* 0x5800 40c0-0x5800 ffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ + /* 0x4000 B400-0x4000 ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ + /* 0x4001 4c00-0x4001 ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ + /* 0x4260 0000-0x47ff ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ + /* 0x4800 2000-0x57ff ffff: Reserved */ +#define STM32_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ + /* 0x5800 40c0-0x5800 ffff: Reserved */ /* Radio Base Addresses *****************************************************/ -#define STM32WL5_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ - /* 0x5801 0400-0x5801 ffff: Reserved */ +#define STM32_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ + /* 0x5801 0400-0x5801 ffff: Reserved */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32WL5_TAMP_BASE 0x4000B000 -#define STM32WL5_LPTIM3_BASE 0x40009800 -#define STM32WL5_LPTIM2_BASE 0x40009400 -#define STM32WL5_LPUART1_BASE 0x40008000 -#define STM32WL5_LPTIM1_BASE 0x40007C00 -#define STM32WL5_DAC_BASE 0x40007400 -#define STM32WL5_I2C3_BASE 0x40005C00 -#define STM32WL5_I2C2_BASE 0x40005800 -#define STM32WL5_I2C1_BASE 0x40005400 -#define STM32WL5_USART2_BASE 0x40004400 -#define STM32WL5_SPI2S2_BASE 0x40003800 -#define STM32WL5_IWDG_BASE 0x40003000 -#define STM32WL5_WWDG_BASE 0x40002C00 -#define STM32WL5_RTC_BASE 0x40002800 -#define STM32WL5_TIM2_BASE 0x40000000 +#define STM32_TAMP_BASE 0x4000B000 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_DAC_BASE 0x40007400 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI2S2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32WL5_TIM17_BASE 0x40014800 -#define STM32WL5_TIM16_BASE 0x40014400 -#define STM32WL5_USART1_BASE 0x40013800 -#define STM32WL5_SPI1_BASE 0x40013000 -#define STM32WL5_TIM1_BASE 0x40012C00 -#define STM32WL5_ADC_BASE 0x40012400 -#define STM32WL5_COMP_BASE 0x40010200 -#define STM32WL5_SYSCFG2_BASE 0x40010100 -#define STM32WL5_VREFBUF_BASE 0x40010030 -#define STM32WL5_SYSCFG_BASE 0x40010000 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_USART1_BASE 0x40013800 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_ADC_BASE 0x40012400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_SYSCFG2_BASE 0x40010100 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32WL5_CRC_BASE 0x40023000 -#define STM32WL5_DMAMUX1_BASE 0x40200800 -#define STM32WL5_DMA2_BASE 0x40200400 -#define STM32WL5_DMA1_BASE 0x40020000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_DMAMUX1_BASE 0x40200800 +#define STM32_DMA2_BASE 0x40200400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WL5_GPIOH_BASE 0x48001C00 -#define STM32WL5_GPIOC_BASE 0x48000800 -#define STM32WL5_GPIOB_BASE 0x48000400 -#define STM32WL5_GPIOA_BASE 0x48000000 +#define STM32_GPIOH_BASE 0x48001C00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WL5_GTZC_TZIC_BASE 0x58004800 -#define STM32WL5_GTZC_TZSC_BASE 0x58004400 -#define STM32WL5_FLASHIF_BASE 0x58004000 -#define STM32WL5_PKA2_BASE 0x58003400 -#define STM32WL5_PKARAM_BASE 0x58002400 -#define STM32WL5_PKA_BASE 0x58002000 -#define STM32WL5_AES_BASE 0x58001800 -#define STM32WL5_HSEM_BASE 0x58001400 -#define STM32WL5_RNG_BASE 0x58001000 -#define STM32WL5_IPCC_BASE 0x58000C00 -#define STM32WL5_EXTI_BASE 0x58000800 -#define STM32WL5_PWR_BASE 0x58000400 -#define STM32WL5_RCC_BASE 0x58000000 +#define STM32_GTZC_TZIC_BASE 0x58004800 +#define STM32_GTZC_TZSC_BASE 0x58004400 +#define STM32_FLASHIF_BASE 0x58004000 +#define STM32_PKA2_BASE 0x58003400 +#define STM32_PKARAM_BASE 0x58002400 +#define STM32_PKA_BASE 0x58002000 +#define STM32_AES_BASE 0x58001800 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_RNG_BASE 0x58001000 +#define STM32_IPCC_BASE 0x58000C00 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_PWR_BASE 0x58000400 +#define STM32_RCC_BASE 0x58000000 /* APB3 Base Addresses ******************************************************/ -#define STM32WL5_SUBGHZSPI_BASE 0x58010000 +#define STM32_SUBGHZSPI_BASE 0x58010000 /* Cortex-M4 Base Addresses *************************************************/ @@ -163,7 +163,7 @@ * this address range */ -#define STM32WL5_SCS_BASE 0xe000e000 -#define STM32WL5_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h index b38799ada8bcc..421bbc2625d11 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pinmap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H /**************************************************************************** * Included Files @@ -331,4 +331,4 @@ #define GPIO_LSCO_1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN2) #define GPIO_MCO_1 (GPIO_ALT|GPIO_AF0 |GPIO_PORTA|GPIO_PIN8) -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h index 978e931a4d588..3523cfbb80438 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H /**************************************************************************** * Included Files @@ -36,53 +36,53 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WL5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WL5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WL5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WL5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WL5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WL5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WL5_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WL5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WL5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WL5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WL5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WL5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WL5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WL5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WL5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WL5_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ -#define STM32WL5_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ -#define STM32WL5_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ -#define STM32WL5_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ -#define STM32WL5_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ -#define STM32WL5_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ +#define STM32_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ +#define STM32_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ +#define STM32_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ /* Register Addresses *******************************************************/ -#define STM32WL5_PWR_CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR1_OFFSET) -#define STM32WL5_PWR_CR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR2_OFFSET) -#define STM32WL5_PWR_CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR3_OFFSET) -#define STM32WL5_PWR_CR4 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR4_OFFSET) -#define STM32WL5_PWR_SR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR1_OFFSET) -#define STM32WL5_PWR_SR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR2_OFFSET) -#define STM32WL5_PWR_SCR (STM32WL5_PWR_BASE+STM32WL5_PWR_SCR_OFFSET) -#define STM32WL5_PWR_CR5 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR5_OFFSET) -#define STM32WL5_PWR_PUCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRA_OFFSET) -#define STM32WL5_PWR_PDCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRA_OFFSET) -#define STM32WL5_PWR_PUCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRB_OFFSET) -#define STM32WL5_PWR_PDCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRB_OFFSET) -#define STM32WL5_PWR_PUCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRC_OFFSET) -#define STM32WL5_PWR_PDCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRC_OFFSET) -#define STM32WL5_PWR_PUCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRH_OFFSET) -#define STM32WL5_PWR_PDCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRH_OFFSET) -#define STM32WL5_PWR_C2CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR1_OFFSET) -#define STM32WL5_PWR_C2CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR3_OFFSET) -#define STM32WL5_PWR_EXTSCR (STM32WL5_PWR_BASE+STM32WL5_PWR_EXTSCR_OFFSET) -#define STM32WL5_PWR_SECCFGR (STM32WL5_PWR_BASE+STM32WL5_PWR_SECCFGR_OFFSET) -#define STM32WL5_PWR_SUBGHZSPICR (STM32WL5_PWR_BASE+STM32WL5_PWR_SUBGHZSPICR_OFFSET) -#define STM32WL5_PWR_RSSCMDR (STM32WL5_PWR_BASE+STM32WL5_PWR_RSSCMDR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE+STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE+STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE+STM32_PWR_EXTSCR_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE+STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_SUBGHZSPICR (STM32_PWR_BASE+STM32_PWR_SUBGHZSPICR_OFFSET) +#define STM32_PWR_RSSCMDR (STM32_PWR_BASE+STM32_PWR_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -197,4 +197,4 @@ * with a few exceptions */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h index 3f7309342f300..d0bfdf1b601ab 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_RCC_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -35,95 +35,95 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WL5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WL5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WL5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WL5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WL5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WL5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WL5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WL5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WL5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WL5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WL5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WL5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WL5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32WL5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WL5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WL5_RCC_EXTCFGR_OFFSET 0x0108 -#define STM32WL5_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ /* Register Addresses *******************************************************/ -#define STM32WL5_RCC_CR (STM32WL5_RCC_BASE + STM32WL5_RCC_CR_OFFSET) -#define STM32WL5_RCC_ICSCR (STM32WL5_RCC_BASE + STM32WL5_RCC_ICSCR_OFFSET) -#define STM32WL5_RCC_CFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_CFGR_OFFSET) -#define STM32WL5_RCC_PLLCFG (STM32WL5_RCC_BASE + STM32WL5_RCC_PLLCFG_OFFSET) -#define STM32WL5_RCC_CIER (STM32WL5_RCC_BASE + STM32WL5_RCC_CIER_OFFSET) -#define STM32WL5_RCC_CIFR (STM32WL5_RCC_BASE + STM32WL5_RCC_CIFR_OFFSET) -#define STM32WL5_RCC_CICR (STM32WL5_RCC_BASE + STM32WL5_RCC_CICR_OFFSET) -#define STM32WL5_RCC_AHB1RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1RSTR_OFFSET) -#define STM32WL5_RCC_AHB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB3RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3RSTR_OFFSET) -#define STM32WL5_RCC_APB1RSTR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR1_OFFSET) -#define STM32WL5_RCC_APB1RSTR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR2_OFFSET) -#define STM32WL5_RCC_APB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1ENR_OFFSET) -#define STM32WL5_RCC_AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2ENR_OFFSET) -#define STM32WL5_RCC_AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3ENR_OFFSET) -#define STM32WL5_RCC_APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR1_OFFSET) -#define STM32WL5_RCC_APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR2_OFFSET) -#define STM32WL5_RCC_APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2ENR_OFFSET) -#define STM32WL5_RCC_AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1SMENR_OFFSET) -#define STM32WL5_RCC_AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2SMENR_OFFSET) -#define STM32WL5_RCC_AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3SMENR_OFFSET) -#define STM32WL5_RCC_APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR1_OFFSET) -#define STM32WL5_RCC_APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR2_OFFSET) -#define STM32WL5_RCC_APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2SMENR_OFFSET) -#define STM32WL5_RCC_CCIPR (STM32WL5_RCC_BASE + STM32WL5_RCC_CCIPR_OFFSET) -#define STM32WL5_RCC_BDCR (STM32WL5_RCC_BASE + STM32WL5_RCC_BDCR_OFFSET) -#define STM32WL5_RCC_CSR (STM32WL5_RCC_BASE + STM32WL5_RCC_CSR_OFFSET) -#define STM32WL5_RCC_EXTCFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_EXTCFGR_OFFSET) -#define STM32WL5_RCC_C2AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1ENR_OFFSET) -#define STM32WL5_RCC_C2AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2ENR_OFFSET) -#define STM32WL5_RCC_C2AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3ENR_OFFSET) -#define STM32WL5_RCC_C2APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR1_OFFSET) -#define STM32WL5_RCC_C2APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR2_OFFSET) -#define STM32WL5_RCC_C2APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2ENR_OFFSET) -#define STM32WL5_RCC_C2APB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3ENR_OFFSET) -#define STM32WL5_RCC_C2AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3SMENR_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR1_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR2_OFFSET) -#define STM32WL5_RCC_C2APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2SMENR_OFFSET) -#define STM32WL5_RCC_C2APB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index 22c61af23aedb..79da83f3530ba 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H /**************************************************************************** * Included Files @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32WL5_HAVE_IP_SPI_V2) +#if defined(STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V3) +#if defined(STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V4) +#if defined(STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -74,66 +74,66 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32WL5_STM32F4XXX) -# define STM32WL5_SPI_CLK_MAX 37500000UL +#if defined(CONFIG_STM32_STM32F4XXX) +# define STM32_SPI_CLK_MAX 37500000UL #else -# define STM32WL5_SPI_CLK_MAX 18000000UL +# define STM32_SPI_CLK_MAX 18000000UL #endif /* Register Offsets *********************************************************/ -#define STM32WL5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WL5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WL5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WL5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WL5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WL5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WL5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ #if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -# define STM32WL5_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif /* Register Addresses *******************************************************/ -#if STM32WL5_NSPI > 0 -# define STM32WL5_SPI1_CR1 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI1_CR2 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI1_SR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI1_DR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI1_CRCPR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI1_RXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI1_TXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 \ + (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 \ + (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR \ + (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR \ + (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR \ + (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32WL5_NSPI > 1 -# define STM32WL5_SPI2S2_CR1 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI2S2_CR2 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI2S2_SR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI2S2_DR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI2S2_CRCPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI2S2_RXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI2S2_TXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2S2_CR1 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2S2_CR2 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2S2_SR \ + (STM32_SPI2S2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2S2_DR \ + (STM32_SPI2S2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2S2_CRCPR \ + (STM32_SPI2S2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2S2_RXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2S2_TXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_TXCRCR_OFFSET) # if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI2S2_I2SCFGR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SCFGR_OFFSET) -# define STM32WL5_SPI2S2_I2SPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SPR_OFFSET) +# define STM32_SPI2S2_I2SCFGR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2S2_I2SPR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif @@ -276,4 +276,4 @@ # define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h index eaf17d3ad0d82..b0025be1da990 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -36,43 +36,43 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WL5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ - -#define STM32WL5_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ - -#define STM32WL5_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WL5_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WL5_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WL5_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WL5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WL5_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WL5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32WL5_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WL5_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ + +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ + +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ +#define STM32_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ /* Register Addresses *******************************************************/ -#define STM32WL5_SYSCFG_MEMRMP (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_MEMRMP_OFFSET) -#define STM32WL5_SYSCFG_CFGR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR1_OFFSET) -#define STM32WL5_SYSCFG_EXTICR(p) (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WL5_SYSCFG_EXTICR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR1) -#define STM32WL5_SYSCFG_EXTICR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR2) -#define STM32WL5_SYSCFG_EXTICR3 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR3) -#define STM32WL5_SYSCFG_EXTICR4 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR4) -#define STM32WL5_SYSCFG_SCSR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SCSR) -#define STM32WL5_SYSCFG_CFGR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR2) -#define STM32WL5_SYSCFG_SWPR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SWPR) -#define STM32WL5_SYSCFG_SKR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SKR) -#define STM32WL5_SYSCFG_IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR1) -#define STM32WL5_SYSCFG_IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR2) -#define STM32WL5_SYSCFG_C2IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR1) -#define STM32WL5_SYSCFG_C2IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR2) -#define STM32WL5_SYSCFG_RFDCR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_RFDCR) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR) +#define STM32_SYSCFG_IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR1) +#define STM32_SYSCFG_IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR2) +#define STM32_SYSCFG_C2IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR1) +#define STM32_SYSCFG_C2IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR2) +#define STM32_SYSCFG_RFDCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RFDCR) /* Register Bitfield Definitions ********************************************/ @@ -243,4 +243,4 @@ #define SYSCFG_RFDCR_RFTBSEL (1 << 0) /* Bit 0: Analog test bus on RF[ADTB[3:0] */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h index 1ffe5b780381b..3871365bc4920 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H /**************************************************************************** * Pre-processor Definitions @@ -31,166 +31,166 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32WL5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ -#define STM32WL5_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WL5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ +#define STM32_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 32-bit General Timers - TIM2 * TIM2 and 5 are 32-bit. * TIM15, 16 and 17 are 16-bit. */ -#define STM32WL5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32WL5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32WL5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32WL5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32WL5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WL5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32WL5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32WL5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 */ -#define STM32WL5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32WL5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32WL5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32WL5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32WL5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32WL5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32WL5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32WL5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32WL5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32WL5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32WL5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32WL5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32WL5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32WL5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32WL5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32WL5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32WL5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32WL5_TIM1_CR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR1_OFFSET) -#define STM32WL5_TIM1_CR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR2_OFFSET) -#define STM32WL5_TIM1_SMCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SMCR_OFFSET) -#define STM32WL5_TIM1_DIER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DIER_OFFSET) -#define STM32WL5_TIM1_SR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SR_OFFSET) -#define STM32WL5_TIM1_EGR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_EGR_OFFSET) -#define STM32WL5_TIM1_CCMR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR1_OFFSET) -#define STM32WL5_TIM1_CCMR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR2_OFFSET) -#define STM32WL5_TIM1_CCER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCER_OFFSET) -#define STM32WL5_TIM1_CNT (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CNT_OFFSET) -#define STM32WL5_TIM1_PSC (STM32WL5_TIM1_BASE+STM32WL5_ATIM_PSC_OFFSET) -#define STM32WL5_TIM1_ARR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_ARR_OFFSET) -#define STM32WL5_TIM1_RCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_RCR_OFFSET) -#define STM32WL5_TIM1_CCR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR1_OFFSET) -#define STM32WL5_TIM1_CCR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR2_OFFSET) -#define STM32WL5_TIM1_CCR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR3_OFFSET) -#define STM32WL5_TIM1_CCR4 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR4_OFFSET) -#define STM32WL5_TIM1_BDTR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_BDTR_OFFSET) -#define STM32WL5_TIM1_DCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DCR_OFFSET) -#define STM32WL5_TIM1_DMAR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DMAR_OFFSET) -#define STM32WL5_TIM1_OR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR1_OFFSET) -#define STM32WL5_TIM1_CCMR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR3_OFFSET) -#define STM32WL5_TIM1_CCR5 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR5_OFFSET) -#define STM32WL5_TIM1_CCR6 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR6_OFFSET) -#define STM32WL5_TIM1_OR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR2_OFFSET) -#define STM32WL5_TIM1_OR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM16-17. * TIM2 is 32-bit. * TIM16 and 17 are 16-bit. */ -#define STM32WL5_TIM2_CR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM2_CR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM2_SMCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SMCR_OFFSET) -#define STM32WL5_TIM2_DIER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM2_SR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM2_EGR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM2_CCMR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM2_CCMR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR2_OFFSET) -#define STM32WL5_TIM2_CCER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM2_CNT (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM2_PSC (STM32WL5_TIM2_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM2_ARR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM2_CCR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM2_CCR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR2_OFFSET) -#define STM32WL5_TIM2_CCR3 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR3_OFFSET) -#define STM32WL5_TIM2_CCR4 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR4_OFFSET) -#define STM32WL5_TIM2_DCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM2_DMAR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM2_OR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM16_CR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM16_CR2 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM16_DIER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM16_SR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM16_EGR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM16_CCMR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM16_CCER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM16_CNT (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM16_PSC (STM32WL5_TIM16_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM16_ARR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM16_RCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM16_CCR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM16_BDTR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM16_DCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM16_DMAR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM16_OR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_OR_OFFSET) - -#define STM32WL5_TIM17_CR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM17_CR2 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM17_DIER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM17_SR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM17_EGR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM17_CCMR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM17_CCER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM17_CNT (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM17_PSC (STM32WL5_TIM17_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM17_ARR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM17_RCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM17_CCR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM17_BDTR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM17_DCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM17_DMAR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DMAR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -999,4 +999,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h index 5eb2450e7a34f..a98e638157028 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H /**************************************************************************** * Included Files @@ -37,57 +37,57 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WL5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WL5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32WL5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32WL5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32WL5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32WL5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32WL5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32WL5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32WL5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32WL5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32WL5_USART_PRESC_OFFSET 0x002c /* Prescaler */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler */ /* Register Addresses *******************************************************/ -#define STM32WL5_USART1_CR1 (STM32WL5_USART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART1_CR2 (STM32WL5_USART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART1_CR3 (STM32WL5_USART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART1_BRR (STM32WL5_USART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART1_GTPR (STM32WL5_USART1_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART1_RTOR (STM32WL5_USART1_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART1_RQR (STM32WL5_USART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART1_ISR (STM32WL5_USART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART1_ICR (STM32WL5_USART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART1_RDR (STM32WL5_USART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART1_TDR (STM32WL5_USART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART1_PRESC (STM32WL5_USART1_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_USART2_CR1 (STM32WL5_USART2_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART2_CR2 (STM32WL5_USART2_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART2_CR3 (STM32WL5_USART2_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART2_BRR (STM32WL5_USART2_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART2_GTPR (STM32WL5_USART2_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART2_RTOR (STM32WL5_USART2_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART2_RQR (STM32WL5_USART2_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART2_ISR (STM32WL5_USART2_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART2_ICR (STM32WL5_USART2_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART2_RDR (STM32WL5_USART2_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART2_TDR (STM32WL5_USART2_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART2_PRESC (STM32WL5_USART2_BASE+STM32WL5_USART_PRESC_OFFSET) - -#define STM32WL5_LPUART1_CR1 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_LPUART1_CR2 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_LPUART1_CR3 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_LPUART1_BRR (STM32WL5_LPUART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_LPUART1_RQR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_LPUART1_ISR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_LPUART1_ICR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_LPUART1_RDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_LPUART1_TDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_LPUART1_PRESC (STM32WL5_LPUART1_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART1_PRESC (STM32_USART1_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART2_PRESC (STM32_USART2_BASE+STM32_USART_PRESC_OFFSET) + +#define STM32_LPUART1_CR1 (STM32_LPUART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_LPUART1_CR2 (STM32_LPUART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_LPUART1_CR3 (STM32_LPUART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_LPUART1_BRR (STM32_LPUART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_LPUART1_RQR (STM32_LPUART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_LPUART1_ISR (STM32_LPUART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_LPUART1_ICR (STM32_LPUART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_LPUART1_RDR (STM32_LPUART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_LPUART1_TDR (STM32_LPUART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_LPUART1_PRESC (STM32_LPUART1_BASE+STM32_USART_PRESC_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -330,4 +330,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5.h b/arch/arm/src/stm32wl5/stm32wl5.h index 5b7eb4404301f..28852b00d7979 100644 --- a/arch/arm/src/stm32wl5/stm32wl5.h +++ b/arch/arm/src/stm32wl5/stm32wl5.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_H /**************************************************************************** * Included Files @@ -64,4 +64,4 @@ void stm32wl5_spidev_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 61e9a51df81f7..af951cb75bf90 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -66,28 +66,28 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32WL5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32WL5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ #ifdef CONFIG_IPCC # define SRAM2_START IPCC_END #else -# define SRAM2_START STM32WL5_SRAM2_BASE +# define SRAM2_START STM32_SRAM2_BASE #endif -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Some sanity checking. If multiple memory regions are defined, verify * that CONFIG_MM_REGIONS is set to match the number of memory regions * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -264,7 +264,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32WL5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti.h b/arch/arm/src/stm32wl5/stm32wl5_exti.h index 9535111414edb..2930a4e3473c7 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/stm32wl5_exti.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H /**************************************************************************** * Included Files @@ -141,7 +141,7 @@ int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_COMP +#ifdef CONFIG_STM32_COMP int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif @@ -152,4 +152,4 @@ int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index 6d6318f023832..f94f6f9bbdabf 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32WL5_EXTI_PR1); + putreg32(0x0001, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32WL5_EXTI_PR1); + putreg32(0x0002, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32WL5_EXTI_PR1); + putreg32(0x0004, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32WL5_EXTI_PR1); + putreg32(0x0008, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32WL5_EXTI_PR1); + putreg32(0x0010, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WL5_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WL5_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -267,7 +267,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WL5_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WL5_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wl5_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WL5_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wl5_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WL5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32WL5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WL5_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32WL5_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 054ca10b3ae1d..41c5793caeaaa 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -50,7 +50,7 @@ #include "stm32wl5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -65,7 +65,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */ @@ -93,35 +93,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WL5_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WL5_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WL5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WL5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -138,17 +138,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", (unsigned int)page); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -227,20 +227,20 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WL5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WL5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } @@ -253,42 +253,42 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WL5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WL5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WL5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WL5_FLASH_PAGESIZE + STM32WL5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WL5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -300,7 +300,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WL5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -338,7 +338,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -372,12 +372,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WL5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WL5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -447,7 +447,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -455,14 +455,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } /* Verify */ - if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -476,7 +476,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; /* Adjust pointers and counts for the next time through the loop */ @@ -492,7 +492,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); } /* If there was an error, clear all error flags in status register (rc_w1 @@ -502,9 +502,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WL5_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.h b/arch/arm/src/stm32wl5/stm32wl5_flash.h index 87f0abbdeb3e6..8e4ab01607789 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int stm32wl5_flash_unlock(void); uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index 3b22db6f904e2..b3ec90cac4cb1 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -55,19 +55,19 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WL5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32WL5_NPORTS > 0 - STM32WL5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32WL5_NPORTS > 1 - STM32WL5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32WL5_NPORTS > 2 - STM32WL5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32WL5_NPORTS > 3 - STM32WL5_GPIOH_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOH_BASE, #endif }; @@ -130,7 +130,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WL5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -179,10 +179,10 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WL5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -205,10 +205,10 @@ int stm32wl5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WL5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -223,12 +223,12 @@ int stm32wl5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32WL5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32WL5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -266,14 +266,14 @@ int stm32wl5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WL5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WL5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -286,7 +286,7 @@ int stm32wl5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -303,7 +303,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WL5_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -365,7 +365,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -386,7 +386,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WL5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -405,7 +405,7 @@ bool stm32wl5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -414,7 +414,7 @@ bool stm32wl5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WL5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 86480eb193a55..04b306205c9f2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H /**************************************************************************** * Included Files @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32WL5_STM32WL5XXX) +#if defined(CONFIG_STM32_STM32WL5XXX) # include "hardware/stm32wl5_gpio.h" #else # error "Unsupported STM32WL5 chip" @@ -237,7 +237,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes @@ -358,4 +358,4 @@ void stm32wl5_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_idle.c b/arch/arm/src/stm32wl5/stm32wl5_idle.c index ec70f83270f97..ab1fb4d073dda 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_idle.c +++ b/arch/arm/src/stm32wl5/stm32wl5_idle.c @@ -88,7 +88,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WL5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index 38a41c718032e..d625e58f1e683 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -225,8 +225,8 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR) >> STM32WL5_IPCC_TX_SHIFT; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + mr = getreg32(STM32_IPCC_C1MR) >> STM32_IPCC_TX_SHIFT; + sr = getreg32(STM32_IPCC_C1TOC2SR); /* Consider only channels that have tx memory free and are unmasked */ @@ -266,7 +266,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) /* Yes, tell another CPU that data is available to read */ txmem->len = nwritten; - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(chan)); } if (circbuf_used(&priv->ipcc->txbuf) == 0) @@ -276,7 +276,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * will be constantly interrupted by tx free irq. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); } #else /* CONFIG_IPCC_BUFFERED */ /* In unbuffered operations we never write anything to IPCC @@ -284,7 +284,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * or else we will constantly get TX interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); #endif /* CONFIG_IPCC_BUFFERED */ /* Wake up all blocked writers that there is free space available * in IPCC memory (or txbuffer) to write. @@ -324,7 +324,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_chan_mem_s *txmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + sr = getreg32(STM32_IPCC_C1TOC2SR); if ((sr & (1 << ipcc->chan))) { @@ -334,7 +334,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * so we are notified when we can write to memory. */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } @@ -343,7 +343,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Disable TX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Copy as much as we can into IPCC memory */ @@ -353,12 +353,12 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Tell another CPU that data is available to read */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(ipcc->chan)); /* Re-enable interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Return number of successfully copied bytes to IPCC memory */ @@ -404,8 +404,8 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR); - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + mr = getreg32(STM32_IPCC_C1MR); + sr = getreg32(STM32_IPCC_C2TOC1SR); /* Consider only channels that have data in rx memory and are unmasked */ @@ -446,7 +446,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * we have to mask rxirq so we don't get that irq again. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); #endif } @@ -485,7 +485,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_s *priv; struct stm32wl5_ipcc_chan_mem_s *rxmem; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << ipcc->chan))) { @@ -502,7 +502,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* This function may be called multiple times to get only part * of data from IPCC memory, ie. There are 8 bytes of data in @@ -525,17 +525,17 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, - STM32WL5_IPCC_SCR_CHNC(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, + STM32_IPCC_SCR_CHNC(ipcc->chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(ipcc->chan), 0); } /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); return to_copy; } @@ -569,7 +569,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, struct stm32wl5_ipcc_chan_mem_s *rxmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << chan))) { @@ -609,7 +609,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, * this one. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); } /* Buffer data. This function cannot really fail us if we @@ -629,11 +629,11 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNC(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNC(chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); } return to_copy; @@ -665,7 +665,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Copy data to buffer */ @@ -673,7 +673,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Return number of bytes that were successfully buffered */ @@ -701,7 +701,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #ifdef CONFIG_IPCC_BUFFERED static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) { - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } #endif @@ -728,8 +728,8 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) /* Mask interrupts for given channel */ - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNFM(ipcc->chan)); - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNOM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNFM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNOM(ipcc->chan)); /* Free allocated ipcc memory */ @@ -798,8 +798,8 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) /* Unmask channel interrupt */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(chan), 0); - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); if (ipcc_fti) { @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); @@ -829,11 +829,11 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * - CPU2 has read message from us and TX memory is free to be used again */ - putreg32(STM32WL5_IPCC_CR_RXOIE | STM32WL5_IPCC_CR_TXFIE, - STM32WL5_IPCC_C1CR); + putreg32(STM32_IPCC_CR_RXOIE | STM32_IPCC_CR_TXFIE, + STM32_IPCC_C1CR); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); ipcc_fti = 1; diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 14b68fdb151f3..2de8022042e4f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -41,17 +41,17 @@ /* channel 1 configuration **************************************************/ -#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_RX_SIZE) -#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_TX_SIZE) +#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32_IPCC_CHAN1_RX_SIZE) +#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32_IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1_START (IPCC_START) #define IPCC_CHAN1_SIZE (IPCC_CHAN1_RX_SIZE + IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1 (1) /* channel 2 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN2) -# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_RX_SIZE) -# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN2) +# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32_IPCC_CHAN2_RX_SIZE) +# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32_IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2_START (IPCC_CHAN1_START + IPCC_CHAN1_SIZE) # define IPCC_CHAN2_SIZE (IPCC_CHAN2_RX_SIZE + IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2 (1) @@ -62,9 +62,9 @@ /* channel 3 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN3) -# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_RX_SIZE) -# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN3) +# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32_IPCC_CHAN3_RX_SIZE) +# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32_IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3_START (IPCC_CHAN2_START + IPCC_CHAN2_SIZE) # define IPCC_CHAN3_SIZE (IPCC_CHAN3_RX_SIZE + IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3 (1) @@ -75,9 +75,9 @@ /* channel 4 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN4) -# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_RX_SIZE) -# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN4) +# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32_IPCC_CHAN4_RX_SIZE) +# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32_IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4_START (IPCC_CHAN3_START + IPCC_CHAN3_SIZE) # define IPCC_CHAN4_SIZE (IPCC_CHAN4_RX_SIZE + IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4 (1) @@ -88,9 +88,9 @@ /* channel 5 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN5) -# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_RX_SIZE) -# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN5) +# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32_IPCC_CHAN5_RX_SIZE) +# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32_IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5_START (IPCC_CHAN4_START + IPCC_CHAN4_SIZE) # define IPCC_CHAN5_SIZE (IPCC_CHAN5_RX_SIZE + IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5 (1) @@ -101,9 +101,9 @@ /* channel 6 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN6) -# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_RX_SIZE) -# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN6) +# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32_IPCC_CHAN6_RX_SIZE) +# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32_IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6_START (IPCC_CHAN5_START + IPCC_CHAN5_SIZE) # define IPCC_CHAN6_SIZE (IPCC_CHAN6_RX_SIZE + IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6 (1) @@ -135,7 +135,7 @@ * of SRAM2. SRAM2 region will be right after IPCC reserved memory */ -#define IPCC_START STM32WL5_SRAM2_BASE +#define IPCC_START STM32_SRAM2_BASE #define IPCC_NCHAN (IPCC_CHAN1 + IPCC_CHAN2 + IPCC_CHAN3 + \ IPCC_CHAN4 + IPCC_CHAN5 + IPCC_CHAN6) #define IPCC_END (IPCC_START + IPCC_CHAN1_SIZE + IPCC_CHAN2_SIZE + \ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index 8e953adb2500f..b0b25e844bce9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -202,13 +202,13 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WL5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WL5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -218,19 +218,19 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WL5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WL5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WL5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WL5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -260,7 +260,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WL5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -314,13 +314,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WL5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WL5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WL5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -330,23 +330,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WL5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WL5_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WL5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WL5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WL5_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WL5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WL5_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL); #endif stm32wl5_dumpnvic("initial", NR_IRQS); @@ -382,7 +382,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -417,7 +417,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -460,10 +460,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WL5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WL5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -476,7 +476,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WL5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 06a47209fc635..474315559282d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -47,70 +47,70 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR -# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART1_TX -# define STM32WL5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART2_TX -# define STM32WL5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WL5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WL5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -118,9 +118,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -136,7 +136,7 @@ /* CR2 settings */ -# if STM32WL5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -178,24 +178,24 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WL5_USARTDIV8 \ - (((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) -# define STM32WL5_USARTDIV16 \ - ((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) /* lpuart has different formula for baud rate than normal uart */ -# define STM32WL5_BRR_VALUE \ - (((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK) +# define STM32_BRR_VALUE \ + (((256ull * STM32_APBCLOCK) / STM32_CONSOLE_BAUD) & LPUART_BRR_MASK) # else /* CONFIG_LPUART1_SERIAL_CONSOLE */ -# if STM32WL5_USARTDIV8 > 2000 -# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WL5_BRR_VALUE \ - ((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -238,22 +238,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WL5_CONSOLE_RS485_DIR - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -279,7 +279,7 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -288,17 +288,17 @@ void stm32wl5_lowsetup(void) * stm32wl5_rcc.c */ -#ifdef STM32WL5_CONSOLE_TX - stm32wl5_configgpio(STM32WL5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wl5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WL5_CONSOLE_RX - stm32wl5_configgpio(STM32WL5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wl5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -306,42 +306,42 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WL5_BRR_VALUE, - STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h index 3ab795bc58ca6..144d1b952985b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32wl5_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 5abad5f93ab6c..b888f633ed9d6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -43,9 +43,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -54,7 +54,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -81,7 +81,7 @@ void stm32wl5_rcc_enablelse(void) int writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -89,7 +89,7 @@ void stm32wl5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -109,28 +109,28 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -139,7 +139,7 @@ void stm32wl5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -149,7 +149,7 @@ void stm32wl5_rcc_enablelse(void) } } -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -167,24 +167,24 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32WL5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32wl5_waste(); } } -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index ea4495ddbd664..5b5b36395dfd6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -46,11 +46,11 @@ void stm32wl5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WL5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32wl5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h index 46968b5add0b2..3d905a8597f3e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32wl5_mpu_uheap(uintptr_t start, size_t size); # define stm32wl5_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index e1a1644ed5631..1e0fa17138968 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -42,18 +42,18 @@ static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WL5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WL5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WL5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -83,7 +83,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32WL5_PWR_CR1_OFFSET); + regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -121,5 +121,5 @@ bool stm32wl5_pwr_enablebkp(bool writable) void stm32wl5_pwr_boot_c2(void) { - modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT); + modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/stm32wl5_pwr.h index 7ad5243285396..7d0d4176c86ff 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ void stm32wl5_pwr_boot_c2(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_PWR_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 571ea43fc7fd7..d24b20e16d330 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -74,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void stm32wl5_rcc_resetbkp(void) { bool init_stat; @@ -84,14 +84,14 @@ static inline void stm32wl5_rcc_resetbkp(void) init_stat = stm32wl5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WL5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WL5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -104,19 +104,19 @@ static inline void stm32wl5_rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WL5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WL5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32WL5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32WL5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } (void)stm32wl5_pwr_enablebkp(false); @@ -139,7 +139,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wl5_board_clockconfig(). * @@ -162,7 +162,7 @@ void stm32wl5_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -199,27 +199,27 @@ static void stm32wl5_rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WL5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WL5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WL5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -238,25 +238,25 @@ static inline void stm32wl5_rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32WL5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32WL5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32WL5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32WL5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIOHEN #endif ); -#endif /* STM32WL5_NPORTS */ +#endif /* STM32_NPORTS */ - putreg32(regval, STM32WL5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -275,33 +275,33 @@ static inline void stm32wl5_rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WL5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32WL5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32WL5_FLASHEN +#ifdef CONFIG_STM32_FLASHEN /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; #endif -#ifdef CONFIG_STM32WL5_IPCC +#ifdef CONFIG_STM32_IPCC /* IPCC interface clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -320,81 +320,81 @@ static inline void stm32wl5_rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WL5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WL5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32WL5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#if defined (CONFIG_STM32WL5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WL5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WL5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -413,45 +413,45 @@ static inline void stm32wl5_rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WL5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif - putreg32(regval, STM32WL5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -471,42 +471,42 @@ static inline void stm32wl5_rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WL5_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WL5_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C1 +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32WL5_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WL5_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WL5_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ - regval |= STM32WL5_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32WL5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -518,19 +518,19 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32WL5_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32WL5_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C4 - regval = getreg32(STM32WL5_RCC_CCIPR2); +#if defined(STM32_I2C_USE_HSI16) +#ifdef CONFIG_STM32_I2C4 + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval |= RCC_CCIPR_I2C4SEL_HSI; - putreg32(regval, STM32WL5_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -548,7 +548,7 @@ static inline void stm32wl5_rcc_enableccip(void) * stm32wl5_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wl5_board_clockconfig(). * @@ -563,7 +563,7 @@ static inline void stm32wl5_rcc_enableccip(void) #ifdef CONFIG_PM void stm32wl5_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -605,17 +605,17 @@ void stm32wl5_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32wl5_stdclockconfig(void) { uint32_t regval; -#if defined(STM32WL5_BOARD_USEHSI) || defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ @@ -623,7 +623,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out */ @@ -632,17 +632,17 @@ void stm32wl5_stdclockconfig(void) } #endif -#if defined(STM32WL5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready */ for (; ; ) { - if ((regval = getreg32(STM32WL5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out */ @@ -653,9 +653,9 @@ void stm32wl5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32WL5_RCC_CR); - regval |= (STM32WL5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready */ @@ -663,7 +663,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out */ @@ -671,23 +671,23 @@ void stm32wl5_stdclockconfig(void) } } -#elif defined(STM32WL5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ -#if defined(STM32WL5_BOARD_USETCXO) +#if defined(STM32_BOARD_USETCXO) /* nucleo-wl55jc uses TCXO crystal, which needs to be first * powered up with PB0 pin - or more conveniently by setting * HSEBYPPWR register. This has to be done before HSE is enabled */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEBYPPWR; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); #endif - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready */ @@ -695,7 +695,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out */ @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32WL5_BOARD_USEHSI, STM32WL5_BOARD_USEMSI, STM32WL5_BOARD_USEHSE defined +# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -714,10 +714,10 @@ void stm32wl5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32WL5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32WL5_SYSCLK_FREQUENCY <= 16000000) + if (STM32_SYSCLK_FREQUENCY <= 16000000) { /* set low power range for frequencies <= 16MHz */ @@ -730,126 +730,126 @@ void stm32wl5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE1; } - putreg32(regval, STM32WL5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32WL5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WL5_RCC_CFGR_HPRE; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE2; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE1; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32WL5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32WL5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32WL5_PLLCFG_PLLM | STM32WL5_PLLCFG_PLLN | - STM32WL5_PLLCFG_PLLP | STM32WL5_PLLCFG_PLLQ | - STM32WL5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32WL5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32WL5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32WL5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WL5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32WL5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WL5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WL5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WL5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure flash wait states according to manual */ - if (STM32WL5_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) + if (STM32_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) { regval = FLASH_ACR_LATENCY_0; } - else if (STM32WL5_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) + else if (STM32_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) { regval = FLASH_ACR_LATENCY_1; } - else /* STM32WL5_HCLK3_FREQUENCY <= 48MHz */ + else /* STM32_HCLK3_FREQUENCY <= 48MHz */ { regval = FLASH_ACR_LATENCY_2; } - putreg32(regval, STM32WL5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WL5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32wl5_rcc_enablelsi(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 1989f237afd61..ca5f15e5ece4e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H /**************************************************************************** * Included Files @@ -77,10 +77,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** @@ -96,7 +96,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wl5_board_clockconfig(). * @@ -119,7 +119,7 @@ void stm32wl5_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32wl5_board_clockconfig(void); #endif @@ -134,7 +134,7 @@ void stm32wl5_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32wl5_stdclockconfig(void); #endif @@ -151,7 +151,7 @@ void stm32wl5_stdclockconfig(void); * stm32wl5_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32wl5_board_clockconfig(). * @@ -220,4 +220,4 @@ void stm32wl5_rcc_enableperipherals(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_RCC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 524483ef5cbe1..a4b7992e24885 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -82,8 +82,8 @@ */ # if defined(CONFIG_USART2_RXDMA) -# if !defined(CONFIG_STM32WL5_DMA1) && !defined(CONFIG_STM32WL5_DMAMUX) -# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32WL5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -98,7 +98,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32WL5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # endif @@ -116,11 +116,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -152,8 +152,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WL5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WL5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -170,7 +170,7 @@ * See stm32wl5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -366,7 +366,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -374,7 +374,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -382,7 +382,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -392,7 +392,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32wl5_serial_s g_lpuart1priv = { .dev = @@ -418,13 +418,13 @@ static struct stm32wl5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WL5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_LPUART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -452,7 +452,7 @@ static struct stm32wl5_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32wl5_serial_s g_usart1priv = { .dev = @@ -478,13 +478,13 @@ static struct stm32wl5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WL5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -514,7 +514,7 @@ static struct stm32wl5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32wl5_serial_s g_usart2priv = { .dev = @@ -540,13 +540,13 @@ static struct stm32wl5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32WL5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32WL5_PCLK1_FREQUENCY, - .usartbase = STM32WL5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -577,15 +577,15 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wl5_serial_s * const - g_uart_devs[STM32WL5_NLPUART + STM32WL5_NUSART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif }; @@ -647,15 +647,15 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * above) */ - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -710,8 +710,8 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - cr3 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -772,7 +772,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; - if (priv->usartbase == STM32WL5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* lpuart has different calculations baudrate, and there is not * oversampling: @@ -804,7 +804,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * But what is small? */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { /* Use usartdiv16 */ @@ -828,14 +828,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); } - stm32wl5serial_putreg(priv, STM32WL5_USART_BRR_OFFSET, brr); + stm32wl5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); /* Configure parity mode */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -873,11 +873,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -885,14 +885,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -906,7 +906,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -951,7 +951,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + while ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1057,7 +1057,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -1096,22 +1096,22 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER - case STM32WL5_LPUART1_BASE: +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WL5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER - case STM32WL5_USART1_BASE: +#ifdef CONFIG_STM32_USART1_SERIALDRIVER + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WL5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER - case STM32WL5_USART2_BASE: +#ifdef CONFIG_STM32_USART2_SERIALDRIVER + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32WL5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1177,7 +1177,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WL5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1198,7 +1198,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1209,26 +1209,26 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1236,9 +1236,9 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1291,7 +1291,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1302,7 +1302,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1316,9 +1316,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1376,9 +1376,9 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1529,8 +1529,8 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WL5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WL5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1544,7 +1544,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Get the masked USART status word. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1612,7 +1612,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, * interrupt clear register (ICR). */ - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1674,7 +1674,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WL5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1685,19 +1685,19 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1742,17 +1742,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WL5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1763,17 +1763,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1793,17 +1793,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; #endif -#ifdef CONFIG_STM32WL5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1814,17 +1814,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1835,11 +1835,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1940,8 +1940,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WL5_USART_BREAKS -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1996,8 +1996,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2009,8 +2009,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2046,7 +2046,7 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wl5serial_getreg(priv, STM32WL5_USART_RDR_OFFSET); + rdr = stm32wl5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2133,7 +2133,7 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2169,7 +2169,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32wl5_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2296,7 +2296,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2307,7 +2307,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2476,7 +2476,7 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_TDR_OFFSET, (uint32_t)ch); + stm32wl5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2521,7 +2521,7 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2561,7 +2561,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2603,11 +2603,11 @@ static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2743,7 +2743,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -2813,7 +2813,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2862,7 +2862,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2882,7 +2882,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ @@ -2891,7 +2891,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 3aa45fe20c4f2..11152797cb9a9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -69,12 +69,12 @@ #include "chip.h" #include "stm32wl5.h" #include "stm32wl5_gpio.h" -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32wl5_dma.h" #endif #include "stm32wl5_spi.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -83,34 +83,34 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # error "DMA driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WL5_SPI_INTERRUPTS) && defined(CONFIG_STM32WL5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# elif defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1 +# elif defined(CONFIG_STM32_STM32WL5XXX_CPU1 #warning "Verify, read doc and Implement" # define SPI_DMA_PRIO DMA_CCR_PRIMED # else # error "Unknown STM32WL5 DMA" # endif -# if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +# if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -120,7 +120,7 @@ /* DMA channel configuration */ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) @@ -137,15 +137,15 @@ # define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK) # define SPIDMA_BUF_ALIGN aligned_data(4) -# if defined(CONFIG_STM32WL5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI2S2_DMA_BUFFER > 0 -# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2S2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2S2_DMA_BUFFER > 0 +# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2S2_DMA_BUFFER) # define SPI2S2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,10 +160,10 @@ struct stm32wl5_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -216,7 +216,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32wl5_spidev_s *priv); static int spi_dmatxwait(struct stm32wl5_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv); @@ -273,7 +273,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -316,13 +316,13 @@ static struct stm32wl5_spidev_s g_spi1dev = { .ops = &g_sp1iops, }, - .spibase = STM32WL5_SPI1_BASE, - .spiclock = STM32WL5_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI1, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, #if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -341,7 +341,7 @@ static struct stm32wl5_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -386,13 +386,13 @@ static struct stm32wl5_spidev_s g_spi2s2dev = { &g_sp2iops }, - .spibase = STM32WL5_SPI2S2_BASE, - .spiclock = STM32WL5_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI2S2, + .spibase = STM32_SPI2S2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, +#ifdef CONFIG_STM32_SPI_INTERRUPTS + .spiirq = STM32_IRQ_SPI2S2, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI2S2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2S2_DMA .rxch = DMACHAN_SPI2S2_RX, .txch = DMACHAN_SPI2S2_TX, #if defined(SPI2S2_DMABUFSIZE_ADJUSTED) @@ -518,7 +518,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) { } @@ -539,11 +539,11 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) if (priv->nbits < 9) { - return (uint16_t)spi_getreg8(priv, STM32WL5_SPI_DR_OFFSET); + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); } else { - return spi_getreg(priv, STM32WL5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } } @@ -568,7 +568,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) { } @@ -576,11 +576,11 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, if (priv->nbits < 9) { - spi_putreg8(priv, STM32WL5_SPI_DR_OFFSET, (uint8_t)word); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); } else { - spi_putreg(priv, STM32WL5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } } @@ -592,7 +592,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) { int ret; @@ -625,7 +625,7 @@ static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) { int ret; @@ -658,7 +658,7 @@ static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -673,7 +673,7 @@ static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -688,7 +688,7 @@ static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; @@ -708,7 +708,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; @@ -728,7 +728,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -779,7 +779,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -830,7 +830,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) { priv->rxresult = 0; @@ -846,7 +846,7 @@ static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) { priv->txresult = 0; @@ -875,12 +875,12 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, uint16_t clrbits) { uint16_t cr1; - cr1 = spi_getreg(priv, STM32WL5_SPI_CR1_OFFSET); + cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); cr1 &= ~clrbits; cr1 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR1_OFFSET, cr1); + spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); - spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR1_OFFSET, + spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR1_OFFSET, cr1); } @@ -904,11 +904,11 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; - cr2 = spi_getreg(priv, STM32WL5_SPI_CR2_OFFSET); + cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); cr2 &= ~clrbits; cr2 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR2_OFFSET, cr2); - spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR2_OFFSET, + spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); + spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR2_OFFSET, cr2); } @@ -1314,7 +1314,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * (Reading from the SR clears the error flags) */ - regval = spi_getreg(priv, STM32WL5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", wd, ret, regval); @@ -1348,9 +1348,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WL5_SPI_DMA) || defined(CONFIG_STM32WL5_DMACAPABLE) || \ - defined(CONFIG_STM32WL5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32WL5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1433,7 +1433,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WL5_SPI_DMA || CONFIG_STM32WL5_DMACAPABLE || CONFIG_STM32WL5_SPI_DMATHRESHOLD */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1456,7 +1456,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1470,12 +1470,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32WL5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32WL5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1493,7 +1493,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32WL5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && priv->txbuf == NULL && !stm32wl5_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && priv->rxbuf == NULL && @@ -1580,7 +1580,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WL5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1601,7 +1601,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; if (!priv->trigarmed) @@ -1731,9 +1731,9 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign @@ -1788,7 +1788,7 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1813,7 +1813,7 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 if (bus == 2) { /* Select SPI2S2 */ @@ -1846,4 +1846,4 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.h b/arch/arm/src/stm32wl5/stm32wl5_spi.h index 17071c7fa3268..76e994a6abb6f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H /**************************************************************************** * Included Files @@ -107,14 +107,14 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid); @@ -142,12 +142,12 @@ int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32wl5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 int stm32wl5_spi2s2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); @@ -160,4 +160,4 @@ int stm32wl5_spi2s2register(struct spi_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_SPI_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index e828fca974eda..0fe20a8d81b7c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -60,8 +60,8 @@ * 0x2000:8000 - Start of internal SRAM2 */ -#define SRAM2_START STM32WL5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) @@ -133,7 +133,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32WL5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.h b/arch/arm/src/stm32wl5/stm32wl5_start.h index b36f7600b6094..0463fd2c8d99b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.h +++ b/arch/arm/src/stm32wl5/stm32wl5_start.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_START_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_START_H /**************************************************************************** * Included Files @@ -44,4 +44,4 @@ void stm32wl5_board_initialize(void); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_START_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 7be699ed8f7fb..2c6e4a68d3eea 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -55,137 +55,137 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32WL5_TIMn is defined then the CONFIG_STM32WL5_TIMn_PWM may + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may * also be defined to indicate that the timer is intended to be used for * pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32WL5_TIMn is - * defined then CONFIG_STM32WL5_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32WL5_TIMn is defined - * then CONFIG_STM32WL5_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32WL5_TIMn is defined then - * CONFIG_STM32WL5_TIMn_QE may also be defined to indicate that timer "n" + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" * is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WL5_TIM1_PWM) || defined (CONFIG_STM32WL5_TIM1_ADC) || \ - defined(CONFIG_STM32WL5_TIM1_DAC) || defined(CONFIG_STM32WL5_TIM1_QE) -# undef CONFIG_STM32WL5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WL5_TIM2_PWM) || defined (CONFIG_STM32WL5_TIM2_ADC) || \ - defined(CONFIG_STM32WL5_TIM2_DAC) || defined(CONFIG_STM32WL5_TIM2_QE) -# undef CONFIG_STM32WL5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WL5_TIM3_PWM) || defined (CONFIG_STM32WL5_TIM3_ADC) || \ - defined(CONFIG_STM32WL5_TIM3_DAC) || defined(CONFIG_STM32WL5_TIM3_QE) -# undef CONFIG_STM32WL5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32WL5_TIM4_PWM) || defined (CONFIG_STM32WL5_TIM4_ADC) || \ - defined(CONFIG_STM32WL5_TIM4_DAC) || defined(CONFIG_STM32WL5_TIM4_QE) -# undef CONFIG_STM32WL5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32WL5_TIM5_PWM) || defined (CONFIG_STM32WL5_TIM5_ADC) || \ - defined(CONFIG_STM32WL5_TIM5_DAC) || defined(CONFIG_STM32WL5_TIM5_QE) -# undef CONFIG_STM32WL5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32WL5_TIM6_ADC) || \ - defined(CONFIG_STM32WL5_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE) -# undef CONFIG_STM32WL5_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32WL5_TIM7_PWM) || defined (CONFIG_STM32WL5_TIM7_ADC) || \ - defined(CONFIG_STM32WL5_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE) -# undef CONFIG_STM32WL5_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32WL5_TIM8_PWM) || defined (CONFIG_STM32WL5_TIM8_ADC) || \ - defined(CONFIG_STM32WL5_TIM8_DAC) || defined(CONFIG_STM32WL5_TIM8_QE) -# undef CONFIG_STM32WL5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32WL5_TIM15_PWM) || defined (CONFIG_STM32WL5_TIM15_ADC) || \ - defined(CONFIG_STM32WL5_TIM15_DAC) || defined(CONFIG_STM32WL5_TIM15_QE) -# undef CONFIG_STM32WL5_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32WL5_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \ - defined(CONFIG_STM32WL5_TIM16_DAC) || defined(CONFIG_STM32WL5_TIM16_QE) -# undef CONFIG_STM32WL5_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WL5_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \ - defined(CONFIG_STM32WL5_TIM17_DAC) || defined(CONFIG_STM32WL5_TIM17_QE) -# undef CONFIG_STM32WL5_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WL5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -196,12 +196,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -302,101 +302,101 @@ static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = .checkint = stm32wl5_tim_checkint, }; -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -484,9 +484,9 @@ static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_EGR_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32WL5_GTIM_EGR_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -495,10 +495,10 @@ static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -507,9 +507,9 @@ static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -523,7 +523,7 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_DISABLED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wl5_tim_disable(dev); } @@ -541,7 +541,7 @@ static void stm32wl5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32WL5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wl5_configgpio(cfg); } @@ -567,13 +567,13 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -582,19 +582,19 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WL5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WL5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WL5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32WL5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32WL5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -603,7 +603,7 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, break; - case STM32WL5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -612,15 +612,15 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32WL5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM8_BASE) + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32WL5_ATIM_BDTR_OFFSET, + stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -656,67 +656,67 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -747,7 +747,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32WL5_GTIM_PSC_OFFSET, prescaler); + stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32wl5_tim_enable(dev); return prescaler; @@ -771,65 +771,65 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -839,7 +839,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32WL5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -851,7 +851,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32WL5_GTIM_ARR_OFFSET, period); + stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -861,7 +861,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32WL5_GTIM_ARR_OFFSET); + return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -871,20 +871,20 @@ static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32WL5_GTIM_CNT_OFFSET); + uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32WL5_TIM2) || defined(CONFIG_STM32WL5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: #endif return counter; @@ -908,7 +908,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WL5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CCER_OFFSET); + ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -929,13 +929,13 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -944,12 +944,12 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32WL5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WL5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WL5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -961,7 +961,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WL5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -976,21 +976,21 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32WL5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CCER_OFFSET, ccer_val); + stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1022,8 +1022,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1055,8 +1055,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1088,8 +1088,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1120,8 +1120,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1153,8 +1153,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1186,8 +1186,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1219,8 +1219,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1252,8 +1252,8 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR1_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR2_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR3_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR4_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1339,16 +1339,16 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR1_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR2_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR3_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR4_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1368,67 +1368,67 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - vectorno = STM32WL5_IRQ_TIM1UP; +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - vectorno = STM32WL5_IRQ_TIM2; +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - vectorno = STM32WL5_IRQ_TIM3; +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - vectorno = STM32WL5_IRQ_TIM4; +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - vectorno = STM32WL5_IRQ_TIM5; +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - vectorno = STM32WL5_IRQ_TIM6; +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - vectorno = STM32WL5_IRQ_TIM7; +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - vectorno = STM32WL5_IRQ_TIM8UP; +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - vectorno = STM32WL5_IRQ_TIM15; +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - vectorno = STM32WL5_IRQ_TIM16; +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - vectorno = STM32WL5_IRQ_TIM17; +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1461,7 +1461,7 @@ static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1472,7 +1472,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1481,7 +1481,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32WL5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1491,7 +1491,7 @@ static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32WL5_GTIM_SR_OFFSET); + uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1511,79 +1511,79 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,7 +1593,7 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32WL5_TIM_MODE_UNUSED) + if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1618,68 +1618,68 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1689,9 +1689,9 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_UNUSED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } -#endif /* defined(CONFIG_STM32WL5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 9826600b87ab0..50a48d7e25204 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H /**************************************************************************** * Included Files @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32WL5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WL5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WL5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WL5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WL5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WL5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WL5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WL5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WL5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WL5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WL5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WL5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WL5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WL5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32wl5_tim_dev_s enum stm32wl5_tim_mode_e { - STM32WL5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WL5_TIM_MODE_MASK = 0x0310, - STM32WL5_TIM_MODE_DISABLED = 0x0000, - STM32WL5_TIM_MODE_UP = 0x0100, - STM32WL5_TIM_MODE_DOWN = 0x0110, - STM32WL5_TIM_MODE_UPDOWN = 0x0200, - STM32WL5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WL5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WL5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WL5_TIM_MODE_CK_EXT = 0x0800, - STM32WL5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WL5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WL5_TIM_MODE_CK_CH1 = 0x0001, - STM32WL5_TIM_MODE_CK_CH2 = 0x0002, - STM32WL5_TIM_MODE_CK_CH3 = 0x0003, - STM32WL5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32wl5_tim_mode_e enum stm32wl5_tim_channel_e { - STM32WL5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WL5_TIM_CH_POLARITY_POS = 0x00, - STM32WL5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WL5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WL5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32WL5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif }; @@ -211,4 +211,4 @@ int stm32wl5_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_TIM_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 572c4c95c218c..7403d50314f19 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -41,28 +41,28 @@ #include "stm32wl5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_TIM1_RES 16 -#define STM32WL5_TIM2_RES 32 -#define STM32WL5_TIM3_RES 16 -#define STM32WL5_TIM4_RES 16 -#define STM32WL5_TIM5_RES 32 -#define STM32WL5_TIM6_RES 16 -#define STM32WL5_TIM7_RES 16 -#define STM32WL5_TIM8_RES 16 -#define STM32WL5_TIM15_RES 16 -#define STM32WL5_TIM16_RES 16 -#define STM32WL5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -118,91 +118,91 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) (struct stm32wl5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WL5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WL5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_DISABLED); - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WL5_TIM_GETCLOCK(priv->tim); - period = STM32WL5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32WL5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WL5_TIM_SETCLOCK(priv->tim, freq); - STM32WL5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WL5_TIM_SETCLOCK(priv->tim, 1000000); - STM32WL5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); @@ -503,66 +503,66 @@ int stm32wl5_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index c4238fbf26827..611bcfd63e105 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -59,12 +59,12 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WL5_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -124,7 +124,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -147,5 +147,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WL5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_uart.h b/arch/arm/src/stm32wl5/stm32wl5_uart.h index 8abf47c83c574..ff12c5ec571f9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uart.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H -#define __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_UART_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_UART_H /**************************************************************************** * Included Files @@ -42,42 +42,42 @@ * device. */ -#if !defined(CONFIG_STM32WL5_HAVE_USART2) -# undef CONFIG_STM32WL5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32WL5_HAVE_USART1) -# undef CONFIG_STM32WL5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32WL5_HAVE_LPUART1) -# undef CONFIG_STM32WL5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32WL5_LPUART1) -# undef CONFIG_STM32WL5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WL5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART1) -# undef CONFIG_STM32WL5_USART1_SERIALDRIVER -# undef CONFIG_STM32WL5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART2) -# undef CONFIG_STM32WL5_USART2_SERIALDRIVER -# undef CONFIG_STM32WL5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WL5_LPUART1) || \ - defined(CONFIG_STM32WL5_USART1) || \ - defined(CONFIG_STM32WL5_USART2) +#if defined(CONFIG_STM32_LPUART1) || \ + defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -85,7 +85,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -93,7 +93,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -121,15 +121,15 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif @@ -156,11 +156,11 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif @@ -224,4 +224,4 @@ void stm32wl5_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32WL5_STM32WL5_UART_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_UART_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c index b8fa93730bf10..311458d7adb11 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32wl5_memorymap.h" #include "stm32wl5_uid.h" -#ifdef STM32WL5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WL5_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32WL5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.h b/arch/arm/src/stm32wl5/stm32wl5_uid.h index 6992f84b9c3ee..f88b8f2b2d6f6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.h @@ -35,8 +35,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_UID_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_UID_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ void stm32wl5_get_uniqueid(uint8_t uniqueid[12]); -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_UID_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.h b/arch/arm/src/stm32wl5/stm32wl5_userspace.h index 3ca2fdf521c6e..b304b90d5bcbe 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.h +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ void stm32wl5_userspace(void); #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.h b/arch/arm/src/stm32wl5/stm32wl5_waste.h index 348469b498213..f4f3beaa2794f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.h +++ b/arch/arm/src/stm32wl5/stm32wl5_waste.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H -#define __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H +#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H +#define __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H /* Waste CPU Time */ @@ -62,4 +62,4 @@ void stm32wl5_waste(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_WASTE_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_bh1750.h b/boards/arm/stm32f7/common/include/stm32_bh1750.h index 0b2dd373d22e8..486468d9a0a02 100644 --- a/boards/arm/stm32f7/common/include/stm32_bh1750.h +++ b/boards/arm/stm32f7/common/include/stm32_bh1750.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bh1750_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BH1750_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_bmi270.h b/boards/arm/stm32f7/common/include/stm32_bmi270.h index 50d4be70ae763..6873857d8729f 100644 --- a/boards/arm/stm32f7/common/include/stm32_bmi270.h +++ b/boards/arm/stm32f7/common/include/stm32_bmi270.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bmi270_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_BMI270_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_can_setup.h b/boards/arm/stm32f7/common/include/stm32_can_setup.h index 5361bfe204abe..1f43512e3e0a0 100644 --- a/boards/arm/stm32f7/common/include/stm32_can_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_can_setup.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ extern "C" * Name: stm32_can_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER int stm32_can_setup(void); #endif @@ -70,4 +70,4 @@ int stm32_can_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CAN_SETUP_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h index 971f2216dcbe2..c902ac7ea45b7 100644 --- a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ extern "C" * Name: stm32_cansock_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET int stm32_cansock_setup(void); #endif @@ -70,4 +70,4 @@ int stm32_cansock_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cs4344.h b/boards/arm/stm32f7/common/include/stm32_cs4344.h index 5050fb7345f11..aab46ba3c5103 100644 --- a/boards/arm/stm32f7/common/include/stm32_cs4344.h +++ b/boards/arm/stm32f7/common/include/stm32_cs4344.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H /**************************************************************************** * Included Files @@ -81,4 +81,4 @@ int board_cs4344_initialize(int devno, int port); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_romfs.h b/boards/arm/stm32f7/common/include/stm32_romfs.h index 3b52acfa36fa5..d07d56ef2b3e6 100644 --- a/boards/arm/stm32f7/common/include/stm32_romfs.h +++ b/boards/arm/stm32f7/common/include/stm32_romfs.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H /**************************************************************************** * Included Files @@ -43,7 +43,7 @@ #include -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /**************************************************************************** * Pre-processor Definitions @@ -72,6 +72,6 @@ int stm32_romfs_initialize(void); -#endif /* CONFIG_STM32F7_ROMFS */ +#endif /* CONFIG_STM32_ROMFS */ -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/stm32f7/common/include/stm32_spitest.h index 09605759e1e0b..326c2cc04d0f8 100644 --- a/boards/arm/stm32f7/common/include/stm32_spitest.h +++ b/boards/arm/stm32f7/common/include/stm32_spitest.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H -#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H /**************************************************************************** * Included Files @@ -62,7 +62,7 @@ extern "C" * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ @@ -73,4 +73,4 @@ int stm32_spidev_bus_test(void); } #endif -#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_SPITEST_H */ +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H */ diff --git a/boards/arm/stm32f7/common/src/stm32_can_setup.c b/boards/arm/stm32f7/common/src/stm32_can_setup.c index 5f62d6da00f17..2eedf06992ea8 100644 --- a/boards/arm/stm32f7/common/src/stm32_can_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_can_setup.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #else # define CAN_PORT 2 @@ -60,7 +60,7 @@ int stm32_can_setup(void) { -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) struct can_dev_s *can; int ret; @@ -85,7 +85,7 @@ int stm32_can_setup(void) return OK; #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c index 2bb60d2b8bc21..58dbf738cfe70 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c @@ -36,7 +36,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2) +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) # error "No CAN is enable. Please enable at least one CAN device" #endif @@ -58,7 +58,7 @@ int stm32_cansock_setup(void) UNUSED(ret); -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(1); @@ -69,7 +69,7 @@ int stm32_cansock_setup(void) } #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(2); diff --git a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c index 53fe0927d43ba..1d105e29b0e09 100644 --- a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c @@ -54,20 +54,20 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_ROMFS -# error "CONFIG_STM32F7_ROMFS must be defined" +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_IMAGEFILE -# error "CONFIG_STM32F7_ROMFS_IMAGEFILE must be defined" +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_DEV_MINOR -# error "CONFIG_STM32F7_ROMFS_DEV_MINOR must be defined" +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_MOUNTPOINT -# error "CONFIG_STM32F7_ROMFS_MOUNTPOINT must be defined" +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" #endif #define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) @@ -76,7 +76,7 @@ #define STR(m) STR2(m) #define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32F7_ROMFS_DEV_MINOR) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) /**************************************************************************** * Private Data @@ -87,7 +87,7 @@ __asm__ ( ".balign 16\n" ".globl romfs_data_begin\n" "romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32F7_ROMFS_IMAGEFILE) "\n"\ + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ \ ".balign " STR(ROMFS_SECTOR_SIZE) "\n" ".globl romfs_data_end\n" @@ -125,7 +125,7 @@ int stm32_romfs_initialize(void) romfs_data_len = romfs_data_end - romfs_data_begin; - ret = romdisk_register(CONFIG_STM32F7_ROMFS_DEV_MINOR, romfs_data_begin, + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); if (ret < 0) { @@ -136,14 +136,14 @@ int stm32_romfs_initialize(void) /* Mount the file system */ finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, "romfs", MS_RDONLY, NULL); if (ret < 0) { ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); return ret; } diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index f82b9b8fe645e..ccdffbcbc11b3 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -43,45 +43,45 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1_TEST) -# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3) -# define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 +#if defined(CONFIG_STM32_SPI1_TEST) +# if defined(CONFIG_STM32_SPI1_TEST_MODE0) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE1) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE2) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI1_TEST_MODE3) +# define CONFIG_STM32_SPI1_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI1_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) -# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3) -# define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 +#if defined(CONFIG_STM32_SPI2_TEST) +# if defined(CONFIG_STM32_SPI2_TEST_MODE0) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE1) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE2) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI2_TEST_MODE3) +# define CONFIG_STM32_SPI2_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI2_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) -# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3) -# define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 +#if defined(CONFIG_STM32_SPI3_TEST) +# if defined(CONFIG_STM32_SPI3_TEST_MODE0) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE1) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE2) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_STM32_SPI3_TEST_MODE3) +# define CONFIG_STM32_SPI3_TEST_MODE SPIDEV_MODE3 # else -# error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" +# error "No CONFIG_STM32_SPI3_TEST_MODEx defined" # endif #endif @@ -89,13 +89,13 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) struct spi_dev_s *g_spi1; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) struct spi_dev_s *g_spi2; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) struct spi_dev_s *g_spi3; #endif @@ -108,7 +108,7 @@ struct spi_dev_s *g_spi3; * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ @@ -116,9 +116,9 @@ int stm32_spidev_bus_test(void) { /* Configure and test SPI- */ - uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE; + uint8_t *tx = (uint8_t *)CONFIG_STM32_SPI_TEST_MESSAGE; -#if defined(CONFIG_STM32F7_SPI1_TEST) +#if defined(CONFIG_STM32_SPI1_TEST) g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) @@ -127,16 +127,16 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ + /* Default SPI1 to STM32_SPI1_FREQ and mode */ - SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); - SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); - SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); + SPI_SETFREQUENCY(g_spi1, CONFIG_STM32_SPI1_TEST_FREQ); + SPI_SETBITS(g_spi1, CONFIG_STM32_SPI1_TEST_BITS); + SPI_SETMODE(g_spi1, CONFIG_STM32_SPI1_TEST_MODE); SPI_EXCHANGE(g_spi1, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) +#if defined(CONFIG_STM32_SPI2_TEST) g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) @@ -145,16 +145,16 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ + /* Default SPI2 to STM32_SPI2_FREQ and mode */ - SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); - SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); - SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); + SPI_SETFREQUENCY(g_spi2, CONFIG_STM32_SPI2_TEST_FREQ); + SPI_SETBITS(g_spi2, CONFIG_STM32_SPI2_TEST_BITS); + SPI_SETMODE(g_spi2, CONFIG_STM32_SPI2_TEST_MODE); SPI_EXCHANGE(g_spi2, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) +#if defined(CONFIG_STM32_SPI3_TEST) g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) @@ -163,13 +163,13 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ + /* Default SPI3 to STM32_SPI3_FREQ and mode */ - SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); - SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); - SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); + SPI_SETFREQUENCY(g_spi3, CONFIG_STM32_SPI3_TEST_FREQ); + SPI_SETBITS(g_spi3, CONFIG_STM32_SPI3_TEST_BITS); + SPI_SETMODE(g_spi3, CONFIG_STM32_SPI3_TEST_MODE); SPI_EXCHANGE(g_spi3, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif return OK; diff --git a/boards/arm/stm32f7/nucleo-f722ze/include/board.h b/boards/arm/stm32f7/nucleo-f722ze/include/board.h index b1094208baea6..ad312ccc4d4aa 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/include/board.h +++ b/boards/arm/stm32f7/nucleo-f722ze/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -567,4 +567,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F722ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 1db1e63552c98..3f71cf026f959 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H +#define __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H /**************************************************************************** * Included Files @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -263,7 +263,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -295,7 +295,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -316,4 +316,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F722ZE_SRC_NUCLEO_F722ZE_H */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 11dab91d01c85..6f66e59090ff3 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index b9a578268f703..2ed57dfe5f35c 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c index 82194ab10bf40..41464d917d5b8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c index 7c848385d0c3a..6339b20c21f21 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c index 2ab163679c5dc..20272a1dac87a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c index 1adc20c2cae70..8614a43c51595 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c index c38a390ca09b7..26f3bf756fd1f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c index 57a304d3a3e64..1a4e5d2f19e4c 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f746zg/include/board.h b/boards/arm/stm32f7/nucleo-f746zg/include/board.h index e2e37b73c08ed..95d61afca086b 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/include/board.h +++ b/boards/arm/stm32f7/nucleo-f746zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -567,4 +567,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F746ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h index a71f98a2c345a..febcb0582abe8 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h +++ b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H +#define __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H /**************************************************************************** * Included Files @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -276,7 +276,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -308,7 +308,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -329,4 +329,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F746ZG_SRC_NUCLEO_F746ZG_H */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 76e270d40d32d..c1f68f2008364 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index e575a7f653d4b..ab415b60f993e 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c index adab9af41bb27..b30ff20886d3a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c index 39d379e5c8dd3..f7cc0a58d8154 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c index bb3c0cfae36b3..983a1bddb5648 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c index a2de94884cc73..8100783be1934 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c index ee391eb04ad6e..417e00c2ae1d3 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c index 1e3c23c0ad729..fe457155c2a08 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f767zi/include/board.h b/boards/arm/stm32f7/nucleo-f767zi/include/board.h index 1dd891145582b..357e8d0129241 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/include/board.h +++ b/boards/arm/stm32f7/nucleo-f767zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -106,7 +106,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) @@ -125,7 +125,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -598,4 +598,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_F767ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F767ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h index 60c9ab458c9a0..84fafbbf8cffd 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h +++ b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H -#define __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H /**************************************************************************** * Included Files @@ -126,7 +126,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -137,7 +137,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -179,9 +179,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -205,11 +205,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -301,7 +301,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -333,7 +333,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif @@ -354,4 +354,4 @@ int stm32_gpio_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_767ZI_SRC_NUCLEO_767ZI_H */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index d8c2ca1239b66..7c871a67cd279 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -48,20 +48,20 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32F7_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32F7_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index d1c7ab99d2d11..f443aaca0aade 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c index c6bf11bbf24da..c6224cb823cda 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c index 4213f82a5a23e..8f705ee31e107 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -112,14 +112,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -154,7 +154,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -167,7 +167,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -203,7 +203,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -215,7 +215,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -227,7 +227,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -239,7 +239,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -253,7 +253,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -262,7 +262,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -270,7 +270,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c index 9ddb493829273..b6619c433102f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c index 800b70d45d06e..9dbd545ea854d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c index 3b19fd2fa6631..788b0c1963c5d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c index 1e4c86e262326..f153ccd2c64e0 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/steval-eth001v1/include/board.h b/boards/arm/stm32f7/steval-eth001v1/include/board.h index cc62976fda671..8b6cb2f790f61 100644 --- a/boards/arm/stm32f7/steval-eth001v1/include/board.h +++ b/boards/arm/stm32f7/steval-eth001v1/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ #define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) /* PA1 */ #define GPIO_TIM2_CH3IN (GPIO_TIM2_CH3IN_1|GPIO_SPEED_50MHz) /* PA2 */ -#endif /* __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_ETH001V1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h index 22026d5156f7f..ffa6fb87c1df1 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h +++ b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H -#define __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H +#ifndef __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H +#define __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H /**************************************************************************** * Included Files @@ -72,7 +72,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC int stm32_foc_setup(void); #endif @@ -90,4 +90,4 @@ int stm32_adc_setup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_ETH001V1_SRC_STEVAL_ETH001V1_H */ diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c index 1ef16e93ce097..b69d7f7481979 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c @@ -65,7 +65,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC /* Initialize and register the FOC device - must be before ADC setup */ ret = stm32_foc_setup(); diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c index 9a27e7bc94852..93d7ec8bd1e28 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c @@ -54,33 +54,33 @@ * 2. PWM complementary channels must have positive polarity */ -#ifndef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # error #endif -#if CONFIG_STM32F7_TIM1_CH1POL != 0 +#if CONFIG_STM32_TIM1_CH1POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2POL != 0 +#if CONFIG_STM32_TIM1_CH2POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3POL != 0 +#if CONFIG_STM32_TIM1_CH3POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH1NPOL != 0 +#if CONFIG_STM32_TIM1_CH1NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2NPOL != 0 +#if CONFIG_STM32_TIM1_CH2NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3NPOL != 0 +#if CONFIG_STM32_TIM1_CH3NPOL != 0 # error #endif /* Aux ADC needs DMA enabled */ #ifdef CONFIG_ADC -# ifndef CONFIG_STM32F7_ADC1_DMA +# ifndef CONFIG_STM32_ADC1_DMA # error # endif #endif @@ -122,7 +122,7 @@ #define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS # define STEVALETH001V1_FOC_VBUS 1 #else # define STEVALETH001V1_FOC_VBUS 0 @@ -133,11 +133,11 @@ /* Check ADC1 configuration */ -#if ADC1_INJECTED != CONFIG_STM32F7_ADC1_INJECTED_CHAN +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN # error #endif -#if CONFIG_STM32F7_ADC1_RESOLUTION != 0 +#if CONFIG_STM32_ADC1_RESOLUTION != 0 # error #endif @@ -186,7 +186,7 @@ static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); static uint8_t g_adc1_chan[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS 14, /* ADC1 REG - VBUS */ #endif 15, /* ADC1 INJ1 - PHASE 1 */ @@ -196,7 +196,7 @@ static uint8_t g_adc1_chan[] = static uint32_t g_adc1_pins[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS GPIO_ADC1_IN14, #endif GPIO_ADC1_IN15, @@ -208,7 +208,7 @@ static uint32_t g_adc1_pins[] = static adc_channel_t g_adc1_stime[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS { .channel = 14, .sample_time = VBUS_SAMPLE_TIME diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index b525313ee6549..9bc6dc43c7c33 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -108,7 +108,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -127,7 +127,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) @@ -316,4 +316,4 @@ #define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) #define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F746_WS_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746_WS_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c index eb4801aefb4ca..16dc06038d050 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c @@ -86,9 +86,9 @@ static void stm32_i2ctool(void) void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -127,7 +127,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* Initialize the SDIO block driver */ int ret = OK; diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c index 9d86414318e99..17ca34d8bfaad 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746-ws.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -195,42 +195,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -238,4 +238,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI6 */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c index b4a9bf9f1926f..4625864a28b2e 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32_gpio.h" #include "stm32f746-ws.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -330,4 +330,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h index 80532801ade46..ddc9e0711e458 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H -#define __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H +#ifndef __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H +#define __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H /**************************************************************************** * Included Files @@ -108,7 +108,7 @@ void weak_function stm32_spidev_initialize(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC1) int stm32_sdio_initialize(void); #endif @@ -128,4 +128,4 @@ int stm32_dma_alloc_init(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F746_WS_SRC_STM32F746_WS_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746_WS_SRC_STM32F746_WS_H */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index b390498974974..f082dfa5aa885 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -90,7 +90,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* Highest SYSCLK with USB OTG FS clock = 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_RNG) /* Highest SYSCLK with USB OTG FS clock <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -143,7 +143,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -152,8 +152,8 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ @@ -168,7 +168,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(344) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(7) @@ -528,7 +528,7 @@ /* SAI2 pinset */ -#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) +#if defined(CONFIG_STM32_SAI2) && defined(CONFIG_STM32_SAI2_A) # define GPIO_SAI2_SD_A (GPIO_SAI2_SD_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_FS_A (GPIO_SAI2_FS_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_SCK_A (GPIO_SAI2_SCK_A_2|GPIO_SPEED_100MHz) @@ -579,4 +579,4 @@ #define GPIO_FMC_SDNE0 (GPIO_FMC_SDNE0_3|GPIO_SPEED_100MHz) #define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_3|GPIO_SPEED_100MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746G_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c index db7cfae782795..374703bb0cb60 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c @@ -36,11 +36,11 @@ #include "stm32_gpio.h" #include "stm32_adc.h" -#ifndef CONFIG_STM32F7_ADC3 +#ifndef CONFIG_STM32_ADC3 # error "Only ADC3 channels are available on the arduino header of the board" #endif -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -104,7 +104,7 @@ static const uint32_t g_pinlist[6] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -150,4 +150,4 @@ int stm32_adc_setup(void) #endif } -#endif /* (CONFIG_ADC) && (CONFIG_STM32F7_ADC3) */ +#endif /* (CONFIG_ADC) && (CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 3992542c13fa8..bc89ac56e8c82 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. @@ -81,13 +81,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_enablefmc(); #endif } diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 774f9204fb621..bd6e034d810af 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -57,11 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 7 +#if STM32_NGPIO < 7 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c index cef610f4c3de9..c353723e5d053 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c @@ -40,7 +40,7 @@ #include "stm32_gpio.h" #include "stm32_ltdc.h" -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c index 66c889a5c926b..9ebe6730adc12 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746g-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c index cb7c130d8cb02..627dd0b399a28 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32F7_I2C3 -# error "FT5x06 support requires CONFIG_STM32F7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c index 8d556b459eca1..7df40f874e304 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f746g-disco.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -334,4 +334,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h index 1bbf837dd78a3..cd5d5c18e06f6 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H -#define __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H +#define __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H /**************************************************************************** * Included Files @@ -43,7 +43,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32F7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -84,7 +84,7 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC +#ifdef CONFIG_STM32_SDMMC #define HAVE_SDIO #else #undef HAVE_SDIO @@ -212,7 +212,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_enablefmc(void); #endif @@ -224,7 +224,7 @@ void stm32_enablefmc(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_disablefmc(void); #endif @@ -263,4 +263,4 @@ int stm32_wm8994_initialize(int minor); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 028b29b002318..21f6d2ffc77ed 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -483,4 +483,4 @@ #define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz) #define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz) -#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32F769I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c index 1ba49ec977e8e..42880e2706db7 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c @@ -59,9 +59,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -87,7 +87,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index 26ee7b72fd32f..a74c94d43f002 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 8 +#if STM32_NGPIO < 8 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c index 4f36938bb58b0..ef0f7aef17db7 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f769i-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h index 5c2ad841e97c2..36111aa9f74dd 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H -#define __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H +#define __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H /**************************************************************************** * Included Files @@ -158,9 +158,9 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32F7_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32F769I_DISCO_SRC_STM32F769I_DISCO_H */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9f5fb71fe13a2..fd495d6838f09 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -148,7 +148,7 @@ /* Configure factors for PLLSAI clock */ -#define CONFIG_STM32F7_PLLSAI 1 +#define CONFIG_STM32_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(384) #define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) @@ -158,8 +158,8 @@ * 25000000 / 25 * 384 / 2 / 8 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ @@ -174,7 +174,7 @@ /* Configure factors for PLLI2S clock */ -#define CONFIG_STM32F7_PLLI2S 1 +#define CONFIG_STM32_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(4) #define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4) diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index fbf4f961fc5b7..a430e4cfef21f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -74,9 +74,9 @@ extern struct qspi_dev_s *stm32f7_qspi_initialize(int intf); void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -102,7 +102,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32_QUADSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index a73495f2e0c29..e2a62c396a90c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 6 +#if STM32_NGPIO < 6 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c index fec4e8256a6be..0d4fb153ceb02 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f777zit6-meadow.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -117,7 +117,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,35 +183,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -219,4 +219,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c index 49a5b7310f706..be5332f7f44dd 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); # ifdef CONFIG_USBHOST stm32_configgpio(GPIO_OTGFS_PWRON); @@ -339,4 +339,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h index 827959faa5766..6fd24bd22f0bb 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h @@ -47,7 +47,7 @@ /* SDCard validation */ -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -165,7 +165,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); void stm32_disablefmc(void); #endif @@ -178,7 +178,7 @@ void stm32_disablefmc(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC2) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC2) int stm32_sdio_initialize(void); #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index 11ff18fb03729..1c9caa9d66353 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -36,7 +36,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_USBFS_HOST) && !defined(CONFIG_STM32H5_USE_HSE) +#if defined(CONFIG_STM32_USBFS_HOST) && !defined(CONFIG_STM32_USE_HSE) #error "This board config requires HSE to use the USB HOST." "HSI48 is not stable enough to use as a host." "To use HSE on the nucleo-H563ZI," @@ -65,7 +65,7 @@ #define STM32_LSI_FREQUENCY 32000 #define STM32_LSE_FREQUENCY 32768 -#ifdef CONFIG_STM32H5_USE_HSE +#ifdef CONFIG_STM32_USE_HSE #define STM32_HSE_FREQUENCY 25000000ul #define STM32_BOARD_USEHSE @@ -108,7 +108,7 @@ #define STM32_VCO2_FRQ ((STM32_HSE_FREQUENCY / 5) * 60) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#if defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS_HOST) /* PLL3 config: Generate 48 MHz for USB from 25 MHz HSE. * VCO input = 25 MHz / 5 = 5 MHz * VCO output = 5 MHz * 96 = 480 MHz @@ -132,9 +132,9 @@ #define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FRQ / 10) /* 48 MHz */ /* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */ -#define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK +#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ #else @@ -181,23 +181,23 @@ #define STM32_VCO2_FRQ ((STM32_HSI_FREQUENCY / 8) * 75) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#endif /* CONFIG_STM32H5_USE_HSE*/ +#endif /* CONFIG_STM32_USE_HSE*/ /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) -# define STM32H5_USE_CLK48 1 +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 #endif -#if defined(CONFIG_STM32H5_USBFS) -# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK -# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB +#if defined(CONFIG_STM32_USBFS) +# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32_HSI48_SYNCSRC SYNCSRC_USB #else -# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif -#if defined(CONFIG_STM32H5_RNG) -# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK +#if defined(CONFIG_STM32_RNG) +# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK #endif /* Enable LSE (for the RTC) */ @@ -426,4 +426,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H563ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h index 0d30bde00d792..693654353ae3e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H -#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H /**************************************************************************** * Included Files @@ -126,7 +126,7 @@ int stm32_bringup(void); int stm32_adc_setup(void); #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS int stm32_dts_setup(int devno); #endif @@ -138,7 +138,7 @@ int stm32_dts_setup(int devno); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(uint8_t port); #endif @@ -159,4 +159,4 @@ int stm32_usbhost_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c index ff662f03c1fd3..61e8ffec9b9b7 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c @@ -37,7 +37,7 @@ #include "stm32.h" #if defined(CONFIG_ADC) -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Identifying number of each ADC channel (even if NCHANNELS is less ) */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist1[ADC1_NCHANNELS] = { @@ -101,10 +101,10 @@ static uint32_t g_pinlist1[ADC1_NPINS] = int stm32_adc_setup(void) { static bool initialized = false; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 struct adc_dev_s *adc1; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 struct adc_dev_s *adc2; #endif int ret; @@ -116,7 +116,7 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { stm32_configgpio(g_pinlist1[i]); @@ -139,7 +139,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { stm32_configgpio(g_pinlist2[i]); @@ -168,5 +168,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c index 1653b49962636..4139cb487f91e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c @@ -107,7 +107,7 @@ int stm32_bringup(void) } #endif /* CONFIG_ADC*/ -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* devno == 0 creates /dev/sensor_temp0 */ ret = stm32_dts_setup(0); @@ -117,9 +117,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /* Initialize CAN and register the CAN driver. */ -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 ret = stm32_can_setup(1); if (ret < 0) { @@ -127,7 +127,7 @@ int stm32_bringup(void) } # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 ret = stm32_can_setup(2); if (ret < 0) { diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c index caa6709a4c30a..d33b11c390bc3 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c @@ -46,7 +46,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32H5_FDCAN1) && !defined(CONFIG_STM32H5_FDCAN2) +#if !defined(CONFIG_STM32_FDCAN1) && !defined(CONFIG_STM32_FDCAN2) # error "No CAN device is enabled. Please enable at least one CAN device" #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c index e1b23b88046c8..03e7b8d1e7065 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c @@ -37,13 +37,13 @@ * Currently the NUCLEO-H563ZI board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c index 4b1fbd9a713a4..e2d96c58a4dfa 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c @@ -34,7 +34,7 @@ #include "stm32.h" -#if defined(CONFIG_STM32H5_DTS) +#if defined(CONFIG_STM32_DTS) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c index 84c307b71813a..ede1d26a5ba2e 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c index cb293dd7f6eba..52df87a4c1a80 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c @@ -42,7 +42,7 @@ #include "stm32.h" #include "stm32_usbdrdhost.h" -#ifdef CONFIG_STM32H5_USBFS_HOST +#ifdef CONFIG_STM32_USBFS_HOST /**************************************************************************** * Pre-processor Definitions @@ -265,4 +265,4 @@ int board_usbhost_select_configuration(FAR struct usbhost_hubport_s *hport, } #endif -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 3072adbe60fba..d4283242bc221 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -488,7 +488,7 @@ * linum board routes only DQ[15:0] bits. */ -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 120000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -502,7 +502,7 @@ * this value will need to be doubled. */ -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC # define BOARD_SDRAM1_SIZE (6*1024*1024) #else # define BOARD_SDRAM1_SIZE (8*1024*1024) @@ -684,4 +684,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_LINUM_STM32H753BI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 8ce1c6eee650e..f08543a9734f1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H -#define __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H +#ifndef __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H +#define __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H /**************************************************************************** * Included Files @@ -86,7 +86,7 @@ * PD7 Enable power supply SD Card pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -162,7 +162,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -225,7 +225,7 @@ int stm32_pwm_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -305,4 +305,4 @@ int board_tone_initialize(int devno); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H */ +#endif /* __BOARDS_ARM_STM32_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index bab56899d14b3..02f6a1cc0ae3b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -47,7 +47,7 @@ # include "stm32_rtc.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -132,10 +132,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -166,7 +166,7 @@ int stm32_bringup(void) struct rtc_lowerhalf_s *lower; #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII /* Reset Ethernet PHY */ stm32_configgpio(GPIO_ETH_RESET); @@ -289,7 +289,7 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 /* Enable and configure CAN1 */ @@ -298,7 +298,7 @@ int stm32_bringup(void) stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 /* Enable and configure CAN2 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c index 15113bb0f06d5..bc5b9ffcacb12 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c index de8539d1a6fcd..097d5fc17aee2 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "linum-stm32h753bi.h" #include "stm32_spi.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32H7_SPI4) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI4) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions @@ -83,4 +83,4 @@ int stm32_mfrc522initialize(const char *devpath) return ret; } -#endif /* CONFIG_SPI && CONFIG_STM32H7_SPI4 && CONFIG_MFRC522 */ +#endif /* CONFIG_SPI && CONFIG_STM32_SPI4 && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c index b64a561aa2a99..18b39f615b11a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 +#ifndef CONFIG_STM32_TIM4 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c index cf5467941e08a..77db8bb8c3f4c 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "linum-stm32h753bi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -132,7 +132,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -140,4 +140,4 @@ int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c index 0ffbbc6e81ae7..76ff702a627bd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C3 -# error "FT5x06 support requires CONFIG_STM32H7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c index 88b139eb458ed..884e370b0c9fd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h723zg/include/board.h b/boards/arm/stm32h7/nucleo-h723zg/include/board.h index e2dba2fa23a41..41d7e715f06a1 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/include/board.h +++ b/boards/arm/stm32h7/nucleo-h723zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -518,4 +518,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H723ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h index b9036604f880b..58d1bb2ca7b11 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h +++ b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H +#define __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ /* Can't support USB host or device features if USB OTG HS is not enabled */ -#ifndef CONFIG_STM32H7_OTGHS +#ifndef CONFIG_STM32_OTGHS # undef HAVE_USBDEV #endif @@ -74,7 +74,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -213,7 +213,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -250,7 +250,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS void weak_function stm32_usbinitialize(void); #endif @@ -278,4 +278,4 @@ int stm32_pwm_setup(void); int stm32_oa_tc6_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index 8170b1decc7f3..de1615329f12e 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c index 4b07cc7033582..ffddcc7d01a61 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c index 445db3e67578d..43d7a676c91f1 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c @@ -97,16 +97,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c index 8df03e001094c..f8b200de7681c 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c index 23d61b098aa0e..0570f528631fe 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h723zg.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_NET_OA_TC6 @@ -101,7 +101,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -159,7 +159,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -173,7 +173,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -187,7 +187,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -225,42 +225,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -268,4 +268,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c index 2216484a5086f..953b452e86f95 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c @@ -78,7 +78,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_VBUS); stm32_configgpio(GPIO_OTGHS_PWRON); stm32_configgpio(GPIO_OTGHS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi/include/board.h b/boards/arm/stm32h7/nucleo-h743zi/include/board.h index f3417aef1553e..744ddeede6069 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -515,4 +515,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 4bcfe00d50ba4..9ecd89b25790f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -251,7 +251,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -288,7 +288,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -302,7 +302,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -401,4 +401,4 @@ int stm32_progmem_init(void); int stm32_mmcsd_initialize(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index 46744e439defb..31d99bd2bafc3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c index 17cfeed669d98..48da9194419b7 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c index a8999a87a404b..ac08dece22d0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -62,7 +62,7 @@ # include "stm32_capture.h" #endif -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG # include "stm32_wdg.h" #endif @@ -96,40 +96,40 @@ static int stm32_capture_setup(void) int ret; struct cap_lowerhalf_s *lower[] = { -#if defined(CONFIG_STM32H7_TIM1_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) stm32_cap_initialize(1), #endif -#if defined(CONFIG_STM32H7_TIM2_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) stm32_cap_initialize(2), #endif -#if defined(CONFIG_STM32H7_TIM3_CAP) +#if defined(CONFIG_STM32_TIM3_CAP) stm32_cap_initialize(3), #endif -#if defined(CONFIG_STM32H7_TIM4_CAP) +#if defined(CONFIG_STM32_TIM4_CAP) stm32_cap_initialize(4), #endif -#if defined(CONFIG_STM32H7_TIM5_CAP) +#if defined(CONFIG_STM32_TIM5_CAP) stm32_cap_initialize(5), #endif -#if defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM8_CAP) stm32_cap_initialize(8), #endif -#if defined(CONFIG_STM32H7_TIM12_CAP) +#if defined(CONFIG_STM32_TIM12_CAP) stm32_cap_initialize(12), #endif -#if defined(CONFIG_STM32H7_TIM13_CAP) +#if defined(CONFIG_STM32_TIM13_CAP) stm32_cap_initialize(13), #endif -#if defined(CONFIG_STM32H7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM14_CAP) stm32_cap_initialize(14), #endif -#if defined(CONFIG_STM32H7_TIM15_CAP) +#if defined(CONFIG_STM32_TIM15_CAP) stm32_cap_initialize(15), #endif -#if defined(CONFIG_STM32H7_TIM16_CAP) +#if defined(CONFIG_STM32_TIM16_CAP) stm32_cap_initialize(16), #endif -#if defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM17_CAP) stm32_cap_initialize(17), #endif /* TODO: LPTIMy_CAP */ @@ -216,16 +216,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -487,7 +487,7 @@ int stm32_bringup(void) #endif /* HAVE_PROGMEM_CHARDEV */ #endif /* CONFIG_MTD */ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c index 6412aca6a93d5..6017b9b69ad3e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -62,7 +62,7 @@ int stm32_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c index a7037b3c4cc85..0d1e880723802 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -66,7 +66,7 @@ int stm32_lsm6dsl_initialize(char *devpath) stm32_configgpio(GPIO_LPS22HB_INT1); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c index 6f5276f12d6e6..bb50400bd619d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM9DS1 driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM9DS1 driver requires CONFIG_STM32_I2C1 to be enabled" #endif #define LSM9DS1MAG_DEVPATH "/dev/lsm9ds1mag0" @@ -66,7 +66,7 @@ int stm32_lsm9ds1_initialize(void) sninfo("Initializing LMS9DS1!\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(LMS9DS1_I2CBUS); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c index 40dbe2fcbf451..7979ef412b81e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c @@ -44,7 +44,7 @@ # error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" #endif -#ifndef CONFIG_STM32H7_SPI3 +#ifndef CONFIG_STM32_SPI3 # error "MMC/SD requires SPI3 enabled" #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c index 0631fcba68842..fba60268a2f54 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h index 6e90378c8fd43..fe0ccc5070dde 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H /**************************************************************************** * Included Files @@ -60,4 +60,4 @@ int stm32_romfs_initialize(void); #endif /* CONFIG_STM32_ROMFS */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_SRC_STM32_ROMFS_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c index 04b75b9f41d7f..42f9a514fe6a2 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h743zi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_WL_NRF24L01 @@ -108,7 +108,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -122,7 +122,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -136,7 +136,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -192,7 +192,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -206,7 +206,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,7 +220,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -258,42 +258,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -301,4 +301,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index 3efae55c0f72a..ed51bc585789b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h index 9f06515763291..d9a2041fb6716 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -472,4 +472,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index ad98bd39fd379..75674b8a01f0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H +#define __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH743ZI2_PWMTIMER 1 #else # define NUCLEOH743ZI2_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -241,4 +241,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI2_SRC_NUCLEO_H743ZI2_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index 04a0ef65f5db7..a4f02f1a5cf41 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c index be6710f36d0a9..29d8de24ef8bb 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c index f0d0a7df159bd..f526cd6876ba9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c @@ -35,11 +35,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -242,18 +242,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -264,7 +264,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -275,7 +275,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c index 51afc1e4447bd..943a4c4a8846d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c index 547fda201e64a..3b7a541084ed6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi2.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h index ff06353a65342..d0315dac37f77 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -153,7 +153,7 @@ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 # define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) #else # define STM32_CPUCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 1) @@ -435,4 +435,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H745ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h index b3b16bee6f644..6d8ffc5e3ed49 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h +++ b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H /**************************************************************************** * Included Files @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -226,7 +226,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) #define NUCLEOH745ZI_PWMTIMER 1 #else #define NUCLEOH745ZI_PWMTIMER 3 @@ -249,7 +249,7 @@ int stm32_bringup(void); -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -287,7 +287,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -315,4 +315,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index 731b1421e9313..f906cca2e3aa8 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -49,9 +49,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -64,7 +64,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -92,7 +92,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -133,7 +133,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(int adcno) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -147,7 +147,7 @@ int stm32_adc_setup(int adcno) snprintf(devname, sizeof(devname), "/dev/adc%d", adcno); #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -178,7 +178,7 @@ int stm32_adc_setup(int adcno) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -208,7 +208,7 @@ int stm32_adc_setup(int adcno) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -220,5 +220,5 @@ int stm32_adc_setup(int adcno) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c index ddc8f1d668ccb..4dcddeb88b7c2 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c @@ -39,7 +39,7 @@ #ifdef CONFIG_ARCH_LEDS -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # error autoleds not supported for M4 core now #endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c index dfbbfecba2b73..265a4399fef3b 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a8e26a5b59120..a782f7371941f 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -62,11 +62,11 @@ void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -105,7 +105,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); @@ -144,11 +144,11 @@ int stm32_bringup(void) int adcno = 0; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 adcno = 0; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 adcno = 2; #endif @@ -172,18 +172,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -194,7 +194,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -205,7 +205,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c index 1e34ac8a09359..adeaaf3673c93 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c index 77b5638be1f6c..c06f89ef35a20 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h745zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h753zi/include/board.h b/boards/arm/stm32h7/nucleo-h753zi/include/board.h index 504c40be53901..66b77b6ff83ef 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h753zi/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -468,4 +468,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H753ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h index 8549c8b633afc..17472c9fffe35 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h +++ b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H -#define __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H +#define __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH753ZI_PWMTIMER 1 #else # define NUCLEOH753ZI_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -241,4 +241,4 @@ int stm32_pwm_setup(void); int stm32_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_H753ZI_SRC_NUCLEO_H753ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 3bd182ef3820a..8871b8f74d9d3 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c index 027cde005d767..417ba5b8bcdd4 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c index be030dcb4d2c8..805c1c4636885 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c @@ -36,11 +36,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -218,18 +218,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -240,7 +240,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -251,7 +251,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c index 24eae1bc1cf1d..8898b9655fa77 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c index 668f6ac2e232f..73ddf89178f30 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h753zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/openh743i/include/board.h b/boards/arm/stm32h7/openh743i/include/board.h index 99a5899c0a3dc..ac18190003e0a 100644 --- a/boards/arm/stm32h7/openh743i/include/board.h +++ b/boards/arm/stm32h7/openh743i/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -378,4 +378,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_OPENH743I_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h index 1645ce0118242..0bd3f2c1a9b06 100644 --- a/boards/arm/stm32h7/openh743i/src/openh743i.h +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H -#define __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H +#ifndef __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H +#define __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H /**************************************************************************** * Included Files @@ -105,7 +105,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SDMMC +#ifdef CONFIG_STM32_SDMMC int stm32_sdio_initialize(void); #endif @@ -118,7 +118,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -136,4 +136,4 @@ void weak_function stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H */ +#endif /* __BOARDS_ARM_STM32_OPENH743I_SRC_OPENH743I_H */ diff --git a/boards/arm/stm32h7/openh743i/src/stm32_boot.c b/boards/arm/stm32h7/openh743i/src/stm32_boot.c index df105a23b30aa..a6193210adae8 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_boot.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_boot.c @@ -52,7 +52,7 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) || defined(CONFIG_STM32_OTGHS_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c index 1bf485416d91c..a9dbd9ae9e715 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -91,7 +91,7 @@ int stm32_bringup(void) usbdev_rndis_initialize(mac); #endif -#if defined(CONFIG_STM32H7_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) +#if defined(CONFIG_STM32_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) /* Initialize the SDIO block driver */ ret = stm32_sdio_initialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c index 600ace9250ac7..eb8a354de6a78 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -45,13 +45,13 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC1 +#ifndef CONFIG_STM32_SDMMC1 # error SDMMC1 supported only #endif /* If IDMA is enabled, internal SRAM must be excluded from heap */ -#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) +#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32_SDMMC_IDMA) # error SDMMC1 with IDMA does not work CONFIG_MM_REGIONS > 1 #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c index 5e53687605cbd..59dbdf27b088c 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usb.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_USBDEV) # ifndef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON # error PWRON must be disabled for this configuration # endif @@ -121,7 +121,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -307,7 +307,7 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) uinfo("resume: %d\n", resume); } -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * diff --git a/boards/arm/stm32h7/portenta-h7/include/board.h b/boards/arm/stm32h7/portenta-h7/include/board.h index 362badffdbe01..4ce9460b7e92b 100644 --- a/boards/arm/stm32h7/portenta-h7/include/board.h +++ b/boards/arm/stm32h7/portenta-h7/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -150,7 +150,7 @@ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 # define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) #else # define STM32_CPUCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 1) @@ -360,4 +360,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_PORTENTA_H7_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_PORTENTA_H7_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h b/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h index 157269188172e..a5672b1f46a31 100644 --- a/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h +++ b/boards/arm/stm32h7/portenta-h7/src/portenta-h7.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H -#define __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H +#ifndef __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H +#define __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H /**************************************************************************** * Included Files @@ -85,4 +85,4 @@ int stm32_bringup(void); -#endif /* __BOARDS_ARM_STM32H7_PORTENTA_H7_SRC_PORTENTA_H7_H */ +#endif /* __BOARDS_ARM_STM32_PORTENTA_H7_SRC_PORTENTA_H7_H */ diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c b/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c index 686f4d5245474..131b0ccc5b21e 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c @@ -39,7 +39,7 @@ #ifdef CONFIG_ARCH_LEDS -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # error autoleds not supported for M4 core now #endif diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c index a61fab1bb6488..cfbcb8fec4cf6 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c @@ -85,16 +85,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h index 1593c65b03275..51fa696247120 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -343,7 +343,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -614,4 +614,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H745I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H745I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c index 24b1520287482..786f655db5312 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c index 5af6ac7f31f97..2b575ec3398e3 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c @@ -35,7 +35,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif @@ -92,11 +92,11 @@ static void convert_lcd_rgb565(void) void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -140,7 +140,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c index df62ee84f7dbb..639db95d733a7 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c @@ -49,8 +49,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c index 7a5b17ad617f9..eb02f937d6e27 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c index d08defcdbc5ad..07f43943a3e68 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h index 57ef2b05e63b0..e432a122d3073 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H -#define __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H +#define __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H /**************************************************************************** * Included Files @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -184,7 +184,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -198,7 +198,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -216,4 +216,4 @@ int stm32_usbhost_initialize(void); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32H745I_DISCO_SRC_STM32H745I_DISCO_H */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/include/board.h b/boards/arm/stm32h7/stm32h747i-disco/include/board.h index 2eeaba7d62ce8..54701cc1ac72d 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h747i-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -471,4 +471,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H747I_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H747I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index 43d90ea1c5857..ce9e0758f3920 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -124,7 +124,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -136,7 +136,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -167,7 +167,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -197,7 +197,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -209,5 +209,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c index 595a6acb393f9..2fe6598915c7e 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGHS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c index 84e93d0e9977b..12a8a37d4fdd0 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c @@ -90,16 +90,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c index a5885be43e0f7..b038469e60bdd 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "stm32h747i-disco.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -91,7 +91,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -105,7 +105,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -119,7 +119,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -171,7 +171,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,42 +209,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -252,4 +252,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c index 7295b74cebe64..84c95e9204b51 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "stm32h747i-disco.h" -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS /**************************************************************************** * Pre-processor Definitions @@ -54,7 +54,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32H7_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -132,7 +132,7 @@ void stm32_usbinitialize(void) { /* Configure the Overcurrent GPIO */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_OVER); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h index c53bb6f8a765e..8a3f154959761 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H -#define __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H +#define __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H /**************************************************************************** * Included Files @@ -95,7 +95,7 @@ /* SD/TF Card'detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -129,7 +129,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -172,4 +172,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32H747I_DISCO_SRC_STM32H747I_DISCO_H */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/include/board.h b/boards/arm/stm32h7/stm32h750b-dk/include/board.h index c63ca3b3fdc21..6f7b603a38cbd 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h750b-dk/include/board.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -340,7 +340,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -611,4 +611,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_STM32H750B_DK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32H750B_DK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c index 0095a26c9b816..e0fe3d7317508 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c index a7200dffe19a8..d4e536b774474 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif @@ -90,11 +90,11 @@ static void convert_lcd_rgb565(void) void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -138,7 +138,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c index e719e3ac6fd94..72e3d357b3477 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c @@ -47,8 +47,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c index de3e72c627fe5..9ffca9632b1e6 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c @@ -37,7 +37,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c index 882307c69852f..50d12205e6557 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c @@ -43,7 +43,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -136,7 +136,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h index 5e0e6b7f2de52..e0579a31433e7 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H -#define __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H +#ifndef __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H +#define __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H /**************************************************************************** * Included Files @@ -42,7 +42,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -182,7 +182,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -196,7 +196,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif @@ -214,4 +214,4 @@ int stm32_usbhost_initialize(void); int stm32_tsc_setup(int minor); #endif -#endif /* __BOARDS_ARM_STM32H7_STM32H750B_DK_SRC_STM32H750B_DK_H */ +#endif /* __BOARDS_ARM_STM32_STM32H750B_DK_SRC_STM32H750B_DK_H */ diff --git a/boards/arm/stm32h7/weact-stm32h743/include/board.h b/boards/arm/stm32h7/weact-stm32h743/include/board.h index b0b0a6cbcc06e..366a3af7cdb76 100644 --- a/boards/arm/stm32h7/weact-stm32h743/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h743/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -406,4 +406,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H743_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c index 4c09ec8ce107d..6173d41518e55 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c index a11654bc8faaf..91513bcf09139 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c index eb46659de268a..4aff43a107a86 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h743.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h index 34f91044d7ec8..59e0f9ebd9fe9 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h +++ b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H +#define __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H /**************************************************************************** * Included Files @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -199,4 +199,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H743_SRC_WEACT_STM32H743_H */ diff --git a/boards/arm/stm32h7/weact-stm32h750/include/board.h b/boards/arm/stm32h7/weact-stm32h750/include/board.h index e85bde12df7e3..321f5f4417cc4 100644 --- a/boards/arm/stm32h7/weact-stm32h750/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h750/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -406,4 +406,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H750_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H750_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c index 34102ce9f2d4f..4c9423b7a3b84 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c index 226882d0e6c40..46b87280b62d8 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c index ca8e4cbab7bab..506bb238ed0bd 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h750.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h index ecf03db790700..d39ffd16f4eec 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h +++ b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H -#define __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H +#ifndef __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H +#define __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H /**************************************************************************** * Included Files @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -199,4 +199,4 @@ int stm32_dma_alloc_init(void); int stm32_sdio_initialize(void); #endif -#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H750_SRC_WEACT_STM32H750_H */ +#endif /* __BOARDS_ARM_STM32_WEACT_STM32H750_SRC_WEACT_STM32H750_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 3782cd800783c..508ba420e0d30 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK_H /**************************************************************************** * Included Files @@ -56,20 +56,20 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -85,13 +85,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -130,7 +130,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -149,7 +149,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -175,7 +175,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -225,7 +225,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -235,13 +235,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -255,72 +255,72 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1, when - * NOT define STM32L4_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. + * NOT define STM32_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM3_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM4_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM5_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM6_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM7_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM1_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM2_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM8_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM15_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM16_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM17_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM8_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -335,7 +335,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -343,78 +343,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -422,71 +422,71 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -495,19 +495,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32L4_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY STM32L4_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#define BOARD_TIM8_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#define BOARD_TIM15_FREQUENCY STM32L4_APB2_TIM15_CLKIN -#define BOARD_TIM16_FREQUENCY STM32L4_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32L4_APB2_TIM17_CLKIN -#define BOARD_LPTIM1_FREQUENCY STM32L4_APB1_LPTIM1_CLKIN -#define BOARD_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN +#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN +#define BOARD_TIM15_FREQUENCY STM32_APB2_TIM15_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define BOARD_LPTIM1_FREQUENCY STM32_APB1_LPTIM1_CLKIN +#define BOARD_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARMSTM32L4__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ +#endif /* __BOARDS_ARMSTM32__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h index c9873219a21fb..57863fae794cd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -188,4 +188,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_B_L475E_IOT01A_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_B_L475E_IOT01A_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h index 831f891cc5ae0..a225fd336aa46 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H -#define __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H +#ifndef __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H +#define __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ /* SPSGRF support depends on: * - * CONFIG_STM32L4_SPI3 - SPI3 support + * CONFIG_STM32_SPI3 - SPI3 support * CONFIG_WL_SPIRIT - Spirit wireless library * CONFIG_SPIRIT_NETDEV - Spirit network driver * CONFIG_SCHED_HPWORK - HP work queue support @@ -57,7 +57,7 @@ * And probably a few other things. */ -#if !defined(CONFIG_STM32L4_SPI3) +#if !defined(CONFIG_STM32_SPI3) # undef HAVE_SPSGRF #endif @@ -73,7 +73,7 @@ # undef HAVE_SPSGRF #endif -#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32L4_QSPI) +#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32_QSPI) # undef HAVE_MX25R6435F #endif @@ -154,8 +154,8 @@ int stm32l4_bringup(void); * ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) void weak_function stm32l4_spidev_initialize(void); #endif @@ -195,4 +195,4 @@ int stm32l4_spirit_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H */ +#endif /* __BOARDS_ARM_STM32_B_L475E_IOT01A_SRC_B_L475E_IOT01A_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index 27bca5f9baec8..02f3b5fcb8891 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -50,7 +50,7 @@ void stm32l4_board_initialize(void) { -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /* Configure SPI chip selects if * 1) SPI is not disabled, and 2) the weak function * stm32l4_spidev_initialize() has been brought into the link. diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index d3a2d3b320ed4..90ade076ba0b8 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -45,16 +45,16 @@ /* Currently no devices are defined on SPI1 or SPI2 */ -#undef CONFIG_STM32L4_SPI1 -#undef CONFIG_STM32L4_SPI2 +#undef CONFIG_STM32_SPI1 +#undef CONFIG_STM32_SPI2 /* Only the SPSGRF is currently supported on SPI3 */ #ifndef HAVE_SPSGRF -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI3 #endif -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -62,15 +62,15 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -89,7 +89,7 @@ struct spi_dev_s *g_spi3; void weak_function stm32l4_spidev_initialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32l4_spibus_initialize(1); @@ -101,7 +101,7 @@ void weak_function stm32l4_spidev_initialize(void) /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32l4_spibus_initialize(2); @@ -109,7 +109,7 @@ void weak_function stm32l4_spidev_initialize(void) /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices */ g_spi3 = stm32l4_spibus_initialize(3); @@ -148,7 +148,7 @@ void weak_function stm32l4_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,7 +162,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -176,7 +176,7 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l4_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -221,21 +221,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -243,4 +243,4 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 36ef0fddd93bf..01d23175df7c7 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -56,7 +56,7 @@ int stm32l4_timer_driver_setup(void) { int ret = OK; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 ret = stm32l4_timer_initialize("/dev/timer0", 1); if (ret < 0) { @@ -65,7 +65,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 ret = stm32l4_timer_initialize("/dev/timer1", 2); if (ret < 0) { @@ -74,7 +74,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 ret = stm32l4_timer_initialize("/dev/timer2", 3); if (ret < 0) { @@ -83,7 +83,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 ret = stm32l4_timer_initialize("/dev/timer3", 4); if (ret < 0) { @@ -92,7 +92,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 ret = stm32l4_timer_initialize("/dev/timer4", 5); if (ret < 0) { @@ -101,7 +101,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 ret = stm32l4_timer_initialize("/dev/timer5", 6); if (ret < 0) { @@ -110,7 +110,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 ret = stm32l4_timer_initialize("/dev/timer6", 7); if (ret < 0) { @@ -119,7 +119,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 ret = stm32l4_timer_initialize("/dev/timer7", 8); if (ret < 0) { @@ -128,7 +128,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 ret = stm32l4_timer_initialize("/dev/timer8", 15); if (ret < 0) { @@ -137,7 +137,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 ret = stm32l4_timer_initialize("/dev/timer9", 16); if (ret < 0) { @@ -146,7 +146,7 @@ int stm32l4_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 ret = stm32l4_timer_initialize("/dev/timer10", 17); if (ret < 0) { diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index cc2f750933f9c..c363e2dea46a7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -264,8 +264,8 @@ * CH1 | 1(A4) 2(A8) */ -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) -# define STM32L4_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) +# define STM32_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN #endif #if 1 @@ -312,4 +312,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index bc2cd77d6dde7..097de375d1032 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H /**************************************************************************** * Included Files @@ -57,20 +57,20 @@ * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL * configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -86,11 +86,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -127,7 +127,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -146,7 +146,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -216,7 +216,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -226,13 +226,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -246,45 +246,45 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -293,16 +293,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -311,9 +311,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -321,7 +321,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -329,59 +329,59 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -390,14 +390,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -406,16 +406,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -423,74 +423,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -500,14 +500,14 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_INCLUDE_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h index b9f111e886a93..6a9a4cf3bc848 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H +#define __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H /**************************************************************************** * Included Files @@ -61,7 +61,7 @@ /* Check if we can support AT45DB FLASH file system */ -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MTD_AT45DB) +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_AT45DB) # undef HAVE_AT45DB #endif @@ -108,10 +108,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif @@ -295,4 +295,4 @@ int board_timer_driver_initialize(const char *devpath, int timer); int stm32l4_qencoder_initialize(const char *devpath, int timer); #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c index e7663aef96171..95e7093287782 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l432kc.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ /* The number of ADC channels in the conversion list */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_NCHANNELS 2 #else # define ADC1_NCHANNELS 1 @@ -58,7 +58,7 @@ /* Identifying number of each ADC channel. */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = { @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC1_IN11_0 }; -#endif /* CONFIG_STM32L4_ADC1_DMA */ +#endif /* CONFIG_STM32_ADC1_DMA */ /**************************************************************************** * Private Functions @@ -139,4 +139,4 @@ int stm32l4_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c index 9accb5984f080..a1ebdaabbdcdd 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c @@ -42,7 +42,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "AT45DB driver requires CONFIG_STM32_SPI1 to be enabled" #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c index 1241ab202ffcd..cdacf2a9a702a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c @@ -72,8 +72,8 @@ void stm32l4_board_initialize(void) * function stm32l4_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) stm32l4_spiinitialize(); #endif @@ -82,7 +82,7 @@ void stm32l4_board_initialize(void) * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) stm32l4_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c index d8dead5bc11cc..be01e6f21d326 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c @@ -58,7 +58,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if (defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C3)) && defined(CONFIG_I2C_DRIVER) +#if (defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3)) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif @@ -82,10 +82,10 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER struct rtc_lowerhalf_s *rtclower; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 struct i2c_master_s *i2c1; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 struct i2c_master_s *i2c3; #endif #ifdef CONFIG_SENSORS_QENCODER @@ -151,7 +151,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Get the I2C lower half instance */ i2c1 = stm32l4_i2cbus_initialize(1); @@ -171,7 +171,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Get the I2C lower half instance */ i2c3 = stm32l4_i2cbus_initialize(3); @@ -220,7 +220,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_ADC +#ifdef CONFIG_STM32_ADC /* Initialize ADC and register the ADC driver. */ ret = stm32l4_adc_setup(); @@ -230,7 +230,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_DAC +#ifdef CONFIG_STM32_DAC /* Initialize DAC and register the DAC driver. */ ret = stm32l4_dac_setup(); @@ -298,7 +298,7 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 1); if (ret != OK) @@ -309,7 +309,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 2); if (ret != OK) @@ -320,7 +320,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 3); if (ret != OK) @@ -331,7 +331,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 4); if (ret != OK) @@ -342,7 +342,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 5); if (ret != OK) @@ -353,7 +353,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 8); if (ret != OK) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c index 4e57f555eb2ca..75a869a444387 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c @@ -41,7 +41,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac; #endif @@ -59,7 +59,7 @@ int stm32l4_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32l4_dacinitialize(0); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c index a62e824fbc014..1605fb2049a7a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_DAC7571) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c index 32d73de778359..2bbea61fa78a6 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c @@ -66,19 +66,19 @@ # error "CONFIG_DAC is required" #endif -#ifndef CONFIG_STM32L4_DAC1 -# error "CONFIG_STM32L4_DAC1 is required" +#ifndef CONFIG_STM32_DAC1 +# error "CONFIG_STM32_DAC1 is required" #endif -#ifndef CONFIG_STM32L4_DAC_LL_OPS -# error "CONFIG_STM32L4_DAC_LL_OPS is required" +#ifndef CONFIG_STM32_DAC_LL_OPS +# error "CONFIG_STM32_DAC_LL_OPS is required" #endif -#ifndef CONFIG_STM32L4_DAC1_DMA -# error "CONFIG_STM32L4_DAC1_DMA is required" +#ifndef CONFIG_STM32_DAC1_DMA +# error "CONFIG_STM32_DAC1_DMA is required" #endif -#if (CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) +#if (CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) # error "DMA buffer size should be equal or greater than the number of samples." #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c index 7a0ca30e193cb..9c25b275d4a0a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA219) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c index cfa9af0ae10ac..6354edb65e418 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA226) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c index fedfb03350873..4912996902160 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c @@ -87,7 +87,7 @@ int stm32l4_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32l4_pwminitialize(1); if (!pwm) { @@ -105,7 +105,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32l4_pwminitialize(2); if (!pwm) { @@ -123,7 +123,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32l4_pwminitialize(15); if (!pwm) { @@ -141,7 +141,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32l4_pwminitialize(16); if (!pwm) { @@ -159,7 +159,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) pwm = stm32l4_lp_pwminitialize(1); if (!pwm) { @@ -177,7 +177,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM2_PWM) pwm = stm32l4_lp_pwminitialize(2); if (!pwm) { diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index 421a2497b2c3c..f887957ec7dfc 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "nucleo-l432kc.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void stm32l4_spiregister(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int ret = spi_register(g_spi1, 1); if (ret < 0) { @@ -78,7 +78,7 @@ void stm32l4_spiregister(void) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int ret = spi_register(g_spi2, 2); if (ret < 0) { @@ -98,7 +98,7 @@ void stm32l4_spiregister(void) void stm32l4_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI1-based devices */ g_spi1 = stm32l4_spibus_initialize(1); @@ -118,7 +118,7 @@ void stm32l4_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI2-based devices */ g_spi2 = stm32l4_spibus_initialize(2); @@ -161,7 +161,7 @@ void stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -182,7 +182,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,14 +220,14 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -235,4 +235,4 @@ int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 63bcbcb47b980..c0591b8cb3b5f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -81,10 +81,10 @@ /* Phase 1 is TIM1 CH1 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 0 -# ifndef CONFIG_STM32L4_TIM1_CH1OUT +# ifndef CONFIG_STM32_TIM1_CH1OUT # error # endif -# ifndef CONFIG_STM32L4_TIM6 +# ifndef CONFIG_STM32_TIM6 # error # endif # endif @@ -92,7 +92,7 @@ /* Phase 2 is TIM1 CH2 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 1 -# ifndef CONFIG_STM32L4_TIM1_CH2OUT +# ifndef CONFIG_STM32_TIM1_CH2OUT # error # endif # endif @@ -100,7 +100,7 @@ /* Phase 3 is TIM1 CH3 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 2 -# ifndef CONFIG_STM32L4_TIM1_CH3OUT +# ifndef CONFIG_STM32_TIM1_CH3OUT # error # endif # endif @@ -108,7 +108,7 @@ /* Phase 4 is TIM1 CH4 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 3 -# ifndef CONFIG_STM32L4_TIM1_CH4OUT +# ifndef CONFIG_STM32_TIM1_CH4OUT # error # endif # endif @@ -336,7 +336,7 @@ static void tim6_handler(void) /* TODO: Software update */ - STM32L4_TIM_ACKINT(tim, ATIM_SR_UIF); + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); } /**************************************************************************** @@ -368,12 +368,12 @@ static int spwm_tim6_setup(struct spwm_s *spwm) freq = spwm->samples * spwm->waveform_freq; - STM32L4_TIM_SETFREQ(tim, freq); - STM32L4_TIM_ENABLE(tim); + STM32_TIM_SETFREQ(tim, freq); + STM32_TIM_ENABLE(tim); /* Attach TIM6 ram vector */ - ret = arm_ramvec_attach(STM32L4_IRQ_TIM6, tim6_handler); + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); if (ret < 0) { printf("ERROR: arm_ramvec_attach failed: %d\n", ret); @@ -383,7 +383,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) /* Set the priority of the TIM6 interrupt vector */ - ret = up_prioritize_irq(STM32L4_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); if (ret < 0) { printf("ERROR: up_prioritize_irq failed: %d\n", ret); @@ -407,8 +407,8 @@ static int spwm_tim6_start(struct spwm_s *spwm) /* Enable the timer interrupt at the NVIC and at TIM6 */ - up_enable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_ENABLEINT(tim, BTIM_DIER_UIE); + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(tim, BTIM_DIER_UIE); return OK; } @@ -423,8 +423,8 @@ static int spwm_tim6_stop(struct spwm_s *spwm) /* Disable the timer interrupt at the NVIC and at TIM6 */ - up_disable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_DISABLEINT(tim, BTIM_DIER_UIE); + up_disable_irq(STM32_IRQ_TIM6); + STM32_TIM_DISABLEINT(tim, BTIM_DIER_UIE); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l452re/include/board.h b/boards/arm/stm32l4/nucleo-l452re/include/board.h index f4bf2ebf864cd..2e9e05f520362 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/board.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -275,4 +275,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 0dd3430e3bda1..1cdf8d97ca8a2 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H /**************************************************************************** * Included Files @@ -44,16 +44,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -69,9 +69,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #if 1 # define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ @@ -85,7 +85,7 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -125,7 +125,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -144,7 +144,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -170,7 +170,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -221,7 +221,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -232,55 +232,55 @@ * want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -289,17 +289,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -308,9 +308,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -318,7 +318,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -326,82 +326,82 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -409,75 +409,75 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -487,17 +487,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -524,4 +524,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_INCLUDE_NUCLEO_L452RE_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 4ab69149c5d59..21b436eabb040 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H +#define __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H /**************************************************************************** * Included Files @@ -58,22 +58,22 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD #endif /* How many SPI modules does this chip support? */ -#if STM32L4_NSPI < 1 -# undef CONFIG_STM32L4_SPI1 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 2 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 3 -# undef CONFIG_STM32L4_SPI3 +#if STM32_NSPI < 1 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 2 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 +#elif STM32_NSPI < 3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-L452RE GPIOs ******************************************************/ @@ -163,4 +163,4 @@ int stm32l4_dac_setup(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L452RE_SRC_NUCLEO_L452RE_H */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c index 2cd9d75fb259f..bf18e9647f2e4 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c @@ -114,7 +114,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -286,7 +286,7 @@ int stm32l4_adc_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c index 31eac2e1376d2..59e37aff5d008 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c @@ -45,7 +45,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c index 09b56bc5ff424..318e88261d24c 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c @@ -57,7 +57,7 @@ int stm32l4_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32l4_dacinitialize(0); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index 4c43919bd200c..17c3483971a0a 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -40,7 +40,7 @@ #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -69,7 +69,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32l4_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32l4_spibus_initialize(1); @@ -83,7 +83,7 @@ void weak_function stm32l4_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32l4_spibus_initialize(2); @@ -120,7 +120,7 @@ void weak_function stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -141,7 +141,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -155,7 +155,7 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l4_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -193,21 +193,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -215,4 +215,4 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/board.h b/boards/arm/stm32l4/nucleo-l476rg/include/board.h index b483107f1ae82..50530a1e0f1bf 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -277,4 +277,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_F476RG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_F476RG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 39623ef7e569d..07dd18aa069c8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H /**************************************************************************** * Included Files @@ -55,16 +55,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -80,11 +80,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -124,7 +124,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -143,7 +143,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -219,7 +219,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -230,13 +230,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -250,68 +250,68 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -326,7 +326,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -334,81 +334,81 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -416,74 +416,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -492,19 +492,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data @@ -531,4 +531,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h index adf24d58b9ae2..ac950b67fae32 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H /**************************************************************************** * Included Files @@ -61,12 +61,12 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SPI) # undef HAVE_MMCSD_SPI #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD_SDIO #endif @@ -265,10 +265,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif #ifdef HAVE_MMCSD_SDIO @@ -446,4 +446,4 @@ int stm32_as726xinitialize(const char *devpath); int stm32_bmp180initialize(const char *devpath); #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 4fc545de40ef2..138c316678952 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l476rg.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -144,4 +144,4 @@ int stm32l4_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index 4b1f6a776a15e..4b7656d5f2560 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -51,8 +51,8 @@ # if !defined(CONFIG_ADC) # error CONFIG_ADC is required for the Itead joystick # undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32L4_ADC1) -# error CONFIG_STM32L4_ADC1 is required for Itead joystick +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick # undef CONFIG_INPUT_AJOYSTICK # endif #endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h index 72b1aa089f8c3..477632532b443 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp280_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index 4800e811aa07e..bdf6ddf8a6f64 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -64,7 +64,7 @@ void stm32l4_board_initialize(void) * function stm32l4_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) stm32l4_spiinitialize(); #endif @@ -73,7 +73,7 @@ void stm32l4_board_initialize(void) * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) stm32l4_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c index 9864ec4040ad8..9f43e3e43a6fa 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c @@ -327,7 +327,7 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 1); if (ret < 0) @@ -338,7 +338,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 2); if (ret < 0) @@ -349,7 +349,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 3); if (ret < 0) @@ -360,7 +360,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 4); if (ret < 0) @@ -371,7 +371,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 5); if (ret < 0) @@ -382,7 +382,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32l4_qencoder_initialize(buf, 8); if (ret < 0) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c index 7a59c087c87f7..8cea1d5c3e0e0 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_STM32_CAN1) # warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #endif @@ -65,7 +65,7 @@ int stm32l4_can_setup(void) { -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c index 43b8d711a5c3b..f59da58d0ad48 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -61,7 +61,7 @@ int stm32l4_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32l4_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c index df404b8147ed6..88465db68455e 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -65,7 +65,7 @@ int stm32l4_lsm6dsl_initialize(char *devpath) stm32l4_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32l4_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h index 34a3cb06fcee1..694c09478a02c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H +#define __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H /**************************************************************************** * Included Files @@ -88,4 +88,4 @@ int board_mpu9250_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index 231a62a88ff71..842185954dd34 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -88,7 +88,7 @@ int stm32l4_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32l4_pwminitialize(1); if (!pwm) { @@ -106,7 +106,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32l4_pwminitialize(2); if (!pwm) { @@ -124,7 +124,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32l4_pwminitialize(3); if (!pwm) { @@ -142,7 +142,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32l4_pwminitialize(4); if (!pwm) { @@ -160,7 +160,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) +#if defined(CONFIG_STM32_TIM5_PWM) pwm = stm32l4_pwminitialize(5); if (!pwm) { @@ -178,7 +178,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) +#if defined(CONFIG_STM32_TIM8_PWM) pwm = stm32l4_pwminitialize(8); if (!pwm) { @@ -196,7 +196,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32l4_pwminitialize(15); if (!pwm) { @@ -214,7 +214,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32l4_pwminitialize(16); if (!pwm) { @@ -232,7 +232,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32_TIM17_PWM) pwm = stm32l4_pwminitialize(17); if (!pwm) { @@ -250,7 +250,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) pwm = stm32l4_lp_pwminitialize(1); if (!pwm) { @@ -268,7 +268,7 @@ int stm32l4_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM2_PWM) pwm = stm32l4_lp_pwminitialize(2); if (!pwm) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index a787754741543..1b681ad9234d2 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -39,8 +39,8 @@ #include "nucleo-l476rg.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32l4_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32l4_spibus_initialize(1); @@ -88,7 +88,7 @@ void weak_function stm32l4_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32l4_spibus_initialize(2); @@ -131,7 +131,7 @@ void weak_function stm32l4_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -168,7 +168,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -189,7 +189,7 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l4_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_PCD8544 @@ -247,14 +247,14 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -262,4 +262,4 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c index d41d00e3f60be..73192327542db 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "SD driver requires CONFIG_STM32_SPI1 to be enabled" #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 7aa8a010e5acd..76a55fa31571e 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -55,20 +55,20 @@ * LSE: 32.768 kHz */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ +#define STM32_LSE_FREQUENCY 32768 #define MSI_CLOCK_CONFIG #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI +#define STM32_BOARD_USEHSI /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -79,13 +79,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -99,71 +99,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -174,11 +174,11 @@ #elif defined(HSE_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSE +#define STM32_BOARD_USEHSE /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz @@ -189,13 +189,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -209,71 +209,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -284,12 +284,12 @@ #elif defined(MSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEMSI -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz @@ -300,13 +300,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -320,71 +320,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -400,19 +400,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /* SDMMC dividers. * Note that slower clocking is required when DMA is disabled @@ -673,4 +673,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L496ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h index e4e2a78aa0e85..f51b90eb9f764 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h +++ b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H -#define __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H +#define __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H /**************************************************************************** * Included Files @@ -103,7 +103,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -114,7 +114,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32L4_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -240,7 +240,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -276,9 +276,9 @@ int stm32_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L496ZG_SRC_NUCLEO_144_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L496ZG_SRC_NUCLEO_144_H */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 83b338839af64..d13e24b1a7f04 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -48,19 +48,19 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 #endif -#if STM32L4_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 #endif -#if STM32L4_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -77,7 +77,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] = { 3 @@ -98,7 +98,7 @@ static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] = { 4, @@ -111,7 +111,7 @@ static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static const uint8_t g_chanlist_adc3[ADC3_NCHANNELS] = { 17, @@ -153,7 +153,7 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { if (g_pinlist_adc1[i] != 0) @@ -163,7 +163,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { if (g_pinlist_adc2[i] != 0) @@ -173,7 +173,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 for (i = 0; i < ADC3_NCHANNELS; i++) { if (g_pinlist_adc3[i] != 0) @@ -187,7 +187,7 @@ int stm32_adc_setup(void) * interface */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 adc = stm32l4_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); if (adc == NULL) { @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 adc = stm32l4_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); if (adc == NULL) { @@ -223,7 +223,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 adc = stm32l4_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); if (adc == NULL) { @@ -249,5 +249,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c index a195c97e0191e..f6d407ce38ecf 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c @@ -64,7 +64,7 @@ void stm32l4_board_initialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32L4_OTGFS) || defined(CONFIG_STM32L4_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c index 06a09421d54df..4d22994d3bac8 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c @@ -40,16 +40,16 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) struct i2c_master_s *i2c1; #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) struct i2c_master_s *i2c2; #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) struct i2c_master_s *i2c3; #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) struct i2c_master_s *i2c4; #endif @@ -102,7 +102,7 @@ int stm32_bringup(void) syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); @@ -161,29 +161,29 @@ int stm32_bringup(void) /* REVISIT: this is ugly! */ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c1 = stm32l4_i2cbus_initialize(1); #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) i2c2 = stm32l4_i2cbus_initialize(2); #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) i2c3 = stm32l4_i2cbus_initialize(3); #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) i2c4 = stm32l4_i2cbus_initialize(4); #endif #ifdef CONFIG_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c_register(i2c1, 1); #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) i2c_register(i2c2, 2); #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) i2c_register(i2c3, 3); #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) i2c_register(i2c4, 4); #endif #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c index 9a303be8f8c14..adbda65eeab25 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c @@ -41,11 +41,11 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac1; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 static struct dac_dev_s *g_dac2; #endif @@ -65,7 +65,7 @@ int stm32_dac_setup(void) { int ret; -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 g_dac1 = stm32l4_dacinitialize(0); if (g_dac1 == NULL) { @@ -81,7 +81,7 @@ int stm32_dac_setup(void) } #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 g_dac2 = stm32l4_dacinitialize(1); if (g_dac2 == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c index 39751a7adad50..732ac134a48f3 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c @@ -35,7 +35,7 @@ #include "stm32l4_dfsdm.h" #include "nucleo-144.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -53,28 +53,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -88,7 +88,7 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { @@ -104,7 +104,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { @@ -120,7 +120,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { @@ -136,7 +136,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { @@ -157,4 +157,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 5dc14e26e1459..031e36dd9fc0a 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -95,7 +95,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -121,7 +121,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -147,7 +147,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -174,13 +174,13 @@ static const uint32_t g_spi3gpio[] = #endif #if defined(CONFIG_NUCLEO_SPI_TEST) -# if defined(CONFIG_STM32L4_SPI1) +# if defined(CONFIG_STM32_SPI1) struct spi_dev_s *spi1; # endif -# if defined(CONFIG_STM32L4_SPI2) +# if defined(CONFIG_STM32_SPI2) struct spi_dev_s *spi2; # endif -# if defined(CONFIG_STM32L4_SPI3) +# if defined(CONFIG_STM32_SPI3) struct spi_dev_s *spi3; # endif #endif @@ -201,7 +201,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -211,7 +211,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -221,7 +221,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -258,7 +258,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -279,7 +279,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -300,7 +300,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -345,21 +345,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index 4e6e5010ed82b..77619c6b3c358 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32l4_otgfs.h" #include "nucleo-144.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32l4_configgpio(GPIO_OTGFS_VBUS); stm32l4_configgpio(GPIO_OTGFS_PWRON); stm32l4_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 7c5ffc6ddfb78..0526495312eb5 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -37,16 +37,16 @@ /* System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -62,11 +62,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -106,7 +106,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -125,7 +125,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -147,7 +147,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -165,7 +165,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -176,13 +176,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -196,87 +196,87 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Pre-processor Definitions @@ -357,4 +357,4 @@ #define GPIO_OTGFS_ID GPIO_OTGFS_ID_0 /* PA10 */ #define GPIO_OTGFS_SOF GPIO_OTGFS_SOF_0 /* PA8 */ -#endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_STLCS01V1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h index b206a8d27d897..79a708e8ad23f 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H -#define __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H +#ifndef __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H +#define __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H /**************************************************************************** * Included Files @@ -93,8 +93,8 @@ int stm32l4_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32l4_usbinitialize(void); #endif -#endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ +#endif /* __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 08d07d743c6cb..3c9239dbe7f7b 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -60,7 +60,7 @@ void stm32l4_board_initialize(void) * selected. */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Enable Vddusb - mandatory to use the USB OTG FS peripheral */ stm32l4_pwr_enableusv(true); diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index 933115652dbfb..506e5774dfc00 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -39,7 +39,7 @@ #include "stm32l4_otgfs.h" #include "steval-stlcs01v1.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -48,7 +48,7 @@ #if defined(CONFIG_USBDEV) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but not CONFIG_USBDEV" +# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" # undef HAVE_USB #endif @@ -99,4 +99,4 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/board.h b/boards/arm/stm32l4/stm32l476-mdk/include/board.h index 679e0d42ce82d..23a7b1bfe08f6 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/board.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/board.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -218,4 +218,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index ce9c293eddccf..7522919c39291 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -35,8 +35,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H /**************************************************************************** * Included Files @@ -59,9 +59,9 @@ * LSE - not installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -79,13 +79,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -96,13 +96,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,65 +116,65 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -185,76 +185,76 @@ /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Disable LSE (for the RTC) */ -#undef STM32L4_USE_LSE +#undef STM32_USE_LSE /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -263,19 +263,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data @@ -302,4 +302,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_INCLUDE_STM32L476_MDK_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 328eb3c834a47..b0d6337920f73 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32l4_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h b/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h index 31aae781ccc8c..c9995d42afc39 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32l476-mdk.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H -#define __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H +#ifndef __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H +#define __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H /**************************************************************************** * Included Files @@ -154,4 +154,4 @@ int stm32_bringup(void); void stm32_spiinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L476_MDK_SRC_STM32L476_MDK_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476_MDK_SRC_STM32L476_MDK_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h index 1923d5b3055b8..dfc573d046b5a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -299,4 +299,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h b/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h index fcc418943a8c5..63954f61754eb 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/boardctl.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ #define BIOC_ENTER_MEMMAP BOARDIOC_USER+1 #define BIOC_EXIT_MEMMAP BOARDIOC_USER+2 -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_BOARDCTL_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index d336955276ea1..95845e26c5e2a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H /**************************************************************************** * Included Files @@ -51,9 +51,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -75,13 +75,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -91,13 +91,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -111,42 +111,42 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -155,17 +155,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -174,14 +174,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -189,78 +189,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -268,71 +268,71 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -343,19 +343,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -382,4 +382,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_INCLUDE_STM32L476VG_DISCO_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index 74a290c5550b3..7de1834ade3c3 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -68,7 +68,7 @@ void stm32l4_board_initialize(void) stm32l4_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index 5257fe5408b0a..6e1538a154672 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32l4_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c index f5aa212e95510..4c24a207ffdd1 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32l4_otgfs.h" #include "stm32l476vg-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32l4_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32l4_configgpio(GPIO_OTGFS_VBUS); stm32l4_configgpio(GPIO_OTGFS_PWRON); stm32l4_configgpio(GPIO_OTGFS_OVER); @@ -325,4 +325,4 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h index a8e921a60d079..5250776f9a137 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H -#define __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H +#define __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H /**************************************************************************** * Included Files @@ -74,7 +74,7 @@ # undef HAVE_N25QXXX_CHARDEV #endif -#ifndef CONFIG_STM32L4_QSPI +#ifndef CONFIG_STM32_QSPI # undef HAVE_N25QXXX # undef HAVE_N25QXXX_NXFFS # undef HAVE_N25QXXX_SMARTFS @@ -116,7 +116,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -283,4 +283,4 @@ void stm32_spiinitialize(void); void stm32l4_usbinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h index cabf4cd5f4768..132506d36fd0d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -293,4 +293,4 @@ void stm32l4_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h index 30454d90bfb40..286cff6a34e6e 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/boardctl.h @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ #define BIOC_ENTER_MEMMAP BOARDIOC_USER+1 #define BIOC_EXIT_MEMMAP BOARDIOC_USER+2 -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_BOARDCTL_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index ddc8d01fb149e..1ed98a871a886 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H /**************************************************************************** * Included Files @@ -53,13 +53,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 -#define STM32L4_HSE_FREQUENCY 16000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 16000000ul -#define STM32L4_SYSCLK_FREQUENCY 120000000ul -#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_SYSCLK_FREQUENCY 120000000ul +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY /* Higher SYSCLK requires more flash wait states. */ @@ -81,11 +81,11 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -96,13 +96,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,47 +116,47 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* AHB clock (HCLK) is SYSCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -165,17 +165,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -184,18 +184,18 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -206,13 +206,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -226,73 +226,73 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz @@ -303,13 +303,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -323,62 +323,62 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif /* clock selection */ @@ -388,19 +388,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data @@ -427,4 +427,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_INCLUDE_STM32L4R9AI_DISCO_CLOCKING_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c index 0e26c9ca5e998..1e5318b529f19 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c @@ -111,7 +111,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -274,7 +274,7 @@ int stm32l4_adc_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index ccc12956c6a36..481741f8ed8dc 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -64,11 +64,11 @@ void stm32l4_board_initialize(void) * function stm32_spiinitialize() has been brought into the link. */ -#ifdef CONFIG_STM32L4_SPI +#ifdef CONFIG_STM32_SPI stm32_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index ae5c959cc3404..4b3be3c8dbc51 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -65,10 +65,10 @@ ****************************************************************************/ #ifdef CONFIG_I2C -# ifdef CONFIG_STM32L4_I2C1 +# ifdef CONFIG_STM32_I2C1 static struct i2c_master_s *g_i2c1; # endif -# ifdef CONFIG_STM32L4_I2C3 +# ifdef CONFIG_STM32_I2C3 static struct i2c_master_s *g_i2c3; # endif #endif @@ -135,14 +135,14 @@ int stm32_bringup(void) #ifdef CONFIG_I2C i2cinfo("Initializing I2C buses\n"); -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 g_i2c1 = stm32l4_i2cbus_initialize(1); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c1, 1); #endif #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 g_i2c3 = stm32l4_i2cbus_initialize(3); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c3, 3); @@ -178,7 +178,7 @@ int stm32_bringup(void) ainfo("Initializing ADC\n"); stm32l4_adc_setup(); -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index e17b57ba7fddf..812e680b3fb78 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -52,122 +52,122 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32l4_board_clockconfig(void) { uint32_t regval; /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -175,36 +175,36 @@ void stm32l4_board_clockconfig(void) * data cache, and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c index 99e82f4d6d257..fce4aada4f5ec 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c @@ -57,7 +57,7 @@ int stm32l4_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32l4_dacinitialize(0); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c index ba31c3d3d17ec..7152d47ff4352 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c @@ -38,7 +38,7 @@ #include -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -56,28 +56,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -91,7 +91,7 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { @@ -107,7 +107,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { @@ -123,7 +123,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { @@ -139,7 +139,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { @@ -160,4 +160,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index f86e4621d120c..5ecc111d80d47 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "stm32l4r9ai-disco.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,13 +48,13 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -72,7 +72,7 @@ struct spi_dev_s *g_spi3; void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices on SPI1 */ g_spi1 = stm32l4_spibus_initialize(1); @@ -90,7 +90,7 @@ void weak_function stm32_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices on SPI2 */ g_spi2 = stm32l4_spibus_initialize(2); @@ -106,7 +106,7 @@ void weak_function stm32_spiinitialize(void) #warning No devices specified on SPI2 #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices on SPI3 */ g_spi3 = stm32l4_spibus_initialize(3); @@ -149,7 +149,7 @@ void weak_function stm32_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -170,7 +170,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -184,7 +184,7 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32l4_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -222,21 +222,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -244,4 +244,4 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c index d36a3b179523a..e08a822848536 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32l4_otgfs.h" #include "stm32l4r9ai-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32l4_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32l4_configgpio(GPIO_OTGFS_VBUS); stm32l4_configgpio(GPIO_OTGFS_PWRON); stm32l4_configgpio(GPIO_OTGFS_OVER); @@ -326,4 +326,4 @@ void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h index b3e2fa0db7fb8..036583c316bcb 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H -#define __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H +#ifndef __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H +#define __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H /**************************************************************************** * Included Files @@ -67,7 +67,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -188,10 +188,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif @@ -252,7 +252,7 @@ int stm32l4_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif @@ -276,4 +276,4 @@ void stm32_spiinitialize(void); void stm32l4_usbinitialize(void); -#endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ +#endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 1cea1f1689eea..2ec0901258236 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -45,16 +45,16 @@ * * System Clock source : PLL (MSI) * SYSCLK(Hz) : 110000000 Determined by PLL configuration - * HCLK(Hz) : 110000000 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * AHB Prescaler : 1 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * APB1 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE1) (Max 110MHz) - * APB2 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE2) (Max 110MHz) + * HCLK(Hz) : 110000000 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 110MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 110MHz) * MSI Frequency(Hz) : 4000000 (nominal) - * PLLM : 1 (STM32L5_PLLCFG_PLLM) - * PLLN : 55 (STM32L5_PLLCFG_PLLN) - * PLLP : 0 (STM32L5_PLLCFG_PLLP) - * PLLQ : 0 (STM32L5_PLLCFG_PLLQ) - * PLLR : 2 (STM32L5_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 55 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * Flash Latency(WS) : 5 */ @@ -65,84 +65,84 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_BOARD_USEMSI 1 -#define STM32L5_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* prescaler common to all PLL inputs */ -#define STM32L5_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L5_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) -#define STM32L5_PLLCFG_PLLP 0 -#undef STM32L5_PLLCFG_PLLP_ENABLED -#define STM32L5_PLLCFG_PLLQ 0 -#undef STM32L5_PLLCFG_PLLQ_ENABLED -#define STM32L5_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L5_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L5_PLLSAI1CFG_PLLP 0 -#undef STM32L5_PLLSAI1CFG_PLLP_ENABLED -#define STM32L5_PLLSAI1CFG_PLLQ 0 -#undef STM32L5_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L5_PLLSAI1CFG_PLLR 0 -#undef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L5_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L5_PLLSAI2CFG_PLLP 0 -#undef STM32L5_PLLSAI2CFG_PLLP_ENABLED -#define STM32L5_PLLSAI2CFG_PLLR 0 -#undef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L5_SYSCLK_FREQUENCY 110000000ul +#define STM32_SYSCLK_FREQUENCY 110000000ul /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG) -# define STM32L5_USE_CLK48 1 -# define STM32L5_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC and for MSI autotrimming) */ -#define STM32L5_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L5_PCLK1_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB1_TIM2_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM3_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM4_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM5_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM6_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM7_CLKIN (STM32L5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB2_TIM1_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM15_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM16_CLKIN (STM32L5_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -150,17 +150,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ @@ -280,4 +280,4 @@ void stm32l5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L552ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h index 847c837138c33..bc0eaf8ef96fb 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h +++ b/boards/arm/stm32l5/nucleo-l552ze/src/nucleo-l552ze.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H -#define __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H +#define __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H /**************************************************************************** * Included Files @@ -116,4 +116,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_L552ZE_SRC_NUCLEO_L552ZE_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 05cd210fce068..c90a4df31f86e 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32l5_board_initialize(void) { stm32l5_pwr_vddio2_valid(true); -#if defined(CONFIG_STM32L5_LPUART1) +#if defined(CONFIG_STM32_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in * stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 395095c7b9c3e..8505bcf7942fa 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -67,15 +67,15 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_MSI_FREQUENCY 4000000ul -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_MSI_FREQUENCY 4000000ul +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_SYSCLK_FREQUENCY 110000000ul -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_PCLK1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_SYSCLK_FREQUENCY 110000000ul +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -83,17 +83,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ @@ -203,4 +203,4 @@ void stm32l5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_STM32L562E_DK_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_STM32L562E_DK_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index 170aab2fe92d9..fca2b1c633284 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -37,13 +37,13 @@ * Currently the STM32L562E-DK board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32l5_board_clockconfig(void) { } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h index 1352d9c3d8f43..8f6006fb682f4 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32l562e-dk.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H -#define __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H +#ifndef __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H +#define __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H /**************************************************************************** * Included Files @@ -113,4 +113,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32L5_STM32L562E_DK_SRC_STM32L562E_DK_H */ +#endif /* __BOARDS_ARM_STM32_STM32L562E_DK_SRC_STM32L562E_DK_H */ diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h index 997a4137f557e..18b7c879d3765 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -181,4 +181,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h b/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h index af0f6bfb37464..62bf8ff273633 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h +++ b/boards/arm/stm32n6/nucleo-n657x0-q/src/nucleo-n657x0-q.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H -#define __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H +#define __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32N6_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_N657X0_Q_SRC_NUCLEO_N657X0_Q_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h index fc900c526b2d9..e0165c42c9d9e 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h +++ b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -197,4 +197,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_B_U585I_IOT02A_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_B_U585I_IOT02A_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h b/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h index 7e383e0bbf388..be0c769b5364e 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/b-u585i-iot02a.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H -#define __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H +#ifndef __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H +#define __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ void stm32_spidev_initialize(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H */ +#endif /* __BOARDS_ARM_STM32_B_U585I_IOT02A_SRC_B_U585I_IOT02A_H */ diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c index b6aa7c6a37197..fb7cc8153096e 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c @@ -43,7 +43,7 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c index 4bea93db07188..13bd3f7989538 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-u585i-iot02a.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h index e8636105d0a17..3ba1bc1f1346b 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -203,4 +203,4 @@ void stm32_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h index 2fa799df2c3e5..3d1752c0fb169 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/nucleo-u5a5zj-q.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H -#define __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H +#define __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ void stm32_spidev_initialize(void); int stm32_bringup(void); #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32U5_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_U5A5ZJ_Q_SRC_NUCLEO_U5A5ZJ_Q_H */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c index 2d246c3377f45..5cde87263ab16 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c @@ -118,7 +118,7 @@ int stm32_bringup(void) return -1; } -#if defined(STM32U5_I2C2) +#if defined(STM32_I2C2) i2c2_m = stm32_i2cbus_initialize(2); if (i2c2_m == NULL) { diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c index 24afdb388badf..bfeb3ec7d5746 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c @@ -43,7 +43,7 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c index efae2e53942f8..34e5a5352dd6b 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-u5a5zj-q.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index e00cf8ce7ae94..3fd4a8e6665ac 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -84,13 +84,13 @@ /* LCD */ -#define STM32WB_LCD_SPINO 2 /* SPI2 */ +#define STM32_LCD_SPINO 2 /* SPI2 */ -#define STM32WB_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN11) -#define STM32WB_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define STM32WB_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) /**************************************************************************** @@ -131,4 +131,4 @@ void stm32wb_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index ce6734fd5a602..a2ac79cd543a2 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H /**************************************************************************** * Included Files @@ -51,10 +51,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -71,145 +71,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -218,18 +218,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ @@ -260,4 +260,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_INCLUDE_FLIPPERZERO_CLOCKING_H */ diff --git a/boards/arm/stm32wb/flipperzero/src/flipperzero.h b/boards/arm/stm32wb/flipperzero/src/flipperzero.h index b7b1015a42424..feaab95878f60 100644 --- a/boards/arm/stm32wb/flipperzero/src/flipperzero.h +++ b/boards/arm/stm32wb/flipperzero/src/flipperzero.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H -#define __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H +#ifndef __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H +#define __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H /**************************************************************************** * Included Files @@ -94,4 +94,4 @@ void weak_function stm32wb_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_FLIPPERZERO_SRC_FLIPPERZERO_H */ +#endif /* __BOARDS_ARM_STM32_FLIPPERZERO_SRC_FLIPPERZERO_H */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index b83f7f7bab36d..824b7657b122b 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -183,7 +183,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32wb_blehci_initialize(); diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index ed22e8917b2cb..4eea343833db8 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -83,23 +83,23 @@ static struct st7565_lcd_s g_st7565_dev = static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32WB_LCD_RST, !on); + stm32wb_gpiowrite(STM32_LCD_RST, !on); } static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 0); + stm32wb_gpiowrite(STM32_LCD_CS, 0); } static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 1); + stm32wb_gpiowrite(STM32_LCD_CS, 1); } static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32WB_LCD_A0, !cmd); + stm32wb_gpiowrite(STM32_LCD_A0, !cmd); } static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, @@ -124,14 +124,14 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32WB_LCD_RST); - stm32wb_configgpio(STM32WB_LCD_A0); + stm32wb_configgpio(STM32_LCD_RST); + stm32wb_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32WB_LCD_SPINO); + g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { - lcderr("ERROR: Failed to initialize SPI port %d\n", STM32WB_LCD_SPINO); + lcderr("ERROR: Failed to initialize SPI port %d\n", STM32_LCD_SPINO); return -ENODEV; } @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32WB_LCD_RST, 0); + stm32wb_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32WB_LCD_RST, 1); + stm32wb_gpiowrite(STM32_LCD_RST, 1); return OK; } @@ -156,12 +156,12 @@ struct lcd_dev_s *board_lcd_getdev(int lcddev) if (!g_lcddev) { lcderr("ERROR: Failed to bind SPI port %d to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); } else { lcdinfo("SPI port %d bound to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index a655b0f4f624c..73c786f5b8a9d 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -55,7 +55,7 @@ void weak_function stm32wb_spidev_initialize(void) */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32WB_LCD_CS); /* ST7565 chip select */ + stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } @@ -85,13 +85,13 @@ void weak_function stm32wb_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32WB_LCD_CS, !selected); + stm32wb_gpiowrite(STM32_LCD_CS, !selected); } #endif } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h index 328fba31d5f0a..f2c7d7d485140 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -201,4 +201,4 @@ void stm32wb_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index d48843b2736c3..8c3ef4e018927 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H /**************************************************************************** * Included Files @@ -52,10 +52,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -72,145 +72,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -219,18 +219,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ @@ -261,4 +261,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h index 3a3dc06255c92..89179756bec40 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H -#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H +#define __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H /**************************************************************************** * Included Files @@ -97,4 +97,4 @@ ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WB55RG_SRC_NUCLEO_WB55RG_H */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index a8199219abe59..62991d13e56ed 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -164,7 +164,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32wb_blehci_initialize(); diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 673b0232ecb88..7b19cafb8f218 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H /**************************************************************************** * Included Files @@ -36,72 +36,72 @@ /* nucleo-wl55jc has installed 32Mhz HSE oscillator */ -#define STM32WL5_XTAL_FREQ 32000000ul +#define STM32_XTAL_FREQ 32000000ul /* Use the HSE */ -#define STM32WL5_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* HSE source is a TCXO crystal which needs to be first powered on */ -#define STM32WL5_BOARD_USETCXO +#define STM32_BOARD_USETCXO /* Prescaler common to all PLL inputs */ -#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ /* 'main' PLL config; we use this to generate our system clock */ /* disable unused pll clocks */ -#define STM32WL5_PLLCFG_PLLP 0 -#undef STM32WL5_PLLCFG_PLLP_ENABLED -#define STM32WL5_PLLCFG_PLLQ 0 -#undef STM32WL5_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED /* further multiplicate source for system clock */ -#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ -#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ -#define STM32WL5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ +#define STM32_PLLCFG_PLLR_ENABLED /* Resulting system clock is 48MHz */ -#define STM32WL5_SYSCLK_FREQUENCY 48000000ul +#define STM32_SYSCLK_FREQUENCY 48000000ul /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the HCLK3 divisor (for flash and sram2) */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ -#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ +#define STM32_HCLK3_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -109,13 +109,13 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Pre-processor Definitions @@ -249,4 +249,4 @@ void stm32wl5_board_initialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_INCLUDE_BOARD_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WL55JC_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h index c25831b622ef4..e54ca1e97bdd3 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H -#define __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H +#ifndef __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H +#define __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H /**************************************************************************** * Included Files @@ -177,4 +177,4 @@ void stm32wl5_spidev_initialize(void); int ipcc_init(void); -#endif /* __BOARDS_ARM_STM32WL5_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H */ +#endif /* __BOARDS_ARM_STM32_NUCLEO_WL55JC_SRC_NUCLEO_WL55JC_H */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c index b823f818470ad..cd93826536b45 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c @@ -108,7 +108,7 @@ void board_late_initialize(void) { int ret; -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) stm32wl5_spidev_initialize(); #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index ec04c1555a604..16b1724823082 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -91,7 +91,7 @@ # warning "There is unused space on flash" #endif -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE /**************************************************************************** * Private Definitions diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c index 1e1275e2ce4be..4999fb03b68b4 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "stm32wl5.h" #include "nucleo-wl55jc.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32wl5_spidev_initialize(void) { -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32wl5_spibus_initialize(1); @@ -123,7 +123,7 @@ void weak_function stm32wl5_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -178,7 +178,7 @@ int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h index 104118bba9e4e..10e86617cbf77 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32wl5_ssd1680.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H -#define __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H +#ifndef __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H +#define __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ struct lcd_dev_s *board_ssd1680_getdev(void); } #endif -#endif /* __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32WL5_SSD1680_H */ \ No newline at end of file +#endif /* __BOARDS_ARM_STMWL5_NUCLEO_WL55JC_INCLUDE_STM32_SSD1680_H */ \ No newline at end of file From 69e431e8852b2aa4fcb8f05439dabf646bd4d67a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:21:36 +0200 Subject: [PATCH 03/52] !arm/stm32f7: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32F7 APIs were renamed from stm32f7_* and stm32f7x9_* forms to canonical stm32_* names. Signed-off-by: raiden00pl --- arch/arm/src/stm32f7/stm32_qspi.c | 12 ++++++------ arch/arm/src/stm32f7/stm32_qspi.h | 6 +++--- arch/arm/src/stm32f7/stm32_rcc.h | 8 ++++---- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 8 ++++---- boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c | 2 +- .../stm32f7/stm32f777zit6-meadow/src/stm32_boot.c | 6 +++--- 6 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 7be8093873074..0bbc0f9659943 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -2489,7 +2489,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2502,7 +2502,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32f7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32f7_qspidev_s *priv; uint32_t regval; @@ -2625,7 +2625,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32f7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2639,7 +2639,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf) * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { @@ -2717,7 +2717,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32f7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2730,7 +2730,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32f7_qspidev_s *priv = (struct stm32f7_qspidev_s *)dev; diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index 9a32fddf891d2..edeeea7157aaf 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,7 +101,7 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); @@ -119,7 +119,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index a12de0c0471d2..e96050d0cea19 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -218,24 +218,24 @@ void stm32_rcc_disablelsi(void); #if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void); +void stm32_rcc_dsisrcphy(void); /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void); +void stm32_rcc_dsisrcpllr(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index c8c21e693db08..a7046107ba069 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -1040,14 +1040,14 @@ static inline void rcc_enableperipherals(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void) +void stm32_rcc_dsisrcphy(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); @@ -1058,14 +1058,14 @@ void stm32f7x9_rcc_dsisrcphy(void) } /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void) +void stm32_rcc_dsisrcpllr(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c index 6524920c68034..3249fb4ac01cb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c @@ -81,7 +81,7 @@ int stm32_n25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32f7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index a430e4cfef21f..6e1fa08f1e1fb 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -46,7 +46,7 @@ /* MEADOW FIXME: header clash? */ -extern struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +extern struct qspi_dev_s *stm32_qspi_initialize(int intf); #endif /**************************************************************************** @@ -132,7 +132,7 @@ void board_late_initialize(void) int ret; - qspi = stm32f7_qspi_initialize(0); + qspi = stm32_qspi_initialize(0); if (!qspi) { syslog(LOG_ERR, "ERROR: sam_qspi_initialize failed\n"); @@ -159,7 +159,7 @@ void board_late_initialize(void) meminfo.buflen = 0; meminfo.buffer = NULL; - stm32f7_qspi_enter_memorymapped(qspi, &meminfo, 80000000); + stm32_qspi_enter_memorymapped(qspi, &meminfo, 80000000); /* FIXME: stm32_mpu_uheap depends on PROTECTED && MPU * From 8e583d570b8ad54c8437f30a639bdbade7aaf621 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:22:18 +0200 Subject: [PATCH 04/52] !arm/stm32h5: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32H5 APIs were renamed from stm32h5_* forms to canonical stm32_* forms. Signed-off-by: raiden00pl --- arch/arm/src/stm32h5/stm32_adc.c | 4 ++-- arch/arm/src/stm32h5/stm32_adc.h | 4 ++-- arch/arm/src/stm32h5/stm32_dts.c | 2 +- arch/arm/src/stm32h5/stm32_dts.h | 2 +- arch/arm/src/stm32h5/stm32_flash.h | 10 +++++----- arch/arm/src/stm32h5/stm32_hsi48.c | 8 ++++---- arch/arm/src/stm32h5/stm32_hsi48.h | 8 ++++---- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 10 +++++----- arch/arm/src/stm32h5/stm32_usbdrdhost.h | 10 +++++----- arch/arm/src/stm32h5/stm32h563xx_flash.c | 20 +++++++++---------- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_adc.c | 4 ++-- .../arm/stm32h5/nucleo-h563zi/src/stm32_dts.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_usb.c | 6 +++--- 14 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index b4e73de4960c7..7d2136db6c694 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -2585,10 +2585,10 @@ static int adc_timinit(struct stm32_dev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize ****************************************************************************/ -struct adc_dev_s *stm32h5_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index fe0c523b27407..ec1aca6e19b41 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -500,7 +500,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -516,7 +516,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h5_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN diff --git a/arch/arm/src/stm32h5/stm32_dts.c b/arch/arm/src/stm32h5/stm32_dts.c index a6d9d63134ac5..b6d5067869fb5 100644 --- a/arch/arm/src/stm32h5/stm32_dts.c +++ b/arch/arm/src/stm32h5/stm32_dts.c @@ -538,7 +538,7 @@ static int stm32_dts_isr(int irq, void *context, void *arg) * Name: stm32_dts_register ****************************************************************************/ -int stm32h5_dts_register(int devno) +int stm32_dts_register(int devno) { int ret; diff --git a/arch/arm/src/stm32h5/stm32_dts.h b/arch/arm/src/stm32h5/stm32_dts.h index 67e796699a992..560ef39cfdb83 100644 --- a/arch/arm/src/stm32h5/stm32_dts.h +++ b/arch/arm/src/stm32h5/stm32_dts.h @@ -65,7 +65,7 @@ extern "C" #define EXTERN extern #endif -int stm32h5_dts_register(int devno); +int stm32_dts_register(int devno); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_flash.h b/arch/arm/src/stm32h5/stm32_flash.h index bb0220a9215f9..6afaad7a1dcd3 100644 --- a/arch/arm/src/stm32h5/stm32_flash.h +++ b/arch/arm/src/stm32h5/stm32_flash.h @@ -45,16 +45,16 @@ extern "C" #define EXTERN extern #endif -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2); +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2); -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, uint32_t clear2, uint32_t set2); -int stm32h5_flash_swapbanks(void); +int stm32_flash_swapbanks(void); -void stm32h5_flash_lock(void); +void stm32_flash_lock(void); -void stm32h5_flash_unlock(void); +void stm32_flash_unlock(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index a24ef8a795024..2825f722e9ec5 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -39,7 +39,7 @@ #ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * The HSI48 @@ -65,7 +65,7 @@ * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -134,7 +134,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) } /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -147,7 +147,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32h5_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index fd4579d47a8c6..290bd4713f1c8 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32H5X3, STM32H596xx/4A6xx and STM32H5XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32h5_disable_hsi48(void); +void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 9261419bff7fb..1333ef56ae551 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -2829,7 +2829,7 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) /* Enable VBUS drive */ - stm32h5_usbhost_vbusdrive(0, true); + stm32_usbdrdhost_vbusdrive(0, true); uinfo("USB Host initialized\n"); @@ -2841,14 +2841,14 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void) +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void) { struct stm32_usbhost_s *priv = &g_usbhost; int ret; @@ -2872,7 +2872,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) } /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Control VBUS power @@ -2881,7 +2881,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) ****************************************************************************/ __attribute__((weak)) -void stm32_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* Default implementation - do nothing. * Board-specific code should override this to control VBUS power. diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.h b/arch/arm/src/stm32h5/stm32_usbdrdhost.h index 7821a258a7cfe..a3f07b1be6793 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.h +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.h @@ -63,7 +63,7 @@ * to the board-level USB host logic. */ -struct stm32h5_usbhost_connection_s +struct stm32_usbhost_connection_s { /* Wait for device connection/disconnection */ @@ -90,7 +90,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller hardware. @@ -108,10 +108,10 @@ extern "C" * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void); +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void); /**************************************************************************** - * Name: stm32h5_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable VBUS power to the connected USB device. @@ -133,7 +133,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void); * ****************************************************************************/ -void stm32h5_usbhost_vbusdrive(int port, bool enable); +void stm32_usbdrdhost_vbusdrive(int port, bool enable); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 5519cb02ab731..f1ca7d5d97af6 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -344,14 +344,14 @@ static void flash_lock_opt(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock_nscr(); @@ -359,14 +359,14 @@ void stm32h5_flash_unlock(void) } /**************************************************************************** - * Name: stm32h5_flash_lock + * Name: stm32_flash_lock * * Description: * Lock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock_nscr(); @@ -374,7 +374,7 @@ void stm32h5_flash_lock(void) } /**************************************************************************** - * Name: stm32h5_flash_getopt + * Name: stm32_flash_getopt * * Description: * Read the current flash option bytes from FLASH_OPTSR_CUR and @@ -386,14 +386,14 @@ void stm32h5_flash_lock(void) * ****************************************************************************/ -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2) { *opt1 = getreg32(STM32_FLASH_OPTSR_CUR); *opt2 = getreg32(STM32_FLASH_OPTSR2_CUR); } /**************************************************************************** - * Name: stm32h5_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. @@ -412,7 +412,7 @@ void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) * ****************************************************************************/ -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, uint32_t clear2, uint32_t set2) { int ret; @@ -451,7 +451,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, } /**************************************************************************** - * Name: stm32h5_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -464,7 +464,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, * ****************************************************************************/ -int stm32h5_flash_swapbanks(void) +int stm32_flash_swapbanks(void) { uint32_t reg; bool was_locked; diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 1682747b2fc47..1a55c06229f3e 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -845,7 +845,7 @@ void stm32_rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c index 61e8ffec9b9b7..08f0568ed2484 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c @@ -122,7 +122,7 @@ int stm32_adc_setup(void) stm32_configgpio(g_pinlist1[i]); } - adc1 = stm32h5_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); + adc1 = stm32_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); if (adc1 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); @@ -145,7 +145,7 @@ int stm32_adc_setup(void) stm32_configgpio(g_pinlist2[i]); } - adc2 = stm32h5_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); + adc2 = stm32_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); if (adc2 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c index e2d96c58a4dfa..422b7a3ec5a80 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c @@ -75,7 +75,7 @@ int stm32_dts_setup(int devno) { /* Register the DTS driver at "/dev/sensor_temp0" */ - ret = stm32h5_dts_register(0); + ret = stm32_dts_register(0); if (ret < 0) { aerr("ERROR: dts_register /dev/dts0 failed: %d\n", ret); diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c index 52df87a4c1a80..f0d920a6ce620 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c @@ -185,7 +185,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32h5_usbhost_initialize(); + g_usbconn = stm32_usbdrdhost_initialize(); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -203,7 +203,7 @@ int stm32_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -232,7 +232,7 @@ int stm32_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32h5_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* The Nucleo-h563zi doesn't have hardware for a vbus drive. * Instead to get host working, you need to put an extra jumper From f8536bb427e777750ea57a21e410f8ea7812a55b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:23:50 +0200 Subject: [PATCH 05/52] !arm/stm32h7: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32H7 APIs were renamed from stm32h7_* forms to canonical stm32_* forms. Signed-off-by: raiden00pl --- arch/arm/src/stm32h7/stm32_adc.c | 4 +-- arch/arm/src/stm32h7/stm32_adc.h | 4 +-- arch/arm/src/stm32h7/stm32_dualcore.c | 8 ++--- arch/arm/src/stm32h7/stm32_dualcore.h | 8 ++--- arch/arm/src/stm32h7/stm32_flash.h | 24 +++++++-------- arch/arm/src/stm32h7/stm32_qspi.c | 12 ++++---- arch/arm/src/stm32h7/stm32_qspi.h | 6 ++-- arch/arm/src/stm32h7/stm32_start.c | 4 +-- arch/arm/src/stm32h7/stm32h743xx_flash.c | 30 +++++++++---------- arch/arm/src/stm32h7/stm32h7b3xx_flash.c | 30 +++++++++---------- .../linum-stm32h753bi/src/stm32_w25q.c | 2 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_adc.c | 6 ++-- .../arm/stm32h7/nucleo-h743zi/src/stm32_adc.c | 6 ++-- .../stm32h7/nucleo-h743zi2/src/stm32_adc.c | 4 +-- .../arm/stm32h7/nucleo-h745zi/src/stm32_adc.c | 4 +-- .../arm/stm32h7/nucleo-h753zi/src/stm32_adc.c | 4 +-- .../stm32h7/stm32h747i-disco/src/stm32_adc.c | 4 +-- 17 files changed, 80 insertions(+), 80 deletions(-) diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 7f74f83a65f7f..4597067194e69 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -2277,7 +2277,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2302,7 +2302,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, * ****************************************************************************/ -struct adc_dev_s *stm32h7_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index 67b693fb307d7..a22ebb45e0cff 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -785,7 +785,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -801,7 +801,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h7_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 77092120e0659..145e1cb6a4668 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -137,14 +137,14 @@ static void stm32_cpu2sem_take(void) defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void) +void stm32_start_cm4(void) { uint32_t regval = 0; @@ -177,14 +177,14 @@ void stm32h7_start_cm4(void) #ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void) +void stm32_waitfor_cm7(void) { if (stm32_cm4_boot() == true) { diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index f8f84deddfc32..21dd549499bb2 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -54,26 +54,26 @@ extern "C" defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void); +void stm32_start_cm4(void); #endif #ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void); +void stm32_waitfor_cm7(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32h7/stm32_flash.h b/arch/arm/src/stm32h7/stm32_flash.h index 39481210ddad1..cdd73d3b31ddc 100644 --- a/arch/arm/src/stm32h7/stm32_flash.h +++ b/arch/arm/src/stm32h7/stm32_flash.h @@ -48,27 +48,27 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void); +uint32_t stm32_flash_getopt(void); /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); +void stm32_flash_optmodify(uint32_t clear, uint32_t set); /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -76,37 +76,37 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); * ****************************************************************************/ -void stm32h7_flash_swapbanks(void); +void stm32_flash_swapbanks(void); /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(void); +int stm32_flash_lock(void); /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t page, bool enabled); +int stm32_flash_writeprotect(size_t page, bool enabled); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index f9885a4331392..f5c615e433b90 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -2543,7 +2543,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2556,7 +2556,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32h7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32h7_qspidev_s *priv; uint32_t regval; @@ -2683,7 +2683,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32h7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2697,7 +2697,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf) * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { @@ -2775,7 +2775,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32h7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2788,7 +2788,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev; diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 98da12b1e5368..0db4496ae660c 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32h7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,7 +101,7 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); @@ -119,7 +119,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 9e123c3e2adc3..b2f89d5fc9d94 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -195,7 +195,7 @@ void __start(void) #ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 /* Wait for CM7 initialization done */ - stm32h7_waitfor_cm7(); + stm32_waitfor_cm7(); #endif /* If enabled reset the MPU */ @@ -309,7 +309,7 @@ void __start(void) /* Start CM4 core after clock configuration is done */ - stm32h7_start_cm4(); + stm32_start_cm4(); #endif nx_start(); diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index 70a22bfb4ce10..292fa63d5da02 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -508,14 +508,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -536,14 +536,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -564,14 +564,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -605,14 +605,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -625,14 +625,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -652,7 +652,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -660,16 +660,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index d0cc1d55394a0..2a3756d9f534c 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -478,14 +478,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -506,14 +506,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -534,14 +534,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -575,14 +575,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -595,14 +595,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -622,7 +622,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -630,16 +630,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c index 26a494c7619a6..98c8454c49c6b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c @@ -79,7 +79,7 @@ int stm32_w25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32h7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index de1615329f12e..1a4bc8d2eafa4 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index 31d99bd2bafc3..1b0a972921a9e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index a4f02f1a5cf41..3d2ddaf2c32b5 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index f906cca2e3aa8..cba9c51771b22 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -160,7 +160,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -191,7 +191,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 8871b8f74d9d3..fca934607efbf 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index ce9e0758f3920..de53c2b874209 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -149,7 +149,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -180,7 +180,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); From bde8db7fb6be81076975356b5e641506700889d6 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:33 +0200 Subject: [PATCH 06/52] !arm/stm32l4: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32L4 interfaces were renamed from stm32l4_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names were normalized to stm32_* equivalents (including timer/lptimer/dma/freerun API-facing types), and stm32l4can_initialize() was renamed to stm32_caninitialize(). The STM32L4 root family header was renamed from stm32l4.h to stm32.h; all STM32L4 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32l4/{stm32l4.h => stm32.h} | 2 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 14 +- arch/arm/src/stm32l4/stm32l4_1wire.h | 10 +- arch/arm/src/stm32l4/stm32l4_adc.c | 32 +- arch/arm/src/stm32l4/stm32l4_adc.h | 4 +- arch/arm/src/stm32l4/stm32l4_allocateheap.c | 8 +- arch/arm/src/stm32l4/stm32l4_can.c | 110 +- arch/arm/src/stm32l4/stm32l4_can.h | 4 +- arch/arm/src/stm32l4/stm32l4_comp.c | 72 +- arch/arm/src/stm32l4/stm32l4_comp.h | 32 +- arch/arm/src/stm32l4/stm32l4_dac.c | 58 +- arch/arm/src/stm32l4/stm32l4_dac.h | 8 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 14 +- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 4 +- arch/arm/src/stm32l4/stm32l4_dfumode.c | 4 +- arch/arm/src/stm32l4/stm32l4_dfumode.h | 4 +- arch/arm/src/stm32l4/stm32l4_dma.h | 72 +- arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 4 +- arch/arm/src/stm32l4/stm32l4_exti.h | 16 +- arch/arm/src/stm32l4/stm32l4_exti_alarm.c | 10 +- arch/arm/src/stm32l4/stm32l4_exti_comp.c | 8 +- arch/arm/src/stm32l4/stm32l4_exti_gpio.c | 40 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.c | 10 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.h | 4 +- arch/arm/src/stm32l4/stm32l4_exti_wakeup.c | 10 +- arch/arm/src/stm32l4/stm32l4_firewall.c | 2 +- arch/arm/src/stm32l4/stm32l4_firewall.h | 6 +- arch/arm/src/stm32l4/stm32l4_flash.c | 16 +- arch/arm/src/stm32l4/stm32l4_flash.h | 8 +- arch/arm/src/stm32l4/stm32l4_freerun.c | 32 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 22 +- arch/arm/src/stm32l4/stm32l4_gpio.c | 28 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 36 +- arch/arm/src/stm32l4/stm32l4_hsi48.c | 8 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 8 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 532 +++---- arch/arm/src/stm32l4/stm32l4_i2c.h | 10 +- arch/arm/src/stm32l4/stm32l4_idle.c | 6 +- arch/arm/src/stm32l4/stm32l4_irq.c | 40 +- arch/arm/src/stm32l4/stm32l4_iwdg.c | 112 +- arch/arm/src/stm32l4/stm32l4_lowputc.c | 20 +- arch/arm/src/stm32l4/stm32l4_lowputc.h | 4 +- arch/arm/src/stm32l4/stm32l4_lptim.c | 238 +-- arch/arm/src/stm32l4/stm32l4_lptim.h | 48 +- arch/arm/src/stm32l4/stm32l4_lse.c | 10 +- arch/arm/src/stm32l4/stm32l4_lsi.c | 8 +- arch/arm/src/stm32l4/stm32l4_mpuinit.c | 8 +- arch/arm/src/stm32l4/stm32l4_mpuinit.h | 12 +- arch/arm/src/stm32l4/stm32l4_oneshot.c | 42 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 28 +- .../src/stm32l4/stm32l4_oneshot_lowerhalf.c | 78 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 12 +- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 1318 ++++++++--------- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 1136 +++++++------- arch/arm/src/stm32l4/stm32l4_pm.h | 20 +- arch/arm/src/stm32l4/stm32l4_pmlpr.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmsleep.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmstandby.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmstop.c | 8 +- arch/arm/src/stm32l4/stm32l4_pulsecount.c | 102 +- arch/arm/src/stm32l4/stm32l4_pulsecount.h | 2 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 160 +- arch/arm/src/stm32l4/stm32l4_pwm.h | 28 +- arch/arm/src/stm32l4/stm32l4_pwr.c | 68 +- arch/arm/src/stm32l4/stm32l4_pwr.h | 22 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 304 ++-- arch/arm/src/stm32l4/stm32l4_qencoder.h | 4 +- arch/arm/src/stm32l4/stm32l4_qspi.c | 122 +- arch/arm/src/stm32l4/stm32l4_qspi.h | 12 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 30 +- arch/arm/src/stm32l4/stm32l4_rcc.h | 34 +- arch/arm/src/stm32l4/stm32l4_rng.c | 34 +- arch/arm/src/stm32l4/stm32l4_rtc.c | 90 +- arch/arm/src/stm32l4/stm32l4_rtc.h | 42 +- arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 152 +- arch/arm/src/stm32l4/stm32l4_sai.c | 104 +- arch/arm/src/stm32l4/stm32l4_sai.h | 4 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 28 +- arch/arm/src/stm32l4/stm32l4_serial.c | 208 +-- arch/arm/src/stm32l4/stm32l4_spi.c | 182 +-- arch/arm/src/stm32l4/stm32l4_spi.h | 48 +- arch/arm/src/stm32l4/stm32l4_start.c | 12 +- arch/arm/src/stm32l4/stm32l4_start.h | 4 +- arch/arm/src/stm32l4/stm32l4_tickless.c | 32 +- arch/arm/src/stm32l4/stm32l4_tim.c | 526 +++---- arch/arm/src/stm32l4/stm32l4_tim.h | 58 +- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 110 +- arch/arm/src/stm32l4/stm32l4_timerisr.c | 8 +- arch/arm/src/stm32l4/stm32l4_uart.h | 4 +- arch/arm/src/stm32l4/stm32l4_uid.c | 4 +- arch/arm/src/stm32l4/stm32l4_uid.h | 2 +- arch/arm/src/stm32l4/stm32l4_usbdev.c | 1036 ++++++------- arch/arm/src/stm32l4/stm32l4_usbdev.h | 6 +- arch/arm/src/stm32l4/stm32l4_usbhost.h | 4 +- arch/arm/src/stm32l4/stm32l4_usbhost_trace.c | 6 +- arch/arm/src/stm32l4/stm32l4_userspace.c | 6 +- arch/arm/src/stm32l4/stm32l4_userspace.h | 4 +- arch/arm/src/stm32l4/stm32l4_waste.c | 4 +- arch/arm/src/stm32l4/stm32l4_waste.h | 4 +- arch/arm/src/stm32l4/stm32l4_wdg.h | 8 +- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 14 +- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 12 +- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 110 +- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 18 +- arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 196 +-- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 12 +- .../b-l475e-iot01a/src/b-l475e-iot01a.h | 14 +- .../b-l475e-iot01a/src/stm32_autoleds.c | 6 +- .../stm32l4/b-l475e-iot01a/src/stm32_boot.c | 12 +- .../b-l475e-iot01a/src/stm32_bringup.c | 14 +- .../stm32l4/b-l475e-iot01a/src/stm32_spi.c | 44 +- .../stm32l4/b-l475e-iot01a/src/stm32_spirit.c | 64 +- .../stm32l4/b-l475e-iot01a/src/stm32_timer.c | 24 +- .../b-l475e-iot01a/src/stm32_userleds.c | 12 +- .../arm/stm32l4/nucleo-l432kc/include/board.h | 4 +- .../stm32l4/nucleo-l432kc/src/nucleo-l432kc.h | 32 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_adc.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_at45db.c | 2 +- .../nucleo-l432kc/src/stm32_autoleds.c | 8 +- .../stm32l4/nucleo-l432kc/src/stm32_boot.c | 12 +- .../stm32l4/nucleo-l432kc/src/stm32_bringup.c | 36 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_dac.c | 6 +- .../stm32l4/nucleo-l432kc/src/stm32_dac7571.c | 10 +- .../nucleo-l432kc/src/stm32_dac_wgen.c | 4 +- .../stm32l4/nucleo-l432kc/src/stm32_gpio.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_ina219.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_ina226.c | 10 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c | 18 +- .../nucleo-l432kc/src/stm32_qencoder.c | 6 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 40 +- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_timer.c | 2 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_uid.c | 2 +- .../nucleo-l432kc/src/stm32_userleds.c | 8 +- .../nucleo-l432kc/src/stm32_zerocross.c | 8 +- .../arm/stm32l4/nucleo-l452re/include/board.h | 4 +- .../stm32l4/nucleo-l452re/src/nucleo-l452re.h | 12 +- .../arm/stm32l4/nucleo-l452re/src/stm32_adc.c | 14 +- .../nucleo-l452re/src/stm32_autoleds.c | 6 +- .../stm32l4/nucleo-l452re/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l452re/src/stm32_bringup.c | 6 +- .../stm32l4/nucleo-l452re/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l452re/src/stm32_dac.c | 6 +- .../arm/stm32l4/nucleo-l452re/src/stm32_spi.c | 44 +- .../nucleo-l452re/src/stm32_userleds.c | 10 +- .../stm32l4/nucleo-l476rg/src/nucleo-l476rg.h | 36 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_adc.c | 10 +- .../nucleo-l476rg/src/stm32_ajoystick.c | 10 +- .../stm32l4/nucleo-l476rg/src/stm32_as726x.c | 4 +- .../nucleo-l476rg/src/stm32_autoleds.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_bmp180.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_bmp280.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_boot.c | 12 +- .../stm32l4/nucleo-l476rg/src/stm32_bringup.c | 46 +- .../stm32l4/nucleo-l476rg/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_can.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_cc1101.c | 14 +- .../stm32l4/nucleo-l476rg/src/stm32_gpio.c | 28 +- .../nucleo-l476rg/src/stm32_lsm303agr.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c | 10 +- .../stm32l4/nucleo-l476rg/src/stm32_mpu9250.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_pcd8544.c | 14 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c | 28 +- .../nucleo-l476rg/src/stm32_qencoder.c | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 58 +- .../nucleo-l476rg/src/stm32_spimmcsd.c | 12 +- .../stm32l4/nucleo-l476rg/src/stm32_timer.c | 2 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_uid.c | 2 +- .../nucleo-l476rg/src/stm32_userleds.c | 12 +- .../arm/stm32l4/nucleo-l496zg/include/board.h | 4 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 14 +- .../nucleo-l496zg/src/stm32_autoleds.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_bringup.c | 10 +- .../stm32l4/nucleo-l496zg/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_dac.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_dfsdm.c | 8 +- .../stm32l4/nucleo-l496zg/src/stm32_sdio.c | 14 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_spi.c | 16 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_uid.c | 2 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 14 +- .../nucleo-l496zg/src/stm32_userleds.c | 6 +- .../steval-stlcs01v1/src/steval-stlcs01v1.h | 8 +- .../steval-stlcs01v1/src/stm32_autoleds.c | 8 +- .../stm32l4/steval-stlcs01v1/src/stm32_boot.c | 16 +- .../steval-stlcs01v1/src/stm32_bringup.c | 4 +- .../stm32l4/steval-stlcs01v1/src/stm32_usb.c | 14 +- .../arm/stm32l4/stm32l476-mdk/include/board.h | 4 +- .../stm32l476-mdk/src/stm32_autoleds.c | 10 +- .../stm32l4/stm32l476-mdk/src/stm32_boot.c | 12 +- .../stm32l4/stm32l476-mdk/src/stm32_buttons.c | 6 +- .../stm32l476-mdk/src/stm32_clockconfig.c | 8 +- .../arm/stm32l4/stm32l476-mdk/src/stm32_spi.c | 2 +- .../stm32l476-mdk/src/stm32_userleds.c | 18 +- .../stm32l4/stm32l476vg-disco/include/board.h | 4 +- .../stm32l476vg-disco/src/stm32_autoleds.c | 26 +- .../stm32l476vg-disco/src/stm32_boot.c | 8 +- .../stm32l476vg-disco/src/stm32_bringup.c | 12 +- .../stm32l476vg-disco/src/stm32_buttons.c | 6 +- .../stm32l476vg-disco/src/stm32_clockconfig.c | 8 +- .../stm32l4/stm32l476vg-disco/src/stm32_spi.c | 2 +- .../stm32l4/stm32l476vg-disco/src/stm32_uid.c | 2 +- .../stm32l4/stm32l476vg-disco/src/stm32_usb.c | 40 +- .../stm32l476vg-disco/src/stm32_userleds.c | 30 +- .../stm32l476vg-disco/src/stm32l476vg-disco.h | 4 +- .../stm32l4/stm32l4r9ai-disco/include/board.h | 4 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_adc.c | 14 +- .../stm32l4r9ai-disco/src/stm32_autoleds.c | 26 +- .../stm32l4r9ai-disco/src/stm32_boot.c | 6 +- .../stm32l4r9ai-disco/src/stm32_bringup.c | 16 +- .../stm32l4r9ai-disco/src/stm32_buttons.c | 6 +- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 8 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_dac.c | 6 +- .../stm32l4r9ai-disco/src/stm32_dfsdm.c | 8 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_spi.c | 40 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_uid.c | 2 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_usb.c | 40 +- .../stm32l4r9ai-disco/src/stm32_userleds.c | 30 +- .../stm32l4r9ai-disco/src/stm32l4r9ai-disco.h | 16 +- include/nuttx/analog/ioctl.h | 6 +- 220 files changed, 4956 insertions(+), 4956 deletions(-) rename arch/arm/src/stm32l4/{stm32l4.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32l4/stm32l4.h b/arch/arm/src/stm32l4/stm32.h similarity index 98% rename from arch/arm/src/stm32l4/stm32l4.h rename to arch/arm/src/stm32l4/stm32.h index d4a19deccdf58..b996ad1a7d9ca 100644 --- a/arch/arm/src/stm32l4/stm32l4.h +++ b/arch/arm/src/stm32l4/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l4/stm32l4.h + * arch/arm/src/stm32l4/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 863ae59a689a1..d22c0e8d5a9e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -575,7 +575,7 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Configure pins for USART use */ - stm32l4_configgpio(config->data_pin); + stm32_configgpio(config->data_pin); ret = irq_attach(config->irq, stm32_1wire_isr, priv); if (ret == OK) @@ -604,7 +604,7 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(config->data_pin); + stm32_unconfiggpio(config->data_pin); /* Disable RXNEIE, Rx, Tx, and the USART */ @@ -1125,7 +1125,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -1141,7 +1141,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port) +struct onewire_dev_s *stm32_1wireinitialize(int port) { struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ @@ -1218,13 +1218,13 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) } /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -1232,7 +1232,7 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev) +int stm32_1wireuninitialize(struct onewire_dev_s *dev) { struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h index e033594d51305..9cb407b6ac401 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ b/arch/arm/src/stm32l4/stm32l4_1wire.h @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -52,16 +52,16 @@ * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port); +struct onewire_dev_s *stm32_1wireinitialize(int port); /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -69,6 +69,6 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port); * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev); +int stm32_1wireuninitialize(struct onewire_dev_s *dev); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index e2e7583df0619..ee7347f7f56fd 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -2354,20 +2354,20 @@ static void adc_dma_start(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); #ifndef CONFIG_STM32_ADC_NOIRQ - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, adc_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); #endif } @@ -2544,7 +2544,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, @@ -2552,7 +2552,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, /* No DMA callback */ - stm32l4_dmastart(priv->dma, NULL, dev, false); + stm32_dmastart(priv->dma, NULL, dev, false); return OK; } @@ -2571,19 +2571,19 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } - dev->dma = stm32l4_dmachannel(dev->dmachan); + dev->dma = stm32_dmachannel(dev->dmachan); - stm32l4_dmasetup(dev->dma, + stm32_dmasetup(dev->dma, dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(dev->dma, callback, dev, false); + stm32_dmastart(dev->dma, callback, dev, false); } /**************************************************************************** @@ -2598,8 +2598,8 @@ static void adc_llops_dma_stop(struct stm32_adc_dev_s *adc) if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } } @@ -2678,7 +2678,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2725,7 +2725,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * ****************************************************************************/ -struct adc_dev_s *stm32l4_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int cchannels) { diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index a1c34e43980b0..2584166f1882e 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -600,7 +600,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -616,7 +616,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_adc_initialize(int intf, +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index cf4e6c70c16da..d05e804dff984 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -241,7 +241,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l4_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -319,7 +319,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ @@ -338,7 +338,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM3 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -357,7 +357,7 @@ void arm_addregion(void) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l4_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 4c8316306d6b7..9d6231f4f1f13 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -41,7 +41,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_can.h" #if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) @@ -72,7 +72,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_can_s +struct stm32_can_s { uint8_t port; /* CAN port number (1 or 2) */ uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ @@ -89,20 +89,20 @@ struct stm32l4_can_s /* CAN Register access */ -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset); -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset); -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); #ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg); #else # define stm32l4can_dumpctrlregs(priv,msg) @@ -113,14 +113,14 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, /* Filtering (todo) */ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg); -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg); #endif -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg); -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg); /* CAN driver methods */ @@ -151,11 +151,11 @@ static int stm32l4can_txinterrupt(int irq, void *context, /* Initialization */ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_bittiming(struct stm32l4_can_s *priv); -static int stm32l4can_cellinit(struct stm32l4_can_s *priv); -static int stm32l4can_filterinit(struct stm32l4_can_s *priv); +static int stm32l4can_enterinitmode(struct stm32_can_s *priv); +static int stm32l4can_exitinitmode(struct stm32_can_s *priv); +static int stm32l4can_bittiming(struct stm32_can_s *priv); +static int stm32l4can_cellinit(struct stm32_can_s *priv); +static int stm32l4can_filterinit(struct stm32_can_s *priv); /**************************************************************************** * Private Data @@ -176,7 +176,7 @@ static const struct can_ops_s g_canops = }; #ifdef CONFIG_STM32_CAN1 -static struct stm32l4_can_s g_can1priv = +static struct stm32_can_s g_can1priv = { .port = 1, .canrx = @@ -271,24 +271,24 @@ static uint32_t stm32l4can_vgetreg(uint32_t addr) return val; } -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->fbase + offset); } #else -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->fbase + offset); @@ -325,26 +325,26 @@ static void stm32l4can_vputreg(uint32_t addr, uint32_t value) putreg32(value, addr); } -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->base + offset, value); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->fbase + offset, value); } #else -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->fbase + offset); @@ -366,7 +366,7 @@ static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, ****************************************************************************/ #ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -411,7 +411,7 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -477,7 +477,7 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_CAN_REGDEBUG -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { int i; @@ -526,7 +526,7 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, static void stm32l4can_reset(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; uint32_t regbit = 0; irqstate_t flags; @@ -583,7 +583,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) static int stm32l4can_setup(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; int ret; caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", @@ -670,7 +670,7 @@ static int stm32l4can_setup(struct can_dev_s *dev) static void stm32l4can_shutdown(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; caninfo("CAN%d\n", priv->port); @@ -707,7 +707,7 @@ static void stm32l4can_shutdown(struct can_dev_s *dev) static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); @@ -743,7 +743,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) static void stm32l4can_txint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); @@ -775,7 +775,7 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) { - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; int ret = -ENOTTY; caninfo("cmd=%04x arg=%lu\n", cmd, arg); @@ -1173,7 +1173,7 @@ static int stm32l4can_remoterequest(struct can_dev_s *dev, uint16_t id) static int stm32l4can_send(struct can_dev_s *dev, struct can_msg_s *msg) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint8_t *ptr; uint32_t regval; uint32_t tmp; @@ -1333,7 +1333,7 @@ static int stm32l4can_send(struct can_dev_s *dev, static bool stm32l4can_txready(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if any mailbox is available */ @@ -1364,7 +1364,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev) static bool stm32l4can_txempty(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if all mailboxes are available */ @@ -1394,7 +1394,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; struct can_hdr_s hdr; uint8_t data[CAN_MAXDATALEN]; uint32_t regval; @@ -1552,7 +1552,7 @@ static int stm32l4can_rx1interrupt(int irq, void *context, void *arg) static int stm32l4can_txinterrupt(int irq, void *context, void *arg) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; uint32_t regval; dev = &g_can1dev; @@ -1682,7 +1682,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4can_bittiming(struct stm32l4_can_s *priv) +static int stm32l4can_bittiming(struct stm32_can_s *priv) { uint32_t tmp; uint32_t brp; @@ -1782,7 +1782,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_enterinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; @@ -1833,7 +1833,7 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_exitinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; @@ -1884,7 +1884,7 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_cellinit(struct stm32l4_can_s *priv) +static int stm32l4can_cellinit(struct stm32_can_s *priv) { uint32_t regval; int ret; @@ -1962,7 +1962,7 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_filterinit(struct stm32l4_can_s *priv) +static int stm32l4can_filterinit(struct stm32_can_s *priv) { uint32_t regval; uint32_t bitmask; @@ -2042,7 +2042,7 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg) { return -ENOTTY; @@ -2068,7 +2068,7 @@ static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2091,7 +2091,7 @@ static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg) { return -ENOTTY; @@ -2115,7 +2115,7 @@ static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, * ****************************************************************************/ -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2125,7 +2125,7 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -2138,14 +2138,14 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -struct can_dev_s *stm32l4can_initialize(int port) +struct can_dev_s *stm32_caninitialize(int port) { struct can_dev_s *dev = NULL; caninfo("CAN%d\n", port); /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided - * by stm32l4_clockconfig() early in the reset sequence. + * by stm32_clockconfig() early in the reset sequence. */ #ifdef CONFIG_STM32_CAN1 @@ -2159,8 +2159,8 @@ struct can_dev_s *stm32l4can_initialize(int port) * file must have been disambiguated in the board.h file. */ - stm32l4_configgpio(GPIO_CAN1_RX); - stm32l4_configgpio(GPIO_CAN1_TX); + stm32_configgpio(GPIO_CAN1_RX); + stm32_configgpio(GPIO_CAN1_TX); } else #endif diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index eae9f677c9f0a..2ba3530405420 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -101,7 +101,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -115,7 +115,7 @@ extern "C" ****************************************************************************/ struct can_dev_s; -struct can_dev_s *stm32l4can_initialize(int port); +struct can_dev_s *stm32_caninitialize(int port); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 5ec7986aa9c54..90df1275b718d 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -66,12 +66,12 @@ /* COMP Register access */ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits); -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg); -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg); +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en); -static int stm32l4_compconfig(const struct comp_dev_s *dev); +static int stm32_compconfig(const struct comp_dev_s *dev); /* COMP Driver Methods */ @@ -96,7 +96,7 @@ static const struct comp_ops_s g_compops = .ao_bind = comp_bind, }; -static struct stm32l4_comp_config_s g_comp1priv = +static struct stm32_comp_config_s g_comp1priv = { .interrupt = { @@ -118,7 +118,7 @@ static struct comp_dev_s g_comp1dev = .ad_priv = &g_comp1priv, }; -static struct stm32l4_comp_config_s g_comp2priv = +static struct stm32_comp_config_s g_comp2priv = { .interrupt = { @@ -148,7 +148,7 @@ static struct comp_dev_s g_comp2dev = * Name: modify_csr ****************************************************************************/ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits) { modifyreg32(cfg->csr, clearbits, setbits); @@ -158,7 +158,7 @@ static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, * Name: get_csr ****************************************************************************/ -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg) +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg) { return getreg32(cfg->csr); } @@ -184,7 +184,7 @@ static int comp_setup(struct comp_dev_s *dev) /* Configure selected comparator */ - ret = stm32l4_compconfig(dev); + ret = stm32_compconfig(dev); if (ret < 0) { aerr("ERROR: Failed to initialize COMP: %d\n", ret); @@ -212,10 +212,10 @@ static int comp_setup(struct comp_dev_s *dev) static void comp_shutdown(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; cfg = dev->ad_priv; - stm32l4_compenable(cfg, false); + stm32_compenable(cfg, false); } /**************************************************************************** @@ -235,7 +235,7 @@ static void comp_shutdown(struct comp_dev_s *dev) static int comp_read(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval; cfg = dev->ad_priv; @@ -283,8 +283,8 @@ static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) static int comp_bind(struct comp_dev_s *dev, const struct comp_callback_s *callback) { - struct stm32l4_comp_config_s *priv = - (struct stm32l4_comp_config_s *)dev->ad_priv; + struct stm32_comp_config_s *priv = + (struct stm32_comp_config_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); priv->interrupt.cb = callback; @@ -296,7 +296,7 @@ static int comp_bind(struct comp_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_compenable + * Name: stm32_compenable * * Description: * Enable/disable comparator @@ -307,7 +307,7 @@ static int comp_bind(struct comp_dev_s *dev, * ****************************************************************************/ -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en) { uint32_t clearbits = en ? 0 : COMP_CSR_EN; @@ -316,10 +316,10 @@ static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, modify_csr(cfg, clearbits, setbits); } -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { struct comp_dev_s *dev = (struct comp_dev_s *)arg; - struct stm32l4_comp_config_s *cfg = dev->ad_priv; + struct stm32_comp_config_s *cfg = dev->ad_priv; DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); @@ -332,7 +332,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_compconfig + * Name: stm32_compconfig * * Description: * Configure comparator and I/Os used as comparators inputs @@ -345,9 +345,9 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_compconfig(const struct comp_dev_s *dev) +static int stm32_compconfig(const struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval = 0; uint32_t mask = 0; uint32_t clearbits; @@ -364,20 +364,20 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) switch (cfg->inp) { case STM32_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; case STM32_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; #if defined(CONFIG_STM32_STM32L4X3) case STM32_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -425,13 +425,13 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; case STM32_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); #if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ defined(CONFIG_STM32_STM32L4XR) @@ -445,7 +445,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) #if defined(CONFIG_STM32_STM32L4X3) case STM32_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -453,7 +453,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -461,7 +461,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -539,18 +539,18 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) /* Enable */ - stm32l4_compenable(cfg, true); + stm32_compenable(cfg, true); /* Enable interrupt */ if (cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)) { - ret = stm32l4_exti_comp(cmp, cfg->interrupt.rising, + ret = stm32_exti_comp(cmp, cfg->interrupt.rising, cfg->interrupt.falling, 0, - stm32l4_exti_comp_isr, (void *)dev); + stm32_exti_comp_isr, (void *)dev); if (ret < 0) { - aerr("stm32l4_exti_comp failed ret = %d\n", ret); + aerr("stm32_exti_comp failed ret = %d\n", ret); return ERROR; } } @@ -561,7 +561,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -579,8 +579,8 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) ****************************************************************************/ struct comp_dev_s * - stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg) + stm32_compinitialize(int intf, + const struct stm32_comp_config_s *cfg) { struct comp_dev_s *dev; diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index ac63ae218f3a2..ecf645f2818ee 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -54,7 +54,7 @@ /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { STM32_COMP1, STM32_COMP2, @@ -63,7 +63,7 @@ enum stm32l4_comp_e /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ @@ -72,7 +72,7 @@ enum stm32l4_comp_inp_e /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { STM32_COMP_INM_1_4_VREF, STM32_COMP_INM_1_2_VREF, @@ -91,7 +91,7 @@ enum stm32l4_comp_inm_e /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { STM32_COMP1, STM32_COMP2, @@ -100,7 +100,7 @@ enum stm32l4_comp_e /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ @@ -108,7 +108,7 @@ enum stm32l4_comp_inp_e /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { STM32_COMP_INM_1_4_VREF, STM32_COMP_INM_1_2_VREF, @@ -123,7 +123,7 @@ enum stm32l4_comp_inm_e /* Hysteresis */ -enum stm32l4_comp_hyst_e +enum stm32_comp_hyst_e { STM32_COMP_HYST_NONE, STM32_COMP_HYST_LOW, @@ -133,7 +133,7 @@ enum stm32l4_comp_hyst_e /* Power/Speed Modes */ -enum stm32l4_comp_speed_e +enum stm32_comp_speed_e { STM32_COMP_SPEED_HIGH, STM32_COMP_SPEED_MEDIUM, @@ -142,7 +142,7 @@ enum stm32l4_comp_speed_e /* Comparator configuration *************************************************/ -struct stm32l4_comp_config_s +struct stm32_comp_config_s { struct { @@ -151,10 +151,10 @@ struct stm32l4_comp_config_s bool falling; } interrupt; - uint8_t inp; /* Plus input pin (see enum stm32l4_comp_inp_e) */ - uint8_t inm; /* Minus input pin (see enum stm32l4_comp_inm_e) */ - uint8_t hyst; /* Hysteresis (see enum stm32l4_comp_hyst_e) */ - uint8_t speed; /* Speed (see stm32l4_comp_speed_e) */ + uint8_t inp; /* Plus input pin (see enum stm32_comp_inp_e) */ + uint8_t inm; /* Minus input pin (see enum stm32_comp_inm_e) */ + uint8_t hyst; /* Hysteresis (see enum stm32_comp_hyst_e) */ + uint8_t speed; /* Speed (see stm32_comp_speed_e) */ bool inverted; /* Invert output? */ uint32_t csr; /* Control and status register */ }; @@ -173,7 +173,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -192,8 +192,8 @@ extern "C" ****************************************************************************/ struct -comp_dev_s *stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg); +comp_dev_s *stm32_compinitialize(int intf, + const struct stm32_comp_config_s *cfg); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index f3f139f6101cd..15cd9f3e4f57c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -40,7 +40,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_dac.h" #include "stm32l4_rcc.h" #include "stm32l4_dma.h" @@ -408,7 +408,7 @@ static const struct stm32_dac_ops_s g_dac_llops = /* Channel 1 */ #ifdef CONFIG_STM32_DAC1_DMA -uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32_DAC1_DMA_BUFFER_SIZE]; +uint16_t stm32_dac1_dmabuffer[CONFIG_STM32_DAC1_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac1priv = @@ -428,7 +428,7 @@ static struct stm32_chan_s g_dac1priv = .hasdma = 1, .dmachan = DAC1_DMA_CHAN, .buffer_len = CONFIG_STM32_DAC1_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac1_dmabuffer, + .dmabuffer = stm32_dac1_dmabuffer, .timer = CONFIG_STM32_DAC1_TIMER, .tsel = DAC1_TSEL_VALUE, .tbase = DAC1_TIMER_BASE, @@ -448,7 +448,7 @@ static struct dac_dev_s g_dac1dev = /* Channel 2 */ #ifdef CONFIG_STM32_DAC2_DMA -uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32_DAC2_DMA_BUFFER_SIZE]; +uint16_t stm32_dac2_dmabuffer[CONFIG_STM32_DAC2_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac2priv = @@ -468,7 +468,7 @@ static struct stm32_chan_s g_dac2priv = .hasdma = 1, .dmachan = DAC2_DMA_CHAN, .buffer_len = CONFIG_STM32_DAC2_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac2_dmabuffer, + .dmabuffer = stm32_dac2_dmabuffer, .timer = CONFIG_STM32_DAC2_TIMER, .tsel = DAC2_TSEL_VALUE, .tbase = DAC2_TIMER_BASE, @@ -511,7 +511,7 @@ static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) } /**************************************************************************** - * Name: stm32l4_dac_modify_cr + * Name: stm32_dac_modify_cr * * Description: * Modify the contents of the DAC control register. @@ -526,7 +526,7 @@ static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) * ****************************************************************************/ -static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, +static inline void stm32_dac_modify_cr(struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { @@ -546,7 +546,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, } /**************************************************************************** - * Name: stm32l4_dac_modify_mcr + * Name: stm32_dac_modify_mcr * * Description: * Modify the contents of the DAC mode register. @@ -561,7 +561,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, * ****************************************************************************/ -static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, +static inline void stm32_dac_modify_mcr(struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { @@ -807,7 +807,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Enable DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_EN); + stm32_dac_modify_cr(chan, 0, DAC_CR_EN); #ifdef HAVE_DMA if (chan->hasdma) @@ -843,17 +843,17 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) * - Peripheral Burst: single */ - stm32l4_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, + stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, chan->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ chan->result = -EBUSY; - stm32l4_dmastart(chan->dma, dac_dmatxcallback, chan, false); + stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN); } else #endif @@ -1098,7 +1098,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (chan->pin != 0xffffffffu) { - stm32l4_configgpio(chan->pin); + stm32_configgpio(chan->pin); } /* DAC channel configuration: @@ -1110,7 +1110,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Disable before change */ - stm32l4_dac_modify_cr(chan, DAC_CR_EN, 0); + stm32_dac_modify_cr(chan, DAC_CR_EN, 0); clearbits = DAC_CR_TSEL_MASK | DAC_CR_MAMP_MASK | @@ -1119,7 +1119,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) chan->tsel | /* Set trigger source (SW or timer TRGO event) */ DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */ DAC_CR_WAVE_DISABLED; /* Set no noise */ - stm32l4_dac_modify_cr(chan, clearbits, setbits); + stm32_dac_modify_cr(chan, clearbits, setbits); /* Enable output buffer or route DAC output to on-chip peripherals (ADC) */ @@ -1133,7 +1133,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) setbits = DAC_MCR_MODE_IN; } - stm32l4_dac_modify_mcr(chan, clearbits, setbits); + stm32_dac_modify_mcr(chan, clearbits, setbits); #ifdef HAVE_DMA /* Determine if DMA is supported by this channel */ @@ -1144,11 +1144,11 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Yes.. DAC trigger enable */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_TEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_TEN); /* Allocate a DMA channel */ - chan->dma = stm32l4_dmachannel(chan->dmachan); + chan->dma = stm32_dmachannel(chan->dmachan); if (!chan->dma) { aerr("ERROR: Failed to allocate a DMA channel\n"); @@ -1161,7 +1161,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (ret < 0) { aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); - stm32l4_dmafree(chan->dma); + stm32_dmafree(chan->dma); return ret; } } @@ -1229,11 +1229,11 @@ static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled) if (enabled) { - stm32l4_dac_modify_cr(priv, 0, DAC_CR_EN); + stm32_dac_modify_cr(priv, 0, DAC_CR_EN); } else { - stm32l4_dac_modify_cr(priv, DAC_CR_EN, 0); + stm32_dac_modify_cr(priv, DAC_CR_EN, 0); } } @@ -1272,17 +1272,17 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) * - Peripheral Burst: single */ - stm32l4_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, + stm32_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, priv->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dma, dac_dmatxcallback, priv, false); + stm32_dmastart(priv->dma, dac_dmatxcallback, priv, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); /* Reset counters (generate an update) */ @@ -1300,11 +1300,11 @@ static void dac_llops_stopdma(struct stm32_dac_dev_s *dev) /* Stop the DMA */ priv->result = -EBUSY; - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); } #endif @@ -1326,7 +1326,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC. @@ -1343,7 +1343,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) * ****************************************************************************/ -struct dac_dev_s *stm32l4_dacinitialize(int intf) +struct dac_dev_s *stm32_dacinitialize(int intf) { struct dac_dev_s *dev; struct stm32_chan_s *chan; diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h index 5069f40a91b9b..67636aebb1d1e 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/stm32l4_dac.h @@ -144,10 +144,10 @@ struct stm32_dac_ops_s ****************************************************************************/ #ifdef CONFIG_STM32_DAC1_DMA -extern uint16_t stm32l4_dac1_dmabuffer[]; +extern uint16_t stm32_dac1_dmabuffer[]; #endif #ifdef CONFIG_STM32_DAC2_DMA -extern uint16_t stm32l4_dac2_dmabuffer[]; +extern uint16_t stm32_dac2_dmabuffer[]; #endif /**************************************************************************** @@ -164,7 +164,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC @@ -178,7 +178,7 @@ extern "C" ****************************************************************************/ struct dac_dev_s; -struct dac_dev_s *stm32l4_dacinitialize(int intf); +struct dac_dev_s *stm32_dacinitialize(int intf); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 026cf0ae95fab..61293972da312 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -1204,19 +1204,19 @@ static int dfsdm_setup(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + FLTRDATAR_OFFSET(priv), (uint32_t)priv->dmabuffer, priv->nchannels, DFSDM_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); } #endif @@ -1735,7 +1735,7 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -1750,7 +1750,7 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, * ****************************************************************************/ -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, int cchannels) { diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index cf3236ff97202..33f09fdffc702 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -306,7 +306,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -322,7 +322,7 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, int nchannels); #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 01ed7e75475ab..a4c76d51dfde8 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -120,7 +120,7 @@ static inline void apb_reset(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode (GCC only). @@ -128,7 +128,7 @@ static inline void apb_reset(void) ****************************************************************************/ #if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) -void stm32l4_dfumode(void) +void stm32_dfumode(void) { uint32_t regval; boot_call_t boot; diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.h b/arch/arm/src/stm32l4/stm32l4_dfumode.h index 0c72fbb761a93..b9d02d0c46622 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.h +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode. @@ -42,7 +42,7 @@ ****************************************************************************/ #if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) -void stm32l4_dfumode(void) noreturn_function; +void stm32_dfumode(void) noreturn_function; #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32_DFUMODE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 111c5e460bf2c..178dc5ad99f92 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -77,13 +77,13 @@ typedef void *DMA_HANDLE; * status - A bit encoded value that provides the completion status. See * the DMASTATUS_* definitions above. * arg - A user-provided value that was provided when - * stm32l4_dmastart() was called. + * stm32_dmastart() was called. */ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32l4_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ @@ -130,7 +130,7 @@ extern "C" defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -139,11 +139,11 @@ extern "C" * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will + * If the DMA channel is not available, then stm32_dmachannel() will * wait until the holder of the channel relinquishes the channel by - * calling stm32l4_dmafree(). WARNING: If you have two devices sharing a + * calling stm32_dmafree(). WARNING: If you have two devices sharing a * DMA channel and the code never releases the channel, the - * stm32l4_dmachannel call for the other will hang forever in this + * stm32_dmachannel call for the other will hang forever in this * function! Don't let your design do that! * * Hmm.. I suppose this interface could be extended to make a non-blocking @@ -166,7 +166,7 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chan); +DMA_HANDLE stm32_dmachannel(unsigned int chan); #elif defined(CONFIG_STM32_STM32L4XR) @@ -195,20 +195,20 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chan); * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); #endif /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32l4_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -220,64 +220,64 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -292,44 +292,44 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32l4_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32l4_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32l4_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index 48d4cace76373..96b483ff201c9 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -86,14 +86,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l4_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 5d793625bfdd8..9b8b2e77cbe1b 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32_COMP -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index 2ad3d44cde555..34f2632605085 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -83,7 +83,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -109,7 +109,7 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index 89cf9899ee9d7..8579f144a093b 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -83,7 +83,7 @@ static const uint32_t g_comp_lines[STM32_COMP_NUM] = * Private Functions ****************************************************************************/ -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { uint32_t pr; uint32_t ln; @@ -118,7 +118,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -136,7 +136,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { irqstate_t flags; @@ -152,7 +152,7 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL); + irq_attach(STM32_IRQ_COMP, stm32_exti_comp_isr, NULL); up_enable_irq(STM32_IRQ_COMP); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 767bffb83caab..1418d7c75d644 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -66,7 +66,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32l4_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -87,7 +87,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -108,7 +108,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -129,7 +129,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -150,7 +150,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -171,7 +171,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -215,14 +215,14 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32l4_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32l4_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,7 +252,7 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -273,37 +273,37 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32l4_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32l4_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32l4_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32l4_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32l4_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32l4_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32l4_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,7 +349,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l4_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index 854df35b91382..01a6dd882f8f5 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -58,14 +58,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -88,7 +88,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -104,7 +104,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -116,7 +116,7 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h index 23fc5e227e285..31c177d19ee9c 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -52,7 +52,7 @@ * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /* __ARCH_ARM_SRC_STM32L4_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 2bcf7b22ef38f..dd0c8b7d44046 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -83,7 +83,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -109,7 +109,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); } else diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index c4597da0e98a5..2a427efb118fa 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -39,7 +39,7 @@ * Public Functions ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) +int stm32_firewallsetup(struct stm32_firewall_t *setup) { uint32_t reg; diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index e0a8f8c9160dd..9cf2f575ecf61 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -52,7 +52,7 @@ * Public Types ****************************************************************************/ -struct stm32l4_firewall_t +struct stm32_firewall_t { uintptr_t codestart; size_t codelen; @@ -84,7 +84,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_firewallsetup + * Name: stm32_firewallsetup * * Description: * Configure the STM32L4 firewall. After this, protected code will only @@ -95,7 +95,7 @@ extern "C" * ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup); +int stm32_firewallsetup(struct stm32_firewall_t *setup); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index da4869d2f7065..6905cd47afe73 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -106,7 +106,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -174,7 +174,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -202,7 +202,7 @@ static void data_cache_enable(void) * Public Functions ****************************************************************************/ -int stm32l4_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -218,7 +218,7 @@ int stm32l4_flash_unlock(void) return ret; } -int stm32l4_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -235,7 +235,7 @@ int stm32l4_flash_lock(void) } /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -251,7 +251,7 @@ int stm32l4_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -289,7 +289,7 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -508,7 +508,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h index 8cc8497d964a7..3cc3a8a0bfdfe 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/stm32l4_flash.h @@ -34,11 +34,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32l4_flash_lock(void); -int stm32l4_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ int stm32l4_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 250cc27375d2c..c768b6237e352 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -44,7 +44,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -61,10 +61,10 @@ * ****************************************************************************/ -static int stm32l4_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32l4_freerun_s *freerun = - (struct stm32l4_freerun_s *)arg; + struct stm32_freerun_s *freerun = + (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; @@ -78,7 +78,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -96,7 +96,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { @@ -110,7 +110,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32l4_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -128,7 +128,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); /* Set timer period */ @@ -144,7 +144,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, } /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -152,7 +152,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -162,7 +162,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -176,7 +176,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32l4_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -238,7 +238,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, } /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -246,7 +246,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -254,7 +254,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); @@ -266,7 +266,7 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) /* Free the timer */ - stm32l4_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index efbd2aa9a2dfa..ee546e37c1961 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -42,16 +42,16 @@ ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32l4_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since the * contents are subject to change. */ -struct stm32l4_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint32_t overflow; /* Timer counter overflow */ - struct stm32l4_tim_dev_s *tch; /* Handle returned by stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ uint32_t frequency; }; @@ -73,7 +73,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -91,11 +91,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -103,7 +103,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -113,11 +113,11 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -125,7 +125,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -133,7 +133,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index a1ac054547d59..1a1e18a76f895 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -94,13 +94,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -108,17 +108,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32l4_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -129,7 +129,7 @@ void stm32l4_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -177,7 +177,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -364,7 +364,7 @@ int stm32l4_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -384,7 +384,7 @@ int stm32l4_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -393,18 +393,18 @@ int stm32l4_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l4_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -438,14 +438,14 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index d88b79e7cd268..bfdcbe57a5614 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -50,7 +50,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l4_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -251,12 +251,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative * function. * @@ -266,10 +266,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -288,30 +288,30 @@ int stm32l4_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -330,11 +330,11 @@ bool stm32l4_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -342,23 +342,23 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l4_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l4_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l4_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index e34c588f6a156..65716843cb1dd 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -64,7 +64,7 @@ * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -133,7 +133,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) } /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -146,7 +146,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32l4_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index e9ac08187bfb8..6c6bee8d2e0d7 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32l4_disable_hsi48(void); +void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 2efbd6c775331..a7ad24d641699 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -328,10 +328,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32l4_i2c_tracereset(p) -# define stm32l4_i2c_tracenew(p,s) -# define stm32l4_i2c_traceevent(p,e,a) -# define stm32l4_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -344,7 +344,7 @@ /* Interrupt state */ -enum stm32l4_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -353,7 +353,7 @@ enum stm32l4_intstate_e /* Trace events */ -enum stm32l4_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -381,18 +381,18 @@ enum stm32l4_trace_e /* Trace data */ -struct stm32l4_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32l4_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32l4_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -407,18 +407,18 @@ struct stm32l4_i2c_config_s /* I2C Device Private Data */ -struct stm32l4_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32l4_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32l4_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -436,7 +436,7 @@ struct stm32l4_i2c_priv_s /* The actual trace data */ - struct stm32l4_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -448,10 +448,10 @@ struct stm32l4_i2c_priv_s /* I2C Device, Instance */ -struct stm32l4_i2c_inst_s +struct stm32_i2c_inst_s { const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32l4_i2c_priv_s *priv; /* Common driver private data structure */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -459,57 +459,57 @@ struct stm32l4_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); #endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv); -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm); -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv); -static inline void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -518,7 +518,7 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_STM32_I2C1 -static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = +static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, @@ -531,9 +531,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32l4_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -548,13 +548,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32_I2C2 -static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = +static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, @@ -567,9 +567,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = +static struct stm32_i2c_priv_s stm32_i2c2_priv = { - .config = &stm32l4_i2c2_config, + .config = &stm32_i2c2_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -584,13 +584,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32_I2C3 -static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = +static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, @@ -603,9 +603,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32l4_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -620,13 +620,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32_I2C4 -static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = +static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, @@ -639,9 +639,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = +static struct stm32_i2c_priv_s stm32_i2c4_priv = { - .config = &stm32l4_i2c4_config, + .config = &stm32_i2c4_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -656,18 +656,18 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32l4_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32l4_i2c_transfer + .transfer = stm32_i2c_transfer #ifdef CONFIG_I2C_RESET - , .reset = stm32l4_i2c_reset + , .reset = stm32_i2c_reset #endif }; @@ -676,7 +676,7 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -684,14 +684,14 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -699,42 +699,42 @@ uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getreg32(struct stm32l4_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -742,7 +742,7 @@ static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -750,7 +750,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -759,7 +759,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -780,7 +780,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #endif /**************************************************************************** - * Name: stm32l4_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -789,15 +789,15 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32l4_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -809,7 +809,7 @@ void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -819,11 +819,11 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32l4_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -835,7 +835,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) #ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32l4_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, CONFIG_STM32_I2CTIMEOTICKS); @@ -861,14 +861,14 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -878,7 +878,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Get the timeout value */ #ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32l4_i2c_toticks(priv->msgc, priv->msgv); + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif @@ -901,7 +901,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * reports that it is done. */ - stm32l4_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -921,91 +921,91 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32l4_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32l4_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32l4_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32l4_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32l4_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -1013,7 +1013,7 @@ stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1067,7 +1067,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32l4_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -1075,9 +1075,9 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -1086,19 +1086,19 @@ static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -1124,7 +1124,7 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -1137,10 +1137,10 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, } } -static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1160,13 +1160,13 @@ static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, } priv->tndx++; - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1185,7 +1185,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32l4_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1237,7 +1237,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { int i2cclk_mhz; @@ -1252,11 +1252,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = (stm32l4_i2c_getreg32(priv, + pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1467,7 +1467,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1494,7 +1494,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1556,13 +1556,13 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1572,18 +1572,18 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32l4_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1591,11 +1591,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32l4_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32l4_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1605,11 +1605,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32l4_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1621,17 +1621,17 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32l4_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1639,13 +1639,13 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32l4_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1653,14 +1653,14 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32l4_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1669,22 +1669,22 @@ void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32l4_i2c_process + * stm32_i2c_process * and - * stm32l4_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1694,8 +1694,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32l4_i2c_tracenew(priv, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1737,7 +1737,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1747,7 +1747,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1801,7 +1801,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1814,7 +1814,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1825,7 +1825,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1847,13 +1847,13 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1866,7 +1866,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1909,7 +1909,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1917,7 +1917,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32l4_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1948,8 +1948,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Unsupported state */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2015,7 +2015,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -2029,7 +2029,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->msgv++; - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -2042,9 +2042,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32l4_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -2123,7 +2123,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -2131,7 +2131,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -2156,9 +2156,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * the transfer. */ - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -2175,9 +2175,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -2193,10 +2193,10 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -2212,11 +2212,11 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32l4_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2225,7 +2225,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32l4_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -2234,7 +2234,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32l4_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -2242,7 +2242,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* clear pointer to message content to reflect we are done * with the current transaction. @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,14 +2281,14 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -2296,24 +2296,24 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32l4_i2c_priv_s *priv = (struct stm32l4_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32l4_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32l4_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ @@ -2336,22 +2336,22 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Configure pins */ - if (stm32l4_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32l4_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32l4_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32l4_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32l4_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2364,33 +2364,33 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32l4_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(priv->config->scl_pin); - stm32l4_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2419,7 +2419,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32l4_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2429,11 +2429,11 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_inst_s *inst = (struct stm32l4_i2c_inst_s *)dev; - struct stm32l4_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2444,11 +2444,11 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32l4_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32l4_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2457,14 +2457,14 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32l4_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32l4_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32l4_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2473,17 +2473,17 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32l4_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32l4_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2491,10 +2491,10 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32l4_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2508,7 +2508,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2613,7 +2613,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2623,7 +2623,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2631,7 +2631,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2642,49 +2642,49 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, break; } - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32l4_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32l4_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; int ret; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Ensure that address or flags don't change meanwhile */ ret = nxmutex_lock(&priv->lock); if (ret >= 0) { - ret = stm32l4_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32l4_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2692,9 +2692,9 @@ static int stm32l4_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev) +static int stm32_i2c_reset(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2706,7 +2706,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Get I2C private structure */ - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2728,7 +2728,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* De-init the port */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ @@ -2737,12 +2737,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Let SDA go high */ - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32l4_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2757,7 +2757,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) */ stretch_count = 0; - while (!stm32l4_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2771,12 +2771,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Drive SCL low */ - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2784,27 +2784,27 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) * state machines. */ - stm32l4_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32l4_unconfiggpio(sda_gpio); - stm32l4_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32l4_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2817,7 +2817,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32l4_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2846,12 +2846,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_i2c_priv_s *priv = - (struct stm32l4_i2c_priv_s *)((char *)cb - - offsetof(struct stm32l4_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2893,17 +2893,17 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32l4_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32l4_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ @@ -2911,22 +2911,22 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) { #ifdef CONFIG_STM32_I2C1 case 1: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif #ifdef CONFIG_STM32_I2C2 case 2: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c2_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif #ifdef CONFIG_STM32_I2C3 case 3: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif #ifdef CONFIG_STM32_I2C4 case 4: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c4_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; #endif default: @@ -2935,14 +2935,14 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32l4_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32l4_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2952,7 +2952,7 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2966,19 +2966,19 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -3003,7 +3003,7 @@ int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h index 41110fa84cdf3..c69ed3b9b28da 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/stm32l4_i2c.h @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_I2C_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 65971927574f7..985d307308bf1 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32l4_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32l4_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32l4_pmstandby(); + stm32_pmstandby(); break; default: diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 77c20d24e4a8b..53ec98f34f6c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l4_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32l4_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l4_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l4_nmi, stm32l4_pendsv, stm32l4_pendsv, stm32l4_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l4_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32l4_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l4_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { #ifndef CONFIG_ARCH_HIPRI_INTERRUPT up_irq_save(); @@ -160,7 +160,7 @@ static int stm32l4_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l4_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -170,7 +170,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -178,7 +178,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l4_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -191,7 +191,7 @@ static inline void stm32l4_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l4_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -199,7 +199,7 @@ static inline void stm32l4_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -325,7 +325,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -339,19 +339,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l4_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -376,7 +376,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -411,7 +411,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -488,7 +488,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l4_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 382b272da6c2f..13df82a38ae22 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -87,7 +87,7 @@ * well-known watchdog_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct watchdog_ops_s *ops; /* Lower half operations */ uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ @@ -105,24 +105,24 @@ struct stm32l4_lowerhalf_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) #endif static inline void -stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv); +stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower); -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower); -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status); -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout); /**************************************************************************** @@ -133,25 +133,25 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, static const struct watchdog_ops_s g_wdgops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .keepalive = stm32l4_keepalive, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, .capture = NULL, .ioctl = NULL, }; /* "Lower half" driver state */ -static struct stm32l4_lowerhalf_s g_wdgdev; +static struct stm32_lowerhalf_s g_wdgdev; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 IWDG register @@ -159,7 +159,7 @@ static struct stm32l4_lowerhalf_s g_wdgdev; ****************************************************************************/ #ifdef CONFIG_STM32_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t count = 0; @@ -214,7 +214,7 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -222,7 +222,7 @@ static uint16_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #ifdef CONFIG_STM32_IWDG_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -235,7 +235,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_setprescaler + * Name: stm32_setprescaler * * Description: * Set up the prescaler and reload values. @@ -246,7 +246,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) * ****************************************************************************/ -static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { irqstate_t flags; @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + stm32_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,14 +289,14 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the watchdog timer, resetting the time to the current timeout, @@ -310,10 +310,10 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) * ****************************************************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower) +static int stm32_start(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry: started\n"); @@ -327,7 +327,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * starting the watchdog timer. */ - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: * If the "Hardware watchdog" feature is enabled through the device @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -345,7 +345,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the watchdog timer @@ -359,7 +359,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) +static int stm32_stop(struct watchdog_lowerhalf_s *lower) { /* There is no way to disable the IDWG timer once it has been started */ @@ -368,7 +368,7 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_keepalive + * Name: stm32_keepalive * * Description: * Reset the watchdog timer to the current timeout value, prevent any @@ -384,10 +384,10 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry\n"); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -403,7 +403,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * Get the current watchdog timer status @@ -418,11 +418,11 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t ticks; uint32_t elapsed; @@ -463,7 +463,7 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the watchdog timer) @@ -478,11 +478,11 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t fiwdg; uint64_t reload; int prescaler; @@ -574,7 +574,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, if (priv->started) { - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); } wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", @@ -588,7 +588,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog timer. The watchdog timer is initialized @@ -605,9 +605,9 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) { - struct stm32l4_lowerhalf_s *priv = &g_wdgdev; + struct stm32_lowerhalf_s *priv = &g_wdgdev; wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); @@ -628,7 +628,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * LSI controls outside of this file. */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog @@ -636,7 +636,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * device option bits, the watchdog is automatically enabled at power-on. */ - stm32l4_settimeout((struct watchdog_lowerhalf_s *)priv, + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 440c185a92cb9..d94d25eacc5bc 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_rcc.h" #include "stm32l4_gpio.h" #include "stm32l4_uart.h" @@ -291,7 +291,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -302,7 +302,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -310,7 +310,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -319,7 +319,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l4_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -335,19 +335,19 @@ void stm32l4_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l4_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32l4_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32l4_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.h b/arch/arm/src/stm32l4/stm32l4_lowputc.h index 72d8b26d92438..511fc227a5cf8 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.h +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 9c1678d8d91a9..9ce24f201a3de 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -79,7 +79,7 @@ #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_lptim.h" #include "stm32l4_rcc.h" @@ -92,10 +92,10 @@ /* TIM Device Structure */ -struct stm32l4_lptim_priv_s +struct stm32_lptim_priv_s { - const struct stm32l4_lptim_ops_s *ops; - stm32l4_lptim_mode_t mode; + const struct stm32_lptim_ops_s *ops; + stm32_lptim_mode_t mode; uint32_t base; /* LPTIMn base address */ uint32_t freq; /* Clocking for the LPTIM module */ }; @@ -104,56 +104,56 @@ struct stm32l4_lptim_priv_s * Private Function Prototypes ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer); -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer); +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits); -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg); -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq); -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); static -uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev); +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = +static const struct stm32_lptim_ops_s stm32_lptim_ops = { - .setmode = &stm32l4_lptim_setmode, - .setclock = &stm32l4_lptim_setclock, - .setchannel = &stm32l4_lptim_setchannel, - .setclocksource = &stm32l4_lptim_setclocksource, - .setpolarity = &stm32l4_lptim_setpolarity, - .getcounter = &stm32l4_lptim_getcounter, - .setcountmode = &stm32l4_lptim_setcountmode, - .setperiod = &stm32l4_lptim_setperiod, - .getperiod = &stm32l4_lptim_getperiod + .setmode = &stm32_lptim_setmode, + .setclock = &stm32_lptim_setclock, + .setchannel = &stm32_lptim_setchannel, + .setclocksource = &stm32_lptim_setclocksource, + .setpolarity = &stm32_lptim_setpolarity, + .getcounter = &stm32_lptim_getcounter, + .setcountmode = &stm32_lptim_setcountmode, + .setperiod = &stm32_lptim_setperiod, + .getperiod = &stm32_lptim_getperiod }; #if defined(CONFIG_STM32_LPTIM1) -static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = +static struct stm32_lptim_priv_s stm32_lptim1_priv = { - .ops = &stm32l4_lptim_ops, + .ops = &stm32_lptim_ops, .mode = STM32_LPTIM_MODE_UNUSED, .base = STM32_LPTIM1_BASE, .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ @@ -161,9 +161,9 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = #endif #if defined(CONFIG_STM32_LPTIM2) -static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = +static struct stm32_lptim_priv_s stm32_lptim2_priv = { - .ops = &stm32l4_lptim_ops, + .ops = &stm32_lptim_ops, .mode = STM32_LPTIM_MODE_UNUSED, .base = STM32_LPTIM2_BASE, .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ @@ -175,20 +175,20 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_getstruct + * Name: stm32_lptim_getstruct ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer) { switch (timer) { #if defined(CONFIG_STM32_LPTIM1) case 1: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim1_priv; #endif #if defined(CONFIG_STM32_LPTIM2) case 2: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim2_priv; #endif default: return NULL; @@ -196,26 +196,26 @@ static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) } /**************************************************************************** - * Name: stm32l4_modifyreg32 + * Name: stm32_modifyreg32 ****************************************************************************/ -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits) { - modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset, + modifyreg32(((struct stm32_lptim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_lptim_enable + * Name: stm32_lptim_enable ****************************************************************************/ -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: @@ -236,14 +236,14 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_disable + * Name: stm32_lptim_disable ****************************************************************************/ -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: @@ -264,14 +264,14 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_reset + * Name: stm32_lptim_reset ****************************************************************************/ -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: @@ -291,18 +291,18 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_get_gpioconfig + * Name: stm32_lptim_get_gpioconfig ****************************************************************************/ -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg) { DEBUGASSERT(dev != NULL && cfg != NULL); channel &= STM32_LPTIM_CH_MASK; - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: @@ -362,13 +362,13 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setmode + * Name: stm32_lptim_setmode ****************************************************************************/ -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode) +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode) { - const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + + const uint32_t addr = ((struct stm32_lptim_priv_s *)dev)->base + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); @@ -397,20 +397,20 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, /* Save mode */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = mode; + ((struct stm32_lptim_priv_s *)dev)->mode = mode; return OK; } /**************************************************************************** - * Name: stm32l4_lptim_setclock + * Name: stm32_lptim_setclock ****************************************************************************/ -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; uint32_t setbits; uint32_t actual; @@ -420,7 +420,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, if (freq == 0) { - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); return 0; } @@ -469,19 +469,19 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); return actual; } /**************************************************************************** - * Name: stm32l4_lptim_setchannel + * Name: stm32_lptim_setchannel ****************************************************************************/ -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable) { int ret = OK; @@ -491,16 +491,16 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, /* Configure GPIOs */ - ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg); + ret = stm32_lptim_get_gpioconfig(dev, channel, &cfg); if (!ret) { if (enable) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } @@ -508,20 +508,20 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setclocksource + * Name: stm32_lptim_setclocksource ****************************************************************************/ -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc) +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -613,7 +613,7 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -622,49 +622,49 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setperiod + * Name: stm32_lptim_setperiod ****************************************************************************/ -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_lptim_setcountmode + * Name: stm32_lptim_setcountmode ****************************************************************************/ -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode) +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode) { DEBUGASSERT(dev != NULL); if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -676,30 +676,30 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity) +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity) { DEBUGASSERT(dev != NULL); switch (polarity) { case STM32_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; case STM32_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; case STM32_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -709,13 +709,13 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); @@ -739,16 +739,16 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_init + * Name: stm32_lptim_init ****************************************************************************/ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) +struct stm32_lptim_dev_s *stm32_lptim_init(int timer) { - struct stm32l4_lptim_dev_s *dev = NULL; + struct stm32_lptim_dev_s *dev = NULL; /* Get structure and enable power */ - dev = stm32l4_lptim_getstruct(timer); + dev = stm32_lptim_getstruct(timer); if (!dev) { return NULL; @@ -756,7 +756,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_lptim_priv_s *)dev)->mode != + if (((struct stm32_lptim_priv_s *)dev)->mode != STM32_LPTIM_MODE_UNUSED) { return NULL; @@ -764,34 +764,34 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Enable power */ - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); /* Reset timer */ - stm32l4_lptim_reset(dev); + stm32_lptim_reset(dev); /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } /**************************************************************************** - * Name: stm32l4_lptim_deinit + * Name: stm32_lptim_deinit ****************************************************************************/ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) +int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) { DEBUGASSERT(dev); /* Disable power */ - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index 7746869fcd21a..1293aa551bc69 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -112,9 +112,9 @@ extern "C" /* LPTIM Device Structure */ -struct stm32l4_lptim_dev_s +struct stm32_lptim_dev_s { - struct stm32l4_lptim_ops_s *ops; + struct stm32_lptim_ops_s *ops; }; /* LPTIM Modes of Operation */ @@ -129,7 +129,7 @@ typedef enum STM32_LPTIM_MODE_SINGLE = 0x0001, STM32_LPTIM_MODE_CONTINUOUS = 0x0002, STM32_LPTIM_MODE_MASK = 0x000f, -} stm32l4_lptim_mode_t; +} stm32_lptim_mode_t; /* LPTIM Clock Source */ @@ -142,7 +142,7 @@ typedef enum STM32_LPTIM_CLK_HSI = 0x0002, STM32_LPTIM_CLK_LSE = 0x0003, STM32_LPTIM_CLK_EXT = 0x0004, -} stm32l4_lptim_clksrc_t; +} stm32_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -152,7 +152,7 @@ typedef enum STM32_LPTIM_COUNT_CLOCK = 0x0000, STM32_LPTIM_COUNT_EXTTRIG = 0x0001, -} stm32l4_lptim_cntmode_t; +} stm32_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -163,7 +163,7 @@ typedef enum STM32_LPTIM_CLKPOL_RISING = 0x0000, STM32_LPTIM_CLKPOL_FALLING = 0x0001, STM32_LPTIM_CLKPOL_BOTH = 0x0002, -} stm32l4_lptim_clkpol_t; +} stm32_lptim_clkpol_t; /* LPTIM Channel Modes */ @@ -178,26 +178,26 @@ typedef enum STM32_LPTIM_CH_CH2 = 0x0002, STM32_LPTIM_CH_CH3 = 0x0003, STM32_LPTIM_CH_MASK = 0x000f, -} stm32l4_lptim_channel_t; +} stm32_lptim_channel_t; /* LPTIM Operations */ -struct stm32l4_lptim_ops_s +struct stm32_lptim_ops_s { - int (*setmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); - int (*setclock)(struct stm32l4_lptim_dev_s *dev, uint32_t freq); - int (*setchannel)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, int enable); - int (*setclocksource)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); - int (*setpolarity)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); - uint32_t (*getcounter)(struct stm32l4_lptim_dev_s *dev); - int (*setcountmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); - void (*setperiod)(struct stm32l4_lptim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_lptim_dev_s *dev); + int (*setmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); + int (*setclock)(struct stm32_lptim_dev_s *dev, uint32_t freq); + int (*setchannel)(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); + int (*setclocksource)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); + int (*setpolarity)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); + uint32_t (*getcounter)(struct stm32_lptim_dev_s *dev); + int (*setcountmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); + void (*setperiod)(struct stm32_lptim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_lptim_dev_s *dev); }; /**************************************************************************** @@ -206,11 +206,11 @@ struct stm32l4_lptim_ops_s /* Get timer structure, power-up, reset, and mark it as used */ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer); +struct stm32_lptim_dev_s *stm32_lptim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s *dev); +int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 57adca45b1e66..c273c49d3e832 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -54,14 +54,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; @@ -78,7 +78,7 @@ void stm32l4_rcc_enablelse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32l4_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -100,7 +100,7 @@ void stm32l4_rcc_enablelse(void) while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32l4_waste(); + stm32_waste(); } #if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ @@ -121,6 +121,6 @@ void stm32l4_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - stm32l4_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index 2897d3646bac1..ae42b876ca25d 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32l4_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.c b/arch/arm/src/stm32l4/stm32l4_mpuinit.c index fe22ca17d483d..1deb74cdf96c4 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.c +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l4_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l4_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l4_mpuinitialize(void) * ****************************************************************************/ -void stm32l4_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.h b/arch/arm/src/stm32l4/stm32l4_mpuinit.h index 4d2952498e2ce..4a7df2c276471 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.h +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l4_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l4_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l4_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index a8b676a8c8aa7..ebacd10a6096c 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -45,20 +45,20 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32l4_oneshot_s *oneshot = (struct stm32l4_oneshot_s *) arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *) arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -107,7 +107,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -121,7 +121,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { #if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; @@ -162,7 +162,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,7 +193,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32l4_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -211,18 +211,18 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32l4_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32l4_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -302,7 +302,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ @@ -326,7 +326,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -337,7 +337,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -350,7 +350,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 96787cc6cec8a..16b15a75a5f8e 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32l4_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32l4_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ #if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32l4_tim_dev_s *tch; /* Pointer returned by - * stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c index 7dd0b0cd73f30..12474e6080762 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32l4_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32l4_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32l4_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32l4_max_delay, - .start = stm32l4_start, - .cancel = stm32l4_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32l4_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32l4_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32l4_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32l4_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32l4_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_start(&priv->oneshot, - stm32l4_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -278,13 +278,13 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32l4_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32l4_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32l4_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -298,10 +298,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, /* Initialize the contained STM32 oneshot timer */ - ret = stm32l4_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index 880e430899a77..7d91fee2009c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -31,7 +31,7 @@ #include -#include "stm32l4.h" +#include "stm32.h" #if defined(CONFIG_STM32_OTGFS) @@ -67,7 +67,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -94,21 +94,21 @@ extern "C" #ifdef CONFIG_USBHOST struct usbhost_connection_s; struct -usbhost_connection_s *stm32l4_otgfshost_initialize(int controller); +usbhost_connection_s *stm32_otgfshost_initialize(int controller); #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the OTG FS + * Board logic must provide the stm32_usbsuspend logic if the OTG FS * device driver is used. This function is called whenever the USB enters * or leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index cb6dd29bc7d08..af2df0c32ada4 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -349,8 +349,8 @@ /* Request queue operations *************************************************/ -#define stm32l4_rqempty(ep) ((ep)->head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /**************************************************************************** * Private Types @@ -358,7 +358,7 @@ /* Overall device state */ -enum stm32l4_devstate_e +enum stm32_devstate_e { DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply * means that the device is not yet been given an @@ -385,11 +385,11 @@ enum stm32l4_devstate_e /* Endpoint 0 states */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or * epsubmit: - * SET: In stm32l4_epin() and stm32l4_epout() when + * SET: In stm32_epin() and stm32_epout() when * we revert from request processing to * SETUP processing. * TESTED: Never @@ -397,51 +397,51 @@ enum stm32l4_ep0state_e EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA * OUT phase of SETUP Packet to complete before * processing a SETUP command (without a USB request): - * SET: Set in stm32l4_rxinterrupt() when SETUP OUT + * SET: Set in stm32_rxinterrupt() when SETUP OUT * packet is received. - * TESTED: In stm32l4_ep0out_receive() + * TESTED: In stm32_ep0out_receive() */ EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and * accompanying data have been received. Processing * of SETUP command will happen soon. - * SET: (1) stm32l4_ep0out_receive() when the OUT + * SET: (1) stm32_ep0out_receive() when the OUT * SETUP data phase completes, or (2) - * stm32l4_rxinterrupt() when an IN SETUP is + * stm32_rxinterrupt() when an IN SETUP is * packet received. - * TESTED: Tested in stm32l4_epout_interrupt() when + * TESTED: Tested in stm32_epout_interrupt() when * SETUP phase is done to see if the SETUP * command is ready to be processed. Also - * tested in stm32l4_ep0out_setup() just to + * tested in stm32_ep0out_setup() just to * double-check that we have a SETUP request * and any accompanying data. */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32l4_ep0out_setup(): + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): * SET: When SETUP packet received in EP0 OUT * TESTED: Never */ EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): * SET: When SETUP response is sent by - * stm32l4_ep0in_setupresponse() + * stm32_ep0in_setupresponse() * TESTED: Never */ EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32l4_epin_request() when a write + * SET: In stm32_epin_request() when a write * request is processed on EP0. - * TESTED: In stm32l4_epin() to see if we should + * TESTED: In stm32_epin() to see if we should * revert to SETUP processing. */ EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a * USB request) - * SET: In stm32l4_epout_request() when a read + * SET: In stm32_epout_request() when a read * request is processed on EP0. - * TESTED: In stm32l4_epout() to see if we should + * TESTED: In stm32_epout() to see if we should * revert to SETUP processing */ }; /* Parsed control request */ -struct stm32l4_ctrlreq_s +struct stm32_ctrlreq_s { uint8_t type; uint8_t req; @@ -452,28 +452,28 @@ struct stm32l4_ctrlreq_s /* A container for a request so that the request may be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t epphy; /* Physical EP address */ uint8_t eptype:2; /* Endpoint type */ uint8_t active:1; /* 1: A request is being processed */ @@ -485,11 +485,11 @@ struct stm32l4_ep_s /* This structure retains the state of the USB device controller */ -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32l4_usbdev_s. + * to struct stm32_usbdev_s. */ struct usbdev_s usbdev; @@ -507,8 +507,8 @@ struct stm32l4_usbdev_s uint8_t wakeup:1; /* 1: Device remote wake-up */ uint8_t dotest:1; /* 1: Test mode selected */ - uint8_t devstate:4; /* See enum stm32l4_devstate_e */ - uint8_t ep0state:4; /* See enum stm32l4_ep0state_e */ + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ uint8_t testmode:4; /* Selected test mode */ uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32_NENDPOINTS]; + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -549,203 +549,203 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t val, uint32_t addr); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ static struct -stm32l4_req_s *stm32l4_req_remfirst(struct stm32l4_ep_s *privep); -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +stm32_req_s *stm32_req_remfirst(struct stm32_ep_s *privep); +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req); /* Low level data transfers and request operations **************************/ /* Special endpoint 0 data transfer logic */ static -void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *data, uint32_t nbytes); static inline -void stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in_activate(void); +void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); static -void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv); +void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); /* IN request and TxFIFO handling */ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* OUT request and RxFIFO handling */ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len); -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len); -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt); -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt); -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* General request handling */ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep); -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_ep_flush(struct stm32_ep_s *privep); +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status); /* Interrupt handling *******************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog); -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl); -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv); +static void stm32_usbreset(struct stm32_usbdev_s *priv); /* Second level OUT endpoint interrupt processing */ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index); -static inline void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq); -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv); +void stm32_epout_interrupt(struct stm32_usbdev_s *priv); /* Second level IN endpoint interrupt processing */ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv); +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); static inline -void stm32l4_epin(struct stm32l4_usbdev_s *priv, uint8_t epno); +void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno); -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv); +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); /* Other second level interrupt processing */ static inline -void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv); +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocininterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); #endif #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv); +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); #endif /* First level interrupt processing */ -static int stm32l4_usbinterrupt(int irq, void *context, +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint operations ******************************************************/ /* Global OUT NAK controls */ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep); -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep); +static void stm32_enablegonak(struct stm32_ep_s *privep); +static void stm32_disablegonak(struct stm32_ep_s *privep); /* Endpoint configuration */ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv); +static void stm32_ep0_configure(struct stm32_usbdev_s *priv); /* Endpoint disable */ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep); -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep); -static int stm32l4_ep_disable(struct usbdev_ep_s *ep); +static void stm32_epout_disable(struct stm32_ep_s *privep); +static void stm32_epin_disable(struct stm32_ep_s *privep); +static int stm32_ep_disable(struct usbdev_ep_s *ep); /* Endpoint request management */ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep); -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep); +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); /* Endpoint buffer management */ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes); -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf); #endif /* Endpoint request submission */ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Endpoint request cancellation */ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Stall handling */ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume); -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv); +static int stm32_epout_setstall(struct stm32_ep_s *privep); +static int stm32_epin_setstall(struct stm32_ep_s *privep); +static int stm32_ep_setstall(struct stm32_ep_s *privep); +static int stm32_ep_clrstall(struct stm32_ep_s *privep); +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(struct stm32_usbdev_s *priv); /* Endpoint allocation */ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep); /* USB device controller operations *****************************************/ -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address); -static int stm32l4_txfifo_flush(uint32_t txfnum); -static int stm32l4_rxfifo_flush(void); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); /* Initialization ***********************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); +static void stm32_swinitialize(struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -755,31 +755,31 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_otgfsdev; +static struct stm32_usbdev_s g_otgfsdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_ep_configure, - .disable = stm32l4_ep_disable, - .allocreq = stm32l4_ep_allocreq, - .freereq = stm32l4_ep_freereq, + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, #ifdef CONFIG_USBDEV_DMA - .allocbuffer = stm32l4_ep_allocbuffer, - .freebuffer = stm32l4_ep_freebuffer, + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, #endif - .submit = stm32l4_ep_submit, - .cancel = stm32l4_ep_cancel, - .stall = stm32l4_ep_stall, + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_ep_alloc, - .freeep = stm32l4_ep_free, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /* Device error strings that may be enabled for more descriptive USB trace @@ -886,7 +886,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register @@ -894,7 +894,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = ****************************************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr) +static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -949,7 +949,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -957,7 +957,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static void stm32l4_putreg(uint32_t val, uint32_t addr) +static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -970,17 +970,17 @@ static void stm32l4_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_req_remfirst + * Name: stm32_req_remfirst * * Description: * Remove a request from the head of an endpoint request queue * ****************************************************************************/ -static struct stm32l4_req_s * -stm32l4_req_remfirst(struct stm32l4_ep_s *privep) +static struct stm32_req_s * +stm32_req_remfirst(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -997,15 +997,15 @@ stm32l4_req_remfirst(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_req_addlast + * Name: stm32_req_addlast * * Description: * Add a request to the end of an endpoint request queue * ****************************************************************************/ -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req) { bool is_empty = !privep->head; @@ -1025,23 +1025,23 @@ static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_ep0in_setupresponse + * Name: stm32_ep0in_setupresponse * * Description: * Schedule a short transfer on Endpoint 0 (IN or OUT) * ****************************************************************************/ -static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *buf, uint32_t nbytes) { - stm32l4_epin_transfer(&priv->epin[EP0], buf, nbytes); + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); priv->ep0state = EP0STATE_SETUPRESPONSE; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0in_transmitzlp + * Name: stm32_ep0in_transmitzlp * * Description: * Send a zero length packet (ZLP) on endpoint 0 IN @@ -1049,26 +1049,26 @@ static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline void -stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv) +stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) { - stm32l4_ep0in_setupresponse(priv, NULL, 0); + stm32_ep0in_setupresponse(priv, NULL, 0); } /**************************************************************************** - * Name: stm32l4_ep0in_activate + * Name: stm32_ep0in_activate * * Description: * Activate the endpoint 0 IN endpoint. * ****************************************************************************/ -static void stm32l4_ep0in_activate(void) +static void stm32_ep0in_activate(void) { uint32_t regval; /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,24 +1083,24 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_ep0out_ctrlsetup + * Name: stm32_ep0out_ctrlsetup * * Description: * Setup to receive a SETUP packet. * ****************************************************************************/ -static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) { uint32_t regval; @@ -1109,24 +1109,24 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** - * Name: stm32l4_txfifo_write + * Name: stm32_txfifo_write * * Description: * Send data to the endpoint's TxFIFO. * ****************************************************************************/ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t regaddr; @@ -1157,19 +1157,19 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Then write the packet data to the TxFIFO */ - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); } } /**************************************************************************** - * Name: stm32l4_epin_transfer + * Name: stm32_epin_transfer * * Description: * Start the Tx data transfer * ****************************************************************************/ -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t pktcnt; @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32_OTGFS_DSTS); + uint32_t status = stm32_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,28 +1254,28 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the * transfer we can just blindly continue. */ - stm32l4_txfifo_write(privep, buf, nbytes); + stm32_txfifo_write(privep, buf, nbytes); } /**************************************************************************** - * Name: stm32l4_epin_request + * Name: stm32_epin_request * * Description: * Begin or continue write request processing. * ****************************************************************************/ -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint8_t *buf; @@ -1286,12 +1286,12 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* We get here in one of four possible ways. From three interrupting * events: * - * 1. From stm32l4_epin as part of the transfer complete interrupt + * 1. From stm32_epin as part of the transfer complete interrupt * processing This interrupt indicates that the last transfer has * completed. * 2. As part of the ITTXFE interrupt processing. That interrupt indicates * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32l4_epin_txfifoempty as part of the TXFE interrupt + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt * processing. The TXFE interrupt is only enabled when the TxFIFO is * full and the software must wait for space to become available in the * TxFIFO. @@ -1299,13 +1299,13 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * And this function may be called immediately when the write request is * queue to start up the next transaction. * - * 4. From stm32l4_ep_submit when a new write request is received WHILE the + * 4. From stm32_ep_submit when a new write request is received WHILE the * endpoint is not active (privep->active == false). */ /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); @@ -1317,9 +1317,9 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer active */ @@ -1426,7 +1426,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * the TxFIFO is empty. */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), @@ -1436,16 +1436,16 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32_OTG_DIEPTXF(privep->epphy)); + regval = stm32_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1463,7 +1463,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* Transfer data to the TxFIFO */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epin_transfer(privep, buf, nbytes); + stm32_epin_transfer(privep, buf, nbytes); /* If it was not before, the OUT endpoint is now actively transferring * data. @@ -1497,19 +1497,19 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * yet completed). */ - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); } } /**************************************************************************** - * Name: stm32l4_rxfifo_read + * Name: stm32_rxfifo_read * * Description: * Read packet from the RxFIFO into a read request. * ****************************************************************************/ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len) { uint32_t regaddr; @@ -1535,7 +1535,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, /* Read 1 x 32-bits of EP0 packet data */ - data.w = stm32l4_getreg(regaddr); + data.w = stm32_getreg(regaddr); /* Write 4 x 8-bits of EP0 packet data */ @@ -1547,14 +1547,14 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_rxfifo_discard + * Name: stm32_rxfifo_discard * * Description: * Discard packet data from the RxFIFO. * ****************************************************************************/ -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) { if (len > 0) { @@ -1571,7 +1571,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) for (i = 0; i < len; i += 4) { - volatile uint32_t data = stm32l4_getreg(regaddr); + volatile uint32_t data = stm32_getreg(regaddr); UNUSED(data); } @@ -1580,7 +1580,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) } /**************************************************************************** - * Name: stm32l4_epout_complete + * Name: stm32_epout_complete * * Description: * This function is called when an OUT transfer complete interrupt is @@ -1589,16 +1589,16 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * ****************************************************************************/ -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Since a transfer just completed, there must be a read request at the * head of the endpoint request queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); DEBUGASSERT(privreq); if (!privreq) @@ -1620,16 +1620,16 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, */ usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); privep->active = false; /* Now set up the next read request (if any) */ - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_ep0out_receive + * Name: stm32_ep0out_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1638,15 +1638,15 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_usbdev_s *priv; + struct stm32_usbdev_s *priv; /* Sanity Checking */ DEBUGASSERT(privep && privep->dev); - priv = (struct stm32l4_usbdev_s *)privep->dev; + priv = (struct stm32_usbdev_s *)privep->dev; uinfo("EP0: bcnt=%d\n", bcnt); usbtrace(TRACE_READ(EP0), bcnt); @@ -1660,11 +1660,11 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, /* Read the data into our special buffer for SETUP data */ int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); - stm32l4_rxfifo_read(privep, priv->ep0data, readlen); + stm32_rxfifo_read(privep, priv->ep0data, readlen); /* Do we have to discard any excess bytes? */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Now we can process the setup command */ @@ -1672,7 +1672,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } else { @@ -1682,13 +1682,13 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, */ usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); - stm32l4_rxfifo_discard(privep, bcnt); + stm32_rxfifo_discard(privep, bcnt); privep->active = false; } } /**************************************************************************** - * Name: stm32l4_epout_receive + * Name: stm32_epout_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1697,10 +1697,10 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *dest; int buflen; int readlen; @@ -1709,7 +1709,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data is available in the RxFIFO, but there is no read setup @@ -1724,7 +1724,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, if (privep->epphy == 0) { - stm32l4_ep0out_receive(privep, bcnt); + stm32_ep0out_receive(privep, bcnt); } else { @@ -1737,7 +1737,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, /* Discard the data in the RxFIFO */ - stm32l4_rxfifo_discard(privep, bcnt); + stm32_rxfifo_discard(privep, bcnt); } privep->active = false; @@ -1760,13 +1760,13 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, /* Transfer the data from the RxFIFO to the request's data buffer */ - stm32l4_rxfifo_read(privep, dest, readlen); + stm32_rxfifo_read(privep, dest, readlen); /* If there were more bytes in the RxFIFO than could be held in the read * request, then we will have to discard those. */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Update the number of bytes transferred */ @@ -1774,7 +1774,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_epout_request + * Name: stm32_epout_request * * Description: * This function is called when either @@ -1784,10 +1784,10 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint32_t xfrsize; @@ -1811,7 +1811,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), @@ -1824,9 +1824,9 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* This endpoint is no longer actively transferring */ @@ -1843,7 +1843,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); } /* Otherwise, we have a usable read request... @@ -1871,16 +1871,16 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); regval |= (pktcnt << OTGFS_DOEPTSIZ_PKTCNT_SHIFT); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Then enable the transfer */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must * also be set appropriately. @@ -1903,7 +1903,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Clearing NAKing and enable the transfer. */ regval |= (OTGFS_DOEPCTL_CNAK | OTGFS_DOEPCTL_EPENA); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* A transfer is now active on this endpoint */ @@ -1921,27 +1921,27 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep_flush + * Name: stm32_ep_flush * * Description: * Flush any primed descriptors from this ep * ****************************************************************************/ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) +static void stm32_ep_flush(struct stm32_ep_s *privep) { if (privep->isin) { - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); } else { - stm32l4_rxfifo_flush(); + stm32_rxfifo_flush(); } } /**************************************************************************** - * Name: stm32l4_req_complete + * Name: stm32_req_complete * * Description: * Handle termination of the request at the head of the endpoint request @@ -1949,14 +1949,14 @@ static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Remove the request at the head of the request list */ - privreq = stm32l4_req_remfirst(privep); + privreq = stm32_req_remfirst(privep); DEBUGASSERT(privreq != NULL); /* If endpoint 0, temporarily reflect the state of protocol stalled @@ -1983,30 +1983,30 @@ static void stm32l4_req_complete(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_req_cancel + * Name: stm32_req_cancel * * Description: * Cancel all pending requests for an endpoint * ****************************************************************************/ -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) { - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { - stm32l4_ep_flush(privep); + stm32_ep_flush(privep); } - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_req_complete(privep, status); + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); } } /**************************************************************************** - * Name: stm32l4_ep_findbyaddr + * Name: stm32_ep_findbyaddr * * Description: * Find the physical endpoint structure corresponding to a logic endpoint @@ -2015,10 +2015,10 @@ static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) ****************************************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); if (epphy >= STM32_NENDPOINTS) @@ -2044,7 +2044,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_req_dispatch + * Name: stm32_req_dispatch * * Description: * Provide unhandled setup actions to the class driver. This is logically @@ -2052,7 +2052,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl) { int ret = -EIO; @@ -2078,28 +2078,28 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_usbreset + * Name: stm32_usbreset * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) +static void stm32_usbreset(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int i; /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. @@ -2121,13 +2121,13 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ privep = &priv->epin[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset IN endpoint status */ @@ -2136,54 +2136,54 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Return read requests to the class implementation */ privep = &priv->epout[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset endpoint status */ privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32_OTGFS_DOEPMSK); + stm32_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32_OTGFS_DIEPMSK); + stm32_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ - stm32l4_setaddress(priv, 0); + stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; priv->usbdev.speed = USB_SPEED_FULL; /* Re-configure EP0 */ - stm32l4_ep0_configure(priv); + stm32_ep0_configure(priv); /* Setup EP0 to receive SETUP packets */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_testmode + * Name: stm32_ep0out_testmode * * Description: * Select test mode * ****************************************************************************/ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index) { uint8_t testmode; @@ -2219,11 +2219,11 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, } priv->dotest = true; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_stdrequest + * Name: stm32_ep0out_stdrequest * * Description: * Handle a standard request on EP0. Pick off the things of interest to @@ -2232,10 +2232,10 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq) +void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Handle standard request */ @@ -2265,7 +2265,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { usbtrace(TRACE_INTDECODE( STM32_TRACEINTID_EPGETSTATUS), 0); - privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( @@ -2284,7 +2284,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } } break; @@ -2304,7 +2304,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, USB_FEATURE_REMOTEWAKEUP); priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { @@ -2322,7 +2322,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, priv->ep0data[0] = 0; priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } break; @@ -2352,23 +2352,23 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_clrstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 0; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } } else @@ -2393,29 +2393,29 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_setstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 1; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_TESTMODE && ((ctrlreq->index & 0xff) == 0)) { - stm32l4_ep0out_testmode(priv, ctrlreq->index); + stm32_ep0out_testmode(priv, ctrlreq->index); } else if (priv->configured) { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2452,8 +2452,8 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * address until the completion of the status phase. */ - stm32l4_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); - stm32l4_ep0in_transmitzlp(priv); + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); } else { @@ -2482,7 +2482,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2508,7 +2508,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, ctrlreq->index == 0 && ctrlreq->len == 1) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2535,7 +2535,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { /* Give the configuration to the class driver */ - int ret = stm32l4_req_dispatch(priv, &priv->ctrlreq); + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); /* If the class driver accepted the configuration, then mark the * device state as configured (or not, depending on the @@ -2581,7 +2581,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2607,7 +2607,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep0out_setup + * Name: stm32_ep0out_setup * * Description: * USB Ctrl EP Setup Event. This is logically part of the USB interrupt @@ -2615,9 +2615,9 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ctrlreq_s ctrlreq; + struct stm32_ctrlreq_s ctrlreq; /* Verify that a SETUP was received */ @@ -2629,8 +2629,8 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) /* Terminate any pending requests */ - stm32l4_req_cancel(&priv->epout[EP0], -EPROTO); - stm32l4_req_cancel(&priv->epin[EP0], -EPROTO); + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); /* Assume NOT stalled */ @@ -2660,13 +2660,13 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) { /* Dispatch any non-standard requests */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { /* Handle standard requests. */ - stm32l4_ep0out_stdrequest(priv, &ctrlreq); + stm32_ep0out_stdrequest(priv, &ctrlreq); } /* Check if the setup processing resulted in a STALL */ @@ -2675,7 +2675,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); - stm32l4_ep0_stall(priv); + stm32_ep0_stall(priv); } /* Reset state/data associated with the SETUP request */ @@ -2684,7 +2684,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epout + * Name: stm32_epout * * Description: * This is part of the OUT endpoint interrupt processing. This function @@ -2692,10 +2692,10 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Endpoint 0 is a special case. */ @@ -2712,7 +2712,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epout_complete(priv, privep); + stm32_epout_complete(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2720,7 +2720,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2732,12 +2732,12 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, else if (priv->devstate == DEVSTATE_CONFIGURED) { - stm32l4_epout_complete(priv, &priv->epout[epno]); + stm32_epout_complete(priv, &priv->epout[epno]); } } /**************************************************************************** - * Name: stm32l4_epout_interrupt + * Name: stm32_epout_interrupt * * Description: * USB OUT endpoint interrupt handler. @@ -2750,7 +2750,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) { uint32_t daint; uint32_t regval; @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINT); + regval &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,7 +2777,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32_OTGFS_DAINT); + regval = stm32_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); + regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,11 +2811,11 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32_OTGFS_DOEPMSK); + doepint = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. - * This interrupt is triggered when stm32l4_rxinterrupt() removes + * This interrupt is triggered when stm32_rxinterrupt() removes * the last packet data from the RxFIFO. * In this case, core internally sets the NAK bit for this endpoint * to prevent it from receiving any more packets. @@ -2828,12 +2828,12 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_XFRC, + stm32_putreg(OTGFS_DOEPINT_XFRC, STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ - stm32l4_epout(priv, epno); + stm32_epout(priv, epno); } /* Endpoint disabled interrupt (ignored because this interrupt is @@ -2849,7 +2849,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2868,10 +2868,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_SETUP_READY) { - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } - stm32l4_putreg(OTGFS_DOEPINT_SETUP, + stm32_putreg(OTGFS_DOEPINT_SETUP, STM32_OTGFS_DOEPINT(epno)); } } @@ -2882,7 +2882,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epin_runtestmode + * Name: stm32_epin_runtestmode * * Description: * Execute the test mode setup by the SET FEATURE request @@ -2890,19 +2890,19 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32_OTGFS_DCTL); + uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32_OTGFS_DCTL); + stm32_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; } /**************************************************************************** - * Name: stm32l4_epin + * Name: stm32_epin * * Description: * This is part of the IN endpoint interrupt processing. This function @@ -2910,10 +2910,10 @@ void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Endpoint 0 is a special case. */ @@ -2927,7 +2927,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2935,7 +2935,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2944,7 +2944,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (priv->dotest) { - stm32l4_epin_runtestmode(priv); + stm32_epin_runtestmode(priv); } } @@ -2956,12 +2956,12 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the endpoint write request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } /**************************************************************************** - * Name: stm32l4_epin_txfifoempty + * Name: stm32_epin_txfifoempty * * Description: * TxFIFO empty interrupt handling @@ -2969,20 +2969,20 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Continue processing the write request queue. This may mean sending * more data from the existing request or terminating the current requests * and (perhaps) starting the IN transfer from the next write request. */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_epin_interrupt + * Name: stm32_epin_interrupt * * Description: * USB IN endpoint interrupt handler. The core generates this interrupt @@ -2994,7 +2994,7 @@ void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) * ****************************************************************************/ -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) { uint32_t diepint; uint32_t daint; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); + daint = stm32_getreg(STM32_OTGFS_DAINT); + daint &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,7 +3022,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32_OTGFS_DAINT); + daint = stm32_getreg(STM32_OTGFS_DAINT); usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); + epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32_OTGFS_DIEPMSK); + mask = stm32_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); + empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3096,13 +3096,13 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(OTGFS_DIEPINT_XFRC, + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(OTGFS_DIEPINT_XFRC, STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ - stm32l4_epin(priv, epno); + stm32_epin(priv, epno); } /* Timeout condition */ @@ -3111,7 +3111,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3125,8 +3125,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); - stm32l4_epin_request(priv, &priv->epin[epno]); - stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTGFS_DIEPINT_ITTXFE, STM32_OTGFS_DIEPINT(epno)); } @@ -3138,7 +3138,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3151,7 +3151,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, + stm32_putreg(OTGFS_DIEPINT_EPDISD, STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3176,16 +3176,16 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ - stm32l4_epin_txfifoempty(priv, epno); + stm32_epin_txfifoempty(priv, epno); } /* Clear the pending TxFIFO empty interrupt */ - stm32l4_putreg(OTGFS_DIEPINT_TXFE, + stm32_putreg(OTGFS_DIEPINT_TXFE, STM32_OTGFS_DIEPINT(epno)); } } @@ -3196,34 +3196,34 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_resumeinterrupt + * Name: stm32_resumeinterrupt * * Description: * Resume/remote wakeup detected interrupt * ****************************************************************************/ -static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Notify the class driver of the resume event */ @@ -3234,7 +3234,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_suspendinterrupt + * Name: stm32_suspendinterrupt * * Description: * USB suspend interrupt @@ -3242,7 +3242,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) { #ifdef CONFIG_USBDEV_LOWPOWER uint32_t regval; @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3286,11 +3286,11 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_rxinterrupt + * Name: stm32_rxinterrupt * * Description: * RxFIFO non-empty interrupt. This interrupt indicates that there is at @@ -3298,18 +3298,18 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32_OTGFS_GRXSTSP); + regval = stm32_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ @@ -3357,7 +3357,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) OTGFS_GRXSTSD_BCNT_SHIFT; if (bcnt > 0) { - stm32l4_epout_receive(privep, bcnt); + stm32_epout_receive(privep, bcnt); } } break; @@ -3420,7 +3420,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) * packets and only that last SETUP packet will be processed. */ - stm32l4_rxfifo_read(&priv->epout[EP0], + stm32_rxfifo_read(&priv->epout[EP0], (uint8_t *)&priv->ctrlreq, USB_SIZEOF_CTRLREQ); @@ -3439,7 +3439,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { /* Reset the endpoint and Stop NAK-ing */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); /* Wait for the data phase. */ @@ -3452,7 +3452,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) */ priv->ep0state = EP0STATE_SETUP_READY; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } } break; @@ -3470,33 +3470,33 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_enuminterrupt + * Name: stm32_enuminterrupt * * Description: * Enumeration done interrupt * ****************************************************************************/ -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Activate EP0 */ - stm32l4_ep0in_activate(); + stm32_ep0in_activate(); /* Set USB turn-around time for the full speed device with internal * PHY interface. */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** - * Name: stm32l4_isocininterrupt + * Name: stm32_isocininterrupt * * Description: * Incomplete isochronous IN transfer interrupt. Assertion of the @@ -3506,7 +3506,7 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) { int i; @@ -3539,8 +3539,8 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32_OTGFS_DSTS); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3561,16 +3561,16 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DIEPCTL_USBAEP too" - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_isocoutinterrupt + * Name: stm32_isocoutinterrupt * * Description: * Incomplete periodic transfer interrupt @@ -3579,10 +3579,10 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; - struct stm32l4_req_s *privreq; + struct stm32_ep_s *privep; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t doepctl; uint32_t dsts; @@ -3623,8 +3623,8 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32_OTGFS_DSTS); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3645,16 +3645,16 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DOEPCTL_USBAEP too" - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_sessioninterrupt + * Name: stm32_sessioninterrupt * * Description: * Session request/new session detected interrupt @@ -3663,14 +3663,14 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) { #warning "Missing logic" } #endif /**************************************************************************** - * Name: stm32l4_otginterrupt + * Name: stm32_otginterrupt * * Description: * OTG interrupt @@ -3678,13 +3678,13 @@ void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Check for session end detected */ - regval = stm32l4_getreg(STM32_OTGFS_GOTGINT); + regval = stm32_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,19 +3692,19 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32_OTGFS_GOTGINT); + stm32_putreg(regval, STM32_OTGFS_GOTGINT); } #endif /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt * * Description: * USB interrupt handler * ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -3713,7 +3713,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; uint32_t regval; uint32_t reserved; @@ -3721,7 +3721,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,15 +3733,15 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32_OTGFS_GINTMSK); + regval &= stm32_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ - stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), + stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and @@ -3764,7 +3764,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); - stm32l4_epout_interrupt(priv); + stm32_epout_interrupt(priv); } /* IN endpoint interrupt. The core sets this bit to indicate that @@ -3775,7 +3775,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); - stm32l4_epin_interrupt(priv); + stm32_epin_interrupt(priv); } /* Host/device mode mismatch error interrupt */ @@ -3794,7 +3794,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); - stm32l4_resumeinterrupt(priv); + stm32_resumeinterrupt(priv); } /* USB suspend interrupt */ @@ -3803,7 +3803,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); - stm32l4_suspendinterrupt(priv); + stm32_suspendinterrupt(priv); } /* Start of frame interrupt */ @@ -3813,7 +3813,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); - usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); + usbdev_sof_irq(&priv->usbdev, stm32_getframe(&priv->usbdev)); } #endif @@ -3825,7 +3825,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); - stm32l4_rxinterrupt(priv); + stm32_rxinterrupt(priv); } /* USB reset interrupt */ @@ -3837,7 +3837,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Perform the device reset */ - stm32l4_usbreset(priv); + stm32_usbreset(priv); usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3848,7 +3848,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); - stm32l4_enuminterrupt(priv); + stm32_enuminterrupt(priv); } /* Incomplete isochronous IN transfer interrupt. When the core finds @@ -3862,7 +3862,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); - stm32l4_isocininterrupt(priv); + stm32_isocininterrupt(priv); } /* Incomplete isochronous OUT transfer. For isochronous OUT @@ -3879,7 +3879,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); - stm32l4_isocoutinterrupt(priv); + stm32_isocoutinterrupt(priv); } #endif @@ -3890,7 +3890,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); - stm32l4_sessioninterrupt(priv); + stm32_sessioninterrupt(priv); } /* OTG interrupt */ @@ -3899,7 +3899,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); - stm32l4_otginterrupt(priv); + stm32_otginterrupt(priv); } #endif } @@ -3913,28 +3913,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enablegonak + * Name: stm32_enablegonak * * Description: * Enable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) +static void stm32_enablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); + while ((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,31 +3954,31 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } /**************************************************************************** - * Name: stm32l4_disablegonak + * Name: stm32_disablegonak * * Description: * Disable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) +static void stm32_disablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_epout_configure + * Name: stm32_epout_configure * * Description: * Configure an OUT endpoint, making it usable @@ -3990,7 +3990,7 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -4043,7 +4043,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { if (regval & OTGFS_DOEPCTL_NAKSTS) @@ -4055,7 +4055,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, regval |= mpsiz; regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT); regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4066,14 +4066,14 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_epin_configure + * Name: stm32_epin_configure * * Description: * Configure an IN endpoint, making it usable @@ -4085,7 +4085,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { @@ -4139,7 +4139,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { if (regval & OTGFS_DIEPCTL_NAKSTS) @@ -4153,7 +4153,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4164,15 +4164,15 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_ep_configure + * Name: stm32_ep_configure * * Description: * Configure endpoint, making it usable @@ -4186,11 +4186,11 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t maxpacket; uint8_t eptype; int ret; @@ -4207,43 +4207,43 @@ static int stm32l4_ep_configure(struct usbdev_ep_s *ep, if (privep->isin) { - ret = stm32l4_epin_configure(privep, eptype, maxpacket); + ret = stm32_epin_configure(privep, eptype, maxpacket); } else { - ret = stm32l4_epout_configure(privep, eptype, maxpacket); + ret = stm32_epout_configure(privep, eptype, maxpacket); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0_configure + * Name: stm32_ep0_configure * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_configure(struct stm32_usbdev_s *priv) { /* Enable EP0 IN and OUT */ - stm32l4_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); - stm32l4_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); } /**************************************************************************** - * Name: stm32l4_epout_disable + * Name: stm32_epout_disable * * Description: * Disable an OUT endpoint will no longer be used * ****************************************************************************/ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) +static void stm32_epout_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4258,17 +4258,17 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits * int DOECPTL register. */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. @@ -4276,7 +4276,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) #if 0 /* Doesn't happen */ regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,36 +4285,36 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_epin_disable + * Name: stm32_epin_disable * * Description: * Disable an IN endpoint when it will no longer be used * ****************************************************************************/ -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) +static void stm32_epin_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4327,7 +4327,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { return; @@ -4342,26 +4342,26 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the INEPNE interrupt that indicates that we are now in * NAK mode */ regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, regaddr); + stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr); #endif /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits @@ -4370,49 +4370,49 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) flags = enter_critical_section(); regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the IN * endpoint is completely disabled. */ regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, stm32l4_getreg(regaddr)); + stm32_putreg(OTGFS_DIEPINT_EPDISD, stm32_getreg(regaddr)); /* Flush any data remaining in the TxFIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_ep_disable + * Name: stm32_ep_disable * * Description: * The endpoint will no longer be used * ****************************************************************************/ -static int stm32l4_ep_disable(struct usbdev_ep_s *ep) +static int stm32_ep_disable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -4430,29 +4430,29 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) { /* Disable the IN endpoint */ - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); } else { /* Disable the OUT endpoint */ - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); } return OK; } /**************************************************************************** - * Name: stm32l4_ep_allocreq + * Name: stm32_ep_allocreq * * Description: * Allocate an I/O request * ****************************************************************************/ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -4462,32 +4462,32 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) } #endif - usbtrace(TRACE_EPALLOCREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); - privreq = (struct stm32l4_req_s *) - kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = (struct stm32_req_s *) + kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_ep_freereq + * Name: stm32_ep_freereq * * Description: * Free an I/O request * ****************************************************************************/ -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) @@ -4497,12 +4497,12 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, } #endif - usbtrace(TRACE_EPFREEREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); kmm_free(privreq); } /**************************************************************************** - * Name: stm32l4_ep_allocbuffer + * Name: stm32_ep_allocbuffer * * Description: * Allocate an I/O buffer @@ -4510,10 +4510,10 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) { - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4524,7 +4524,7 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, #endif /**************************************************************************** - * Name: stm32l4_ep_freebuffer + * Name: stm32_ep_freebuffer * * Description: * Free an I/O buffer @@ -4532,9 +4532,9 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) { - usbtrace(TRACE_EPFREEBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); @@ -4545,19 +4545,19 @@ static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) #endif /**************************************************************************** - * Name: stm32l4_ep_submit + * Name: stm32_ep_submit * * Description: * Submit an I/O request to the endpoint * ****************************************************************************/ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; int ret = OK; @@ -4604,7 +4604,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, { /* Add the new request to the request queue for the endpoint. */ - if (stm32l4_req_addlast(privep, privreq) && !privep->active) + if (stm32_req_addlast(privep, privreq) && !privep->active) { /* If a request was added to an IN endpoint, then attempt to send * the request data buffer now. @@ -4620,7 +4620,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, if (!privep->active) { - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } @@ -4632,7 +4632,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, else { usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } } } @@ -4642,17 +4642,17 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_ep_cancel + * Name: stm32_ep_cancel * * Description: * Cancel an I/O request previously sent to an endpoint * ****************************************************************************/ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_FEATURES @@ -4673,20 +4673,20 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, * but ... all other implementations cancel all requests ... */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epout_setstall + * Name: stm32_epout_setstall * * Description: * Stall an OUT endpoint * ****************************************************************************/ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) +static int stm32_epout_setstall(struct stm32_ep_s *privep) { #if 1 /* This implementation follows the requirements from the STM32 F4 reference @@ -4698,16 +4698,16 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Put the core in the Global OUT NAK mode */ - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits * in the DOECPTL register. */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. @@ -4715,7 +4715,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) #if 0 /* Doesn't happen */ regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4724,7 +4724,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Disable Global OUT NAK mode */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* The endpoint is now stalled */ @@ -4743,9 +4743,9 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4755,14 +4755,14 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_epin_setstall + * Name: stm32_epin_setstall * * Description: * Stall an IN endpoint * ****************************************************************************/ -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) +static int stm32_epin_setstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4770,12 +4770,12 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) /* Get the IN endpoint device control register */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); /* Then stall the endpoint */ regval |= OTGFS_DIEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4784,14 +4784,14 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_setstall + * Name: stm32_ep_setstall * * Description: * Stall an endpoint * ****************************************************************************/ -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) +static int stm32_ep_setstall(struct stm32_ep_s *privep) { usbtrace(TRACE_EPSTALL, privep->epphy); @@ -4799,23 +4799,23 @@ static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) if (privep->isin == 1) { - return stm32l4_epin_setstall(privep); + return stm32_epin_setstall(privep); } else { - return stm32l4_epout_setstall(privep); + return stm32_epout_setstall(privep); } } /**************************************************************************** - * Name: stm32l4_ep_clrstall + * Name: stm32_ep_clrstall * * Description: * Resume a stalled endpoint * ****************************************************************************/ -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) +static int stm32_ep_clrstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4845,7 +4845,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) /* Clear the stall bit */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~stallbit; /* Set the DATA0 pid for interrupt and bulk endpoints */ @@ -4858,7 +4858,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) regval |= data0bit; } - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer stalled */ @@ -4867,16 +4867,16 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_stall + * Name: stm32_ep_stall * * Description: * Stall or resume an endpoint * ****************************************************************************/ -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; int ret; @@ -4885,11 +4885,11 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) flags = enter_critical_section(); if (resume) { - ret = stm32l4_ep_clrstall(privep); + ret = stm32_ep_clrstall(privep); } else { - ret = stm32l4_ep_setstall(privep); + ret = stm32_ep_setstall(privep); } leave_critical_section(flags); @@ -4898,19 +4898,19 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) } /**************************************************************************** - * Name: stm32l4_ep0_stall + * Name: stm32_ep0_stall * * Description: * Stall endpoint 0 * ****************************************************************************/ -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_stall(struct stm32_usbdev_s *priv) { - stm32l4_epin_setstall(&priv->epin[EP0]); - stm32l4_epout_setstall(&priv->epout[EP0]); + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); priv->stalled = true; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** @@ -4918,7 +4918,7 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_ep_alloc + * Name: stm32_ep_alloc * * Description: * Allocate an endpoint matching the parameters. @@ -4933,11 +4933,11 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t eplog, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint8_t epavail; irqstate_t flags; int epphy; @@ -5013,18 +5013,18 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, } /**************************************************************************** - * Name: stm32l4_ep_free + * Name: stm32_ep_free * * Description: * Free the previously allocated endpoint * ****************************************************************************/ -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); @@ -5040,14 +5040,14 @@ static void stm32l4_ep_free(struct usbdev_s *dev, } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Returns the current frame number * ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint32_t regval; @@ -5055,21 +5055,21 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup * * Description: * Exit suspend mode. * ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint32_t regval; irqstate_t flags; @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5108,16 +5108,16 @@ static int stm32l4_wakeup(struct usbdev_s *dev) } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered * * Description: * Sets/clears the device self-powered feature * ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); @@ -5134,21 +5134,21 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup * * Description: * Software-controlled connect to/disconnect from USB host * ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,30 +5166,30 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_setaddress + * Name: stm32_setaddress * * Description: * Set the devices USB address * ****************************************************************************/ -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) { uint32_t regval; /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5208,14 +5208,14 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_txfifo_flush + * Name: stm32_txfifo_flush * * Description: * Flush the specific TX fifo. * ****************************************************************************/ -static int stm32l4_txfifo_flush(uint32_t txfnum) +static int stm32_txfifo_flush(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32_OTGFS_GRSTCTL); + stm32_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5243,27 +5243,27 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_rxfifo_flush + * Name: stm32_rxfifo_flush * * Description: * Flush the RX fifo. * ****************************************************************************/ -static int stm32l4_rxfifo_flush(void) +static int stm32_rxfifo_flush(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); + stm32_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5277,21 +5277,21 @@ static int stm32l4_rxfifo_flush(void) } /**************************************************************************** - * Name: stm32l4_swinitialize + * Name: stm32_swinitialize * * Description: * Initialize all driver data structures. * ****************************************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_swinitialize(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; int i; /* Initialize the device state structure */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; @@ -5356,14 +5356,14 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_hwinitialize + * Name: stm32_hwinitialize * * Description: * Configure the OTG FS core for operation. * ****************************************************************************/ -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_hwinitialize(struct stm32_usbdev_s *priv) { uint32_t regval; uint32_t timeout; @@ -5372,7 +5372,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* At start-up the core is in FS mode. */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); + stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5393,7 +5393,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + stm32_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,48 +5426,48 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32_OTGFS_GCCFG); + stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32_OTGFS_GOTGCTL); + regval = stm32_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32_OTGFS_GOTGCTL); + stm32_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32_OTGFS_PCGCCTL); + stm32_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); #if STM32_NENDPOINTS > 0 /* EP0 TX */ @@ -5475,7 +5475,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF0); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif #if STM32_NENDPOINTS > 1 @@ -5484,7 +5484,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(1)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif #if STM32_NENDPOINTS > 2 @@ -5493,7 +5493,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(2)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif #if STM32_NENDPOINTS > 3 @@ -5502,7 +5502,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(3)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif #if STM32_NENDPOINTS > 4 @@ -5511,7 +5511,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(4)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif #if STM32_NENDPOINTS > 5 @@ -5520,27 +5520,27 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(5)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); - stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32_OTGFS_GINTMSK); + stm32_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32_OTGFS_GOTGINT); + stm32_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); + stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32_OTGFS_GINTMSK); + stm32_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5621,7 +5621,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * empty (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, + stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); } @@ -5653,7 +5653,7 @@ void arm_usbinitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVINIT, 0); @@ -5681,14 +5681,14 @@ void arm_usbinitialize(void) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable. */ #ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Uninitialize the hardware so that we know that we are starting from a @@ -5699,11 +5699,11 @@ void arm_usbinitialize(void) /* Initialize the driver data structure */ - stm32l4_swinitialize(priv); + stm32_swinitialize(priv); /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5712,15 +5712,15 @@ void arm_usbinitialize(void) /* Initialize the USB OTG core */ - stm32l4_hwinitialize(priv); + stm32_hwinitialize(priv); /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Reset/Re-initialize the USB hardware */ - stm32l4_usbreset(priv); + stm32_usbreset(priv); /* Enable USB controller interrupts at the NVIC */ @@ -5744,7 +5744,7 @@ void arm_usbuninitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; int i; @@ -5759,7 +5759,7 @@ void arm_usbuninitialize(void) /* Disconnect device */ flags = enter_critical_section(); - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable and detach IRQs */ @@ -5771,20 +5771,20 @@ void arm_usbuninitialize(void) for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* TODO: Turn off USB power and clocking */ @@ -5810,7 +5810,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -5856,7 +5856,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * that logic to the class drivers but left this logic here. */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -5883,7 +5883,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -5901,7 +5901,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_usbreset(priv); + stm32_usbreset(priv); leave_critical_section(flags); /* Unbind the class driver */ @@ -5915,7 +5915,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Unhook the driver */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index f40c03d08b326..a560625f724f6 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -154,7 +154,7 @@ * state machine (for debug purposes only) */ -enum stm32l4_smstate_e +enum stm32_smstate_e { SMSTATE_DETACHED = 0, /* Not attached to a device */ SMSTATE_ATTACHED, /* Attached to a device */ @@ -164,7 +164,7 @@ enum stm32l4_smstate_e /* This enumeration provides the reason for the channel halt. */ -enum stm32l4_chreason_e +enum stm32_chreason_e { CHREASON_IDLE = 0, /* Inactive (initial state) */ CHREASON_FREED, /* Channel is no longer in use */ @@ -180,15 +180,15 @@ enum stm32l4_chreason_e /* This structure retains the state of one host channel. NOTE: Since there * is only one channel operation active at a time, some of the fields in - * in the structure could be moved in struct stm32l4_ubhost_s to achieve + * in the structure could be moved in struct stm32_ubhost_s to achieve * some memory savings. */ -struct stm32l4_chan_s +struct stm32_chan_s { sem_t waitsem; /* Channel wait semaphore */ volatile uint8_t result; /* The result of the transfer */ - volatile uint8_t chreason; /* Channel halt reason. See enum stm32l4_chreason_e */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ uint8_t chidx; /* Channel index */ uint8_t epno; /* Device endpoint number (0-127) */ uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */ @@ -218,7 +218,7 @@ struct stm32l4_chan_s * the endpoint. */ -struct stm32l4_ctrlinfo_s +struct stm32_ctrlinfo_s { uint8_t inndx; /* EP0 IN control channel index */ uint8_t outndx; /* EP0 OUT control channel index */ @@ -226,7 +226,7 @@ struct stm32l4_ctrlinfo_s /* This structure retains the state of the USB host controller */ -struct stm32l4_usbhost_s +struct stm32_usbhost_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbhost_s @@ -248,7 +248,7 @@ struct stm32l4_usbhost_s volatile bool pscwait; /* True: Thread is waiting for a port event */ mutex_t lock; /* Support mutually exclusive access */ sem_t pscsem; /* Semaphore to wait for a port event */ - struct stm32l4_ctrlinfo_s ep0; /* Root hub port EP0 description */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ #ifdef CONFIG_USBHOST_HUB /* Used to pass external hub port events */ @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32_MAX_TX_FIFOS]; + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -270,96 +270,96 @@ struct stm32l4_usbhost_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t addr, uint32_t value); +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); #ifdef CONFIG_STM32_USBHOST_PKTDUMP -# define stm32l4_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else -# define stm32l4_pktdump(m,b,n) +# define stm32_pktdump(m,b,n) #endif /* Byte stream access helper functions **************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val); +static inline uint16_t stm32_getle16(const uint8_t *val); /* Channel management *******************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, +static int stm32_chan_alloc(struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv); -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, - int chidx, enum stm32l4_chreason_e chreason); -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); +static void stm32_chan_halt(struct stm32_usbhost_s *priv, + int chidx, enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep); -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, + struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); /* Control/data transfer logic **********************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx); #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void); +static inline uint16_t stm32_getframe(void); #endif -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req); -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif @@ -368,106 +368,106 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, /* Lower level interrupt handlers */ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen); -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv); -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv); +static void stm32_gint_connected(struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ #ifdef CONFIG_STM32_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv); +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void -stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv); +stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); static inline void -stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv); +stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32l4_gint_isr(int irq, void *context, void *arg); +static int stm32_gint_isr(int irq, void *context, void *arg); /* Interrupt controls */ -static void stm32l4_gint_enable(void); -static void stm32l4_gint_disable(void); -static inline void stm32l4_hostinit_enable(void); -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); /* USB host controller operations *******************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport); -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize); -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_epfree(struct usbhost_driver_s *drvr, +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen); -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen); -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer); -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer); -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_cancel(struct usbhost_driver_s *drvr, +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected); #endif -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport); /* Initialization ***********************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv); -static void stm32l4_flush_txfifos(uint32_t txfnum); -static void stm32l4_flush_rxfifo(void); -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, +static void stm32_portreset(struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv); +static void stm32_host_initialize(struct stm32_usbhost_s *priv); -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv); -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); /**************************************************************************** * Private Data @@ -478,7 +478,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); * single global instance. */ -static struct stm32l4_usbhost_s g_usbhost = +static struct stm32_usbhost_s g_usbhost = { .lock = NXMUTEX_INITIALIZER, .pscsem = SEM_INITIALIZER(0), @@ -488,8 +488,8 @@ static struct stm32l4_usbhost_s g_usbhost = static struct usbhost_connection_s g_usbconn = { - .wait = stm32l4_wait, - .enumerate = stm32l4_enumerate, + .wait = stm32_wait, + .enumerate = stm32_enumerate, }; /**************************************************************************** @@ -497,7 +497,7 @@ static struct usbhost_connection_s g_usbconn = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_printreg + * Name: stm32_printreg * * Description: * Print the contents of an STM32xx register operation @@ -505,14 +505,14 @@ static struct usbhost_connection_s g_usbconn = ****************************************************************************/ #ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { lldbg("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: stm32l4_checkreg + * Name: stm32_checkreg * * Description: * Get the contents of an STM32 register @@ -520,7 +520,7 @@ static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) ****************************************************************************/ #ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -551,7 +551,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - stm32l4_printreg(prevaddr, preval, prevwrite); + stm32_printreg(prevaddr, preval, prevwrite); } else { @@ -570,13 +570,13 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - stm32l4_printreg(addr, val, iswrite); + stm32_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register @@ -584,7 +584,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) ****************************************************************************/ #ifdef CONFIG_STM32_USBHOST_REGDEBUG -static uint32_t stm32l4_getreg(uint32_t addr) +static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -592,13 +592,13 @@ static uint32_t stm32l4_getreg(uint32_t addr) /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, false); + stm32_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -606,11 +606,11 @@ static uint32_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #ifdef CONFIG_STM32_USBHOST_REGDEBUG -static void stm32l4_putreg(uint32_t addr, uint32_t val) +static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, true); + stm32_checkreg(addr, val, true); /* Write the value */ @@ -619,41 +619,41 @@ static void stm32l4_putreg(uint32_t addr, uint32_t val) #endif /**************************************************************************** - * Name: stm32l4_modifyreg + * Name: stm32_modifyreg * * Description: * Modify selected bits of an STM32 register. * ****************************************************************************/ -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits) { - stm32l4_putreg(addr, (((stm32l4_getreg(addr)) & ~clrbits) | setbits)); + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); } /**************************************************************************** - * Name: stm32l4_getle16 + * Name: stm32_getle16 * * Description: * Get a (possibly unaligned) 16-bit little endian value. * ****************************************************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val) +static inline uint16_t stm32_getle16(const uint8_t *val) { return (uint16_t)val[1] << 8 | (uint16_t)val[0]; } /**************************************************************************** - * Name: stm32l4_chan_alloc + * Name: stm32_chan_alloc * * Description: * Allocate a channel. * ****************************************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) +static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; @@ -678,20 +678,20 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_chan_free + * Name: stm32_chan_free * * Description: * Free a previoiusly allocated channel. * ****************************************************************************/ -static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) +static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) { DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_FREED); + stm32_chan_halt(priv, chidx, CHREASON_FREED); /* Mark the channel available */ @@ -699,14 +699,14 @@ static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) } /**************************************************************************** - * Name: stm32l4_chan_freeall + * Name: stm32_chan_freeall * * Description: * Free all channels. * ****************************************************************************/ -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) { uint8_t chidx; @@ -714,12 +714,12 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { - stm32l4_chan_free(priv, chidx); + stm32_chan_free(priv, chidx); } } /**************************************************************************** - * Name: stm32l4_chan_configure + * Name: stm32_chan_configure * * Description: * Configure or re-configure a host channel. Host channels are configured @@ -728,15 +728,15 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,11 +876,11 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** - * Name: stm32l4_chan_halt + * Name: stm32_chan_halt * * Description: * Halt the channel associated with 'chidx' by setting the CHannel DISable @@ -888,8 +888,8 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, - enum stm32l4_chreason_e chreason) +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) { uint32_t hcchar; uint32_t intmsk; @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32_OTGFS_HNPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32_OTGFS_HPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,17 +957,17 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + intmsk = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** - * Name: stm32l4_chan_waitsetup + * Name: stm32_chan_waitsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -982,8 +982,8 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags = enter_critical_section(); int ret = -ENODEV; @@ -1010,7 +1010,7 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_asynchsetup + * Name: stm32_chan_asynchsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -1025,8 +1025,8 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg) { irqstate_t flags = enter_critical_section(); @@ -1053,7 +1053,7 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_chan_wait + * Name: stm32_chan_wait * * Description: * Wait for a transfer on a channel to complete. @@ -1063,8 +1063,8 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags; int ret; @@ -1102,7 +1102,7 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_wakeup + * Name: stm32_chan_wakeup * * Description: * A channel transfer has completed... wakeup any threads waiting for the @@ -1114,8 +1114,8 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { /* Is the transfer complete? */ @@ -1151,11 +1151,11 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, if (chan->in) { - stm32l4_in_next(priv, chan); + stm32_in_next(priv, chan); } else { - stm32l4_out_next(priv, chan); + stm32_out_next(priv, chan); } } #endif @@ -1163,23 +1163,23 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_ctrlchan_alloc + * Name: stm32_ctrlchan_alloc * * Description: * Allocate and configured channels for a control pipe. * ****************************************************************************/ -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep) + struct stm32_ctrlinfo_s *ctrlep) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int inndx; int outndx; - outndx = stm32l4_chan_alloc(priv); + outndx = stm32_chan_alloc(priv); if (outndx < 0) { return -ENOMEM; @@ -1199,14 +1199,14 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, /* Configure control OUT channels */ - stm32l4_chan_configure(priv, outndx); + stm32_chan_configure(priv, outndx); /* Allocate and initialize the control IN channel */ - inndx = stm32l4_chan_alloc(priv); + inndx = stm32_chan_alloc(priv); if (inndx < 0) { - stm32l4_chan_free(priv, outndx); + stm32_chan_free(priv, outndx); return -ENOMEM; } @@ -1224,12 +1224,12 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, /* Configure control IN channels */ - stm32l4_chan_configure(priv, inndx); + stm32_chan_configure(priv, inndx); return OK; } /**************************************************************************** - * Name: stm32l4_ctrlep_alloc + * Name: stm32_ctrlep_alloc * * Description: * Allocate a container and channels for control pipe. @@ -1249,12 +1249,12 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_ctrlinfo_s *ctrlep; + struct stm32_ctrlinfo_s *ctrlep; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -1266,8 +1266,8 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a container for the control endpoint */ - ctrlep = (struct stm32l4_ctrlinfo_s *) - kmm_malloc(sizeof(struct stm32l4_ctrlinfo_s)); + ctrlep = (struct stm32_ctrlinfo_s *) + kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); if (ctrlep == NULL) { uerr("ERROR: Failed to allocate control endpoint container\n"); @@ -1276,11 +1276,11 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Then allocate and configure the IN/OUT channels */ - ret = stm32l4_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, hport->funcaddr, hport->speed, ctrlep); if (ret < 0) { - uerr("ERROR: stm32l4_ctrlchan_alloc failed: %d\n", ret); + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); kmm_free(ctrlep); return ret; } @@ -1292,7 +1292,7 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_xfrep_alloc + * Name: stm32_xfrep_alloc * * Description: * Allocate and configure one unidirectional endpoint. @@ -1312,12 +1312,12 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int chidx; /* Sanity check. NOTE that this method should only be called if a device @@ -1329,7 +1329,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a host channel for the endpoint */ - chidx = stm32l4_chan_alloc(priv); + chidx = stm32_chan_alloc(priv); if (chidx < 0) { uerr("ERROR: Failed to allocate a host channel\n"); @@ -1355,7 +1355,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Then configure the endpoint */ - stm32l4_chan_configure(priv, chidx); + stm32_chan_configure(priv, chidx); /* Return the index to the allocated channel as the endpoint "handle" */ @@ -1364,17 +1364,17 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_transfer_start + * Name: stm32_transfer_start * * Description: * Start at transfer on the select IN or OUT channel. * ****************************************************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int npackets; unsigned int maxpacket; @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); + stm32_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32_OTGFS_HFNUM) & 1) == 0) + if ((stm32_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1541,7 +1541,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, /* Write packet into the Tx FIFO. */ - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /* Did we put the entire buffer into the Tx FIFO? */ @@ -1553,13 +1553,13 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * FIFO becomes empty. */ - stm32l4_txfe_enable(priv, chidx); + stm32_txfe_enable(priv, chidx); } } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Get the current frame number. The frame number (FRNUM) field increments @@ -1569,26 +1569,26 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void) +static inline uint16_t stm32_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif /**************************************************************************** - * Name: stm32l4_ctrl_sendsetup + * Name: stm32_ctrl_sendsetup * * Description: * Send an IN/OUT SETUP packet. * ****************************************************************************/ -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; int ret; @@ -1609,7 +1609,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1618,11 +1618,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Return on success and for all failures other than EAGAIN. EAGAIN * means that the device NAKed the SETUP command and that we should @@ -1653,7 +1653,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_ctrl_senddata + * Name: stm32_ctrl_senddata * * Description: * Send data in the data phase of an OUT control transfer. Or send status @@ -1661,11 +1661,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->outndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; int ret; /* Save buffer information */ @@ -1689,7 +1689,7 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1698,15 +1698,15 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_ctrl_recvdata + * Name: stm32_ctrl_recvdata * * Description: * Receive data in the data phase of an IN control transfer. Or receive @@ -1714,11 +1714,11 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->inndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; int ret; /* Save buffer information */ @@ -1730,7 +1730,7 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1739,24 +1739,24 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->inndx); + stm32_transfer_start(priv, ep0->inndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_in_setup + * Name: stm32_in_setup * * Description: * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -1803,23 +1803,23 @@ static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_in_transfer + * Name: stm32_in_transfer * * Description: * Transfer 'buflen' bytes into 'buffer' from an IN channel. * ****************************************************************************/ -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; ssize_t xfrd; int ret; @@ -1840,7 +1840,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, { /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1849,16 +1849,16 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* EAGAIN indicates that the device NAKed the transfer. */ @@ -1973,7 +1973,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } } @@ -1993,7 +1993,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_in_next + * Name: stm32_in_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2004,8 +2004,8 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2022,13 +2022,13 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_in_setup(priv, chan->chidx); + ret = stm32_in_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); result = ret; } @@ -2058,7 +2058,7 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_in_asynch + * Name: stm32_in_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2069,11 +2069,11 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2083,19 +2083,19 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2105,16 +2105,16 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_out_setup + * Name: stm32_out_setup * * Description: * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -2165,23 +2165,23 @@ static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_out_transfer + * Name: stm32_out_transfer * * Description: * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. * ****************************************************************************/ -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; size_t xfrlen; @@ -2212,7 +2212,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -2221,16 +2221,16 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Handle transfer failures */ @@ -2253,7 +2253,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, { /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } @@ -2261,7 +2261,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, * the data in the FIFO when the NAK occurs? Does it discard it? */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); /* Get the device a little time to catch up. Then retry the * transfer using the same buffer pointer and length. @@ -2284,7 +2284,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_out_next + * Name: stm32_out_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2295,8 +2295,8 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2313,13 +2313,13 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_out_setup(priv, chan->chidx); + ret = stm32_out_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); result = ret; } @@ -2349,7 +2349,7 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_out_asynch + * Name: stm32_out_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2360,11 +2360,11 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2374,19 +2374,19 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2396,7 +2396,7 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_gint_wrpacket + * Name: stm32_gint_wrpacket * * Description: * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with @@ -2404,14 +2404,14 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen) { uint32_t *src; uint32_t fifo; int buflen32; - stm32l4_pktdump("Sending", buffer, buflen); + stm32_pktdump("Sending", buffer, buflen); /* Get the number of 32-byte words associated with this byte size */ @@ -2427,7 +2427,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, for (; buflen32 > 0; buflen32--) { uint32_t data = *src++; - stm32l4_putreg(fifo, data); + stm32_putreg(fifo, data); } /* Increment the count of bytes "in-flight" in the Tx FIFO */ @@ -2436,7 +2436,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_gint_hcinisr + * Name: stm32_gint_hcinisr * * Description: * USB OTG FS host IN channels interrupt handler @@ -2454,10 +2454,10 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,14 +2489,14 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); /* When there is a STALL, clear any pending NAK so that it is not * processed below. @@ -2513,11 +2513,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2527,11 +2527,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2549,22 +2549,22 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear any pending NAK condition. The 'indata1' data toggle * should have been appropriately updated by the RxFIFO * logic as each packet was received. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2629,11 +2629,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2654,7 +2654,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); } /* Re-activate CTRL and BULK channels. @@ -2671,30 +2671,30 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else /* Halt all transfers on the NAK -- CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); #endif /* Clear the NAK condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_hcoutisr + * Name: stm32_gint_hcoutisr * * Description: * USB OTG FS host OUT channels interrupt handler @@ -2712,10 +2712,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2747,11 +2747,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel (probably not necessary for FRMOR) */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2768,11 +2768,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,13 +2781,13 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2796,11 +2796,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2811,11 +2811,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2825,11 +2825,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_NYET); + stm32_chan_halt(priv, chidx, CHREASON_NYET); /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2841,11 +2841,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,23 +2913,23 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_connected + * Name: stm32_gint_connected * * Description: * Handle a connection event. * ****************************************************************************/ -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_connected(struct stm32_usbhost_s *priv) { /* We we previously disconnected? */ @@ -2954,14 +2954,14 @@ static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_disconnected + * Name: stm32_gint_disconnected * * Description: * Handle a disconnection event. * ****************************************************************************/ -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) { /* Were we previously connected? */ @@ -2986,7 +2986,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) priv->smstate = SMSTATE_DETACHED; priv->connected = false; priv->change = true; - stm32l4_chan_freeall(priv); + stm32_chan_freeall(priv); priv->rhport.hport.speed = USB_SPEED_FULL; priv->rhport.hport.funcaddr = 0; @@ -3002,7 +3002,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_sofisr + * Name: stm32_gint_sofisr * * Description: * USB OTG FS start-of-frame interrupt handler @@ -3010,7 +3010,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3018,19 +3018,19 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif /**************************************************************************** - * Name: stm32l4_gint_rxflvlisr + * Name: stm32_gint_rxflvlisr * * Description: * USB OTG FS RxFIFO non-empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) { uint32_t *dest; uint32_t grxsts; @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32_OTGFS_GINTMSK); + intmsk = stm32_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32_OTGFS_GRXSTSP); + grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3082,10 +3082,10 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) for (i = 0; i < bcnt32; i++) { - *dest++ = stm32l4_getreg(fifo); + *dest++ = stm32_getreg(fifo); } - stm32l4_pktdump("Received", priv->chan[chidx].buffer, bcnt); + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); /* Toggle the IN data pid (Used by Bulk and INTR only) */ @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,20 +3121,20 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** - * Name: stm32l4_gint_nptxfeisr + * Name: stm32_gint_nptxfeisr * * Description: * USB OTG FS non-periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3211,20 +3211,20 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) "wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_ptxfeisr + * Name: stm32_gint_ptxfeisr * * Description: * USB OTG FS periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3301,18 +3301,18 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) " buflen: %d xfrd: %d wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_hcisr + * Name: stm32_gint_hcisr * * Description: * USB OTG FS host channels interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) { uint32_t haint; uint32_t hcchar; @@ -3323,7 +3323,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32_OTGFS_HAINT); + haint = stm32_getreg(STM32_OTGFS_HAINT); for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(i)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3340,27 +3340,27 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Handle the HC IN channel interrupt */ - stm32l4_gint_hcinisr(priv, i); + stm32_gint_hcinisr(priv, i); } else { /* Handle the HC OUT channel interrupt */ - stm32l4_gint_hcoutisr(priv, i); + stm32_gint_hcoutisr(priv, i); } } } } /**************************************************************************** - * Name: stm32l4_gint_hprtisr + * Name: stm32_gint_hprtisr * * Description: * USB OTG FS host port interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) { uint32_t hprt; uint32_t newhprt; @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32_OTGFS_HPRT); + hprt = stm32_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3402,8 +3402,8 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PCDET, 0); newhprt |= OTGFS_HPRT_PCDET; - stm32l4_portreset(priv); - stm32l4_gint_connected(priv); + stm32_portreset(priv); + stm32_gint_connected(priv); } /* Check for Port Enable CHaNGed (PENCHNG) */ @@ -3421,11 +3421,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) { /* Yes.. handle the new connection event */ - stm32l4_gint_connected(priv); + stm32_gint_connected(priv); /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32_OTGFS_HCFG); + hcfg = stm32_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32_OTGFS_HFIR, 6000); + stm32_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,17 +3449,17 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32_OTGFS_HFIR, 48000); + stm32_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,11 +3472,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } } @@ -3484,37 +3484,37 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32_OTGFS_HPRT, newhprt); + stm32_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** - * Name: stm32l4_gint_discisr + * Name: stm32_gint_discisr * * Description: * USB OTG FS disconnect detected interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) { /* Handle the disconnection event */ - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** - * Name: stm32l4_gint_ipxfrisr + * Name: stm32_gint_ipxfrisr * * Description: * USB OTG FS incomplete periodic interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) { uint32_t regval; @@ -3522,24 +3522,24 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(0)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32_OTGFS_HCCHAR(0), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** - * Name: stm32l4_gint_isr + * Name: stm32_gint_isr * * Description: * USB OTG FS global interrupt handler * ****************************************************************************/ -static int stm32l4_gint_isr(int irq, void *context, void *arg) +static int stm32_gint_isr(int irq, void *context, void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -3548,7 +3548,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; uint32_t pending; /* If OTG were supported, we would need to check if we are in host or @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32_OTGFS_GINTMSK); + pending = stm32_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3584,7 +3584,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_SOF) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); - stm32l4_gint_sofisr(priv); + stm32_gint_sofisr(priv); } #endif @@ -3593,7 +3593,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_RXFLVL) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_RXFLVL, 0); - stm32l4_gint_rxflvlisr(priv); + stm32_gint_rxflvlisr(priv); } /* Handle the non-periodic TxFIFO empty interrupt */ @@ -3601,7 +3601,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_NPTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); - stm32l4_gint_nptxfeisr(priv); + stm32_gint_nptxfeisr(priv); } /* Handle the periodic TxFIFO empty interrupt */ @@ -3609,7 +3609,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_PTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); - stm32l4_gint_ptxfeisr(priv); + stm32_gint_ptxfeisr(priv); } /* Handle the host channels interrupt */ @@ -3617,14 +3617,14 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_HC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); - stm32l4_gint_hcisr(priv); + stm32_gint_hcisr(priv); } /* Handle the host port interrupt */ if ((pending & OTGFS_GINT_HPRT) != 0) { - stm32l4_gint_hprtisr(priv); + stm32_gint_hprtisr(priv); } /* Handle the disconnect detected interrupt */ @@ -3632,7 +3632,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_DISC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); - stm32l4_gint_discisr(priv); + stm32_gint_discisr(priv); } /* Handle the incomplete periodic transfer */ @@ -3640,7 +3640,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_IPXFR) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); - stm32l4_gint_ipxfrisr(priv); + stm32_gint_ipxfrisr(priv); } } @@ -3650,7 +3650,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_gint_enable and stm32l4_gint_disable + * Name: stm32_gint_enable and stm32_gint_disable * * Description: * Respectively enable or disable the global OTG FS interrupt. @@ -3663,30 +3663,30 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static void stm32l4_gint_enable(void) +static void stm32_gint_enable(void) { uint32_t regval; /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } -static void stm32l4_gint_disable(void) +static void stm32_gint_disable(void) { uint32_t regval; /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** - * Name: stm32l4_hostinit_enable + * Name: stm32_hostinit_enable * * Description: * Enable host interrupts. @@ -3699,25 +3699,25 @@ static void stm32l4_gint_disable(void) * ****************************************************************************/ -static inline void stm32l4_hostinit_enable(void) +static inline void stm32_hostinit_enable(void) { uint32_t regval; /* Disable all interrupts. */ - stm32l4_putreg(STM32_OTGFS_GINTMSK, 0); + stm32_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); + stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3753,11 +3753,11 @@ static inline void stm32l4_hostinit_enable(void) regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** - * Name: stm32l4_txfe_enable + * Name: stm32_txfe_enable * * Description: * Enable Tx FIFO empty interrupts. This is necessary when the entire @@ -3778,10 +3778,10 @@ static inline void stm32l4_hostinit_enable(void) * ****************************************************************************/ -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; irqstate_t flags; uint32_t regval; @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTMSK); + regval = stm32_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3819,7 +3819,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_wait + * Name: stm32_wait * * Description: * Wait for a device to be connected or disconnected to/from a hub port. @@ -3843,10 +3843,10 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; struct usbhost_hubport_s *connport; irqstate_t flags; int ret; @@ -3910,7 +3910,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, } /**************************************************************************** - * Name: stm32l4_enumerate + * Name: stm32_enumerate * * Description: * Enumerate the connected device. As part of this enumeration process, @@ -3937,7 +3937,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { @@ -3968,11 +3968,11 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Get the current device speed */ - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -3984,7 +3984,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Allocate and initialize the root hub port EP0 channels */ - ret = stm32l4_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0); if (ret < 0) { @@ -3994,10 +3994,10 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, return ret; } -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; int ret; DEBUGASSERT(hport); @@ -4011,7 +4011,7 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, if (ROOTHUB(hport)) #endif { - ret = stm32l4_rh_enumerate(priv, conn, hport); + ret = stm32_rh_enumerate(priv, conn, hport); if (ret < 0) { return ret; @@ -4035,14 +4035,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, /* Return to the disconnected state */ uerr("ERROR: Enumeration failed: %d\n", ret); - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0configure + * Name: stm32_ep0configure * * Description: * Configure endpoint 0. This method is normally used internally by the @@ -4068,14 +4068,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; + struct stm32_chan_s *chan; int ret; DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && @@ -4096,7 +4096,7 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->outndx); + stm32_chan_configure(priv, ep0info->outndx); /* Configure the EP0 IN channel */ @@ -4105,14 +4105,14 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->inndx); + stm32_chan_configure(priv, ep0info->inndx); nxmutex_unlock(&priv->lock); return OK; } /**************************************************************************** - * Name: stm32l4_epalloc + * Name: stm32_epalloc * * Description: * Allocate and configure one endpoint. @@ -4133,11 +4133,11 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -4162,11 +4162,11 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, if (epdesc->xfrtype == OTGFS_EPTYPE_CTRL) { - ret = stm32l4_ctrlep_alloc(priv, epdesc, ep); + ret = stm32_ctrlep_alloc(priv, epdesc, ep); } else { - ret = stm32l4_xfrep_alloc(priv, epdesc, ep); + ret = stm32_xfrep_alloc(priv, epdesc, ep); } nxmutex_unlock(&priv->lock); @@ -4174,7 +4174,7 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_epfree + * Name: stm32_epfree * * Description: * Free and endpoint previously allocated by DRVR_EPALLOC. @@ -4193,9 +4193,9 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; DEBUGASSERT(priv); @@ -4213,17 +4213,17 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { /* Halt the channel and mark the channel available */ - stm32l4_chan_free(priv, (int)ep); + stm32_chan_free(priv, (int)ep); } else { /* Halt both control channel and mark the channels available */ - struct stm32l4_ctrlinfo_s *ctrlep = - (struct stm32l4_ctrlinfo_s *)ep; + struct stm32_ctrlinfo_s *ctrlep = + (struct stm32_ctrlinfo_s *)ep; - stm32l4_chan_free(priv, ctrlep->inndx); - stm32l4_chan_free(priv, ctrlep->outndx); + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); /* And free the control endpoint container */ @@ -4235,7 +4235,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_alloc + * Name: stm32_alloc * * Description: * Some hardware supports special memory in which request and descriptor @@ -4268,7 +4268,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #warning this function name is too generic -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen) { uint8_t *alloc; @@ -4291,7 +4291,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_free + * Name: stm32_free * * Description: * Some hardware supports special memory in which request and descriptor @@ -4315,7 +4315,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4326,7 +4326,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ioalloc + * Name: stm32_ioalloc * * Description: * Some hardware supports special memory in which larger IO buffers can @@ -4355,7 +4355,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen) { uint8_t *alloc; @@ -4377,7 +4377,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_iofree + * Name: stm32_iofree * * Description: * Some hardware supports special memory in which IO data can be accessed @@ -4399,7 +4399,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4410,7 +4410,7 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ctrlin and stm32l4_ctrlout + * Name: stm32_ctrlin and stm32_ctrlout * * Description: * Process a IN or OUT request on the control endpoint. These methods @@ -4446,14 +4446,14 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4468,7 +4468,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4484,7 +4484,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4495,7 +4495,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, if (buflen > 0) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, buffer, buflen); + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_RECVDATA, -ret); @@ -4511,7 +4511,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Handle the status OUT phase */ priv->chan[ep0info->outndx].outdata1 ^= true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactions exit here */ @@ -4535,14 +4535,14 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, return -ETIMEDOUT; } -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4557,7 +4557,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4573,7 +4573,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4592,7 +4592,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Start DATA out transfer (only one DATA packet) */ priv->chan[ep0info->outndx].outdata1 = true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDDATA, -ret); @@ -4603,7 +4603,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, if (ret == OK) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactins exit here */ @@ -4629,7 +4629,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_transfer + * Name: stm32_transfer * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4667,11 +4667,11 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; ssize_t nbytes; int ret; @@ -4692,11 +4692,11 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, if (priv->chan[chidx].in) { - nbytes = stm32l4_in_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); } else { - nbytes = stm32l4_out_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); } nxmutex_unlock(&priv->lock); @@ -4704,7 +4704,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_asynch + * Name: stm32_asynch * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4740,11 +4740,11 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; int ret; @@ -4764,11 +4764,11 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, if (priv->chan[chidx].in) { - ret = stm32l4_in_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); } else { - ret = stm32l4_out_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); } nxmutex_unlock(&priv->lock); @@ -4777,7 +4777,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, #endif /* CONFIG_USBHOST_ASYNCH */ /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel a pending transfer on an endpoint. Cancelled synchronous or @@ -4795,10 +4795,10 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * ****************************************************************************/ -static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_chan_s *chan; unsigned int chidx = (unsigned int)ep; irqstate_t flags; @@ -4815,7 +4815,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_CANCELLED); + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); chan->result = -ESHUTDOWN; /* Is there a thread waiting for this transfer to complete? */ @@ -4864,7 +4864,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_connect + * Name: stm32_connect * * Description: * New connections may be detected by an attached hub. This method is @@ -4885,11 +4885,11 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; irqstate_t flags; DEBUGASSERT(priv != NULL && hport != NULL); @@ -4916,7 +4916,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, #endif /**************************************************************************** - * Name: stm32l4_disconnect + * Name: stm32_disconnect * * Description: * Called by the class when an error occurs and driver has been @@ -4941,7 +4941,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport) { DEBUGASSERT(hport != NULL); @@ -4953,7 +4953,7 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_portreset + * Name: stm32_portreset * * Description: * Reset the USB host port. @@ -4972,26 +4972,26 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) +static void stm32_portreset(struct stm32_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } /**************************************************************************** - * Name: stm32l4_flush_txfifos + * Name: stm32_flush_txfifos * * Description: * Flush the selected Tx FIFO. @@ -5004,7 +5004,7 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_flush_txfifos(uint32_t txfnum) +static void stm32_flush_txfifos(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32_OTGFS_GRSTCTL, regval); + stm32_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5031,7 +5031,7 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_flush_rxfifo + * Name: stm32_flush_rxfifo * * Description: * Flush the Rx FIFO. @@ -5044,20 +5044,20 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) * ****************************************************************************/ -static void stm32l4_flush_rxfifo(void) +static void stm32_flush_rxfifo(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5070,7 +5070,7 @@ static void stm32l4_flush_rxfifo(void) } /**************************************************************************** - * Name: stm32l4_vbusdrive + * Name: stm32_vbusdrive * * Description: * Drive the Vbus +5V. @@ -5084,41 +5084,41 @@ static void stm32l4_flush_rxfifo(void) * ****************************************************************************/ -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) { uint32_t regval; /* Enable/disable the external charge pump */ - stm32l4_usbhost_vbusdrive(0, state); + stm32_usbhost_vbusdrive(0, state); /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); } /**************************************************************************** - * Name: stm32l4_host_initialize + * Name: stm32_host_initialize * * Description: * Initialize/re-initialize hardware for host mode operation. At present, - * this function is called only from stm32l4_hw_initialize(). But if OTG + * this function is called only from stm32_hw_initialize(). But if OTG * mode were supported, this function would also be called to switch * between host and device modes on a connector ID change interrupt. * @@ -5130,7 +5130,7 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) * ****************************************************************************/ -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) +static void stm32_host_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; uint32_t offset; @@ -5138,24 +5138,24 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32_OTGFS_PCGCCTL, 0); + stm32_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,7 +5163,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); + stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ @@ -5171,7 +5171,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32_OTGFS_HNPTXFSIZ, regval); + stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ @@ -5179,7 +5179,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32_OTGFS_HPTXFSIZ, regval); + stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5187,30 +5187,30 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Flush all FIFOs */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); - stm32l4_flush_rxfifo(); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); /* Clear all pending HC Interrupts */ for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32_OTGFS_HCINTMSK(i), 0); + stm32_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG * mode. */ - stm32l4_vbusdrive(priv, true); + stm32_vbusdrive(priv, true); /* Enable host interrupts */ - stm32l4_hostinit_enable(); + stm32_hostinit_enable(); } /**************************************************************************** - * Name: stm32l4_sw_initialize + * Name: stm32_sw_initialize * * Description: * One-time setup of the host driver state structure. @@ -5223,7 +5223,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) { struct usbhost_driver_s *drvr; struct usbhost_hubport_s *hport; @@ -5232,24 +5232,24 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Initialize the device operations */ drvr = &priv->drvr; - drvr->ep0configure = stm32l4_ep0configure; - drvr->epalloc = stm32l4_epalloc; - drvr->epfree = stm32l4_epfree; - drvr->alloc = stm32l4_alloc; - drvr->free = stm32l4_free; - drvr->ioalloc = stm32l4_ioalloc; - drvr->iofree = stm32l4_iofree; - drvr->ctrlin = stm32l4_ctrlin; - drvr->ctrlout = stm32l4_ctrlout; - drvr->transfer = stm32l4_transfer; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; #ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = stm32l4_asynch; + drvr->asynch = stm32_asynch; #endif - drvr->cancel = stm32l4_cancel; + drvr->cancel = stm32_cancel; #ifdef CONFIG_USBHOST_HUB - drvr->connect = stm32l4_connect; + drvr->connect = stm32_connect; #endif - drvr->disconnect = stm32l4_disconnect; + drvr->disconnect = stm32_disconnect; /* Initialize the public port representation */ @@ -5275,13 +5275,13 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); /* Initialize each channel */ for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { - struct stm32l4_chan_s *chan = &priv->chan[i]; + struct stm32_chan_s *chan = &priv->chan[i]; chan->chidx = i; nxsem_init(&chan->waitsem, 0, 0); @@ -5289,7 +5289,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_hw_initialize + * Name: stm32_hw_initialize * * Description: * One-time setup of the host controller hardware for normal operations. @@ -5302,7 +5302,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; unsigned long timeout; @@ -5311,9 +5311,9 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. @@ -5322,7 +5322,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5355,7 +5355,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifdef CONFIG_STM32_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32_OTGFS_GCCFG, regval); + stm32_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,15 +5364,15 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ - stm32l4_host_initialize(priv); + stm32_host_initialize(priv); return OK; } @@ -5381,7 +5381,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -5405,7 +5405,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) +struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; /* Sanity checks */ @@ -5422,11 +5422,11 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Make sure that interrupts from the OTG FS core are disabled */ - stm32l4_gint_disable(); + stm32_gint_disable(); /* Reset the state of the host driver */ - stm32l4_sw_initialize(priv); + stm32_sw_initialize(priv); /* Alternate function pin configuration. Here we assume that: * @@ -5451,23 +5451,23 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable */ #ifdef CONFIG_STM32_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Initialize the USB OTG FS core */ - stm32l4_hw_initialize(priv); + stm32_hw_initialize(priv); /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5475,7 +5475,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable USB OTG FS global interrupts */ - stm32l4_gint_enable(); + stm32_gint_enable(); /* Enable interrupts at the interrupt controller */ diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h index 466571b6330d4..b4cf0be0318fa 100644 --- a/arch/arm/src/stm32l4/stm32l4_pm.h +++ b/arch/arm/src/stm32l4/stm32l4_pm.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32l4_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32l4_pmstop(bool lpds); * ****************************************************************************/ -int stm32l4_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32l4_pmstop2(void); * ****************************************************************************/ -int stm32l4_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32l4_pmstandby(void); * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32l4_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32l4_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index d43ae86f66ffb..ae7a525c5eb21 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -54,7 +54,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -69,7 +69,7 @@ * ****************************************************************************/ -int stm32l4_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmsleep.c b/arch/arm/src/stm32l4/stm32l4_pmsleep.c index 24e4170a62acf..24dd46592318e 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmsleep.c +++ b/arch/arm/src/stm32l4/stm32l4_pmsleep.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index 0866f7a2f5a53..759ef841e9bf0 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -69,7 +69,7 @@ * ****************************************************************************/ -int stm32l4_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index f116c76968fbd..cd57bbd4aa83d 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -88,7 +88,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -106,7 +106,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32l4_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -130,7 +130,7 @@ int stm32l4_pmstop(bool lpds) } /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -145,7 +145,7 @@ int stm32l4_pmstop(bool lpds) * ****************************************************************************/ -int stm32l4_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 4c4a4d4691e20..14704082eb707 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pulsecount.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_tim.h" /* This module then only compiles if there is at least one enabled timer @@ -66,7 +66,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pulsecount_dumpgpio(p,m) #endif @@ -77,7 +77,7 @@ /* Pulsecount output configuration */ -struct stm32l4_out_s +struct stm32_out_s { uint8_t in_use:1; uint8_t pol:1; @@ -88,17 +88,17 @@ struct stm32l4_out_s /* Pulsecount channel configuration */ -struct stm32l4_chan_s +struct stm32_chan_s { uint8_t channel; - struct stm32l4_out_s out1; + struct stm32_out_s out1; }; /* This structure represents the state of one pulsecount timer */ -struct stm32l4_tim_s +struct stm32_tim_s { - struct stm32l4_chan_s channel; + struct stm32_chan_s channel; uint8_t timid:5; uint8_t timtype:3; uint8_t t_dts:3; @@ -113,10 +113,10 @@ struct stm32l4_tim_s void *handle; }; -struct stm32l4_pulsecount_s +struct stm32_pulsecount_s { const struct pulsecount_ops_s *ops; - struct stm32l4_tim_s *timer; + struct stm32_tim_s *timer; }; /**************************************************************************** @@ -125,10 +125,10 @@ struct stm32l4_pulsecount_s /* Register access */ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value); -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_TIMER_INFO @@ -146,11 +146,11 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty); static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency); -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv); +static int pulsecount_timer_configure(struct stm32_tim_s *priv); static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel); -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, - struct stm32l4_chan_s *chan); +static int pulsecount_output_configure(struct stm32_tim_s *priv, + struct stm32_chan_s *chan); static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state); static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, @@ -191,7 +191,7 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, #ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount1dev = +static struct stm32_tim_s g_pulsecount1dev = { .channel = { @@ -242,7 +242,7 @@ static struct stm32l4_tim_s g_pulsecount1dev = #ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount8dev = +static struct stm32_tim_s g_pulsecount8dev = { .channel = { @@ -301,7 +301,7 @@ static const struct pulsecount_ops_s g_pulsecountops = }; #ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount1lower = +static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount1dev, @@ -309,7 +309,7 @@ static struct stm32l4_pulsecount_s g_pulsecount1lower = #endif #ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount8lower = +static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount8dev, @@ -335,7 +335,7 @@ static struct stm32l4_pulsecount_s g_pulsecount8lower = * ****************************************************************************/ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -355,7 +355,7 @@ static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) * ****************************************************************************/ -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value) { putreg16(value, priv->base + offset); @@ -378,7 +378,7 @@ static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, * ****************************************************************************/ -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { modifyreg16(priv->base + offset, (uint16_t)clearbits, @@ -403,7 +403,7 @@ static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, const char *msg) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", @@ -441,7 +441,7 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t offset = 0; /* CCR channel indices are one-based to match timer channel numbers. */ @@ -505,7 +505,7 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -547,7 +547,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -632,7 +632,7 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, * ****************************************************************************/ -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) +static int pulsecount_timer_configure(struct stm32_tim_s *priv) { uint16_t cr1 = 0; @@ -669,7 +669,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -765,7 +765,7 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, * ****************************************************************************/ -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, +static int pulsecount_output_configure(struct stm32_tim_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -824,7 +824,7 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, * * Input Parameters: * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32l4_pulsecount_chan_e) + * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) * state - Enable/disable operation * ****************************************************************************/ @@ -832,7 +832,7 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; @@ -877,7 +877,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, bool enable) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; if (enable) { @@ -898,7 +898,7 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, ****************************************************************************/ static uint16_t -pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, +pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) { uint16_t outputs = 0; @@ -925,7 +925,7 @@ pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t outputs = 0; int ret = OK; @@ -991,7 +991,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; ub16_t duty = 0; uint8_t channel = 0; uint16_t outputs = 0; @@ -1139,7 +1139,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t regval; /* Verify that this is an update interrupt. Nothing else is expected. */ @@ -1297,7 +1297,7 @@ static uint8_t pulsecount_count(uint32_t count) * ****************************************************************************/ -static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, +static int pulsecount_setapbclock(struct stm32_tim_s *priv, bool on) { uint32_t en_bit; @@ -1371,7 +1371,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg; _info("TIM%u\n", priv->timid); @@ -1389,7 +1389,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) pincfg = priv->channel.out1.pincfg; _info("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pulsecount_dumpgpio(pincfg, "pulsecount setup"); } @@ -1414,7 +1414,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg = 0; int ret = OK; @@ -1442,7 +1442,7 @@ static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } errout: @@ -1470,7 +1470,7 @@ static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -1547,7 +1547,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; /* There are no platform-specific ioctl commands */ @@ -1558,7 +1558,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; int ret; ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); @@ -1572,7 +1572,7 @@ static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) pulse->timer); } @@ -1581,8 +1581,8 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info, void *handle) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; - struct stm32l4_tim_s *priv = pulse->timer; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + struct stm32_tim_s *priv = pulse->timer; if (info->count > 0) { @@ -1600,14 +1600,14 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); } static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, cmd, arg); } @@ -1616,9 +1616,9 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Public Functions ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) { - struct stm32l4_pulsecount_s *lower = NULL; + struct stm32_pulsecount_s *lower = NULL; _info("TIM%u\n", timer); diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.h b/arch/arm/src/stm32l4/stm32l4_pulsecount.h index 81eddce243644..1e0fd8667a5a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.h +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.h @@ -34,6 +34,6 @@ * Public Function Prototypes ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer); +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 4468b2b603094..dabf608f7b6cf 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -40,7 +40,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pwm.h" -#include "stm32l4.h" +#include "stm32.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. @@ -125,7 +125,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pwm_dumpgpio(p,m) #endif @@ -136,7 +136,7 @@ /* PWM output configuration */ -struct stm32l4_pwm_out_s +struct stm32_pwm_out_s { uint8_t in_use:1; /* Output in use */ uint8_t pol:1; /* Polarity. Default: positive */ @@ -147,33 +147,33 @@ struct stm32l4_pwm_out_s /* PWM channel configuration */ -struct stm32l4_pwmchan_s +struct stm32_pwmchan_s { uint8_t channel:4; /* Timer output channel: {1,..4} */ - uint8_t mode:4; /* PWM channel mode (see stm32l4_pwm_chanmode_e) */ - struct stm32l4_pwm_out_s out1; /* PWM output configuration */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ + struct stm32_pwm_out_s out1; /* PWM output configuration */ #ifdef HAVE_BREAK - struct stm32l4_pwm_break_s brk; /* PWM break configuration */ + struct stm32_pwm_break_s brk; /* PWM break configuration */ #endif #ifdef HAVE_PWM_COMPLEMENTARY - struct stm32l4_pwm_out_s out2; /* PWM complementary output configuration */ + struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ #endif }; /* This structure represents the state of one PWM timer */ -struct stm32l4_pwmtimer_s +struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ #ifdef CONFIG_STM32_PWM_LL_OPS - const struct stm32l4_pwm_ops_s *llops; /* Low-level PWM ops */ + const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif - struct stm32l4_pwmchan_s *channels; /* Channels configuration */ + struct stm32_pwmchan_s *channels; /* Channels configuration */ uint8_t timid:5; /* Timer ID {1,...,17} */ uint8_t chan_num:3; /* Number of configured channels */ uint8_t timtype:3; /* See the TIMTYPE_* definitions */ - uint8_t mode:3; /* Timer mode (see stm32l4_pwm_tim_mode_e) */ + uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ uint8_t lock:2; /* TODO: Lock configuration */ uint8_t t_dts:3; /* Clock division for t_DTS */ uint8_t _res:5; /* Reserved */ @@ -197,10 +197,10 @@ struct stm32l4_pwmtimer_s /* Register access */ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset); -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value); -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_PWM_INFO @@ -274,7 +274,7 @@ static const struct pwm_ops_s g_pwmops = }; #ifdef CONFIG_STM32_PWM_LL_OPS -static const struct stm32l4_pwm_ops_s g_llpwmops = +static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, .soft_break = pwm_soft_break, @@ -298,7 +298,7 @@ static const struct stm32l4_pwm_ops_s g_llpwmops = #ifdef CONFIG_STM32_TIM1_PWM -static struct stm32l4_pwmchan_s g_pwm1channels[] = +static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ @@ -435,7 +435,7 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm1dev = +static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -461,7 +461,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = #ifdef CONFIG_STM32_TIM2_PWM -static struct stm32l4_pwmchan_s g_pwm2channels[] = +static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ @@ -531,7 +531,7 @@ static struct stm32l4_pwmchan_s g_pwm2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm2dev = +static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -558,7 +558,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = #ifdef CONFIG_STM32_TIM3_PWM -static struct stm32l4_pwmchan_s g_pwm3channels[] = +static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ @@ -628,7 +628,7 @@ static struct stm32l4_pwmchan_s g_pwm3channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm3dev = +static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -654,7 +654,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = #ifdef CONFIG_STM32_TIM4_PWM -static struct stm32l4_pwmchan_s g_pwm4channels[] = +static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ @@ -724,7 +724,7 @@ static struct stm32l4_pwmchan_s g_pwm4channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm4dev = +static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -750,7 +750,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = #ifdef CONFIG_STM32_TIM5_PWM -static struct stm32l4_pwmchan_s g_pwm5channels[] = +static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ @@ -818,7 +818,7 @@ static struct stm32l4_pwmchan_s g_pwm5channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm5dev = +static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -844,7 +844,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = #ifdef CONFIG_STM32_TIM8_PWM -static struct stm32l4_pwmchan_s g_pwm8channels[] = +static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ @@ -981,7 +981,7 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm8dev = +static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1007,7 +1007,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = #ifdef CONFIG_STM32_TIM15_PWM -static struct stm32l4_pwmchan_s g_pwm15channels[] = +static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ @@ -1063,7 +1063,7 @@ static struct stm32l4_pwmchan_s g_pwm15channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm15dev = +static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1089,7 +1089,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = #ifdef CONFIG_STM32_TIM16_PWM -static struct stm32l4_pwmchan_s g_pwm16channels[] = +static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ @@ -1129,7 +1129,7 @@ static struct stm32l4_pwmchan_s g_pwm16channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm16dev = +static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1155,7 +1155,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = #ifdef CONFIG_STM32_TIM17_PWM -static struct stm32l4_pwmchan_s g_pwm17channels[] = +static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ @@ -1195,7 +1195,7 @@ static struct stm32l4_pwmchan_s g_pwm17channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm17dev = +static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1221,7 +1221,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = #ifdef CONFIG_STM32_LPTIM1_PWM -static struct stm32l4_pwmchan_s g_pwmlp1channels[] = +static struct stm32_pwmchan_s g_pwmlp1channels[] = { /* LPTIM1 has 1 channel */ @@ -1243,7 +1243,7 @@ static struct stm32l4_pwmchan_s g_pwmlp1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp1dev = +static struct stm32_pwmtimer_s g_pwmlp1dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1277,7 +1277,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #ifdef CONFIG_STM32_LPTIM2_PWM -static struct stm32l4_pwmchan_s g_pwmlp2channels[] = +static struct stm32_pwmchan_s g_pwmlp2channels[] = { /* LPTIM2 has 1 channel */ @@ -1299,7 +1299,7 @@ static struct stm32l4_pwmchan_s g_pwmlp2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp2dev = +static struct stm32_pwmtimer_s g_pwmlp2dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32_PWM_LL_OPS @@ -1350,7 +1350,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = * ****************************************************************************/ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -1370,7 +1370,7 @@ static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && @@ -1412,7 +1412,7 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, * ****************************************************************************/ -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && @@ -1456,7 +1456,7 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, const char *msg) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { @@ -1520,7 +1520,7 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; #ifdef HAVE_LPTIM @@ -1604,7 +1604,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, #ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; switch (index) @@ -1664,7 +1664,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Update ARR register */ @@ -1686,7 +1686,7 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { @@ -1717,7 +1717,7 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -1761,7 +1761,7 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; #ifdef HAVE_LPTIM if (priv->timtype != TIMTYPE_LOWPOWER) @@ -1812,7 +1812,7 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -1911,7 +1911,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Calculated values */ @@ -1985,7 +1985,7 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_timer_configure(struct stm32_pwmtimer_s *priv) { uint16_t cr1 = 0; int ret = OK; @@ -2086,7 +2086,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -2331,7 +2331,7 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, +static int pwm_output_configure(struct stm32_pwmtimer_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -2439,7 +2439,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, * * Input Parameters: * dev - A reference to the lower half PWM driver state structure - * outputs - outputs to set (look at enum stm32l4_chan_e in stm32l4_pwm.h) + * outputs - outputs to set (look at enum stm32_chan_e in stm32l4_pwm.h) * state - Enable/disable operation * ****************************************************************************/ @@ -2447,7 +2447,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; @@ -2499,7 +2499,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t bdtr = 0; int ret = OK; @@ -2541,7 +2541,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); @@ -2564,7 +2564,7 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (state == true) { @@ -2591,7 +2591,7 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) ****************************************************************************/ static uint16_t -pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) +pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) { uint16_t outputs = 0; uint8_t channel = 0; @@ -2641,7 +2641,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) * ****************************************************************************/ -static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv) { uint32_t bdtr = 0; @@ -2721,7 +2721,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) static int pwm_configure(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; uint8_t j = 0; int ret = OK; @@ -2845,7 +2845,7 @@ static int pwm_configure(struct pwm_lowerhalf_s *dev) static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint8_t channel = 0; ub16_t duty = 0; int ret = OK; @@ -2930,7 +2930,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, static int pwm_timer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; int ret = OK; @@ -3038,7 +3038,7 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, static int pwm_lptimer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t cr; int ret = OK; @@ -3110,7 +3110,7 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, +static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) { uint32_t en_bit; @@ -3332,7 +3332,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, static int pwm_setup(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg; int ret; int i; @@ -3361,7 +3361,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out1.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } @@ -3371,7 +3371,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out2.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } #endif @@ -3411,7 +3411,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) static int pwm_shutdown(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg = 0; int i = 0; int ret = OK; @@ -3449,7 +3449,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -3461,7 +3461,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #endif } @@ -3489,7 +3489,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { int ret = OK; - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* if frequency has not changed we just update duty */ @@ -3565,7 +3565,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, static int pwm_stop(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -3712,7 +3712,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -3726,7 +3726,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -3742,9 +3742,9 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("TIM%u\n", timer); @@ -3819,7 +3819,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) } /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -3836,9 +3836,9 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) ****************************************************************************/ #ifdef HAVE_LPTIM -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("LPTIM%u\n", timer); diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index a55d6e48a3be8..5df747e22295c 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -797,7 +797,7 @@ #ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops - * access can be found in stm32l4_pwm_dev_s + * access can be found in stm32_pwm_dev_s */ #define PWM_SETUP(dev) \ @@ -842,7 +842,7 @@ /* Timer mode */ -enum stm32l4_timmode_e +enum stm32_timmode_e { STM32_TIMMODE_COUNTUP = 0, STM32_TIMMODE_COUNTDOWN = 1, @@ -853,7 +853,7 @@ enum stm32l4_timmode_e /* Timer output polarity */ -enum stm32l4_pwm_pol_e +enum stm32_pwm_pol_e { STM32_POL_POS = 0, STM32_POL_NEG = 1, @@ -861,7 +861,7 @@ enum stm32l4_pwm_pol_e /* Timer output IDLE state */ -enum stm32l4_pwm_idle_e +enum stm32_pwm_idle_e { STM32_IDLE_INACTIVE = 0, STM32_IDLE_ACTIVE = 1 @@ -869,7 +869,7 @@ enum stm32l4_pwm_idle_e /* PWM channel mode */ -enum stm32l4_chanmode_e +enum stm32_chanmode_e { STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ @@ -887,7 +887,7 @@ enum stm32l4_chanmode_e /* PWM timer channel */ -enum stm32l4_pwm_chan_e +enum stm32_pwm_chan_e { STM32_PWM_CHAN1 = 1, STM32_PWM_CHAN2 = 2, @@ -899,7 +899,7 @@ enum stm32l4_pwm_chan_e /* PWM timer channel output */ -enum stm32l4_pwm_output_e +enum stm32_pwm_output_e { STM32_PWM_OUT1 = (1 << 0), STM32_PWM_OUT1N = (1 << 1), @@ -928,7 +928,7 @@ enum stm32l4_pwm_output_e * "lower-half" PWM driver structure. */ -struct stm32l4_pwm_dev_s +struct stm32_pwm_dev_s { /* The first field of this state structure must be a pointer to the PWM * callback structure to be consistent with upper-half PWM driver. @@ -938,7 +938,7 @@ struct stm32l4_pwm_dev_s /* Publicly visible portion of the "lower-half" PWM driver structure */ - const struct stm32l4_pwm_ops_s *llops; + const struct stm32_pwm_ops_s *llops; /* Require cast-compatibility with private "lower-half" PWM structure */ }; @@ -946,7 +946,7 @@ struct stm32l4_pwm_dev_s /* Low-level operations for PWM */ struct pwm_lowerhalf_s; -struct stm32l4_pwm_ops_s +struct stm32_pwm_ops_s { /* Update CCR register */ @@ -1030,7 +1030,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -1046,10 +1046,10 @@ extern "C" * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -1065,7 +1065,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index 6ace61ca5aaf2..5bd1d6db51eee 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -39,12 +39,12 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } @@ -70,7 +70,7 @@ static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; @@ -99,7 +99,7 @@ bool stm32l4_pwr_enableclk(bool enable) } /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l4_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l4_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,7 +163,7 @@ bool stm32l4_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; @@ -174,12 +174,12 @@ bool stm32l4_pwr_enableusv(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -222,7 +222,7 @@ bool stm32l4_pwr_enableusv(bool set) ****************************************************************************/ #if !defined(CONFIG_STM32_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set) +bool stm32_pwr_enable_pvme2(bool set) { uint32_t regval; bool was_set; @@ -233,12 +233,12 @@ bool stm32l4_pwr_enable_pvme2(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,26 +248,26 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -278,7 +278,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) * ****************************************************************************/ -bool stm32l4_pwr_get_pvmo2(void) +bool stm32_pwr_get_pvmo2(void) { uint32_t regval; bool was_clk_enabled; @@ -288,23 +288,23 @@ bool stm32l4_pwr_get_pvmo2(void) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return !!(regval & PWR_SR2_PVMO2); } /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -319,7 +319,7 @@ bool stm32l4_pwr_get_pvmo2(void) * ****************************************************************************/ -bool stm32l4_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; @@ -330,12 +330,12 @@ bool stm32l4_pwr_vddio2_valid(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,19 +345,19 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 84c1232980bbd..c10f8a982f3be 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l4_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l4_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -122,11 +122,11 @@ bool stm32l4_pwr_enableusv(bool set); ****************************************************************************/ #if !defined(CONFIG_STM32_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set); +bool stm32_pwr_enable_pvme2(bool set); #endif /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -138,11 +138,11 @@ bool stm32l4_pwr_enable_pvme2(bool set); ****************************************************************************/ #if !defined(CONFIG_STM32_STM32L4X3) -bool stm32l4_pwr_get_pvmo2(void); +bool stm32_pwr_get_pvmo2(void); #endif /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -157,7 +157,7 @@ bool stm32l4_pwr_get_pvmo2(void); ****************************************************************************/ #if !defined(CONFIG_STM32_STM32L4X3) -bool stm32l4_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #endif /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 71580be5e2b90..18ca8468adf45 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" #include "stm32l4_qencoder.h" @@ -163,7 +163,7 @@ #ifdef CONFIG_DEBUG_SENSORS # ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) # else # define qe_dumpgpio(p,m) # endif @@ -177,7 +177,7 @@ /* Constant configuration structure that is retained in FLASH */ -struct stm32l4_qeconfig_s +struct stm32_qeconfig_s { uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ uint8_t irq; /* Timer update IRQ */ @@ -192,7 +192,7 @@ struct stm32l4_qeconfig_s /* Overall, RAM-based state structure */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* The first field of this state structure must be a pointer to the lower- * half callback structure: @@ -202,7 +202,7 @@ struct stm32l4_lowerhalf_s /* STM32 driver-specific fields: */ - const struct stm32l4_qeconfig_s *config; /* static onfiguration */ + const struct stm32_qeconfig_s *config; /* static onfiguration */ bool inuse; /* True: The lower-half driver is in-use */ @@ -218,38 +218,38 @@ struct stm32l4_lowerhalf_s /* Helper functions */ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value); -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value); #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg); #else -# define stm32l4_dumpregs(priv,msg) +# define stm32_dumpregs(priv,msg) #endif -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ -static int stm32l4_setup(struct qe_lowerhalf_s *lower); -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower); -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_setup(struct qe_lowerhalf_s *lower); +static int stm32_shutdown(struct qe_lowerhalf_s *lower); +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32l4_reset(struct qe_lowerhalf_s *lower); -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, +static int stm32_reset(struct qe_lowerhalf_s *lower); +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg); /**************************************************************************** @@ -260,19 +260,19 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, static const struct qe_ops_s g_qecallbacks = { - .setup = stm32l4_setup, - .shutdown = stm32l4_shutdown, - .position = stm32l4_position, + .setup = stm32_setup, + .shutdown = stm32_shutdown, + .position = stm32_position, .setposmax = NULL, /* not supported yet */ - .reset = stm32l4_reset, + .reset = stm32_reset, .setindex = NULL, /* not supported yet */ - .ioctl = stm32l4_ioctl, + .ioctl = stm32_ioctl, }; /* Per-timer state structures */ #ifdef CONFIG_STM32_TIM1_QE -static const struct stm32l4_qeconfig_s g_tim1config = +static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, .irq = STM32_IRQ_TIM1UP, @@ -285,7 +285,7 @@ static const struct stm32l4_qeconfig_s g_tim1config = .ti2cfg = GPIO_TIM1_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim1lower = +static struct stm32_lowerhalf_s g_tim1lower = { .ops = &g_qecallbacks, .config = &g_tim1config, @@ -296,7 +296,7 @@ static struct stm32l4_lowerhalf_s g_tim1lower = #endif #ifdef CONFIG_STM32_TIM2_QE -static const struct stm32l4_qeconfig_s g_tim2config = +static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, .irq = STM32_IRQ_TIM2, @@ -309,7 +309,7 @@ static const struct stm32l4_qeconfig_s g_tim2config = .ti2cfg = GPIO_TIM2_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim2lower = +static struct stm32_lowerhalf_s g_tim2lower = { .ops = &g_qecallbacks, .config = &g_tim2config, @@ -320,7 +320,7 @@ static struct stm32l4_lowerhalf_s g_tim2lower = #endif #ifdef CONFIG_STM32_TIM3_QE -static const struct stm32l4_qeconfig_s g_tim3config = +static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, .irq = STM32_IRQ_TIM3, @@ -333,7 +333,7 @@ static const struct stm32l4_qeconfig_s g_tim3config = .ti2cfg = GPIO_TIM3_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim3lower = +static struct stm32_lowerhalf_s g_tim3lower = { .ops = &g_qecallbacks, .config = &g_tim3config, @@ -344,7 +344,7 @@ static struct stm32l4_lowerhalf_s g_tim3lower = #endif #ifdef CONFIG_STM32_TIM4_QE -static const struct stm32l4_qeconfig_s g_tim4config = +static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, .irq = STM32_IRQ_TIM4, @@ -357,7 +357,7 @@ static const struct stm32l4_qeconfig_s g_tim4config = .ti2cfg = GPIO_TIM4_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim4lower = +static struct stm32_lowerhalf_s g_tim4lower = { .ops = &g_qecallbacks, .config = &g_tim4config, @@ -368,7 +368,7 @@ static struct stm32l4_lowerhalf_s g_tim4lower = #endif #ifdef CONFIG_STM32_TIM5_QE -static const struct stm32l4_qeconfig_s g_tim5config = +static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, .irq = STM32_IRQ_TIM5, @@ -381,7 +381,7 @@ static const struct stm32l4_qeconfig_s g_tim5config = .ti2cfg = GPIO_TIM5_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim5lower = +static struct stm32_lowerhalf_s g_tim5lower = { .ops = &g_qecallbacks, .config = &g_tim5config, @@ -392,7 +392,7 @@ static struct stm32l4_lowerhalf_s g_tim5lower = #endif #ifdef CONFIG_STM32_TIM8_QE -static const struct stm32l4_qeconfig_s g_tim8config = +static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, .irq = STM32_IRQ_TIM8UP, @@ -405,7 +405,7 @@ static const struct stm32l4_qeconfig_s g_tim8config = .ti2cfg = GPIO_TIM8_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim8lower = +static struct stm32_lowerhalf_s g_tim8lower = { .ops = &g_qecallbacks, .config = &g_tim8config, @@ -420,7 +420,7 @@ static struct stm32l4_lowerhalf_s g_tim8lower = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Read the value of a 16-bit timer register. @@ -434,14 +434,14 @@ static struct stm32l4_lowerhalf_s g_tim8lower = * ****************************************************************************/ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 16-bit timer register. @@ -455,7 +455,7 @@ static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value) { @@ -463,7 +463,7 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Read the value of a 32-bit timer register. @@ -480,14 +480,14 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 32-bit timer register. @@ -504,7 +504,7 @@ static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value) { @@ -512,7 +512,7 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_dumpregs + * Name: stm32_dumpregs * * Description: * Dump all timer registers. @@ -526,61 +526,61 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, ****************************************************************************/ #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg) { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); + stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); + stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif /**************************************************************************** - * Name: stm32l4_tim2lower + * Name: stm32_tim2lower * * Description: * Map a timer number to a device structure * ****************************************************************************/ -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { @@ -614,7 +614,7 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) } /**************************************************************************** - * Name: stm32l4_interrupt + * Name: stm32_interrupt * * Description: * Common timer interrupt handling. NOTE: Only 16-bit timers require timer @@ -623,10 +623,10 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) ****************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg) +static int stm32_interrupt(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)arg; uint16_t regval; DEBUGASSERT(priv != NULL); @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -661,7 +661,7 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_setup + * Name: stm32_setup * * Description: * This method is called when the driver is opened. The lower half driver @@ -670,10 +670,10 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_setup(struct qe_lowerhalf_s *lower) +static int stm32_setup(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint16_t dier; uint32_t smcr; uint32_t ccmr1; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -736,7 +736,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * on the encoder resolution. */ - stm32l4_putreg16(priv, + stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); #if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) @@ -744,7 +744,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); + stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,30 +752,30 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ - stm32l4_configgpio(priv->config->ti1cfg); - stm32l4_configgpio(priv->config->ti2cfg); + stm32_configgpio(priv->config->ti1cfg); + stm32_configgpio(priv->config->ti2cfg); /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET); + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -790,28 +790,28 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -853,10 +853,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, stm32l4_interrupt, priv); + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); if (ret < 0) { - stm32l4_shutdown(lower); + stm32_shutdown(lower); return ret; } @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,30 +886,30 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - stm32l4_dumpregs(priv, "After setup"); + stm32_dumpregs(priv, "After setup"); return OK; } /**************************************************************************** - * Name: stm32l4_shutdown + * Name: stm32_shutdown * * Description: * This method is called when the driver is closed. The lower half driver @@ -918,10 +918,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) +static int stm32_shutdown(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; uint32_t regaddr; uint32_t regval; @@ -943,8 +943,8 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ @@ -992,7 +992,7 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) } /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32l4_start() can be called. + * into a state where stm32_start() can be called. */ regval = getreg32(regaddr); @@ -1005,37 +1005,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", regaddr, resetbit); - stm32l4_dumpregs(priv, "After stop"); + stm32_dumpregs(priv, "After stop"); /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); return OK; } /**************************************************************************** - * Name: stm32l4_position + * Name: stm32_position * * Description: * Return the current position measurement. * ****************************************************************************/ -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; int32_t position; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); + count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,23 +1062,23 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset * * Description: * Reset the position measurement to zero. * ****************************************************************************/ -static int stm32l4_reset(struct qe_lowerhalf_s *lower) +static int stm32_reset(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,20 +1099,20 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } /**************************************************************************** - * Name: stm32l4_ioctl + * Name: stm32_ioctl * * Description: * Lower-half logic may support platform-specific ioctl commands * ****************************************************************************/ -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg) { /* No ioctl commands supported */ @@ -1127,7 +1127,7 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -1143,16 +1143,16 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim) +int stm32_qeinitialize(const char *devpath, int tim) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; /* Find the pre-allocated timer state structure corresponding to this * timer */ - priv = stm32l4_tim2lower(tim); + priv = stm32_tim2lower(tim); if (!priv) { snerr("ERROR: TIM%d support not configured\n", tim); @@ -1178,7 +1178,7 @@ int stm32l4_qeinitialize(const char *devpath, int tim) /* Make sure that the timer is in the shutdown state */ - stm32l4_shutdown((struct qe_lowerhalf_s *)priv); + stm32_shutdown((struct qe_lowerhalf_s *)priv); /* The driver is now in-use */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h index 4f7d006c436ad..1197bdfc67acc 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -95,7 +95,7 @@ * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim); +int stm32_qeinitialize(const char *devpath, int tim); #endif /* CONFIG_SENSORS_QENCODER */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 990eeb37ad345..5c5f29eeb08d3 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -149,7 +149,7 @@ * designed to support multiple QSPI peripherals. */ -struct stm32l4_qspidev_s +struct stm32_qspidev_s { struct qspi_dev_s qspi; /* Externally visible part of the QSPI interface */ uint32_t base; /* QSPI controller register base address */ @@ -180,7 +180,7 @@ struct stm32l4_qspidev_s /* Debug stuff */ #ifdef CONFIG_STM32_QSPI_DMADEBUG - struct stm32l4_dmaregs_s dmaregs[DMA_NSAMPLES]; + struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif #ifdef CONFIG_STM32_QSPI_REGDEBUG @@ -234,19 +234,19 @@ struct qspi_xctnspec_s /* Helpers */ #ifdef CONFIG_STM32_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else # define qspi_checkreg(priv,wr,value,address) (false) #endif -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset); -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset); #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg); #else # define qspi_dumpregs(priv,msg) @@ -270,9 +270,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg); #ifdef CONFIG_STM32_QSPI_DMA # ifdef CONFIG_STM32_QSPI_DMADEBUG -# define qspi_dma_sample(s,i) stm32l4_dmasample((s)->dmach, &(s)->dmaregs[i]) -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv); -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv); +# define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # else # define qspi_dma_sample(s,i) # define qspi_dma_sampleinit(s) @@ -301,7 +301,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer); /* Initialization */ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv); +static int qspi_hw_initialize(struct stm32_qspidev_s *priv); /**************************************************************************** * Private Data @@ -326,7 +326,7 @@ static const struct qspi_ops_s g_qspi0ops = /* This is the overall state of the QSPI0 controller */ -static struct stm32l4_qspidev_s g_qspi0dev = +static struct stm32_qspidev_s g_qspi0dev = { .qspi = { @@ -367,7 +367,7 @@ static struct stm32l4_qspidev_s g_qspi0dev = ****************************************************************************/ #ifdef CONFIG_STM32_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { if (wr == priv->wrlast && /* Same kind of access? */ @@ -412,7 +412,7 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, * ****************************************************************************/ -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset) { uint32_t address = priv->base + offset; @@ -436,7 +436,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset) { uint32_t address = priv->base + offset; @@ -467,7 +467,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, ****************************************************************************/ #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg) { uint32_t regval; spiinfo("%s:\n", msg); @@ -596,16 +596,16 @@ static void qspi_dumpgpioconfig(const char *msg) * ****************************************************************************/ -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv) { /* Put contents of register samples into a known state */ memset(priv->dmaregs, 0xff, - DMA_NSAMPLES * sizeof(struct stm32l4_dmaregs_s)); + DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); /* Then get the initial samples */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); } /**************************************************************************** @@ -622,27 +622,27 @@ static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv) { /* Sample the final registers */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); /* Then dump the sampled DMA registers */ /* Initial register values */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], "Initial Registers"); /* Register values after DMA setup */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], "After DMA Setup"); /* Register values after DMA start */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], "After DMA Start"); /* Register values at the time of the TX and RX DMA callbacks @@ -655,16 +655,16 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) if (priv->result == -ETIMEDOUT) { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], "At DMA timeout"); } else { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], "At DMA callback"); } - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], "At End-of-Transfer"); } #endif @@ -944,7 +944,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, * ****************************************************************************/ -static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, +static void qspi_waitstatusflags(struct stm32_qspidev_s *priv, uint32_t mask, int polarity) { uint32_t regval; @@ -975,7 +975,7 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static void qspi_abort(struct stm32l4_qspidev_s *priv) +static void qspi_abort(struct stm32_qspidev_s *priv) { uint32_t regval; @@ -1000,7 +1000,7 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, +static void qspi_ccrconfig(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn, uint8_t fctn) { @@ -1290,7 +1290,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) static void qspi_dma_timeout(wdparm_t arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Sample DMA registers at the time of the timeout */ @@ -1326,7 +1326,7 @@ static void qspi_dma_timeout(wdparm_t arg) static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Cancel the watchdog timeout */ @@ -1374,7 +1374,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, +static inline uintptr_t qspi_regaddr(struct stm32_qspidev_s *priv, unsigned int offset) { return priv->base + offset; @@ -1396,7 +1396,7 @@ static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, +static int qspi_memory_dma(struct stm32_qspidev_s *priv, struct qspi_meminfo_s *meminfo, struct qspi_xctnspec_s *xctn) { @@ -1425,7 +1425,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, DMA_CCR_MINC); } - stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, + stm32_dmasetup(priv->dmach, qspi_regaddr(priv, STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); @@ -1446,7 +1446,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dmach, qspi_dma_callback, priv, false); + stm32_dmastart(priv->dmach, qspi_dma_callback, priv, false); qspi_dma_sample(priv, DMA_AFTER_START); @@ -1510,7 +1510,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * on an error condition). */ - stm32l4_dmastop(priv->dmach); + stm32_dmastop(priv->dmach); regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; @@ -1543,7 +1543,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_receive_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; @@ -1621,7 +1621,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_transmit_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; @@ -1692,7 +1692,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, static int qspi_lock(struct qspi_dev_s *dev, bool lock) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; int ret; spiinfo("lock=%d\n", lock); @@ -1725,7 +1725,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock) static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t actual; uint32_t prescaler; uint32_t regval; @@ -1822,7 +1822,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; if (priv->memmap) @@ -1924,7 +1924,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits) static int qspi_command(struct qspi_dev_s *dev, struct qspi_cmdinfo_s *cmdinfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -2106,7 +2106,7 @@ static int qspi_command(struct qspi_dev_s *dev, static int qspi_memory(struct qspi_dev_s *dev, struct qspi_meminfo_s *meminfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -2346,7 +2346,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer) * ****************************************************************************/ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) +static int qspi_hw_initialize(struct stm32_qspidev_s *priv) { uint32_t regval; @@ -2429,7 +2429,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2442,9 +2442,9 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32l4_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { - struct stm32l4_qspidev_s *priv; + struct stm32_qspidev_s *priv; uint32_t regval; int ret; @@ -2482,12 +2482,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Configure multiplexed pins as connected on the board. */ - stm32l4_configgpio(GPIO_QSPI_CS); - stm32l4_configgpio(GPIO_QSPI_IO0); - stm32l4_configgpio(GPIO_QSPI_IO1); - stm32l4_configgpio(GPIO_QSPI_IO2); - stm32l4_configgpio(GPIO_QSPI_IO3); - stm32l4_configgpio(GPIO_QSPI_SCK); + stm32_configgpio(GPIO_QSPI_CS); + stm32_configgpio(GPIO_QSPI_IO0); + stm32_configgpio(GPIO_QSPI_IO1); + stm32_configgpio(GPIO_QSPI_IO2); + stm32_configgpio(GPIO_QSPI_IO3); + stm32_configgpio(GPIO_QSPI_SCK); } else { @@ -2506,7 +2506,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) if (priv->candma) { - priv->dmach = stm32l4_dmachannel(DMACHAN_QUADSPI); + priv->dmach = stm32_dmachannel(DMACHAN_QUADSPI); if (!priv->dmach) { spierr("ERROR: Failed to allocate the DMA channel\n"); @@ -2557,7 +2557,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) #ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { - stm32l4_dmafree(priv->dmach); + stm32_dmafree(priv->dmach); priv->dmach = NULL; } #endif @@ -2566,7 +2566,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2580,11 +2580,11 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; struct qspi_xctnspec_s xctn; @@ -2658,7 +2658,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2671,9 +2671,9 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; qspi_lock(dev, true); diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index 7c3b5a8fa2d36..d81c8b573709f 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -68,7 +68,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -82,10 +82,10 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32l4_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -100,12 +100,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf); * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -118,7 +118,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 190d532fdc46c..26830f433d553 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -37,7 +37,7 @@ #include "chip.h" #include "stm32l4_rcc.h" #include "stm32l4_flash.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_waste.h" #include "stm32l4_rtc.h" @@ -105,7 +105,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -122,7 +122,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -143,7 +143,7 @@ static inline void rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -155,7 +155,7 @@ static inline void rcc_resetbkp(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -165,7 +165,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -175,7 +175,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l4_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -189,7 +189,7 @@ void stm32l4_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -197,7 +197,7 @@ void stm32l4_clockconfig(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -207,7 +207,7 @@ void stm32l4_clockconfig(void) } /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -217,12 +217,12 @@ void stm32l4_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -233,13 +233,13 @@ void stm32l4_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -247,7 +247,7 @@ void stm32l4_clockenable(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 2850bfc0e78ce..624a25ec93391 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -64,7 +64,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. @@ -82,7 +82,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32l4_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -99,7 +99,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -109,7 +109,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -119,10 +119,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l4_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l4_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L4 board may replace the "standard" board clock configuration @@ -131,11 +131,11 @@ void stm32l4_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32l4_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -144,12 +144,12 @@ void stm32l4_board_clockconfig(void); * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -160,11 +160,11 @@ void stm32l4_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -177,27 +177,27 @@ void stm32l4_clockenable(void); * ****************************************************************************/ -void stm32l4_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 9a81038f86e59..9c3e70831ae7a 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -48,11 +48,11 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32l4_rng_initialize(void); -static int stm32l4_rnginterrupt(int irq, void *context, void *arg); -static void stm32l4_rngenable(void); -static void stm32l4_rngdisable(void); -static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t); +static int stm32_rng_initialize(void); +static int stm32_rnginterrupt(int irq, void *context, void *arg); +static void stm32_rngenable(void); +static void stm32_rngdisable(void); +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t); /**************************************************************************** * Private Types @@ -82,18 +82,18 @@ static const struct file_operations g_rngops = { NULL, /* open */ NULL, /* close */ - stm32l4_rngread, /* read */ + stm32_rngread, /* read */ }; /**************************************************************************** * Private functions ****************************************************************************/ -static int stm32l4_rng_initialize(void) +static int stm32_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -105,7 +105,7 @@ static int stm32l4_rng_initialize(void) return OK; } -static void stm32l4_rngenable(void) +static void stm32_rngenable(void) { uint32_t regval; @@ -121,7 +121,7 @@ static void stm32l4_rngenable(void) up_enable_irq(STM32_IRQ_RNG); } -static void stm32l4_rngdisable(void) +static void stm32_rngdisable(void) { uint32_t regval; @@ -133,7 +133,7 @@ static void stm32l4_rngdisable(void) putreg32(regval, STM32_RNG_CR); } -static int stm32l4_rnginterrupt(int irq, void *context, void *arg) +static int stm32_rnginterrupt(int irq, void *context, void *arg) { uint32_t rngsr; uint32_t data; @@ -216,7 +216,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) { /* Buffer filled, stop further interrupts. */ - stm32l4_rngdisable(); + stm32_rngdisable(); nxsem_post(&g_rngdev.rd_readsem); } @@ -224,10 +224,10 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_rngread + * Name: stm32_rngread ****************************************************************************/ -static ssize_t stm32l4_rngread(struct file *filep, +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen) { int ret; @@ -251,7 +251,7 @@ static ssize_t stm32l4_rngread(struct file *filep, /* Enable RNG with interrupts */ - stm32l4_rngenable(); + stm32_rngenable(); /* Wait until the buffer is filled */ @@ -285,7 +285,7 @@ static ssize_t stm32l4_rngread(struct file *filep, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - stm32l4_rng_initialize(); + stm32_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -308,7 +308,7 @@ void devrandom_register(void) void devurandom_register(void) { #ifndef CONFIG_DEV_RANDOM - stm32l4_rng_initialize(); + stm32_rng_initialize(); #endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 7f9c1a687584d..afd88e708aa8a 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -208,7 +208,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -246,7 +246,7 @@ static inline void rtc_wprlock(void) /* Disable write access to the backup domain. */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -445,7 +445,7 @@ static void rtc_resume(void) } /**************************************************************************** - * Name: stm32l4_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -460,7 +460,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -474,7 +474,7 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ @@ -540,7 +540,7 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -746,14 +746,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32l4_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -768,7 +768,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -809,7 +809,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -825,7 +825,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -860,14 +860,14 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); #if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, @@ -902,7 +902,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -978,7 +978,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -988,7 +988,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -998,7 +998,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1018,7 +1018,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS @@ -1153,7 +1153,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1187,12 +1187,12 @@ int up_rtc_getdatetime(struct tm *tp) # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32l4_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1270,9 +1270,9 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1283,7 +1283,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1293,7 +1293,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1322,11 +1322,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32l4_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1340,7 +1340,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1415,7 +1415,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1429,7 +1429,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1515,7 +1515,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) #endif /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1529,7 +1529,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1542,7 +1542,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMA: { alarmreg = STM32_RTC_ALRMAR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1551,7 +1551,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMB: { alarmreg = STM32_RTC_ALRMBR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1567,7 +1567,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1581,18 +1581,18 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_rtc_wakeup_handler(int irq, void *context, +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; putreg32(regval, STM32_RTC_ISR); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1616,7 +1616,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32l4_exti_wakeup(true, false, true, stm32l4_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1644,7 +1644,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) #endif /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1659,7 +1659,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1788,7 +1788,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1801,7 +1801,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index d1ae9b632da95..92e214791ae26 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -118,7 +118,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -133,10 +133,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -157,12 +157,12 @@ bool stm32l4_rtc_is_initialized(void); ****************************************************************************/ #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -179,11 +179,11 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32l4_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -193,11 +193,11 @@ int stm32l4_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -210,10 +210,10 @@ bool stm32l4_rtc_havesettime(void); * ****************************************************************************/ -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -226,10 +226,10 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -242,13 +242,13 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -262,11 +262,11 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -278,11 +278,11 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32l4_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32L4. General usage: @@ -291,7 +291,7 @@ int stm32l4_rtc_cancelperiodic(void); * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -305,7 +305,7 @@ int stm32l4_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index 27e3aaabfc0ec..0d87286eb681e 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -52,7 +52,7 @@ ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32l4_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument to accompany callback */ @@ -64,7 +64,7 @@ struct stm32l4_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,30 +97,30 @@ struct stm32l4_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -131,24 +131,24 @@ stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32l4_rdtime, - .settime = stm32l4_settime, - .havesettime = stm32l4_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32l4_setalarm, - .setrelative = stm32l4_setrelative, - .cancelalarm = stm32l4_cancelalarm, - .rdalarm = stm32l4_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32l4_setperiodic, - .cancelperiodic = stm32l4_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32L4 RTC device state */ -static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -159,7 +159,7 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -174,17 +174,17 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32l4_lowerhalf_s *lower; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32l4_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -207,7 +207,7 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32l4_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -222,13 +222,13 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -247,7 +247,7 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -262,13 +262,13 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -280,14 +280,14 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32l4_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32l4_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -300,13 +300,13 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32l4_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32l4_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -323,11 +323,11 @@ static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -335,7 +335,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -356,13 +356,13 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32l4_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32l4_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -376,7 +376,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -394,7 +394,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -440,7 +440,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32l4_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -451,7 +451,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -468,16 +468,16 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -498,7 +498,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, /* Then cancel the alarm */ - ret = stm32l4_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -507,7 +507,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -523,7 +523,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -544,7 +544,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32l4_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -554,7 +554,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -570,14 +570,14 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32l4_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -595,7 +595,7 @@ static int stm32l4_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -614,14 +614,14 @@ static int stm32l4_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -630,8 +630,8 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32l4_rtc_setperiodic(&alarminfo->period, - stm32l4_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -639,7 +639,7 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -655,13 +655,13 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -671,7 +671,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32l4_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -683,7 +683,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -692,7 +692,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -704,7 +704,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index c8123ca729af8..775cb3a429c64 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -142,7 +142,7 @@ struct sai_buffer_s /* The state of the one SAI peripheral */ -struct stm32l4_sai_s +struct stm32_sai_s { struct i2s_dev_s dev; /* Externally visible I2S interface */ uintptr_t base; /* SAI block register base address */ @@ -176,7 +176,7 @@ struct stm32l4_sai_s ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg); #else # define sai_dump_regs(s,m) #endif @@ -184,15 +184,15 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); /* Buffer container helpers */ static struct sai_buffer_s * - sai_buf_allocate(struct stm32l4_sai_s *priv); -static void sai_buf_free(struct stm32l4_sai_s *priv, + sai_buf_allocate(struct stm32_sai_s *priv); +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer); -static void sai_buf_initialize(struct stm32l4_sai_s *priv); +static void sai_buf_initialize(struct stm32_sai_s *priv); /* DMA support */ #ifdef CONFIG_STM32_SAI_DMA -static void sai_schedule(struct stm32l4_sai_s *priv, int result); +static void sai_schedule(struct stm32_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -230,7 +230,7 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ #ifdef CONFIG_STM32_SAI1_A -static struct stm32l4_sai_s g_sai1a_priv = +static struct stm32_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_A_BASE, @@ -251,7 +251,7 @@ static struct stm32l4_sai_s g_sai1a_priv = #endif #ifdef CONFIG_STM32_SAI1_B -static struct stm32l4_sai_s g_sai1b_priv = +static struct stm32_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_B_BASE, @@ -274,7 +274,7 @@ static struct stm32l4_sai_s g_sai1b_priv = /* SAI2 state */ #ifdef CONFIG_STM32_SAI2_A -static struct stm32l4_sai_s g_sai2a_priv = +static struct stm32_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_A_BASE, @@ -295,7 +295,7 @@ static struct stm32l4_sai_s g_sai2a_priv = #endif #ifdef CONFIG_STM32_SAI2_B -static struct stm32l4_sai_s g_sai2b_priv = +static struct stm32_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_B_BASE, @@ -333,7 +333,7 @@ static struct stm32l4_sai_s g_sai2b_priv = * ****************************************************************************/ -static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) +static inline uint32_t sai_getbitrate(struct stm32_sai_s *priv) { /* Calculate the bitrate in Hz */ @@ -355,7 +355,7 @@ static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) +static inline uint32_t sai_getreg(struct stm32_sai_s *priv, uint8_t offset) { return getreg32(priv->base + offset); } @@ -376,7 +376,7 @@ static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) * ****************************************************************************/ -static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, +static inline void sai_putreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->base + offset); @@ -399,7 +399,7 @@ static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, * ****************************************************************************/ -static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, +static void sai_modifyreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -426,7 +426,7 @@ static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg) { if (msg) i2sinfo("%s\n", msg); @@ -460,7 +460,7 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) * ****************************************************************************/ -static void sai_mckdivider(struct stm32l4_sai_s *priv) +static void sai_mckdivider(struct stm32_sai_s *priv) { uint32_t mckdiv; @@ -497,13 +497,13 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) static void sai_timeout(wdparm_t arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv != NULL); #ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); #endif /* Then schedule completion of the transfer to occur on the worker @@ -531,7 +531,7 @@ static void sai_timeout(wdparm_t arg) ****************************************************************************/ #ifdef CONFIG_STM32_SAI_DMA -static int sai_dma_setup(struct stm32l4_sai_s *priv) +static int sai_dma_setup(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; struct ap_buffer_s *apb; @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -630,7 +630,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Start the DMA, saving the container as the current active transfer */ - stm32l4_dmastart(priv->dma, sai_dma_callback, priv, false); + stm32_dmastart(priv->dma, sai_dma_callback, priv, false); /* Enable the transmitter */ @@ -675,7 +675,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) static void sai_worker(void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -759,7 +759,7 @@ static void sai_worker(void *arg) * ****************************************************************************/ -static void sai_schedule(struct stm32l4_sai_s *priv, int result) +static void sai_schedule(struct stm32_sai_s *priv, int result) { struct sai_buffer_s *bfcontainer; int ret; @@ -817,7 +817,7 @@ static void sai_schedule(struct stm32l4_sai_s *priv, int result) #ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv); /* Cancel the watchdog timeout */ @@ -847,7 +847,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; DEBUGASSERT(priv && rate > 0); @@ -877,7 +877,7 @@ static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; uint32_t setbits; DEBUGASSERT(priv && bits >= 8); @@ -947,7 +947,7 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -1052,7 +1052,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -1144,7 +1144,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * ****************************************************************************/ -static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) +static struct sai_buffer_s *sai_buf_allocate(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -1191,7 +1191,7 @@ static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_buf_free(struct stm32l4_sai_s *priv, +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer) { irqstate_t flags; @@ -1227,7 +1227,7 @@ static void sai_buf_free(struct stm32l4_sai_s *priv, * ****************************************************************************/ -static void sai_buf_initialize(struct stm32l4_sai_s *priv) +static void sai_buf_initialize(struct stm32_sai_s *priv) { int i; @@ -1252,7 +1252,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_portinitialize(struct stm32l4_sai_s *priv) +static void sai_portinitialize(struct stm32_sai_s *priv) { sai_dump_regs(priv, "Before initialization"); @@ -1272,7 +1272,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) #ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ - priv->dma = stm32l4_dmachannel(priv->dma_ch); + priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); @@ -1302,7 +1302,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -1315,9 +1315,9 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf) +struct i2s_dev_s *stm32_sai_initialize(int intf) { - struct stm32l4_sai_s *priv; + struct stm32_sai_s *priv; irqstate_t flags; flags = enter_critical_section(); @@ -1330,11 +1330,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI1 Block A Selected\n"); priv = &g_sai1a_priv; - stm32l4_configgpio(GPIO_SAI1_SD_A); + stm32_configgpio(GPIO_SAI1_SD_A); # ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI1_FS_A); - stm32l4_configgpio(GPIO_SAI1_SCK_A); - stm32l4_configgpio(GPIO_SAI1_MCLK_A); + stm32_configgpio(GPIO_SAI1_FS_A); + stm32_configgpio(GPIO_SAI1_SCK_A); + stm32_configgpio(GPIO_SAI1_MCLK_A); # endif break; } @@ -1346,11 +1346,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI1 Block B Selected\n"); priv = &g_sai1b_priv; - stm32l4_configgpio(GPIO_SAI1_SD_B); + stm32_configgpio(GPIO_SAI1_SD_B); # ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI1_FS_B); - stm32l4_configgpio(GPIO_SAI1_SCK_B); - stm32l4_configgpio(GPIO_SAI1_MCLK_B); + stm32_configgpio(GPIO_SAI1_FS_B); + stm32_configgpio(GPIO_SAI1_SCK_B); + stm32_configgpio(GPIO_SAI1_MCLK_B); # endif break; } @@ -1362,11 +1362,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI2 Block A Selected\n"); priv = &g_sai2a_priv; - stm32l4_configgpio(GPIO_SAI2_SD_A); + stm32_configgpio(GPIO_SAI2_SD_A); # ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI2_FS_A); - stm32l4_configgpio(GPIO_SAI2_SCK_A); - stm32l4_configgpio(GPIO_SAI2_MCLK_A); + stm32_configgpio(GPIO_SAI2_FS_A); + stm32_configgpio(GPIO_SAI2_SCK_A); + stm32_configgpio(GPIO_SAI2_MCLK_A); # endif break; } @@ -1378,11 +1378,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI2 Block B Selected\n"); priv = &g_sai2b_priv; - stm32l4_configgpio(GPIO_SAI2_SD_B); + stm32_configgpio(GPIO_SAI2_SD_B); # ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI2_FS_B); - stm32l4_configgpio(GPIO_SAI2_SCK_B); - stm32l4_configgpio(GPIO_SAI2_MCLK_B); + stm32_configgpio(GPIO_SAI2_FS_B); + stm32_configgpio(GPIO_SAI2_SCK_B); + stm32_configgpio(GPIO_SAI2_MCLK_B); # endif break; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.h b/arch/arm/src/stm32l4/stm32l4_sai.h index 08f8863b80274..8de7dcc14f597 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/stm32l4_sai.h @@ -71,7 +71,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -84,7 +84,7 @@ extern "C" * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf); +struct i2s_dev_s *stm32_sai_initialize(int intf); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 85e2e8ea1fc9d..bea2a35c088d8 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -1373,7 +1373,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * terminates on an error condition). */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -2127,7 +2127,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) * terminates on an error condition. */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -2751,7 +2751,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* DMA must be possible to the buffer */ - if (!stm32l4_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri)) { return -EFAULT; @@ -2818,14 +2818,14 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN); - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri); /* Start the DMA */ stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; @@ -2883,7 +2883,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Configure the TX DMA */ - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_TXDMA32_CONFIG | priv->dmapri); @@ -2893,7 +2893,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Start the DMA */ - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); /* Enable TX interrupts */ @@ -3056,14 +3056,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) * utility in the scope of the board support package. */ #ifndef CONFIG_SDIO_MUXBUS - stm32l4_configgpio(GPIO_SDMMC1_D0); + stm32_configgpio(GPIO_SDMMC1_D0); #ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY - stm32l4_configgpio(GPIO_SDMMC1_D1); - stm32l4_configgpio(GPIO_SDMMC1_D2); - stm32l4_configgpio(GPIO_SDMMC1_D3); + stm32_configgpio(GPIO_SDMMC1_D1); + stm32_configgpio(GPIO_SDMMC1_D2); + stm32_configgpio(GPIO_SDMMC1_D3); #endif - stm32l4_configgpio(GPIO_SDMMC1_CK); - stm32l4_configgpio(GPIO_SDMMC1_CMD); + stm32_configgpio(GPIO_SDMMC1_CK); + stm32_configgpio(GPIO_SDMMC1_CMD); #endif } else @@ -3113,7 +3113,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) #ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ - priv->dma = stm32l4_dmachannel(dmachan); + priv->dma = stm32_dmachannel(dmachan); DEBUGASSERT(priv->dma); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 6b4b700cb3ec8..1e3180a641b52 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -209,7 +209,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -323,9 +323,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev); static void stm32l4serial_dmashutdown(struct uart_dev_s *dev); static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv); +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv); +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev); @@ -442,7 +442,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 LPUART1 port. */ #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static struct stm32l4_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -504,7 +504,7 @@ static struct stm32l4_serial_s g_lpuart1priv = /* This describes the state of the STM32 USART1 port. */ #ifdef CONFIG_STM32_USART1_SERIALDRIVER -static struct stm32l4_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -566,7 +566,7 @@ static struct stm32l4_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32_USART2_SERIALDRIVER -static struct stm32l4_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -628,7 +628,7 @@ static struct stm32l4_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ #ifdef CONFIG_STM32_USART3_SERIALDRIVER -static struct stm32l4_serial_s g_usart3priv = +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -690,7 +690,7 @@ static struct stm32l4_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ #ifdef CONFIG_STM32_UART4_SERIALDRIVER -static struct stm32l4_serial_s g_uart4priv = +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -752,7 +752,7 @@ static struct stm32l4_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ #ifdef CONFIG_STM32_UART5_SERIALDRIVER -static struct stm32l4_serial_s g_uart5priv = +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -813,7 +813,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l4_serial_s * +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER @@ -858,7 +858,7 @@ static struct ****************************************************************************/ static inline -uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) +uint32_t stm32l4serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -867,7 +867,7 @@ uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) * Name: stm32l4serial_putreg ****************************************************************************/ -static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, +static inline void stm32l4serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -878,7 +878,7 @@ static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, ****************************************************************************/ static inline -void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, +void stm32l4serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -906,7 +906,7 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * Name: up_restoreusartint ****************************************************************************/ -static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -922,7 +922,7 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, * Name: stm32l4serial_disableusartint ****************************************************************************/ -static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -988,11 +988,11 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) +static int stm32l4serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l4_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1007,7 +1007,7 @@ static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) +static void stm32l4serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -1077,7 +1077,7 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) +static void stm32l4serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -1115,8 +1115,8 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l4serial_setformat(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ @@ -1220,7 +1220,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -1239,7 +1239,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l4_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1268,7 +1268,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1309,7 +1309,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l4_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1358,7 +1358,7 @@ static void stm32l4serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1384,8 +1384,8 @@ static void stm32l4serial_pm_setsuspend(bool suspend) static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1456,14 +1456,14 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l4serial_setup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l4_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1474,18 +1474,18 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1499,15 +1499,15 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l4_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_configgpio(priv->rs485_dir_gpio); - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1582,8 +1582,8 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1600,14 +1600,14 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l4_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1618,7 +1618,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1645,7 +1645,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -1656,7 +1656,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -1675,8 +1675,8 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) static void stm32l4serial_shutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1707,32 +1707,32 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l4_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1749,8 +1749,8 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1758,11 +1758,11 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l4_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1785,8 +1785,8 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) static int stm32l4serial_attach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1816,8 +1816,8 @@ static int stm32l4serial_attach(struct uart_dev_s *dev) static void stm32l4serial_detach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1836,7 +1836,7 @@ static void stm32l4serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1901,7 +1901,7 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l4serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1967,8 +1967,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1977,15 +1977,15 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l4_serial_s *user = - (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *user = + (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32l4_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -2031,7 +2031,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -2042,7 +2042,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2268,7 +2268,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l4_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2285,7 +2285,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2348,8 +2348,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, static int stm32l4serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2378,8 +2378,8 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2441,8 +2441,8 @@ static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2476,8 +2476,8 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32_FLOWCONTROL_BROKEN) @@ -2485,7 +2485,7 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l4_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2560,8 +2560,8 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l4serial_dmanextrx(priv) != priv->rxdmanext) @@ -2599,14 +2599,14 @@ static int stm32l4serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2617,7 +2617,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2638,7 +2638,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -2649,7 +2649,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -2670,7 +2670,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2721,8 +2721,8 @@ static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2756,8 +2756,8 @@ static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_RXDMA static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2777,13 +2777,13 @@ static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l4serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2800,8 +2800,8 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2873,8 +2873,8 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l4serial_txready(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2892,7 +2892,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l4serial_dmarxavailable(&priv->dev)) { @@ -3051,7 +3051,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l4_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -3060,7 +3060,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3224,7 +3224,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3235,7 +3235,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3298,7 +3298,7 @@ void stm32l4_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l4_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l4serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index 347ad4f26aff6..8eb04f9ef9e30 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l4_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,7 +73,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_dma.h" #include "stm32l4_spi.h" @@ -132,7 +132,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -173,37 +173,37 @@ struct stm32l4_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv); -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv); -static int spi_dmatxwait(struct stm32l4_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -251,16 +251,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l4_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -309,16 +309,16 @@ static struct stm32l4_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l4_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,13 +331,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -365,16 +365,16 @@ static struct stm32l4_spidev_s g_spi2dev = static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l4_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,13 +387,13 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { @@ -436,7 +436,7 @@ static struct stm32l4_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l4_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,7 +518,7 @@ static inline void spi_putreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -543,7 +543,7 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -569,7 +569,7 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -596,7 +596,7 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l4_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -636,7 +636,7 @@ static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -669,7 +669,7 @@ static int spi_dmarxwait(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmatxwait(struct stm32l4_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -702,7 +702,7 @@ static int spi_dmatxwait(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -717,7 +717,7 @@ static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -734,7 +734,7 @@ static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -754,7 +754,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -772,7 +772,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -823,7 +823,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -875,10 +875,10 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l4_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -891,10 +891,10 @@ static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l4_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -914,7 +914,7 @@ static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -948,7 +948,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -981,7 +981,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1089,7 +1089,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1157,7 +1157,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1290,7 +1290,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1364,7 +1364,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1465,14 +1465,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; #ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && - !stm32l4_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l4_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1662,8 +1662,8 @@ static void spi_recvblock(struct spi_dev_s *dev, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)((char *)cb - - offsetof(struct stm32l4_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1715,7 +1715,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1757,16 +1757,16 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32_SPI_DMA - /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32l4_dmachannel() + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32l4_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32l4_dmachannel(priv->rxch); - priv->txdma = stm32l4_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1791,7 +1791,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1804,9 +1804,9 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l4_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1823,9 +1823,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI1_SCK); - stm32l4_configgpio(GPIO_SPI1_MISO); - stm32l4_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1848,9 +1848,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI2_SCK); - stm32l4_configgpio(GPIO_SPI2_MISO); - stm32l4_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1873,9 +1873,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI3_SCK); - stm32l4_configgpio(GPIO_SPI3_MISO); - stm32l4_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h index e296a7e82c4c7..a86dbf23c5711 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/stm32l4_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l4_spi1/2/...select and stm32l4_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l4_spi1/2/...select, - * stm32l4_spi1/2/...status, and stm32l4_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/...select() and stm32l4_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l4_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l4_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l4_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,28 +105,28 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l4_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -147,19 +147,19 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1register(struct spi_dev_s *dev, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2register(struct spi_dev_s *dev, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI3 -int stm32l4_spi3register(struct spi_dev_s *dev, +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index edea1f411ea56..411490c5bbcba 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_userspace.h" #include "stm32l4_start.h" @@ -149,10 +149,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l4_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l4_lowsetup(); - stm32l4_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -203,13 +203,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l4_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l4_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.h b/arch/arm/src/stm32l4/stm32l4_start.h index 33ba733a4fc3c..ed06d18ea65c1 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.h +++ b/arch/arm/src/stm32l4/stm32l4_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_START_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index d1e9d16c35a95..541399ba03829 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -107,24 +107,24 @@ * Private Types ****************************************************************************/ -struct stm32l4_tickless_s +struct stm32_tickless_s { - struct stm32l4_oneshot_s oneshot; - struct stm32l4_freerun_s freerun; + struct stm32_oneshot_s oneshot; + struct stm32_freerun_s freerun; }; /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Called when the one shot timer expires @@ -141,7 +141,7 @@ static struct stm32l4_tickless_s g_tickless; * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { tmrinfo("Expired...\n"); nxsched_process_timer(); @@ -185,22 +185,22 @@ void up_timer_initialize(void) /* Initialize the one-shot timer */ - ret = stm32l4_oneshot_initialize(&g_tickless.oneshot, + ret = stm32_oneshot_initialize(&g_tickless.oneshot, CONFIG_STM32_TICKLESS_ONESHOT, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed\n"); + tmrerr("ERROR: stm32_oneshot_initialize failed\n"); DEBUGPANIC(); } #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP /* Get the maximum delay of the one-shot timer in microseconds */ - ret = stm32l4_oneshot_max_delay(&g_tickless.oneshot, &max_delay); + ret = stm32_oneshot_max_delay(&g_tickless.oneshot, &max_delay); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_max_delay failed\n"); + tmrerr("ERROR: stm32_oneshot_max_delay failed\n"); DEBUGPANIC(); } @@ -219,12 +219,12 @@ void up_timer_initialize(void) /* Initialize the free-running timer */ - ret = stm32l4_freerun_initialize(&g_tickless.freerun, + ret = stm32_freerun_initialize(&g_tickless.freerun, CONFIG_STM32_TICKLESS_FREERUN, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_freerun_initialize failed\n"); + tmrerr("ERROR: stm32_freerun_initialize failed\n"); DEBUGPANIC(); } } @@ -264,7 +264,7 @@ void up_timer_initialize(void) int up_timer_gettime(struct timespec *ts) { - return stm32l4_freerun_counter(&g_tickless.freerun, ts); + return stm32_freerun_counter(&g_tickless.freerun, ts); } /**************************************************************************** @@ -305,7 +305,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_cancel(struct timespec *ts) { - return stm32l4_oneshot_cancel(&g_tickless.oneshot, ts); + return stm32_oneshot_cancel(&g_tickless.oneshot, ts); } /**************************************************************************** @@ -335,7 +335,7 @@ int up_timer_cancel(struct timespec *ts) int up_timer_start(const struct timespec *ts) { - return stm32l4_oneshot_start(&g_tickless.oneshot, - stm32l4_oneshot_handler, NULL, ts); + return stm32_oneshot_start(&g_tickless.oneshot, + stm32_oneshot_handler, NULL, ts); } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 4f085abbcf87c..65a83b9158990 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -39,7 +39,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" @@ -207,10 +207,10 @@ /* TIM Device Structure */ -struct stm32l4_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l4_tim_ops_s *ops; - enum stm32l4_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -220,184 +220,184 @@ struct stm32l4_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_tim_getperiod(struct stm32l4_tim_dev_s *dev); -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev); -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_tim_ops_s stm32l4_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l4_tim_enable, - .disable = stm32l4_tim_disable, - .setmode = stm32l4_tim_setmode, - .setfreq = stm32l4_tim_setfreq, - .setclock = stm32l4_tim_setclock, - .getclock = stm32l4_tim_getclock, - .setperiod = stm32l4_tim_setperiod, - .getperiod = stm32l4_tim_getperiod, - .getcounter = stm32l4_tim_getcounter, - .setchannel = stm32l4_tim_setchannel, - .setcompare = stm32l4_tim_setcompare, - .getcapture = stm32l4_tim_getcapture, - .setisr = stm32l4_tim_setisr, - .enableint = stm32l4_tim_enableint, - .disableint = stm32l4_tim_disableint, - .ackint = stm32l4_tim_ackint, - .checkint = stm32l4_tim_checkint, - .dump_regs = stm32l4_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32_TIM1 -struct stm32l4_tim_priv_s stm32l4_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 -struct stm32l4_tim_priv_s stm32l4_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32_TIM3 -struct stm32l4_tim_priv_s stm32l4_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32_TIM4 -struct stm32l4_tim_priv_s stm32l4_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32_TIM5 -struct stm32l4_tim_priv_s stm32l4_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32_TIM6 -struct stm32l4_tim_priv_s stm32l4_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32_TIM7 -struct stm32l4_tim_priv_s stm32l4_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32_TIM8 -struct stm32l4_tim_priv_s stm32l4_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32_TIM15 -struct stm32l4_tim_priv_s stm32l4_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32_TIM16 -struct stm32l4_tim_priv_s stm32l4_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32_TIM17 -struct stm32l4_tim_priv_s stm32l4_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -408,51 +408,51 @@ struct stm32l4_tim_priv_s stm32l4_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32 @@ -460,14 +460,14 @@ static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32 @@ -475,49 +475,49 @@ static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -525,14 +525,14 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32l4_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l4_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -540,8 +540,8 @@ static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: * Add support for input capture and bipolar dual outputs for TIM8 @@ -549,69 +549,69 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l4_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32l4_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -622,10 +622,10 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -667,16 +667,16 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, return -EINVAL; } - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -684,10 +684,10 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -701,7 +701,7 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -711,7 +711,7 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -838,17 +838,17 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32l4_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -860,7 +860,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -870,7 +870,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -963,16 +963,16 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32l4_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -984,7 +984,7 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1054,46 +1054,46 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l4_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l4_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: @@ -1112,12 +1112,12 @@ static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1145,10 +1145,10 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -1194,15 +1194,15 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1210,25 +1210,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1243,25 +1243,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1276,25 +1276,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1309,24 +1309,24 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1341,25 +1341,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1374,25 +1374,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1407,25 +1407,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1440,25 +1440,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1473,25 +1473,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1509,10 +1509,10 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1543,10 +1543,10 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1554,26 +1554,26 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l4_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1581,7 +1581,7 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1669,44 +1669,44 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l4_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l4_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l4_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1715,12 +1715,12 @@ static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l4_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1728,76 +1728,76 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) { #ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,30 +1808,30 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l4_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l4_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1904,7 +1904,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 698aa71e9a797..46cd7a6e2efa1 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -74,14 +74,14 @@ extern "C" /* TIM Device Structure */ -struct stm32l4_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l4_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l4_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -118,7 +118,7 @@ enum stm32l4_tim_mode_e /* TIM Channel Modes */ -enum stm32l4_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -151,41 +151,41 @@ enum stm32l4_tim_channel_e /* TIM Operations */ -struct stm32l4_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l4_tim_dev_s *dev); - void (*disable)(struct stm32l4_tim_dev_s *dev); - int (*setmode)(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); - int (*setfreq)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l4_tim_dev_s *dev); - void (*setperiod)(struct stm32l4_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l4_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l4_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); - int (*setcompare)(struct stm32l4_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l4_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l4_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l4_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l4_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32l4_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -194,14 +194,14 @@ struct stm32l4_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -219,7 +219,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index fcdfdb7656c8c..1c60f9abcf5e6 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -92,10 +92,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l4_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -108,17 +108,17 @@ struct stm32l4_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower); -static int stm32l4_stop(struct timer_lowerhalf_s *lower); -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -129,16 +129,16 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, - .setcallback = stm32l4_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32_TIM1 -static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -146,7 +146,7 @@ static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32_TIM2 -static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -154,7 +154,7 @@ static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32_TIM3 -static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -162,7 +162,7 @@ static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32_TIM4 -static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -170,7 +170,7 @@ static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32_TIM5 -static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -178,7 +178,7 @@ static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32_TIM6 -static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -186,7 +186,7 @@ static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32_TIM7 -static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -194,7 +194,7 @@ static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32_TIM8 -static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -202,7 +202,7 @@ static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32_TIM15 -static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -210,7 +210,7 @@ static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32_TIM16 -static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -218,7 +218,7 @@ static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32_TIM17 -static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -230,7 +230,7 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -241,10 +241,10 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *lower = - (struct stm32l4_lowerhalf_s *) arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *) arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -258,14 +258,14 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) } else { - stm32l4_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -279,10 +279,10 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -290,7 +290,7 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -304,7 +304,7 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -318,10 +318,10 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -338,7 +338,7 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -353,11 +353,11 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -405,7 +405,7 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -420,11 +420,11 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -449,7 +449,7 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -468,11 +468,11 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -482,7 +482,7 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -499,7 +499,7 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -516,9 +516,9 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -595,7 +595,7 @@ int stm32l4_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l4_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index 71e0c36f6125e..2c2b0747a38b8 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -84,7 +84,7 @@ * ****************************************************************************/ -static int stm32l4_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 94aaa33934608..059b5335cb58a 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -282,7 +282,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -295,7 +295,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c index eb955770cb610..20c63b2751a0e 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_uid.c + * arch/arm/src/stm32l4/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. @@ -50,7 +50,7 @@ * Public Functions ****************************************************************************/ -void stm32l4_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h index 935c67074bcbf..628e62290a946 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.h +++ b/arch/arm/src/stm32l4/stm32l4_uid.h @@ -48,6 +48,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l4_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32L4_STM32_UID_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index fd08208479c4a..5bbac6ed9b726 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -45,7 +45,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_usbdev.h" @@ -150,8 +150,8 @@ /* Request queue operations *************************************************/ -#define stm32l4_rqempty(ep) ((ep)->head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /* USB trace ****************************************************************/ @@ -236,7 +236,7 @@ /* The various states of a control pipe */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* No request in progress */ EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ @@ -249,7 +249,7 @@ enum stm32l4_ep0state_e /* Resume states */ -enum stm32l4_rsmstate_e +enum stm32_rsmstate_e { RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ RSMSTATE_STARTED, /* Resume sequence has been started */ @@ -264,28 +264,28 @@ union wb_u /* A container for a request so that the request make be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t bufno; /* Allocated buffer number */ uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t halted:1; /* true: Endpoint feature halted */ @@ -293,7 +293,7 @@ struct stm32l4_ep_s uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ }; -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s @@ -308,8 +308,8 @@ struct stm32l4_usbdev_s /* STM32-specific fields */ - uint8_t ep0state; /* State of EP0 (see enum stm32l4_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32l4_rsmstate_e) */ + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ uint8_t nesofs; /* ESOF counter (for resume support) */ uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ uint8_t selfpowered:1; /* 1: Device is self powered */ @@ -328,7 +328,7 @@ struct stm32l4_usbdev_s * ep0data * For OUT SETUP requests, the SETUP data phase must also complete before * the SETUP command can be processed. The ep0 packet receipt logic - * stm32l4_ep0_rdrequest will save the accompanying EP0 OUT data in + * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in * ep0data[] before the SETUP command is re-processed. * * ep0datlen @@ -342,7 +342,7 @@ struct stm32l4_usbdev_s /* The endpoint list */ - struct stm32l4_ep_s eplist[STM32_NENDPOINTS]; + struct stm32_ep_s eplist[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -352,156 +352,156 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); -static void stm32l4_checksetup(void); -static void stm32l4_dumpep(int epno); +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_checksetup(void); +static void stm32_dumpep(int epno); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) -# define stm32l4_checksetup() -# define stm32l4_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ static inline void - stm32l4_seteptxcount(uint8_t epno, uint16_t count); + stm32_seteptxcount(uint8_t epno, uint16_t count); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteptxaddr(uint8_t epno); -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count); + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); static inline uint16_t - stm32l4_geteprxcount(uint8_t epno); + stm32_geteprxcount(uint8_t epno); static inline void - stm32l4_seteprxaddr(uint8_t epno, uint16_t addr); + stm32_seteprxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteprxaddr(uint8_t epno); + stm32_geteprxaddr(uint8_t epno); static inline void - stm32l4_setepaddress(uint8_t epno, uint16_t addr); + stm32_setepaddress(uint8_t epno, uint16_t addr); static inline void - stm32l4_seteptype(uint8_t epno, uint16_t type); + stm32_seteptype(uint8_t epno, uint16_t type); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline void - stm32l4_setstatusout(uint8_t epno); + stm32_setstatusout(uint8_t epno); static inline void - stm32l4_clrstatusout(uint8_t epno); -static void stm32l4_clrrxdtog(uint8_t epno); -static void stm32l4_clrtxdtog(uint8_t epno); -static void stm32l4_clrepctrrx(uint8_t epno); -static void stm32l4_clrepctrtx(uint8_t epno); -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state); + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); static inline uint16_t - stm32l4_geteptxstatus(uint8_t epno); + stm32_geteptxstatus(uint8_t epno); static inline uint16_t - stm32l4_geteprxstatus(uint8_t epno); -static bool stm32l4_eptxstalled(uint8_t epno); -static bool stm32l4_eprxstalled(uint8_t epno); -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits); /* Suspend/Resume Helpers ***************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv); -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv); -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ; +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; /* Request Helpers **********************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes); static inline void - stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, + stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); -static struct stm32l4_req_s * - stm32l4_rqdequeue(struct stm32l4_ep_s *privep); -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); static inline void - stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_epwrite(struct stm32l4_usbdev_s *buf, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, const uint8_t *data, uint32_t nbytes); -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); inline static int - stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline int - stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv); -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep); + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); /* Interrupt level processing ***********************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv); -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno); -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void - stm32l4_ep0done(struct stm32l4_usbdev_s *priv, uint16_t istr); -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv); -static int stm32l4_usbinterrupt(int irq, void *context, void *arg); + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint helpers *********************************************************/ -static inline struct stm32l4_ep_s * - stm32l4_epreserve(struct stm32l4_usbdev_s *priv, +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); static inline void - stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline bool - stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno); -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv); + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); static inline void - stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* Endpoint operations ******************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static int stm32l4_epdisable(struct usbdev_ep_s *ep); +static int stm32_epdisable(struct usbdev_ep_s *ep); static struct usbdev_req_s * - stm32l4_epallocreq(struct usbdev_ep_s *ep); -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epcancel(struct usbdev_ep_s *ep, +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); /* USB device controller operations *****************************************/ static struct usbdev_ep_s * - stm32l4_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); /* Initialization/Reset *****************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -511,27 +511,27 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_usbdev; +static struct stm32_usbdev_s g_usbdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_epconfigure, - .disable = stm32l4_epdisable, - .allocreq = stm32l4_epallocreq, - .freereq = stm32l4_epfreereq, - .submit = stm32l4_epsubmit, - .cancel = stm32l4_epcancel, - .stall = stm32l4_epstall, + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_allocep, - .freeep = stm32l4_freeep, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /**************************************************************************** @@ -615,11 +615,11 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg ****************************************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint16_t preval = 0; @@ -674,11 +674,11 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg ****************************************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -691,11 +691,11 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_dumpep + * Name: stm32_dumpep ****************************************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32l4_dumpep(int epno) +static void stm32_dumpep(int epno) { uint32_t addr; @@ -734,11 +734,11 @@ static void stm32l4_dumpep(int epno) #endif /**************************************************************************** - * Name: stm32l4_checksetup + * Name: stm32_checksetup ****************************************************************************/ #ifdef CONFIG_STM32_USBDEV_REGDEBUG -static void stm32l4_checksetup(void) +static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR1); @@ -757,40 +757,40 @@ static void stm32l4_checksetup(void) #endif /**************************************************************************** - * Name: stm32l4_seteptxcount + * Name: stm32_seteptxcount ****************************************************************************/ -static inline void stm32l4_seteptxcount(uint8_t epno, uint16_t count) +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_TX(epno); *epaddr = count; } /**************************************************************************** - * Name: stm32l4_seteptxaddr + * Name: stm32_seteptxaddr ****************************************************************************/ -static inline void stm32l4_seteptxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) { volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); *txaddr = addr; } /**************************************************************************** - * Name: stm32l4_geteptxaddr + * Name: stm32_geteptxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteptxaddr(uint8_t epno) +static inline uint16_t stm32_geteptxaddr(uint8_t epno) { volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); return (uint16_t)*txaddr; } /**************************************************************************** - * Name: stm32l4_seteprxcount + * Name: stm32_seteprxcount ****************************************************************************/ -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) +static void stm32_seteprxcount(uint8_t epno, uint16_t count) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); uint32_t rxcount = 0; @@ -836,72 +836,72 @@ static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) } /**************************************************************************** - * Name: stm32l4_geteprxcount + * Name: stm32_geteprxcount ****************************************************************************/ -static inline uint16_t stm32l4_geteprxcount(uint8_t epno) +static inline uint16_t stm32_geteprxcount(uint8_t epno) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); return (*epaddr) & USB_COUNT_RX_MASK; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline void stm32l4_seteprxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) { volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); *rxaddr = addr; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteprxaddr(uint8_t epno) +static inline uint16_t stm32_geteprxaddr(uint8_t epno) { volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); return (uint16_t)*rxaddr; } /**************************************************************************** - * Name: stm32l4_setepaddress + * Name: stm32_setepaddress ****************************************************************************/ -static inline void stm32l4_setepaddress(uint8_t epno, uint16_t addr) +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EA_MASK; regval |= (addr << USB_EPR_EA_SHIFT); - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteptype + * Name: stm32_seteptype ****************************************************************************/ -static inline void stm32l4_seteptype(uint8_t epno, uint16_t type) +static inline void stm32_seteptype(uint8_t epno, uint16_t type) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EPTYPE_MASK; regval |= type; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_setstatusout + * Name: stm32_setstatusout ****************************************************************************/ -static inline void stm32l4_setstatusout(uint8_t epno) +static inline void stm32_setstatusout(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -911,17 +911,17 @@ static inline void stm32l4_setstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval |= USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrstatusout + * Name: stm32_clrstatusout ****************************************************************************/ -static inline void stm32l4_clrstatusout(uint8_t epno) +static inline void stm32_clrstatusout(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -931,102 +931,102 @@ static inline void stm32l4_clrstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrrxdtog + * Name: stm32_clrrxdtog ****************************************************************************/ -static void stm32l4_clrrxdtog(uint8_t epno) +static void stm32_clrrxdtog(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_RX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrtxdtog + * Name: stm32_clrtxdtog ****************************************************************************/ -static void stm32l4_clrtxdtog(uint8_t epno) +static void stm32_clrtxdtog(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_TX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrepctrrx + * Name: stm32_clrepctrrx ****************************************************************************/ -static void stm32l4_clrepctrrx(uint8_t epno) +static void stm32_clrepctrrx(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrepctrtx + * Name: stm32_clrepctrtx ****************************************************************************/ -static void stm32l4_clrepctrtx(uint8_t epno) +static void stm32_clrepctrtx(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_geteptxstatus + * Name: stm32_geteptxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteptxstatus(uint8_t epno) +static inline uint16_t stm32_geteptxstatus(uint8_t epno) { - return (uint16_t)(stm32l4_getreg(STM32_USB_EPR(epno)) & + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); } /**************************************************************************** - * Name: stm32l4_geteprxstatus + * Name: stm32_geteprxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteprxstatus(uint8_t epno) +static inline uint16_t stm32_geteprxstatus(uint8_t epno) { - return (stm32l4_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); } /**************************************************************************** - * Name: stm32l4_seteptxstatus + * Name: stm32_seteptxstatus ****************************************************************************/ -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -1036,7 +1036,7 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_TX bits to 1 if there value is different * from the bits requested in 'state' @@ -1044,14 +1044,14 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_TXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteprxstatus + * Name: stm32_seteprxstatus ****************************************************************************/ -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -1061,7 +1061,7 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_RX bits to 1 if there value is different * from the bits requested in 'state' @@ -1069,32 +1069,32 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_RXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_eptxstalled + * Name: stm32_eptxstalled ****************************************************************************/ -static inline bool stm32l4_eptxstalled(uint8_t epno) +static inline bool stm32_eptxstalled(uint8_t epno) { - return (stm32l4_geteptxstatus(epno) == USB_EPR_STATTX_STALL); + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); } /**************************************************************************** - * Name: stm32l4_eprxstalled + * Name: stm32_eprxstalled ****************************************************************************/ -static inline bool stm32l4_eprxstalled(uint8_t epno) +static inline bool stm32_eprxstalled(uint8_t epno) { - return (stm32l4_geteprxstatus(epno) == USB_EPR_STATRX_STALL); + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); } /**************************************************************************** - * Name: stm32l4_copytopma + * Name: stm32_copytopma ****************************************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *dest; @@ -1123,11 +1123,11 @@ static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, } /**************************************************************************** - * Name: stm32l4_copyfrompma + * Name: stm32_copyfrompma ****************************************************************************/ static inline void -stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *src; int nwords = (nbytes + 1) >> 1; @@ -1151,12 +1151,12 @@ stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) } /**************************************************************************** - * Name: stm32l4_rqdequeue + * Name: stm32_rqdequeue ****************************************************************************/ -static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -1173,11 +1173,11 @@ static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_rqenqueue + * Name: stm32_rqenqueue ****************************************************************************/ -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) { req->flink = NULL; if (!privep->head) @@ -1193,12 +1193,12 @@ static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_abortrequest + * Name: stm32_abortrequest ****************************************************************************/ static inline void -stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, int16_t result) +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); @@ -1213,18 +1213,18 @@ stm32l4_abortrequest(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_reqcomplete + * Name: stm32_reqcomplete ****************************************************************************/ -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ flags = enter_critical_section(); - privreq = stm32l4_rqdequeue(privep); + privreq = stm32_rqdequeue(privep); leave_critical_section(flags); if (privreq) @@ -1258,8 +1258,8 @@ static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) * Name: tm32_epwrite ****************************************************************************/ -static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, const uint8_t *buf, uint32_t nbytes) { uint8_t epno = USB_EPNO(privep->ep.eplog); @@ -1273,12 +1273,12 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, * endpoint */ - stm32l4_copytopma(buf, stm32l4_geteptxaddr(epno), nbytes); + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); } /* Send the packet (might be a null packet nbytes == 0) */ - stm32l4_seteptxcount(epno, nbytes); + stm32_seteptxcount(epno, nbytes); priv->txstatus = USB_EPR_STATTX_VALID; /* Indicate that there is data in the TX packet memory. This will be @@ -1289,30 +1289,30 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_wrrequest_ep0 + * Name: stm32_wrrequest_ep0 * * Description: * Handle the ep0 state on writes. * ****************************************************************************/ -inline static int stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { int ret; - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); return ret; } /**************************************************************************** - * Name: stm32l4_wrrequest + * Name: stm32_wrrequest ****************************************************************************/ -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *buf; uint8_t epno; int nbytes; @@ -1326,7 +1326,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* There is no TX transfer in progress and no new pending TX @@ -1388,7 +1388,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Send the packet (might be a null packet nbytes == 0) */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epwrite(priv, privep, buf, nbytes); + stm32_epwrite(priv, privep, buf, nbytes); /* Update for the next data IN interrupt */ @@ -1406,24 +1406,24 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); privep->txnullpkt = 0; - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_ep0_rdrequest + * Name: stm32_ep0_rdrequest * * Description: - * This function is called from the stm32l4_ep0out handler when the + * This function is called from the stm32_ep0out handler when the * ep0state is EP0STATE_SETUP_OUT and upon new incoming data is available * in the endpoint 0's buffer. This function will simply copy the OUT data * into ep0data. * ****************************************************************************/ -static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) { uint32_t src; int pmalen; @@ -1431,7 +1431,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(EP0); + pmalen = stm32_geteprxcount(EP0); uinfo("EP0: pmalen=%d\n", pmalen); usbtrace(TRACE_READ(EP0), pmalen); @@ -1439,11 +1439,11 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Read the data into our special buffer for SETUP data */ readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32l4_geteprxaddr(EP0); + src = stm32_geteprxaddr(EP0); /* Receive the next packet */ - stm32l4_copyfrompma(&priv->ep0data[0], src, readlen); + stm32_copyfrompma(&priv->ep0data[0], src, readlen); /* Now we can process the setup command */ @@ -1451,20 +1451,20 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) priv->ep0datlen = readlen; usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); - stm32l4_ep0setup(priv); + stm32_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ return OK; } /**************************************************************************** - * Name: stm32l4_rdrequest + * Name: stm32_rdrequest ****************************************************************************/ -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t src; uint8_t *dest; uint8_t epno; @@ -1474,7 +1474,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ epno = USB_EPNO(privep->ep.eplog); - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data available in PMA, but no packet to receive the data. @@ -1494,7 +1494,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); return OK; } @@ -1503,16 +1503,16 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Get the source and destination transfer addresses */ dest = privreq->req.buf + privreq->req.xfrd; - src = stm32l4_geteprxaddr(epno); + src = stm32_geteprxaddr(epno); /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(epno); + pmalen = stm32_geteprxcount(epno); readlen = MIN(privreq->req.len, pmalen); /* Receive the next packet */ - stm32l4_copyfrompma(dest, src, readlen); + stm32_copyfrompma(dest, src, readlen); /* If the receive buffer is full or this is a partial packet, * then we are finished with the request buffer). @@ -1524,23 +1524,23 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Return the read request to the class driver. */ usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_cancelrequests + * Name: stm32_cancelrequests ****************************************************************************/ -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) +static void stm32_cancelrequests(struct stm32_ep_s *privep) { - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_reqcomplete(privep, -ESHUTDOWN); + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); } } @@ -1549,10 +1549,10 @@ static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dispatchrequest + * Name: stm32_dispatchrequest ****************************************************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) { int ret; @@ -1574,17 +1574,17 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epdone + * Name: stm32_epdone ****************************************************************************/ -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint16_t epr; /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32_USB_EPR(epno)); + epr = stm32_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1600,11 +1600,11 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) * accept the host data. */ - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { /* Read host data into the current read request */ - stm32l4_rdrequest(priv, privep); + stm32_rdrequest(priv, privep); /* "After the received data is processed, the application software * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, @@ -1616,7 +1616,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* NAK further OUT packets if there there no more read requests */ - if (stm32l4_rqempty(privep)) + if (stm32_rqempty(privep)) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); @@ -1634,8 +1634,8 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear the interrupt status and set the new RX status */ - stm32l4_clrepctrrx(epno); - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); } /* IN: device-to-host @@ -1647,7 +1647,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) { /* Clear interrupt status */ - stm32l4_clrepctrtx(epno); + stm32_clrepctrtx(epno); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ @@ -1655,24 +1655,24 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } /**************************************************************************** - * Name: stm32l4_setdevaddr + * Name: stm32_setdevaddr ****************************************************************************/ -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) { int epno; @@ -1680,26 +1680,26 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - if (stm32l4_epreserved(priv, epno)) + if (stm32_epreserved(priv, epno)) { - stm32l4_setepaddress((uint8_t)epno, (uint8_t)epno); + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); } } /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** - * Name: stm32l4_ep0setup + * Name: stm32_ep0setup ****************************************************************************/ -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32l4_req_s *privreq = stm32l4_rqpeek(ep0); - struct stm32l4_ep_s *privep; + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; union wb_u value; union wb_u index; union wb_u len; @@ -1712,7 +1712,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * was a zero-length transfer!) */ - while (!stm32l4_rqempty(ep0)) + while (!stm32_rqempty(ep0)) { int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) @@ -1721,7 +1721,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32l4_reqcomplete(ep0, result); + stm32_reqcomplete(ep0, result); } /* Assume NOT stalled; no TX in progress */ @@ -1739,7 +1739,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * request */ - stm32l4_copyfrompma((uint8_t *)&priv->ctrl, stm32l4_geteprxaddr(EP0), + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); /* And extract the little-endian 16-bit values to host order */ @@ -1777,7 +1777,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Let the class implementation handle all non-standar requests */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); return; } @@ -1828,7 +1828,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { /* IN Endpoint stalled */ @@ -1839,7 +1839,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { /* OUT Endpoint stalled */ @@ -1913,7 +1913,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * the endpoint recipient) */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1926,7 +1926,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 0; - stm32l4_epstall(&privep->ep, true); + stm32_epstall(&privep->ep, true); } else { @@ -1962,7 +1962,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * endpoint */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1975,7 +1975,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 1; - stm32l4_epstall(&privep->ep, false); + stm32_epstall(&privep->ep, false); } else { @@ -2033,7 +2033,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2056,7 +2056,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -2084,7 +2084,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -2114,7 +2114,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2171,16 +2171,16 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Send the response (might be a zero-length packet) */ - stm32l4_epwrite(priv, ep0, response.b, nbytes); + stm32_epwrite(priv, ep0, response.b, nbytes); priv->ep0state = EP0STATE_IDLE; } } /**************************************************************************** - * Name: stm32l4_ep0in + * Name: stm32_ep0in ****************************************************************************/ -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) +static void stm32_ep0in(struct stm32_usbdev_s *priv) { /* There is no longer anything in the EP0 TX packet memory */ @@ -2192,7 +2192,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_WRREQUEST) { - stm32l4_wrrequest_ep0(priv, &priv->eplist[EP0]); + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); } /* No.. Are we processing the completion of a status response? */ @@ -2209,7 +2209,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) { union wb_u value; value.w = GETUINT16(priv->ctrl.value); - stm32l4_setdevaddr(priv, value.b[LSB]); + stm32_setdevaddr(priv, value.b[LSB]); } } else @@ -2219,24 +2219,24 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0out + * Name: stm32_ep0out ****************************************************************************/ -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out(struct stm32_usbdev_s *priv) { int ret; - struct stm32l4_ep_s *privep = &priv->eplist[EP0]; + struct stm32_ep_s *privep = &priv->eplist[EP0]; switch (priv->ep0state) { case EP0STATE_RDREQUEST: /* Read request in progress */ case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32l4_rdrequest(priv, privep); + ret = stm32_rdrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); break; case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32l4_ep0_rdrequest(priv); /* Off load the data and run the + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the * last set up command with the * OUT data */ @@ -2259,10 +2259,10 @@ static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0done + * Name: stm32_ep0done ****************************************************************************/ -static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) { uint16_t epr; @@ -2277,8 +2277,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Set both RX and TX status to NAK */ - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); /* Check the direction bit to determine if this the completion of an EP0 * packet sent to or received from the host PC. @@ -2289,14 +2289,14 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* EP0 IN: device-to-host (DIR=0) */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } else { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32_USB_EPR(EP0)); + epr = stm32_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2305,8 +2305,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } /* SETUP is set by the hardware when the last completed @@ -2316,8 +2316,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0setup(priv); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); } /* Set by the hardware when an OUT/SETUP transaction successfully @@ -2327,8 +2327,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0out(priv); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); } /* None of the above */ @@ -2342,7 +2342,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2379,24 +2379,24 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Now set the new TX and RX status */ - stm32l4_seteprxstatus(EP0, priv->rxstatus); - stm32l4_seteptxstatus(EP0, priv->txstatus); + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); } /**************************************************************************** - * Name: stm32l4_lptransfer + * Name: stm32_lptransfer ****************************************************************************/ -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) +static void stm32_lptransfer(struct stm32_usbdev_s *priv) { uint8_t epno; uint16_t istr; /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2406,31 +2406,31 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) if (epno == 0) { - stm32l4_ep0done(priv, istr); + stm32_ep0done(priv, istr); } /* Handle other endpoint completion events */ else { - stm32l4_epdone(priv, epno); + stm32_epdone(priv, epno); } } } /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32_USB_ISTR); + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr = stm32_getreg(STM32_USB_ISTR); usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); @@ -2443,14 +2443,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. */ - stm32l4_reset(priv); + stm32_reset(priv); goto out; } @@ -2464,13 +2464,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), - stm32l4_getreg(STM32_USB_FNR)); + stm32_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the wakeup interrupt, and @@ -2478,31 +2478,31 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * interrupts. */ - stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); - stm32l4_suspend(priv); + stm32_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); - stm32l4_esofpoll(priv); + stm32_esofpoll(priv); } if ((istr & USB_ISTR_CTR & priv->imask) != 0) @@ -2510,20 +2510,20 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Low priority endpoint correct transfer interrupt */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); - stm32l4_lptransfer(priv); + stm32_lptransfer(priv); } out: usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32_USB_EP0R)); + stm32_getreg(STM32_USB_EP0R)); return OK; } /**************************************************************************** - * Name: stm32l4_setimask + * Name: stm32_setimask ****************************************************************************/ -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t regval; @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2548,10 +2548,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_suspend + * Name: stm32_suspend ****************************************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) +static void stm32_suspend(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2566,16 +2566,16 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,23 +2586,23 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_initresume + * Name: stm32_initresume ****************************************************************************/ -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) +static void stm32_initresume(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2616,17 +2616,17 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2637,10 +2637,10 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_esofpoll + * Name: stm32_esofpoll ****************************************************************************/ -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) +static void stm32_esofpoll(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,18 +2666,18 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable * the WKUP interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2693,13 +2693,13 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epreserve + * Name: stm32_epreserve ****************************************************************************/ -static inline struct stm32l4_ep_s * -stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) { - struct stm32l4_ep_s *privep = NULL; + struct stm32_ep_s *privep = NULL; irqstate_t flags; int epndx = 0; @@ -2733,12 +2733,12 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) } /**************************************************************************** - * Name: stm32l4_epunreserve + * Name: stm32_epunreserve ****************************************************************************/ static inline void -stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); @@ -2746,20 +2746,20 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_epreserved + * Name: stm32_epreserved ****************************************************************************/ static inline bool -stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) { return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** - * Name: stm32l4_epallocpma + * Name: stm32_epallocpma ****************************************************************************/ -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) +static int stm32_epallocpma(struct stm32_usbdev_s *priv) { irqstate_t flags; int bufno = ERROR; @@ -2789,11 +2789,11 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epfreepma + * Name: stm32_epfreepma ****************************************************************************/ static inline void -stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); priv->epavail |= STM32_ENDP_BIT(privep->bufno); @@ -2805,14 +2805,14 @@ stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epconfigure + * Name: stm32_epconfigure ****************************************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t pma; uint16_t setting; uint16_t maxpacket; @@ -2860,7 +2860,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, return -EINVAL; } - stm32l4_seteptype(epno, setting); + stm32_seteptype(epno, setting); /* Get the address of the PMA buffer allocated for this endpoint */ @@ -2883,9 +2883,9 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up TX; disable RX */ - stm32l4_seteptxaddr(epno, pma); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); } else { @@ -2895,23 +2895,23 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up RX; disable TX */ - stm32l4_seteprxaddr(epno, pma); - stm32l4_seteprxcount(epno, maxpacket); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); } - stm32l4_dumpep(epno); + stm32_dumpep(epno); return OK; } /**************************************************************************** - * Name: stm32l4_epdisable + * Name: stm32_epdisable ****************************************************************************/ -static int stm32l4_epdisable(struct usbdev_ep_s *ep) +static int stm32_epdisable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; uint8_t epno; @@ -2930,25 +2930,25 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) /* Cancel any ongoing activity */ flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Disable TX; disable RX */ - stm32l4_seteprxcount(epno, 0); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epallocreq + * Name: stm32_epallocreq ****************************************************************************/ -static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -2960,25 +2960,25 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_epfreereq + * Name: stm32_epfreereq ****************************************************************************/ -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) @@ -2994,14 +2994,14 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_epsubmit + * Name: stm32_epsubmit ****************************************************************************/ -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; uint8_t epno; int ret = OK; @@ -3040,7 +3040,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { - stm32l4_abortrequest(privep, privreq, -EBUSY); + stm32_abortrequest(privep, privreq, -EBUSY); uerr("ERROR: stalled\n"); ret = -EBUSY; } @@ -3054,7 +3054,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* Add the new request to the request queue for the IN endpoint */ - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_INREQQUEUED(epno), req->len); /* If the IN endpoint FIFO is available, then transfer the data now */ @@ -3064,16 +3064,16 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - ret = stm32l4_wrrequest_ep0(priv, privep); + ret = stm32_wrrequest_ep0(priv, privep); } else { - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } @@ -3084,7 +3084,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) /* Add the new request to the request queue for the OUT endpoint */ privep->txnullpkt = 0; - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_OUTREQQUEUED(epno), req->len); /* This there a incoming data pending the availability of a request? */ @@ -3099,7 +3099,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) */ priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_seteprxstatus(epno, priv->rxstatus); /* Data is no longer pending */ @@ -3112,12 +3112,12 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) } /**************************************************************************** - * Name: stm32l4_epcancel + * Name: stm32_epcancel ****************************************************************************/ -static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_USB @@ -3131,19 +3131,19 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epstall + * Name: stm32_epstall ****************************************************************************/ -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep; - struct stm32l4_usbdev_s *priv; + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; uint8_t epno; uint16_t status; irqstate_t flags; @@ -3156,8 +3156,8 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) } #endif - privep = (struct stm32l4_ep_s *)ep; - priv = (struct stm32l4_usbdev_s *)privep->dev; + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; epno = USB_EPNO(ep->eplog); /* STALL or RESUME the endpoint */ @@ -3171,11 +3171,11 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (USB_ISEPIN(ep->eplog)) { - status = stm32l4_geteptxstatus(epno); + status = stm32_geteptxstatus(epno); } else { - status = stm32l4_geteprxstatus(epno); + status = stm32_geteprxstatus(epno); } if (status == 0) @@ -3204,32 +3204,32 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { - stm32l4_clrtxdtog(epno); + stm32_clrtxdtog(epno); /* Restart any queued write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } else { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { if (epno == EP0) { @@ -3237,15 +3237,15 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) * enable the default endpoint receiver */ - stm32l4_seteprxcount(epno, ep->maxpacket); + stm32_seteprxcount(epno, ep->maxpacket); } else { - stm32l4_clrrxdtog(epno); + stm32_clrrxdtog(epno); } priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); } } } @@ -3262,14 +3262,14 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) /* IN endpoint */ priv->txstatus = USB_EPR_STATTX_STALL; - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_STALL); + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); } else { /* OUT endpoint */ priv->rxstatus = USB_EPR_STATRX_STALL; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_STALL); + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); } } @@ -3282,15 +3282,15 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_allocep + * Name: stm32_allocep ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = NULL; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; uint8_t epset = STM32_ENDP_ALLSET; int bufno; @@ -3335,7 +3335,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, /* Check if the selected endpoint number is available */ - privep = stm32l4_epreserve(priv, epset); + privep = stm32_epreserve(priv, epset); if (!privep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); @@ -3345,7 +3345,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, /* Allocate a PMA buffer for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32l4_epallocpma(priv); + bufno = stm32_epallocpma(priv); if (bufno < 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); @@ -3356,19 +3356,19 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, return &privep->ep; errout_with_ep: - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); errout: return NULL; } /**************************************************************************** - * Name: stm32l4_freeep + * Name: stm32_freeep ****************************************************************************/ -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv; - struct stm32l4_ep_s *privep; + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; #ifdef CONFIG_DEBUG_USB if (!dev || !ep) @@ -3378,27 +3378,27 @@ static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) } #endif - priv = (struct stm32l4_usbdev_s *)dev; - privep = (struct stm32l4_ep_s *)ep; + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); if (priv && privep) { /* Free the PMA buffer assigned to this endpoint */ - stm32l4_epfreepma(priv, privep); + stm32_epfreepma(priv, privep); /* Mark the endpoint as available */ - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint16_t fnr; @@ -3412,18 +3412,18 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32_USB_FNR); + fnr = stm32_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; irqstate_t flags; usbtrace(TRACE_DEVWAKEUP, 0); @@ -3440,7 +3440,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ flags = enter_critical_section(); - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_STARTED; /* Disable the SUSP interrupt (until we are fully resumed), disable @@ -3449,19 +3449,19 @@ static int stm32l4_wakeup(struct usbdev_s *dev) * pending ESOF interrupt. */ - stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); @@ -3478,10 +3478,10 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; irqstate_t flags; @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32_USB_BCDR); + regval = stm32_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32_USB_BCDR); + stm32_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3517,16 +3517,16 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset ****************************************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv) +static void stm32_reset(struct stm32_usbdev_s *priv) { int epno; /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3544,17 +3544,17 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - struct stm32l4_ep_s *privep = &priv->eplist[epno]; + struct stm32_ep_s *privep = &priv->eplist[epno]; /* Cancel any queued requests. Since they are canceled * with status -ESHUTDOWN, then will not be requeued * until the configuration is reset. NOTE: This should * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32l4_epdisable + * result in the class implementation calling stm32_epdisable * for each of its configured endpoints. */ - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Reset endpoint status */ @@ -3566,59 +3566,59 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Re-configure the USB controller in its initial, unconnected state */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); priv->usbdev.speed = USB_SPEED_FULL; } /**************************************************************************** - * Name: stm32l4_hwreset + * Name: stm32_hwreset ****************************************************************************/ -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) +static void stm32_hwreset(struct stm32_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32_USB_CNTR); + stm32_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ - stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32_EP0_TXADDR); - stm32l4_clrstatusout(EP0); - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); /* Set the device to respond on default address */ - stm32l4_setdevaddr(priv, 0); + stm32_setdevaddr(priv, 0); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32_CNTR_SETUP, + stm32_setimask(priv, STM32_CNTR_SETUP, (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); - stm32l4_dumpep(EP0); + stm32_dumpep(EP0); } /**************************************************************************** - * Name: stm32l4_hwsetup + * Name: stm32_hwsetup ****************************************************************************/ -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) +static void stm32_hwsetup(struct stm32_usbdev_s *priv) { int epno; @@ -3626,20 +3626,20 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Initialize the device state structure. NOTE: many fields * have the initial value of zero and, hence, are not explicitly * initialized here. */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); @@ -3691,33 +3691,33 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } /**************************************************************************** - * Name: stm32l4_hwshutdown + * Name: stm32_hwshutdown ****************************************************************************/ -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) { priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3739,25 +3739,25 @@ void arm_usbinitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; usbtrace(TRACE_DEVINIT, 0); - stm32l4_checksetup(); + stm32_checksetup(); /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* Power up the USB controller, but leave it in the reset state */ - stm32l4_hwsetup(priv); + stm32_hwsetup(priv); /* Attach USB controller interrupt handler. The hardware will not be * initialized and interrupts will not be enabled until the class device * driver is bound. */ - if (irq_attach(STM32_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32_usbinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), (uint16_t)STM32_IRQ_USB_FS); @@ -3780,7 +3780,7 @@ void arm_usbuninitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; flags = enter_critical_section(); @@ -3799,11 +3799,11 @@ void arm_usbuninitialize(void) /* Put the hardware in an inactive state */ - stm32l4_hwshutdown(priv); + stm32_hwshutdown(priv); /* Disable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(false); + stm32_pwr_enableusv(false); leave_critical_section(flags); } @@ -3824,7 +3824,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -3861,7 +3861,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * the USB controller */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); /* Enable USB controller interrupt at the NVIC */ @@ -3871,7 +3871,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * The host should enumerate us some time after this */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -3896,7 +3896,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -3914,7 +3914,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_reset(priv); + stm32_reset(priv); /* Unbind the class driver */ @@ -3925,12 +3925,12 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32l4_reset() + * in the reset state (this is probably not necessary, the stm32_reset() * call above was probably sufficient). */ - stm32l4_hwshutdown(priv); - stm32l4_hwsetup(priv); + stm32_hwshutdown(priv); + stm32_hwsetup(priv); /* Unhook the driver */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.h b/arch/arm/src/stm32l4/stm32l4_usbdev.h index e20b4be89ca85..427244a5789af 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.h @@ -50,17 +50,17 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index 98d04ef5a5377..a0fa0b24f9c24 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -168,7 +168,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -196,7 +196,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_usbhost_vbusdrive(int iface, bool enable); +void stm32_usbhost_vbusdrive(int iface, bool enable); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c index 178beee45e5e8..8ff1252348072 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c +++ b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c @@ -47,7 +47,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_usbhost_trace_s +struct stm32_usbhost_trace_s { #if 0 uint16_t id; @@ -60,7 +60,7 @@ struct stm32l4_usbhost_trace_s * Private Data ****************************************************************************/ -static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = { TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"), @@ -117,7 +117,7 @@ static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = #endif }; -static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = { TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"), diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.c b/arch/arm/src/stm32l4/stm32l4_userspace.c index e6e181f9e19d9..d23687632538b 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.c +++ b/arch/arm/src/stm32l4/stm32l4_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l4_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l4_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l4_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.h b/arch/arm/src/stm32l4/stm32l4_userspace.h index df0479c82b519..c1b820bff13e6 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.h +++ b/arch/arm/src/stm32l4/stm32l4_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_waste.c b/arch/arm/src/stm32l4/stm32l4_waste.c index 1335005e75b5a..97750308cebde 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.c +++ b/arch/arm/src/stm32l4/stm32l4_waste.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_waste.c + * arch/arm/src/stm32l4/stm32_waste.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ uint32_t g_waste_counter = 0; * Public Functions ****************************************************************************/ -void stm32l4_waste(void) +void stm32_waste(void) { g_waste_counter++; } diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h index f0c9df7cd3fbe..0f128b24a8b4c 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ b/arch/arm/src/stm32l4/stm32l4_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32l4_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a * measure of badly written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32l4_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index e09421158406a..99a41479eb3bd 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog time. The watchdog timer is initialized @@ -72,11 +72,11 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_STM32_IWDG -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif /**************************************************************************** - * Name: stm32l4_wwdginitialize + * Name: stm32_wwdginitialize * * Description: * Initialize the WWDG watchdog time. The watchdog timer is initialized @@ -93,7 +93,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); ****************************************************************************/ #ifdef CONFIG_STM32_WWDG -void stm32l4_wwdginitialize(const char *devpath); +void stm32_wwdginitialize(const char *devpath); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 6c9d589242d2e..5c46cc182bcad 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -591,7 +591,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -601,7 +601,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -886,7 +886,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -901,7 +901,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -912,7 +912,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -942,7 +942,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 9eae8bc68ff38..254efbeb45b00 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -581,7 +581,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -591,7 +591,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -876,7 +876,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -891,7 +891,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -902,7 +902,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 565ddbf5a61bd..3d9f0a7f91a9b 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -41,7 +41,7 @@ #include "sched/sched.h" #include "chip.h" #include "stm32l4_dma.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ /* This structure describes one DMA channel */ -struct stm32l4_dma_s +struct stm32_dma_s { uint8_t chan; /* DMA channel number (0-6) */ uint8_t function; /* DMA peripheral connected to this channel (0-7) */ @@ -82,7 +82,7 @@ struct stm32l4_dma_s /* This array describes the state of each DMA */ -static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, @@ -182,7 +182,7 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* Get non-channel register from DMA1 or DMA2 */ -static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(DMA_BASE(dmach->base) + offset); @@ -190,7 +190,7 @@ static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, /* Write to non-channel register in DMA1 or DMA2 */ -static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, DMA_BASE(dmach->base) + offset); @@ -198,7 +198,7 @@ static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, /* Get channel register from DMA1 or DMA2 */ -static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(dmach->base + offset); @@ -206,21 +206,21 @@ static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, /* Write to channel register in DMA1 or DMA2 */ -static inline void dmachan_putreg(struct stm32l4_dma_s *dmach, +static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, dmach->base + offset); } /**************************************************************************** - * Name: stm32l4_dmachandisable + * Name: stm32_dmachandisable * * Description: * Disable the DMA channel * ****************************************************************************/ -static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) +static void stm32_dmachandisable(struct stm32_dma_s *dmach) { uint32_t regval; @@ -241,16 +241,16 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) } /**************************************************************************** - * Name: stm32l4_dmainterrupt + * Name: stm32_dmainterrupt * * Description: * DMA interrupt handler * ****************************************************************************/ -static int stm32l4_dmainterrupt(int irq, void *context, void *arg) +static int stm32_dmainterrupt(int irq, void *context, void *arg) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; uint32_t isr; int chndx = 0; @@ -303,7 +303,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dmainitialize + * Name: stm32_dmainitialize * * Description: * Initialize the DMA subsystem @@ -315,7 +315,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) void weak_function arm_dma_initialize(void) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; int chndx; /* Initialize each DMA channel */ @@ -326,11 +326,11 @@ void weak_function arm_dma_initialize(void) /* Attach DMA interrupt vectors */ - irq_attach(dmach->irq, stm32l4_dmainterrupt, NULL); + irq_attach(dmach->irq, stm32_dmainterrupt, NULL); /* Disable the DMA channel */ - stm32l4_dmachandisable(dmach); + stm32_dmachandisable(dmach); /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ @@ -339,7 +339,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -348,10 +348,10 @@ void weak_function arm_dma_initialize(void) * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will wait + * If the DMA channel is not available, then stm32_dmachannel() will wait * until the holder of the channel relinquishes the channel by calling - * stm32l4_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32l4_dmachannel + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel * call for the other will hang forever in this function! Don't let your * design do that! * @@ -375,12 +375,12 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) +DMA_HANDLE stm32_dmachannel(unsigned int chndef) { int ret; int chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> DMACHAN_SETTING_CHANNEL_SHIFT; - struct stm32l4_dma_s *dmach = &g_dma[chndx]; + struct stm32_dma_s *dmach = &g_dma[chndx]; DEBUGASSERT(chndx < DMA_NCHANNELS); @@ -407,13 +407,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA channel - * in a call to stm32l4_dmachannel, then this function will re-assign the + * in a call to stm32_dmachannel, then this function will re-assign the * DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32l4_dmachannel() is + * in this argument must NEVER be used again until stm32_dmachannel() is * called again to re-gain access to the channel. * * Returned Value: @@ -425,9 +425,9 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; DEBUGASSERT(handle != NULL); @@ -437,17 +437,17 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t regval; DEBUGASSERT(handle != NULL); @@ -505,21 +505,21 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t ccr; DEBUGASSERT(handle != NULL); @@ -571,44 +571,44 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - stm32l4_dmachandisable(dmach); + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -622,7 +622,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t mend; @@ -698,20 +698,20 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; irqstate_t flags; flags = enter_critical_section(); @@ -726,21 +726,21 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); dmainfo("DMA Registers: %s\n", msg); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 8b5984d6294ca..7e2aedd47365d 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -659,7 +659,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -669,7 +669,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -812,7 +812,7 @@ static void stm32l4_stdclockconfig(void) /* TODO: this seems to hang on STM32L476, at least for MSI@48MHz */ #if 0 - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(1); #endif } @@ -822,7 +822,7 @@ static void stm32l4_stdclockconfig(void) * frequencies below 24 MHz */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(2); } @@ -1002,7 +1002,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_BOARD_USEHSI) @@ -1025,7 +1025,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -1036,7 +1036,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -1066,7 +1066,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 0627df9e053bc..0c7891e318751 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -82,20 +82,20 @@ /* This structure described one DMAMUX device */ -struct stm32l4_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32l4_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32l4_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32l4_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -104,7 +104,7 @@ struct stm32l4_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32l4_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -117,11 +117,11 @@ struct stm32l4_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32l4_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32l4_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -152,12 +152,12 @@ struct stm32l4_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -167,19 +167,19 @@ struct stm32l4_dma_ops_s ****************************************************************************/ #if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan); -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg); -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32l4_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_sample(DMA_HANDLE handle, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -194,14 +194,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -210,20 +210,20 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { #ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -236,14 +236,14 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* 1 - DMA2 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -255,7 +255,7 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, @@ -266,7 +266,7 @@ static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = /* This array describes the state of each controller */ -static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ @@ -291,7 +291,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { #ifdef CONFIG_STM32_DMA1 /* DMA1 */ @@ -524,7 +524,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32l4_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -532,7 +532,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -540,7 +540,7 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -548,14 +548,14 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32l4_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -574,14 +574,14 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, #if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** - * Name: stm32l4_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -604,14 +604,14 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) } /**************************************************************************** - * Name: stm32l4_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -650,7 +650,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32l4_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ @@ -673,14 +673,14 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -745,13 +745,13 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, } /**************************************************************************** - * Name: stm32l4_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -807,10 +807,10 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32l4_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32l4_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -820,11 +820,11 @@ static size_t stm32l4_dma12_residual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; @@ -837,7 +837,7 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -846,12 +846,12 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -879,7 +879,7 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } @@ -888,12 +888,12 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, #endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** - * Name: stm32l4_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); @@ -906,12 +906,12 @@ static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, #endif /**************************************************************************** - * Name: stm32l4_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", @@ -987,7 +987,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1011,7 +1011,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1033,7 +1033,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1077,13 +1077,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1095,7 +1095,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1121,14 +1121,14 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1145,18 +1145,18 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1194,19 +1194,19 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1235,17 +1235,17 @@ void stm32l4_dmastop(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1261,7 +1261,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1278,7 +1278,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1354,18 +1354,18 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1382,18 +1382,18 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index e420f09624e04..e3a42befec099 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -646,7 +646,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -656,7 +656,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -951,7 +951,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -967,7 +967,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -997,7 +997,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h index a225fd336aa46..c18d2e1e4d3e1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h @@ -133,7 +133,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -142,11 +142,11 @@ ****************************************************************************/ #if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) -int stm32l4_bringup(void); +int stm32_bringup(void); #endif /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -156,7 +156,7 @@ int stm32l4_bringup(void); #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ defined(CONFIG_STM32_SPI3) -void weak_function stm32l4_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif /**************************************************************************** @@ -175,11 +175,11 @@ void weak_function stm32l4_spidev_initialize(void); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void); +int stm32_timer_driver_setup(void); #endif /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -191,7 +191,7 @@ int stm32l4_timer_driver_setup(void); ****************************************************************************/ #ifdef HAVE_SPSGRF -int stm32l4_spirit_initialize(void); +int stm32_spirit_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c index 065c7aca0d09b..269354efbc1fa 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c @@ -73,7 +73,7 @@ void board_autoled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** @@ -84,7 +84,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); } } @@ -96,7 +96,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); } } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index 02f3b5fcb8891..550eb357b23e2 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -48,17 +48,17 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /* Configure SPI chip selects if * 1) SPI is not disabled, and 2) the weak function - * stm32l4_spidev_initialize() has been brought into the link. + * stm32_spidev_initialize() has been brought into the link. */ - if (stm32l4_spidev_initialize) + if (stm32_spidev_initialize) { - stm32l4_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -88,6 +88,6 @@ void board_late_initialize(void) { /* Perform board initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c index cdbb58f24fbeb..838b4349ff675 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c @@ -49,7 +49,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -57,7 +57,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; @@ -95,10 +95,10 @@ int stm32l4_bringup(void) struct qspi_dev_s *g_qspi; struct mtd_dev_s *g_mtd_fs; - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (g_qspi == NULL) { - syslog(LOG_ERR, "ERROR: stm32l4_qspi_initialize failed\n"); + syslog(LOG_ERR, "ERROR: stm32_qspi_initialize failed\n"); return -EIO; } @@ -222,10 +222,10 @@ int stm32l4_bringup(void) #ifdef HAVE_SPSGRF /* Configure Spirit/SPSGRF wireless */ - ret = stm32l4_spirit_initialize(); + ret = stm32_spirit_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_spirit_initialize() failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_spirit_initialize() failed: %d\n", ret); } #endif @@ -233,7 +233,7 @@ int stm32l4_bringup(void) #ifdef CONFIG_TIMER /* Register timer drivers */ - ret = stm32l4_timer_driver_setup(); + ret = stm32_timer_driver_setup(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index 90ade076ba0b8..dac9cc457eab1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -79,7 +79,7 @@ struct spi_dev_s *g_spi3; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -87,12 +87,12 @@ struct spi_dev_s *g_spi3; * ****************************************************************************/ -void weak_function stm32l4_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { #ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -104,7 +104,7 @@ void weak_function stm32l4_spidev_initialize(void) #ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); /* Configure chip select GPIOs */ #endif @@ -112,30 +112,30 @@ void weak_function stm32l4_spidev_initialize(void) #ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); /* Configure chip select GPIOs */ #ifdef HAVE_SPSGRF - stm32l4_configgpio(GPIO_SPSGRF_CS); + stm32_configgpio(GPIO_SPSGRF_CS); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. * They are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by * common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -149,35 +149,35 @@ void weak_function stm32l4_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -186,19 +186,19 @@ void stm32l4_spi3select(struct spi_dev_s *dev, #ifdef HAVE_SPSGRF if (devid == SPIDEV_WIRELESS(0)) { - stm32l4_gpiowrite(GPIO_SPSGRF_CS, !selected); + stm32_gpiowrite(GPIO_SPSGRF_CS, !selected); } #endif } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -222,21 +222,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c index 0adaebb0c1822..9a471bd9f0cbd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c @@ -59,7 +59,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_priv_s +struct stm32_priv_s { struct spirit_lower_s dev; xcpt_t handler; @@ -77,18 +77,18 @@ struct stm32l4_priv_s * to isolate the Spirit driver from differences in GPIO interrupt handling * varying boards and MCUs. * - * stm32l4_reset - Reset the Spirit part. - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_reset - Reset the Spirit part. + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_reset(const struct spirit_lower_s *lower); -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_reset(const struct spirit_lower_s *lower); +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg); -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state); -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); +static int stm32_spirit_devsetup(struct stm32_priv_s *priv); /**************************************************************************** * Private Data @@ -104,11 +104,11 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); * may modify frequency or X plate resistance values. */ -static struct stm32l4_priv_s g_spirit = +static struct stm32_priv_s g_spirit = { - .dev.reset = stm32l4_reset, - .dev.attach = stm32l4_attach_irq, - .dev.enable = stm32l4_enable_irq, + .dev.reset = stm32_reset, + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, .handler = NULL, .arg = NULL, .intcfg = GPIO_SPSGRF_INT, @@ -122,16 +122,16 @@ static struct stm32l4_priv_s g_spirit = /* Reset the Spirit 1 part */ -static int stm32l4_reset(const struct spirit_lower_s *lower) +static int stm32_reset(const struct spirit_lower_s *lower) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); /* Reset pulse */ - stm32l4_gpiowrite(priv->sdncfg, true); - stm32l4_gpiowrite(priv->sdncfg, false); + stm32_gpiowrite(priv->sdncfg, true); + stm32_gpiowrite(priv->sdncfg, false); /* Wait minimum 1.5 ms to allow Spirit a proper boot-up sequence */ @@ -145,15 +145,15 @@ static int stm32l4_reset(const struct spirit_lower_s *lower) * interrupts should be configured on both rising and falling edges * so that contact and loss-of-contact events can be detected. * - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); @@ -164,10 +164,10 @@ static int stm32l4_attach_irq(const struct spirit_lower_s *lower, return OK; } -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; /* The caller should not attempt to enable interrupts if the handler * has not yet been 'attached' @@ -183,20 +183,20 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, { /* Enable interrupts on falling edge (active low) */ - stm32l4_gpiosetevent(priv->intcfg, false, true, false, + stm32_gpiosetevent(priv->intcfg, false, true, false, priv->handler, priv->arg); } else { /* Disable interrupts */ - stm32l4_gpiosetevent(priv->intcfg, false, false, false, + stm32_gpiosetevent(priv->intcfg, false, false, false, NULL, NULL); } } /**************************************************************************** - * Name: stm32l4_spirit_devsetup + * Name: stm32_spirit_devsetup * * Description: * Initialize one the Spirit device @@ -207,7 +207,7 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, * ****************************************************************************/ -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) +static int stm32_spirit_devsetup(struct stm32_priv_s *priv) { struct spi_dev_s *spi; int ret; @@ -216,12 +216,12 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * powers down the Spirit. */ - stm32l4_configgpio(priv->intcfg); - stm32l4_configgpio(priv->sdncfg); + stm32_configgpio(priv->intcfg); + stm32_configgpio(priv->sdncfg); /* Initialize the SPI bus and get an instance of the SPI interface */ - spi = stm32l4_spibus_initialize(priv->spidev); + spi = stm32_spibus_initialize(priv->spidev); if (spi == NULL) { wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); @@ -245,7 +245,7 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -256,13 +256,13 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * ****************************************************************************/ -int stm32l4_spirit_initialize(void) +int stm32_spirit_initialize(void) { int ret; wlinfo("Configuring Spirit\n"); - ret = stm32l4_spirit_devsetup(&g_spirit); + ret = stm32_spirit_devsetup(&g_spirit); if (ret < 0) { wlerr("ERROR: Failed to initialize Spirit: %d\n", ret); diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 01d23175df7c7..ecfabfc0424d3 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -52,12 +52,12 @@ ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void) +int stm32_timer_driver_setup(void) { int ret = OK; #ifdef CONFIG_STM32_TIM1 - ret = stm32l4_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", @@ -66,7 +66,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM2 - ret = stm32l4_timer_initialize("/dev/timer1", 2); + ret = stm32_timer_initialize("/dev/timer1", 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer1: %d\n", @@ -75,7 +75,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM3 - ret = stm32l4_timer_initialize("/dev/timer2", 3); + ret = stm32_timer_initialize("/dev/timer2", 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM3 at /dev/timer2: %d\n", @@ -84,7 +84,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM4 - ret = stm32l4_timer_initialize("/dev/timer3", 4); + ret = stm32_timer_initialize("/dev/timer3", 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer3: %d\n", @@ -93,7 +93,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM5 - ret = stm32l4_timer_initialize("/dev/timer4", 5); + ret = stm32_timer_initialize("/dev/timer4", 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM5 at /dev/timer4: %d\n", @@ -102,7 +102,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM6 - ret = stm32l4_timer_initialize("/dev/timer5", 6); + ret = stm32_timer_initialize("/dev/timer5", 6); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM6 at /dev/timer5: %d\n", @@ -111,7 +111,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM7 - ret = stm32l4_timer_initialize("/dev/timer6", 7); + ret = stm32_timer_initialize("/dev/timer6", 7); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM7 at /dev/timer6: %d\n", @@ -120,7 +120,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM8 - ret = stm32l4_timer_initialize("/dev/timer7", 8); + ret = stm32_timer_initialize("/dev/timer7", 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM8 at /dev/timer7: %d\n", @@ -129,7 +129,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM15 - ret = stm32l4_timer_initialize("/dev/timer8", 15); + ret = stm32_timer_initialize("/dev/timer8", 15); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM15 at /dev/time8: %d\n", @@ -138,7 +138,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM16 - ret = stm32l4_timer_initialize("/dev/timer9", 16); + ret = stm32_timer_initialize("/dev/timer9", 16); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM16 at /dev/time9: %d\n", @@ -147,7 +147,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32_TIM17 - ret = stm32l4_timer_initialize("/dev/timer10", 17); + ret = stm32_timer_initialize("/dev/timer10", 17); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM17 at /dev/time10: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c index e431ebdcee9b6..d4bf80c9c5f30 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c @@ -46,8 +46,8 @@ uint32_t board_userled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED1); - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); return BOARD_NLEDS; } @@ -59,11 +59,11 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LED1) { - stm32l4_gpiowrite(GPIO_LED1, ledon); + stm32_gpiowrite(GPIO_LED1, ledon); } else if (led == BOARD_LED2) { - stm32l4_gpiowrite(GPIO_LED2, ledon); + stm32_gpiowrite(GPIO_LED2, ledon); } } @@ -73,8 +73,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); - stm32l4_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); + stm32_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); } #endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index c363e2dea46a7..fc6615cd13082 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -294,7 +294,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -304,7 +304,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h index 6a9a4cf3bc848..766d7e6528a73 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h @@ -133,7 +133,7 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -141,11 +141,11 @@ int stm32_bringup(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of initialized @@ -153,30 +153,30 @@ int stm32l4_gpio_initialize(void); * ****************************************************************************/ -void stm32l4_spiregister(void); +void stm32_spiregister(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -184,11 +184,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -196,11 +196,11 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. @@ -208,7 +208,7 @@ int stm32l4_adc_setup(void); ****************************************************************************/ #ifdef CONFIG_DAC -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); #endif /**************************************************************************** @@ -284,7 +284,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -292,7 +292,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif #endif /* __BOARDS_ARM_STM32_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c index 95e7093287782..d1dfcba1bf41e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c @@ -98,14 +98,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -115,12 +115,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c index a1ebdaabbdcdd..6c3c1d65e23d4 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c @@ -79,7 +79,7 @@ int stm32_at45dbinitialize(int minor) finfo("INFO: Initializing AT45DB\n"); - spi = stm32l4_spibus_initialize(AT45DB_SPI_PORT); + spi = stm32_spibus_initialize(AT45DB_SPI_PORT); if (spi == NULL) { ferr("ERROR: Failed to initialize SPI port %d\n", AT45DB_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c index 1631395cab793..c2f3cff13fb56 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD3, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD3, false); } } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c index cdacf2a9a702a..a370c0e67b145 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c @@ -50,7 +50,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -60,7 +60,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -69,21 +69,21 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ defined(CONFIG_STM32_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c index be01e6f21d326..48ac6fff613b7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include @@ -119,7 +119,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -130,7 +130,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -154,7 +154,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_I2C1 /* Get the I2C lower half instance */ - i2c1 = stm32l4_i2cbus_initialize(1); + i2c1 = stm32_i2cbus_initialize(1); if (i2c1 == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -174,7 +174,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_I2C3 /* Get the I2C lower half instance */ - i2c3 = stm32l4_i2cbus_initialize(3); + i2c3 = stm32_i2cbus_initialize(3); if (i2c3 == NULL) { i2cerr("ERROR: Initialize I2C3: %d\n", ret); @@ -192,7 +192,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SPI_DRIVER - stm32l4_spiregister(); + stm32_spiregister(); /* If called it during board_init, * registering failed due to heap doesn't be initialized yet. */ @@ -213,30 +213,30 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif #ifdef CONFIG_STM32_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif #ifdef CONFIG_STM32_DAC /* Initialize DAC and register the DAC driver. */ - ret = stm32l4_dac_setup(); + ret = stm32_dac_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_dac_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); } #endif @@ -300,7 +300,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -311,7 +311,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -322,7 +322,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -333,7 +333,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -344,7 +344,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -355,7 +355,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c index 75a869a444387..fd48f855ab3b5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c @@ -50,10 +50,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -62,7 +62,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c index 1605fb2049a7a..48cabb1d468bd 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_DAC7571) @@ -80,12 +80,12 @@ int stm32_dac7571initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -110,7 +110,7 @@ int stm32_dac7571initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c index 2bbea61fa78a6..140d8488f45b3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c @@ -104,7 +104,7 @@ struct dac_wgen_s static struct dac_wgen_s g_dac_wgen = { .dac = NULL, - .dac_dmabuffer = stm32l4_dac1_dmabuffer, + .dac_dmabuffer = stm32_dac1_dmabuffer, .samples = CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES, .waveform_freq = ((float)CONFIG_NUCLEOL432KC_DAC_WGEN_FREQ) }; @@ -199,7 +199,7 @@ int dac_wgen_setup(struct dac_wgen_s *dac_wgen) int ret = OK; - dac = stm32l4_dacinitialize(0); + dac = stm32_dacinitialize(0); if (dac == NULL) { syslog(LOG_ERR, "Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c index 6b762ea218626..9164fd1db317f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c @@ -151,7 +151,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } #endif @@ -165,7 +165,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -177,7 +177,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } #endif @@ -205,7 +205,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -219,7 +219,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -240,7 +240,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -248,7 +248,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) else { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -268,7 +268,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int i; int pincount = 0; @@ -285,7 +285,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -303,8 +303,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -322,7 +322,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c index 9c25b275d4a0a..89946981ecefe 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA219) @@ -84,12 +84,12 @@ int stm32_ina219initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina219initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c index 6354edb65e418..49be6a531d5b3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA226) @@ -84,12 +84,12 @@ int stm32_ina226initialize(const char *devpath) /* Configure A4(PA5) and A5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_A4); - stm32l4_configgpio(GPIO_I2C1_A5); + stm32_configgpio(GPIO_I2C1_A4); + stm32_configgpio(GPIO_I2C1_A5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina226initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c index 4912996902160..6997424c27566 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM interface + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ /* PWM @@ -88,7 +88,7 @@ int stm32l4_pwm_setup(void) */ #if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -106,7 +106,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -124,7 +124,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -142,7 +142,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -160,7 +160,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -178,7 +178,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c index 1a02e18bb8cf8..311955dee90bb 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index f887957ec7dfc..f52a6b7bbbfb2 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l432kc.h" @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of @@ -68,7 +68,7 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void stm32l4_spiregister(void) +void stm32_spiregister(void) { #ifdef CONFIG_STM32_SPI1 int ret = spi_register(g_spi1, 1); @@ -88,7 +88,7 @@ void stm32l4_spiregister(void) } /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L432KC @@ -96,12 +96,12 @@ void stm32l4_spiregister(void) * ****************************************************************************/ -void stm32l4_spiinitialize(void) +void stm32_spiinitialize(void) { #ifdef CONFIG_STM32_SPI1 /* Configure SPI1-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -114,14 +114,14 @@ void stm32l4_spiinitialize(void) /* Setup CS, EN & IRQ line IOs */ #ifdef CONFIG_MTD_AT45DB - stm32l4_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ + stm32_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ #endif #endif #ifdef CONFIG_STM32_SPI2 /* Configure SPI2-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 2\n"); @@ -136,19 +136,19 @@ void stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2select and stm32l4_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32l4_spi1/2select and stm32l4_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including * up_spiinitialize()) are provided by common STM32 logic. To use this * common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2select() and stm32l4_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. @@ -162,7 +162,7 @@ void stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %08X CS: %s\n", (int)devid, @@ -171,33 +171,33 @@ void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, #ifdef CONFIG_MTD_AT45DB if (devid == SPIDEV_FLASH(0)) { - stm32l4_gpiowrite(AT45DB_SPI1_CS, !selected); + stm32_gpiowrite(AT45DB_SPI1_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -221,14 +221,14 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index c0591b8cb3b5f..c1842f4e555f5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -138,9 +138,9 @@ struct spwm_s { - struct stm32l4_pwm_dev_s *pwm; + struct stm32_pwm_dev_s *pwm; #ifdef CONFIG_NUCLEOL432KC_SPWM_USE_TIM1 - struct stm32l4_tim_dev_s *tim; + struct stm32_tim_dev_s *tim; #endif float waveform[SAMPLES_NUM]; /* Waveform samples */ float phase_step; /* Waveform phase step */ @@ -314,8 +314,8 @@ static int spwm_stop(struct spwm_s *spwm) static void tim6_handler(void) { struct spwm_s *spwm = &g_spwm; - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_pwm_dev_s *pwm = spwm->pwm; + struct stm32_tim_dev_s *tim = spwm->tim; uint8_t i = 0; for (i = 0; i < spwm->phases; i += 1) @@ -345,13 +345,13 @@ static void tim6_handler(void) static int spwm_tim6_setup(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = NULL; + struct stm32_tim_dev_s *tim = NULL; uint64_t freq = 0; int ret = OK; /* Get TIM6 interface */ - tim = stm32l4_tim_init(6); + tim = stm32_tim_init(6); if (tim == NULL) { printf("ERROR: Failed to get TIM6 interface\n"); @@ -403,7 +403,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) static int spwm_tim6_start(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Enable the timer interrupt at the NVIC and at TIM6 */ @@ -419,7 +419,7 @@ static int spwm_tim6_start(struct spwm_s *spwm) static int spwm_tim6_stop(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Disable the timer interrupt at the NVIC and at TIM6 */ @@ -435,12 +435,12 @@ static int spwm_tim6_stop(struct spwm_s *spwm) static int spwm_tim1_setup(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = NULL; + struct stm32_pwm_dev_s *pwm = NULL; int ret = OK; /* Get TIM1 PWM interface */ - pwm = (struct stm32l4_pwm_dev_s *)stm32l4_pwminitialize(1); + pwm = (struct stm32_pwm_dev_s *)stm32_pwminitialize(1); if (pwm == NULL) { printf("ERROR: Failed to get TIM1 PWM interface\n"); @@ -486,7 +486,7 @@ static int spwm_tim1_setup(struct spwm_s *spwm) static int spwm_tim1_start(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; @@ -514,7 +514,7 @@ static int spwm_tim1_start(struct spwm_s *spwm) static int spwm_tim1_stop(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c index d0b9d26524b23..8d7ac77627f2f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c index bf21e6c4ea1c9..848add8c3b7e2 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c index c80bd6b70042c..8009c8346e5a8 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD3) { - stm32l4_gpiowrite(GPIO_LD3, ledon); + stm32_gpiowrite(GPIO_LD3, ledon); } } @@ -176,7 +176,7 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); + stm32_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c index f717e3049652d..010e9af5d506a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c @@ -98,7 +98,7 @@ static void zcross_enable(const struct zc_lowerhalf_s *lower, g_zcrossarg = arg; } - stm32l4_gpiosetevent(GPIO_ZEROCROSS, rising, falling, + stm32_gpiosetevent(GPIO_ZEROCROSS, rising, falling, true, zcross_interrupt, NULL); leave_critical_section(flags); @@ -120,7 +120,7 @@ static void zcross_disable(void) flags = enter_critical_section(); - stm32l4_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); + stm32_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); leave_critical_section(flags); @@ -164,10 +164,10 @@ static int zcross_interrupt(int irq, void *context, void *arg) int stm32_zerocross_initialize(void) { /* Configure the GPIO pin as input. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32l4_gpiosetevent(). + * interrupting pins since it will also be done by stm32_gpiosetevent(). */ - stm32l4_configgpio(GPIO_ZEROCROSS); + stm32_configgpio(GPIO_ZEROCROSS); /* Make sure that all interrupts are disabled */ diff --git a/boards/arm/stm32l4/nucleo-l452re/include/board.h b/boards/arm/stm32l4/nucleo-l452re/include/board.h index 2e9e05f520362..007a934ca53fb 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/board.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/board.h @@ -257,7 +257,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -267,7 +267,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 21b436eabb040..f3c2242f39b21 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -118,36 +118,36 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_bringup diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c index bf18e9647f2e4..cfbe5dedc47e0 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c @@ -147,14 +147,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct file filestruct; @@ -277,10 +277,10 @@ int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; @@ -296,15 +296,15 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c index 86102cae00a88..3abec894bc54d 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c @@ -53,7 +53,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -64,7 +64,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -76,7 +76,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c index 94bf0983a8ca9..0031ce09d0548 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c @@ -40,7 +40,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -50,7 +50,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c index 59e37aff5d008..0dcd2af919135 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c @@ -102,7 +102,7 @@ int stm32_bringup(void) #ifdef HAVE_I2C_DRIVER /* Get the I2C lower half instance */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -122,13 +122,13 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); + stm32_adc_setup(); #endif UNUSED(ret); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c index 261d03e6f292b..18ea50c5ace2e 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -75,7 +75,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -108,7 +108,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c index 318e88261d24c..91caf4947c310 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c @@ -48,10 +48,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -60,7 +60,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index 17c3483971a0a..ab1e9fac9a653 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -34,7 +34,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l452re.h" @@ -60,33 +60,33 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { #ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif #ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -95,19 +95,19 @@ void weak_function stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -121,7 +121,7 @@ void weak_function stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -130,47 +130,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -194,21 +194,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c index 6911949d1111a..8344890d1ab10 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c @@ -155,7 +155,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -167,7 +167,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -177,15 +177,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h index ac950b67fae32..aa3e277de64e1 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h @@ -293,27 +293,27 @@ extern struct sdio_dev_s *g_sdio; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -322,11 +322,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_can_setup -- DisruptiveNL + * Name: stm32_can_setup -- DisruptiveNL * * Description: * Initialize CAN and register the CAN device. @@ -335,11 +335,11 @@ int stm32l4_gpio_initialize(void); ****************************************************************************/ #ifdef CONFIG_CAN -int stm32l4_can_setup(void); +int stm32_can_setup(void); #endif /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -347,11 +347,11 @@ int stm32l4_can_setup(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -359,7 +359,7 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** @@ -375,7 +375,7 @@ int board_ajoy_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initializes SPI-based SD card @@ -383,7 +383,7 @@ int board_ajoy_initialize(void); ****************************************************************************/ #ifdef CONFIG_MMCSD_SPI -int stm32l4_mmcsd_initialize(int minor); +int stm32_mmcsd_initialize(int minor); #endif /**************************************************************************** @@ -399,7 +399,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -407,11 +407,11 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver @@ -419,7 +419,7 @@ int stm32l4_qencoder_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_WL_CC1101 -int stm32l4_cc1101_initialize(void); +int stm32_cc1101_initialize(void); #endif /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 138c316678952..d3e99dada1ca7 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -103,14 +103,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -120,12 +120,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index 4b7656d5f2560..96fc9df7c48e6 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -298,7 +298,7 @@ ajoy_buttons(const struct ajoy_lowerhalf_s *lower) * button is pressed. */ - if (!stm32l4_gpioread(g_joygpio[i])) + if (!stm32_gpioread(g_joygpio[i])) { ret |= (1 << i); } @@ -368,7 +368,7 @@ static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32l4_gpiosetevent(g_joygpio[i], rising, falling, + stm32_gpiosetevent(g_joygpio[i], rising, falling, true, ajoy_interrupt, NULL); } } @@ -395,7 +395,7 @@ static void ajoy_disable(void) flags = up_irq_save(); for (i = 0; i < AJOY_NGPIOS; i++) { - stm32l4_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } up_irq_restore(flags); @@ -461,14 +461,14 @@ int board_ajoy_initialize(void) /* Configure the GPIO pins as interrupting inputs. NOTE: This is * unnecessary for interrupting pins since it will also be done by - * stm32l4_gpiosetevent(). + * stm32_gpiosetevent(). */ for (i = 0; i < AJOY_NGPIOS; i++) { /* Configure the PIO as an input */ - stm32l4_configgpio(g_joygpio[i]); + stm32_configgpio(g_joygpio[i]); } /* Register the joystick device as /dev/ajoy0 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c index 01913bd594e29..12bb3c4aedc8b 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c @@ -46,7 +46,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -83,7 +83,7 @@ int stm32_as726xinitialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(AS726X_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(AS726X_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c index b3af9c5a740ae..fd2c0f744c82c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c index d6fb30862285f..208b8c59a337d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c @@ -32,7 +32,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -65,7 +65,7 @@ int stm32_bmp180initialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(BMP180_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(BMP180_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c index b5f07c0a8f03c..55b74b50d38c8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_bmp280.h" @@ -89,7 +89,7 @@ int board_bmp280_initialize(int devno, int busno) /* Initialize BMP280 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index bdf6ddf8a6f64..93bede4772f40 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -61,20 +61,20 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c index 9f43e3e43a6fa..4b229423773ad 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include @@ -95,7 +95,7 @@ static void stm32_i2c_register(int bus) struct i2c_master_s *i2c; int ret; - i2c = stm32l4_i2cbus_initialize(bus); + i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); @@ -107,7 +107,7 @@ static void stm32_i2c_register(int bus) { syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); } } } @@ -178,7 +178,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -261,28 +261,28 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif #ifdef CONFIG_CAN - ret = stm32l4_can_setup(); + ret = stm32_can_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_can_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); return ret; } #endif @@ -290,7 +290,7 @@ int stm32_bringup(void) /* Initialize MMC and register the MMC driver. */ #ifdef HAVE_MMCSD_SPI - ret = stm32l4_mmcsd_initialize(MMCSD_MINOR); + ret = stm32_mmcsd_initialize(MMCSD_MINOR); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); @@ -329,7 +329,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -340,7 +340,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -351,7 +351,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -362,7 +362,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -373,7 +373,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -384,7 +384,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -395,7 +395,7 @@ int stm32_bringup(void) #endif /* CONFIG_SENSORS_QENCODER */ #ifdef CONFIG_SENSORS_HTS221 - ret = stm32l4_hts221_initialize("/dev/hts221"); + ret = stm32_hts221_initialize("/dev/hts221"); if (ret < 0) { serr("ERROR: Failed to initialize HTC221 driver: %d\n", ret); @@ -403,7 +403,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM6DSL - ret = stm32l4_lsm6dsl_initialize("/dev/lsm6dsl0"); + ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM6DSL driver: %d\n", ret); @@ -411,7 +411,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM303AGR - ret = stm32l4_lsm303agr_initialize("/dev/lsm303mag0"); + ret = stm32_lsm303agr_initialize("/dev/lsm303mag0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM303AGR driver: %d\n", ret); @@ -419,7 +419,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -430,10 +430,10 @@ int stm32_bringup(void) #ifdef CONFIG_WL_CC1101 /* Initialize and register the cc1101 radio */ - ret = stm32l4_cc1101_initialize(); + ret = stm32_cc1101_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_cc1101_initialize failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_cc1101_initialize failed: %d\n", ret); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c index b44a8deaedc37..efcfb4efe31ce 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -72,7 +72,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c index 8cea1d5c3e0e0..117aa61f8f74c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c @@ -56,22 +56,22 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_can_setup + * Name: stm32_can_setup * * Description: * Initialize CAN and register the CAN device * ****************************************************************************/ -int stm32l4_can_setup(void) +int stm32_can_setup(void) { #ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; - /* Call stm32l4can_initialize() to get an instance of the CAN interface */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - can = stm32l4can_initialize(CAN_PORT); + can = stm32_caninitialize(CAN_PORT); if (can == NULL) { canerr("ERROR: Failed to get CAN interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c index 6a29402d6dfe2..c1bfb8febdb10 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c @@ -36,7 +36,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_WL_CC1101 @@ -54,7 +54,7 @@ static void cc1101_wait(struct cc1101_dev_s *dev, uint32_t pin) { - while (stm32l4_gpioread(pin) == true) + while (stm32_gpioread(pin) == true) { } } @@ -70,11 +70,11 @@ static void cc1101_irq(struct cc1101_dev_s *dev, bool enable) { if (enable) { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); + stm32_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); } else { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); + stm32_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); } } @@ -94,19 +94,19 @@ static void cc1101_pwr(struct cc1101_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver * ****************************************************************************/ -int stm32l4_cc1101_initialize(void) +int stm32_cc1101_initialize(void) { struct spi_dev_s *spi = NULL; struct cc1101_dev_s *dev = NULL; - spi = stm32l4_spibus_initialize(CONFIG_CC1101_SPIDEV); + spi = stm32_spibus_initialize(CONFIG_CC1101_SPIDEV); if (spi == NULL) { ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_CC1101_SPIDEV); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c index f772ef0a32b25..473fc52a0b6aa 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c @@ -40,7 +40,7 @@ #include "chip.h" -#include +#include #include "nucleo-l476rg.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -160,7 +160,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } @@ -173,7 +173,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -186,7 +186,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } @@ -199,7 +199,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -213,7 +213,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -234,7 +234,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -243,7 +243,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -255,14 +255,14 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int pincount = 0; int i; @@ -279,7 +279,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -297,8 +297,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -316,7 +316,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c index f59da58d0ad48..10b19e930042f 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -48,13 +48,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm303agr_initialize + * Name: stm32_lsm303agr_initialize * * Description: * Initialize I2C-based LSM303AGR. ****************************************************************************/ -int stm32l4_lsm303agr_initialize(char *devpath) +int stm32_lsm303agr_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; @@ -62,7 +62,7 @@ int stm32l4_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); #if defined(CONFIG_STM32_I2C1) - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c index 88465db68455e..bda0f7bf9dcdb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -48,13 +48,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm6dsl_initialize + * Name: stm32_lsm6dsl_initialize * * Description: * Initialize I2C-based LSM6DSL. ****************************************************************************/ -int stm32l4_lsm6dsl_initialize(char *devpath) +int stm32_lsm6dsl_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; @@ -63,10 +63,10 @@ int stm32l4_lsm6dsl_initialize(char *devpath) /* Configure the GPIO interrupt */ - stm32l4_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ + stm32_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ #if defined(CONFIG_STM32_I2C1) - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c index cd5252a20031a..3211666f237fd 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_mpu9250.h" @@ -94,7 +94,7 @@ int board_mpu9250_initialize(int devno, int busno) /* Initialize MPU9250 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { /* Then try to register the IMU sensor in I2Cx */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c index eb9316cb51fef..ab30d3c77a87a 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c @@ -72,12 +72,12 @@ int board_lcd_initialize(void) { /* Configure the GPIO pins */ - stm32l4_configgpio(STM32_LCD_RST); - stm32l4_configgpio(STM32_LCD_CD); - stm32l4_gpiowrite(STM32_LCD_RST, 1); - stm32l4_gpiowrite(STM32_LCD_CD, 1); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_CD); + stm32_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_CD, 1); - g_spidev = stm32l4_spibus_initialize(LCD_SPI_PORTNO); + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); if (!g_spidev) { @@ -85,9 +85,9 @@ int board_lcd_initialize(void) return -ENODEV; } - stm32l4_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(10); - stm32l4_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index 842185954dd34..8cb546fc69d0c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM + /* Call stm32_pwminitialize() to get an instance of the PWM * interface */ @@ -89,7 +89,7 @@ int stm32l4_pwm_setup(void) */ #if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -107,7 +107,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -125,7 +125,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM3_PWM) - pwm = stm32l4_pwminitialize(3); + pwm = stm32_pwminitialize(3); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -143,7 +143,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM4_PWM) - pwm = stm32l4_pwminitialize(4); + pwm = stm32_pwminitialize(4); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -161,7 +161,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM5_PWM) - pwm = stm32l4_pwminitialize(5); + pwm = stm32_pwminitialize(5); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -179,7 +179,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM8_PWM) - pwm = stm32l4_pwminitialize(8); + pwm = stm32_pwminitialize(8); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -197,7 +197,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -215,7 +215,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -233,7 +233,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_TIM17_PWM) - pwm = stm32l4_pwminitialize(17); + pwm = stm32_pwminitialize(17); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -251,7 +251,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -269,7 +269,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c index 9e366385cf07f..a87fc8c891656 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index 1b681ad9234d2..5903f519b5c51 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l476rg.h" @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG @@ -68,57 +68,57 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { #ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD_SPI - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #ifdef CONFIG_LCD_PCD8544 - stm32l4_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ + stm32_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ #endif #endif #ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); #ifdef CONFIG_WL_CC1101 /* Setup CS, IRQ(gdo2) line IOs */ - stm32l4_configgpio(GPIO_CC1101_PWR); - stm32l4_configgpio(GPIO_CC1101_CS); - stm32l4_configgpio(GPIO_CC1101_GDO2); + stm32_configgpio(GPIO_CC1101_PWR); + stm32_configgpio(GPIO_CC1101_CS); + stm32_configgpio(GPIO_CC1101_GDO2); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your * board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -132,7 +132,7 @@ void weak_function stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -141,19 +141,19 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD_SPI if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) { - stm32l4_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { uint8_t status = 0; @@ -169,7 +169,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -178,33 +178,33 @@ void stm32l4_spi2select(struct spi_dev_s *dev, #ifdef CONFIG_WL_CC1101 if (devid == SPIDEV_WIRELESS(5)) { - stm32l4_gpiowrite(GPIO_CC1101_CS, !selected); + stm32_gpiowrite(GPIO_CC1101_CS, !selected); } #endif } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -228,7 +228,7 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) @@ -237,7 +237,7 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - stm32l4_gpiowrite(STM32_LCD_CD, !cmd); + stm32_gpiowrite(STM32_LCD_CD, !cmd); return OK; } @@ -248,14 +248,14 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c index 73192327542db..fe006549d8153 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include "stm32l4_spi.h" /**************************************************************************** @@ -68,14 +68,14 @@ static const int SD_SLOT_NO = 0; /* There is only one SD slot */ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spi1register + * Name: stm32_spi1register * * Description: * Registers media change callback * ****************************************************************************/ -int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) { spiinfo("INFO: Registering spi1 device\n"); @@ -83,21 +83,21 @@ int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, } /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initialize SPI-based SD card and card detect thread. * ****************************************************************************/ -int stm32l4_mmcsd_initialize(int minor) +int stm32_mmcsd_initialize(int minor) { struct spi_dev_s *spi; int rv; mcinfo("INFO: Initializing mmcsd card\n"); - spi = stm32l4_spibus_initialize(SD_SPI_PORT); + spi = stm32_spibus_initialize(SD_SPI_PORT); if (spi == NULL) { mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c index a0c347aea59c5..7ae7885ca8bfe 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c index 278b51f7c2ae3..15536f8784beb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c index 92c96b1dc0094..34384cb9dc323 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -176,15 +176,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 76a55fa31571e..e753e7f0952cc 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -655,7 +655,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -665,7 +665,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index d13e24b1a7f04..e0ba48ff0a776 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -158,7 +158,7 @@ int stm32_adc_setup(void) { if (g_pinlist_adc1[i] != 0) { - stm32l4_configgpio(g_pinlist_adc1[i]); + stm32_configgpio(g_pinlist_adc1[i]); } } #endif @@ -168,7 +168,7 @@ int stm32_adc_setup(void) { if (g_pinlist_adc2[i] != 0) { - stm32l4_configgpio(g_pinlist_adc2[i]); + stm32_configgpio(g_pinlist_adc2[i]); } } #endif @@ -178,17 +178,17 @@ int stm32_adc_setup(void) { if (g_pinlist_adc3[i] != 0) { - stm32l4_configgpio(g_pinlist_adc3[i]); + stm32_configgpio(g_pinlist_adc3[i]); } } #endif - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ #ifdef CONFIG_STM32_ADC1 - adc = stm32l4_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -206,7 +206,7 @@ int stm32_adc_setup(void) #endif #ifdef CONFIG_STM32_ADC2 - adc = stm32l4_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -224,7 +224,7 @@ int stm32_adc_setup(void) #endif #ifdef CONFIG_STM32_ADC3 - adc = stm32l4_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c index f0d57f250feff..1c728a838d81a 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c @@ -61,7 +61,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l4_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -80,7 +80,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l4_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c index f6d407ce38ecf..4e59599a7e01a 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c @@ -46,7 +46,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -56,7 +56,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c index 4d22994d3bac8..b9133caa56d83 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c @@ -148,7 +148,7 @@ int stm32_bringup(void) /* Initialize the SDIO block driver */ - ret = stm32l4_sdio_initialize(); + ret = stm32_sdio_initialize(); if (ret != OK) { ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); @@ -162,16 +162,16 @@ int stm32_bringup(void) /* REVISIT: this is ugly! */ #if defined(CONFIG_STM32_I2C1) - i2c1 = stm32l4_i2cbus_initialize(1); + i2c1 = stm32_i2cbus_initialize(1); #endif #if defined(CONFIG_STM32_I2C2) - i2c2 = stm32l4_i2cbus_initialize(2); + i2c2 = stm32_i2cbus_initialize(2); #endif #if defined(CONFIG_STM32_I2C3) - i2c3 = stm32l4_i2cbus_initialize(3); + i2c3 = stm32_i2cbus_initialize(3); #endif #if defined(CONFIG_STM32_I2C4) - i2c4 = stm32l4_i2cbus_initialize(4); + i2c4 = stm32_i2cbus_initialize(4); #endif #ifdef CONFIG_I2C_DRIVER #if defined(CONFIG_STM32_I2C1) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c index 0238265167266..16d7a80a1cc4c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -66,7 +66,7 @@ uint32_t board_button_initialize(void) uint32_t board_buttons(void) { - return stm32l4_gpioread(GPIO_BTN_USER) ? 1 : 0; + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; } /**************************************************************************** @@ -98,7 +98,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c index adbda65eeab25..573f956fc5091 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c @@ -66,7 +66,7 @@ int stm32_dac_setup(void) int ret; #ifdef CONFIG_STM32_DAC1 - g_dac1 = stm32l4_dacinitialize(0); + g_dac1 = stm32_dacinitialize(0); if (g_dac1 == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); @@ -82,7 +82,7 @@ int stm32_dac_setup(void) #endif #ifdef CONFIG_STM32_DAC2 - g_dac2 = stm32l4_dacinitialize(1); + g_dac2 = stm32_dacinitialize(1); if (g_dac2 == NULL) { aerr("ERROR: Failed to get DAC2 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c index 732ac134a48f3..ab8ee9c843056 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c @@ -89,7 +89,7 @@ int stm32_dfsdm_setup(void) */ #ifdef CONFIG_STM32_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -105,7 +105,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -121,7 +121,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -137,7 +137,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c index 30d768cbc0fa2..9a7df66b11e84 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c @@ -76,11 +76,11 @@ static bool g_sd_inserted; ****************************************************************************/ #ifdef HAVE_NCD -static int stm32l4_ncd_interrupt(int irq, void *context) +static int stm32_ncd_interrupt(int irq, void *context) { bool present; - present = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + present = !stm32_gpioread(GPIO_SDMMC1_NCD); if (g_sdio_dev && present != g_sd_inserted) { sdio_mediachange(g_sdio_dev, present); @@ -103,19 +103,19 @@ static int stm32l4_ncd_interrupt(int irq, void *context) * ****************************************************************************/ -int stm32l4_sdio_initialize(void) +int stm32_sdio_initialize(void) { int ret; #ifdef HAVE_NCD /* Configure the card detect GPIO */ - stm32l4_configgpio(GPIO_SDMMC1_NCD); + stm32_configgpio(GPIO_SDMMC1_NCD); /* Register an interrupt handler for the card detect pin */ - stm32l4_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, - stm32l4_ncd_interrupt, NULL); + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ @@ -147,7 +147,7 @@ int stm32l4_sdio_initialize(void) #ifdef HAVE_NCD /* Use SD card detect pin to check if a card is g_sd_inserted */ - g_sd_inserted = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); finfo("Card detect : %d\n", g_sd_inserted); sdio_mediachange(g_sdio_dev, g_sd_inserted); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 031e36dd9fc0a..f39ee47e68997 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi1gpio[i] != 0) { - stm32l4_configgpio(g_spi1gpio[i]); + stm32_configgpio(g_spi1gpio[i]); } } #endif @@ -216,7 +216,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi2gpio[i] != 0) { - stm32l4_configgpio(g_spi2gpio[i]); + stm32_configgpio(g_spi2gpio[i]); } } #endif @@ -226,7 +226,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi3gpio[i] != 0) { - stm32l4_configgpio(g_spi3gpio[i]); + stm32_configgpio(g_spi3gpio[i]); } } #endif @@ -269,7 +269,7 @@ void stm32_spi1select(struct spi_dev_s *dev, if (g_spi1gpio[index] != 0) { - stm32l4_gpiowrite(g_spi1gpio[index], !selected); + stm32_gpiowrite(g_spi1gpio[index], !selected); } } @@ -290,7 +290,7 @@ void stm32_spi2select(struct spi_dev_s *dev, if (g_spi2gpio[index] != 0) { - stm32l4_gpiowrite(g_spi2gpio[index], !selected); + stm32_gpiowrite(g_spi2gpio[index], !selected); } } @@ -311,7 +311,7 @@ void stm32_spi3select(struct spi_dev_s *dev, if (g_spi3gpio[index] != 0) { - stm32l4_gpiowrite(g_spi3gpio[index], !selected); + stm32_gpiowrite(g_spi3gpio[index], !selected); } } @@ -393,7 +393,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) - spi2 = stm32l4_spibus_initialize(2); + spi2 = stm32_spibus_initialize(2); if (!spi2) { @@ -410,7 +410,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) - spi3 = stm32l4_spibus_initialize(3); + spi3 = stm32_spibus_initialize(3); if (!spi3) { diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c index 277f8527b9a7e..13d47f603d6c3 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index 77619c6b3c358..a499ca891ce06 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -139,9 +139,9 @@ void stm32_usbinitialize(void) */ #ifdef CONFIG_STM32_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } @@ -220,7 +220,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -273,7 +273,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) /* Set the Power Switch by driving the active low enable pin */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, !enable); + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); } #endif @@ -297,7 +297,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST int stm32_setup_overcurrent(xcpt_t handler, void *arg) { - return stm32l4_gpiosetevent(GPIO_OTGFS_OVER, + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); } #endif @@ -314,7 +314,7 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c index 578fa289a31b2..a981d49c6fbcb 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l4_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -120,7 +120,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h index 79a708e8ad23f..68917c358af35 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h @@ -72,7 +72,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture specific initialization @@ -82,10 +82,10 @@ * ****************************************************************************/ -int stm32l4_bringup(void); +int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called from stm32_usbinitialize very early in initialization to setup @@ -94,7 +94,7 @@ int stm32l4_bringup(void); ****************************************************************************/ #ifdef CONFIG_STM32_OTGFS -void weak_function stm32l4_usbinitialize(void); +void weak_function stm32_usbinitialize(void); #endif #endif /* __BOARDS_ARM_STM32_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c index 577914d757f4f..ea26a99180087 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "steval-stlcs01v1.h" @@ -47,7 +47,7 @@ void board_autoled_initialize(void) { /* Configure LD1 GPIO for output */ - stm32l4_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD1); } /**************************************************************************** @@ -58,7 +58,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD1, true); } } @@ -70,6 +70,6 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD1, false); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 3c9239dbe7f7b..5908bb4deac4e 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,10 +52,10 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32l4_usbinitialize() has been + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ @@ -63,17 +63,17 @@ void stm32l4_board_initialize(void) #ifdef CONFIG_STM32_OTGFS /* Enable Vddusb - mandatory to use the USB OTG FS peripheral */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); - if (stm32l4_usbinitialize) + if (stm32_usbinitialize) { - stm32l4_usbinitialize(); + stm32_usbinitialize(); } #endif /* Enable Vddio2 - mandatory to use the PG2 - PG15 I/Os. */ - stm32l4_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); /* Configure on-board LEDs if LED support has been selected. */ @@ -101,6 +101,6 @@ void board_late_initialize(void) { /* Perform board-specific initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c index d885272feb37a..108b28ef4905e 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture-specific initialization @@ -46,7 +46,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index 506e5774dfc00..87f30cd3ee766 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -35,7 +35,7 @@ #include #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "steval-stlcs01v1.h" @@ -65,15 +65,15 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -81,10 +81,10 @@ void stm32l4_usbinitialize(void) } /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. * This is an opportunity for the board logic to shutdown clocks, power, @@ -93,7 +93,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/board.h b/boards/arm/stm32l4/stm32l476-mdk/include/board.h index 23a7b1bfe08f6..6c4c5b5a525be 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/board.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/board.h @@ -200,7 +200,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -210,7 +210,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c index d4585229ecf6b..990571be0068f 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c @@ -89,9 +89,9 @@ void board_autoled_initialize(void) { /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); } /**************************************************************************** @@ -102,7 +102,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ } } @@ -114,7 +114,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ + stm32_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ } } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c index ab4b6b3ddc43a..9600a50507a94 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c @@ -43,7 +43,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_uid.h" #include "stm32l476-mdk.h" @@ -66,7 +66,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -76,7 +76,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ @@ -90,7 +90,7 @@ void stm32l4_board_initialize(void) * stm32_spiinitialize() has been brought into the link. */ - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif } @@ -133,7 +133,7 @@ void board_late_initialize(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { syslog(LOG_ERR, @@ -181,7 +181,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c index a39653988ec36..e8aa789c2fc42 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c @@ -76,7 +76,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); } return NUM_BUTTONS; @@ -97,7 +97,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = stm32l4_gpioread(g_buttons[i]); + bool released = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -139,7 +139,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index b0d6337920f73..e8ee098c11195 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c index 766cd2f1646be..74f0778215770 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476-mdk.h" diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c index 19b645de1a0ff..db4d7ded75125 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c @@ -48,9 +48,9 @@ uint32_t board_userled_initialize(void) #ifndef CONFIG_ARCH_LEDS /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); #endif return BOARD_NLEDS; } @@ -63,16 +63,16 @@ void board_userled(int led, bool ledon) { if (led == BOARD_RED_LED) { - stm32l4_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ } else if (led == BOARD_GREEN_LED) { - stm32l4_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ } #ifndef CONFIG_ARCH_LEDS else if (led == BOARD_WHITE_LED) { - stm32l4_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ } #endif } @@ -85,9 +85,9 @@ void board_userled_all(uint32_t ledset) { /* Low illuminates */ - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); - stm32l4_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); #ifndef CONFIG_ARCH_LEDS - stm32l4_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); #endif } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h index dfc573d046b5a..afb63e27460d7 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h @@ -281,7 +281,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -291,7 +291,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c index a5c0dceaba472..bf1c2cd510329 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index 7de1834ade3c3..34834af60d0a2 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -65,7 +65,7 @@ void stm32l4_board_initialize(void) */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif #ifdef CONFIG_STM32_OTGFS @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c index f96a416d76178..f3137ceb23211 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include @@ -124,7 +124,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -148,10 +148,10 @@ int stm32_bringup(void) #ifdef HAVE_N25QXXX /* Create an instance of the STM32L4 QSPI device driver */ - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (!g_qspi) { - _err("ERROR: stm32l4_qspi_initialize failed\n"); + _err("ERROR: stm32_qspi_initialize failed\n"); return ret; } else @@ -242,11 +242,11 @@ int stm32_bringup(void) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c index 4bc824ac86995..13e713e899838 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index 6e1538a154672..202b4e0dbcc78 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c index fcb4521d78998..dc297132fa986 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476vg-disco.h" diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c index 7c6da8f1cdc85..60809d9a07f55 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c index 4c24a207ffdd1..40155f6c84a7e 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c @@ -40,7 +40,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l476vg-disco.h" @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to + * Called from stm32_usbinitialize very early in initialization to * setup USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -138,14 +138,14 @@ void stm32l4_usbinitialize(void) */ #ifdef CONFIG_STM32_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be provided @@ -265,7 +265,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -273,19 +273,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -300,18 +300,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -319,7 +319,7 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c index 5ff1fcd886e09..39f749747e450 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h index 5250776f9a137..3a81fb74df2a6 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -274,13 +274,13 @@ int stm32_bringup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); #endif /* __BOARDS_ARM_STM32_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h index 132506d36fd0d..13b58c7980e5a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -285,7 +285,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c index 1e5318b529f19..f0ed838edef25 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c @@ -144,14 +144,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct adc_msg_s sample[ADC1_NCHANNELS]; @@ -265,10 +265,10 @@ int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; @@ -284,13 +284,13 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC */ + /* Call stm32_adc_initialize() to get an instance of the ADC */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c index a7af9a1dda8ac..fb79f4dbec311 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index 481741f8ed8dc..98c867d816ae7 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * also selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index 4b3be3c8dbc51..ecbd830baddb5 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include @@ -112,7 +112,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -136,14 +136,14 @@ int stm32_bringup(void) #ifdef CONFIG_I2C i2cinfo("Initializing I2C buses\n"); #ifdef CONFIG_STM32_I2C1 - g_i2c1 = stm32l4_i2cbus_initialize(1); + g_i2c1 = stm32_i2cbus_initialize(1); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c1, 1); #endif #endif #ifdef CONFIG_STM32_I2C3 - g_i2c3 = stm32l4_i2cbus_initialize(3); + g_i2c3 = stm32_i2cbus_initialize(3); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c3, 3); #endif @@ -151,11 +151,11 @@ int stm32_bringup(void) #endif /* CONFIG_I2C */ #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); @@ -177,7 +177,7 @@ int stm32_bringup(void) #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); + stm32_adc_setup(); #ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ @@ -192,7 +192,7 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif return ret; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c index ba8240c175cd1..3c50102b1315c 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index 812e680b3fb78..0aec106529524 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c index fce4aada4f5ec..63124aab2074b 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c @@ -48,10 +48,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -60,7 +60,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c index 7152d47ff4352..641f9dc111565 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c @@ -92,7 +92,7 @@ int stm32_dfsdm_setup(void) */ #ifdef CONFIG_STM32_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -108,7 +108,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -124,7 +124,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -140,7 +140,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index 5ecc111d80d47..6d9e8e2bf6d8a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #include "stm32l4r9ai-disco.h" @@ -75,7 +75,7 @@ void weak_function stm32_spiinitialize(void) #ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices on SPI1 */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -86,14 +86,14 @@ void weak_function stm32_spiinitialize(void) #endif #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif #ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices on SPI2 */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: [boot] FAILED to initialize SPI port 2\n"); @@ -109,7 +109,7 @@ void weak_function stm32_spiinitialize(void) #ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices on SPI3 */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) { spierr("ERROR: [boot] FAILED to initialize SPI port 3\n"); @@ -124,14 +124,14 @@ void weak_function stm32_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common STM32 + * (including stm32_spibus_initialize()) are provided by common STM32 * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -140,9 +140,9 @@ void weak_function stm32_spiinitialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -150,7 +150,7 @@ void weak_function stm32_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -159,47 +159,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1/2/3cmddata + * Name: stm32_spi1/2/3cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -223,21 +223,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c index bb1720bae25fd..94a5221d7efce 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c index e08a822848536..314bef362e16f 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c @@ -40,7 +40,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l4r9ai-disco.h" @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -138,14 +138,14 @@ void stm32l4_usbinitialize(void) */ #ifdef CONFIG_STM32_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -266,7 +266,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -274,19 +274,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -301,18 +301,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -320,7 +320,7 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c index 557436dade860..5d07a4d35840c 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h index 036583c316bcb..8c23f52d0f041 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h @@ -213,36 +213,36 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_dfsdm_setup @@ -267,13 +267,13 @@ int stm32_dfsdm_setup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); #endif /* __BOARDS_ARM_STM32_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h index 25e759e26c057..19bcaad40e2e8 100644 --- a/include/nuttx/analog/ioctl.h +++ b/include/nuttx/analog/ioctl.h @@ -93,12 +93,12 @@ /* See arch/arm/src/stm32l4/stm32l4_adc.h */ -#define AN_STM32L4_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) -#define AN_STM32L4_NCMDS 2 +#define AN_STM32_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) +#define AN_STM32_NCMDS 2 /* See include/nuttx/analog/max1161x.h */ -#define AN_MAX1161X_FIRST (AN_STM32L4_FIRST + AN_STM32L4_NCMDS) +#define AN_MAX1161X_FIRST (AN_STM32_FIRST + AN_STM32_NCMDS) #define AN_MAX1161X_NCMDS 8 /* See include/nuttx/analog/mcp48xx.h */ From 47735ed59ce5e4e4ed1e6252e0ecdbc1e33e1676 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:44 +0200 Subject: [PATCH 07/52] !arm/stm32l5: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32L5 interfaces were renamed from stm32l5_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32L5 timer/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32L5 root family header was renamed from stm32l5.h to stm32.h; all STM32L5 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32l5/{stm32l5.h => stm32.h} | 2 +- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 18 +- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 8 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 4 +- arch/arm/src/stm32l5/stm32l5_exti.h | 16 +- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 10 +- arch/arm/src/stm32l5/stm32l5_flash.c | 16 +- arch/arm/src/stm32l5/stm32l5_flash.h | 8 +- arch/arm/src/stm32l5/stm32l5_gpio.c | 28 +- arch/arm/src/stm32l5/stm32l5_gpio.h | 36 +- arch/arm/src/stm32l5/stm32l5_irq.c | 40 +- arch/arm/src/stm32l5/stm32l5_lowputc.c | 20 +- arch/arm/src/stm32l5/stm32l5_lowputc.h | 4 +- arch/arm/src/stm32l5/stm32l5_lse.c | 10 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.h | 12 +- arch/arm/src/stm32l5/stm32l5_pwr.c | 44 +- arch/arm/src/stm32l5/stm32l5_pwr.h | 14 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 28 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 42 +- arch/arm/src/stm32l5/stm32l5_serial.c | 204 ++++---- arch/arm/src/stm32l5/stm32l5_spi.c | 184 +++---- arch/arm/src/stm32l5/stm32l5_spi.h | 48 +- arch/arm/src/stm32l5/stm32l5_start.c | 12 +- arch/arm/src/stm32l5/stm32l5_start.h | 4 +- arch/arm/src/stm32l5/stm32l5_tim.c | 460 +++++++++--------- arch/arm/src/stm32l5/stm32l5_tim.h | 54 +- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 110 ++--- arch/arm/src/stm32l5/stm32l5_timerisr.c | 8 +- arch/arm/src/stm32l5/stm32l5_uart.h | 4 +- arch/arm/src/stm32l5/stm32l5_uid.c | 4 +- arch/arm/src/stm32l5/stm32l5_uid.h | 2 +- arch/arm/src/stm32l5/stm32l5_userspace.c | 6 +- arch/arm/src/stm32l5/stm32l5_userspace.h | 4 +- arch/arm/src/stm32l5/stm32l5_waste.c | 4 +- arch/arm/src/stm32l5/stm32l5_waste.h | 4 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 4 +- .../nucleo-l552ze/src/stm32_autoleds.c | 4 +- .../stm32l5/nucleo-l552ze/src/stm32_boot.c | 12 +- .../stm32l5/nucleo-l552ze/src/stm32_buttons.c | 6 +- .../nucleo-l552ze/src/stm32_userleds.c | 6 +- .../arm/stm32l5/stm32l562e-dk/include/board.h | 4 +- .../stm32l562e-dk/src/stm32_autoleds.c | 4 +- .../stm32l5/stm32l562e-dk/src/stm32_boot.c | 6 +- .../stm32l5/stm32l562e-dk/src/stm32_buttons.c | 6 +- .../stm32l562e-dk/src/stm32_clockconfig.c | 2 +- .../stm32l562e-dk/src/stm32_userleds.c | 6 +- 48 files changed, 774 insertions(+), 774 deletions(-) rename arch/arm/src/stm32l5/{stm32l5.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32l5/stm32l5.h b/arch/arm/src/stm32l5/stm32.h similarity index 98% rename from arch/arm/src/stm32l5/stm32l5.h rename to arch/arm/src/stm32l5/stm32.h index 4dacd389b6bc3..9ce64f1178564 100644 --- a/arch/arm/src/stm32l5/stm32l5.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/stm32l5.h + * arch/arm/src/stm32l5/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index 92cabb9d701e6..7de591b215d8f 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -575,10 +575,10 @@ static inline void rcc_enableccip(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { rcc_enableccip(); rcc_enableahb1(); @@ -589,7 +589,7 @@ void stm32l5_rcc_enableperipherals(void) } /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -599,7 +599,7 @@ void stm32l5_rcc_enableperipherals(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void) +void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -704,7 +704,7 @@ void stm32l5_stdclockconfig(void) /* Ensure Power control is enabled before modifying it. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* Select correct main regulator range */ @@ -901,7 +901,7 @@ void stm32l5_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -916,7 +916,7 @@ void stm32l5_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -927,7 +927,7 @@ void stm32l5_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l5_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 556a9bf5ae5bc..2be31186e6c77 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -240,7 +240,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -318,7 +318,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif @@ -338,7 +338,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM3 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -357,7 +357,7 @@ void arm_addregion(void) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index f5dc0ed6ce791..cf5760c43f65a 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -86,14 +86,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l5_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index bc1ad7da345d4..8d8eab5c8fc14 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32_COMP -int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index 67a6a051e235a..10e1099e0ec88 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -67,7 +67,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routine - Dispatcher ****************************************************************************/ -static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) +static int stm32_exti0_15_isr(int irq, void *context, void *arg) { int ret = OK; int exti; @@ -98,7 +98,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -120,7 +120,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { uint32_t pin = pinset & GPIO_PIN_MASK; @@ -134,7 +134,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (func) { - irq_attach(irq, stm32l5_exti0_15_isr, NULL); + irq_attach(irq, stm32_exti0_15_isr, NULL); up_enable_irq(irq); } else @@ -151,7 +151,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 8fdf84590a73c..f4182f8239aa8 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -107,7 +107,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) @@ -156,7 +156,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); @@ -166,14 +166,14 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -void stm32l5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock(); nxmutex_unlock(&g_lock); } -void stm32l5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock(); @@ -181,7 +181,7 @@ void stm32l5_flash_lock(void) } /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -197,7 +197,7 @@ void stm32l5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -229,7 +229,7 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -431,7 +431,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.h b/arch/arm/src/stm32l5/stm32l5_flash.h index f78f510b04d3e..4f0223c3ac853 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/stm32l5_flash.h @@ -34,11 +34,11 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_flash_lock(void); -void stm32l5_flash_unlock(void); +void stm32_flash_lock(void); +void stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ void stm32l5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32L5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 2d9afa34849a0..297a5deb18287 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -91,13 +91,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -105,17 +105,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32l5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -126,7 +126,7 @@ void stm32l5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -169,7 +169,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -304,7 +304,7 @@ int stm32l5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -324,7 +324,7 @@ int stm32l5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -333,18 +333,18 @@ int stm32l5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -378,14 +378,14 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index 6e53d43b23bd6..05eb5396392c8 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -248,12 +248,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -284,30 +284,30 @@ int stm32l5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -326,11 +326,11 @@ bool stm32l5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -338,23 +338,23 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index f42f2dda2ab8e..46195910a0c5f 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -112,11 +112,11 @@ static void stm32l5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l5_nmi, stm32l5_pendsv, stm32l5_pendsv, stm32l5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -126,7 +126,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -134,7 +134,7 @@ static int stm32l5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -142,7 +142,7 @@ static int stm32l5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -152,7 +152,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -160,7 +160,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -173,7 +173,7 @@ static inline void stm32l5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -181,7 +181,7 @@ static inline void stm32l5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -309,7 +309,7 @@ void up_irqinitialize(void) #endif - stm32l5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -323,19 +323,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -360,7 +360,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -395,7 +395,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -472,7 +472,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index 6229979f9a2e3..d10ce831abf3b 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_rcc.h" #include "stm32l5_gpio.h" #include "stm32l5_uart.h" @@ -308,7 +308,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -319,7 +319,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -327,7 +327,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -336,7 +336,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -352,19 +352,19 @@ void stm32l5_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l5_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32l5_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32l5_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.h b/arch/arm/src/stm32l5/stm32l5_lowputc.h index 316cd5a0ec427..0f8de0670dfd1 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.h +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index afe4793c6d942..0a18e77e62733 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -68,14 +68,14 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32l5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; @@ -100,7 +100,7 @@ void stm32l5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32l5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -173,7 +173,7 @@ void stm32l5_rcc_enablelse(void) while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32l5_waste(); + stm32_waste(); } } @@ -188,6 +188,6 @@ void stm32l5_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - stm32l5_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index a47bd5ea1dd47..6d57b07aac4ae 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32l5_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.c b/arch/arm/src/stm32l5/stm32l5_mpuinit.c index 94d42c795aefa..2c70971fdded1 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.c +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l5_mpuinitialize(void) * ****************************************************************************/ -void stm32l5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.h b/arch/arm/src/stm32l5/stm32l5_mpuinit.h index 4e13d0640de32..7eee119c5793e 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.h +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 3b306923e8e67..90ac2900f6bf8 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -39,12 +39,12 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } @@ -70,7 +70,7 @@ static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; @@ -99,7 +99,7 @@ bool stm32l5_pwr_enableclk(bool enable) } /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l5_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,7 +163,7 @@ bool stm32l5_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; @@ -174,12 +174,12 @@ bool stm32l5_pwr_enableusv(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -223,7 +223,7 @@ bool stm32l5_pwr_enableusv(bool set) * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; @@ -234,12 +234,12 @@ bool stm32l5_pwr_vddio2_valid(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,19 +249,19 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.h b/arch/arm/src/stm32l5/stm32l5_pwr.h index 3db2dd1f1d26f..4a7f5c33df224 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/stm32l5_pwr.h @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l5_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l5_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -123,7 +123,7 @@ bool stm32l5_pwr_enableusv(bool set); * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index a95f4c1f06a0e..b624e1aed3d01 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -37,7 +37,7 @@ #include "chip.h" #include "stm32l5_rcc.h" #include "stm32l5_flash.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_waste.h" /**************************************************************************** @@ -90,7 +90,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32l5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -107,7 +107,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32l5_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l5_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -150,7 +150,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -160,7 +160,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -175,7 +175,7 @@ void stm32l5_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -183,13 +183,13 @@ void stm32l5_clockconfig(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32l5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -202,12 +202,12 @@ void stm32l5_clockconfig(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -218,13 +218,13 @@ void stm32l5_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -232,7 +232,7 @@ void stm32l5_clockenable(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index cafb7ec7e2cfa..efa70a2ef9275 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -58,7 +58,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32l562xx @@ -75,7 +75,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32l5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -92,7 +92,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -102,7 +102,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -112,10 +112,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L5 board may replace the "standard" board clock configuration @@ -124,11 +124,11 @@ void stm32l5_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32l5_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -139,11 +139,11 @@ void stm32l5_board_clockconfig(void); ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void); +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -152,12 +152,12 @@ void stm32l5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,11 +168,11 @@ void stm32l5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -185,30 +185,30 @@ void stm32l5_clockenable(void); * ****************************************************************************/ -void stm32l5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -217,7 +217,7 @@ void stm32l5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index d7bdfff9d5d05..9e994dfb0c312 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -212,7 +212,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -327,9 +327,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev); static void stm32l5serial_dmashutdown(struct uart_dev_s *dev); static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv); +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv); +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev); @@ -446,7 +446,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static struct stm32l5_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -506,7 +506,7 @@ static struct stm32l5_serial_s g_lpuart1priv = #endif #ifdef CONFIG_STM32_USART1_SERIALDRIVER -static struct stm32l5_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -568,7 +568,7 @@ static struct stm32l5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32_USART2_SERIALDRIVER -static struct stm32l5_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -630,7 +630,7 @@ static struct stm32l5_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ #ifdef CONFIG_STM32_USART3_SERIALDRIVER -static struct stm32l5_serial_s g_usart3priv = +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -692,7 +692,7 @@ static struct stm32l5_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ #ifdef CONFIG_STM32_UART4_SERIALDRIVER -static struct stm32l5_serial_s g_uart4priv = +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -754,7 +754,7 @@ static struct stm32l5_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ #ifdef CONFIG_STM32_UART5_SERIALDRIVER -static struct stm32l5_serial_s g_uart5priv = +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -815,7 +815,7 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l5_serial_s * const +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER @@ -862,7 +862,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) +uint32_t stm32l5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -872,7 +872,7 @@ uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32l5serial_putreg(struct stm32l5_serial_s *priv, +void stm32l5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -883,7 +883,7 @@ void stm32l5serial_putreg(struct stm32l5_serial_s *priv, ****************************************************************************/ static inline -void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, +void stm32l5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -911,7 +911,7 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * Name: up_restoreusartint ****************************************************************************/ -static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -927,7 +927,7 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, * Name: stm32l5serial_disableusartint ****************************************************************************/ -static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -988,11 +988,11 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) +static int stm32l5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1009,8 +1009,8 @@ static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l5serial_setformat(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -1140,7 +1140,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -1159,7 +1159,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1188,7 +1188,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1229,7 +1229,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1278,7 +1278,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1304,8 +1304,8 @@ static void stm32l5serial_pm_setsuspend(bool suspend) static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1376,14 +1376,14 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l5serial_setup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1394,18 +1394,18 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1419,15 +1419,15 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_configgpio(priv->rs485_dir_gpio); - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1502,8 +1502,8 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1520,14 +1520,14 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1538,7 +1538,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1565,7 +1565,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -1576,7 +1576,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -1595,8 +1595,8 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) static void stm32l5serial_shutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1627,32 +1627,32 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1669,8 +1669,8 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1678,11 +1678,11 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1705,8 +1705,8 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) static int stm32l5serial_attach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1737,8 +1737,8 @@ static int stm32l5serial_attach(struct uart_dev_s *dev) static void stm32l5serial_detach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1757,7 +1757,7 @@ static void stm32l5serial_detach(struct uart_dev_s *dev) static int stm32l5serial_interrupt(int irq, void *context, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1817,7 +1817,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1883,8 +1883,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1893,9 +1893,9 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32l5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1903,7 +1903,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32l5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1958,7 +1958,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1969,7 +1969,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2195,7 +2195,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2212,7 +2212,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2275,8 +2275,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, static int stm32l5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2305,8 +2305,8 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2365,8 +2365,8 @@ static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2400,8 +2400,8 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32_FLOWCONTROL_BROKEN) @@ -2409,7 +2409,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2484,8 +2484,8 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2523,14 +2523,14 @@ static int stm32l5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2541,7 +2541,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2562,7 +2562,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -2573,7 +2573,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -2594,7 +2594,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2645,8 +2645,8 @@ static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2680,8 +2680,8 @@ static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2701,13 +2701,13 @@ static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2724,8 +2724,8 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2793,8 +2793,8 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l5serial_txready(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); @@ -2813,7 +2813,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l5serial_dmarxavailable(&priv->dev)) { @@ -2971,7 +2971,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2980,7 +2980,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3144,7 +3144,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3155,7 +3155,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3218,7 +3218,7 @@ void stm32l5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 234c245b5ba86..87c822ee87a0b 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l5_spi1/2/3select and stm32l5_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/3select() and stm32l5_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your board * is configured. - * 3. Add a calls to stm32l5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l5_spibus_initialize() may then be used to + * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -74,7 +74,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #ifdef CONFIG_STM32_SPI_DMA # include "stm32l5_dma.h" @@ -135,7 +135,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -176,34 +176,34 @@ struct stm32l5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv); -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv); -static void spi_dmatxwait(struct stm32l5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv); +static void spi_dmarxwait(struct stm32_spidev_s *priv); +static void spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -251,16 +251,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -309,16 +309,16 @@ static struct stm32l5_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l5_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,13 +331,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -365,16 +365,16 @@ static struct stm32l5_spidev_s g_spi2dev = static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l5_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,13 +387,13 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { @@ -436,7 +436,7 @@ static struct stm32l5_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,7 +518,7 @@ static inline void spi_putreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -543,7 +543,7 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -569,7 +569,7 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -596,7 +596,7 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l5_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -636,7 +636,7 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv) +static void spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -667,7 +667,7 @@ static void spi_dmarxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxwait(struct stm32l5_spidev_s *priv) +static void spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -698,7 +698,7 @@ static void spi_dmatxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -713,7 +713,7 @@ static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -730,7 +730,7 @@ static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -750,7 +750,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -768,7 +768,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -819,7 +819,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -870,10 +870,10 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -886,10 +886,10 @@ static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -909,7 +909,7 @@ static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -943,7 +943,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -979,7 +979,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1087,7 +1087,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1155,7 +1155,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; int savbits = nbits; @@ -1225,7 +1225,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1289,7 +1289,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1363,7 +1363,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1464,13 +1464,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && - !stm32l5_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l5_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1654,9 +1654,9 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l5_spidev_s *priv = - (struct stm32l5_spidev_s *)((char *)cb - - offsetof(struct stm32l5_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = + (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1707,7 +1707,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1750,17 +1750,17 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. - * NOTE: stm32l5_dmachannel() will always assign the DMA channel. - * If the channel is not available, then stm32l5_dmachannel() will + * NOTE: stm32_dmachannel() will always assign the DMA channel. + * If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. * WARNING: If you have another device sharing a DMA channel with SPI and * the code never releases that channel, then the call to - * stm32l5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32l5_dmachannel(priv->rxch); - priv->txdma = stm32l5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1785,7 +1785,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1798,9 +1798,9 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1817,9 +1817,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI1_SCK); - stm32l5_configgpio(GPIO_SPI1_MISO); - stm32l5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1842,9 +1842,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI2_SCK); - stm32l5_configgpio(GPIO_SPI2_MISO); - stm32l5_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1867,9 +1867,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI3_SCK); - stm32l5_configgpio(GPIO_SPI3_MISO); - stm32l5_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index 184ff3caa5834..48b2537d370a5 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l5_spi1/2/...select, - * stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be provided * by board-specific logic. These are implementations of the select, * status, and cmddata methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l5_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data * selection operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,28 +105,28 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32l5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI2 -void stm32l5_spi2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI3 -void stm32l5_spi3select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l5_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -147,19 +147,19 @@ int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32_SPI1 -int stm32l5_spi1register(struct spi_dev_s *dev, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI2 -int stm32l5_spi2register(struct spi_dev_s *dev, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI3 -int stm32l5_spi3register(struct spi_dev_s *dev, +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 467ec246fbae8..45d63d4f1b605 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_userspace.h" #include "stm32l5_start.h" @@ -151,10 +151,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l5_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l5_lowsetup(); - stm32l5_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -205,13 +205,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.h b/arch/arm/src/stm32l5/stm32l5_start.h index 953989eeee368..90860b8b5ccc7 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.h +++ b/arch/arm/src/stm32l5/stm32l5_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32L5_STM32_START_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 19c5ebbd5e0d0..dc176524d9fa6 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_tim.h" @@ -208,10 +208,10 @@ /* TIM Device Structure */ -struct stm32l5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l5_tim_ops_s *ops; - enum stm32l5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -221,179 +221,179 @@ struct stm32l5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l5_tim_getperiod(struct stm32l5_tim_dev_s *dev); -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev); -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l5_tim_ops_s stm32l5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l5_tim_enable, - .disable = stm32l5_tim_disable, - .setmode = stm32l5_tim_setmode, - .setclock = stm32l5_tim_setclock, - .getclock = stm32l5_tim_getclock, - .setperiod = stm32l5_tim_setperiod, - .getperiod = stm32l5_tim_getperiod, - .getcounter = stm32l5_tim_getcounter, - .setchannel = stm32l5_tim_setchannel, - .setcompare = stm32l5_tim_setcompare, - .getcapture = stm32l5_tim_getcapture, - .setisr = stm32l5_tim_setisr, - .enableint = stm32l5_tim_enableint, - .disableint = stm32l5_tim_disableint, - .ackint = stm32l5_tim_ackint, - .checkint = stm32l5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; #ifdef CONFIG_STM32_TIM1 -struct stm32l5_tim_priv_s stm32l5_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 -struct stm32l5_tim_priv_s stm32l5_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32_TIM3 -struct stm32l5_tim_priv_s stm32l5_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32_TIM4 -struct stm32l5_tim_priv_s stm32l5_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32_TIM5 -struct stm32l5_tim_priv_s stm32l5_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32_TIM6 -struct stm32l5_tim_priv_s stm32l5_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32_TIM7 -struct stm32l5_tim_priv_s stm32l5_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32_TIM8 -struct stm32l5_tim_priv_s stm32l5_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32_TIM15 -struct stm32l5_tim_priv_s stm32l5_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32_TIM16 -struct stm32l5_tim_priv_s stm32l5_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32_TIM17 -struct stm32l5_tim_priv_s stm32l5_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -404,51 +404,51 @@ struct stm32l5_tim_priv_s stm32l5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -456,14 +456,14 @@ static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -471,48 +471,48 @@ static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -520,14 +520,14 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32l5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -535,28 +535,28 @@ static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -567,10 +567,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -610,16 +610,16 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, return -EINVAL; } - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -627,10 +627,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -642,7 +642,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, if (freq == 0) { - stm32l5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -652,7 +652,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -745,17 +745,17 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32l5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32l5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -767,7 +767,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -837,46 +837,46 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: @@ -895,12 +895,12 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -928,10 +928,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -977,15 +977,15 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -993,25 +993,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1026,25 +1026,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1059,25 +1059,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1092,24 +1092,24 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1124,25 +1124,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1157,25 +1157,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1190,25 +1190,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1223,25 +1223,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1256,25 +1256,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1292,10 +1292,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1326,10 +1326,10 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1337,26 +1337,26 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1364,7 +1364,7 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1452,44 +1452,44 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1498,12 +1498,12 @@ static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1511,76 +1511,76 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) { #ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,30 +1591,30 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1687,7 +1687,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index 0a14ed05ff6ec..10218a23018a2 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -72,14 +72,14 @@ extern "C" /* TIM Device Structure */ -struct stm32l5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l5_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -116,7 +116,7 @@ enum stm32l5_tim_mode_e /* TIM Channel Modes */ -enum stm32l5_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -147,36 +147,36 @@ enum stm32l5_tim_channel_e /* TIM Operations */ -struct stm32l5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l5_tim_dev_s *dev); - void (*disable)(struct stm32l5_tim_dev_s *dev); - int (*setmode)(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); - int (*setclock)(struct stm32l5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l5_tim_dev_s *dev); - void (*setperiod)(struct stm32l5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l5_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); - int (*setcompare)(struct stm32l5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -185,14 +185,14 @@ struct stm32l5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -210,7 +210,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 4e6bfd5907120..789b50c7bdc61 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32l5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower); -static int stm32l5_stop(struct timer_lowerhalf_s *lower); -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,16 +110,16 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l5_start, - .stop = stm32l5_stop, - .getstatus = stm32l5_getstatus, - .settimeout = stm32l5_settimeout, - .setcallback = stm32l5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32_TIM1 -static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -127,7 +127,7 @@ static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32_TIM2 -static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -135,7 +135,7 @@ static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32_TIM3 -static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -143,7 +143,7 @@ static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32_TIM4 -static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -151,7 +151,7 @@ static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32_TIM5 -static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -159,7 +159,7 @@ static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32_TIM6 -static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -167,7 +167,7 @@ static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32_TIM7 -static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -175,7 +175,7 @@ static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32_TIM8 -static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -183,7 +183,7 @@ static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32_TIM15 -static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -191,7 +191,7 @@ static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32_TIM16 -static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -199,7 +199,7 @@ static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32_TIM17 -static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -211,7 +211,7 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,10 +222,10 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l5_lowerhalf_s *lower = - (struct stm32l5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -239,14 +239,14 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) } else { - stm32l5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,10 +260,10 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -271,7 +271,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -285,7 +285,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,10 +299,10 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -319,7 +319,7 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -386,7 +386,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -430,7 +430,7 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,7 +463,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -480,7 +480,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,9 +497,9 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -576,7 +576,7 @@ int stm32l5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 70b0d18aed082..0415a3ece422a 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -87,7 +87,7 @@ * ****************************************************************************/ -static int stm32l5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index f2d168a426732..44d48120bdb45 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -288,7 +288,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index 1b354bc4b7b5b..29f68da29bb4b 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_uid.c + * arch/arm/src/stm32l5/stm32_uid.c * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h index c6d67008c7268..782e85bda4af5 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ b/arch/arm/src/stm32l5/stm32l5_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32L5_STM32_UID_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.c b/arch/arm/src/stm32l5/stm32l5_userspace.c index 7b97d5b6b64d7..bd7d6944ab8d6 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.c +++ b/arch/arm/src/stm32l5/stm32l5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.h b/arch/arm/src/stm32l5/stm32l5_userspace.h index 70e0cd3a8164d..bbde34cefc392 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.h +++ b/arch/arm/src/stm32l5/stm32l5_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_waste.c b/arch/arm/src/stm32l5/stm32l5_waste.c index 7a6a60bc8e64b..3706b18e216db 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.c +++ b/arch/arm/src/stm32l5/stm32l5_waste.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_waste.c + * arch/arm/src/stm32l5/stm32_waste.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0; * Public Functions ****************************************************************************/ -void stm32l5_waste(void) +void stm32_waste(void) { idle_wastecounter++; } diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h index 48b31621409a5..55daea18a6641 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ b/arch/arm/src/stm32l5/stm32l5_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32l5_waste() is the logic that will be executed when portions of kernel + * stm32_waste() is the logic that will be executed when portions of kernel * or user-app is polling some register or similar, waiting for desired * status. This time is wasted away. This function offers a measure of badly * written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32l5_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 2ec0901258236..7b8d6d255d865 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -262,7 +262,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -272,7 +272,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c index 012f7938fbd00..f27e0286dd99f 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c @@ -64,7 +64,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l5_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -83,7 +83,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index c90a4df31f86e..7ba2e3c8fab64 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -52,18 +52,18 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #if defined(CONFIG_STM32_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in - * stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes + * stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. */ - stm32l5_configgpio(GPIO_LPUART1_TX); - stm32l5_configgpio(GPIO_LPUART1_RX); + stm32_configgpio(GPIO_LPUART1_TX); + stm32_configgpio(GPIO_LPUART1_RX); #endif #ifdef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c index 0ade669c51194..429c818dd1156 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c index f13c4b5f62766..8318cb30f2cc5 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -119,7 +119,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 8505bcf7942fa..ec882f5582b2e 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -185,7 +185,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -195,7 +195,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c index 0206ca6ca4877..4d3dd8249468f 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c @@ -63,7 +63,7 @@ static void phy_set_led(int led, bool state) { /* Active Low */ - stm32l5_gpiowrite(g_ledmap[led], !state); + stm32_gpiowrite(g_ledmap[led], !state); } /**************************************************************************** @@ -82,7 +82,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c index 9f40e9807a750..458aab5873360 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { /* On the STM32L562E-DK Vddio2 is supplied by Vdd_mcu. Thus, when the MCU * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by @@ -59,7 +59,7 @@ void stm32l5_board_initialize(void) * Vddio2 to be valid here. */ - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c index 133fb020e88cb..3091f1790814c 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index fca2b1c633284..79ba04835ac3b 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -44,7 +44,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) -void stm32l5_board_clockconfig(void) +void stm32_board_clockconfig(void) { } #endif diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c index 97342f1dfe8a6..fa01c25726108 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c @@ -76,7 +76,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -96,7 +96,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], !ledon); + stm32_gpiowrite(g_ledcfg[led], !ledon); } } @@ -118,7 +118,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + stm32_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); } } From 6a37b8993a299f4695f2a47f52d8d19d80cd9203 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:52 +0200 Subject: [PATCH 08/52] !arm/stm32wb: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32WB interfaces were renamed from stm32wb_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32WB timer/dma/freerun/oneshot/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32WB root family header was renamed from stm32wb.h to stm32.h; all STM32WB arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32wb/{stm32wb.h => stm32.h} | 2 +- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 6 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 62 +- arch/arm/src/stm32wb/stm32wb_blehci.h | 4 +- arch/arm/src/stm32wb/stm32wb_dma.c | 196 +++--- arch/arm/src/stm32wb/stm32wb_dma.h | 60 +- arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 4 +- arch/arm/src/stm32wb/stm32wb_exti.h | 12 +- arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 40 +- arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 10 +- arch/arm/src/stm32wb/stm32wb_flash.c | 16 +- arch/arm/src/stm32wb/stm32wb_flash.h | 8 +- arch/arm/src/stm32wb/stm32wb_freerun.c | 32 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 26 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_gpio.h | 36 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 516 ++++++++-------- arch/arm/src/stm32wb/stm32wb_i2c.h | 10 +- arch/arm/src/stm32wb/stm32wb_idle.c | 6 +- arch/arm/src/stm32wb/stm32wb_ipcc.c | 8 +- arch/arm/src/stm32wb/stm32wb_ipcc.h | 36 +- arch/arm/src/stm32wb/stm32wb_irq.c | 38 +- arch/arm/src/stm32wb/stm32wb_lowputc.c | 20 +- arch/arm/src/stm32wb/stm32wb_lowputc.h | 4 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 330 +++++----- arch/arm/src/stm32wb/stm32wb_mbox.h | 32 +- arch/arm/src/stm32wb/stm32wb_mbox_list.h | 36 +- arch/arm/src/stm32wb/stm32wb_mbox_shci.h | 2 +- arch/arm/src/stm32wb/stm32wb_mpuinit.c | 8 +- arch/arm/src/stm32wb/stm32wb_mpuinit.h | 12 +- arch/arm/src/stm32wb/stm32wb_oneshot.c | 42 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 28 +- .../src/stm32wb/stm32wb_oneshot_lowerhalf.c | 78 +-- arch/arm/src/stm32wb/stm32wb_pm.h | 20 +- arch/arm/src/stm32wb/stm32wb_pmlpr.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmsleep.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstandby.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstop.c | 8 +- arch/arm/src/stm32wb/stm32wb_pwr.c | 26 +- arch/arm/src/stm32wb/stm32wb_pwr.h | 8 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 40 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 8 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 10 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 8 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 90 +-- arch/arm/src/stm32wb/stm32wb_rtc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 152 ++--- arch/arm/src/stm32wb/stm32wb_serial.c | 574 +++++++++--------- arch/arm/src/stm32wb/stm32wb_spi.c | 166 ++--- arch/arm/src/stm32wb/stm32wb_spi.h | 40 +- arch/arm/src/stm32wb/stm32wb_start.c | 12 +- arch/arm/src/stm32wb/stm32wb_start.h | 4 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 94 +-- arch/arm/src/stm32wb/stm32wb_tim.c | 436 ++++++------- arch/arm/src/stm32wb/stm32wb_tim.h | 60 +- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 84 +-- arch/arm/src/stm32wb/stm32wb_timerisr.c | 6 +- arch/arm/src/stm32wb/stm32wb_uart.h | 4 +- arch/arm/src/stm32wb/stm32wb_uid.c | 4 +- arch/arm/src/stm32wb/stm32wb_uid.h | 2 +- arch/arm/src/stm32wb/stm32wb_userspace.c | 6 +- arch/arm/src/stm32wb/stm32wb_userspace.h | 4 +- arch/arm/src/stm32wb/stm32wb_waste.c | 4 +- arch/arm/src/stm32wb/stm32wb_waste.h | 4 +- .../arm/stm32wb/flipperzero/include/board.h | 4 +- .../arm/stm32wb/flipperzero/src/flipperzero.h | 4 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 16 +- .../flipperzero/src/stm32_lcd_st7565.c | 54 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 28 +- .../arm/stm32wb/nucleo-wb55rg/include/board.h | 4 +- .../nucleo-wb55rg/src/stm32_autoleds.c | 20 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 12 +- .../nucleo-wb55rg/src/stm32_userleds.c | 32 +- 76 files changed, 1956 insertions(+), 1956 deletions(-) rename arch/arm/src/stm32wb/{stm32wb.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32.h similarity index 98% rename from arch/arm/src/stm32wb/stm32wb.h rename to arch/arm/src/stm32wb/stm32.h index 8b54c5f9d2d6e..ef7f8b5db4872 100644 --- a/arch/arm/src/stm32wb/stm32wb.h +++ b/arch/arm/src/stm32wb/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/stm32wb.h + * arch/arm/src/stm32wb/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index 23c485617ba6a..6b94fcd14020d 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -201,7 +201,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wb_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -289,7 +289,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2a heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); + stm32_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); #endif @@ -309,7 +309,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2b heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); + stm32_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 32472809c6417..3df0927bd0e03 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -106,14 +106,14 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev); -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driveropen(struct bt_driver_s *btdev); +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len); -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt); -static void stm32wb_blehci_bleinit(void); -static int stm32wb_blehci_driverinitialize(void); -static void stm32wb_blehci_drvinitworker(void *arg); +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt); +static void stm32_blehci_bleinit(void); +static int stm32_blehci_driverinitialize(void); +static void stm32_blehci_drvinitworker(void *arg); /**************************************************************************** * Private Data @@ -122,8 +122,8 @@ static void stm32wb_blehci_drvinitworker(void *arg); static struct bt_driver_s g_blehci_driver = { .head_reserve = 0, - .open = stm32wb_blehci_driveropen, - .send = stm32wb_blehci_driversend + .open = stm32_blehci_driveropen, + .send = stm32_blehci_driversend }; static mutex_t g_lock = NXMUTEX_INITIALIZER; @@ -134,19 +134,19 @@ struct work_s g_drv_init_work; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_driveropen + * Name: stm32_blehci_driveropen ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev) +static int stm32_blehci_driveropen(struct bt_driver_s *btdev) { return 0; } /**************************************************************************** - * Name: stm32wb_blehci_driversend + * Name: stm32_blehci_driversend ****************************************************************************/ -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len) { @@ -177,11 +177,11 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, if (type == BT_CMD) { - ret = stm32wb_mbox_blecmd(data, len); + ret = stm32_mbox_blecmd(data, len); } else { - ret = stm32wb_mbox_bleacl(data, len); + ret = stm32_mbox_bleacl(data, len); } nxmutex_unlock(&g_lock); @@ -191,10 +191,10 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, } /**************************************************************************** - * Name: stm32wb_blehci_rxevt + * Name: stm32_blehci_rxevt ****************************************************************************/ -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) { size_t len; @@ -259,7 +259,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { - stm32wb_blehci_bleinit(); + stm32_blehci_bleinit(); } break; @@ -276,7 +276,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) /* Make driver initialisation in low priority work queue */ work_queue(LPWORK, &g_drv_init_work, - stm32wb_blehci_drvinitworker, NULL, 0); + stm32_blehci_drvinitworker, NULL, 0); } break; @@ -288,14 +288,14 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) } /**************************************************************************** - * Name: stm32wb_blehci_bleinit + * Name: stm32_blehci_bleinit ****************************************************************************/ -static void stm32wb_blehci_bleinit(void) +static void stm32_blehci_bleinit(void) { /* Prepare BLE configuration */ - struct stm32wb_shci_ble_init_cfg_s params = + struct stm32_shci_ble_init_cfg_s params = { .ble_buf = NULL, .ble_buf_size = 0, @@ -323,14 +323,14 @@ static void stm32wb_blehci_bleinit(void) /* Initialise BLE */ - stm32wb_mbox_bleinit(¶ms); + stm32_mbox_bleinit(¶ms); } /**************************************************************************** - * Name: stm32wb_blehci_driverinitialize + * Name: stm32_blehci_driverinitialize ****************************************************************************/ -static int stm32wb_blehci_driverinitialize(void) +static int stm32_blehci_driverinitialize(void) { int ret = 0; @@ -345,12 +345,12 @@ static int stm32wb_blehci_driverinitialize(void) } /**************************************************************************** - * Name: stm32wb_blehci_drvinitworker + * Name: stm32_blehci_drvinitworker ****************************************************************************/ -static void stm32wb_blehci_drvinitworker(void *arg) +static void stm32_blehci_drvinitworker(void *arg) { - stm32wb_blehci_driverinitialize(); + stm32_blehci_driverinitialize(); } /**************************************************************************** @@ -358,7 +358,7 @@ static void stm32wb_blehci_drvinitworker(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -367,15 +367,15 @@ static void stm32wb_blehci_drvinitworker(void *arg) * ****************************************************************************/ -void stm32wb_blehci_initialize(void) +void stm32_blehci_initialize(void) { /* Initialize mbox internal data structures and set * event receive handler. */ - stm32wb_mboxinitialize(stm32wb_blehci_rxevt); + stm32_mboxinitialize(stm32_blehci_rxevt); /* Enable communication hardware and boot up CPU2 */ - stm32wb_mboxenable(); + stm32_mboxenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.h b/arch/arm/src/stm32wb/stm32wb_blehci.h index 83525224e1098..eaa7fa0f2edd9 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.h +++ b/arch/arm/src/stm32wb/stm32wb_blehci.h @@ -50,7 +50,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -59,7 +59,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_blehci_initialize(void); +void stm32_blehci_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index 60509469bef54..2ba7cdd517d48 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -75,20 +75,20 @@ /* This structure described one DMAMUX device */ -struct stm32wb_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32wb_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32wb_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32wb_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -97,7 +97,7 @@ struct stm32wb_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32wb_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -110,11 +110,11 @@ struct stm32wb_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32wb_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32wb_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -145,12 +145,12 @@ struct stm32wb_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -160,19 +160,19 @@ struct stm32wb_dma_ops_s ****************************************************************************/ #if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan); -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg); -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32wb_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_sample(DMA_HANDLE handle, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -187,14 +187,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -203,20 +203,20 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { #ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -229,14 +229,14 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* 1 - DMA2 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -248,7 +248,7 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, @@ -259,7 +259,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = /* This array describes the state of each controller */ -static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ @@ -284,7 +284,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { #ifdef CONFIG_STM32_DMA1 /* DMA1 */ @@ -517,7 +517,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32wb_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -525,7 +525,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -533,7 +533,7 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -541,14 +541,14 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32wb_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -567,14 +567,14 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, #if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** - * Name: stm32wb_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -597,14 +597,14 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) } /**************************************************************************** - * Name: stm32wb_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -643,7 +643,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32wb_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ @@ -666,14 +666,14 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -738,13 +738,13 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, } /**************************************************************************** - * Name: stm32wb_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -800,10 +800,10 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32wb_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32wb_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -813,11 +813,11 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; @@ -830,7 +830,7 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -839,12 +839,12 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -872,7 +872,7 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } @@ -881,12 +881,12 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, #endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** - * Name: stm32wb_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); @@ -899,12 +899,12 @@ static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, #endif /**************************************************************************** - * Name: stm32wb_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", @@ -980,7 +980,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32wb_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1004,7 +1004,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1026,7 +1026,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1070,13 +1070,13 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1088,7 +1088,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1114,14 +1114,14 @@ void stm32wb_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1138,18 +1138,18 @@ void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1187,19 +1187,19 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1228,17 +1228,17 @@ void stm32wb_dmastop(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1254,7 +1254,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1271,7 +1271,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1347,18 +1347,18 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1375,18 +1375,18 @@ void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index 27474afce3cea..8fb0903eae7ff 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -71,7 +71,7 @@ typedef void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32wb_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ @@ -139,18 +139,18 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32wb_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -162,64 +162,64 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -234,44 +234,44 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_STM32_DMACAPABLE -bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32wb_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32wb_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32wb_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index b29a131b57feb..6d3a9fddd60d1 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -66,14 +66,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32wb_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32wb/stm32wb_exti.h b/arch/arm/src/stm32wb/stm32wb_exti.h index 5a9341ce6540a..ffcc754fe79f6 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/stm32wb_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,7 +118,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index 8a4b9cf1538fc..cff98eaeb9384 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 6d5afe56e694e..6e6597b60ca33 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -65,7 +65,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wb_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -107,7 +107,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -128,7 +128,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -149,7 +149,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -170,7 +170,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -214,14 +214,14 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wb_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wb_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -229,7 +229,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -251,7 +251,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -271,37 +271,37 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32wb_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wb_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wb_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wb_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wb_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32wb_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32wb_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -347,7 +347,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wb_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index 8caaed920191f..0cc045d27ca27 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -56,14 +56,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -102,7 +102,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -114,7 +114,7 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index 0e44b3f4dcc2d..32fba5d71e982 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); } else diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 62efc7e11a941..4b1baf8a7ae9c 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -93,7 +93,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -143,7 +143,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -153,7 +153,7 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -int stm32wb_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -169,7 +169,7 @@ int stm32wb_flash_unlock(void) return ret; } -int stm32wb_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -186,7 +186,7 @@ int stm32wb_flash_lock(void) } /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -202,7 +202,7 @@ int stm32wb_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -240,7 +240,7 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -453,7 +453,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32wb/stm32wb_flash.h b/arch/arm/src/stm32wb/stm32wb_flash.h index 2476cd597e2c0..72bf966904fdc 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/stm32wb_flash.h @@ -35,11 +35,11 @@ * Public Function Prototypes ****************************************************************************/ -int stm32wb_flash_lock(void); -int stm32wb_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -55,6 +55,6 @@ int stm32wb_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32WB_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index 95ffa6455ef6a..c308a611db3c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -44,7 +44,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -62,9 +62,9 @@ ****************************************************************************/ #ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32wb_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32wb_freerun_s *freerun = (struct stm32wb_freerun_s *)arg; + struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; @@ -79,7 +79,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -97,7 +97,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { uint32_t frequency; @@ -110,7 +110,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32wb_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -135,7 +135,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); #endif /* Set timer period */ @@ -156,7 +156,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, } /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -164,7 +164,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -176,7 +176,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -190,7 +190,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -253,7 +253,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) { *counter = STM32_TIM_GETCOUNTER(freerun->tch); @@ -263,7 +263,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -271,7 +271,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -279,7 +279,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); @@ -291,7 +291,7 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Free the timer */ - stm32wb_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index e545d8456dcde..82bb66d54d3d3 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -42,17 +42,17 @@ ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32wb_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; #ifndef CONFIG_CLOCK_TIMEKEEPING @@ -82,7 +82,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -100,11 +100,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -112,7 +112,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -124,18 +124,18 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter); #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -143,7 +143,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -151,7 +151,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index 433df3cea150c..a38e7398b74d2 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -71,13 +71,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -85,17 +85,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32wb_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -106,7 +106,7 @@ void stm32wb_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -147,7 +147,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wb_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -305,7 +305,7 @@ int stm32wb_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -325,7 +325,7 @@ int stm32wb_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -334,18 +334,18 @@ int stm32wb_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wb_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -379,14 +379,14 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index 94b52f3358f5e..f388d935afeb0 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -52,7 +52,7 @@ # define STM32_NPORTS 4 #endif -/* Bit-encoded input to stm32wb_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -257,12 +257,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -271,10 +271,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -293,30 +293,30 @@ int stm32wb_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -335,11 +335,11 @@ bool stm32wb_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -347,23 +347,23 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wb_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wb_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wb_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index fe8718c1c2d3e..50fdb01b3fde5 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -245,10 +245,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32wb_i2c_tracereset(p) -# define stm32wb_i2c_tracenew(p,s) -# define stm32wb_i2c_traceevent(p,e,a) -# define stm32wb_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -261,7 +261,7 @@ /* Interrupt state */ -enum stm32wb_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -270,7 +270,7 @@ enum stm32wb_intstate_e /* Trace events */ -enum stm32wb_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -293,18 +293,18 @@ enum stm32wb_trace_e /* Trace data */ -struct stm32wb_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32wb_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32wb_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -319,18 +319,18 @@ struct stm32wb_i2c_config_s /* I2C Device Private Data */ -struct stm32wb_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32wb_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32wb_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -348,7 +348,7 @@ struct stm32wb_i2c_priv_s /* The actual trace data */ - struct stm32wb_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -360,10 +360,10 @@ struct stm32wb_i2c_priv_s /* I2C Device, Instance */ -struct stm32wb_i2c_inst_s +struct stm32_i2c_inst_s { - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32wb_i2c_priv_s *priv; /* Common driver private data structure */ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -371,57 +371,57 @@ struct stm32wb_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); #endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv); -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm); -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv); -static inline void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -430,7 +430,7 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_STM32_I2C1 -static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = +static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, @@ -443,9 +443,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32wb_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -460,13 +460,13 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32_I2C3 -static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = +static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, @@ -479,9 +479,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32wb_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -496,18 +496,18 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32wb_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32wb_i2c_transfer, + .transfer = stm32_i2c_transfer, #ifdef CONFIG_I2C_RESET - .reset = stm32wb_i2c_reset + .reset = stm32_i2c_reset #endif }; @@ -516,7 +516,7 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -524,14 +524,14 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -539,42 +539,42 @@ uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getreg32(struct stm32wb_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -582,7 +582,7 @@ static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -590,7 +590,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -599,7 +599,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -620,7 +620,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #endif /**************************************************************************** - * Name: stm32wb_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -629,15 +629,15 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32wb_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -649,7 +649,7 @@ void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -659,11 +659,11 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32wb_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -675,7 +675,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32wb_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, CONFIG_STM32_I2CTIMEOTICKS); @@ -701,14 +701,14 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -718,7 +718,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Get the timeout value */ #ifdef CONFIG_STM32_I2C_DYNTIMEO - timeout = stm32wb_i2c_toticks(priv->msgc, priv->msgv); + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif @@ -741,7 +741,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * reports that it is done. */ - stm32wb_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -760,92 +760,92 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32wb_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } /**************************************************************************** - * Name: stm32wb_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32wb_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32wb_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32wb_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32wb_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32wb_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -853,7 +853,7 @@ stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -909,7 +909,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -917,9 +917,9 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -928,19 +928,19 @@ static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -966,7 +966,7 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -979,10 +979,10 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, } } -static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1002,13 +1002,13 @@ static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, } priv->tndx++; - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1026,7 +1026,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32wb_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1066,7 +1066,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { uint32_t pe; @@ -1076,10 +1076,10 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1141,7 +1141,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1168,7 +1168,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1230,13 +1230,13 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1246,18 +1246,18 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32wb_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1265,11 +1265,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32wb_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32wb_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1279,11 +1279,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32wb_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1295,17 +1295,17 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32wb_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1313,13 +1313,13 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32wb_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1327,14 +1327,14 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32wb_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1342,22 +1342,22 @@ void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32wb_i2c_process + * stm32_i2c_process * and - * stm32wb_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1367,8 +1367,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32wb_i2c_tracenew(priv, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1410,7 +1410,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1420,7 +1420,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1474,7 +1474,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1487,7 +1487,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1498,7 +1498,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1520,13 +1520,13 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1539,7 +1539,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1582,7 +1582,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1590,7 +1590,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32wb_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1621,8 +1621,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Unsupported state */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1688,7 +1688,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -1702,7 +1702,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->msgv++; - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -1715,9 +1715,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32wb_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1796,7 +1796,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -1804,7 +1804,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -1829,9 +1829,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * the transfer. */ - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -1848,9 +1848,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1866,10 +1866,10 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -1885,11 +1885,11 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32wb_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1898,7 +1898,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32wb_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -1907,7 +1907,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32wb_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -1915,7 +1915,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* Clear pointer to message content to reflect we are done * with the current transaction. @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,14 +1954,14 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -1969,24 +1969,24 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32wb_i2c_priv_s *priv = (struct stm32wb_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32wb_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32wb_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ @@ -1998,22 +1998,22 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Configure pins */ - if (stm32wb_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32wb_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32wb_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32wb_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32wb_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2026,33 +2026,33 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32wb_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32wb_unconfiggpio(priv->config->scl_pin); - stm32wb_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2072,7 +2072,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2082,11 +2082,11 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32wb_i2c_inst_s *inst = (struct stm32wb_i2c_inst_s *)dev; - struct stm32wb_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2097,11 +2097,11 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32wb_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32wb_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2110,14 +2110,14 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32wb_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32wb_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32wb_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2126,17 +2126,17 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32wb_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32wb_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2144,10 +2144,10 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32wb_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2161,7 +2161,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2266,7 +2266,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2276,7 +2276,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2284,7 +2284,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2295,27 +2295,27 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, break; } - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32wb_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32wb_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { @@ -2323,17 +2323,17 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, /* Ensure that address or flags don't change meanwhile */ - ret = nxmutex_lock(&((struct stm32wb_i2c_inst_s *)dev)->priv->lock); + ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock); if (ret >= 0) { - ret = stm32wb_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32wb_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2341,9 +2341,9 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s * dev) +static int stm32_i2c_reset(struct i2c_master_s * dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2355,7 +2355,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Get I2C private structure */ - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2377,24 +2377,24 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* De-init the port */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - stm32wb_configgpio(sda_gpio); - stm32wb_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); /* Let SDA go high */ - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32wb_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2409,7 +2409,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) */ stretch_count = 0; - while (!stm32wb_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2423,12 +2423,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Drive SCL low */ - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2436,27 +2436,27 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) * state machines. */ - stm32wb_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32wb_unconfiggpio(sda_gpio); - stm32wb_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32wb_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2469,7 +2469,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32wb_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2498,12 +2498,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_i2c_priv_s *priv = - (struct stm32wb_i2c_priv_s *)((char *)cb - - offsetof(struct stm32wb_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2545,17 +2545,17 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32wb_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32wb_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ @@ -2563,12 +2563,12 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) { #ifdef CONFIG_STM32_I2C1 case 1: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif #ifdef CONFIG_STM32_I2C3 case 3: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif default: @@ -2577,14 +2577,14 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32wb_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32wb_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2594,7 +2594,7 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2608,19 +2608,19 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -2645,7 +2645,7 @@ int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index 8d64fa09b8d46..af266f5ff02a4 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32wb_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); #endif /* __ARCH_ARM_SRC_STM32WB_STM32_I2C_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 24f9513b0ba31..4001f8210e593 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32wb_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32wb_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32wb_pmstandby(); + stm32_pmstandby(); break; default: diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index 795ec398c46a6..c9b889aec9a02 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -40,14 +40,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void) +void stm32_ipccreset(void) { uint32_t regval; @@ -77,14 +77,14 @@ void stm32wb_ipccreset(void) } /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void) +void stm32_ipccenable(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index 49a66ea347975..e492c24e7f972 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -55,77 +55,77 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void); +void stm32_ipccreset(void); /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void); +void stm32_ipccenable(void); /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxactive + * Name: stm32_ipcc_rxactive * * Description: * Check channel receive active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_rxactive(uint8_t chan) +static inline bool stm32_ipcc_rxactive(uint8_t chan) { return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_txactive + * Name: stm32_ipcc_txactive * * Description: * Check channel transmit active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_txactive(uint8_t chan) +static inline bool stm32_ipcc_txactive(uint8_t chan) { return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_settxactive + * Name: stm32_ipcc_settxactive * * Description: * Set channel transmit active flag. * ****************************************************************************/ -static inline void stm32wb_ipcc_settxactive(uint8_t chan) +static inline void stm32_ipcc_settxactive(uint8_t chan) { putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** - * Name: stm32wb_ipcc_masktxf + * Name: stm32_ipcc_masktxf * * Description: * Mask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_masktxf(uint8_t chan) +static inline void stm32_ipcc_masktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); @@ -133,14 +133,14 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_unmasktxf + * Name: stm32_ipcc_unmasktxf * * Description: * Unmask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) +static inline void stm32_ipcc_unmasktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); @@ -148,14 +148,14 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Mask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_maskrxo(uint8_t chan) +static inline void stm32_ipcc_maskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); @@ -163,14 +163,14 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Unmask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) +static inline void stm32_ipcc_unmaskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index f87503a7802f5..d03886cee305c 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -65,7 +65,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -73,7 +73,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wb_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -129,11 +129,11 @@ static void stm32wb_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wb_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wb_nmi, stm32wb_pendsv,stm32wb_pendsv, stm32wb_reserved + * Name: stm32_nmi, stm32_pendsv,stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -143,7 +143,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wb_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -151,7 +151,7 @@ static int stm32wb_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wb_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -159,7 +159,7 @@ static int stm32wb_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wb_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -169,7 +169,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wb_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -177,7 +177,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wb_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -190,7 +190,7 @@ static inline void stm32wb_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wb_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -198,7 +198,7 @@ static inline void stm32wb_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -328,7 +328,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -342,19 +342,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wb_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -379,7 +379,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -414,7 +414,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -491,7 +491,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wb_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index c8807a1f5bfb5..9175c37cffddf 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_rcc.h" #include "stm32wb_gpio.h" #include "stm32wb_uart.h" @@ -214,7 +214,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -225,7 +225,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -233,7 +233,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -242,7 +242,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wb_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -258,19 +258,19 @@ void stm32wb_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wb_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32wb_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32wb_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.h b/arch/arm/src/stm32wb/stm32wb_lowputc.h index c05e6f430003b..86c2296525798 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.h +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index a4062bcd78faf..b066a6a804dac 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -48,14 +48,14 @@ /* Mailbox shared buffer fields */ -#define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) +#define stm32_mbox_shared \ + (*(struct stm32_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) -#define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) -#define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) -#define stm32wb_mbox_sys_table (stm32wb_mbox_shared.sys_table) -#define stm32wb_mbox_mm_table (stm32wb_mbox_shared.mm_table) -#define stm32wb_mbox_ble_table (stm32wb_mbox_shared.ble_table) +#define stm32_mbox_ref_table (stm32_mbox_shared.ref_table) +#define stm32_mbox_di_table (stm32_mbox_shared.dev_info_table) +#define stm32_mbox_sys_table (stm32_mbox_shared.sys_table) +#define stm32_mbox_mm_table (stm32_mbox_shared.mm_table) +#define stm32_mbox_ble_table (stm32_mbox_shared.ble_table) /* Mailbox buffer sizes */ @@ -72,19 +72,19 @@ /* Mailbox shared buffer structures */ -begin_packed_struct struct stm32wb_mbox_safe_boot_info_table_s +begin_packed_struct struct stm32_mbox_safe_boot_info_table_s { uint32_t version; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_fus_info_table_s +begin_packed_struct struct stm32_mbox_fus_info_table_s { uint32_t version; uint32_t memory_size; uint32_t fus_info; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s +begin_packed_struct struct stm32_mbox_wireless_fw_info_table_s { uint32_t version; uint32_t memory_size; @@ -92,14 +92,14 @@ begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s uint32_t reserved; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_device_info_table_s +begin_packed_struct struct stm32_mbox_device_info_table_s { - struct stm32wb_mbox_safe_boot_info_table_s safe_boot_info_table; - struct stm32wb_mbox_fus_info_table_s fus_info_table; - struct stm32wb_mbox_wireless_fw_info_table_s wireless_fw_info_table; + struct stm32_mbox_safe_boot_info_table_s safe_boot_info_table; + struct stm32_mbox_fus_info_table_s fus_info_table; + struct stm32_mbox_wireless_fw_info_table_s wireless_fw_info_table; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ble_table_s +begin_packed_struct struct stm32_mbox_ble_table_s { void *cmd_buffer; void *cs_buffer; @@ -107,13 +107,13 @@ begin_packed_struct struct stm32wb_mbox_ble_table_s void *acl_buffer; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_sys_table_s +begin_packed_struct struct stm32_mbox_sys_table_s { void *cmd_buffer; void *evt_queue; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_mem_manager_table_s +begin_packed_struct struct stm32_mbox_mem_manager_table_s { void *ble_spare_buffer; void *sys_spare_buffer; @@ -124,13 +124,13 @@ begin_packed_struct struct stm32wb_mbox_mem_manager_table_s uint32_t traces_evtpool_size; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ref_table_s +begin_packed_struct struct stm32_mbox_ref_table_s { - struct stm32wb_mbox_device_info_table_s *dev_info_table; - struct stm32wb_mbox_ble_table_s *ble_table; + struct stm32_mbox_device_info_table_s *dev_info_table; + struct stm32_mbox_ble_table_s *ble_table; void *thread_table; - struct stm32wb_mbox_sys_table_s *sys_table; - struct stm32wb_mbox_mem_manager_table_s *mm_table; + struct stm32_mbox_sys_table_s *sys_table; + struct stm32_mbox_mem_manager_table_s *mm_table; void *traces_table; void *mac_802_15_4_table; void *zigbee_table; @@ -140,20 +140,20 @@ begin_packed_struct struct stm32wb_mbox_ref_table_s /* Mailbox shared buffer memory layout structure */ -struct stm32wb_mbox_shared_buffer_s +struct stm32_mbox_shared_buffer_s { - aligned_data(4) struct stm32wb_mbox_ref_table_s ref_table; + aligned_data(4) struct stm32_mbox_ref_table_s ref_table; - aligned_data(4) struct stm32wb_mbox_device_info_table_s dev_info_table; - aligned_data(4) struct stm32wb_mbox_ble_table_s ble_table; - aligned_data(4) struct stm32wb_mbox_sys_table_s sys_table; - aligned_data(4) struct stm32wb_mbox_mem_manager_table_s mm_table; + aligned_data(4) struct stm32_mbox_device_info_table_s dev_info_table; + aligned_data(4) struct stm32_mbox_ble_table_s ble_table; + aligned_data(4) struct stm32_mbox_sys_table_s sys_table; + aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; - aligned_data(4) stm32wb_mbox_list_t evtfree_buffer; + aligned_data(4) stm32_mbox_list_t evtfree_buffer; #ifdef CONFIG_STM32_BLE - aligned_data(4) stm32wb_mbox_list_t ble_evt_queue; + aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif - aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; + aligned_data(4) stm32_mbox_list_t sys_evt_queue; #ifdef CONFIG_STM32_BLE aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; @@ -170,11 +170,11 @@ struct stm32wb_mbox_shared_buffer_s /* Mailbox channel data type */ -struct stm32wb_mbox_channel_s +struct stm32_mbox_channel_s { uint8_t ch_num; - stm32wb_mbox_list_t cmd_buf_queue; - struct stm32wb_mbox_cmd_s *cmd_buf; + stm32_mbox_list_t cmd_buf_queue; + struct stm32_mbox_cmd_s *cmd_buf; bool ack_ready; }; @@ -182,18 +182,18 @@ struct stm32wb_mbox_channel_s * Private Function prototypes ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_mbox_rxworker(void *arg); -static void stm32wb_mbox_txworker(void *arg); +static void stm32_mbox_rxworker(void *arg); +static void stm32_mbox_txworker(void *arg); -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt); -static void stm32wb_mbox_acksyscmd(void); +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt); +static void stm32_mbox_acksyscmd(void); -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len); -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan); /**************************************************************************** * Private Data @@ -202,26 +202,26 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); static struct work_s g_rx_evt_work; static struct work_s g_tx_cmd_work; -static stm32wb_mbox_list_t g_rx_evt_queue; -static stm32wb_mbox_list_t g_tx_evtfree_queue; +static stm32_mbox_list_t g_rx_evt_queue; +static stm32_mbox_list_t g_tx_evtfree_queue; static uint8_t g_free_buffers[CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN] [STM32_MBOX_CMDPKT_BUF_SIZE]; -static stm32wb_mbox_list_t g_free_buffers_pool; +static stm32_mbox_list_t g_free_buffers_pool; -static struct stm32wb_mbox_channel_s g_syscmd_channel; +static struct stm32_mbox_channel_s g_syscmd_channel; #ifdef CONFIG_STM32_BLE -static struct stm32wb_mbox_channel_s g_blecmd_channel; -static struct stm32wb_mbox_channel_s g_bleacl_channel; +static struct stm32_mbox_channel_s g_blecmd_channel; +static struct stm32_mbox_channel_s g_bleacl_channel; #endif -static stm32wb_mbox_evt_handler_t receive_evt_handler; +static stm32_mbox_evt_handler_t receive_evt_handler; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxoisr + * Name: stm32_ipcc_rxoisr * * Description: * RX channel occupied interrupt handler (communication data posted @@ -229,15 +229,15 @@ static stm32wb_mbox_evt_handler_t receive_evt_handler; * ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) { uint32_t clrmask = 0; /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.sys_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); @@ -247,9 +247,9 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.ble_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); @@ -260,7 +260,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_rx_evt_work)) { - work_queue(HPWORK, &g_rx_evt_work, stm32wb_mbox_rxworker, NULL, 0); + work_queue(HPWORK, &g_rx_evt_work, stm32_mbox_rxworker, NULL, 0); } /* Clear active statuses */ @@ -269,7 +269,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_ipcc_txfisr + * Name: stm32_ipcc_txfisr * * Description: * TX channel free interrupt handler (communication data retrieved @@ -277,7 +277,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) * ****************************************************************************/ -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; @@ -296,14 +296,14 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { /* Move all released events (if any) into transmission mailbox */ - if (!stm32wb_mbox_list_is_empty(&g_tx_evtfree_queue)) + if (!stm32_mbox_list_is_empty(&g_tx_evtfree_queue)) { - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } @@ -327,7 +327,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_tx_cmd_work)) { - work_queue(HPWORK, &g_tx_cmd_work, stm32wb_mbox_txworker, NULL, 0); + work_queue(HPWORK, &g_tx_cmd_work, stm32_mbox_txworker, NULL, 0); } } @@ -337,10 +337,10 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_txworker + * Name: stm32_mbox_txworker ****************************************************************************/ -static void stm32wb_mbox_txworker(void *arg) +static void stm32_mbox_txworker(void *arg) { bool handled; @@ -350,28 +350,28 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ if (g_syscmd_channel.ack_ready) { - stm32wb_mbox_acksyscmd(); + stm32_mbox_acksyscmd(); g_syscmd_channel.ack_ready = false; } - handled = stm32wb_mbox_txnext(&g_syscmd_channel); + handled = stm32_mbox_txnext(&g_syscmd_channel); } #ifdef CONFIG_STM32_BLE - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_blecmd_channel); + handled |= stm32_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_bleacl_channel); + handled |= stm32_mbox_txnext(&g_bleacl_channel); } #endif } @@ -379,12 +379,12 @@ static void stm32wb_mbox_txworker(void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_rxworker + * Name: stm32_mbox_rxworker ****************************************************************************/ -static void stm32wb_mbox_rxworker(void *arg) +static void stm32_mbox_rxworker(void *arg) { - stm32wb_mbox_list_t *evt; + stm32_mbox_list_t *evt; irqstate_t flags; while (1) @@ -393,7 +393,7 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pull an event from the queue */ - evt = stm32wb_mbox_list_remove_head(&g_rx_evt_queue); + evt = stm32_mbox_list_remove_head(&g_rx_evt_queue); leave_critical_section(flags); @@ -404,18 +404,18 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pass event to a callback function without a list header */ - receive_evt_handler((struct stm32wb_mbox_evt_s *)(evt + 1)); + receive_evt_handler((struct stm32_mbox_evt_s *)(evt + 1)); /* Free completed event. Released event needs to return to CPU2 * via release channel. */ - stm32wb_mbox_eventfree((stm32wb_mbox_list_t *)evt); + stm32_mbox_eventfree((stm32_mbox_list_t *)evt); } } /**************************************************************************** - * Name: stm32wb_mbox_txdata + * Name: stm32_mbox_txdata * * Description: * Send data over specified mailbox channel if possible. If the @@ -423,11 +423,11 @@ static void stm32wb_mbox_rxworker(void *arg) * ****************************************************************************/ -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len) { irqstate_t flags; - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; flags = enter_critical_section(); @@ -435,8 +435,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * none of other waiting commands and none of unprocessed ack responses. */ - if (stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) && - !stm32wb_ipcc_txactive(chan->ch_num) && !chan->ack_ready) + if (stm32_mbox_list_is_empty(&chan->cmd_buf_queue) && + !stm32_ipcc_txactive(chan->ch_num) && !chan->ack_ready) { /* Channel is ready, copy command into transmission buffer */ @@ -446,8 +446,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Otherwise get temp buffer for command */ - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&g_free_buffers_pool); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&g_free_buffers_pool); } leave_critical_section(flags); @@ -464,9 +464,9 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Command is ready in mailbox buffer, start transmission now */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue) || chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get @@ -474,7 +474,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * And the system channel needs to check ack on completion. */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } } else @@ -482,31 +482,31 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, /* Command is in temp buffer, push it into queue */ flags = enter_critical_section(); - stm32wb_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); leave_critical_section(flags); /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } return OK; } /**************************************************************************** - * Name: stm32wb_mbox_txnext + * Name: stm32_mbox_txnext * * Description: * Send next command from the queue. * ****************************************************************************/ -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan) { - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&chan->cmd_buf_queue); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&chan->cmd_buf_queue); if (pkt_buf != NULL) { @@ -525,32 +525,32 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) /* Start transmission */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue)) + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue)) { /* Unmask TXF interrupt to get notified when completed */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } /* Put back to pool the freed command buffer */ - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); } return pkt_buf != NULL; } /**************************************************************************** - * Name: stm32wb_mbox_eventfree + * Name: stm32_mbox_eventfree * * Description: * Free handled mailbox event. * ****************************************************************************/ -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt) { irqstate_t flags; @@ -558,48 +558,48 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Collect releasing events in the global list */ - stm32wb_mbox_list_add_tail(&g_tx_evtfree_queue, evt); + stm32_mbox_list_add_tail(&g_tx_evtfree_queue, evt); /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_mbox_acksyscmd + * Name: stm32_mbox_acksyscmd * * Description: * Send ACK response event for completed system command. * ****************************************************************************/ -static void stm32wb_mbox_acksyscmd(void) +static void stm32_mbox_acksyscmd(void) { - struct stm32wb_mbox_evt_s *evt; + struct stm32_mbox_evt_s *evt; /* System command ACK response is placed at the same address as the * processed command but without a list header. */ - evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); + evt = (struct stm32_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); @@ -610,7 +610,7 @@ static void stm32wb_mbox_acksyscmd(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -620,79 +620,79 @@ static void stm32wb_mbox_acksyscmd(void) * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) { int i; /* Init mailbox shared data */ - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.sys_evt_queue); - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); #ifdef CONFIG_STM32_BLE - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.ble_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif - stm32wb_mbox_ref_table.dev_info_table = &stm32wb_mbox_di_table; - stm32wb_mbox_ref_table.ble_table = &stm32wb_mbox_ble_table; - stm32wb_mbox_ref_table.sys_table = &stm32wb_mbox_sys_table; - stm32wb_mbox_ref_table.mm_table = &stm32wb_mbox_mm_table; + stm32_mbox_ref_table.dev_info_table = &stm32_mbox_di_table; + stm32_mbox_ref_table.ble_table = &stm32_mbox_ble_table; + stm32_mbox_ref_table.sys_table = &stm32_mbox_sys_table; + stm32_mbox_ref_table.mm_table = &stm32_mbox_mm_table; - stm32wb_mbox_sys_table.cmd_buffer = &stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_sys_table.evt_queue = &stm32wb_mbox_shared.sys_evt_queue; + stm32_mbox_sys_table.cmd_buffer = &stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_sys_table.evt_queue = &stm32_mbox_shared.sys_evt_queue; - stm32wb_mbox_mm_table.evtpool_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_buffer = &stm32_mbox_shared .evtpool_buffer; - stm32wb_mbox_mm_table.evtpool_size = sizeof(stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_size = sizeof(stm32_mbox_shared .evtpool_buffer); - stm32wb_mbox_mm_table.evtfree_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtfree_buffer = &stm32_mbox_shared .evtfree_buffer; - stm32wb_mbox_mm_table.sys_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; #ifdef CONFIG_STM32_BLE - stm32wb_mbox_mm_table.ble_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif #ifdef CONFIG_STM32_BLE - stm32wb_mbox_ble_table.cmd_buffer = &stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_ble_table.acl_buffer = &stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_ble_table.cs_buffer = &stm32wb_mbox_shared.ble_cs_buffer; - stm32wb_mbox_ble_table.evt_queue = &stm32wb_mbox_shared.ble_evt_queue; + stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; + stm32_mbox_ble_table.evt_queue = &stm32_mbox_shared.ble_evt_queue; #endif /* Init system channel data */ g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; - g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); + g_syscmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); #ifdef CONFIG_STM32_BLE /* Init BLE command channel data */ g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; - g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); + g_blecmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; - g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); + g_bleacl_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); #endif /* Init local (not shared) queues */ - stm32wb_mbox_list_initialize(&g_rx_evt_queue); - stm32wb_mbox_list_initialize(&g_tx_evtfree_queue); + stm32_mbox_list_initialize(&g_rx_evt_queue); + stm32_mbox_list_initialize(&g_tx_evtfree_queue); - stm32wb_mbox_list_initialize(&g_free_buffers_pool); + stm32_mbox_list_initialize(&g_free_buffers_pool); for (i = 0; i < CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN; i++) { - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, - (stm32wb_mbox_list_t *)g_free_buffers[i]); + stm32_mbox_list_add_tail(&g_free_buffers_pool, + (stm32_mbox_list_t *)g_free_buffers[i]); } /* Set event receive function */ @@ -701,7 +701,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) } /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -709,16 +709,16 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) * ****************************************************************************/ -void stm32wb_mboxenable(void) +void stm32_mboxenable(void) { uint32_t regval; /* Setup RXO and TXF interrupts */ - irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32_ipcc_rxoisr, NULL); up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32_ipcc_txfisr, NULL); up_enable_irq(STM32_IRQ_IPCCTX); regval = getreg32(STM32_IPCC_C1CR); @@ -729,15 +729,15 @@ void stm32wb_mboxenable(void) * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ - stm32wb_ipccenable(); + stm32_ipccenable(); } /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -745,15 +745,15 @@ void stm32wb_mboxenable(void) * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len) +int stm32_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, + return stm32_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } #ifdef CONFIG_STM32_BLE /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -761,14 +761,14 @@ int stm32wb_mbox_syscmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len) +int stm32_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, + return stm32_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -776,27 +776,27 @@ int stm32wb_mbox_blecmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len) +int stm32_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, + return stm32_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) { struct bt_hci_cmd_hdr_s *cmd; /* Just borrow a temporary free buffer for command data */ - cmd = (struct bt_hci_cmd_hdr_s *)stm32wb_mbox_shared.sys_spare_buffer; + cmd = (struct bt_hci_cmd_hdr_s *)stm32_mbox_shared.sys_spare_buffer; /* Prepare command data */ @@ -806,10 +806,10 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Send BLE init command to CPU2 */ - stm32wb_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); + stm32_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } #endif /* CONFIG_STM32_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index 26a78c8f1b492..72eab3ba72fdc 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -77,7 +77,7 @@ /* Mailbox data transfer packets */ -begin_packed_struct struct stm32wb_mbox_evt_s +begin_packed_struct struct stm32_mbox_evt_s { uint8_t type; union @@ -87,9 +87,9 @@ begin_packed_struct struct stm32wb_mbox_evt_s }; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_cmd_s +begin_packed_struct struct stm32_mbox_cmd_s { - stm32wb_mbox_list_t list_hdr; + stm32_mbox_list_t list_hdr; uint8_t type; union { @@ -100,14 +100,14 @@ begin_packed_struct struct stm32wb_mbox_cmd_s /* Mailbox receive event handler type */ -typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); +typedef int (*stm32_mbox_evt_handler_t)(struct stm32_mbox_evt_s *); /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -117,10 +117,10 @@ typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler); /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -128,10 +128,10 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); * ****************************************************************************/ -void stm32wb_mboxenable(void); +void stm32_mboxenable(void); /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -139,10 +139,10 @@ void stm32wb_mboxenable(void); * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len); +int stm32_mbox_syscmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -150,10 +150,10 @@ int stm32wb_mbox_syscmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len); +int stm32_mbox_blecmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -161,16 +161,16 @@ int stm32wb_mbox_blecmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len); +int stm32_mbox_bleacl(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params); +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params); #endif /* __ARCH_ARM_SRC_STM32WB_STM32_MBOX_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_list.h b/arch/arm/src/stm32wb/stm32wb_mbox_list.h index f8bd643db4d85..35f9e3cb1e595 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_list.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_list.h @@ -38,42 +38,42 @@ * a new list_moveall function. */ -begin_packed_struct struct stm32wb_mbox_list_s +begin_packed_struct struct stm32_mbox_list_s { - struct stm32wb_mbox_list_s *next; - struct stm32wb_mbox_list_s *prev; + struct stm32_mbox_list_s *next; + struct stm32_mbox_list_s *prev; } end_packed_struct; -typedef struct stm32wb_mbox_list_s stm32wb_mbox_list_t; +typedef struct stm32_mbox_list_s stm32_mbox_list_t; /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mbox_list_initialize + * Name: stm32_mbox_list_initialize * * Description: * Initialize internal fields. * ****************************************************************************/ -static inline void stm32wb_mbox_list_initialize(stm32wb_mbox_list_t *list) +static inline void stm32_mbox_list_initialize(stm32_mbox_list_t *list) { list->prev = list; list->next = list; } /**************************************************************************** - * Name: stm32wb_mbox_list_add_tail + * Name: stm32_mbox_list_add_tail * * Description: * Add new node at the end of the list. * ****************************************************************************/ -static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, - stm32wb_mbox_list_t *item) +static inline void stm32_mbox_list_add_tail(stm32_mbox_list_t *list, + stm32_mbox_list_t *item) { item->prev = list->prev; item->next = list; @@ -82,19 +82,19 @@ static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, } /**************************************************************************** - * Name: stm32wb_mbox_list_remove_head + * Name: stm32_mbox_list_remove_head * * Description: * Remove and return first node from the list head (if any). * ****************************************************************************/ -static inline stm32wb_mbox_list_t * -stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) +static inline stm32_mbox_list_t * +stm32_mbox_list_remove_head(stm32_mbox_list_t *list) { if (list->next != list) { - stm32wb_mbox_list_t *item = list->next; + stm32_mbox_list_t *item = list->next; item->next->prev = item->prev; item->prev->next = item->next; item->prev = NULL; @@ -108,20 +108,20 @@ stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) } /**************************************************************************** - * Name: stm32wb_mbox_list_is_empty + * Name: stm32_mbox_list_is_empty * * Description: * Check if the list is empty. * ****************************************************************************/ -static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) +static inline bool stm32_mbox_list_is_empty(stm32_mbox_list_t *list) { return (list->next == list); } /**************************************************************************** - * Name: stm32wb_mbox_list_moveall + * Name: stm32_mbox_list_moveall * * Description: * Remove all nodes from source list and add them to the end of the @@ -129,8 +129,8 @@ static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) * ****************************************************************************/ -static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, - stm32wb_mbox_list_t *dst) +static inline void stm32_mbox_list_moveall(stm32_mbox_list_t *src, + stm32_mbox_list_t *dst) { if (src->next != src) { diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 4687fadbc63c9..267d6dad3f513 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -119,7 +119,7 @@ /* STM32_SHCI_BLE_INIT command params */ -begin_packed_struct struct stm32wb_shci_ble_init_cfg_s +begin_packed_struct struct stm32_shci_ble_init_cfg_s { void *ble_buf; /* Not used, must be NULL. */ uint32_t ble_buf_size; /* Not used, must be 0. */ diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.c b/arch/arm/src/stm32wb/stm32wb_mpuinit.c index b9d878aadd047..acc1576a64611 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.c +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wb_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wb_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wb_mpuinitialize(void) * ****************************************************************************/ -void stm32wb_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.h b/arch/arm/src/stm32wb/stm32wb_mpuinit.h index ae64e386983d1..bd15906f7d272 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.h +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wb_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wb_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wb_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32WB_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index f798cf7ddae73..80e63c4b4e9f8 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -45,20 +45,20 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32wb_oneshot_s *oneshot = (struct stm32wb_oneshot_s *)arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -107,7 +107,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -121,7 +121,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { #if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; @@ -162,7 +162,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,7 +193,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32wb_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -211,18 +211,18 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32wb_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32wb_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -301,7 +301,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ @@ -325,7 +325,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -336,7 +336,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -349,7 +349,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 097b66c738e09..21343fad3b4f7 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32wb_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ #if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c index 4c1b7030377cf..d98270362c4b7 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32wb_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32wb_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32wb_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32wb_max_delay, - .start = stm32wb_start, - .cancel = stm32wb_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32wb_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32wb_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32wb_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32wb_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32wb_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_start(&priv->oneshot, - stm32wb_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32wb_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -277,13 +277,13 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32wb_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32wb_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32wb_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -297,10 +297,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) /* Initialize the contained STM32 oneshot timer */ - ret = stm32wb_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32wb/stm32wb_pm.h b/arch/arm/src/stm32wb/stm32wb_pm.h index a984512594706..d30bf136c64d4 100644 --- a/arch/arm/src/stm32wb/stm32wb_pm.h +++ b/arch/arm/src/stm32wb/stm32wb_pm.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32wb_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32wb_pmstop(bool lpds); * ****************************************************************************/ -int stm32wb_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32wb_pmstop2(void); * ****************************************************************************/ -int stm32wb_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32wb_pmstandby(void); * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32wb_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32wb_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index fa601b27961bb..a86617edbfafb 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -39,7 +39,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -int stm32wb_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmsleep.c b/arch/arm/src/stm32wb/stm32wb_pmsleep.c index b9b64dd940c1b..8a2b0d629673e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmsleep.c +++ b/arch/arm/src/stm32wb/stm32wb_pmsleep.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index 657f4bf677926..09b81ae023680 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -int stm32wb_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 1cbd80f0e23b4..31a53a9160219 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -72,7 +72,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -90,7 +90,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32wb_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -114,7 +114,7 @@ int stm32wb_pmstop(bool lpds) } /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -129,7 +129,7 @@ int stm32wb_pmstop(bool lpds) * ****************************************************************************/ -int stm32wb_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index 62fe1b7be840b..7e7338b9e1e59 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -39,17 +39,17 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg32(STM32_PWR_BASE + (uint32_t)offset, @@ -61,7 +61,7 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers and backup @@ -75,14 +75,14 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -110,7 +110,7 @@ bool stm32wb_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -125,14 +125,14 @@ bool stm32wb_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.h b/arch/arm/src/stm32wb/stm32wb_pwr.h index 26c5c3d57614d..e154381dfb913 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/stm32wb_pwr.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -86,7 +86,7 @@ bool stm32wb_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** * Name: stm32_pwr_setvos diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 74c8e67fa0401..bd2878d4523b0 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -504,7 +504,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32wb_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -514,7 +514,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -static void stm32wb_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -789,7 +789,7 @@ static void stm32wb_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wb_rcc_enable_lsi(); + stm32_rcc_enable_lsi(); #endif #if defined(STM32_USE_LSE) @@ -805,7 +805,7 @@ static void stm32wb_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32wb_rcc_enable_lse(); + stm32_rcc_enable_lse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -846,7 +846,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -878,7 +878,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -895,7 +895,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -914,7 +914,7 @@ static inline void rcc_resetbkp(void) } } - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -922,7 +922,7 @@ static inline void rcc_resetbkp(void) #endif /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -932,7 +932,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -942,7 +942,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32wb_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -956,7 +956,7 @@ void stm32wb_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -964,7 +964,7 @@ void stm32wb_clockconfig(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -974,7 +974,7 @@ void stm32wb_clockconfig(void) } /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -984,12 +984,12 @@ void stm32wb_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -1000,13 +1000,13 @@ void stm32wb_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -1014,7 +1014,7 @@ void stm32wb_clockenable(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index d82d0ffbf5bc0..75d766426b163 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -68,7 +68,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output and clock divider on MC pin @@ -84,7 +84,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; * ****************************************************************************/ -static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) +static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; @@ -107,7 +107,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -117,7 +117,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -127,10 +127,10 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * ****************************************************************************/ -void stm32wb_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wb_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WB board may replace the "standard" board clock configuration @@ -139,11 +139,11 @@ void stm32wb_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32wb_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -153,12 +153,12 @@ void stm32wb_board_clockconfig(void); * re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -169,11 +169,11 @@ void stm32wb_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -186,30 +186,30 @@ void stm32wb_clockenable(void); * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void); +void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void); +void stm32_rcc_enable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void); +void stm32_rcc_disable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -235,10 +235,10 @@ void stm32wb_rcc_disable_lsi(void); * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc); /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -251,7 +251,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void); +void stm32_rcc_disable_hsi48(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index abdb78b4b4430..c3276e6d236a7 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -61,7 +61,7 @@ * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc) { uint32_t regval; @@ -130,7 +130,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) } /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -143,7 +143,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void) +void stm32_rcc_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 7bc64fec90591..8a830216564f3 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -54,14 +54,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void) +void stm32_rcc_enable_lse(void) { bool writable; uint32_t regval; @@ -78,7 +78,7 @@ void stm32wb_rcc_enable_lse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32wb_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -100,7 +100,7 @@ void stm32wb_rcc_enable_lse(void) while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32wb_waste(); + stm32_waste(); } #if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ @@ -121,6 +121,6 @@ void stm32wb_rcc_enable_lse(void) /* Disable backup domain access if it was disabled on entry */ - stm32wb_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 9fa23cfc73a8e..7dcdc39a50b48 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -34,14 +34,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void) +void stm32_rcc_enable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -55,14 +55,14 @@ void stm32wb_rcc_enable_lsi(void) } /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void) +void stm32_rcc_disable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index 11f9261e1847f..ed057295c6929 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -199,7 +199,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -237,7 +237,7 @@ static inline void rtc_wprlock(void) /* Disable write access to the backup domain. */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -436,7 +436,7 @@ static void rtc_resume(void) } /**************************************************************************** - * Name: stm32wb_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -451,7 +451,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -465,7 +465,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ @@ -531,7 +531,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -737,14 +737,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32wb_exti_alarm(true, false, true, stm32wb_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32wb_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -759,7 +759,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -800,7 +800,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -816,7 +816,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -851,14 +851,14 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); #if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, @@ -893,7 +893,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -960,7 +960,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -979,7 +979,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -989,7 +989,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1009,7 +1009,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS @@ -1140,7 +1140,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1174,12 +1174,12 @@ int up_rtc_getdatetime(struct tm *tp) # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1194,7 +1194,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32wb_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1257,9 +1257,9 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1270,7 +1270,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1280,7 +1280,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1309,11 +1309,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32wb_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1327,7 +1327,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1402,7 +1402,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1416,7 +1416,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1502,7 +1502,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) #endif /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1516,7 +1516,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1529,7 +1529,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMA: { alarmreg = STM32_RTC_ALRMAR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1538,7 +1538,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMB: { alarmreg = STM32_RTC_ALRMBR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1554,7 +1554,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1568,17 +1568,17 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; putreg32(regval, STM32_RTC_ISR); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1602,7 +1602,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32wb_exti_wakeup(true, false, true, stm32wb_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1630,7 +1630,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) #endif /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1645,7 +1645,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1774,7 +1774,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1787,7 +1787,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 016bed990f953..a59d829100e83 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -120,7 +120,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -135,10 +135,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -159,11 +159,11 @@ bool stm32wb_rtc_is_initialized(void); ****************************************************************************/ #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -180,11 +180,11 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32wb_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -194,11 +194,11 @@ int stm32wb_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -211,10 +211,10 @@ bool stm32wb_rtc_havesettime(void); * ****************************************************************************/ -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -227,10 +227,10 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -243,13 +243,13 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -263,11 +263,11 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -279,11 +279,11 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32wb_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32WB. General usage: @@ -292,7 +292,7 @@ int stm32wb_rtc_cancelperiodic(void); * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -306,7 +306,7 @@ int stm32wb_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 16fc6ea85587c..fca4009e4bf73 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -52,7 +52,7 @@ ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32wb_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument for callback */ @@ -64,7 +64,7 @@ struct stm32wb_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,29 +97,29 @@ struct stm32wb_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -130,24 +130,24 @@ stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32wb_rdtime, - .settime = stm32wb_settime, - .havesettime = stm32wb_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32wb_setalarm, - .setrelative = stm32wb_setrelative, - .cancelalarm = stm32wb_cancelalarm, - .rdalarm = stm32wb_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32wb_setperiodic, - .cancelperiodic = stm32wb_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32WB RTC device state */ -static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -158,7 +158,7 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -173,17 +173,17 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32wb_lowerhalf_s *lower; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32wb_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -206,7 +206,7 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32wb_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -221,13 +221,13 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -246,7 +246,7 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -261,13 +261,13 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -279,14 +279,14 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32wb_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32wb_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -299,13 +299,13 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32wb_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32wb_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -322,11 +322,11 @@ static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -334,7 +334,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -355,13 +355,13 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32wb_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32wb_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -375,7 +375,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -393,7 +393,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -439,7 +439,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32wb_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -450,7 +450,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -467,15 +467,15 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -496,7 +496,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) /* Then cancel the alarm */ - ret = stm32wb_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -505,7 +505,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) #endif /**************************************************************************** - * Name: stm32wb_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -521,7 +521,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -542,7 +542,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32wb_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -552,7 +552,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -568,14 +568,14 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32wb_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -593,7 +593,7 @@ static int stm32wb_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -612,14 +612,14 @@ static int stm32wb_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -628,8 +628,8 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32wb_rtc_setperiodic(&alarminfo->period, - stm32wb_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -637,7 +637,7 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -653,13 +653,13 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -669,7 +669,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32wb_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -681,7 +681,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -690,7 +690,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -702,7 +702,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 9c548fb474f19..a67006f7cf9b2 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -138,7 +138,7 @@ * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. * - * See stm32wb_serial_restoreusartint where the masking is done. + * See stm32_serial_restoreusartint where the masking is done. */ #ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT @@ -153,7 +153,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -239,51 +239,51 @@ struct stm32wb_serial_s ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev); +static void stm32_serial_setformat(struct uart_dev_s *dev); #endif -static int stm32wb_serial_setup(struct uart_dev_s *dev); -static void stm32wb_serial_shutdown(struct uart_dev_s *dev); -static int stm32wb_serial_attach(struct uart_dev_s *dev); -static void stm32wb_serial_detach(struct uart_dev_s *dev); +static int stm32_serial_setup(struct uart_dev_s *dev); +static void stm32_serial_shutdown(struct uart_dev_s *dev); +static int stm32_serial_attach(struct uart_dev_s *dev); +static void stm32_serial_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev); +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_rxavailable(struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch); -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_txready(struct uart_dev_s *dev); +static void stm32_serial_send(struct uart_dev_s *dev, int ch); +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_txready(struct uart_dev_s *dev); #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev); -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev); -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmasetup(struct uart_dev_s *dev); +static void stm32_serial_dmashutdown(struct uart_dev_s *dev); +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv); +static void stm32_serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv); +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev); +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev); -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend); -static void stm32wb_serial_pm_setsuspend(bool suspend); -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32_serial_pm_setsuspend(bool suspend); +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -294,42 +294,42 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, #ifndef SERIAL_HAVE_ONLY_DMA static const struct uart_ops_s g_uart_ops = { - .setup = stm32wb_serial_setup, - .shutdown = stm32wb_serial_shutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_receive, - .rxint = stm32wb_serial_rxint, - .rxavailable = stm32wb_serial_rxavailable, + .setup = stm32_serial_setup, + .shutdown = stm32_serial_shutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_receive, + .rxint = stm32_serial_rxint, + .rxavailable = stm32_serial_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif #ifdef SERIAL_HAVE_RXDMA static const struct uart_ops_s g_uart_dma_ops = { - .setup = stm32wb_serial_dmasetup, - .shutdown = stm32wb_serial_dmashutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_dmareceive, - .rxint = stm32wb_serial_dmarxint, - .rxavailable = stm32wb_serial_dmarxavailable, + .setup = stm32_serial_dmasetup, + .shutdown = stm32_serial_dmashutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_dmareceive, + .rxint = stm32_serial_dmarxint, + .rxavailable = stm32_serial_dmarxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif @@ -354,7 +354,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static struct stm32wb_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -416,7 +416,7 @@ static struct stm32wb_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ #ifdef CONFIG_STM32_USART1_SERIALDRIVER -static struct stm32wb_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -477,7 +477,7 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wb_serial_s * +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER @@ -495,8 +495,8 @@ static struct bool serial_suspended; } g_serialpm = { - .pm_cb.notify = stm32wb_serial_pmnotify, - .pm_cb.prepare = stm32wb_serial_pmprepare, + .pm_cb.notify = stm32_serial_pmnotify, + .pm_cb.prepare = stm32_serial_pmprepare, .serial_suspended = false }; #endif @@ -506,31 +506,31 @@ static struct ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_getreg + * Name: stm32_serial_getreg ****************************************************************************/ static inline -uint32_t stm32wb_serial_getreg(struct stm32wb_serial_s *priv, int offset) +uint32_t stm32_serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_putreg + * Name: stm32_serial_putreg ****************************************************************************/ -static inline void stm32wb_serial_putreg(struct stm32wb_serial_s *priv, +static inline void stm32_serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_setusartint + * Name: stm32_serial_setusartint ****************************************************************************/ static inline -void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) +void stm32_serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -542,38 +542,38 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; flags = spin_lock_irqsave(&priv->lock); - stm32wb_serial_setusartint(priv, ie); + stm32_serial_setusartint(priv, ie); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_disableusartint + * Name: stm32_serial_disableusartint ****************************************************************************/ -static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -624,13 +624,13 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, /* Disable all interrupts */ - stm32wb_serial_setusartint(priv, 0); + stm32_serial_setusartint(priv, 0); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_dmanextrx + * Name: stm32_serial_dmanextrx * * Description: * Returns the index into the RX FIFO where the DMA will place the next @@ -639,18 +639,18 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) +static int stm32_serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wb_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_usart + * Name: stm32_serial_setbaud_usart * * Description: * Set the serial line baud rate (USART only). @@ -658,7 +658,7 @@ static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,13 +713,13 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_lpuart + * Name: stm32_serial_setbaud_lpuart * * Description: * Set the serial line baud rate (LPUART only). @@ -728,7 +728,7 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -750,13 +750,13 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif /**************************************************************************** - * Name: stm32wb_serial_setformat + * Name: stm32_serial_setformat * * Description: * Set the serial line format and speed. @@ -764,9 +764,9 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev) +static void stm32_serial_setformat(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ @@ -774,17 +774,17 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { - stm32wb_serial_setbaud_lpuart(priv); + stm32_serial_setbaud_lpuart(priv); } else #endif { - stm32wb_serial_setbaud_usart(priv); + stm32_serial_setbaud_usart(priv); } /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,11 +834,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) @@ -855,12 +855,12 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** - * Name: stm32wb_serial_setsuspend + * Name: stm32_serial_setsuspend * * Description: * Suspend or resume serial peripheral. @@ -868,9 +868,9 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -889,18 +889,18 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wb_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif /* Disable interrupts to prevent Tx. */ - stm32wb_serial_disableusartint(priv, &priv->suspended_ie); + stm32_serial_disableusartint(priv, &priv->suspended_ie); /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + while ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -918,7 +918,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -932,7 +932,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } else #endif @@ -942,7 +942,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) * to DMA buffer before suspending). */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); priv->rxdmasusp = false; } @@ -952,14 +952,14 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Re-enable interrupts to resume Tx. */ - stm32wb_serial_restoreusartint(priv, priv->suspended_ie); + stm32_serial_restoreusartint(priv, priv->suspended_ie); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Restore peripheral RTS control. */ - stm32wb_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -977,7 +977,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) if (priv->rxdma != NULL) { - stm32wb_serial_dmarxcallback(priv->rxdma, 0, priv); + stm32_serial_dmarxcallback(priv->rxdma, 0, priv); } leave_critical_section(flags); @@ -987,7 +987,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #endif /**************************************************************************** - * Name: stm32wb_serial_pm_setsuspend + * Name: stm32_serial_pm_setsuspend * * Description: * Suspend or resume serial peripherals for/from deep-sleep/stop modes. @@ -995,7 +995,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pm_setsuspend(bool suspend) +static void stm32_serial_pm_setsuspend(bool suspend) { int n; @@ -1010,18 +1010,18 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (priv != NULL && priv->initialized != NULL) { - stm32wb_serial_setsuspend(&priv->dev, suspend); + stm32_serial_setsuspend(&priv->dev, suspend); } } } #endif /**************************************************************************** - * Name: stm32wb_serial_setapbclock + * Name: stm32_serial_setapbclock * * Description: * Enable or disable APB clock for the USART peripheral @@ -1032,9 +1032,9 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) * ****************************************************************************/ -static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) +static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1071,7 +1071,7 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) } /**************************************************************************** - * Name: stm32wb_serial_setup + * Name: stm32_serial_setup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1079,37 +1079,37 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) * ****************************************************************************/ -static int stm32wb_serial_setup(struct uart_dev_s *dev) +static int stm32_serial_setup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wb_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, true); + stm32_serial_setapbclock(dev, true); /* Configure pins for USART use */ if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1123,15 +1123,15 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wb_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_configgpio(priv->rs485_dir_gpio); - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,36 +1150,36 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1195,7 +1195,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_dmasetup + * Name: stm32_serial_dmasetup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1204,9 +1204,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) +static int stm32_serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1214,7 +1214,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) if (!dev->isconsole) { - result = stm32wb_serial_setup(dev); + result = stm32_serial_setup(dev); if (result != OK) { return result; @@ -1223,14 +1223,14 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wb_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1241,7 +1241,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1268,7 +1268,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -1279,7 +1279,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -1288,7 +1288,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) #endif /**************************************************************************** - * Name: stm32wb_serial_shutdown + * Name: stm32_serial_shutdown * * Description: * Disable the USART. This method is called when the serial @@ -1296,9 +1296,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_shutdown(struct uart_dev_s *dev) +static void stm32_serial_shutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1307,17 +1307,17 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable all interrupts */ - stm32wb_serial_disableusartint(priv, NULL); + stm32_serial_disableusartint(priv, NULL); /* Disable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, false); + stm32_serial_setapbclock(dev, false); /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1329,38 +1329,38 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wb_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wb_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } /**************************************************************************** - * Name: stm32wb_serial_dmashutdown + * Name: stm32_serial_dmashutdown * * Description: * Disable the USART. This method is called when the serial @@ -1369,27 +1369,27 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) +static void stm32_serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ - stm32wb_serial_shutdown(dev); + stm32_serial_shutdown(dev); /* Stop the DMA channel */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wb_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif /**************************************************************************** - * Name: stm32wb_serial_attach + * Name: stm32_serial_attach * * Description: * Configure the USART to operation in interrupt driven mode. This method @@ -1404,9 +1404,9 @@ static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) * ****************************************************************************/ -static int stm32wb_serial_attach(struct uart_dev_s *dev) +static int stm32_serial_attach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1425,7 +1425,7 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_detach + * Name: stm32_serial_detach * * Description: * Detach USART interrupts. This method is called when the serial port is @@ -1434,9 +1434,9 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_detach(struct uart_dev_s *dev) +static void stm32_serial_detach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1455,7 +1455,7 @@ static void stm32wb_serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1520,8 +1520,8 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1571,14 +1571,14 @@ static int up_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_serial_ioctl + * Name: stm32_serial_ioctl * * Description: * All ioctl calls will be routed through this method * ****************************************************************************/ -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) @@ -1586,7 +1586,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1595,14 +1595,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wb_serial_s *user = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *user = (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32wb_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1648,7 +1648,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1659,7 +1659,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1667,11 +1667,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,11 +1718,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1860,7 +1860,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, * TCSADRAIN / TCSAFLUSH */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); } break; #endif /* CONFIG_SERIAL_TERMIOS */ @@ -1877,7 +1877,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - stm32wb_serial_txint(dev, false); + stm32_serial_txint(dev, false); /* Configure TX as a GPIO output pin and Send a break signal */ @@ -1885,7 +1885,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wb_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1902,14 +1902,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; /* Enable further tx activity */ - stm32wb_serial_txint(dev, true); + stm32_serial_txint(dev, true); leave_critical_section(flags); } @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1952,7 +1952,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, } /**************************************************************************** - * Name: stm32wb_serial_receive + * Name: stm32_serial_receive * * Description: * Called (usually) from the interrupt level to receive one @@ -1962,15 +1962,15 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); + rdr = stm32_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -1984,7 +1984,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_rxint + * Name: stm32_serial_rxint * * Description: * Call to enable or disable RX interrupts @@ -1992,9 +1992,9 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2040,13 +2040,13 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) /* Then set the new interrupt state */ - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxavailable + * Name: stm32_serial_rxavailable * * Description: * Return true if the receive register is not empty @@ -2054,17 +2054,17 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) +static bool stm32_serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxflowcontrol + * Name: stm32_serial_rxflowcontrol * * Description: * Called when Rx buffer is full (or exceeds configured watermark levels @@ -2087,10 +2087,10 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32_FLOWCONTROL_BROKEN) @@ -2098,7 +2098,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wb_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2160,7 +2160,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareceive + * Name: stm32_serial_dmareceive * * Description: * Called (usually) from the interrupt level to receive one @@ -2170,13 +2170,13 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int c = 0; - if (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext) + if (stm32_serial_dmanextrx(priv) != priv->rxdmanext) { c = priv->rxfifo[priv->rxdmanext]; @@ -2203,7 +2203,7 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareenable + * Name: stm32_serial_dmareenable * * Description: * Call to re-enable RX DMA. @@ -2211,14 +2211,14 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) +static void stm32_serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2229,7 +2229,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2250,7 +2250,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -2261,7 +2261,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -2274,7 +2274,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) #endif /**************************************************************************** - * Name: stm32wb_serial_dmaiflowrestart + * Name: stm32_serial_dmaiflowrestart * * Description: * Call to restart RX DMA for input flow-controlled USART @@ -2282,7 +2282,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2298,7 +2298,7 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) { /* Rx DMA in suspended state. */ - if (stm32wb_serial_dmarxavailable(&priv->dev)) + if (stm32_serial_dmarxavailable(&priv->dev)) { /* DMA buffer has unprocessed data, do not re-enable yet. */ @@ -2316,14 +2316,14 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) * re-enabling without data loss is now safe. */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); return true; } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxint + * Name: stm32_serial_dmarxint * * Description: * Call to enable or disable RX interrupts @@ -2331,9 +2331,9 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2350,14 +2350,14 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxavailable + * Name: stm32_serial_dmarxavailable * * Description: * Return true if the receive register is not empty @@ -2365,51 +2365,51 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev) +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. */ - return (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext); + return (stm32_serial_dmanextrx(priv) != priv->rxdmanext); } #endif /**************************************************************************** - * Name: stm32wb_serial_send + * Name: stm32_serial_send * * Description: * This method will send one byte on the USART * ****************************************************************************/ -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) +static void stm32_serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); + stm32_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** - * Name: stm32wb_serial_txint + * Name: stm32_serial_txint * * Description: * Call to enable or disable TX interrupts * ****************************************************************************/ -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2452,7 +2452,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -2465,29 +2465,29 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_serial_txready + * Name: stm32_serial_txready * * Description: * Return true if the transmit data register is empty * ****************************************************************************/ -static bool stm32wb_serial_txready(struct uart_dev_s *dev) +static bool stm32_serial_txready(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } /**************************************************************************** - * Name: stm32wb_serial_dmarxcallback + * Name: stm32_serial_dmarxcallback * * Description: * This function checks the current DMA state and calls the generic @@ -2496,12 +2496,12 @@ static bool stm32wb_serial_txready(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - if (priv->rxenable && stm32wb_serial_dmarxavailable(&priv->dev)) + if (priv->rxenable && stm32_serial_dmarxavailable(&priv->dev)) { uart_recvchars(&priv->dev); @@ -2510,7 +2510,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2537,7 +2537,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif /**************************************************************************** - * Name: stm32wb_serial_pmnotify + * Name: stm32_serial_pmnotify * * Description: * Notify the driver of new power state. This callback is called after @@ -2559,17 +2559,17 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { switch (pmstate) { case PM_NORMAL: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_IDLE: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_STANDBY: @@ -2579,11 +2579,11 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, * Rx/Tx buffers are empty (checked in pmprepare). */ - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; case PM_SLEEP: - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; default: @@ -2594,7 +2594,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, #endif /**************************************************************************** - * Name: stm32wb_serial_pmprepare + * Name: stm32_serial_pmprepare * * Description: * Request the driver to prepare for a new power state. This is a warning @@ -2627,7 +2627,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { int n; @@ -2648,7 +2648,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wb_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2657,7 +2657,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2727,14 +2727,14 @@ void arm_earlyserialinit(void) { if (g_uart_devs[i]) { - stm32wb_serial_disableusartint(g_uart_devs[i], NULL); + stm32_serial_disableusartint(g_uart_devs[i], NULL); } } /* Configure whichever one is the console */ #if CONSOLE_UART > 0 - stm32wb_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* HAVE UART */ } @@ -2779,7 +2779,7 @@ void arm_serialinit(void) #ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ - stm32wb_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* CONSOLE_UART > 0 */ @@ -2814,7 +2814,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2825,7 +2825,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2834,14 +2834,14 @@ void stm32wb_serial_dma_poll(void) #ifdef CONFIG_LPUART1_RXDMA if (g_lpuart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + stm32_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); } #endif #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + stm32_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); } #endif @@ -2860,12 +2860,12 @@ void stm32wb_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wb_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; - stm32wb_serial_disableusartint(priv, &ie); + stm32_serial_disableusartint(priv, &ie); arm_lowputc(ch); - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 957840238ac9a..515f98920ab11 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,7 +73,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_gpio.h" #include "stm32wb_dma.h" #include "stm32wb_spi.h" @@ -131,7 +131,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -172,34 +172,34 @@ struct stm32wb_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv); -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv); -static int spi_dmatxwait(struct stm32wb_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -230,7 +230,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -247,16 +247,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32wb_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -269,13 +269,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -305,16 +305,16 @@ static struct stm32wb_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32wb_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -327,13 +327,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -376,7 +376,7 @@ static struct stm32wb_spidev_s g_spi2dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -398,7 +398,7 @@ static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -419,7 +419,7 @@ static inline void spi_putreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -438,7 +438,7 @@ static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wb_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -458,7 +458,7 @@ static inline void spi_putreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -483,7 +483,7 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -509,7 +509,7 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -536,7 +536,7 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32wb_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -562,7 +562,7 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -576,7 +576,7 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -609,7 +609,7 @@ static int spi_dmarxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmatxwait(struct stm32wb_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -642,7 +642,7 @@ static int spi_dmatxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -657,7 +657,7 @@ static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -674,7 +674,7 @@ static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -694,7 +694,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -712,7 +712,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { /* 8- or 16-bit mode? */ @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -762,7 +762,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -813,10 +813,10 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wb_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -829,10 +829,10 @@ static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wb_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -852,7 +852,7 @@ static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -886,7 +886,7 @@ static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -918,7 +918,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1026,7 +1026,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1094,7 +1094,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1162,7 +1162,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1300,7 +1300,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1401,14 +1401,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; #ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && - !stm32wb_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && - !stm32wb_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1596,8 +1596,8 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)((char *)cb - - offsetof(struct stm32wb_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1647,7 +1647,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1689,16 +1689,16 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32_SPI_DMA - /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32wb_dmachannel() + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32wb_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32wb_dmachannel(priv->rxch); - priv->txdma = stm32wb_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1723,7 +1723,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1736,9 +1736,9 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wb_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1755,9 +1755,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI1_SCK); - stm32wb_configgpio(GPIO_SPI1_MISO); - stm32wb_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1780,9 +1780,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI2_SCK); - stm32wb_configgpio(GPIO_SPI2_MISO); - stm32wb_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index 1f5d0ae1ee80e..cf19583f6263d 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wb_spi1/2/...select and stm32wb_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32wb_spi1/2/...select, - * stm32wb_spi1/2/...status, and stm32wb_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32wb_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2/...select() and stm32wb_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wb_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wb_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wb_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,21 +105,21 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32wb_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wb_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -140,12 +140,12 @@ int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32_SPI1 -int stm32wb_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI2 -int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index da2252328c9bf..6e80fa7f6d87d 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -164,15 +164,15 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wb_clockconfig(); + stm32_clockconfig(); #ifdef CONFIG_STM32_IPCC - stm32wb_ipccreset(); + stm32_ipccreset(); #endif arm_fpuconfig(); - /* Todo: stm32wb_lowsetup(); */ + /* Todo: stm32_lowsetup(); */ - stm32wb_gpioinit(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -223,13 +223,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wb_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wb_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.h b/arch/arm/src/stm32wb/stm32wb_start.h index 6c4b5757c87fe..7e9b47cd2523a 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.h +++ b/arch/arm/src/stm32wb/stm32wb_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WB_STM32_START_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index 4ef185247524c..a8ae84dc54e3d 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -52,7 +52,7 @@ * There are two interrupts generated from our timer, the overflow interrupt * which drives the timing handler and the capture/compare interrupt which * drives the interval handler. There are some low level timer control - * functions implemented here because the API of stm32wb_tim.c does not + * functions implemented here because the API of stm32_tim.c does not * provide adequate control over capture/compare interrupts. * ****************************************************************************/ @@ -96,13 +96,13 @@ * Private Types ****************************************************************************/ -struct stm32wb_tickless_s +struct stm32_tickless_s { uint8_t timer; /* The timer/counter in use */ uint8_t channel; /* The timer channel to use * for intervals */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ @@ -114,93 +114,93 @@ struct stm32wb_tickless_s * Private Data ****************************************************************************/ -static struct stm32wb_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(uint8_t offset) +static inline uint16_t stm32_getreg16(uint8_t offset) { return getreg16(g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(uint8_t offset, uint16_t value) +static inline void stm32_putreg16(uint8_t offset, uint16_t value) { putreg16(value, g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, +static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg16(g_tickless.base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_tickless_enableint + * Name: stm32_tickless_enableint ****************************************************************************/ -static inline void stm32wb_tickless_enableint(int channel) +static inline void stm32_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** - * Name: stm32wb_tickless_disableint + * Name: stm32_tickless_disableint ****************************************************************************/ -static inline void stm32wb_tickless_disableint(int channel) +static inline void stm32_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** - * Name: stm32wb_tickless_ackint + * Name: stm32_tickless_ackint ****************************************************************************/ -static inline void stm32wb_tickless_ackint(int channel) +static inline void stm32_tickless_ackint(int channel) { - stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); + stm32_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** - * Name: stm32wb_tickless_getint + * Name: stm32_tickless_getint ****************************************************************************/ -static inline uint16_t stm32wb_tickless_getint(void) +static inline uint16_t stm32_tickless_getint(void) { - return stm32wb_getreg16(STM32_TIM_SR_OFFSET); + return stm32_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tickless_setchannel + * Name: stm32_tickless_setchannel ****************************************************************************/ -static int stm32wb_tickless_setchannel(uint8_t channel) +static int stm32_tickless_setchannel(uint8_t channel) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -234,17 +234,17 @@ static int stm32wb_tickless_setchannel(uint8_t channel) ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(ccmr_offset); + ccmr_orig = stm32_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(ccmr_offset, ccmr_orig); + stm32_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } /**************************************************************************** - * Name: stm32wb_interval_handler + * Name: stm32_interval_handler * * Description: * Called when the timer counter matches the compare register @@ -261,14 +261,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) * ****************************************************************************/ -static void stm32wb_interval_handler(void) +static void stm32_interval_handler(void) { tmrinfo("Expired...\n"); /* Disable the compare interrupt now. */ - stm32wb_tickless_disableint(g_tickless.channel); - stm32wb_tickless_ackint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); g_tickless.pending = false; @@ -276,7 +276,7 @@ static void stm32wb_interval_handler(void) } /**************************************************************************** - * Name: stm32wb_timing_handler + * Name: stm32_timing_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -290,7 +290,7 @@ static void stm32wb_interval_handler(void) * ****************************************************************************/ -static void stm32wb_timing_handler(void) +static void stm32_timing_handler(void) { g_tickless.overflow++; @@ -298,7 +298,7 @@ static void stm32wb_timing_handler(void) } /**************************************************************************** - * Name: stm32wb_tickless_handler + * Name: stm32_tickless_handler * * Description: * Generic interrupt handler for this timer. It checks the source of the @@ -312,18 +312,18 @@ static void stm32wb_timing_handler(void) * ****************************************************************************/ -static int stm32wb_tickless_handler(int irq, void *context, void *arg) +static int stm32_tickless_handler(int irq, void *context, void *arg) { - int interrupt_flags = stm32wb_tickless_getint(); + int interrupt_flags = stm32_tickless_getint(); if (interrupt_flags & GTIM_SR_UIF) { - stm32wb_timing_handler(); + stm32_timing_handler(); } if (interrupt_flags & (1 << g_tickless.channel)) { - stm32wb_interval_handler(); + stm32_interval_handler(); } return OK; @@ -402,7 +402,7 @@ void up_timer_initialize(void) tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", g_tickless.timer, g_tickless.channel, g_tickless.frequency); - g_tickless.tch = stm32wb_tim_init(g_tickless.timer); + g_tickless.tch = stm32_tim_init(g_tickless.timer); if (!g_tickless.tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); @@ -413,7 +413,7 @@ void up_timer_initialize(void) /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); /* Initialize interval to zero */ @@ -421,7 +421,7 @@ void up_timer_initialize(void) /* Setup compare channel for the interval timing */ - stm32wb_tickless_setchannel(g_tickless.channel); + stm32_tickless_setchannel(g_tickless.channel); /* Set timer period */ @@ -493,7 +493,7 @@ int up_timer_gettime(struct timespec *ts) DEBUGASSERT(g_tickless.tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -679,7 +679,7 @@ int up_timer_cancel(struct timespec *ts) /* Disable the interrupt. */ - stm32wb_tickless_disableint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; @@ -829,8 +829,8 @@ int up_timer_start(const struct timespec *ts) * occurs. */ - stm32wb_tickless_ackint(g_tickless.channel); - stm32wb_tickless_enableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); + stm32_tickless_enableint(g_tickless.channel); g_tickless.pending = true; leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index f1bbe370e8034..22402ed4da183 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_tim.h" #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" @@ -128,10 +128,10 @@ /* TIM Device Structure */ -struct stm32wb_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wb_tim_ops_s *ops; - enum stm32wb_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -141,116 +141,116 @@ struct stm32wb_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq); -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wb_tim_getperiod(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev); -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source); -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source); -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wb_tim_ops_s stm32wb_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wb_tim_enable, - .disable = stm32wb_tim_disable, - .setmode = stm32wb_tim_setmode, - .setfreq = stm32wb_tim_setfreq, - .setclock = stm32wb_tim_setclock, - .getclock = stm32wb_tim_getclock, - .setperiod = stm32wb_tim_setperiod, - .getperiod = stm32wb_tim_getperiod, - .getcounter = stm32wb_tim_getcounter, - .getwidth = stm32wb_tim_getwidth, - .setchannel = stm32wb_tim_setchannel, - .setcompare = stm32wb_tim_setcompare, - .getcapture = stm32wb_tim_getcapture, - .setisr = stm32wb_tim_setisr, - .enableint = stm32wb_tim_enableint, - .disableint = stm32wb_tim_disableint, - .ackint = stm32wb_tim_ackint, - .checkint = stm32wb_tim_checkint, - .dump_regs = stm32wb_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .getwidth = stm32_tim_getwidth, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32_TIM1 -struct stm32wb_tim_priv_s stm32wb_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 -struct stm32wb_tim_priv_s stm32wb_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32_TIM16 -struct stm32wb_tim_priv_s stm32wb_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32_TIM17 -struct stm32wb_tim_priv_s stm32wb_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -261,51 +261,51 @@ struct stm32wb_tim_priv_s stm32wb_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32WB @@ -313,14 +313,14 @@ static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32WB @@ -328,49 +328,49 @@ static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -378,86 +378,86 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32wb_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wb_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wb_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wb_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wb_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32wb_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val; @@ -469,14 +469,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { #if defined(CONFIG_STM32_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif #if defined(CONFIG_STM32_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -519,15 +519,15 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, return -EINVAL; } - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); #ifdef CONFIG_STM32_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -535,10 +535,10 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -551,7 +551,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -561,7 +561,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -647,17 +647,17 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32wb_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -668,7 +668,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -678,7 +678,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -730,16 +730,16 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32wb_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -751,7 +751,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -782,44 +782,44 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wb_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wb_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -829,15 +829,15 @@ static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_getwidth + * Name: stm32_tim_getwidth ****************************************************************************/ -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -849,12 +849,12 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -872,7 +872,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ @@ -903,15 +903,15 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -919,25 +919,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -952,25 +952,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -985,7 +985,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif @@ -1000,7 +1000,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif @@ -1018,10 +1018,10 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1052,10 +1052,10 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1063,26 +1063,26 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wb_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1090,7 +1090,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1138,41 +1138,41 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** - * Name: stm32wb_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** - * Name: stm32wb_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** - * Name: stm32wb_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1181,12 +1181,12 @@ static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wb_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1194,28 +1194,28 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) { #ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,30 +1226,30 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wb_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wb_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1281,7 +1281,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index 742221eb57aff..e928d3e6ddd9b 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -101,14 +101,14 @@ extern "C" /* TIM Device Structure */ -struct stm32wb_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wb_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wb_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -145,7 +145,7 @@ enum stm32wb_tim_mode_e /* TIM Channel Modes */ -enum stm32wb_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -178,37 +178,37 @@ enum stm32wb_tim_channel_e /* TIM Operations */ -struct stm32wb_tim_ops_s +struct stm32_tim_ops_s { - void (*enable)(struct stm32wb_tim_dev_s *dev); - void (*disable)(struct stm32wb_tim_dev_s *dev); - int (*setmode)(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); - int (*setfreq)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wb_tim_dev_s *dev); - void (*setperiod)(struct stm32wb_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32wb_tim_dev_s *dev); - int (*setchannel)(struct stm32wb_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); - int (*setcompare)(struct stm32wb_tim_dev_s *dev, uint8_t channel, + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - uint32_t (*getcapture)(struct stm32wb_tim_dev_s *dev, uint8_t channel); + uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wb_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wb_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wb_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32wb_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -217,14 +217,14 @@ struct stm32wb_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -242,7 +242,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wb_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index 976cc1ba2f1c1..38e8db5b4aabb 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -58,10 +58,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wb_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -74,17 +74,17 @@ struct stm32wb_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower); -static int stm32wb_stop(struct timer_lowerhalf_s *lower); -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -95,16 +95,16 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wb_start, - .stop = stm32wb_stop, - .getstatus = stm32wb_getstatus, - .settimeout = stm32wb_settimeout, - .setcallback = stm32wb_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32_TIM1 -static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -112,7 +112,7 @@ static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32_TIM2 -static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -120,7 +120,7 @@ static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32_TIM16 -static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -128,7 +128,7 @@ static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32_TIM17 -static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -140,7 +140,7 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -151,9 +151,9 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); @@ -167,14 +167,14 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) } else { - stm32wb_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -188,9 +188,9 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -198,7 +198,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } @@ -212,7 +212,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -226,9 +226,9 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -245,7 +245,7 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -260,10 +260,10 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -311,7 +311,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -326,10 +326,10 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -354,7 +354,7 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -373,10 +373,10 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -386,7 +386,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else @@ -403,7 +403,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -420,9 +420,9 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wb_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -458,7 +458,7 @@ int stm32wb_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wb_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index 00d539eec5548..ea28a500667ed 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -77,7 +77,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -85,7 +85,7 @@ * ****************************************************************************/ -static int stm32wb_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index a6d2376bbb702..c2745718b5ce6 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -151,7 +151,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32WB UART is configured for DMA. @@ -164,7 +164,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 17a3808d3633d..e63d65cd6407a 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_uid.c + * arch/arm/src/stm32wb/stm32_uid.c * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h index 3e2694302bad4..6710825385010 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ b/arch/arm/src/stm32wb/stm32wb_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32WB_STM32_UID_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.c b/arch/arm/src/stm32wb/stm32wb_userspace.c index 6f9a3451e63dc..e07473c8d67a2 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.c +++ b/arch/arm/src/stm32wb/stm32wb_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wb_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wb_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wb_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.h b/arch/arm/src/stm32wb/stm32wb_userspace.h index b1141e5a61f65..67f2b2dbb7200 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.h +++ b/arch/arm/src/stm32wb/stm32wb_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32WB_STM32W_USERSPACE_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_waste.c b/arch/arm/src/stm32wb/stm32wb_waste.c index 48f022c7d4811..ec2fc9d9c510c 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.c +++ b/arch/arm/src/stm32wb/stm32wb_waste.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_waste.c + * arch/arm/src/stm32wb/stm32_waste.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ uint32_t g_waste_counter; * Public Functions ****************************************************************************/ -void stm32wb_waste(void) +void stm32_waste(void) { g_waste_counter++; } diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h index 4bdf7c664b3c6..64e7e6b0943fa 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ b/arch/arm/src/stm32wb/stm32wb_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32wb_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a * measure of badly written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32wb_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index 3fd4a8e6665ac..a0119be94cd06 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -113,7 +113,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -123,7 +123,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/src/flipperzero.h b/boards/arm/stm32wb/flipperzero/src/flipperzero.h index feaab95878f60..6bb7850aefdd5 100644 --- a/boards/arm/stm32wb/flipperzero/src/flipperzero.h +++ b/boards/arm/stm32wb/flipperzero/src/flipperzero.h @@ -82,7 +82,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. @@ -90,7 +90,7 @@ ****************************************************************************/ #ifdef CONFIG_SPI -void weak_function stm32wb_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index 824b7657b122b..2f549b32aac0a 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,16 +68,16 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ #ifdef CONFIG_SPI - if (stm32wb_spidev_initialize) + if (stm32_spidev_initialize) { - stm32wb_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -142,7 +142,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -166,7 +166,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -186,7 +186,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif } #endif @@ -206,7 +206,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index 4eea343833db8..de3771d606233 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -55,14 +55,14 @@ * Private Function Prototypes ****************************************************************************/ -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on); -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on); +static void stm32_st7565_select(struct st7565_lcd_s *lcd); +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd); +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd); -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size); -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level); +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level); /**************************************************************************** * Private Data @@ -73,43 +73,43 @@ static struct lcd_dev_s *g_lcddev; static struct st7565_lcd_s g_st7565_dev = { - .reset = stm32wb_st7565_reset, - .select = stm32wb_st7565_select, - .deselect = stm32wb_st7565_deselect, - .cmddata = stm32wb_st7565_cmddata, - .senddata = stm32wb_st7565_senddata, - .backlight = stm32wb_st7565_backlight + .reset = stm32_st7565_reset, + .select = stm32_st7565_select, + .deselect = stm32_st7565_deselect, + .cmddata = stm32_st7565_cmddata, + .senddata = stm32_st7565_senddata, + .backlight = stm32_st7565_backlight }; -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32_LCD_RST, !on); + stm32_gpiowrite(STM32_LCD_RST, !on); } -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) +static void stm32_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 0); + stm32_gpiowrite(STM32_LCD_CS, 0); } -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 1); + stm32_gpiowrite(STM32_LCD_CS, 1); } -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32_LCD_A0, !cmd); + stm32_gpiowrite(STM32_LCD_A0, !cmd); } -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size) { SPI_SNDBLOCK(g_spidev, data, size); return 0; } -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level) { return 0; } @@ -124,10 +124,10 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32_LCD_RST); - stm32wb_configgpio(STM32_LCD_A0); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); + g_spidev = stm32_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index 73c786f5b8a9d..fedf459eceed2 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -40,45 +40,45 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32wb_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { - /* NOTE: Clocking was already provided in stm32wb_rcc.c. + /* NOTE: Clocking was already provided in stm32_rcc.c. * Here, we only initialize chip select pins unique to the board * architecture. */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ + stm32_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } /**************************************************************************** - * Name: stm32wb_spi1/2select and stm32wb_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -86,17 +86,17 @@ void weak_function stm32wb_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h index f2c7d7d485140..479d2c17f7aec 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h @@ -183,7 +183,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -193,7 +193,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c index 1b81d27c678ea..61ff88b7ea0cd 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifdef CONFIG_ARCH_LEDS @@ -51,9 +51,9 @@ void board_autoled_initialize(void) { /* Configure LEDs GPIO for output. Initial state is OFF */ - stm32wb_configgpio(GPIO_LED1); - stm32wb_configgpio(GPIO_LED2); - stm32wb_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); } /**************************************************************************** @@ -68,15 +68,15 @@ void board_autoled_on(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, true); + stm32_gpiowrite(GPIO_LED1, true); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, true); + stm32_gpiowrite(GPIO_LED3, true); break; } } @@ -93,15 +93,15 @@ void board_autoled_off(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED1, false); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, false); + stm32_gpiowrite(GPIO_LED3, false); break; } } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index 62991d13e56ed..ff849aff0dbc2 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,7 +68,7 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -131,7 +131,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -155,7 +155,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -167,7 +167,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif UNUSED(ret); } @@ -188,7 +188,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c index 054482588dfb5..6c911a423c868 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifndef CONFIG_ARCH_LEDS @@ -94,8 +94,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -160,9 +160,9 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, uint32_t board_userled_initialize(void) { - stm32wb_configgpio(GPIO_LED_RED); - stm32wb_configgpio(GPIO_LED_GREEN); - stm32wb_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); return BOARD_NLEDS; } @@ -178,15 +178,15 @@ void board_userled(int led, bool ledon) break; case BOARD_LED_RED: - stm32wb_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case GPIO_LED_GREEN: - stm32wb_gpiowrite(GPIO_LED_GREEN, ledon); + stm32_gpiowrite(GPIO_LED_GREEN, ledon); break; case GPIO_LED_BLUE: - stm32wb_gpiowrite(GPIO_LED_BLUE, ledon); + stm32_gpiowrite(GPIO_LED_BLUE, ledon); break; } } @@ -197,9 +197,9 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32wb_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); } /**************************************************************************** From ed269bfde4640b03e0b1e27ace8e8535214f1c03 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:59 +0200 Subject: [PATCH 09/52] !arm/stm32wl5: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32WL5 interfaces were renamed from stm32wl5_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32WL5 timer/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32WL5 root family header was renamed from stm32wl5.h to stm32.h; all STM32WL5 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32wl5/{stm32wl5.h => stm32.h} | 6 +- arch/arm/src/stm32wl5/stm32wl5_allocateheap.c | 4 +- arch/arm/src/stm32wl5/stm32wl5_exti.h | 16 +- arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c | 40 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 16 +- arch/arm/src/stm32wl5/stm32wl5_flash.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_gpio.c | 28 +- arch/arm/src/stm32wl5/stm32wl5_gpio.h | 36 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.c | 110 ++--- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_irq.c | 40 +- arch/arm/src/stm32wl5/stm32wl5_lowputc.c | 20 +- arch/arm/src/stm32wl5/stm32wl5_lowputc.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_lse.c | 10 +- arch/arm/src/stm32wl5/stm32wl5_lsi.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_mpuinit.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_mpuinit.h | 12 +- arch/arm/src/stm32wl5/stm32wl5_pwr.c | 20 +- arch/arm/src/stm32wl5/stm32wl5_pwr.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 66 +-- arch/arm/src/stm32wl5/stm32wl5_rcc.h | 42 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 198 ++++---- arch/arm/src/stm32wl5/stm32wl5_spi.c | 162 +++--- arch/arm/src/stm32wl5/stm32wl5_spi.h | 40 +- arch/arm/src/stm32wl5/stm32wl5_start.c | 12 +- arch/arm/src/stm32wl5/stm32wl5_start.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_tim.c | 460 +++++++++--------- arch/arm/src/stm32wl5/stm32wl5_tim.h | 54 +- .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 110 ++--- arch/arm/src/stm32wl5/stm32wl5_timerisr.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_uart.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_uid.c | 4 +- arch/arm/src/stm32wl5/stm32wl5_uid.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_userspace.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_userspace.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_waste.c | 4 +- arch/arm/src/stm32wl5/stm32wl5_waste.h | 4 +- .../stm32wl5/nucleo-wl55jc/include/board.h | 4 +- .../nucleo-wl55jc/src/nucleo-wl55jc.h | 10 +- .../stm32wl5/nucleo-wl55jc/src/stm32_boot.c | 16 +- .../nucleo-wl55jc/src/stm32_buttons.c | 18 +- .../stm32wl5/nucleo-wl55jc/src/stm32_flash.c | 2 +- .../stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c | 4 +- .../stm32wl5/nucleo-wl55jc/src/stm32_leds.c | 20 +- .../stm32wl5/nucleo-wl55jc/src/stm32_spi.c | 95 +--- .../nucleo-wl55jc/src/stm32_ssd1680.c | 14 +- 46 files changed, 855 insertions(+), 908 deletions(-) rename arch/arm/src/stm32wl5/{stm32wl5.h => stm32.h} (95%) diff --git a/arch/arm/src/stm32wl5/stm32wl5.h b/arch/arm/src/stm32wl5/stm32.h similarity index 95% rename from arch/arm/src/stm32wl5/stm32wl5.h rename to arch/arm/src/stm32wl5/stm32.h index 28852b00d7979..3fe581bc7f3d3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5.h +++ b/arch/arm/src/stm32wl5/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5.h + * arch/arm/src/stm32wl5/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -55,13 +55,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32wl5_spidev_initialize(void); +void stm32_spidev_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index af951cb75bf90..29422cc4b0bd3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -192,7 +192,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wl5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -270,7 +270,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32wl5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti.h b/arch/arm/src/stm32wl5/stm32wl5_exti.h index 2930a4e3473c7..1ea988fbaf38e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/stm32wl5_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wl5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32_COMP -int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index f94f6f9bbdabf..eec0c58a667c0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -66,7 +66,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wl5_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -87,7 +87,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -108,7 +108,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -129,7 +129,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -150,7 +150,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -171,7 +171,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -215,14 +215,14 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wl5_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,7 +252,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -273,37 +273,37 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32wl5_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wl5_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wl5_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wl5_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wl5_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32wl5_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32wl5_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,7 +349,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wl5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 41c5793caeaaa..40737cbe8012c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -95,7 +95,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -145,7 +145,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -155,7 +155,7 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -int stm32wl5_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -171,7 +171,7 @@ int stm32wl5_flash_unlock(void) return ret; } -int stm32wl5_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -188,7 +188,7 @@ int stm32wl5_flash_lock(void) } /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -204,7 +204,7 @@ int stm32wl5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -242,7 +242,7 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -457,7 +457,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.h b/arch/arm/src/stm32wl5/stm32wl5_flash.h index 8e4ab01607789..063b45e36ab7d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.h @@ -36,11 +36,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32wl5_flash_lock(void); -int stm32wl5_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -56,6 +56,6 @@ int stm32wl5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index b3ec90cac4cb1..402d44079f963 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -80,13 +80,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -94,17 +94,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32wl5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -115,7 +115,7 @@ void stm32wl5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -158,7 +158,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wl5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -317,7 +317,7 @@ int stm32wl5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -337,7 +337,7 @@ int stm32wl5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -346,18 +346,18 @@ int stm32wl5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wl5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -391,14 +391,14 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 04b306205c9f2..7cfdb7fac2f10 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32wl5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -244,12 +244,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -258,10 +258,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -280,30 +280,30 @@ int stm32wl5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -322,11 +322,11 @@ bool stm32wl5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wl5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -334,23 +334,23 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wl5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wl5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wl5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index d625e58f1e683..e8960ddced0b3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -35,7 +35,7 @@ #include #include "hardware/stm32wl5_ipcc.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_ipcc.h" /**************************************************************************** @@ -44,7 +44,7 @@ /* This structure describes tx or rx of single channel in memory */ -struct stm32wl5_ipcc_chan_mem_s +struct stm32_ipcc_chan_mem_s { unsigned len; /* Number of valid bytes in data[] */ char data[]; /* Data in IPCC memory */ @@ -52,7 +52,7 @@ struct stm32wl5_ipcc_chan_mem_s /* Internal stm32wl5 ipcc structure describing channel state. */ -struct stm32wl5_ipcc_s +struct stm32_ipcc_s { /* Pointer to API connecting upper and lower half of the driver */ @@ -65,14 +65,14 @@ struct stm32wl5_ipcc_s char *rxmem; /* Maximum length of data that rxmem can hold. It is size of the - * reserved space for rxmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for rxmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned rxlen; /* Number of bytes copied from IPCC memory to buffer. Can be less than - * stm32wl5_ipcc_chan_mem_s.len after copy operation when buffer is full. - * Value can persist between multiple ISR and stm32wl5_ipcc_buffer_data() + * stm32_ipcc_chan_mem_s.len after copy operation when buffer is full. + * Value can persist between multiple ISR and stm32_ipcc_buffer_data() * calls, until all data from IPCC memory is successfully buffered. * * When unbuffered version is used, this holds number of bytes already @@ -89,7 +89,7 @@ struct stm32wl5_ipcc_s char *txmem; /* Maximum length of data that txmem can hold. It is size of the - * reserved space for txmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for txmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned txlen; @@ -99,24 +99,24 @@ struct stm32wl5_ipcc_s * Private Function Prototypes ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen); -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen); #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf); -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf); #endif -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg); -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = +struct stm32_ipcc_s g_ipccpriv[IPCC_NCHAN] = { /* Channel 1 is always enabled when IPCC is enabled */ @@ -183,7 +183,7 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_tx_isr + * Name: stm32_ipcc_tx_isr * * Description: * IPCC TX interrupt service routine. This interrupt is called when @@ -209,16 +209,16 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = * ****************************************************************************/ -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED size_t nwritten; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_chan_mem_s *txmem; #endif UNUSED(context); @@ -251,7 +251,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Copy as much as we can into IPCC memory, circbuf won't copy * more than there is in the buffer. @@ -297,7 +297,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_write + * Name: stm32_ipcc_write * * Description: * Function writes buffer to IPCC memory that will be later read by @@ -316,12 +316,12 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen) { size_t to_copy; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *txmem; uint32_t sr; sr = getreg32(STM32_IPCC_C1TOC2SR); @@ -339,7 +339,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, } priv = &g_ipccpriv[ipcc->chan]; - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Disable TX interrupt since we will modify shared data */ @@ -366,7 +366,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, } /**************************************************************************** - * Name: stm32wl5_ipcc_rx_isr + * Name: stm32_ipcc_rx_isr * * Description: * Interrupt service routine - this function is called when another CPU @@ -389,13 +389,13 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * ****************************************************************************/ -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED ssize_t nread; #endif @@ -429,7 +429,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - nread = stm32wl5_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); + nread = stm32_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); if (nread) #endif /* CONFIG_IPCC_BUFFERED */ @@ -454,7 +454,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_read + * Name: stm32_ipcc_read * * Description: * Function will copy requests number of bytes to buffer. If there is not @@ -477,13 +477,13 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen) { size_t to_copy; uint32_t sr; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; sr = getreg32(STM32_IPCC_C2TOC1SR); @@ -498,7 +498,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, } priv = &g_ipccpriv[ipcc->chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* Disable RX interrupt since we will modify shared data */ @@ -541,7 +541,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, } /**************************************************************************** - * Name: stm32wl5_ipcc_copy_to_buffer + * Name: stm32_ipcc_copy_to_buffer * * Description: * Copies as much bytes from channel as possible to rxbuf circ buffer. @@ -560,13 +560,13 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf) { size_t to_copy; size_t rxbuf_space; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; uint32_t sr; sr = getreg32(STM32_IPCC_C2TOC1SR); @@ -582,7 +582,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, } priv = &g_ipccpriv[chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* If buffer is full, it's possible we did not copy everything from * IPCC memory to buffer in previous interrupt. Then when another @@ -641,7 +641,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_buffer_data + * Name: stm32_ipcc_buffer_data * * Description: * Copies as many bytes as possible from ipcc channel to rxbuf. @@ -658,7 +658,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf) { int ret; @@ -669,7 +669,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Copy data to buffer */ - ret = stm32wl5_ipcc_copy_to_buffer(ipcc->chan, rxbuf); + ret = stm32_ipcc_copy_to_buffer(ipcc->chan, rxbuf); /* Re-enable interrupt */ @@ -682,7 +682,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_write_notify + * Name: stm32_ipcc_write_notify * * Description: * This function is called when there is new data on circ buffer. @@ -699,7 +699,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) +static ssize_t stm32_ipcc_write_notify(struct ipcc_lower_s *ipcc) { modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; @@ -707,10 +707,10 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) #endif /**************************************************************************** - * Name: stm32wl5_ipcc_cleanup + * Name: stm32_ipcc_cleanup * * Description: - * Cleans up resources initialized by stm32wl5_ipcc_init(). This will + * Cleans up resources initialized by stm32_ipcc_init(). This will * free() ipcc pointer! * * Input Parameters: @@ -721,7 +721,7 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) +static int stm32_ipcc_cleanup(struct ipcc_lower_s *ipcc) { DEBUGASSERT(ipcc); DEBUGASSERT(ipcc->chan <= IPCC_NCHAN); @@ -743,7 +743,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_init + * Name: stm32_ipcc_init * * Description: * Function initializes runtime options for IPCC. This function is called @@ -762,7 +762,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) +struct ipcc_lower_s *stm32_ipcc_init(int chan) { int ret; static int ipcc_fti; @@ -786,12 +786,12 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * upper half needs to call to work properly. */ - ipcc->ops.read = stm32wl5_ipcc_read; - ipcc->ops.write = stm32wl5_ipcc_write; - ipcc->ops.cleanup = stm32wl5_ipcc_cleanup; + ipcc->ops.read = stm32_ipcc_read; + ipcc->ops.write = stm32_ipcc_write; + ipcc->ops.cleanup = stm32_ipcc_cleanup; #ifdef CONFIG_IPCC_BUFFERED - ipcc->ops.buffer_data = stm32wl5_ipcc_buffer_data; - ipcc->ops.write_notify = stm32wl5_ipcc_write_notify; + ipcc->ops.buffer_data = stm32_ipcc_buffer_data; + ipcc->ops.write_notify = stm32_ipcc_write_notify; #endif ipcc->chan = chan; @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 2de8022042e4f..bd420571efc44 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -142,6 +142,6 @@ IPCC_CHAN3_SIZE + IPCC_CHAN4_SIZE + \ IPCC_CHAN5_SIZE + IPCC_CHAN6_SIZE) -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan); +struct ipcc_lower_s *stm32_ipcc_init(int chan); #endif /* __ARCH_ARM_SRC_STM32WL5_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index b0b25e844bce9..3fc635c72f7e9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wl5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wl5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wl5_nmi, stm32wl5_pendsv, stm32wl5_pendsv, stm32wl5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wl5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32wl5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wl5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -158,7 +158,7 @@ static int stm32wl5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wl5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -168,7 +168,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wl5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -176,7 +176,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wl5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -189,7 +189,7 @@ static inline void stm32wl5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wl5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -197,7 +197,7 @@ static inline void stm32wl5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -323,7 +323,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -337,19 +337,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wl5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -374,7 +374,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -409,7 +409,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -486,7 +486,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wl5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 474315559282d..fd992865e706e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -34,7 +34,7 @@ #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_rcc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_uart.h" @@ -241,7 +241,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -252,7 +252,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -260,7 +260,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -269,7 +269,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wl5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -285,19 +285,19 @@ void stm32wl5_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wl5_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32wl5_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32wl5_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h index 144d1b952985b..f4c7d186d3b10 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index b888f633ed9d6..4ab6997b283c8 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -69,14 +69,14 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { int writable; uint32_t regval; @@ -101,7 +101,7 @@ void stm32wl5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32wl5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -174,7 +174,7 @@ void stm32wl5_rcc_enablelse(void) while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32wl5_waste(); + stm32_waste(); } } @@ -189,6 +189,6 @@ void stm32wl5_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - (void)stm32wl5_pwr_enablebkp(writable); + (void)stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index 5b5b36395dfd6..12ce587823d89 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32wl5_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c index beab699c02548..07fe40f5aefc2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wl5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wl5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wl5_mpuinitialize(void) * ****************************************************************************/ -void stm32wl5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h index 3d905a8597f3e..4ea88ebba9892 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wl5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wl5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wl5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index 1e0fa17138968..001302dab922f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -40,17 +40,17 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, @@ -62,7 +62,7 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -76,14 +76,14 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -111,7 +111,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -119,7 +119,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void) +void stm32_pwr_boot_c2(void) { modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/stm32wl5_pwr.h index 7d0d4176c86ff..824bb05fe19f7 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -79,7 +79,7 @@ bool stm32wl5_pwr_enablebkp(bool writable); * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void); +void stm32_pwr_boot_c2(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index d24b20e16d330..37174ffbf6b19 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -38,7 +38,7 @@ #include "chip.h" #include "stm32wl5_rcc.h" #include "stm32wl5_flash.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_waste.h" /**************************************************************************** @@ -75,13 +75,13 @@ ****************************************************************************/ #if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) -static inline void stm32wl5_rcc_resetbkp(void) +static inline void stm32_rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32wl5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -98,7 +98,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * backup data registers and backup SRAM). */ - (void)stm32wl5_pwr_enablebkp(true); + (void)stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -119,7 +119,7 @@ static inline void stm32wl5_rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - (void)stm32wl5_pwr_enablebkp(false); + (void)stm32_pwr_enablebkp(false); } } #else @@ -141,7 +141,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -151,7 +151,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * ****************************************************************************/ -void stm32wl5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -166,7 +166,7 @@ void stm32wl5_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -174,13 +174,13 @@ void stm32wl5_clockconfig(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32wl5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -191,7 +191,7 @@ void stm32wl5_clockconfig(void) * ****************************************************************************/ -static void stm32wl5_rcc_enableahb1(void) +static void stm32_rcc_enableahb1(void) { uint32_t regval; @@ -230,7 +230,7 @@ static void stm32wl5_rcc_enableahb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb2(void) +static inline void stm32_rcc_enableahb2(void) { uint32_t regval; @@ -267,7 +267,7 @@ static inline void stm32wl5_rcc_enableahb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb3(void) +static inline void stm32_rcc_enableahb3(void) { uint32_t regval; @@ -312,7 +312,7 @@ static inline void stm32wl5_rcc_enableahb3(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb1(void) +static inline void stm32_rcc_enableapb1(void) { uint32_t regval; @@ -405,7 +405,7 @@ static inline void stm32wl5_rcc_enableapb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb2(void) +static inline void stm32_rcc_enableapb2(void) { uint32_t regval; @@ -462,7 +462,7 @@ static inline void stm32wl5_rcc_enableapb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableccip(void) +static inline void stm32_rcc_enableccip(void) { uint32_t regval; @@ -545,12 +545,12 @@ static inline void stm32wl5_rcc_enableccip(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -561,13 +561,13 @@ static inline void stm32wl5_rcc_enableccip(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -575,28 +575,28 @@ void stm32wl5_clockenable(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif } #endif /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { - stm32wl5_rcc_enableccip(); - stm32wl5_rcc_enableahb1(); - stm32wl5_rcc_enableahb2(); - stm32wl5_rcc_enableahb3(); - stm32wl5_rcc_enableapb1(); - stm32wl5_rcc_enableapb2(); + stm32_rcc_enableccip(); + stm32_rcc_enableahb1(); + stm32_rcc_enableahb2(); + stm32_rcc_enableahb3(); + stm32_rcc_enableapb1(); + stm32_rcc_enableapb2(); } /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -606,7 +606,7 @@ void stm32wl5_rcc_enableperipherals(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void) +void stm32_stdclockconfig(void) { uint32_t regval; @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -852,7 +852,7 @@ void stm32wl5_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wl5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index ca5f15e5ece4e..5b1cd5dc7ef67 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32wl562xx @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32wl5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -88,7 +88,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -98,7 +98,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -108,10 +108,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32wl5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wl5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WL5 board may replace the "standard" board clock configuration @@ -120,11 +120,11 @@ void stm32wl5_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32wl5_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -135,11 +135,11 @@ void stm32wl5_board_clockconfig(void); ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void); +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -148,12 +148,12 @@ void stm32wl5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -164,11 +164,11 @@ void stm32wl5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -181,30 +181,30 @@ void stm32wl5_clockenable(void); * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -213,7 +213,7 @@ void stm32wl5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index a4b7992e24885..757055353331c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -182,7 +182,7 @@ * Private Types ****************************************************************************/ -struct stm32wl5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -297,9 +297,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev); static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev); static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv); +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv); +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev); @@ -393,7 +393,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER -static struct stm32wl5_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -453,7 +453,7 @@ static struct stm32wl5_serial_s g_lpuart1priv = #endif #ifdef CONFIG_STM32_USART1_SERIALDRIVER -static struct stm32wl5_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -515,7 +515,7 @@ static struct stm32wl5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32_USART2_SERIALDRIVER -static struct stm32wl5_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -576,7 +576,7 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wl5_serial_s * const +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32_LPUART1_SERIALDRIVER @@ -614,7 +614,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) +uint32_t stm32wl5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -624,7 +624,7 @@ uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, +void stm32wl5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -635,7 +635,7 @@ void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, ****************************************************************************/ static inline -void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) +void stm32wl5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -662,7 +662,7 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * Name: up_restoreusartint ****************************************************************************/ -static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -678,7 +678,7 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, * Name: stm32wl5serial_disableusartint ****************************************************************************/ -static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -739,11 +739,11 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) +static int stm32wl5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wl5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -760,8 +760,8 @@ static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32wl5serial_setformat(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -921,7 +921,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -940,7 +940,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wl5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -969,7 +969,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1010,7 +1010,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32wl5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1059,7 +1059,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1085,8 +1085,8 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1139,14 +1139,14 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32wl5serial_setup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wl5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1157,18 +1157,18 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1182,15 +1182,15 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wl5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_configgpio(priv->rs485_dir_gpio); - stm32wl5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1265,8 +1265,8 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1283,14 +1283,14 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wl5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1301,7 +1301,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1328,7 +1328,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -1339,7 +1339,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -1358,8 +1358,8 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) static void stm32wl5serial_shutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1390,32 +1390,32 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wl5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1432,8 +1432,8 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1441,11 +1441,11 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wl5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1468,8 +1468,8 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) static int stm32wl5serial_attach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1500,8 +1500,8 @@ static int stm32wl5serial_attach(struct uart_dev_s *dev) static void stm32wl5serial_detach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1521,7 +1521,7 @@ static void stm32wl5serial_detach(struct uart_dev_s *dev) static int stm32wl5serial_interrupt(int irq, void *context, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1581,7 +1581,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32wl5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } @@ -1648,8 +1648,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1658,9 +1658,9 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wl5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32wl5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1668,7 +1668,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32wl5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1723,7 +1723,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1734,7 +1734,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1960,7 +1960,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wl5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1977,7 +1977,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2040,8 +2040,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, static int stm32wl5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2070,8 +2070,8 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2130,8 +2130,8 @@ static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2165,8 +2165,8 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32_FLOWCONTROL_BROKEN) @@ -2174,7 +2174,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wl5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2249,8 +2249,8 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32wl5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2288,14 +2288,14 @@ static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2306,7 +2306,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2327,7 +2327,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -2338,7 +2338,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -2359,7 +2359,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2410,8 +2410,8 @@ static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2445,8 +2445,8 @@ static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2466,13 +2466,13 @@ static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2489,8 +2489,8 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2558,8 +2558,8 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wl5serial_txready(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); @@ -2578,7 +2578,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32wl5serial_dmarxavailable(&priv->dev)) { @@ -2736,7 +2736,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wl5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2745,7 +2745,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2909,7 +2909,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2920,7 +2920,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2962,7 +2962,7 @@ void stm32wl5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wl5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32wl5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 11152797cb9a9..9c7f0008af69b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wl5_spi1/2select and stm32wl5_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). - * All other methods (including stm32wl5_spibus_initialize()) are provided + * All other methods (including stm32_spibus_initialize()) are provided * by common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -67,7 +67,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #ifdef CONFIG_STM32_SPI_DMA #include "stm32wl5_dma.h" @@ -155,7 +155,7 @@ * Private Types ****************************************************************************/ -struct stm32wl5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -196,45 +196,45 @@ struct stm32wl5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value); -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv); -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); /* DMA support */ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv); -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -267,7 +267,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /**************************************************************************** * Private Data @@ -277,16 +277,16 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, - .select = stm32wl5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -299,7 +299,7 @@ static const struct spi_ops_s g_sp1iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif @@ -310,7 +310,7 @@ static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -345,16 +345,16 @@ static struct stm32wl5_spidev_s g_spi1dev = static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, - .select = stm32wl5_spi2s2select, + .select = stm32_spi2s2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi2s2status, + .status = stm32_spi2s2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi2s2cmddata, + .cmddata = stm32_spi2s2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -367,7 +367,7 @@ static const struct spi_ops_s g_sp2iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_s2register, /* provided externally */ + .registercallback = stm32_s2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif @@ -380,7 +380,7 @@ static uint8_t g_spi2s2_rxbuf[SPI2S2_DMABUFSIZE_ADJUSTED] SPI2S2_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi2s2dev = +static struct stm32_spidev_s g_spi2s2dev = { .spidev = { @@ -427,7 +427,7 @@ static struct stm32wl5_spidev_s g_spi2s2dev = * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -448,7 +448,7 @@ static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -470,7 +470,7 @@ static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { @@ -493,7 +493,7 @@ static inline void spi_putreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { @@ -514,7 +514,7 @@ static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -563,7 +563,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -593,7 +593,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -626,7 +626,7 @@ static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -659,7 +659,7 @@ static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -674,7 +674,7 @@ static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -691,7 +691,7 @@ static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -711,7 +711,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -729,7 +729,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -780,7 +780,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -831,10 +831,10 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wl5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -847,10 +847,10 @@ static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32_SPI_DMA -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wl5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -870,7 +870,7 @@ static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr1(struct stm32wl5_spidev_s *priv, +static void spi_modifycr1(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { @@ -900,7 +900,7 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, +static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; @@ -935,7 +935,7 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -968,7 +968,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1069,7 +1069,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1168,7 +1168,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1237,7 +1237,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1301,7 +1301,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1359,7 +1359,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1460,7 +1460,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; void *xbuffer = rxbuffer; int ret; @@ -1495,9 +1495,9 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && priv->txbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && priv->rxbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region fall back to non-DMA method. */ @@ -1602,7 +1602,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, static int spi_trigger(struct spi_dev_s *dev) { #ifdef CONFIG_STM32_SPI_DMA - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) { @@ -1695,7 +1695,7 @@ static void spi_recvblock(struct spi_dev_s *dev, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1736,18 +1736,18 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) #ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { - /* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign * the DMA channel. If the channel is not available, then - * stm32wl5_dmachannel() will block and wait until the channel becomes + * stm32_dmachannel() will block and wait until the channel becomes * available. * WARNING: If you have another device sharing a DMA channel with * SPI and the code never releases that channel, then the call to - * stm32wl5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32wl5_dmachannel(priv->rxch); - priv->txdma = stm32wl5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); @@ -1769,7 +1769,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1782,9 +1782,9 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wl5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1801,9 +1801,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI1_SCK); - stm32wl5_configgpio(GPIO_SPI1_MISO); - stm32wl5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1826,9 +1826,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI2S2 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI2S2_SCK); - stm32wl5_configgpio(GPIO_SPI2S2_MISO); - stm32wl5_configgpio(GPIO_SPI2S2_MOSI); + stm32_configgpio(GPIO_SPI2S2_SCK); + stm32_configgpio(GPIO_SPI2S2_MISO); + stm32_configgpio(GPIO_SPI2S2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.h b/arch/arm/src/stm32wl5/stm32wl5_spi.h index 76e994a6abb6f..aa505c047b8da 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.h @@ -61,7 +61,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -74,33 +74,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wl5_spi1/2select and stm32wl5_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wl5_spi1/2select, stm32wl5_spi1/2status, - * and stm32wl5_spi1/2cmddata must be provided by board-specific logic. + * The external functions, stm32_spi1/2select, stm32_spi1/2status, + * and stm32_spi1/2cmddata must be provided by board-specific logic. * These are implementations of the select, status, and cmddata methods of * the SPI interface defined by struct spi_ops_s (see * include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will * perform chip selection and status operations using GPIOs in the way * your board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wl5_spi1/2cmddata() functions in your board- + * then provide stm32_spi1/2cmddata() functions in your board- * specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wl5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wl5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -108,21 +108,21 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wl5_spi1/2s2register + * Name: stm32_spi1/2s2register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -143,12 +143,12 @@ int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32_SPI1 -int stm32wl5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32_SPI2S2 -int stm32wl5_spi2s2register(struct spi_dev_s *dev, +int stm32_spi2s2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index 0fe20a8d81b7c..24a7a9c240a8a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_userspace.h" #include "stm32wl5_start.h" @@ -153,9 +153,9 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wl5_clockconfig(); - stm32wl5_lowsetup(); - stm32wl5_gpioinit(); + stm32_clockconfig(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -202,13 +202,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wl5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wl5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.h b/arch/arm/src/stm32wl5/stm32wl5_start.h index 0463fd2c8d99b..254676852790a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.h +++ b/arch/arm/src/stm32wl5/stm32wl5_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_START_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 2c6e4a68d3eea..56bcfa281f6a2 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -41,7 +41,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_tim.h" @@ -209,10 +209,10 @@ /* TIM Device Structure */ -struct stm32wl5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wl5_tim_ops_s *ops; - enum stm32wl5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -222,179 +222,179 @@ struct stm32wl5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wl5_tim_getperiod(struct stm32wl5_tim_dev_s *dev); -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev); -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wl5_tim_enable, - .disable = stm32wl5_tim_disable, - .setmode = stm32wl5_tim_setmode, - .setclock = stm32wl5_tim_setclock, - .getclock = stm32wl5_tim_getclock, - .setperiod = stm32wl5_tim_setperiod, - .getperiod = stm32wl5_tim_getperiod, - .getcounter = stm32wl5_tim_getcounter, - .setchannel = stm32wl5_tim_setchannel, - .setcompare = stm32wl5_tim_setcompare, - .getcapture = stm32wl5_tim_getcapture, - .setisr = stm32wl5_tim_setisr, - .enableint = stm32wl5_tim_enableint, - .disableint = stm32wl5_tim_disableint, - .ackint = stm32wl5_tim_ackint, - .checkint = stm32wl5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; #ifdef CONFIG_STM32_TIM1 -struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 -struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32_TIM3 -struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32_TIM4 -struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32_TIM5 -struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32_TIM6 -struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32_TIM7 -struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32_TIM8 -struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32_TIM15 -struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32_TIM16 -struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32_TIM17 -struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -405,51 +405,51 @@ struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wl5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -457,14 +457,14 @@ static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -472,48 +472,48 @@ static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -521,14 +521,14 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32wl5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wl5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -536,28 +536,28 @@ static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wl5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wl5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wl5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -568,10 +568,10 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -611,16 +611,16 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, return -EINVAL; } - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -629,10 +629,10 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -644,7 +644,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, if (freq == 0) { - stm32wl5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -654,7 +654,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -747,17 +747,17 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32wl5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32wl5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -769,7 +769,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -839,46 +839,46 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wl5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wl5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wl5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: @@ -897,12 +897,12 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wl5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -930,10 +930,10 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -979,15 +979,15 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -995,25 +995,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1028,25 +1028,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1061,25 +1061,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1094,24 +1094,24 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1126,25 +1126,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1159,25 +1159,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1192,25 +1192,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1225,25 +1225,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1258,25 +1258,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1294,10 +1294,10 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1328,10 +1328,10 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1339,26 +1339,26 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wl5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1366,7 +1366,7 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1454,44 +1454,44 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32wl5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32wl5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32wl5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1500,12 +1500,12 @@ static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wl5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1513,76 +1513,76 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) { #ifdef CONFIG_STM32_TIM1 case 1: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM3 case 3: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32_TIM4 case 4: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32_TIM5 case 5: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32_TIM6 case 6: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32_TIM7 case 7: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32_TIM8 case 8: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32_TIM15 case 15: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,30 +1593,30 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wl5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wl5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: @@ -1689,7 +1689,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 50a48d7e25204..7bdffaa7800fa 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -72,14 +72,14 @@ extern "C" /* TIM Device Structure */ -struct stm32wl5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wl5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wl5_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -116,7 +116,7 @@ enum stm32wl5_tim_mode_e /* TIM Channel Modes */ -enum stm32wl5_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -139,36 +139,36 @@ enum stm32wl5_tim_channel_e /* TIM Operations */ -struct stm32wl5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32wl5_tim_dev_s *dev); - void (*disable)(struct stm32wl5_tim_dev_s *dev); - int (*setmode)(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); - int (*setclock)(struct stm32wl5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wl5_tim_dev_s *dev); - void (*setperiod)(struct stm32wl5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wl5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wl5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); - int (*setcompare)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32wl5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wl5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wl5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wl5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -177,14 +177,14 @@ struct stm32wl5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -202,7 +202,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wl5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 7403d50314f19..233008d82f047 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wl5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wl5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32wl5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower); -static int stm32wl5_stop(struct timer_lowerhalf_s *lower); -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,16 +110,16 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wl5_start, - .stop = stm32wl5_stop, - .getstatus = stm32wl5_getstatus, - .settimeout = stm32wl5_settimeout, - .setcallback = stm32wl5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32_TIM1 -static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -127,7 +127,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32_TIM2 -static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -135,7 +135,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32_TIM3 -static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -143,7 +143,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32_TIM4 -static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -151,7 +151,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32_TIM5 -static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -159,7 +159,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32_TIM6 -static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -167,7 +167,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32_TIM7 -static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -175,7 +175,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32_TIM8 -static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -183,7 +183,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32_TIM15 -static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -191,7 +191,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32_TIM16 -static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -199,7 +199,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32_TIM17 -static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -211,7 +211,7 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,10 +222,10 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wl5_lowerhalf_s *lower = - (struct stm32wl5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -239,14 +239,14 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) } else { - stm32wl5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wl5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,10 +260,10 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -271,7 +271,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -285,7 +285,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,10 +299,10 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -319,7 +319,7 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -386,7 +386,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wl5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -430,7 +430,7 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wl5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,7 +463,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -480,7 +480,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,9 +497,9 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wl5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wl5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -576,7 +576,7 @@ int stm32wl5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wl5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index 611bcfd63e105..4de3d6b393692 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -38,7 +38,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -80,7 +80,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -88,7 +88,7 @@ * ****************************************************************************/ -static int stm32wl5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uart.h b/arch/arm/src/stm32wl5/stm32wl5_uart.h index ff12c5ec571f9..06c8ed8c86fac 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uart.h @@ -202,7 +202,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -215,7 +215,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c index 311458d7adb11..763fd031ccb7e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_uid.c + * arch/arm/src/stm32wl5/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. @@ -50,7 +50,7 @@ * Public Functions ****************************************************************************/ -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.h b/arch/arm/src/stm32wl5/stm32wl5_uid.h index f88b8f2b2d6f6..22d6f4dbcc28f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.h @@ -48,6 +48,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_UID_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.c b/arch/arm/src/stm32wl5/stm32wl5_userspace.c index 345a6f0f45772..23a8bfe9bba65 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.c +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wl5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wl5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wl5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.h b/arch/arm/src/stm32wl5/stm32wl5_userspace.h index b304b90d5bcbe..900a75750a1bd 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.h +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32WL5_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.c b/arch/arm/src/stm32wl5/stm32wl5_waste.c index 96f0e621cf3b1..7b2ddbf141ebf 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.c +++ b/arch/arm/src/stm32wl5/stm32wl5_waste.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_waste.c + * arch/arm/src/stm32wl5/stm32_waste.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0; * Public Functions ****************************************************************************/ -void stm32wl5_waste(void) +void stm32_waste(void) { idle_wastecounter++; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.h b/arch/arm/src/stm32wl5/stm32wl5_waste.h index f4f3beaa2794f..974f59745d9a3 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.h +++ b/arch/arm/src/stm32wl5/stm32wl5_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32wl5_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a measure * of badly written piece of software or some undesired behavior. At @@ -54,7 +54,7 @@ extern "C" * be used for other purposes (yet). */ -void stm32wl5_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 7b19cafb8f218..9616e510d43d0 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -231,7 +231,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -241,7 +241,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h index e54ca1e97bdd3..adce7b8ed71aa 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h @@ -31,7 +31,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -148,24 +148,24 @@ void board_leds_initialize(void); /**************************************************************************** - * Name: stm32wl5_flash_init + * Name: stm32_flash_init * * Description: * Initialize on-board FLASH partition table * ****************************************************************************/ -int stm32wl5_flash_init(void); +int stm32_flash_init(void); /**************************************************************************** - * Name: stm32wl5_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Initialize SPIs * ****************************************************************************/ -void stm32wl5_spidev_initialize(void); +void stm32_spidev_initialize(void); /**************************************************************************** * Name: ipcc_init diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c index cd93826536b45..86454d000626f 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c @@ -47,7 +47,7 @@ #include #endif -#include +#include #include #include @@ -73,7 +73,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -83,7 +83,7 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs, which are always enabled */ @@ -109,7 +109,7 @@ void board_late_initialize(void) int ret; #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) - stm32wl5_spidev_initialize(); + stm32_spidev_initialize(); #endif #if defined(CONFIG_LCD_SSD1680) && !defined(CONFIG_VIDEO_FB) @@ -161,10 +161,10 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_FLASH_MOUNT) /* Register partition table for on-board FLASH memory */ - ret = stm32wl5_flash_init(); + ret = stm32_flash_init(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32wl5_flash_init() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_flash_init() failed: %d\n", ret); } #endif @@ -181,7 +181,7 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_ENABLE_CPU2) /* Start second CPU */ - stm32wl5_pwr_boot_c2(); + stm32_pwr_boot_c2(); #endif UNUSED(ret); @@ -203,7 +203,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wl5_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c index adf9448398ce6..1ef9e8a33d030 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c @@ -57,10 +57,10 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32wl5_configgpio(GPIO_BUTTON1); - stm32wl5_configgpio(GPIO_BUTTON2); + stm32_configgpio(GPIO_BUTTON1); + stm32_configgpio(GPIO_BUTTON2); #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - stm32wl5_configgpio(GPIO_BUTTON3); + stm32_configgpio(GPIO_BUTTON3); return 3; /* number of buttons */ #else return 2; /* number of buttons */ @@ -81,18 +81,18 @@ uint32_t board_buttons(void) state = 0; - if (stm32wl5_gpioread(GPIO_BUTTON1) == 0) + if (stm32_gpioread(GPIO_BUTTON1) == 0) { state |= BUTTON1_BIT; } - if (stm32wl5_gpioread(GPIO_BUTTON2) == 0) + if (stm32_gpioread(GPIO_BUTTON2) == 0) { state |= BUTTON2_BIT; } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - if (stm32wl5_gpioread(GPIO_BUTTON3) == 0) + if (stm32_gpioread(GPIO_BUTTON3) == 0) { state |= BUTTON3_BIT; } @@ -130,20 +130,20 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BOARD_BUTTON1) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON1, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON1, true, true, false, irqhandler, arg); } if (id == BOARD_BUTTON2) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON2, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON2, true, true, false, irqhandler, arg); } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ if (id == BOARD_BUTTON3) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON3, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON3, true, true, false, irqhandler, arg); } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index 16b1724823082..4ae514cd0c60a 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -173,7 +173,7 @@ static const struct part_table part_table[] = * Public Functions ****************************************************************************/ -int stm32wl5_flash_init(void) +int stm32_flash_init(void) { struct mtd_dev_s *mtd; struct mtd_dev_s *mtd_part; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c index 8d6b8f1d913c4..de0cce3e3a1d2 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c @@ -116,9 +116,9 @@ static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen) struct ipcc_lower_s *ipcc; int ret; - if ((ipcc = stm32wl5_ipcc_init(chan)) == NULL) + if ((ipcc = stm32_ipcc_init(chan)) == NULL) { - syslog(LOG_ERR, "ERROR: stm32wl5_ipcc_init(%d) failed\n", chan); + syslog(LOG_ERR, "ERROR: stm32_ipcc_init(%d) failed\n", chan); return -1; } diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c index a0a23318bfd58..c276a1c52c056 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include @@ -64,17 +64,17 @@ static void led_state(int state, unsigned int leds) { if (leds & BOARD_LED_BLUE_BIT) { - stm32wl5_gpiowrite(GPIO_LED_BLUE, state); + stm32_gpiowrite(GPIO_LED_BLUE, state); } if (leds & BOARD_LED_RED_BIT) { - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); } if (leds & BOARD_LED_GREEN_BIT) { - stm32wl5_gpiowrite(GPIO_LED_GREEN, state); + stm32_gpiowrite(GPIO_LED_GREEN, state); } } @@ -93,12 +93,12 @@ static int button3_led(int irq, void *context, void *arg) (void)arg; int state; - state = stm32wl5_gpioread(GPIO_LED_RED); + state = stm32_gpioread(GPIO_LED_RED); /* toggle state */ state = !state; - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); return 0; } #endif @@ -113,9 +113,9 @@ static int button3_led(int irq, void *context, void *arg) void board_leds_initialize(void) { - stm32wl5_configgpio(GPIO_LED_BLUE); - stm32wl5_configgpio(GPIO_LED_RED); - stm32wl5_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); } /**************************************************************************** @@ -222,7 +222,7 @@ uint32_t board_userled_initialize(void) #ifdef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ /* Configure B3 button to fire an interrupt on falling edge (on press) */ - stm32wl5_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); + stm32_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); #endif return BOARD_NLEDS; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c index 4999fb03b68b4..a3748c2db24e9 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) @@ -68,12 +68,12 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32wl5_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { #ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32wl5_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -82,10 +82,10 @@ void weak_function stm32wl5_spidev_initialize(void) #ifdef CONFIG_LCD_SSD1680 spiinfo("Preparing additional lines for SSD1680 device\n"); - stm32wl5_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ - stm32wl5_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ + stm32_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ #endif #endif @@ -105,7 +105,7 @@ void weak_function stm32wl5_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -114,9 +114,9 @@ void weak_function stm32wl5_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -124,7 +124,7 @@ void weak_function stm32wl5_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : @@ -133,26 +133,26 @@ void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CS, !selected); + stm32_gpiowrite(GPIO_SSD1680_CS, !selected); } #endif #if defined(CONFIG_CAN_MCP2515) if (devid == SPIDEV_CANBUS(0)) { - stm32wl5_gpiowrite(GPIO_MCP2515_CS, !selected); + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); } #endif #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32wl5_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) @@ -164,12 +164,12 @@ uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) return 0; } -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CMD, !cmd); + stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); } #endif @@ -179,76 +179,23 @@ int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #ifdef CONFIG_STM32_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} - -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD16800) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } -#endif -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} #endif -#endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c index d57e2c42bfba4..289609b19b4f8 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c @@ -33,7 +33,7 @@ #include #include -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_ssd1680.h" @@ -59,7 +59,7 @@ static bool ssd1680_set_vcc(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_RST) static bool ssd1680_set_rst(bool state) { - stm32wl5_gpiowrite(GPIO_SSD1680_RST, state); + stm32_gpiowrite(GPIO_SSD1680_RST, state); return true; } #endif @@ -67,7 +67,7 @@ static bool ssd1680_set_rst(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_BUSY) static bool ssd1680_check_busy(void) { - return stm32wl5_gpioread(GPIO_SSD1680_BUSY); + return stm32_gpioread(GPIO_SSD1680_BUSY); } #endif @@ -106,20 +106,20 @@ int board_lcd_initialize(void) /* Initialize additional I/O for e-ink display */ #if defined(GPIO_SSD1680_PWR) - stm32wl5_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ + stm32_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ lcdinfo("SSD1680 power line is available (0x%08x)\n", GPIO_SSD1680_PWR); #else lcdinfo("PWR control line is disabled\n"); #endif #if defined(GPIO_SSD1680_RST) - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ lcdinfo("SSD1680 reset line is available (0x%08x)\n", GPIO_SSD1680_RST); #elif lcdinfo("SSD1680 RESET line is disabled\n"); #endif #if defined(GPIO_SSD1680_BUSY) - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ lcdinfo("SSD1680 Line for reading busy state is available (0x%08x)\n", GPIO_SSD1680_BUSY); #elif @@ -128,7 +128,7 @@ int board_lcd_initialize(void) /* Initialize SPI */ - spi = stm32wl5_spibus_initialize(CONFIG_SSD1680_SPI_BUS); + spi = stm32_spibus_initialize(CONFIG_SSD1680_SPI_BUS); if (!spi) { lcderr("ERROR: Failed to initialize SPI port %d\n", From cf4777dc9a7477cd7a4142bef8027215c2f9e7a7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 10/52] !arm/stm32: split legacy STM32 family selectors BREAKING CHANGE: Convert the legacy STM32 F1/F2/F3/F4/G4/L1 port to the concrete family selectors while keeping the shared STM32 selector hidden. Legacy STM32 family selector Kconfig symbols were split by concrete STM32 sub-family. Out-of-tree defconfigs and code must update CONFIG_ARCH_CHIP_* selections to the new family-specific selectors. Signed-off-by: raiden00pl --- .../arm/stm32f1/boards/fire-stm32v2/index.rst | 2 +- arch/arm/src/stm32/Kconfig | 992 +----------------- .../arm/stm32/axoloti/configs/nsh/defconfig | 2 +- .../stm32/b-g431b-esc1/configs/can/defconfig | 2 +- .../b-g431b-esc1/configs/cansock/defconfig | 2 +- .../b-g431b-esc1/configs/foc_b16/defconfig | 2 +- .../b-g431b-esc1/configs/foc_f32/defconfig | 2 +- .../stm32/b-g431b-esc1/configs/nsh/defconfig | 2 +- .../b-g474e-dpow1/configs/buckboost/defconfig | 2 +- .../stm32/b-g474e-dpow1/configs/nsh/defconfig | 2 +- .../b-g474e-dpow1/configs/ostest/defconfig | 2 +- .../clicker2-stm32/configs/knsh/defconfig | 2 +- .../configs/mrf24j40-6lowpan/defconfig | 2 +- .../configs/mrf24j40-mac/defconfig | 2 +- .../configs/mrf24j40-starhub/defconfig | 2 +- .../configs/mrf24j40-starpoint/defconfig | 2 +- .../clicker2-stm32/configs/nsh/defconfig | 2 +- .../clicker2-stm32/configs/usbnsh/defconfig | 2 +- .../configs/xbee-6lowpan/defconfig | 2 +- .../arm/stm32/cloudctrl/configs/nsh/defconfig | 2 +- .../arm/stm32/emw3162/configs/nsh/defconfig | 2 +- .../arm/stm32/emw3162/configs/wlan/defconfig | 2 +- .../et-stm32-stamp/configs/nsh/defconfig | 2 +- .../stm32/fire-stm32v2/configs/nsh/defconfig | 2 +- .../stm32/hymini-stm32v/configs/nsh/defconfig | 2 +- .../hymini-stm32v/configs/nsh2/defconfig | 2 +- .../hymini-stm32v/configs/usbmsc/defconfig | 2 +- .../hymini-stm32v/configs/usbnsh/defconfig | 2 +- .../hymini-stm32v/configs/usbserial/defconfig | 2 +- boards/arm/stm32/maple/configs/nsh/defconfig | 2 +- boards/arm/stm32/maple/configs/nx/defconfig | 2 +- .../arm/stm32/maple/configs/usbnsh/defconfig | 2 +- .../mikroe-stm32f4/configs/fulldemo/defconfig | 2 +- .../mikroe-stm32f4/configs/kostest/defconfig | 2 +- .../mikroe-stm32f4/configs/nsh/defconfig | 2 +- .../stm32/mikroe-stm32f4/configs/nx/defconfig | 2 +- .../mikroe-stm32f4/configs/nxlines/defconfig | 2 +- .../mikroe-stm32f4/configs/nxtext/defconfig | 2 +- .../mikroe-stm32f4/configs/usbnsh/defconfig | 2 +- .../stm32/nucleo-f103rb/configs/adc/defconfig | 2 +- .../configs/ihm07m1_b16/defconfig | 2 +- .../stm32/nucleo-f103rb/configs/nsh/defconfig | 2 +- .../stm32/nucleo-f103rb/configs/pwm/defconfig | 2 +- .../nucleo-f103rb/configs/qenco/defconfig | 2 +- .../stm32/nucleo-f207zg/configs/adc/defconfig | 2 +- .../stm32/nucleo-f207zg/configs/nsh/defconfig | 2 +- .../stm32/nucleo-f207zg/configs/pwm/defconfig | 2 +- .../stm32/nucleo-f302r8/configs/can/defconfig | 2 +- .../nucleo-f302r8/configs/cansock/defconfig | 2 +- .../nucleo-f302r8/configs/highpri/defconfig | 2 +- .../configs/ihm07m1_b16/defconfig | 2 +- .../configs/ihm07m1_f32/defconfig | 2 +- .../stm32/nucleo-f302r8/configs/nsh/defconfig | 2 +- .../nucleo-f302r8/configs/qenco/defconfig | 2 +- .../stm32/nucleo-f303re/configs/adc/defconfig | 2 +- .../stm32/nucleo-f303re/configs/can/defconfig | 2 +- .../nucleo-f303re/configs/hello/defconfig | 2 +- .../stm32/nucleo-f303re/configs/nsh/defconfig | 2 +- .../nucleo-f303re/configs/nxlines/defconfig | 2 +- .../stm32/nucleo-f303re/configs/pwm/defconfig | 2 +- .../nucleo-f303re/configs/serialrx/defconfig | 2 +- .../stm32/nucleo-f303ze/configs/adc/defconfig | 2 +- .../stm32/nucleo-f303ze/configs/nsh/defconfig | 2 +- .../configs/nxlines_oled/defconfig | 2 +- .../stm32/nucleo-f334r8/configs/adc/defconfig | 2 +- .../nucleo-f334r8/configs/highpri/defconfig | 2 +- .../stm32/nucleo-f334r8/configs/nsh/defconfig | 2 +- .../nucleo-f334r8/configs/spwm1/defconfig | 2 +- .../nucleo-f334r8/configs/spwm2/defconfig | 2 +- .../stm32/nucleo-f401re/configs/fb/defconfig | 2 +- .../stm32/nucleo-f401re/configs/nsh/defconfig | 2 +- .../stm32/nucleo-f410rb/configs/nsh/defconfig | 2 +- .../configs/mcp2515-extid/defconfig | 2 +- .../stm32/nucleo-f411re/configs/nsh/defconfig | 2 +- .../nucleo-f412zg/configs/coremark/defconfig | 2 +- .../stm32/nucleo-f412zg/configs/nsh/defconfig | 2 +- .../nucleo-f412zg/configs/ostest/defconfig | 2 +- .../nucleo-f429zi/configs/netnsh/defconfig | 2 +- .../stm32/nucleo-f429zi/configs/nsh/defconfig | 2 +- .../nucleo-f429zi/configs/trace/defconfig | 2 +- .../stm32/nucleo-f446re/configs/adc/defconfig | 2 +- .../stm32/nucleo-f446re/configs/can/defconfig | 2 +- .../nucleo-f446re/configs/cansock/defconfig | 2 +- .../stm32/nucleo-f446re/configs/dac/defconfig | 2 +- .../nucleo-f446re/configs/gpio/defconfig | 2 +- .../configs/ihm08m1_b16/defconfig | 2 +- .../configs/ihm08m1_f32/defconfig | 2 +- .../stm32/nucleo-f446re/configs/lcd/defconfig | 2 +- .../stm32/nucleo-f446re/configs/nsh/defconfig | 2 +- .../stm32/nucleo-f446re/configs/pwm/defconfig | 2 +- .../nucleo-f446re/configs/qenco/defconfig | 2 +- .../configs/systemview/defconfig | 2 +- .../nucleo-g431kb/configs/comp/defconfig | 2 +- .../stm32/nucleo-g431kb/configs/nsh/defconfig | 2 +- .../stm32/nucleo-g431kb/configs/pwm/defconfig | 2 +- .../stm32/nucleo-g431rb/configs/adc/defconfig | 2 +- .../stm32/nucleo-g431rb/configs/can/defconfig | 2 +- .../nucleo-g431rb/configs/cansock/defconfig | 2 +- .../nucleo-g431rb/configs/cordic/defconfig | 2 +- .../configs/ihm16m1_b16/defconfig | 2 +- .../configs/ihm16m1_f32/defconfig | 2 +- .../stm32/nucleo-g431rb/configs/nsh/defconfig | 2 +- .../stm32/nucleo-g431rb/configs/pwm/defconfig | 2 +- .../nucleo-g431rb/configs/qenco/defconfig | 2 +- .../nucleo-g474re/configs/lpuartnsh/defconfig | 2 +- .../stm32/nucleo-g474re/configs/nsh/defconfig | 2 +- .../nucleo-g474re/configs/usbserial/defconfig | 2 +- .../stm32/nucleo-l152re/configs/lcd/defconfig | 2 +- .../stm32/nucleo-l152re/configs/nsh/defconfig | 2 +- .../arm/stm32/odrive36/configs/nsh/defconfig | 2 +- .../stm32/odrive36/configs/usbnsh/defconfig | 2 +- .../configs/bmp180/defconfig | 2 +- .../olimex-stm32-e407/configs/dac/defconfig | 2 +- .../configs/discover/defconfig | 2 +- .../configs/ina219/defconfig | 2 +- .../configs/mrf24j40-6lowpan/defconfig | 2 +- .../configs/mrf24j40-mac/defconfig | 2 +- .../configs/netnsh/defconfig | 2 +- .../olimex-stm32-e407/configs/nsh/defconfig | 2 +- .../configs/telnetd/defconfig | 2 +- .../olimex-stm32-e407/configs/timer/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../configs/webserver/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../olimex-stm32-h407/configs/nsh/defconfig | 2 +- .../configs/nsh_uext/defconfig | 2 +- .../olimex-stm32-p107/configs/nsh/defconfig | 2 +- .../olimex-stm32-p207/configs/nsh/defconfig | 2 +- .../olimex-stm32-p407/configs/audio/defconfig | 2 +- .../olimex-stm32-p407/configs/dhtxx/defconfig | 2 +- .../configs/hidkbd/defconfig | 2 +- .../olimex-stm32-p407/configs/kelf/defconfig | 2 +- .../configs/kmodule/defconfig | 2 +- .../olimex-stm32-p407/configs/knsh/defconfig | 2 +- .../configs/module/defconfig | 2 +- .../olimex-stm32-p407/configs/mqttc/defconfig | 2 +- .../olimex-stm32-p407/configs/nsh/defconfig | 2 +- .../configs/zmodem/defconfig | 2 +- .../olimexino-stm32/configs/can/defconfig | 2 +- .../configs/composite/defconfig | 2 +- .../olimexino-stm32/configs/nsh/defconfig | 2 +- .../configs/smallnsh/defconfig | 2 +- .../olimexino-stm32/configs/tiny/defconfig | 2 +- .../arm/stm32/omnibusf4/configs/nsh/defconfig | 2 +- boards/arm/stm32/photon/configs/adb/defconfig | 2 +- boards/arm/stm32/photon/configs/nsh/defconfig | 2 +- .../arm/stm32/photon/configs/rgbled/defconfig | 2 +- .../arm/stm32/photon/configs/usbnsh/defconfig | 2 +- .../stm32/photon/configs/wlan-perf/defconfig | 2 +- .../arm/stm32/photon/configs/wlan/defconfig | 2 +- .../arm/stm32/shenzhou/configs/nsh/defconfig | 2 +- .../arm/stm32/shenzhou/configs/nxwm/defconfig | 2 +- .../stm32/shenzhou/configs/thttpd/defconfig | 2 +- .../stm3210e-eval/configs/composite/defconfig | 2 +- .../stm32/stm3210e-eval/configs/nsh/defconfig | 2 +- .../stm3210e-eval/configs/nsh2/defconfig | 2 +- .../stm32/stm3210e-eval/configs/nx/defconfig | 2 +- .../stm3210e-eval/configs/nxterm/defconfig | 2 +- .../stm32/stm3210e-eval/configs/pm/defconfig | 2 +- .../stm3210e-eval/configs/usbmsc/defconfig | 2 +- .../stm3210e-eval/configs/usbserial/defconfig | 2 +- .../stm3220g-eval/configs/dhcpd/defconfig | 2 +- .../stm3220g-eval/configs/nettest/defconfig | 2 +- .../stm32/stm3220g-eval/configs/nsh/defconfig | 2 +- .../stm3220g-eval/configs/nsh2/defconfig | 2 +- .../stm3220g-eval/configs/nxwm/defconfig | 2 +- .../stm3220g-eval/configs/telnetd/defconfig | 2 +- .../stm3240g-eval/configs/dhcpd/defconfig | 2 +- .../stm3240g-eval/configs/discover/defconfig | 2 +- .../stm32/stm3240g-eval/configs/fb/defconfig | 2 +- .../stm3240g-eval/configs/knxwm/defconfig | 2 +- .../stm3240g-eval/configs/nettest/defconfig | 2 +- .../stm32/stm3240g-eval/configs/nsh/defconfig | 2 +- .../stm3240g-eval/configs/nsh2/defconfig | 2 +- .../stm3240g-eval/configs/nxterm/defconfig | 2 +- .../stm3240g-eval/configs/nxwm/defconfig | 2 +- .../stm3240g-eval/configs/telnetd/defconfig | 2 +- .../stm3240g-eval/configs/webserver/defconfig | 2 +- .../stm3240g-eval/configs/xmlrpc/defconfig | 2 +- .../stm32/stm32_tiny/configs/nsh/defconfig | 2 +- .../stm32/stm32_tiny/configs/usbnsh/defconfig | 2 +- .../stm32butterfly2/configs/nsh/defconfig | 2 +- .../stm32butterfly2/configs/nshnet/defconfig | 2 +- .../configs/nshusbdev/defconfig | 2 +- .../configs/nshusbhost/defconfig | 2 +- .../stm32f103-minimum/configs/adb/defconfig | 2 +- .../configs/apds9960/defconfig | 2 +- .../configs/audio_tone/defconfig | 2 +- .../configs/buttons/defconfig | 2 +- .../stm32f103-minimum/configs/can/defconfig | 2 +- .../stm32f103-minimum/configs/hello/defconfig | 2 +- .../configs/jlx12864g/defconfig | 2 +- .../configs/lcd1602/defconfig | 2 +- .../configs/mcp2515/defconfig | 2 +- .../stm32f103-minimum/configs/nrf24/defconfig | 2 +- .../stm32f103-minimum/configs/nsh/defconfig | 2 +- .../stm32f103-minimum/configs/pwm/defconfig | 2 +- .../configs/rfid-rc522/defconfig | 2 +- .../configs/rgbled/defconfig | 2 +- .../configs/sensors/defconfig | 2 +- .../configs/ssd1306/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../configs/userled/defconfig | 2 +- .../configs/veml6070/defconfig | 2 +- .../configs/buckboost/defconfig | 2 +- .../stm32f334-disco/configs/nsh/defconfig | 2 +- .../configs/powerled/defconfig | 2 +- .../stm32f3discovery/configs/nsh/defconfig | 2 +- .../stm32f3discovery/configs/usbnsh/defconfig | 2 +- .../stm32f401rc-rs485/configs/adc/defconfig | 2 +- .../configs/bmp280/defconfig | 2 +- .../stm32f401rc-rs485/configs/dac/defconfig | 2 +- .../configs/hcsr04/defconfig | 2 +- .../configs/lcd1602/defconfig | 2 +- .../stm32f401rc-rs485/configs/lm75/defconfig | 2 +- .../configs/max7219/defconfig | 2 +- .../configs/mfrc522/defconfig | 2 +- .../configs/modbus_master/defconfig | 2 +- .../configs/modbus_slave/defconfig | 2 +- .../stm32f401rc-rs485/configs/nsh/defconfig | 2 +- .../configs/qencoder/defconfig | 2 +- .../stm32f401rc-rs485/configs/rndis/defconfig | 2 +- .../configs/sdcard/defconfig | 2 +- .../configs/ssd1309/defconfig | 2 +- .../configs/telnetd/defconfig | 2 +- .../configs/usbmsc/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../configs/ws2812/defconfig | 2 +- .../configs/composite/defconfig | 2 +- .../stm32f411-minimum/configs/nsh/defconfig | 2 +- .../stm32f411-minimum/configs/pwm/defconfig | 2 +- .../configs/rgbled/defconfig | 2 +- .../configs/spifsnsh/defconfig | 2 +- .../configs/usbmsc/defconfig | 2 +- .../stm32f411e-disco/configs/nsh/defconfig | 2 +- .../stm32f429i-disco/configs/adc/defconfig | 2 +- .../configs/bootlogo/defconfig | 2 +- .../configs/extflash/defconfig | 2 +- .../stm32f429i-disco/configs/fb/defconfig | 2 +- .../configs/gdbstub/defconfig | 2 +- .../configs/highpri/defconfig | 2 +- .../stm32f429i-disco/configs/lcd/defconfig | 2 +- .../stm32f429i-disco/configs/lvgl/defconfig | 2 +- .../stm32f429i-disco/configs/nsh/defconfig | 2 +- .../configs/nxhello/defconfig | 2 +- .../stm32f429i-disco/configs/nxwm/defconfig | 2 +- .../configs/ofloader/defconfig | 2 +- .../stm32f429i-disco/configs/stack/defconfig | 2 +- .../configs/systemview/defconfig | 2 +- .../stm32f429i-disco/configs/usbmsc/defconfig | 2 +- .../stm32f429i-disco/configs/usbnsh/defconfig | 2 +- .../stm32f4discovery/configs/adb/defconfig | 2 +- .../stm32f4discovery/configs/audio/defconfig | 2 +- .../configs/brickmatch/defconfig | 2 +- .../stm32f4discovery/configs/canard/defconfig | 2 +- .../configs/composite/defconfig | 2 +- .../configs/cxx-oot-build/defconfig | 2 +- .../configs/cxxtest/defconfig | 2 +- .../stm32f4discovery/configs/elf/defconfig | 2 +- .../configs/ether_w5500/defconfig | 2 +- .../stm32f4discovery/configs/ipv6/defconfig | 2 +- .../configs/kostest/defconfig | 2 +- .../configs/lcd1602/defconfig | 2 +- .../stm32f4discovery/configs/lwl/defconfig | 2 +- .../configs/max31855/defconfig | 2 +- .../configs/max7219/defconfig | 2 +- .../configs/mmcsdspi/defconfig | 2 +- .../configs/modbus_slave/defconfig | 2 +- .../stm32f4discovery/configs/module/defconfig | 2 +- .../configs/mpr121_keypad/defconfig | 2 +- .../stm32f4discovery/configs/mt6816/defconfig | 2 +- .../stm32f4discovery/configs/netnsh/defconfig | 2 +- .../stm32f4discovery/configs/nsh/defconfig | 2 +- .../configs/nxlines/defconfig | 2 +- .../configs/nxscope_cdcacm/defconfig | 2 +- .../stm32f4discovery/configs/pm/defconfig | 2 +- .../configs/posix_spawn/defconfig | 2 +- .../configs/pseudoterm/defconfig | 2 +- .../stm32f4discovery/configs/rgbled/defconfig | 2 +- .../stm32f4discovery/configs/rndis/defconfig | 2 +- .../configs/sbutton/defconfig | 2 +- .../configs/sporadic/defconfig | 2 +- .../stm32f4discovery/configs/st7567/defconfig | 2 +- .../stm32f4discovery/configs/st7789/defconfig | 2 +- .../configs/testlibcxx/defconfig | 2 +- .../stm32f4discovery/configs/usbmsc/defconfig | 2 +- .../stm32f4discovery/configs/usbnsh/defconfig | 2 +- .../stm32f4discovery/configs/wifi/defconfig | 2 +- .../configs/xen1210/defconfig | 2 +- .../stm32ldiscovery/configs/chrono/defconfig | 2 +- .../stm32ldiscovery/configs/nsh/defconfig | 2 +- .../stm32vldiscovery/configs/nsh/defconfig | 2 +- .../configs/ft80x/defconfig | 2 +- .../configs/highpri/defconfig | 2 +- .../configs/netnsh/defconfig | 2 +- .../viewtool-stm32f107/configs/nsh/defconfig | 2 +- .../configs/tcpblaster/defconfig | 2 +- 297 files changed, 322 insertions(+), 1262 deletions(-) diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index e82450a5e2f9e..19ce66c3fb07f 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -324,7 +324,7 @@ M3 Wildfire-specific Configuration Options CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: - CONFIG_ARCH_CHIP_STM32 + CONFIG_ARCH_CHIP_STM32F1 CONFIG_ARCH_CHIP_STM32F103VE CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f6d7ff5b37e79..dd3ca73b81c47 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -8,7 +8,7 @@ comment "STM32 Configuration Options" choice prompt "STM32 Chip Selection" default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32 + depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 config ARCH_CHIP_STM32L151C6 bool "STM32L151C6" @@ -1207,77 +1207,42 @@ config ARCH_CHIP_STM32G474V endchoice -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_CONFIG_DEFAULT - depends on ARCH_CHIP_STM32 - ---help--- - STM32F/STM32G/STM32L series parts numbering (sans the package type) - ends with a number or letter that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - Z 192 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - If the STM32F407VE is chosen, the Flash configuration would be - 'E', if a variant of the part with a 2048 KiB Flash is released - in the future one could simply select the 'I' designator here. - - If an STM32F42xxx or Series parts is chosen the default Flash - configuration will be 'G' and can be set herein to 'I' to choose - the larger FLASH part. - config STM32_FLASH_CONFIG_DEFAULT - bool "Default" + bool config STM32_FLASH_CONFIG_4 - bool "4 16KiB" + bool config STM32_FLASH_CONFIG_6 - bool "6 32KiB" + bool config STM32_FLASH_CONFIG_8 - bool "8 64KiB" + bool config STM32_FLASH_CONFIG_B - bool "B 128KiB" + bool config STM32_FLASH_CONFIG_Z - bool "Z 192KiB" + bool config STM32_FLASH_CONFIG_C - bool "C 256KiB" + bool config STM32_FLASH_CONFIG_D - bool "D 384KiB" + bool config STM32_FLASH_CONFIG_E - bool "E 512KiB" + bool config STM32_FLASH_CONFIG_F - bool "F 768KiB" + bool config STM32_FLASH_CONFIG_G - bool "G 1024KiB" + bool config STM32_FLASH_CONFIG_I - bool "I 2048KiB" + bool -endchoice # This is really 15XX/16XX, but we treat the two the same. config STM32_STM32L15XX @@ -2260,6 +2225,10 @@ config STM32_HAVE_LTDC bool default n +config STM32_HAVE_USART2 + bool + default n + config STM32_HAVE_USART3 bool default n @@ -2504,6 +2473,10 @@ config STM32_HAVE_ETHMAC bool default n +config STM32_HAVE_I2C1 + bool + default n + config STM32_HAVE_I2C2 bool default n @@ -2524,6 +2497,10 @@ config STM32_HAVE_LPUART1 bool default n +config STM32_HAVE_SPI1 + bool + default n + config STM32_HAVE_SPI2 bool default n @@ -3709,25 +3686,6 @@ config STM32_FLASH_PREFETCH on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch properly and enabling this option may interfere with ADC accuracy. -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG bool "Disable IDLE Sleep (WFI) in debug mode" @@ -6131,33 +6089,6 @@ config STM32_TIM1_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM1 ADC channel" - default STM32_TIM1_ADC1 - depends on STM32_TIM1_ADC - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice config STM32_TIM2_ADC bool "TIM2 ADC" @@ -6173,33 +6104,6 @@ config STM32_TIM2_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM2 ADC channel" - default STM32_TIM2_ADC1 - depends on STM32_TIM2_ADC - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice config STM32_TIM3_ADC bool "TIM3 ADC" @@ -6215,33 +6119,6 @@ config STM32_TIM3_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM3 ADC channel" - default STM32_TIM3_ADC1 - depends on STM32_TIM3_ADC - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice config STM32_TIM4_ADC bool "TIM4 ADC" @@ -6257,33 +6134,6 @@ config STM32_TIM4_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM4 ADC channel" - default STM32_TIM4_ADC1 - depends on STM32_TIM4_ADC - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice config STM32_TIM5_ADC bool "TIM5 ADC" @@ -6299,33 +6149,6 @@ config STM32_TIM5_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM5 ADC channel" - default STM32_TIM5_ADC1 - depends on STM32_TIM5_ADC - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice config STM32_TIM8_ADC bool "TIM8 ADC" @@ -6341,33 +6164,6 @@ config STM32_TIM8_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM8 ADC channel" - default STM32_TIM8_ADC1 - depends on STM32_TIM8_ADC - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice config STM32_HAVE_ADC1_TIMER bool @@ -6443,22 +6239,6 @@ config STM32_TIM1_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM1 DAC channel" - default STM32_TIM1_DAC1 - depends on STM32_TIM1_DAC - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice config STM32_TIM2_DAC bool "TIM2 DAC" @@ -6474,22 +6254,6 @@ config STM32_TIM2_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM2 DAC channel" - default STM32_TIM2_DAC1 - depends on STM32_TIM2_DAC - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice config STM32_TIM3_DAC bool "TIM3 DAC" @@ -6505,22 +6269,6 @@ config STM32_TIM3_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM3 DAC channel" - default STM32_TIM3_DAC1 - depends on STM32_TIM3_DAC - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice config STM32_TIM4_DAC bool "TIM4 DAC" @@ -6536,22 +6284,6 @@ config STM32_TIM4_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM4 DAC channel" - default STM32_TIM4_DAC1 - depends on STM32_TIM4_DAC - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice config STM32_TIM5_DAC bool "TIM5 DAC" @@ -6567,22 +6299,6 @@ config STM32_TIM5_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM5 DAC channel" - default STM32_TIM5_DAC1 - depends on STM32_TIM5_DAC - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice config STM32_TIM6_DAC bool "TIM6 DAC" @@ -6598,22 +6314,6 @@ config STM32_TIM6_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM6 DAC channel" - default STM32_TIM6_DAC1 - depends on STM32_TIM6_DAC - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice config STM32_TIM7_DAC bool "TIM7 DAC" @@ -6629,22 +6329,6 @@ config STM32_TIM7_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM7 DAC channel" - default STM32_TIM7_DAC1 - depends on STM32_TIM7_DAC - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice config STM32_TIM8_DAC bool "TIM8 DAC" @@ -6660,22 +6344,6 @@ config STM32_TIM8_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM8 DAC channel" - default STM32_TIM8_DAC1 - depends on STM32_TIM8_DAC - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice config STM32_TIM9_DAC bool "TIM9 DAC" @@ -6691,22 +6359,6 @@ config STM32_TIM9_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM9 DAC channel" - default STM32_TIM9_DAC1 - depends on STM32_TIM9_DAC - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice config STM32_TIM10_DAC bool "TIM10 DAC" @@ -6722,22 +6374,6 @@ config STM32_TIM10_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM10 DAC channel" - default STM32_TIM10_DAC1 - depends on STM32_TIM10_DAC - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice config STM32_TIM11_DAC bool "TIM11 DAC" @@ -6753,22 +6389,6 @@ config STM32_TIM11_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM11 DAC channel" - default STM32_TIM11_DAC1 - depends on STM32_TIM11_DAC - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice config STM32_TIM12_DAC bool "TIM12 DAC" @@ -6784,22 +6404,6 @@ config STM32_TIM12_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM12 DAC channel" - default STM32_TIM12_DAC1 - depends on STM32_TIM12_DAC - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice config STM32_TIM13_DAC bool "TIM13 DAC" @@ -6815,22 +6419,6 @@ config STM32_TIM13_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM13 DAC channel" - default STM32_TIM13_DAC1 - depends on STM32_TIM13_DAC - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice config STM32_TIM14_DAC bool "TIM14 DAC" @@ -6846,22 +6434,6 @@ config STM32_TIM14_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM14 DAC channel" - default STM32_TIM14_DAC1 - depends on STM32_TIM14_DAC - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice config STM32_TIM1_CAP bool "TIM1 Capture" @@ -9705,27 +9277,6 @@ menu "U[S]ART Configuration" comment "U[S]ART Device Configuration" -choice - prompt "USART1 Driver Configuration" - default STM32_USART1_SERIALDRIVER - depends on STM32_USART1 - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration if STM32_USART1_SERIALDRIVER @@ -9798,27 +9349,6 @@ config STM32_HCIUART1_RXDMA endif # STM32_USART1_HCIUART -choice - prompt "USART2 Driver Configuration" - default STM32_USART2_SERIALDRIVER - depends on STM32_USART2 - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration if STM32_USART2_SERIALDRIVER @@ -9891,27 +9421,6 @@ config STM32_HCIUART2_RXDMA endif # STM32_USART2_HCIUART -choice - prompt "USART3 Driver Configuration" - default STM32_USART3_SERIALDRIVER - depends on STM32_USART3 - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration if STM32_USART3_SERIALDRIVER @@ -9984,22 +9493,6 @@ config STM32_HCIUART3_RXDMA endif # STM32_USART3_HCIUART -choice - prompt "UART4 Driver Configuration" - default STM32_UART4_SERIALDRIVER - depends on STM32_UART4 - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration if STM32_UART4_SERIALDRIVER @@ -10036,22 +9529,6 @@ config UART4_TXDMA endif # STM32_UART4_SERIALDRIVER -choice - prompt "UART5 Driver Configuration" - default STM32_UART5_SERIALDRIVER - depends on STM32_UART5 - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration if STM32_UART5_SERIALDRIVER @@ -10088,27 +9565,6 @@ config UART5_TXDMA endif # STM32_UART5_SERIALDRIVER -choice - prompt "USART6 Driver Configuration" - default STM32_USART6_SERIALDRIVER - depends on STM32_USART6 - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration if STM32_USART6_SERIALDRIVER @@ -10367,18 +9823,6 @@ config STM32_HCIUART8_RXDMA endif # STM32_UART8_HCIUART -choice - prompt "LPUART1 Driver Configuration" - default STM32_LPUART1_SERIALDRIVER - depends on STM32_LPUART1 - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration if STM32_LPUART1_SERIALDRIVER @@ -10919,26 +10363,6 @@ config STM32_RTC_MAGIC_TIME_SET Value used as Magic to determine if the RTC has been setup and has time set -choice - prompt "RTC clock source" - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source endmenu # RTC configuration menu "Ethernet MAC configuration" @@ -10966,37 +10390,6 @@ config STM32_MII ---help--- Support Ethernet MII interface. -choice - prompt "MII clock configuration" - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_MII - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice config STM32_AUTONEG bool "Use autonegotiation" @@ -11147,37 +10540,6 @@ config STM32_RMII bool default !STM32_MII -choice - prompt "RMII clock configuration" - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_RMII - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] - -endchoice config STM32_ETHMAC_REGDEBUG bool "Register-Level Debug" @@ -11340,20 +10702,6 @@ config STM32_USB_ITRMP menu "CAN driver configuration" depends on STM32_CAN -choice - prompt "CAN character driver or SocketCAN support" - default STM32_CAN_CHARDRIVER - -config STM32_CAN_CHARDRIVER - bool "STM32 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support config STM32_CAN1_BAUD int "CAN1 BAUD" @@ -11394,21 +10742,6 @@ endmenu # "CAN driver configuration" menu "FDCAN driver configuration" depends on STM32_FDCAN -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32_FDCAN_CHARDRIVER - -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support config STM32_FDCAN_REGDEBUG bool "CAN Register level debug" @@ -11425,44 +10758,7 @@ config STM32_FDCAN_QUEUE_MODE menu "FDCAN1 device driver options" depends on STM32_FDCAN1 -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 - -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC - -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. -endchoice # FDCAN1 mode config STM32_FDCAN1_LOOPBACK bool "Enable FDCAN1 loopback mode" @@ -11539,44 +10835,7 @@ endmenu # FDCAN1 device driver options menu "FDCAN2 device driver options" depends on STM32_FDCAN2 -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode config STM32_FDCAN2_LOOPBACK bool "Enable FDCAN2 loopback mode" @@ -11839,43 +11098,6 @@ config STM32_LTDC_L1_COLOR hex "Layer L1 default color" default 0x00000000 -choice - prompt "Layer 1 color format" - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format config STM32_LTDC_L2 bool "Enable Layer 2 support" @@ -11895,43 +11117,6 @@ config STM32_LTDC_L2_CHROMAKEY hex "Layer L2 initial chroma key" default 0x00000000 -choice - prompt "Layer 2 (top layer) color format" - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - depends on STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32_LTDC_L2_AL44 - depends on STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32_LTDC_L2_AL88 - depends on STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32_LTDC_L2_RGB565 - depends on STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32_LTDC_L2_ARGB4444 - depends on STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32_LTDC_L2_ARGB1555 - depends on STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32_LTDC_L2_RGB888 - depends on STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32_LTDC_L2_ARGB8888 - depends on STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format endif # STM32_LTDC_L2 @@ -12189,64 +11374,7 @@ config STM32_QENCODER_FILTER bool "Enable filtering on STM32 QEncoder input" default y -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32_QENCODER_SAMPLE_FDTS_4 - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel event count" - default STM32_QENCODER_SAMPLE_EVENT_6 - -config STM32_QENCODER_SAMPLE_EVENT_1 - depends on STM32_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32_QENCODER_SAMPLE_EVENT_2 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32_QENCODER_SAMPLE_EVENT_4 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32_QENCODER_SAMPLE_EVENT_5 - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - bool "5" -config STM32_QENCODER_SAMPLE_EVENT_6 - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32_QENCODER_SAMPLE_EVENT_8 - depends on !STM32_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice endmenu @@ -12254,6 +11382,7 @@ menuconfig STM32_FOC bool "STM32 lower-half FOC support" default n select ARCH_IRQPRIO + select STM32_ADC select STM32_PWM_MULTICHAN select STM32_PWM_LL_OPS select STM32_ADC_LL_OPS @@ -12278,83 +11407,14 @@ config STM32_FOC_FOC1 ---help--- Enable support for FOC1 device that uses TIM8 for PWM modulation -choice - prompt "FOC ADC trigger selection" - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" if STM32_FOC_FOC0 -choice - prompt "FOC0 device ADC selection" - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" endif # STM32_FOC_FOC0 if STM32_FOC_FOC1 -choice - prompt "FOC1 device ADC selection" - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" endif # STM32_FOC_FOC1 diff --git a/boards/arm/stm32/axoloti/configs/nsh/defconfig b/boards/arm/stm32/axoloti/configs/nsh/defconfig index 1d43644ebd105..1527d1283178c 100644 --- a/boards/arm/stm32/axoloti/configs/nsh/defconfig +++ b/boards/arm/stm32/axoloti/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="axoloti" CONFIG_ARCH_BOARD_AXOLOTI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F427I=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig index 43dc0f4143a21..493be180951fe 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig index ba24fe7e2fe9a..273c6b7a87458 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig index a8d73452d001e..b1072cad33010 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig index 2dd0555c613ff..f8aec241b4ba5 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig index 7008df0865512..46c71c62c2b0a 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig index fadfe62a85213..3625c3af8d889 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig index 067ed86173846..0b9c303e3a46d 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig index 70a00af2020a5..b6bc84bd10ac8 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig index b44ea5be1a4b9..ab40dd86d1e54 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig index 67b83406eb150..5ac5c06b41f9b 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig index bb355e1aeb496..167735240cfcd 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig index 1d2e6c692f546..54fe586554946 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig index d49e01b2da3c0..5278c9e1f68fd 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig index 8d0945efcca12..241e636355d92 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig index 48aee341fff70..9ba8e7f754ded 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig index 4f4c219be01c2..47920cf847c04 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig index be4882c81d088..4a1bfe1b92b1b 100644 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="cloudctrl" CONFIG_ARCH_BOARD_CLOUDCTRL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32/emw3162/configs/nsh/defconfig index 9688757eaf295..09c55962b4462 100644 --- a/boards/arm/stm32/emw3162/configs/nsh/defconfig +++ b/boards/arm/stm32/emw3162/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="emw3162" CONFIG_ARCH_BOARD_EMW3162=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32/emw3162/configs/wlan/defconfig index ceeedd6a6b56f..50a635fa1439e 100644 --- a/boards/arm/stm32/emw3162/configs/wlan/defconfig +++ b/boards/arm/stm32/emw3162/configs/wlan/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="emw3162" CONFIG_ARCH_BOARD_EMW3162=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig index 4c71777c0f8a7..7d2988de7f7fb 100644 --- a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig +++ b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="et-stm32-stamp" CONFIG_ARCH_BOARD_ET_STM32_STAMP=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig index 334352f98536b..a08ecdee55b64 100644 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="fire-stm32v2" CONFIG_ARCH_BOARD_FIRE_STM32=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig index 46a47095c31e1..966728982c123 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig index 07770b9836be2..dd50de960fc5e 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig index 429596080a6e9..6c87e1b256e9f 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig index 73800aa8adfc4..eb3a920940b70 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig index 7f6da595e2a9e..f5f7b23c3acc5 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32/maple/configs/nsh/defconfig index 7c9ac9e17fbbc..83fb1a2b48cdf 100644 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ b/boards/arm/stm32/maple/configs/nsh/defconfig @@ -24,7 +24,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32/maple/configs/nx/defconfig index 9ffbeb782a291..6172ac4e83d7c 100644 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ b/boards/arm/stm32/maple/configs/nx/defconfig @@ -26,7 +26,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32/maple/configs/usbnsh/defconfig index 5dac2d2057063..4fe25ce070a27 100644 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ b/boards/arm/stm32/maple/configs/usbnsh/defconfig @@ -25,7 +25,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig index 7413ebbd7f9db..cb009bea9044f 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig index e89262a68b986..c2d6d9d08910b 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig index 78dfe980601ea..690bb98ed8420 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig index c8b0ef583d7e5..6a95af7bc2118 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig index 9245c04e424dd..a11ce7db414a0 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig index 7959ef4608663..c5fb7c7da969a 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig index c011fdde8bb9b..3b71a1d199511 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig index 46570b4a60830..1cf2c0c90efb6 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig index e8185cb780297..f88aae75d79c5 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig index 2be574f9f8662..abb3742b68f24 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig index 1fd7b4dd5e8c9..083b57d867fd4 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig index df060b58063de..15f67d0b52e6f 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig index 2615e630e80d0..6d856b068e752 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig index 855e4c155bb5d..36ccf9508fd0b 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig index 03abe05bec910..b2d25ed4d8968 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig index def904eba3da8..ebc1520b3f303 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig index 701e71056cc6d..cfdaa95faeb2a 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig index 386f0a3d39965..f25864d20f015 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig index 39910fedf6952..6deed35ec2b7c 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig index c3c5fc1ce3430..6ef0621ec8fc5 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig index a1df51d77ca57..a9d463268ef04 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig index 1197a24f5e613..1294b209f920f 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig @@ -63,7 +63,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQPRIO=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig index ea4831dc3fd30..8bcd928f594fb 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig index 4c85a315731f0..ed465f2924106 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig index a51fa54aaa0b7..0a7ca25b383e0 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig index 95b091e30b498..ae360cfb4b3fd 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig index 8bacca4eb3fb6..fd970c2a6761e 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig index 7c449ee522c3e..3f4c63188fe85 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig index 16397524983bf..4576cc7e981d2 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig index b90be268b186f..f2d6468fb91a3 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-f303ze" CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig index 7081c146db74b..4e7c31dd5960a 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f303ze" CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig index 3c09c2da60034..2246e4f79306a 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig index 33656febfca35..061b531d0df21 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig index 1866cd70f3cf7..91edb447bbc3e 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig index 2bb393ba17062..a93dc875a7856 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig index 37daa3d7509e5..da76b4a0a0bea 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig index d238c8b4564f3..268872d84fffb 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig index 88504078e4d20..a1b50fd19ba8e 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig +++ b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F401RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig index 8bf7d35ad498e..e4de249cbd58a 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f401re" CONFIG_ARCH_BOARD_NUCLEO_F401RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig index 58fb8efa0e53d..084541c3257e1 100644 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f410rb" CONFIG_ARCH_BOARD_NUCLEO_F410RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F410RB=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig index 78f646b76fe3c..a3f262eade067 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig +++ b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f411re" CONFIG_ARCH_BOARD_NUCLEO_F411RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411RE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig index ecb6ba9c1d2f2..7d747965a4ca8 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f411re" CONFIG_ARCH_BOARD_NUCLEO_F411RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411RE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig index 6dd586b0050fc..5eeb2976c6693 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig index fc06830d00be0..1592d27e09ba6 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig index 5c9c9c9657cc1..0e148998477e3 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig index 8af3bb56e5f71..540dba0fb4c97 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig index d13b9d0031e44..9f4b9ecb6cdae 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig index a82d50d95dd03..725c9eb2f4d84 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig index 20fde7d94c882..44cf45de768df 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig index f699366f92dc5..03a39c1bc977e 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig index 1ed153216c627..6fbda28d15b89 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig index 8b4215f22ec5d..4e6f30b3248ab 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig index 7436007b48370..196dd1384db81 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig index 2c152f31e767a..453e2c87c7d6f 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig index 5b3e84da6ad8a..daf78d0af9a1e 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig index 2c85afecb9f49..2863a56217ddc 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig index 1dd5ff9cb1776..4a868074d9ea4 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig index 64d5b681a44e8..b55efe9b8c152 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig index d0da232ae1bc8..1b02b7f1f6ce1 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQPRIO=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig index 01ea37491e5ab..4acf305216efc 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig index 5631b4f1a607b..f6f47682d13ac 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig index 2470af3cfacf1..d9c35a7176968 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig index b8e9c1184c3ee..5d629e84f5c74 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig index 143878d3afd82..c783fa1869d2e 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig index 4796db68b7df9..ee1142d3bc673 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig index dbca1ec3f65f3..f63b294d6bc4e 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig index 105f0e801d73e..755e3605c821c 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig index 198ec5e96451f..cba47d6c50216 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig index 54b46c61d05c2..b1da16e313b60 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig index b28e171393d61..f760847d8e7aa 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig index 8f56b95cda311..9a390b1dbd801 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig index a3b86c5b5b5be..1af962f93e9ef 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig index bbfd0aa9b5223..cb1bf8ee517b2 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig index 0850c88d054b0..5e03072fbf5f6 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig index e93dcf5ab625f..2d0e3747829cb 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig index 5695f7ee012f2..a877414347662 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig index 4232102fb6154..a014bf12d2565 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 diff --git a/boards/arm/stm32/odrive36/configs/nsh/defconfig b/boards/arm/stm32/odrive36/configs/nsh/defconfig index 2f27a769673b4..ec8b2cd552759 100644 --- a/boards/arm/stm32/odrive36/configs/nsh/defconfig +++ b/boards/arm/stm32/odrive36/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="odrive36" CONFIG_ARCH_BOARD_ODRIVE36=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15272 diff --git a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig index c0b74daa75366..d56e316f5c53d 100644 --- a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig +++ b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="odrive36" CONFIG_ARCH_BOARD_ODRIVE36=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig index d5df1ff53bac9..76a1fb22c4c37 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig index 19fe331945263..e8b7e412e0a28 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig index a83bf4730a9c9..9a68e4e14850f 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig index e406cc5fb0235..68fcf5a41382b 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig index c0f90c9741115..705fc73e15577 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig index a9221bfba48c3..aa23ce824c460 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig index 2e75fb27370b4..f099771caefd3 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig index 571f8a9adb70a..ec0a10d31c543 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig index 6a11a0f3b3939..a81d22650165a 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig index 98aa59ace4cd6..e98d6d69fa97e 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig index 93de54935666f..6105ef196c890 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig index f01bcc9c11cac..1a98f84122a37 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig index 302f0bd148fb0..a3ba7928726f2 100644 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-h405" CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig index b2e63d079be3f..a7d1a43050305 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-h407" CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig index 2095476d0ef07..2a561e5dad30c 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-h407" CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig index 0e6f00bff3bca..92e3f709d9e78 100644 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p107" CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig index 4e50e59cce329..ed329af28cdb3 100644 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p207" CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207ZE=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig index 1d4015c480202..f9ead32d95bbd 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig index 1ec9ec6df1f4e..2ffe4347fa1da 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig index ed45a26523b3c..c9560ec454115 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig index bb4a056ff466a..d7b726a5612fc 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig index cde47ac79db37..d03474e354acd 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig index 7be5a978eda06..c7ce54486b294 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig index 7157051491cb3..854cda731db49 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig index 76e96ce5920c8..d59e71b70d949 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig index bb3cbd8e78037..068f384397b42 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig index 7c2ccb8cb1f0d..c5f244513af7e 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig index d02669c55029d..95cf7656244e4 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig index ce360b21b9464..8a01242f25bbf 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig index 7fac8d7932b9f..fbbcff77f4c10 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig index 9e47e5a1c4add..7687414c781bf 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig index 34a814085c57a..35eb903db23cd 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig index 3c35b9f82b28d..ad1678e330e08 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="omnibusf4" CONFIG_ARCH_BOARD_OMNIBUSF4=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_IOCTL=y diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig index 1cd0b1d4e0f8e..7291e7e2ddea9 100644 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ b/boards/arm/stm32/photon/configs/adb/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32/photon/configs/nsh/defconfig index e0e25c7c346f3..e1c4b317d0a28 100644 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ b/boards/arm/stm32/photon/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig index d1096c8a84d31..bc62471ce2024 100644 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ b/boards/arm/stm32/photon/configs/rgbled/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32/photon/configs/usbnsh/defconfig index 860b33017022a..7349032a1c81d 100644 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ b/boards/arm/stm32/photon/configs/usbnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/photon/configs/wlan-perf/defconfig b/boards/arm/stm32/photon/configs/wlan-perf/defconfig index d6a02110e3b7c..c4d498634d86b 100644 --- a/boards/arm/stm32/photon/configs/wlan-perf/defconfig +++ b/boards/arm/stm32/photon/configs/wlan-perf/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32/photon/configs/wlan/defconfig index c2cf5294c3b44..ac6ceaea97fd8 100644 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ b/boards/arm/stm32/photon/configs/wlan/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32/shenzhou/configs/nsh/defconfig index 3cad521d66645..6458d6ddcb1a5 100644 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig index 815572c9038c3..b26d3effac213 100644 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig index 7a6bad14a95a7..9bd6be420efbe 100644 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig index 82259cb815680..1e7956808cc67 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig index 315e9136cf1a8..268aee418cc55 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig index 0f9b059c5d238..760f1b8b5cfd7 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig index f221932c7c707..b75dbf44445e1 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig index 395633cb5f030..2421726a6d08a 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig index 4fd1d15afc423..4df26c1ffef14 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_IDLE_CUSTOM=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig index 976438a23932a..3a83a3e914e07 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig index 205b97bbc4ebd..3177d178960b6 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig index 4765c757824ab..4e5992c98af68 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig index ad6101db81811..29550b5cd4246 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig index 45e7aca47f147..b1df69ce5e01d 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig index 25cbc3ad5eb00..57d9b07abc807 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig index 4756ef1512f6d..068d4c090decd 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig index 7ca6a50bbac63..43b76f0b4da57 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig index 1e1d4bae5c173..ef5bf8ed08713 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig index fa73ac6e959d5..b17d7f63105d1 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig index 7db5d2ec714c4..95c71a7752181 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig index dc2de40c87105..0e2ea7668494e 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig index cecabe2f65f31..9a38a060c90f7 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig index e445c306c4d4e..1b212f135dc02 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig index 007647eefa558..3c038271c3336 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig index cdf394741be44..52d25eaf5fa92 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig index 550058e72ce9a..416c842d4c472 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig index b34caaabfe6d3..24e0a378c3819 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig index b50bf38bc9126..133e6f23b899c 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig index ca17c0e962fb8..353a903f228b1 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig index 221484c5f5975..ff2c3f8694598 100644 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32_tiny" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32_TINY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig index 39ded7939a64a..627a8111f2051 100644 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32_tiny" CONFIG_ARCH_BOARD_STM32_TINY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig index 79655e199f1a4..00e362af8bce3 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig index 762efdfdce220..7c9318d5a8d2e 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig index 294531d34d641..a75cab61efdc9 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig index 79655e199f1a4..00e362af8bce3 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig index 493f2fdb00338..60d0b587290f7 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig index 2789b752ecf43..8204b158b8cc1 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig index 6c6800df69d9d..f6aca5546d964 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig index 11c015562a8d0..cb630b8a5c346 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig index 8d76332f3deef..8609d8332fb4f 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig @@ -34,7 +34,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig index 029d1efc9443f..625735d4b99ac 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_DEFAULT_SMALL=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig index 5eea66e1f1b5d..07ad100354746 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig index b91f9cca66b55..e648a558cc3c7 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig index 9f2e614adb3ac..226a3fc04215e 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig index ac06a6bc606b6..c5b2ce959c997 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig index 3c704737ee264..6cce4dd24af19 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig @@ -34,7 +34,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig index 8d0dda31037f1..88305a3a2464a 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig index 9b30668c97ea4..82ebe0e454faf 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig index cba32112192c0..0aa109abc0034 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig index 589d6e8d4ddff..d281ac189e745 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig index 8ab229454da28..a10002a0e1a9f 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig @@ -34,7 +34,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig index a633b57853733..d355792be1a69 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig index 931b29c9dede6..a95bf5abb4c02 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig index 3f439883df67f..baa759d2c7451 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig index 8c31ee1302b90..374b8bdc590c1 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig index db3bc11cbbb2d..9ed9e4d15f3db 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig index 10a5ed5968f49..08b072eda47fa 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig @@ -28,7 +28,7 @@ CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig index 1973cf7321ab8..8fd33f99d8cd1 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f3discovery" CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig index 5d388639fb48f..72cd5cdaeb7e0 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f3discovery" CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_CHIP_STM32F303VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig index 2c10476201ee6..6389be0013f70 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig index ee0e197c2655d..f82b09d2f9091 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig index 4487a2834aaa9..51c16c29654b4 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig index 87491419a250a..de8ac9fa46eaa 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig index 68f78a2565b3a..cf6d3abb7978b 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig index b431f061e801c..347ce193ef3ce 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig index 100a1658edffc..2e2272e87d58d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig index d24b43acad199..9d8225dcdd8c7 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig index 2e5ad3de7e2fd..c65f62a46b3d6 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -23,7 +23,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig index 199a6fe8f2321..7067c5a9386f0 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig index 4effd9f205643..7df3e220a81dc 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig index 041d1063cf925..0f5de2d968ed2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig index e6a0c65cdab01..e5bc3efabcaf4 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig index bdd8cbb1b33f4..4620407de0458 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig index 0ebbf98d62c77..c006b542eab46 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig index 38212b7cf512e..9f84d79196068 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig index 8810cd175f3d1..e3f070a97e28e 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig index 8394c946d47cd..d22a6dc62bec4 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig index 7f4abba8eac5a..26a52a6e1af7c 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig index 3b481dfd674d8..815e19ca8b04b 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig index 371cea88bf7a2..4f5c7bc0cdbe1 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig index 3f60dea548167..d2c984c4aeee8 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig index c5ebec8a82b82..f1273c7d5650f 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig index bc6985a1d4ce1..5ca14bc662afa 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig index 1d49a8275be78..d489172e6a3a7 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig index 3a2397b01beab..db7826a6b94f1 100644 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411e-disco" CONFIG_ARCH_BOARD_STM32F411E_DISCO=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F411VE=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig index 2e4718deb92b3..1addeb2e1b8d0 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig index d9f7431a0247f..aa691be350b72 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig index 6126452086010..cccc4378d2312 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig index f4449b5807ff3..a98b7de6841a9 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig index a2ae14866f206..82332b7e9fe95 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_INTERRUPTSTACK=4096 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig index d8fe5c1b7d90b..816e761186400 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig index 55ff0bb5b9f95..a0308040c9199 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig index d4b2f40ad717c..36849b2e3e81e 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig index 1b17784c3aac4..37383ba2e6239 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig index fc3c836a06499..4daefe0a7476f 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig index 819fa8d7df831..1db71182f3112 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig index e0d8d16cb0f9e..f948552f17c6d 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig index 03a81bfa4c32a..c9e0881603240 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_INSTRUMENT_ALL=y CONFIG_ARCH_INTERRUPTSTACK=4096 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig index 2500bae8c273c..a7293527dc2c6 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig index 03447b3fac8b1..0e37eddf1ab99 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig index 7246fb6ffad44..1c20aa029a01a 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig index 70765999bf7d8..165220b6cbe92 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig index 7a58739b22135..f30298ce9ae06 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig index bb8d3b332702f..4220e68169f23 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig index 553cc77d00240..2922985e15590 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig index 8485892f11c54..4eb4037db8123 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig index 6dd62ac3583a5..53f1a03f82066 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig index 9784e9650a4f4..6da12af7d4289 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig index d67f3e5aa69aa..41930cc1dae8e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_CONSTRUCTORS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig index 41f42ad54d132..6659ea3bcc4e7 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig index 910ab3e1436d6..4f103fa26f4b4 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig index cc106c43eb404..12fbc10e64f28 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig index da7f85f99a7b6..fe6437b339e90 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig index 562e7ffef0e7f..fdb159aa6f946 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig index 05486e4a8f735..aa01c29c274c6 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig index 9be5d50f0b3ce..120398ee50c63 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig @@ -45,7 +45,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig index 7c3b724bbedf9..4a3511f054699 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig index 7e4857ec739a2..a0b33e071f609 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig index 3b84fd63e69e6..baae91a957c31 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_ROMDISK=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig index c6b607db2870e..012456083ba42 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig index 609bf1e8f072e..d5d4a081473f5 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig index acf1c69a8867f..20094fe529c66 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig index 27dc6222bebb4..0b5d259baa585 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig index 8ecab5062eb96..0e98105330cd2 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig index efc7a7cfe4525..33c24e9c6302e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig index 4f196c9c570b3..b1c252b5e6c3b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_IDLE_CUSTOM=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig index 9f49ec41573bd..245906de64f0f 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_CONSTRUCTORS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig index 2deb457fa7783..0da7f887e4182 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig index 48ded7700ac78..57b1645f4fa6b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig index fde9264166505..0130b48eb6a11 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig index 2dbb1e6193a64..e6b0d17a5dbfc 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig index 3af85b79a137f..61fa2cab6f9e3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig index e3166d9e8a17d..01904582935ec 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig index 9d846ecf6a4bc..96ae4a22989bf 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig index fd17d3158312a..35821863695b4 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig index 0bc84e9ee02c1..660319b4b17d6 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig index dce3e3d343b5c..2b1efa580e7c6 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig index 9867fcf30a580..3179db663c279 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig index e0237c63e672e..fb9fdbfc6b712 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig index 0167eac8ad0e2..7348760dcdcd8 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig index f6f307ffc1e2a..c486a692f0f5b 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig index 58ac9e12dae02..fc5c0296bf715 100644 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig @@ -23,7 +23,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32vldiscovery" CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F100RB=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2398 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig index f952c3ca348eb..431ff572a077f 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig index 817e9d62fd4f3..4b412ea8f066e 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig index 083ecf7359a96..c71355f280664 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig index b68528e2301f8..1f9679122ed30 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig index 1e3c72298e85f..f9a2ca62b57af 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 From 2a49a0040e2a45bec018d80d6f8b5d26853b1444 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 11/52] !arm/stm32f0l0g0: use common STM32 Kconfig symbols BREAKING CHANGE: STM32F0/L0/G0/C0 Kconfig symbols were renamed from CONFIG_STM32F0L0G0_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- arch/arm/include/stm32f0l0g0/stm32g0_irq.h | 4 +- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 40 +- arch/arm/src/stm32f0l0g0/Kconfig | 2559 ++++++++--------- arch/arm/src/stm32f0l0g0/Make.defs | 40 +- arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h | 6 +- .../src/stm32f0l0g0/hardware/stm32_dmamux.h | 4 +- .../stm32f0l0g0/hardware/stm32_memorymap.h | 8 +- .../src/stm32f0l0g0/hardware/stm32_pinmap.h | 8 +- arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h | 8 +- arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h | 2 +- .../arm/src/stm32f0l0g0/hardware/stm32_uart.h | 4 +- .../src/stm32f0l0g0/hardware/stm32_usbdev.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_adc.c | 116 +- arch/arm/src/stm32f0l0g0/stm32_adc.h | 118 +- arch/arm/src/stm32f0l0g0/stm32_dma.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_dma.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_dma_v1.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c | 60 +- arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c | 6 +- arch/arm/src/stm32f0l0g0/stm32_fdcan.c | 64 +- arch/arm/src/stm32f0l0g0/stm32_fdcan.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c | 66 +- arch/arm/src/stm32f0l0g0/stm32_flash.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_gpio.c | 8 +- arch/arm/src/stm32f0l0g0/stm32_gpio.h | 2 +- arch/arm/src/stm32f0l0g0/stm32_hsi48.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_i2c.c | 92 +- arch/arm/src/stm32f0l0g0/stm32_i2c.h | 8 +- arch/arm/src/stm32f0l0g0/stm32_idle.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_irq.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_lowputc.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c | 10 +- arch/arm/src/stm32f0l0g0/stm32_pulsecount.c | 22 +- arch/arm/src/stm32f0l0g0/stm32_pwm.c | 178 +- arch/arm/src/stm32f0l0g0/stm32_pwm.h | 384 ++- arch/arm/src/stm32f0l0g0/stm32_pwr.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_pwr.h | 12 +- arch/arm/src/stm32f0l0g0/stm32_qencoder.c | 170 +- arch/arm/src/stm32f0l0g0/stm32_qencoder.h | 34 +- arch/arm/src/stm32f0l0g0/stm32_rcc.c | 14 +- arch/arm/src/stm32f0l0g0/stm32_rng.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_serial.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_serial_v1.c | 76 +- arch/arm/src/stm32f0l0g0/stm32_serial_v2.c | 70 +- arch/arm/src/stm32f0l0g0/stm32_spi.c | 86 +- arch/arm/src/stm32f0l0g0/stm32_spi.h | 12 +- arch/arm/src/stm32f0l0g0/stm32_tim.c | 300 +- .../arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32f0l0g0/stm32_timerisr.c | 6 +- arch/arm/src/stm32f0l0g0/stm32_uart.h | 236 +- arch/arm/src/stm32f0l0g0/stm32_usbdev.c | 14 +- arch/arm/src/stm32f0l0g0/stm32_wdg.h | 4 +- arch/arm/src/stm32f0l0g0/stm32c0_rcc.c | 54 +- arch/arm/src/stm32f0l0g0/stm32f0_rcc.c | 74 +- arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c | 8 +- arch/arm/src/stm32f0l0g0/stm32g0_pwr.c | 4 +- arch/arm/src/stm32f0l0g0/stm32g0_rcc.c | 80 +- arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c | 68 +- arch/arm/src/stm32f0l0g0/stm32l0_rcc.c | 80 +- .../b-l072z-lrwan1/configs/adc/defconfig | 10 +- .../b-l072z-lrwan1/configs/nsh/defconfig | 4 +- .../configs/nxlines_oled/defconfig | 6 +- .../b-l072z-lrwan1/configs/sx127x/defconfig | 6 +- .../b-l072z-lrwan1/include/board.h | 2 +- .../b-l072z-lrwan1/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/b-l072z-lrwan1/src/Make.defs | 2 +- .../b-l072z-lrwan1/src/b-l072z-lrwan1.h | 2 +- .../b-l072z-lrwan1/src/stm32_adc.c | 4 +- .../b-l072z-lrwan1/src/stm32_boot.c | 2 +- .../b-l072z-lrwan1/src/stm32_bringup.c | 6 +- .../b-l072z-lrwan1/src/stm32_spi.c | 14 +- .../nucleo-c071rb/configs/adcscope/defconfig | 20 +- .../nucleo-c071rb/configs/jumbo/defconfig | 28 +- .../nucleo-c071rb/configs/nsh/defconfig | 2 +- .../nucleo-c071rb/src/stm32_boot.c | 2 +- .../nucleo-c071rb/src/stm32_bringup.c | 4 +- .../nucleo-c092rc/configs/can/defconfig | 10 +- .../nucleo-c092rc/configs/cansock/defconfig | 12 +- .../nucleo-c092rc/configs/jumbo/defconfig | 30 +- .../nucleo-c092rc/configs/nsh/defconfig | 2 +- .../nucleo-c092rc/src/CMakeLists.txt | 6 +- .../stm32f0l0g0/nucleo-c092rc/src/Make.defs | 6 +- .../nucleo-c092rc/src/nucleo-c092rc.h | 4 +- .../nucleo-c092rc/src/stm32_boot.c | 2 +- .../nucleo-c092rc/src/stm32_bringup.c | 8 +- .../nucleo-f072rb/configs/nsh/defconfig | 4 +- .../stm32f0l0g0/nucleo-f072rb/include/board.h | 4 +- .../nucleo-f072rb/src/nucleo-f072rb.h | 12 +- .../nucleo-f072rb/src/stm32_bringup.c | 2 +- .../nucleo-f091rc/configs/nsh/defconfig | 4 +- .../nucleo-f091rc/configs/sx127x/defconfig | 6 +- .../stm32f0l0g0/nucleo-f091rc/include/board.h | 4 +- .../nucleo-f091rc/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/nucleo-f091rc/src/Make.defs | 2 +- .../nucleo-f091rc/src/nucleo-f091rc.h | 14 +- .../nucleo-f091rc/src/stm32_boot.c | 2 +- .../stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c | 14 +- .../nucleo-g070rb/configs/nsh/defconfig | 82 +- .../nucleo-g070rb/src/stm32_boot.c | 2 +- .../nucleo-g070rb/src/stm32_bringup.c | 8 +- .../stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c | 14 +- .../nucleo-g071rb/configs/nsh/defconfig | 4 +- .../nucleo-g071rb/src/stm32_boot.c | 2 +- .../nucleo-g0b1re/configs/adc/defconfig | 6 +- .../nucleo-g0b1re/configs/adc_dma/defconfig | 24 +- .../nucleo-g0b1re/configs/nsh/defconfig | 4 +- .../stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c | 2 +- .../nucleo-g0b1re/src/stm32_boot.c | 2 +- .../nucleo-l073rz/configs/nsh/defconfig | 4 +- .../nucleo-l073rz/configs/sx127x/defconfig | 6 +- .../stm32f0l0g0/nucleo-l073rz/include/board.h | 2 +- .../nucleo-l073rz/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/nucleo-l073rz/src/Make.defs | 2 +- .../nucleo-l073rz/src/nucleo-l073rz.h | 2 +- .../nucleo-l073rz/src/stm32_boot.c | 2 +- .../nucleo-l073rz/src/stm32_mfrc522.c | 2 +- .../stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c | 18 +- .../stm32f051-discovery/configs/nsh/defconfig | 4 +- .../stm32f051-discovery/include/board.h | 4 +- .../stm32f051-discovery/src/CMakeLists.txt | 2 +- .../stm32f051-discovery/src/Make.defs | 2 +- .../src/stm32f051-discovery.h | 12 +- .../stm32f072-discovery/configs/nsh/defconfig | 4 +- .../stm32f072-discovery/include/board.h | 4 +- .../stm32f072-discovery/src/CMakeLists.txt | 2 +- .../stm32f072-discovery/src/Make.defs | 2 +- .../src/stm32f072-discovery.h | 12 +- .../stm32g071b-disco/configs/nsh/defconfig | 4 +- .../stm32g071b-disco/configs/oled/defconfig | 8 +- .../stm32g071b-disco/src/stm32_boot.c | 2 +- .../stm32g071b-disco/src/stm32_ina226.c | 2 +- .../stm32g071b-disco/src/stm32_spi.c | 18 +- .../stm32l0538-disco/configs/nsh/defconfig | 4 +- .../stm32l0538-disco/include/board.h | 2 +- 134 files changed, 2787 insertions(+), 3090 deletions(-) diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h index ef718cff08533..ae5e5a29194dc 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h @@ -80,8 +80,8 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ -#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +#if defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ # define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ # define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt index a60ec1966a7ec..44b85031e93e5 100644 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ b/arch/arm/src/stm32f0l0g0/CMakeLists.txt @@ -35,15 +35,15 @@ list( stm32_rcc.c stm32_uid.c) -if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F0L0G0_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32F0L0G0_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() @@ -59,11 +59,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c) endif() -if(CONFIG_STM32F0L0G0_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() -if(CONFIG_STM32F0L0G0_GPIOIRQ) +if(CONFIG_STM32_GPIOIRQ) list(APPEND SRCS stm32_gpioint.c) endif() @@ -71,59 +71,59 @@ if(CONFIG_ARCH_IRQPRIO) list(APPEND SRCS stm32_irqprio.c) endif() -if(CONFIG_STM32F0L0G0_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() -if(CONFIG_STM32F0L0G0_USB) +if(CONFIG_STM32_USB) list(APPEND SRCS stm32_usbdev.c) endif() -if(CONFIG_STM32F0L0G0_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F0L0G0_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_PULSECOUNT AND CONFIG_STM32F0L0G0_TIM1_PULSECOUNT) +if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F0L0G0_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F0L0G0_AES) +if(CONFIG_STM32_AES) list(APPEND SRCS stm32_aes.c) endif() -if(CONFIG_STM32F0L0G0_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F0L0G0_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F0L0G0_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32F0L0G0_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_fdcan.c) endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) + if(CONFIG_STM32_FDCAN_SOCKET) list(APPEND SRCS stm32_fdcan_sock.c) endif() endif() diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 31cddad994e15..40cddb539a162 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -15,712 +15,712 @@ choice config ARCH_CHIP_STM32F030C6 bool "STM32F030C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030C8 bool "STM32F030C8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030CC bool "STM32F030CC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030F4 bool "STM32F030F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030K6 bool "STM32F030K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030R8 bool "STM32F030R8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030RC bool "STM32F030RC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C4 bool "STM32F031C4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C6 bool "STM32F031C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031E6 bool "STM32F031E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F4 bool "STM32F031F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F6 bool "STM32F031F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G4 bool "STM32F031G4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G6 bool "STM32F031G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K4 bool "STM32F031K4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K6 bool "STM32F031K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038C6 bool "STM32F038C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038E6 bool "STM32F038E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038F6 bool "STM32F038F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038G6 bool "STM32F038G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038K6 bool "STM32F038K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C4 bool "STM32F042C4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C6 bool "STM32F042C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F4 bool "STM32F042F4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F6 bool "STM32F042F6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G4 bool "STM32F042G4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G6 bool "STM32F042G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K4 bool "STM32F042K4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K6 bool "STM32F042K6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042T6 bool "STM32F042T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048C6 bool "STM32F048C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048G6 bool "STM32F048G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048T6 bool "STM32F048T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C4 bool "STM32F051C4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C6 bool "STM32F051C6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C8 bool "STM32F051C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K4 bool "STM32F051K4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K6 bool "STM32F051K6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K8 bool "STM32F051K8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R4 bool "STM32F051R4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R6 bool "STM32F051R6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R8 bool "STM32F051R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051T8 bool "STM32F051T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058C8 bool "STM32F058C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058R8 bool "STM32F058R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058T8 bool "STM32F058T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070C6 bool "STM32F070C6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070CB bool "STM32F070CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070F6 bool "STM32F070F6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070RB bool "STM32F070RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071C8 bool "STM32F071C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071CB bool "STM32F071CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071RB bool "STM32F071RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071V8 bool "STM32F071V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071VB bool "STM32F071VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072C8 bool "STM32F072C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072CB bool "STM32F072CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072R8 bool "STM32F072R8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072RB bool "STM32F072RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072V8 bool "STM32F072V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072VB bool "STM32F072VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078CB bool "STM32F078CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078RB bool "STM32F078RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078VB bool "STM32F078VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CB bool "STM32F091CB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CC bool "STM32F091CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RB bool "STM32F091RB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RC bool "STM32F091RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VB bool "STM32F091VB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VC bool "STM32F091VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098CC bool "STM32F098CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098RC bool "STM32F098RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098VC bool "STM32F098VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32G070CB bool "STM32G070CB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G070KB bool "STM32G070KB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G070RB bool "STM32G070RB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071EB bool "STM32G071EB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8 bool "STM32G071G8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GB bool "STM32G071GB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8XN bool "STM32G071G8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GBXN bool "STM32G071GBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8 bool "STM32G071K8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KB bool "STM32G071KB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8XN bool "STM32G071K8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KBXN bool "STM32G071KBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071C8 bool "STM32G071C8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071CB bool "STM32G071CB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071R8 bool "STM32G071R8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071RB bool "STM32G071RB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KB bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CB bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RB bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MB bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VB bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KC bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CC bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RC bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MC bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VC bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KE bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CE bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RE bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1NE bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1ME bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VE bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KB bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CB bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RB bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MB bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VB bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KC bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CC bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RC bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MC bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VC bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KE bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CE bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RE bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1NE bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1ME bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VE bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32L053C8 @@ -751,86 +751,86 @@ config ARCH_CHIP_STM32L071KZ config ARCH_CHIP_STM32L071C8 bool "STM32L071C8" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CB bool "STM32L071CB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CZ bool "STM32L071CZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071V8 bool "STM32L071V8" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VB bool "STM32L071VB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VZ bool "STM32L071VZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RB bool "STM32L071RB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RZ bool "STM32L071RZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072V8 bool "STM32L072V8" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VB bool "STM32L072VB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VZ bool "STM32L072VZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KB @@ -846,29 +846,29 @@ config ARCH_CHIP_STM32L072KZ config ARCH_CHIP_STM32L072CB bool "STM32L072CB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CZ bool "STM32L072CZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RB bool "STM32L072RB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RZ bool "STM32L072RZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073V8 @@ -909,683 +909,623 @@ config ARCH_CHIP_STM32L073RZ config ARCH_CHIP_STM32C051D8 bool "STM32C051D8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051F6 bool "STM32C051F6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051F8 bool "STM32C051F8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051G6 bool "STM32C051G6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051G8 bool "STM32C051G8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051K6 bool "STM32C051K6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051K8 bool "STM32C051K8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051C6 bool "STM32C051C6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051C8 bool "STM32C051C8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071F8 bool "STM32C071F8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071FB bool "STM32C071FB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071G8 bool "STM32C071G8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071GB bool "STM32C071GB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071K8 bool "STM32C071K8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071KB bool "STM32C071KB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071C8 bool "STM32C071C8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071CB bool "STM32C071CB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071R8 bool "STM32C071R8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071RB bool "STM32C071RB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091FB bool "STM32C091FB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091FC bool "STM32C091FC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091EC bool "STM32C091EC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091GB bool "STM32C091GB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091GC bool "STM32C091GC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091KB bool "STM32C091KB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091KC bool "STM32C091KC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091CB bool "STM32C091CB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091CC bool "STM32C091CC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091RB bool "STM32C091RB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091RC bool "STM32C091RC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092FB bool "STM32C092FB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092FC bool "STM32C092FC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092EC bool "STM32C092EC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092GB bool "STM32C092GB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092GC bool "STM32C092GC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092KB bool "STM32C092KB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092KC bool "STM32C092KC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092CB bool "STM32C092CB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092CC bool "STM32C092CC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092RB bool "STM32C092RB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092RC bool "STM32C092RC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C endchoice # ST STM32F0/L0/G0/C0 Chip Selection # Flash configurations -config STM32F0L0G0_FLASH_CONFIG_4 +config STM32_FLASH_CONFIG_4 bool default n -config STM32F0L0G0_FLASH_CONFIG_6 +config STM32_FLASH_CONFIG_6 bool default n -config STM32F0L0G0_FLASH_CONFIG_8 +config STM32_FLASH_CONFIG_8 bool default n -config STM32F0L0G0_FLASH_CONFIG_B +config STM32_FLASH_CONFIG_B bool default n -config STM32F0L0G0_FLASH_CONFIG_C +config STM32_FLASH_CONFIG_C bool default n -config STM32F0L0G0_FLASH_CONFIG_D +config STM32_FLASH_CONFIG_D bool default n -config STM32F0L0G0_FLASH_CONFIG_E +config STM32_FLASH_CONFIG_E bool default n -config STM32F0L0G0_FLASH_CONFIG_F +config STM32_FLASH_CONFIG_F bool default n -config STM32F0L0G0_FLASH_CONFIG_G +config STM32_FLASH_CONFIG_G bool default n -config STM32F0L0G0_FLASH_CONFIG_I +config STM32_FLASH_CONFIG_I bool default n -config STM32F0L0G0_FLASH_OVERRIDE +config STM32_FLASH_OVERRIDE bool "Override Flash Designator" default n -choice - prompt "Override Flash Size Designator" - depends on STM32F0L0G0_FLASH_OVERRIDE - default STM32F0L0G0_FLASH_OVERRIDE_B - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - -config STM32F0L0G0_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # Override Flash Size Designator - -config STM32F0L0G0_STM32F0 - bool - default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 - -config STM32F0L0G0_STM32G0 - bool - default n - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_I2C2 + +config STM32_STM32F0 + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_EXTI_V1 + +config STM32_STM32G0 + bool + default n + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C2 select ARCH_HAVE_PROGMEM -config STM32F0L0G0_STM32L0 +config STM32_STM32L0 bool default n - select STM32F0L0G0_ENERGYLITE - select STM32F0L0G0_HAVE_VREFINT - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 + select STM32_ENERGYLITE + select STM32_HAVE_VREFINT + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_EXTI_V1 -config STM32F0L0G0_STM32C0 +config STM32_STM32C0 bool default n - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 select ARCH_HAVE_PROGMEM -config STM32F0L0G0_STM32F03X +config STM32_STM32F03X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F04X +config STM32_STM32F04X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F05X +config STM32_STM32F05X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F07X +config STM32_STM32F07X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F09X +config STM32_STM32F09X bool default n - select STM32F0L0G0_STM32F0 - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_DMA2 + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 -config STM32F0L0G0_STM32G030 +config STM32_STM32G030 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X + select STM32_STM32G0 + select STM32_STM32G03X -config STM32F0L0G0_STM32G031 +config STM32_STM32G031 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G03X + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G03X +config STM32_STM32G03X bool default n -config STM32F0L0G0_STM32G041 +config STM32_STM32G041 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G050 +config STM32_STM32G050 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X + select STM32_STM32G0 + select STM32_STM32G05X -config STM32F0L0G0_STM32G051 +config STM32_STM32G051 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G05X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G05X +config STM32_STM32G05X bool default n - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 -config STM32F0L0G0_STM32G061 +config STM32_STM32G061 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G070 +config STM32_STM32G070 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X + select STM32_STM32G0 + select STM32_STM32G07X -config STM32F0L0G0_STM32G071 +config STM32_STM32G071 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G07X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G07X +config STM32_STM32G07X bool default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 -config STM32F0L0G0_STM32G081 +config STM32_STM32G081 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G0B0 +config STM32_STM32G0B0 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX + select STM32_STM32G0 + select STM32_STM32G0BX -config STM32F0L0G0_STM32G0B1 +config STM32_STM32G0B1 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC + select STM32_STM32G0 + select STM32_STM32G0BX + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC -config STM32F0L0G0_STM32G0BX +config STM32_STM32G0BX bool default n - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_LPUART1 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_CRS + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_HSI48 -config STM32F0L0G0_STM32G0C1 +config STM32_STM32G0C1 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_HSI48 - -config STM32F0L0G0_VALUELINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 + select STM32_STM32G0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_CRS + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_LPUART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + select STM32_HAVE_HSI48 + +config STM32_VALUELINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 -config STM32F0L0G0_ACCESSLINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - -config STM32F0L0G0_LOWVOLTLINE - bool - default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 +config STM32_ACCESSLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32_LOWVOLTLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 -config STM32F0L0G0_USBLINE +config STM32_USBLINE bool default n - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_USBDEV + select STM32_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + select STM32_HAVE_USBDEV -config STM32F0L0G0_ENERGYLITE +config STM32_ENERGYLITE bool default n config ARCH_CHIP_STM32L053XX bool - select STM32F0L0G0_STM32L0 + select STM32_STM32L0 config ARCH_CHIP_STM32L071XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 config ARCH_CHIP_STM32L072XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_I2C2 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32L073XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32C051XX bool - select STM32F0L0G0_STM32C0 + select STM32_STM32C0 config ARCH_CHIP_STM32C071XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32C0 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32C091XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM15 + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM15 config ARCH_CHIP_STM32C092XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_FDCAN1 + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_FDCAN1 -config STM32F0L0G0_DFU +config STM32_DFU bool "DFU bootloader" default n - depends on !STM32F0L0G0_VALUELINE + depends on !STM32_VALUELINE ---help--- Configure and position code for use with the STMicro DFU bootloader. Do not select this option if you will load code using JTAG/SWM. -config STM32F0L0G0_PROGMEM +config STM32_PROGMEM bool "Flash PROGMEM support" default n depends on ARCH_HAVE_PROGMEM @@ -1597,623 +1537,617 @@ config STM32F0L0G0_PROGMEM choice prompt "SysTick clock source" - default STM32F0L0G0_SYSTICK_CORECLK + default STM32_SYSTICK_CORECLK -config STM32F0L0G0_SYSTICK_CORECLK +config STM32_SYSTICK_CORECLK bool "Cortex-M0 core clock" -config STM32F0L0G0_SYSTICK_CORECLK_DIV16 +config STM32_SYSTICK_CORECLK_DIV16 bool "Cortex-M0 core clock divided by 16" endchoice # SysTick clock source -config ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available # for the selected MCU -config STM32F0L0G0_HAVE_AES +config STM32_HAVE_AES bool default n -config STM32F0L0G0_HAVE_VREFINT +config STM32_HAVE_VREFINT bool default n -config STM32F0L0G0_HAVE_CCM +config STM32_HAVE_CCM bool default n -config STM32F0L0G0_HAVE_HSI48 +config STM32_HAVE_HSI48 bool default n -config STM32F0L0G0_HAVE_LCD +config STM32_HAVE_LCD bool default n -config STM32F0L0G0_HAVE_USBDEV +config STM32_HAVE_USBDEV bool default n -config STM32F0L0G0_HAVE_FSMC +config STM32_HAVE_FSMC bool default n -config STM32F0L0G0_HAVE_USART3 +config STM32_HAVE_USART3 bool default n -config STM32F0L0G0_HAVE_USART4 +config STM32_HAVE_USART4 bool default n -config STM32F0L0G0_HAVE_USART5 +config STM32_HAVE_USART5 bool default n -config STM32F0L0G0_HAVE_USART6 +config STM32_HAVE_USART6 bool default n -config STM32F0L0G0_HAVE_USART7 +config STM32_HAVE_USART7 bool default n -config STM32F0L0G0_HAVE_USART8 +config STM32_HAVE_USART8 bool default n -config STM32F0L0G0_HAVE_LPUART1 +config STM32_HAVE_LPUART1 bool default n -config STM32F0L0G0_HAVE_LPUART2 +config STM32_HAVE_LPUART2 bool default n -config STM32F0L0G0_HAVE_TIM1 +config STM32_HAVE_TIM1 bool default n -config STM32F0L0G0_HAVE_TIM2 +config STM32_HAVE_TIM2 bool default n -config STM32F0L0G0_HAVE_TIM3 +config STM32_HAVE_TIM3 bool default n -config STM32F0L0G0_HAVE_TIM4 +config STM32_HAVE_TIM4 bool default n -config STM32F0L0G0_HAVE_TIM6 +config STM32_HAVE_TIM6 bool default n -config STM32F0L0G0_HAVE_TIM7 +config STM32_HAVE_TIM7 bool default n -config STM32F0L0G0_HAVE_TIM14 +config STM32_HAVE_TIM14 bool default n -config STM32F0L0G0_HAVE_TIM15 +config STM32_HAVE_TIM15 bool default n -config STM32F0L0G0_HAVE_TIM16 +config STM32_HAVE_TIM16 bool default n -config STM32F0L0G0_HAVE_TIM17 +config STM32_HAVE_TIM17 bool default n -config STM32F0L0G0_HAVE_TSC +config STM32_HAVE_TSC bool default n -config STM32F0L0G0_HAVE_ADC1_DMA +config STM32_HAVE_ADC1_DMA bool default n -config STM32F0L0G0_HAVE_ADC_OVERSAMPLE +config STM32_HAVE_ADC_OVERSAMPLE bool - default STM32F0L0G0_STM32L0 || STM32F0L0G0_STM32G0 || STM32F0L0G0_STM32C0 + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 -config STM32F0L0G0_HAVE_CEC +config STM32_HAVE_CEC bool default n -config STM32F0L0G0_HAVE_CAN1 +config STM32_HAVE_CAN1 bool default n -config STM32F0L0G0_HAVE_COMP1 +config STM32_HAVE_COMP1 bool default n -config STM32F0L0G0_HAVE_COMP2 +config STM32_HAVE_COMP2 bool default n -config STM32F0L0G0_HAVE_COMP3 +config STM32_HAVE_COMP3 bool default n -config STM32F0L0G0_HAVE_DAC1 +config STM32_HAVE_DAC1 bool default n -config STM32F0L0G0_HAVE_DMAMUX +config STM32_HAVE_DMAMUX bool default n -config STM32F0L0G0_HAVE_DMA2 +config STM32_HAVE_DMA2 bool default n -config STM32F0L0G0_HAVE_RNG +config STM32_HAVE_RNG bool default n -config STM32F0L0G0_HAVE_CRS +config STM32_HAVE_CRS bool default n -config STM32F0L0G0_HAVE_I2C2 +config STM32_HAVE_I2C2 bool default n -config STM32F0L0G0_HAVE_I2C3 +config STM32_HAVE_I2C3 bool default n -config STM32F0L0G0_HAVE_SPI2 +config STM32_HAVE_SPI2 bool default n -config STM32F0L0G0_HAVE_SPI3 +config STM32_HAVE_SPI3 bool default n -config STM32F0L0G0_HAVE_SAIPLL +config STM32_HAVE_SAIPLL bool default n -config STM32F0L0G0_HAVE_SDIO +config STM32_HAVE_SDIO bool default n -config STM32F0L0G0_HAVE_I2SPLL +config STM32_HAVE_I2SPLL bool default n -config STM32F0L0G0_HAVE_OPAMP1 +config STM32_HAVE_OPAMP1 bool default n -config STM32F0L0G0_HAVE_OPAMP2 +config STM32_HAVE_OPAMP2 bool default n -config STM32F0L0G0_HAVE_OPAMP3 +config STM32_HAVE_OPAMP3 bool default n -config STM32F0L0G0_HAVE_OPAMP4 +config STM32_HAVE_OPAMP4 bool default n -config STM32F0L0G0_HAVE_FDCAN1 +config STM32_HAVE_FDCAN1 bool default n -config STM32F0L0G0_HAVE_FDCAN2 +config STM32_HAVE_FDCAN2 bool default n -config STM32F0L0G0_HAVE_I2S2 +config STM32_HAVE_I2S2 bool default n -config STM32F0L0G0_HAVE_UCPD1 +config STM32_HAVE_UCPD1 bool default n -config STM32F0L0G0_HAVE_UCPD2 +config STM32_HAVE_UCPD2 bool default n # These are STM32 peripherals IP blocks -config STM32F0L0G0_HAVE_IP_USART_V1 +config STM32_HAVE_IP_USART_V1 bool default n -config STM32F0L0G0_HAVE_IP_USART_V2 +config STM32_HAVE_IP_USART_V2 bool default n -config STM32F0L0G0_HAVE_IP_EXTI_V1 +config STM32_HAVE_IP_EXTI_V1 bool default n -config STM32F0L0G0_HAVE_IP_EXTI_V2 +config STM32_HAVE_IP_EXTI_V2 bool default n # These are the peripheral selections proper -config STM32F0L0G0_ADC1 +config STM32_ADC1 bool "ADC1" default n - select STM32F0L0G0_ADC + select STM32_ADC -config STM32F0L0G0_COMP1 +config STM32_COMP1 bool "COMP1" default n - depends on STM32F0L0G0_HAVE_COMP1 + depends on STM32_HAVE_COMP1 -config STM32F0L0G0_COMP2 +config STM32_COMP2 bool "COMP2" default n - depends on STM32F0L0G0_HAVE_COMP2 + depends on STM32_HAVE_COMP2 -config STM32F0L0G0_BKP +config STM32_BKP bool "BKP" default n -config STM32F0L0G0_BKPSRAM +config STM32_BKPSRAM bool "Enable BKP RAM Domain" default n -config STM32F0L0G0_CAN1 +config STM32_CAN1 bool "CAN1" default n select CAN - select STM32F0L0G0_CAN - depends on STM32F0L0G0_HAVE_CAN1 + select STM32_CAN + depends on STM32_HAVE_CAN1 -config STM32F0L0G0_AES +config STM32_AES bool "128-bit AES" default n - depends on STM32F0L0G0_HAVE_AES + depends on STM32_HAVE_AES select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST -config STM32F0L0G0_VREFINT +config STM32_VREFINT bool "Enable VREFINT" default n - depends on STM32F0L0G0_HAVE_VREFINT + depends on STM32_HAVE_VREFINT -config STM32F0L0G0_CEC +config STM32_CEC bool "CEC" default n - depends on STM32F0L0G0_HAVE_CEC + depends on STM32_HAVE_CEC -config STM32F0L0G0_CRC +config STM32_CRC bool "CRC" default n -config STM32F0L0G0_CRYP +config STM32_CRYP bool "CRYP" default n - depends on STM32F0L0G0_HAVE_HASH + depends on STM32_HAVE_HASH -config STM32F0L0G0_DMA1 +config STM32_DMA1 bool "DMA1" default n select ARCH_DMA - select STM32F0L0G0_DMA + select STM32_DMA -config STM32F0L0G0_DMA2 +config STM32_DMA2 bool "DMA2" default n - depends on STM32F0L0G0_HAVE_DMA2 + depends on STM32_HAVE_DMA2 select ARCH_DMA - select STM32F0L0G0_DMA + select STM32_DMA -config STM32F0L0G0_DAC1 +config STM32_DAC1 bool "DAC1" default n - depends on STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_DAC + depends on STM32_HAVE_DAC1 + select STM32_DAC -config STM32F0L0G0_FDCAN1 +config STM32_FDCAN1 bool "FDCAN1" default n - depends on STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_FDCAN + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN -config STM32F0L0G0_FSMC +config STM32_FSMC bool "FSMC" default n - depends on STM32F0L0G0_HAVE_FSMC + depends on STM32_HAVE_FSMC -config STM32F0L0G0_HASH +config STM32_HASH bool "HASH" default n - depends on STM32F0L0G0_HAVE_HASH + depends on STM32_HAVE_HASH -config STM32F0L0G0_I2C1 +config STM32_I2C1 bool "I2C1" default n - select STM32F0L0G0_I2C + select STM32_I2C -config STM32F0L0G0_I2C2 +config STM32_I2C2 bool "I2C2" default n - depends on STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_I2C + depends on STM32_HAVE_I2C2 + select STM32_I2C -config STM32F0L0G0_I2C3 +config STM32_I2C3 bool "I2C3" default n - depends on STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_I2C + depends on STM32_HAVE_I2C3 + select STM32_I2C -config STM32F0L0G0_PWR +config STM32_PWR bool "PWR" default n -config STM32F0L0G0_RNG +config STM32_RNG bool "RNG" default n - depends on STM32F0L0G0_HAVE_RNG + depends on STM32_HAVE_RNG select ARCH_HAVE_RNG -config STM32F0L0G0_SDIO +config STM32_SDIO bool "SDIO" default n - depends on STM32F0L0G0_HAVE_SDIO + depends on STM32_HAVE_SDIO select ARCH_HAVE_SDIO select ARCH_HAVE_SDIOWAIT_WRCOMPLETE select ARCH_HAVE_SDIO_PREFLIGHT -config STM32F0L0G0_SPI1 +config STM32_SPI1 bool "SPI1" default n select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SPI2 +config STM32_SPI2 bool "SPI2" default n - depends on STM32F0L0G0_HAVE_SPI2 + depends on STM32_HAVE_SPI2 select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SPI3 +config STM32_SPI3 bool "SPI3" default n - depends on STM32F0L0G0_HAVE_SPI3 + depends on STM32_HAVE_SPI3 select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SYSCFG +config STM32_SYSCFG bool "SYSCFG" default y -config STM32F0L0G0_TIM1 +config STM32_TIM1 bool "TIM1" default n - depends on STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM1 + select STM32_TIM -config STM32F0L0G0_TIM2 +config STM32_TIM2 bool "TIM2" default n - depends on STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM2 + select STM32_TIM -config STM32F0L0G0_TIM3 +config STM32_TIM3 bool "TIM3" default n - depends on STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM3 + select STM32_TIM -config STM32F0L0G0_TIM6 +config STM32_TIM6 bool "TIM6" default n - depends on STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM6 + select STM32_TIM -config STM32F0L0G0_TIM7 +config STM32_TIM7 bool "TIM7" default n - depends on STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM7 + select STM32_TIM -config STM32F0L0G0_TIM14 +config STM32_TIM14 bool "TIM14" default n - depends on STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM14 + select STM32_TIM -config STM32F0L0G0_TIM15 +config STM32_TIM15 bool "TIM15" default n - depends on STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM15 + select STM32_TIM -config STM32F0L0G0_TIM16 +config STM32_TIM16 bool "TIM16" default n - depends on STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM16 + select STM32_TIM -config STM32F0L0G0_TIM17 +config STM32_TIM17 bool "TIM17" default n - depends on STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM17 + select STM32_TIM -config STM32F0L0G0_TSC +config STM32_TSC bool "TSC" default n - depends on STM32F0L0G0_HAVE_TSC + depends on STM32_HAVE_TSC -config STM32F0L0G0_USART1 +config STM32_USART1 bool "USART1" default n - select STM32F0L0G0_USART + select STM32_USART -config STM32F0L0G0_USART2 +config STM32_USART2 bool "USART2" default n - select STM32F0L0G0_USART + select STM32_USART -config STM32F0L0G0_USART3 +config STM32_USART3 bool "USART3" default n - depends on STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART3 + select STM32_USART -config STM32F0L0G0_USART4 +config STM32_USART4 bool "USART4" default n - depends on STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART4 + select STM32_USART -config STM32F0L0G0_USART5 +config STM32_USART5 bool "USART5" default n - depends on STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART5 + select STM32_USART -config STM32F0L0G0_USART6 +config STM32_USART6 bool "USART6" default n - depends on STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART6 + select STM32_USART -config STM32F0L0G0_USART7 +config STM32_USART7 bool "USART7" default n - depends on STM32F0L0G0_HAVE_USART7 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART7 + select STM32_USART -config STM32F0L0G0_USART8 +config STM32_USART8 bool "USART8" default n - depends on STM32F0L0G0_HAVE_USART8 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART8 + select STM32_USART -config STM32F0L0G0_USB +config STM32_USB bool "USB Device" default n - depends on STM32F0L0G0_HAVE_USBDEV + depends on STM32_HAVE_USBDEV select USBDEV -config STM32F0L0G0_LCD +config STM32_LCD bool "Segment LCD" default n - depends on STM32F0L0G0_HAVE_LCD + depends on STM32_HAVE_LCD select USBDEV -config STM32F0L0G0_IWDG +config STM32_IWDG bool "IWDG" default n select WATCHDOG -config STM32F0L0G0_WWDG +config STM32_WWDG bool "WWDG" default n select WATCHDOG endmenu # STM32 Peripheral Support -config STM32F0L0G0_COMP +config STM32_COMP bool default n -config STM32F0L0G0_ADC +config STM32_ADC bool default n -config STM32F0L0G0_DAC +config STM32_DAC bool default n -config STM32F0L0G0_DMA +config STM32_DMA bool default n -config STM32F0L0G0_SPI +config STM32_SPI bool -config STM32F0L0G0_SPI_DMA +config STM32_SPI_DMA bool default n -config STM32F0L0G0_I2C +config STM32_I2C bool default n -config STM32F0L0G0_CAN +config STM32_CAN bool default n -config STM32F0L0G0_PWM +config STM32_PWM bool default n -config STM32F0L0G0_USART +config STM32_USART bool default n -config STM32F0L0G0_TIM +config STM32_TIM bool default n -config STM32F0L0G0_FDCAN +config STM32_FDCAN bool default n -config STM32F0L0G0_SERIALDRIVER +config STM32_SERIALDRIVER bool default n -config STM32F0L0G0_1WIREDRIVER +config STM32_1WIREDRIVER bool default n menu "Timer Configuration" -config STM32F0L0G0_TIM1_PULSECOUNT +config STM32_TIM1_PULSECOUNT bool "TIM1 pulse count" default n - depends on STM32F0L0G0_TIM1 + depends on STM32_TIM1 select ARCH_HAVE_PULSECOUNT select PULSECOUNT ---help--- Reserve timer 1 for use by the pulse count driver. - Timer devices may be used for different purposes. If STM32F0L0G0_TIM1 + Timer devices may be used for different purposes. If STM32_TIM1 is defined then this option may also be defined to indicate that TIM1 is intended to generate a fixed number of output pulses. -config STM32F0L0G0_TIM1_PWM +config STM32_TIM1_PWM bool "TIM1 PWM" default n - depends on STM32F0L0G0_TIM1 && !STM32F0L0G0_TIM1_PULSECOUNT - select STM32F0L0G0_PWM + depends on STM32_TIM1 && !STM32_TIM1_PULSECOUNT + select STM32_PWM ---help--- Reserve timer 1 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM1 is defined then this option may also be defined to + STM32_TIM1 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2225,9 +2159,9 @@ config STM32F0L0G0_TIM1_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM1_PWM +if STM32_TIM1_PWM -config STM32F0L0G0_TIM1_MODE +config STM32_TIM1_MODE int "TIM1 Mode" default 0 range 0 4 @@ -2240,126 +2174,126 @@ config STM32F0L0G0_TIM1_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM1_CHANNEL1 +config STM32_TIM1_CHANNEL1 bool "TIM1 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM1_CHANNEL1 +if STM32_TIM1_CHANNEL1 -config STM32F0L0G0_TIM1_CH1MODE +config STM32_TIM1_CH1MODE int "TIM1 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH1OUT +config STM32_TIM1_CH1OUT bool "TIM1 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM1_CH1NOUT +config STM32_TIM1_CH1NOUT bool "TIM1 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH1OUT + depends on STM32_TIM1_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL1 +endif # STM32_TIM1_CHANNEL1 -config STM32F0L0G0_TIM1_CHANNEL2 +config STM32_TIM1_CHANNEL2 bool "TIM1 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM1_CHANNEL2 +if STM32_TIM1_CHANNEL2 -config STM32F0L0G0_TIM1_CH2MODE +config STM32_TIM1_CH2MODE int "TIM1 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH2OUT +config STM32_TIM1_CH2OUT bool "TIM1 Channel 2 Output" default n ---help--- Enables channel 2 output. -config STM32F0L0G0_TIM1_CH2NOUT +config STM32_TIM1_CH2NOUT bool "TIM1 Channel 2 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH2OUT + depends on STM32_TIM1_CH2OUT ---help--- Enables channel 2 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL2 +endif # STM32_TIM1_CHANNEL2 -config STM32F0L0G0_TIM1_CHANNEL3 +config STM32_TIM1_CHANNEL3 bool "TIM1 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM1_CHANNEL3 +if STM32_TIM1_CHANNEL3 -config STM32F0L0G0_TIM1_CH3MODE +config STM32_TIM1_CH3MODE int "TIM1 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH3OUT +config STM32_TIM1_CH3OUT bool "TIM1 Channel 3 Output" default n ---help--- Enables channel 3 output. -config STM32F0L0G0_TIM1_CH3NOUT +config STM32_TIM1_CH3NOUT bool "TIM1 Channel 3 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH3OUT + depends on STM32_TIM1_CH3OUT ---help--- Enables channel 3 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL3 +endif # STM32_TIM1_CHANNEL3 -config STM32F0L0G0_TIM1_CHANNEL4 +config STM32_TIM1_CHANNEL4 bool "TIM1 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM1_CHANNEL4 +if STM32_TIM1_CHANNEL4 -config STM32F0L0G0_TIM1_CH4MODE +config STM32_TIM1_CH4MODE int "TIM1 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH4OUT +config STM32_TIM1_CH4OUT bool "TIM1 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM1_CHANNEL4 +endif # STM32_TIM1_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM1_CHANNEL +config STM32_TIM1_CHANNEL int "TIM1 PWM Output Channel" default 1 range 1 4 @@ -2367,46 +2301,46 @@ config STM32F0L0G0_TIM1_CHANNEL If TIM1 is enabled for output usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM1_CHMODE +config STM32_TIM1_CHMODE int "TIM1 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM1_PWM +endif # STM32_TIM1_PWM -if STM32F0L0G0_TIM1_PULSECOUNT +if STM32_TIM1_PULSECOUNT -config STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL +config STM32_TIM1_PULSECOUNT_CHANNEL int "TIM1 pulse count channel" default 1 range 1 4 ---help--- Specifies the timer channel {1,..,4}. -endif # STM32F0L0G0_TIM1_PULSECOUNT +endif # STM32_TIM1_PULSECOUNT -config STM32F0L0G0_TIM1_QE +config STM32_TIM1_QE bool "TIM1 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM1 + depends on STM32_TIM1 ---help--- Reserve TIM1 for use by Quadrature Encoder. -config STM32F0L0G0_TIM2_PWM +config STM32_TIM2_PWM bool "TIM2 PWM" default n - depends on STM32F0L0G0_TIM2 - select STM32F0L0G0_PWM + depends on STM32_TIM2 + select STM32_PWM ---help--- Reserve timer 2 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM2 is defined then THIS option may also be defined to + STM32_TIM2 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2418,9 +2352,9 @@ config STM32F0L0G0_TIM2_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM2_PWM +if STM32_TIM2_PWM -config STM32F0L0G0_TIM2_MODE +config STM32_TIM2_MODE int "TIM2 Mode" default 0 range 0 4 @@ -2433,105 +2367,105 @@ config STM32F0L0G0_TIM2_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM2_CHANNEL1 +config STM32_TIM2_CHANNEL1 bool "TIM2 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM2_CHANNEL1 +if STM32_TIM2_CHANNEL1 -config STM32F0L0G0_TIM2_CH1MODE +config STM32_TIM2_CH1MODE int "TIM2 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH1OUT +config STM32_TIM2_CH1OUT bool "TIM2 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM2_CHANNEL1 +endif # STM32_TIM2_CHANNEL1 -config STM32F0L0G0_TIM2_CHANNEL2 +config STM32_TIM2_CHANNEL2 bool "TIM2 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM2_CHANNEL2 +if STM32_TIM2_CHANNEL2 -config STM32F0L0G0_TIM2_CH2MODE +config STM32_TIM2_CH2MODE int "TIM2 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH2OUT +config STM32_TIM2_CH2OUT bool "TIM2 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM2_CHANNEL2 +endif # STM32_TIM2_CHANNEL2 -config STM32F0L0G0_TIM2_CHANNEL3 +config STM32_TIM2_CHANNEL3 bool "TIM2 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM2_CHANNEL3 +if STM32_TIM2_CHANNEL3 -config STM32F0L0G0_TIM2_CH3MODE +config STM32_TIM2_CH3MODE int "TIM2 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH3OUT +config STM32_TIM2_CH3OUT bool "TIM2 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32F0L0G0_TIM2_CHANNEL3 +endif # STM32_TIM2_CHANNEL3 -config STM32F0L0G0_TIM2_CHANNEL4 +config STM32_TIM2_CHANNEL4 bool "TIM2 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM2_CHANNEL4 +if STM32_TIM2_CHANNEL4 -config STM32F0L0G0_TIM2_CH4MODE +config STM32_TIM2_CH4MODE int "TIM2 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH4OUT +config STM32_TIM2_CH4OUT bool "TIM2 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM2_CHANNEL4 +endif # STM32_TIM2_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM2_CHANNEL +config STM32_TIM2_CHANNEL int "TIM2 PWM Output Channel" default 1 range 1 4 @@ -2539,35 +2473,35 @@ config STM32F0L0G0_TIM2_CHANNEL If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM2_CHMODE +config STM32_TIM2_CHMODE int "TIM2 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM2_PWM +endif # STM32_TIM2_PWM -config STM32F0L0G0_TIM2_QE +config STM32_TIM2_QE bool "TIM2 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM2 + depends on STM32_TIM2 ---help--- Reserve TIM2 for use by Quadrature Encoder. -config STM32F0L0G0_TIM3_PWM +config STM32_TIM3_PWM bool "TIM3 PWM" default n - depends on STM32F0L0G0_TIM3 - select STM32F0L0G0_PWM + depends on STM32_TIM3 + select STM32_PWM ---help--- Reserve timer 3 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM3 is defined then THIS option may also be defined to + STM32_TIM3 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2579,9 +2513,9 @@ config STM32F0L0G0_TIM3_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM3_PWM +if STM32_TIM3_PWM -config STM32F0L0G0_TIM3_MODE +config STM32_TIM3_MODE int "TIM3 Mode" default 0 range 0 4 @@ -2594,105 +2528,105 @@ config STM32F0L0G0_TIM3_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM3_CHANNEL1 +config STM32_TIM3_CHANNEL1 bool "TIM3 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM3_CHANNEL1 +if STM32_TIM3_CHANNEL1 -config STM32F0L0G0_TIM3_CH1MODE +config STM32_TIM3_CH1MODE int "TIM3 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH1OUT +config STM32_TIM3_CH1OUT bool "TIM3 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM3_CHANNEL1 +endif # STM32_TIM3_CHANNEL1 -config STM32F0L0G0_TIM3_CHANNEL2 +config STM32_TIM3_CHANNEL2 bool "TIM3 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM3_CHANNEL2 +if STM32_TIM3_CHANNEL2 -config STM32F0L0G0_TIM3_CH2MODE +config STM32_TIM3_CH2MODE int "TIM3 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH2OUT +config STM32_TIM3_CH2OUT bool "TIM3 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM3_CHANNEL2 +endif # STM32_TIM3_CHANNEL2 -config STM32F0L0G0_TIM3_CHANNEL3 +config STM32_TIM3_CHANNEL3 bool "TIM3 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM3_CHANNEL3 +if STM32_TIM3_CHANNEL3 -config STM32F0L0G0_TIM3_CH3MODE +config STM32_TIM3_CH3MODE int "TIM3 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH3OUT +config STM32_TIM3_CH3OUT bool "TIM3 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32F0L0G0_TIM3_CHANNEL3 +endif # STM32_TIM3_CHANNEL3 -config STM32F0L0G0_TIM3_CHANNEL4 +config STM32_TIM3_CHANNEL4 bool "TIM3 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM3_CHANNEL4 +if STM32_TIM3_CHANNEL4 -config STM32F0L0G0_TIM3_CH4MODE +config STM32_TIM3_CH4MODE int "TIM3 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH4OUT +config STM32_TIM3_CH4OUT bool "TIM3 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM3_CHANNEL4 +endif # STM32_TIM3_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM3_CHANNEL +config STM32_TIM3_CHANNEL int "TIM3 PWM Output Channel" default 1 range 1 4 @@ -2700,68 +2634,68 @@ config STM32F0L0G0_TIM3_CHANNEL If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM3_CHMODE +config STM32_TIM3_CHMODE int "TIM3 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM3_PWM +endif # STM32_TIM3_PWM -config STM32F0L0G0_TIM3_QE +config STM32_TIM3_QE bool "TIM3 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM3 + depends on STM32_TIM3 ---help--- Reserve TIM3 for use by Quadrature Encoder. -config STM32F0L0G0_TIM4_QE +config STM32_TIM4_QE bool "TIM3 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM4 + depends on STM32_TIM4 ---help--- Reserve TIM4 for use by Quadrature Encoder. menu "STM32F0L0G0 QEncoder Driver" depends on SENSORS_QENCODER - depends on STM32F0L0G0_TIM1 || STM32F0L0G0_TIM2 || STM32F0L0G0_TIM3 || STM32F0L0G0_TIM4 + depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 -config STM32F0L0G0_TIM1_QEPSC +config STM32_TIM1_QEPSC int "TIM1 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM1_QE + depends on STM32_TIM1_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM2_QEPSC +config STM32_TIM2_QEPSC int "TIM2 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM2_QE + depends on STM32_TIM2_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM3_QEPSC +config STM32_TIM3_QEPSC int "TIM3 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM3_QE + depends on STM32_TIM3_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM4_QEPSC +config STM32_TIM4_QEPSC int "TIM3 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM4_QE + depends on STM32_TIM4_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS bool "Disable QEncoder timers extension from 16-bit to 32-bit" default n ---help--- @@ -2770,7 +2704,7 @@ config STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS counter width (16-bit or 32-bit). This reduces interrupt overhead but limits the position range for 16-bit timers. -config STM32F0L0G0_QENCODER_INDEX_PIN +config STM32_QENCODER_INDEX_PIN bool "Enable QEncoder timers support for index pin" default n ---help--- @@ -2778,122 +2712,61 @@ config STM32F0L0G0_QENCODER_INDEX_PIN used to reset the encoder position to a known value when the index pulse is detected. -config STM32F0L0G0_QENCODER_FILTER +config STM32_QENCODER_FILTER bool "Enable filtering on STM32F0L0G0 QEncoder input" default y ---help--- Enable input filtering on quadrature encoder channels to reduce noise. -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - ---help--- - Select the sampling frequency for the input filter. - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "fCK_INT" -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel event count" - default STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - ---help--- - Select the number of consecutive events required to validate a transition. - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_1 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_2 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_4 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_5 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 || STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS && !STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice endmenu # STM32F0L0G0 QEncoder Driver -config STM32F0L0G0_TIM14_PWM +config STM32_TIM14_PWM bool "TIM14 PWM" default n - depends on STM32F0L0G0_TIM14 - select STM32F0L0G0_PWM + depends on STM32_TIM14 + select STM32_PWM ---help--- Reserve timer 14 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM14 + to generate modulated outputs for such things as motor control. If STM32_TIM14 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM14_PWM +if STM32_TIM14_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM14_CHANNEL1 +config STM32_TIM14_CHANNEL1 bool "TIM14 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM14_CHANNEL1 +if STM32_TIM14_CHANNEL1 -config STM32F0L0G0_TIM14_CH1MODE +config STM32_TIM14_CH1MODE int "TIM14 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM14_CH1OUT +config STM32_TIM14_CH1OUT bool "TIM14 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM14_CHANNEL1 +endif # STM32_TIM14_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM14_CHANNEL +config STM32_TIM14_CHANNEL int "TIM14 PWM Output Channel" default 1 range 1 1 @@ -2901,92 +2774,92 @@ config STM32F0L0G0_TIM14_CHANNEL If TIM14 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM14_CHMODE +config STM32_TIM14_CHMODE int "TIM14 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM14_PWM +endif # STM32_TIM14_PWM -config STM32F0L0G0_TIM15_PWM +config STM32_TIM15_PWM bool "TIM15 PWM" default n - depends on STM32F0L0G0_TIM15 - select STM32F0L0G0_PWM + depends on STM32_TIM15 + select STM32_PWM ---help--- Reserve timer 15 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM15 + to generate modulated outputs for such things as motor control. If STM32_TIM15 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM15_PWM +if STM32_TIM15_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM15_CHANNEL1 +config STM32_TIM15_CHANNEL1 bool "TIM15 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM15_CHANNEL1 +if STM32_TIM15_CHANNEL1 -config STM32F0L0G0_TIM15_CH1MODE +config STM32_TIM15_CH1MODE int "TIM15 Channel 1 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM15_CH1OUT +config STM32_TIM15_CH1OUT bool "TIM15 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM15_CH1NOUT +config STM32_TIM15_CH1NOUT bool "TIM15 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM15_CH1OUT + depends on STM32_TIM15_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM15_CHANNEL1 +endif # STM32_TIM15_CHANNEL1 -config STM32F0L0G0_TIM15_CHANNEL2 +config STM32_TIM15_CHANNEL2 bool "TIM15 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM15_CHANNEL2 +if STM32_TIM15_CHANNEL2 -config STM32F0L0G0_TIM15_CH2MODE +config STM32_TIM15_CH2MODE int "TIM15 Channel 2 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM15_CH2OUT +config STM32_TIM15_CH2OUT bool "TIM15 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM15_CHANNEL2 +endif # STM32_TIM15_CHANNEL2 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM15_CHANNEL +config STM32_TIM15_CHANNEL int "TIM15 PWM Output Channel" default 1 range 1 2 @@ -2994,69 +2867,69 @@ config STM32F0L0G0_TIM15_CHANNEL If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} -config STM32F0L0G0_TIM15_CHMODE +config STM32_TIM15_CHMODE int "TIM15 Channel Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM15_PWM +endif # STM32_TIM15_PWM -config STM32F0L0G0_TIM16_PWM +config STM32_TIM16_PWM bool "TIM16 PWM" default n - depends on STM32F0L0G0_TIM16 - select STM32F0L0G0_PWM + depends on STM32_TIM16 + select STM32_PWM ---help--- Reserve timer 16 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM16 + to generate modulated outputs for such things as motor control. If STM32_TIM16 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM16_PWM +if STM32_TIM16_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM16_CHANNEL1 +config STM32_TIM16_CHANNEL1 bool "TIM16 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM16_CHANNEL1 +if STM32_TIM16_CHANNEL1 -config STM32F0L0G0_TIM16_CH1MODE +config STM32_TIM16_CH1MODE int "TIM16 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM16_CH1OUT +config STM32_TIM16_CH1OUT bool "TIM16 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM16_CH1NOUT +config STM32_TIM16_CH1NOUT bool "TIM16 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM16_CH1OUT + depends on STM32_TIM16_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM16_CHANNEL1 +endif # STM32_TIM16_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM16_CHANNEL +config STM32_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 @@ -3064,69 +2937,69 @@ config STM32F0L0G0_TIM16_CHANNEL If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM16_CHMODE +config STM32_TIM16_CHMODE int "TIM16 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM16_PWM +endif # STM32_TIM16_PWM -config STM32F0L0G0_TIM17_PWM +config STM32_TIM17_PWM bool "TIM17 PWM" default n - depends on STM32F0L0G0_TIM17 - select STM32F0L0G0_PWM + depends on STM32_TIM17 + select STM32_PWM ---help--- Reserve timer 17 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM17 + to generate modulated outputs for such things as motor control. If STM32_TIM17 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM17_PWM +if STM32_TIM17_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM17_CHANNEL1 +config STM32_TIM17_CHANNEL1 bool "TIM17 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM17_CHANNEL1 +if STM32_TIM17_CHANNEL1 -config STM32F0L0G0_TIM17_CH1MODE +config STM32_TIM17_CH1MODE int "TIM17 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM17_CH1OUT +config STM32_TIM17_CH1OUT bool "TIM17 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM17_CH1NOUT +config STM32_TIM17_CH1NOUT bool "TIM17 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM17_CH1OUT + depends on STM32_TIM17_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM17_CHANNEL1 +endif # STM32_TIM17_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM17_CHANNEL +config STM32_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 @@ -3134,123 +3007,71 @@ config STM32F0L0G0_TIM17_CHANNEL If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM17_CHMODE +config STM32_TIM17_CHMODE int "TIM17 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM17_PWM +endif # STM32_TIM17_PWM -config STM32F0L0G0_PWM_MULTICHAN +config STM32_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n - depends on STM32F0L0G0_PWM + depends on STM32_PWM ---help--- Specifies that the PWM driver supports multiple output channels per timer. -config STM32F0L0G0_TIM1_ADC +config STM32_TIM1_ADC bool "TIM1 ADC" default n - depends on STM32F0L0G0_TIM1 && STM32F0L0G0_ADC + depends on STM32_TIM1 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM1 ADC channel" - default STM32F0L0G0_TIM1_ADC1 - depends on STM32F0L0G0_TIM1_ADC - -config STM32F0L0G0_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -endchoice -config STM32F0L0G0_TIM2_ADC +config STM32_TIM2_ADC bool "TIM2 ADC" default n - depends on STM32F0L0G0_TIM2 && STM32F0L0G0_ADC + depends on STM32_TIM2 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM2 ADC channel" - default STM32F0L0G0_TIM2_ADC1 - depends on STM32F0L0G0_TIM2_ADC - -config STM32F0L0G0_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -endchoice -config STM32F0L0G0_TIM3_ADC +config STM32_TIM3_ADC bool "TIM3 ADC" default n - depends on STM32F0L0G0_TIM3 && STM32F0L0G0_ADC + depends on STM32_TIM3 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM3 ADC channel" - default STM32F0L0G0_TIM3_ADC1 - depends on STM32F0L0G0_TIM3_ADC - -config STM32F0L0G0_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -endchoice -config STM32F0L0G0_TIM15_ADC +config STM32_TIM15_ADC bool "TIM15 ADC" default n - depends on STM32F0L0G0_TIM15 && STM32F0L0G0_ADC + depends on STM32_TIM15 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM15 ADC channel" - default STM32F0L0G0_TIM15_ADC1 - depends on STM32F0L0G0_TIM15_ADC - -config STM32F0L0G0_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 -endchoice - -config STM32F0L0G0_HAVE_ADC1_TIMER +config STM32_HAVE_ADC1_TIMER bool -config STM32F0L0G0_ADC1_SAMPLE_FREQUENCY +config STM32_ADC1_SAMPLE_FREQUENCY int "ADC1 Sampling Frequency" default 100 - depends on STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_HAVE_ADC1_TIMER ---help--- ADC1 sampling frequency. Default: 100Hz -config STM32F0L0G0_ADC1_TIMTRIG +config STM32_ADC1_TIMTRIG int "ADC1 Timer Trigger" default 0 range 0 5 - depends on STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_HAVE_ADC1_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. This option must match with the MCU's supported EXTSEL. @@ -3258,25 +3079,10 @@ config STM32F0L0G0_ADC1_TIMTRIG endmenu # Timer Configuration menu "FDCAN driver configuration" - depends on STM32F0L0G0_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32F0L0G0_FDCAN_CHARDRIVER - -config STM32F0L0G0_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F0L0G0_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD + depends on STM32_FDCAN -endchoice # FDCAN character driver or SocketCAN support -config STM32F0L0G0_FDCAN_REGDEBUG +config STM32_FDCAN_REGDEBUG bool "CAN Register level debug" depends on DEBUG_CAN_INFO default n @@ -3284,53 +3090,16 @@ config STM32F0L0G0_FDCAN_REGDEBUG Output detailed register-level CAN device debug information. Requires also CONFIG_DEBUG_CAN_INFO. -config STM32F0L0G0_FDCAN_QUEUE_MODE +config STM32_FDCAN_QUEUE_MODE bool "FDCAN QUEUE mode (vs FIFO mode)" default n menu "FDCAN1 device driver options" - depends on STM32F0L0G0_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32F0L0G0_FDCAN1_ISO11898_1 - -config STM32F0L0G0_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32F0L0G0_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + depends on STM32_FDCAN1 -endchoice # FDCAN1 frame format -choice - prompt "FDCAN1 mode" - default STM32F0L0G0_FDCAN1_CLASSIC - -config STM32F0L0G0_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32F0L0G0_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32F0L0G0_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode -config STM32F0L0G0_FDCAN1_LOOPBACK +config STM32_FDCAN1_LOOPBACK bool "Enable FDCAN1 loopback mode" default n ---help--- @@ -3338,28 +3107,28 @@ config STM32F0L0G0_FDCAN1_LOOPBACK comment "Nominal Bit Timing" -config STM32F0L0G0_FDCAN1_BITRATE +config STM32_FDCAN1_BITRATE int "FDCAN bitrate" default 500000 range 0 1000000 ---help--- - FDCAN1 bitrate in bits per second. Required if STM32F0L0G0_FDCAN1 is defined. + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. -config STM32F0L0G0_FDCAN1_NTSEG1 +config STM32_FDCAN1_NTSEG1 int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" default 6 range 1 256 ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_NTSEG2 +config STM32_FDCAN1_NTSEG2 int "FDCAN1 NTSEG2 (PhaseSeg2)" default 7 range 1 128 ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_NSJW +config STM32_FDCAN1_NSJW int "FDCAN1 synchronization jump width" default 1 range 1 128 @@ -3367,36 +3136,36 @@ config STM32F0L0G0_FDCAN1_NSJW The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). comment "Data Bit Timing" - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS -config STM32F0L0G0_FDCAN1_DBITRATE +config STM32_FDCAN1_DBITRATE int "FDCAN1 data bitrate" default 2000000 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). -config STM32F0L0G0_FDCAN1_DTSEG1 +config STM32_FDCAN1_DTSEG1 int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" default 4 range 1 31 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_DTSEG2 +config STM32_FDCAN1_DTSEG2 int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" default 4 range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_DSJW +config STM32_FDCAN1_DSJW int "FDCAN1 fast synchronization jump width" default 2 range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The duration of a synchronization jump is Tcan_clk x DSJW. @@ -3405,34 +3174,18 @@ endmenu # FDCAN1 device driver options endmenu # "FDCAN driver configuration" menu "U[S]ART Configuration" - depends on STM32F0L0G0_USART + depends on STM32_USART comment "U[S]ART Device Configuration" -choice - prompt "USART1 Driver Configuration" - default STM32F0L0G0_USART1_SERIALDRIVER - depends on STM32F0L0G0_USART1 - -config STM32F0L0G0_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART1 Driver Configuration -if STM32F0L0G0_USART1_SERIALDRIVER +if STM32_USART1_SERIALDRIVER config USART1_RXFIFO_THRES int "USART1 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 + depends on STM32_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -3463,32 +3216,16 @@ config USART1_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32F0L0G0_USART2_SERIALDRIVER - depends on STM32F0L0G0_USART2 - -config STM32F0L0G0_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER +endif # STM32_USART1_SERIALDRIVER -endchoice # USART2 Driver Configuration -if STM32F0L0G0_USART2_SERIALDRIVER +if STM32_USART2_SERIALDRIVER config USART2_RXFIFO_THRES int "USART2 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 + depends on STM32_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -3519,26 +3256,10 @@ config USART2_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32F0L0G0_USART3_SERIALDRIVER - depends on STM32F0L0G0_USART3 - -config STM32F0L0G0_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER +endif # STM32_USART2_SERIALDRIVER -endchoice # USART3 Driver Configuration -if STM32F0L0G0_USART3_SERIALDRIVER +if STM32_USART3_SERIALDRIVER config USART3_RS485 bool "RS-485 on USART3" @@ -3556,26 +3277,26 @@ config USART3_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART3_SERIALDRIVER +endif # STM32_USART3_SERIALDRIVER choice prompt "USART4 Driver Configuration" - default STM32F0L0G0_USART4_SERIALDRIVER - depends on STM32F0L0G0_USART4 + default STM32_USART4_SERIALDRIVER + depends on STM32_USART4 -config STM32F0L0G0_USART4_SERIALDRIVER +config STM32_USART4_SERIALDRIVER bool "Standard serial driver" select USART4_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART4_1WIREDRIVER +config STM32_USART4_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART4 Driver Configuration -if STM32F0L0G0_USART4_SERIALDRIVER +if STM32_USART4_SERIALDRIVER config USART4_RS485 bool "RS-485 on USART4" @@ -3593,26 +3314,26 @@ config USART4_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART4_SERIALDRIVER +endif # STM32_USART4_SERIALDRIVER choice prompt "USART5 Driver Configuration" - default STM32F0L0G0_USART5_SERIALDRIVER - depends on STM32F0L0G0_USART5 + default STM32_USART5_SERIALDRIVER + depends on STM32_USART5 -config STM32F0L0G0_USART5_SERIALDRIVER +config STM32_USART5_SERIALDRIVER bool "Standard serial driver" select USART5_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART5_1WIREDRIVER +config STM32_USART5_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART5 Driver Configuration -if STM32F0L0G0_USART5_SERIALDRIVER +if STM32_USART5_SERIALDRIVER config USART5_RS485 bool "RS-485 on USART5" @@ -3630,26 +3351,10 @@ config USART5_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32F0L0G0_USART6_SERIALDRIVER - depends on STM32F0L0G0_USART6 - -config STM32F0L0G0_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER +endif # STM32_USART5_SERIALDRIVER -endchoice # USART6 Driver Configuration -if STM32F0L0G0_USART6_SERIALDRIVER +if STM32_USART6_SERIALDRIVER config USART6_RS485 bool "RS-485 on USART6" @@ -3667,26 +3372,26 @@ config USART6_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART6_SERIALDRIVER +endif # STM32_USART6_SERIALDRIVER choice prompt "USART7 Driver Configuration" - default STM32F0L0G0_USART7_SERIALDRIVER - depends on STM32F0L0G0_USART7 + default STM32_USART7_SERIALDRIVER + depends on STM32_USART7 -config STM32F0L0G0_USART7_SERIALDRIVER +config STM32_USART7_SERIALDRIVER bool "Standard serial driver" select USART7_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART7_1WIREDRIVER +config STM32_USART7_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART7 Driver Configuration -if STM32F0L0G0_USART7_SERIALDRIVER +if STM32_USART7_SERIALDRIVER config USART7_RS485 bool "RS-485 on USART7" @@ -3704,26 +3409,26 @@ config USART7_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART7_SERIALDRIVER +endif # STM32_USART7_SERIALDRIVER choice prompt "USART8 Driver Configuration" - default STM32F0L0G0_USART8_SERIALDRIVER - depends on STM32F0L0G0_USART8 + default STM32_USART8_SERIALDRIVER + depends on STM32_USART8 -config STM32F0L0G0_USART8_SERIALDRIVER +config STM32_USART8_SERIALDRIVER bool "Standard serial driver" select USART8_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART8_1WIREDRIVER +config STM32_USART8_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART8 Driver Configuration -if STM32F0L0G0_USART8_SERIALDRIVER +if STM32_USART8_SERIALDRIVER config USART8_RS485 bool "RS-485 on USART8" @@ -3741,12 +3446,12 @@ config USART8_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART8_SERIALDRIVER +endif # STM32_USART8_SERIALDRIVER menu "Serial Driver Configuration" - depends on STM32F0L0G0_SERIALDRIVER + depends on STM32_SERIALDRIVER -config STM32F0L0G0_SERIAL_DISABLE_REORDERING +config STM32_SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." default n ---help--- @@ -3759,10 +3464,10 @@ config STM32F0L0G0_SERIAL_DISABLE_REORDERING want the side effect of having all serial port names change when just the console is moved from serial to USB. -config STM32F0L0G0_USART_SINGLEWIRE +config STM32_USART_SINGLEWIRE bool "Single Wire Support" default n - depends on STM32F0L0G0_USART + depends on STM32_USART ---help--- Enable single wire UART support. The option enables support for the TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. @@ -3771,7 +3476,7 @@ endmenu # Serial Driver Configuration if PM -config STM32F0L0G0_PM_SERIAL_ACTIVITY +config STM32_PM_SERIAL_ACTIVITY int "PM serial activity" default 10 ---help--- @@ -3783,20 +3488,20 @@ endif # PM endmenu # U[S]ART Configuration menu "ADC Configuration" - depends on STM32F0L0G0_ADC + depends on STM32_ADC -config STM32F0L0G0_ADC1_RESOLUTION +config STM32_ADC1_RESOLUTION int "ADC1 resolution" - depends on STM32F0L0G0_ADC1 + depends on STM32_ADC1 default 0 range 0 3 ---help--- ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32F0L0G0_ADC_MAX_SAMPLES +config STM32_ADC_MAX_SAMPLES int "The maximum number of channels that can be sampled" - default 16 if STM32F0L0G0_ADC1_DMA - default 1 if !STM32F0L0G0_ADC1_DMA + default 16 if STM32_ADC1_DMA + default 1 if !STM32_ADC1_DMA ---help--- The maximum number of samples which can be handled without overrun depends on various factors. This is the user's @@ -3805,66 +3510,66 @@ config STM32F0L0G0_ADC_MAX_SAMPLES for all supported devices, the user can change the default values in the board initialization logic and avoid ADC overrun. -config STM32F0L0G0_ADC_NO_STARTUP_CONV +config STM32_ADC_NO_STARTUP_CONV bool "Do not start conversion when opening ADC device" default n ---help--- Do not start conversion when opening ADC device. -config STM32F0L0G0_ADC_NOIRQ +config STM32_ADC_NOIRQ bool "Do not use default ADC interrupts" default n ---help--- Do not use default ADC interrupts handlers. -config STM32F0L0G0_ADC_LL_OPS +config STM32_ADC_LL_OPS bool "ADC low-level operations" default n ---help--- Enable low-level ADC ops. -config STM32F0L0G0_ADC_CHANGE_SAMPLETIME +config STM32_ADC_CHANGE_SAMPLETIME bool "ADC sample time configuration" default n - depends on STM32F0L0G0_ADC_LL_OPS + depends on STM32_ADC_LL_OPS ---help--- Enable ADC sample time configuration (SMPRx registers). -config STM32F0L0G0_ADC1_DMA +config STM32_ADC1_DMA bool "ADC1 DMA" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC1_DMA + depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32F0L0G0_ADC1_DMA_CFG +config STM32_ADC1_DMA_CFG int "ADC1 DMA configuration" - depends on STM32F0L0G0_ADC1_DMA && !STM32F0L0G0_HAVE_IP_ADC_V1_BASIC + depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode -config STM32F0L0G0_ADC_OVERSAMPLE +config STM32_ADC_OVERSAMPLE bool "Enable ADC hardware oversampling support" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC_OVERSAMPLE + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE default n ---help--- Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). Only STM32G0 and STM32L0 series include this hardware block. -if STM32F0L0G0_ADC_OVERSAMPLE +if STM32_ADC_OVERSAMPLE -config STM32F0L0G0_ADC_TOVS +config STM32_ADC_TOVS bool "Enable triggered oversampling (CFGR2.TOVS)" default n ---help--- If set, oversampling will only occur when a trigger event occurs. If not set, oversampling occurs continuously (TOVS=0). -config STM32F0L0G0_ADC_OVSR +config STM32_ADC_OVSR int "Oversampling ratio (CFGR2.OVSR)" default 0 range 0 7 @@ -3876,7 +3581,7 @@ config STM32F0L0G0_ADC_OVSR ... 7 -> 256× -config STM32F0L0G0_ADC_OVSS +config STM32_ADC_OVSS int "Oversampling right-shift bits (CFGR2.OVSS)" default 0 range 0 8 @@ -3884,11 +3589,11 @@ config STM32F0L0G0_ADC_OVSS Sets how many bits the accumulated result is right-shifted. Max of 8-bits. -endif # STM32F0L0G0_ADC_OVERSAMPLE +endif # STM32_ADC_OVERSAMPLE -config STM32F0L0G0_ADC1_DMA_BATCH +config STM32_ADC1_DMA_BATCH int "ADC1 DMA number of conversions" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_ADC1_DMA + depends on STM32_ADC1 && STM32_ADC1_DMA default 1 ---help--- This option allows you to select the number of regular group conversions @@ -3896,17 +3601,17 @@ config STM32F0L0G0_ADC1_DMA_BATCH By default, this value is 1, which means that data is transferred after each group conversion. -config STM32F0L0G0_ADC1_EXTSEL +config STM32_ADC1_EXTSEL bool "ADC1 external trigger for regular group" - depends on STM32F0L0G0_ADC1 && !STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER default n ---help--- Enable EXTSEL for ADC1. -config STM32F0L0G0_ADC1_CONTINUOUS +config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" default n - depends on STM32F0L0G0_ADC1 + depends on STM32_ADC1 ---help--- If enabled, the ADC will operate in continuous conversion mode. Otherwise, it will perform single conversions. @@ -3916,9 +3621,9 @@ config STM32F0L0G0_ADC1_CONTINUOUS endmenu # ADC Configuration menu "SPI Configuration" - depends on STM32F0L0G0_SPI + depends on STM32_SPI -config STM32F0L0G0_SPI_INTERRUPTS +config STM32_SPI_INTERRUPTS bool "Interrupt driver SPI" default n ---help--- @@ -3926,87 +3631,87 @@ config STM32F0L0G0_SPI_INTERRUPTS poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -config STM32F0L0G0_SPI1_DMA +config STM32_SPI1_DMA bool "SPI1 DMA" default n - depends on STM32F0L0G0_SPI1 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI1 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI2_DMA +config STM32_SPI2_DMA bool "SPI2 DMA" default n - depends on STM32F0L0G0_SPI2 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI2 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI3_DMA +config STM32_SPI3_DMA bool "SPI3 DMA" default n - depends on STM32F0L0G0_SPI3 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI3 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI1_COMMTYPE +config STM32_SPI1_COMMTYPE int "SPI1 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI1 + depends on STM32_SPI1 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) -config STM32F0L0G0_SPI2_COMMTYPE +config STM32_SPI2_COMMTYPE int "SPI2 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI2 + depends on STM32_SPI2 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) -config STM32F0L0G0_SPI3_COMMTYPE +config STM32_SPI3_COMMTYPE int "SPI3 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI3 + depends on STM32_SPI3 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) endmenu # SPI Configuration menu "I2C Configuration" - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2C_DYNTIMEO +config STM32_I2C_DYNTIMEO bool "Use dynamic timeouts" default n - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE +config STM32_I2C_DYNTIMEO_USECPERBYTE int "Timeout Microseconds per Byte" default 500 - depends on STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP +config STM32_I2C_DYNTIMEO_STARTSTOP int "Timeout for Start/Stop (Milliseconds)" default 1000 - depends on STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2CTIMEOSEC +config STM32_I2CTIMEOSEC int "Timeout seconds" default 0 - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2CTIMEOMS +config STM32_I2CTIMEOMS int "Timeout Milliseconds" default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C && !STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2CTIMEOTICKS +config STM32_I2CTIMEOTICKS int "Timeout for Done and Stop (ticks)" default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C && !STM32_I2C_DYNTIMEO endmenu #I2C Configuration diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index e4ab1438876cc..8ff7580bde293 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -25,15 +25,15 @@ include armv6-m/Make.defs CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c -ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),) +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F0L0G0_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F0L0G0_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -49,69 +49,69 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32F0L0G0_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif -ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y) +ifeq ($(CONFIG_STM32_GPIOIRQ),y) CHIP_CSRCS += stm32_gpioint.c endif -ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32F0L0G0_USB),y) +ifeq ($(CONFIG_STM32_USB),y) CHIP_CSRCS += stm32_usbdev.c endif -ifeq ($(CONFIG_STM32F0L0G0_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F0L0G0_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32F0L0G0_TIM1_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif endif -ifeq ($(CONFIG_STM32F0L0G0_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F0L0G0_AES),y) +ifeq ($(CONFIG_STM32_AES),y) CHIP_CSRCS += stm32_aes.c endif -ifeq ($(CONFIG_STM32F0L0G0_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F0L0G0_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F0L0G0_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32F0L0G0_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CHIP_CSRCS += stm32_fdcan.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) CHIP_CSRCS += stm32_fdcan_sock.c endif endif diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index b855b530df532..f074647fe54dc 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -49,7 +49,7 @@ /* Support for ADC clock prescaler */ -#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0) # define HAVE_ADC_PRE #else # undef HAVE_ADC_PRE @@ -57,7 +57,7 @@ /* Support for LCD voltage */ -#ifdef CONFIG_STM32F0L0G0_HAVE_LCD +#ifdef CONFIG_STM32_HAVE_LCD # define HAVE_ADC_VLCD #else # undef HAVE_ADC_VLCD @@ -65,7 +65,7 @@ /* Support for Low frequency mode */ -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE +#ifdef CONFIG_STM32_ENERGYLITE # define HAVE_ADC_LFM #else # undef HAVE_ADC_LFM diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h index 31402fafbc02e..ccab2c6f14ae9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h @@ -151,9 +151,9 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32G0) # include "hardware/stm32g0_dmamux.h" -#elif defined(CONFIG_STM32F0L0G0_STM32C0) +#elif defined(CONFIG_STM32_STM32C0) # include "hardware/stm32c0_dmamux.h" #else # error "Unsupported STM32 M0 sub family" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h index dba663e2a366d..f6f07839c12f9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F03X) +#if defined(CONFIG_STM32_STM32F03X) # include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || \ - defined(CONFIG_STM32F0L0G0_STM32F07X) || \ - defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_STM32_STM32F05X) || \ + defined(CONFIG_STM32_STM32F07X) || \ + defined(CONFIG_STM32_STM32F09X) # include "hardware/stm32f05xf07xf09x_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_memorymap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h index 54cea66eed1ea..3f1e617b3cb7a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h @@ -30,13 +30,13 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F03X) +#if defined(CONFIG_STM32_STM32F03X) # include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) +#elif defined(CONFIG_STM32_STM32F05X) # include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F07X) +#elif defined(CONFIG_STM32_STM32F07X) # include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_STM32_STM32F09X) # include "hardware/stm32f09x_pinmap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_pinmap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h index 0a058ebf09468..fd63397093ee7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h @@ -32,11 +32,11 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32F0) || \ + defined(CONFIG_STM32_STM32G0) || \ + defined(CONFIG_STM32_STM32C0) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32L0) # define HAVE_IP_SPI_V1 #else # error Unsupported family diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index 91fea96af14cf..7149293388a29 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -41,7 +41,7 @@ #if defined(CONFIG_ARCH_CHIP_STM32L0) # define HAVE_TIM2_16BIT 1 # undef HAVE_TIM2_32BIT -#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32_STM32F09X) # define HAVE_TIM2_32BIT 1 # undef HAVE_TIM2_16BIT #else diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h index 576fcddc3e3fb..1a03d8f4dcdbd 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "hardware/stm32_uart_v2.h" #else # error "Unsupported STM32 M0 USART" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h index 9b1c6c78ce1e1..52f0df5aef25d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV +#ifdef CONFIG_STM32_HAVE_USBDEV /**************************************************************************** * Pre-processor Definitions @@ -251,5 +251,5 @@ #define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */ +#endif /* CONFIG_STM32_HAVE_USBDEV */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c index 8435f1f8b6f45..6366eb0ed321d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c @@ -54,13 +54,13 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F0L0G0_ADC +#ifdef CONFIG_STM32_ADC /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) -#if defined(CONFIG_STM32F0L0G0_STM32F0) +#if defined(CONFIG_STM32_STM32F0) # error Not tested #endif @@ -90,11 +90,11 @@ /* C0 and G0 support additional sample time selection 2 */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) # define ADC_HAVE_SMPR_SMP2 #endif -#if defined(ADC_HAVE_DMA) || (CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES == 1) +#if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) # if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) # define ADC_SMP1_DEFAULT ADC_SMPR_12p5 # define ADC_SMP2_DEFAULT ADC_SMPR_12p5 @@ -121,10 +121,10 @@ * (ST manual) */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32L0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32F0) || \ + defined(CONFIG_STM32_STM32L0) || \ + defined(CONFIG_STM32_STM32C0) || \ + defined(CONFIG_STM32_STM32G0) # define ADC_CHANNELS_NUMBER 19 #else # error "Not supported" @@ -155,7 +155,7 @@ #define ADC_HAVE_DMACFG 1 -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0) # ifndef ANIOC_SET_OVERSAMPLE # define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f) # endif @@ -181,10 +181,10 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) | defined(ADC_HAVE_DMA) const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -206,7 +206,7 @@ struct stm32_dev_s bool hasdma; /* True: This channel supports DMA */ uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. */ # ifdef ADC_HAVE_SMPR_SMP2 @@ -242,7 +242,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -280,10 +280,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc1_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -334,7 +334,7 @@ static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static void adc_llops_intack(struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(struct stm32_adc_dev_s *dev, @@ -349,7 +349,7 @@ static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len); # endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -375,7 +375,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -387,7 +387,7 @@ static const struct stm32_adc_ops_s g_adc_llops = # ifdef ADC_HAVE_DMA .regbuf_reg = adc_llops_regbufregister, # endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -397,47 +397,47 @@ static const struct stm32_adc_ops_s g_adc_llops = /* ADC1 state */ -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES * - CONFIG_STM32F0L0G0_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc1_interrupt, -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ #ifdef HAVE_ADC_CMN_DATA .cmn = &ADC1CMN_DATA, #endif .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, #endif .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, # ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, # endif .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F0L0G0_ADC1_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH #endif }; @@ -1178,7 +1178,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) switch (priv->intf) { -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) case 1: { adcbit = RCC_RSTR_ADC1RST; @@ -1322,7 +1322,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, static int adc_bind(struct adc_dev_s *dev, const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1399,7 +1399,7 @@ static void adc_mode_cfg(struct stm32_dev_s *priv) clrbits |= ADC_CFGR1_EXTEN_MASK; setbits |= ADC_CFGR1_EXTEN_NONE; -#ifdef CONFIG_STM32F0L0G0_ADC1_CONTINUOUS +#ifdef CONFIG_STM32_ADC1_CONTINUOUS setbits |= ADC_CFGR1_CONT; #endif @@ -1432,7 +1432,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) /* Initialize the same sample time for each ADC. * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME struct adc_sample_time_s time_samples = { # ifdef STM32_ADC1_SMPR_SMP1 .smp1 = STM32_ADC1_SMPR_SMP1, @@ -1682,7 +1682,7 @@ static void adc_configure(struct adc_dev_s *dev) adc_dumpregs(priv); } - #ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE + #ifdef CONFIG_STM32_ADC_OVERSAMPLE /**************************************************************************** * Name: adc_oversample @@ -1696,10 +1696,10 @@ static void adc_oversample(struct adc_dev_s *dev) ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK; uint32_t setbits = ADC_CFGR2_OVSE | - (CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | - (CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); + (CONFIG_STM32_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | + (CONFIG_STM32_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); -# ifdef CONFIG_STM32F0L0G0_ADC_TOVS +# ifdef CONFIG_STM32_ADC_TOVS setbits |= ADC_CFGR2_TOVS; # endif @@ -1779,15 +1779,15 @@ static void adc_reset(struct adc_dev_s *dev) static int adc_setup(struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ - defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ + defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1804,7 +1804,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_configure(dev); -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE +#ifdef CONFIG_STM32_ADC_OVERSAMPLE adc_oversample(dev); #endif @@ -1829,7 +1829,7 @@ static int adc_setup(struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1838,7 +1838,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1880,7 +1880,7 @@ static void adc_shutdown(struct adc_dev_s *dev) adc_enable(priv, false); -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2274,7 +2274,7 @@ static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) return ret; } -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE +#ifdef CONFIG_STM32_ADC_OVERSAMPLE /**************************************************************************** * Name: adc_ioc_set_oversample @@ -2494,7 +2494,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) break; } -#if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC_OVERSAMPLE) case ANIOC_SET_OVERSAMPLE: { ret = adc_ioc_set_oversample(dev, arg); @@ -2513,7 +2513,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2620,9 +2620,9 @@ static int adc1_interrupt(int irq, void *context, void *arg) return OK; } -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2736,7 +2736,7 @@ static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, } #endif /* ADC_HAVE_DMA */ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /**************************************************************************** * Name: adc_sampletime_write * @@ -2796,7 +2796,7 @@ static void adc_sampletime_set(struct stm32_adc_dev_s *dev, priv->smpsel = time_samples->smpsel; #endif } -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -2809,7 +2809,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -2841,7 +2841,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); @@ -2862,7 +2862,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(channels <= CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES); + DEBUGASSERT(channels <= CONFIG_STM32_ADC_MAX_SAMPLES); priv->cr_channels = channels; memcpy(priv->r_chanlist, chanlist, channels); @@ -2878,5 +2878,5 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32F0L0G0_ADC1 */ -#endif /* CONFIG_STM32F0L0G0_ADC */ +#endif /* CONFIG_STM32_ADC1 */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h index 89ac9b8da5d21..579d1ffc21c55 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h @@ -43,45 +43,45 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_ADC must also be defined to indicate that + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_ADC must also be defined to indicate that * timer "n" is intended to be used for that purpose. Timers 1-6 and 8 may * be used. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_ADC -# undef CONFIG_STM32F0L0G0_TIM1_ADC1 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_ADC -# undef CONFIG_STM32F0L0G0_TIM2_ADC1 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_ADC -# undef CONFIG_STM32F0L0G0_TIM3_ADC1 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_ADC -# undef CONFIG_STM32F0L0G0_TIM15_ADC1 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 #endif /* Up to 1 ADC interfaces are supported */ #if STM32_NADC < 1 -# undef CONFIG_STM32F0L0G0_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F0L0G0_ADC1_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F0L0G0_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA @@ -91,19 +91,19 @@ * information about the timer. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN @@ -112,11 +112,11 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F0L0G0_ADC1_TIMTRIG -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -129,7 +129,7 @@ /* EXTSEL */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) +#if defined(CONFIG_STM32_STM32F0) # define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -139,7 +139,7 @@ * TRG6 reserved * TRG7 reserved */ -#elif defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32L0) /* TRG0 reserved */ # define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -148,7 +148,7 @@ # define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5 /* TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0) +#elif defined(CONFIG_STM32_STM32G0) # define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -156,7 +156,7 @@ # define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32C0) +#elif defined(CONFIG_STM32_STM32C0) # define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -171,49 +171,49 @@ /* EXTSEL configuration *****************************************************/ /* NOTE: - * this configuration if used only if CONFIG_STM32F0L0G0_TIMx_ADCy is + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is * selected. * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F0L0G0_ADCx_EXTSEL option. + * CONFIG_STM32_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM21_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM21_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21CC2 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif @@ -222,7 +222,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F0L0G0_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -322,9 +322,9 @@ enum stm32_adc_resoluton_e ADC_RESOLUTION_6BIT = 3 /* 6 bit */ }; -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME struct adc_sample_time_s { @@ -332,7 +332,7 @@ struct adc_sample_time_s uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */ uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */ }; -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -380,7 +380,7 @@ struct stm32_adc_ops_s void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -394,7 +394,7 @@ struct stm32_adc_ops_s void (*dump_regs)(struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -433,7 +433,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, * Name: stm32_adc_llops_get ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *stm32_adc_llops_get(struct adc_dev_s *dev); #endif @@ -444,5 +444,5 @@ const struct stm32_adc_ops_s #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/stm32f0l0g0/stm32_dma.c index 4d60de3763b6d..3e3b9af30ead7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma.c @@ -28,7 +28,7 @@ #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_DMAMUX) +#if defined(CONFIG_STM32_HAVE_DMAMUX) # include "stm32_dma_v1mux.c" #else # include "stm32_dma_v1.c" diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h index 0d6d729a0cc5c..ce5cb1a18af6e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ b/arch/arm/src/stm32f0l0g0/stm32_dma.h @@ -32,7 +32,7 @@ #include "hardware/stm32_dma_v1.h" -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX +#ifdef CONFIG_STM32_HAVE_DMAMUX # include "hardware/stm32_dmamux.h" #endif @@ -238,7 +238,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index 28ffac90950cc..3117fad02ec9a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -51,7 +51,7 @@ * the DMA requests for each channel. */ -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX +#ifdef CONFIG_STM32_HAVE_DMAMUX # error DMAMUX not supported here. Look at stm32_dma_v1mux.c #endif @@ -628,7 +628,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c index a179bc8b9de49..e622ab417d501 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c @@ -50,20 +50,20 @@ #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 # if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) # define DMA1_NCHAN 5 # define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) +# elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) # define DMA1_NCHAN 7 # define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +# elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define DMA1_NCHAN 7 # define DMA2_NCHAN 5 # else @@ -86,16 +86,16 @@ /* DMAMUX channels */ #if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) # define DMAMUX_NCHANNELS 5 -#elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) +#elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) # define DMAMUX_NCHANNELS 7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +#elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define DMAMUX_NCHANNELS 12 #else # error "Unknown chip for DMAMUX channel count" @@ -191,7 +191,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_dma12_disable(DMA_CHANNEL dmachan); static int stm32_dma12_interrupt(int irq, void *context, void *arg); static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -237,7 +237,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -257,7 +257,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -293,7 +293,7 @@ static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -305,7 +305,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -322,7 +322,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -396,7 +396,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = # endif #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -628,7 +628,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_dma12_disable @@ -680,14 +680,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { channel = irq - STM32_IRQ_DMA2CH1; @@ -753,7 +753,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -942,7 +942,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32F0L0G0_DMA1 || CONFIG_STM32F0L0G0_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32_dmamux_sample @@ -1334,7 +1334,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c index 433b0b6e39954..5e8beb51a12a6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V2) # define STM32_EXTI_FTSR STM32_EXTI_FTSR1 # define STM32_EXTI_RTSR STM32_EXTI_RTSR1 # define STM32_EXTI_IMR STM32_EXTI_IMR1 @@ -77,7 +77,7 @@ static struct gpio_callback_s g_gpio_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { @@ -121,7 +121,7 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg, return ret; } -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c index 8f35cb89f26f6..02d2c0f773de3 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c @@ -72,7 +72,7 @@ # define FDCAN_MSGRAM_WORDS (212) # define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# ifdef CONFIG_STM32F0L0G0_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -93,16 +93,16 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -117,19 +117,19 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 # define FDCAN1_DBRP 1 # define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ # if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX # error Invalid FDCAN1 DTSEG1 @@ -156,12 +156,12 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* Loopback mode */ #undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) # define STM32_FDCAN_LOOPBACK 1 #endif @@ -243,7 +243,7 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif /**************************************************************************** @@ -348,7 +348,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -364,7 +364,7 @@ struct stm32_fdcan_s static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -441,7 +441,7 @@ static const struct can_ops_s g_fdcanops = .co_txempty = fdcan_txempty, }; -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -451,7 +451,7 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -463,14 +463,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_0, .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -486,7 +486,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -508,7 +508,7 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; static struct can_dev_s g_fdcan1dev; -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /**************************************************************************** * Private Functions @@ -528,7 +528,7 @@ static struct can_dev_s g_fdcan1dev; * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -608,7 +608,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -648,7 +648,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -694,7 +694,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -737,7 +737,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -786,7 +786,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -3096,7 +3096,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; @@ -3185,7 +3185,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h index b96772738a2c1..83893b284efe0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h @@ -65,7 +65,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /**************************************************************************** * Name: stm32_fdcaninitialize @@ -84,7 +84,7 @@ extern "C" struct can_dev_s *stm32_fdcaninitialize(int port); #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /**************************************************************************** * Name: stm32_fdcansockinitialize diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c index 46464bec39533..f17be5729df59 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c @@ -93,7 +93,7 @@ # define FDCAN_MSGRAM_WORDS (212) # define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# ifdef CONFIG_STM32F0L0G0_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -114,16 +114,16 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -138,19 +138,19 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 # define FDCAN1_DBRP 1 # define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ # if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX # error Invalid FDCAN1 DTSEG1 @@ -177,12 +177,12 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* Loopback mode */ #undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) # define STM32_FDCAN_LOOPBACK 1 #endif @@ -259,7 +259,7 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif /**************************************************************************** @@ -362,7 +362,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -399,7 +399,7 @@ struct stm32_fdcan_s static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -489,7 +489,7 @@ static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -499,7 +499,7 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -511,14 +511,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_0, .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -534,7 +534,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -555,7 +555,7 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /**************************************************************************** * Private Functions @@ -575,7 +575,7 @@ static struct stm32_fdcan_s g_fdcan1priv; * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -655,7 +655,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -695,7 +695,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -741,7 +741,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -784,7 +784,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -833,7 +833,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -2567,7 +2567,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; @@ -2916,7 +2916,7 @@ int stm32_fdcansockinitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ @@ -2984,7 +2984,7 @@ int stm32_fdcansockinitialize(int port) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F0L0G0_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_fdcansockinitialize(FDCAN1); #endif } diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/stm32f0l0g0/stm32_flash.c index 8e2d4b7dd592f..010d5059c0c76 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ b/arch/arm/src/stm32f0l0g0/stm32_flash.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) # include "stm32g0c0_flash.c" #else # error "Flash driver unsupported on selected chip." diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c index 19d50cf7637cc..7917ca44a79c0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c @@ -40,9 +40,9 @@ #include "chip.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # include "hardware/stm32_syscfg.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) # include "hardware/stm32_exti.h" #endif @@ -317,7 +317,7 @@ int stm32_configgpio(uint32_t cfgset) uint32_t regaddr; int shift; -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) /* Set the bits in the SYSCFG EXTICR register */ regaddr = STM32_SYSCFG_EXTICR(pin); @@ -327,7 +327,7 @@ int stm32_configgpio(uint32_t cfgset) regval |= (((uint32_t)port) << shift); putreg32(regval, regaddr); -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) /* Set the bits in the EXTI EXTICR register */ regaddr = STM32_EXTI_EXTICR(pin); diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/stm32_gpio.h index d4a90cc57128c..0d6e7c881acf3 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.h @@ -188,7 +188,7 @@ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -#if defined (CONFIG_STM32F0L0G0_STM32F03X) +#if defined (CONFIG_STM32_STM32F03X) # define GPIO_PORTF (4 << GPIO_PORT_SHIFT) /* GPIOF */ #else # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h index 37a6981ff5d5b..216fce2501e86 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c index 1991004a026a0..b2f689f97981a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -153,24 +153,24 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32F0L0G0_I2C1 - * CONFIG_STM32F0L0G0_I2C2 - * CONFIG_STM32F0L0G0_I2C3 - * CONFIG_STM32F0L0G0_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -243,8 +243,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \ - defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -260,25 +260,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS -# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -448,9 +448,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -490,7 +490,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -525,7 +525,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -595,7 +595,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -724,7 +724,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -741,7 +741,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -798,12 +798,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F0L0G0_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -841,10 +841,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2708,22 +2708,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2810,5 +2810,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \ - * CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h index 0a52455ba3374..9d1d09b17a94b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/stm32f0l0g0/stm32_idle.c index e6f004d60995b..1b971a961caf6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ b/arch/arm/src/stm32f0l0g0/stm32_idle.c @@ -83,7 +83,7 @@ void up_idle(void) * disabled in order to save power." */ -#ifdef CONFIG_STM32F0L0G0_GPDMA +#ifdef CONFIG_STM32_GPDMA if (g_dma_inprogress == 0) #endif { diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c index a6e21b8ca8e4a..c46388c264139 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -217,7 +217,7 @@ void up_irqinitialize(void) * configured pin interrupts. */ -#ifdef CONFIG_STM32F0L0G0_GPIOIRQ +#ifdef CONFIG_STM32_GPIOIRQ stm32_gpioirqinitialize(); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c index b15eb7eb39f4e..91bd0cfbeae41 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c @@ -27,9 +27,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "stm32_lowputc_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c index 81bcd23faf2e9..2f3e87315b390 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c @@ -268,7 +268,7 @@ void stm32_lowsetup(void) /* Setup clocking and GPIO pins for all configured USARTs */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* Enable USART APB2 clock */ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); @@ -284,7 +284,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); @@ -300,7 +300,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); @@ -316,7 +316,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); @@ -332,7 +332,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c index a60c576c4a59a..e644f31003f22 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c @@ -45,7 +45,7 @@ /* This module only supports pulse count on advanced timers. */ -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT /**************************************************************************** * Pre-processor Definitions @@ -68,13 +68,13 @@ # define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN #endif -#if CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 1 +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT #else # error Unsupported TIM1 pulse count channel @@ -180,14 +180,14 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = stm32pulsecount_ioctl, }; -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecounttimer_s g_pulsecount1dev = { .ops = &g_pulsecountops, .timid = 1, .channel = { - .channel = CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL, + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, .pincfg = PULSECOUNT_TIM1_CHCFG, }, .timtype = TIMTYPE_TIM1, @@ -958,7 +958,7 @@ static void stm32pulsecount_setapbclock( switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; @@ -1166,7 +1166,7 @@ static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; @@ -1255,7 +1255,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: lower = &g_pulsecount1dev; @@ -1274,4 +1274,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) return (struct pulsecount_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F0L0G0_TIMx_PULSECOUNT */ +#endif /* CONFIG_STM32_TIMx_PULSECOUNT */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index df066d05163a3..0710973de1b91 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -64,10 +64,10 @@ * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) /**************************************************************************** * Pre-processor Definitions @@ -98,15 +98,15 @@ /* Advanced timer */ -#if defined (CONFIG_STM32F0L0G0_TIM1_PWM) +#if defined (CONFIG_STM32_TIM1_PWM) # define HAVE_IP_TIMERS_V2 1 #endif -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM8_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || \ + defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -114,8 +114,8 @@ /* CCMR2 */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) # define HAVE_CCMR2 #else # undef HAVE_CCMR2 @@ -237,159 +237,159 @@ static const struct pwm_ops_s g_pwmops = .ioctl = stm32pwm_ioctl, }; -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, .timid = 1, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM1_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, .npincfg = PWM_TIM1_CH1NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM1_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH2MODE, + .mode = CONFIG_STM32_TIM1_CH2MODE, .npincfg = PWM_TIM1_CH2NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM1_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH3MODE, + .mode = CONFIG_STM32_TIM1_CH3MODE, .npincfg = PWM_TIM1_CH3NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM1_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH4MODE, + .mode = CONFIG_STM32_TIM1_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F0L0G0_TIM1_MODE, + .mode = CONFIG_STM32_TIM1_MODE, .base = STM32_TIM1_BASE, .pclk = STM32_APB2_TIM1_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, .timid = 2, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM2_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH1MODE, + .mode = CONFIG_STM32_TIM2_CH1MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM2_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH2MODE, + .mode = CONFIG_STM32_TIM2_CH2MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM2_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH3MODE, + .mode = CONFIG_STM32_TIM2_CH3MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM2_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH4MODE, + .mode = CONFIG_STM32_TIM2_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F0L0G0_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .base = STM32_TIM2_BASE, .pclk = STM32_APB1_TIM2_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, .timid = 3, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM3_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH1MODE, + .mode = CONFIG_STM32_TIM3_CH1MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM3_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH2MODE, + .mode = CONFIG_STM32_TIM3_CH2MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM3_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH3MODE, + .mode = CONFIG_STM32_TIM3_CH3MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM3_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH4MODE, + .mode = CONFIG_STM32_TIM3_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F0L0G0_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .base = STM32_TIM3_BASE, .pclk = STM32_APB1_TIM3_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, .timid = 14, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM14_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM14_CH1MODE, + .mode = CONFIG_STM32_TIM14_CH1MODE, .npincfg = PWM_TIM14_CH1NCFG, }, #endif @@ -401,26 +401,26 @@ static struct stm32_pwmtimer_s g_pwm14dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, .timid = 15, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM15_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, .npincfg = PWM_TIM15_CH1NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM15_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH2MODE, + .mode = CONFIG_STM32_TIM15_CH2MODE, .npincfg = 0, }, #endif @@ -432,18 +432,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, .timid = 16, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM16_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, .npincfg = PWM_TIM16_CH1NCFG, }, #endif @@ -455,18 +455,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, .timid = 17, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM17_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, .npincfg = PWM_TIM17_CH1NCFG, }, #endif @@ -689,7 +689,7 @@ static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, stm32pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), stm32pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), stm32pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -939,9 +939,9 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, * and TIMTYPE_BASIC */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16 && priv->timtype != TIMTYPE_COUNTUP16_N) @@ -1001,7 +1001,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, /* Set the advanced timer's repetition counter */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { /* If a non-zero repetition count has been selected, then set the @@ -1394,43 +1394,43 @@ static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; @@ -1683,70 +1683,70 @@ static int stm32pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM14RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM15RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; @@ -1834,7 +1834,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: lower = &g_pwm1dev; @@ -1843,31 +1843,31 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: lower = &g_pwm2dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: lower = &g_pwm3dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: lower = &g_pwm4dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: lower = &g_pwm5dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: lower = &g_pwm8dev; @@ -1876,25 +1876,25 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: lower = &g_pwm14dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: lower = &g_pwm15dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: lower = &g_pwm16dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: lower = &g_pwm17dev; break; @@ -1908,4 +1908,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/stm32f0l0g0/stm32_pwm.h index 88683b9b6626e..fc5beb4482cde 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.h @@ -64,56 +64,56 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM * must also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM14 -# undef CONFIG_STM32F0L0G0_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM16 -# undef CONFIG_STM32F0L0G0_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM17 -# undef CONFIG_STM32F0L0G0_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) * are not capable of generating output pulses */ -#undef CONFIG_STM32F0L0G0_TIM6_PWM -#undef CONFIG_STM32F0L0G0_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) -#ifdef CONFIG_STM32F0L0G0_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # else # define PWM_TIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 @@ -122,13 +122,13 @@ #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # else # define PWM_TIM1_CH2CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 @@ -137,13 +137,13 @@ #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # else # define PWM_TIM1_CH3CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 @@ -152,8 +152,8 @@ #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # define PWM_TIM1_CH4CFG 0 @@ -165,8 +165,8 @@ #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # else # define PWM_TIM2_CH1CFG 0 @@ -175,8 +175,8 @@ #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # else # define PWM_TIM2_CH2CFG 0 @@ -185,8 +185,8 @@ #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # else # define PWM_TIM2_CH3CFG 0 @@ -195,8 +195,8 @@ #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # define PWM_TIM2_CH4CFG 0 @@ -208,8 +208,8 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # else # define PWM_TIM3_CH1CFG 0 @@ -218,8 +218,8 @@ #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # else # define PWM_TIM3_CH2CFG 0 @@ -228,8 +228,8 @@ #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # else # define PWM_TIM3_CH3CFG 0 @@ -238,8 +238,8 @@ #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # define PWM_TIM3_CH4CFG 0 @@ -251,13 +251,13 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT # else # define PWM_TIM14_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1NOUT +# ifdef CONFIG_STM32_TIM14_CH1NOUT # define PWM_TIM14_CH1NCFG GPIO_TIM14_CH1NOUT # else # define PWM_TIM14_CH1NCFG 0 @@ -268,13 +268,13 @@ #endif #define PWM_TIM14_NCHANNELS PWM_TIM14_CHANNEL1 -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # else # define PWM_TIM15_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1NOUT +# ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT # else # define PWM_TIM15_CH1NCFG 0 @@ -283,8 +283,8 @@ #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else # define PWM_TIM15_CH2CFG 0 @@ -295,13 +295,13 @@ #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # else # define PWM_TIM16_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1NOUT +# ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT # else # define PWM_TIM16_CH1NCFG 0 @@ -312,13 +312,13 @@ #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # else # define PWM_TIM17_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1NOUT +# ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT # else # define PWM_TIM17_CH1NCFG 0 @@ -337,178 +337,170 @@ MAX(PWM_TIM16_NCHANNELS, \ PWM_TIM17_NCHANNELS)))))) -#else /* !CONFIG_STM32F0L0G0_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel - * {1,..,4} - * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. - * In the case where there are multiple pin selections, the correct - * setting must be provided in the arch/board/board.h file. + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel + * {1,..,4} PWM_TIMx_CHn - One of the values defined in + * chip/stm32*_pinmap.h. In the case where there are multiple pin + * selections, the correct setting must be provided in the arch/board/board.h + * file. * - * NOTE: - * The STM32 timers are each capable of generating different signals on - * each of the four channels with different duty cycles. That capability - * is not supported by this driver: Only one output channel per timer. + * NOTE: The STM32 timers are each capable of generating different signals on + * each of the four channels with different duty cycles. That capability is + * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# define PWM_TIM1_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# define PWM_TIM1_CH2NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# define PWM_TIM1_CH3NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# define PWM_TIM1_CH1NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# define PWM_TIM1_CH2NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# define PWM_TIM1_CH3NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif -# define PWM_TIM1_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +#endif + +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif -# define PWM_TIM2_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +#endif + +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif -# define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# define PWM_TIM14_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# define PWM_TIM14_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif -# define PWM_TIM14_NCHANNELS 1 -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +#endif + +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# define PWM_TIM15_CH1NCFG 0 +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif -# define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# define PWM_TIM16_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# define PWM_TIM16_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif -# define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# define PWM_TIM17_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# define PWM_TIM17_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif -# define PWM_TIM17_NCHANNELS 1 #endif #define PWM_NCHANNELS 1 -#endif /* CONFIG_STM32F0L0G0_PWM_MULTICHAN */ +#endif /* Complementary outputs support */ -#if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F0L0G0_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -566,6 +558,6 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c index 76f6b07bf9cd4..70c8df356ab39 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.c @@ -31,9 +31,9 @@ * according to the selected MCU family. */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32G0) # include "stm32g0_pwr.c" -#elif defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) # include "stm32f0l0_pwr.c" #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h index 21673d02c3ea2..1562b6073283e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_pwr.h" -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /**************************************************************************** * Pre-processor Definitions @@ -172,9 +172,9 @@ bool stm32_pwr_getwuf(void); * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) || defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE || CONFIG_STM32F0L0G0_STM32G0 */ +#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */ /**************************************************************************** * Name: stm32_pwr_setpvd @@ -193,7 +193,7 @@ void stm32_pwr_setvos(uint16_t vos); * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) +#if defined(CONFIG_STM32_ENERGYLITE) void stm32_pwr_setpvd(uint16_t pls); /**************************************************************************** @@ -216,7 +216,7 @@ void stm32_pwr_enablepvd(void); void stm32_pwr_disablepvd(void); -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ +#endif /* CONFIG_STM32_ENERGYLITE */ #undef EXTERN #if defined(__cplusplus) @@ -224,5 +224,5 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/stm32f0l0g0/stm32_qencoder.c index 8f09d5596fb15..65cc99455469d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ b/arch/arm/src/stm32f0l0g0/stm32_qencoder.c @@ -51,13 +51,13 @@ /* Timers *******************************************************************/ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS # undef HAVE_32BIT_TIMERS # undef HAVE_16BIT_TIMERS /* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ -# if defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_32BIT) +# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT) # define HAVE_32BIT_TIMERS 1 # endif @@ -65,9 +65,9 @@ * 16-bit timers */ -# if defined(CONFIG_STM32F0L0G0_TIM1_QE) || defined(CONFIG_STM32F0L0G0_TIM3_QE) || \ - defined(CONFIG_STM32F0L0G0_TIM4_QE) || \ - (defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_16BIT)) +# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || \ + (defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT)) # define HAVE_16BIT_TIMERS 1 # endif @@ -92,65 +92,65 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F0L0G0_QENCODER_FILTER -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_1) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_2) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_4) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32F0L0G0_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32F0L0G0_QENCODER_ICF -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32F0L0G0_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -207,13 +207,13 @@ struct stm32_lowerhalf_s bool inuse; /* True: The lower-half driver is in-use */ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN uint32_t index_pin; /* Index pin GPIO */ bool index_use; /* True: Index pin is configured */ int32_t index_offset; /* Index pin offset */ #endif -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS volatile int32_t position; /* The current position offset */ #endif spinlock_t lock; /* Spinlock */ @@ -243,11 +243,11 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN static int stm32_qe_index_irq(int irq, void *context, void *arg); #endif -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS static int stm32_interrupt(int irq, void *context, void *arg); #endif @@ -281,7 +281,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -290,7 +290,7 @@ static const struct stm32_qeconfig_s g_tim1config = .width = TIM1_BITWIDTH, #endif .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F0L0G0_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -305,7 +305,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -314,7 +314,7 @@ static const struct stm32_qeconfig_s g_tim2config = .width = TIM2_BITWIDTH, #endif .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F0L0G0_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -329,7 +329,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -338,7 +338,7 @@ static const struct stm32_qeconfig_s g_tim3config = .width = TIM3_BITWIDTH, #endif .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F0L0G0_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -353,7 +353,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -362,7 +362,7 @@ static const struct stm32_qeconfig_s g_tim4config = .width = TIM4_BITWIDTH, #endif .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F0L0G0_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -511,7 +511,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) +#if defined(CONFIG_STM32_TIM1_QE) if (priv->config->timid == 1) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -542,19 +542,19 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif @@ -571,7 +571,7 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN static int stm32_qe_index_irq(int irq, void *context, void *arg) { struct stm32_lowerhalf_s *priv; @@ -601,7 +601,7 @@ static int stm32_qe_index_irq(int irq, void *context, void *arg) * ****************************************************************************/ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS static int stm32_interrupt(int irq, void *context, void *arg) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; @@ -656,7 +656,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) uint32_t ccmr1; uint16_t ccer; uint16_t cr1; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS uint16_t regval; int ret; #endif @@ -699,7 +699,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) +#if defined(CONFIG_STM32_TIM1_QE) if (priv->config->timid == 1) { /* Clear the Repetition Counter value */ @@ -741,7 +741,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -777,7 +777,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -806,7 +806,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) /* There is no need for interrupts with 32-bit timers */ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS #ifdef HAVE_MIXEDWIDTH_TIMERS if (priv->config->width != 32) #endif @@ -839,7 +839,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) /* There is no need for interrupts with 32-bit timers */ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS #ifdef HAVE_MIXEDWIDTH_TIMERS if (priv->config->width != 32) #endif @@ -857,7 +857,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) } #endif -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN priv->index_offset = 0; #endif @@ -913,25 +913,25 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; @@ -961,14 +961,14 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32_configgpio(pincfg); return OK; @@ -985,7 +985,7 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS irqstate_t flags; int32_t position; int32_t verify; @@ -1027,7 +1027,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) static int stm32_reset(struct qe_lowerhalf_s *lower) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS irqstate_t flags; sninfo("Resetting position to zero\n"); @@ -1094,7 +1094,7 @@ static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) { -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = OK; @@ -1201,7 +1201,7 @@ int stm32_qeinitialize(const char *devpath, int tim) return OK; } -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN /**************************************************************************** * Name: stm32_qe_index_init * diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h index b6f1c4c9d9c7d..c46fbdf913574 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h @@ -38,23 +38,23 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F0L0G0_TIMn is - * defined then the CONFIG_STM32F0L0G0_TIMn_QE must also be defined to + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is + * defined then the CONFIG_STM32_TIMn_QE must also be defined to * indicate that timer "n" is intended to be used for as a quadrature * encoder. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM4 -# undef CONFIG_STM32F0L0G0_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif /* Only timers 1-4 can be used as a quadrature encoder (timers with @@ -63,12 +63,12 @@ * capability. */ -#undef CONFIG_STM32F0L0G0_TIM6_QE -#undef CONFIG_STM32F0L0G0_TIM7_QE -#undef CONFIG_STM32F0L0G0_TIM14_QE -#undef CONFIG_STM32F0L0G0_TIM15_QE -#undef CONFIG_STM32F0L0G0_TIM16_QE -#undef CONFIG_STM32F0L0G0_TIM17_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE /**************************************************************************** * Public Function Prototypes @@ -93,7 +93,7 @@ int stm32_qeinitialize(const char *devpath, int tim); -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN /**************************************************************************** * Name: stm32_qe_index_init * diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c index 7e89c4b1e20da..b227f714756c2 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.c @@ -42,13 +42,13 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG # ifndef STM32_USE_CLK48 # error RNG requires CLK48 enabled # endif #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # ifndef STM32_USE_CLK48 # error USB requires CLK48 enabled # endif @@ -103,7 +103,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) static inline void rcc_resetbkp(void) { uint32_t regval; @@ -144,7 +144,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ stm32_board_clockconfig(); @@ -198,7 +198,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -213,7 +213,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ stm32_board_clockconfig(); diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c index 49b43f2796e76..2ccebb1060b5d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F0L0G0_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c index a0d8178b52fb0..5edb01036ef7e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial.c @@ -33,9 +33,9 @@ * - STM32 UART IP version 2 - G0 */ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "stm32_serial_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 55f290837bf9c..444e48887214f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -84,14 +84,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA1 -# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA2 -# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -160,8 +160,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -175,7 +175,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -348,7 +348,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -356,7 +356,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -364,7 +364,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -372,7 +372,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; # ifdef CONFIG_USART4_RXDMA @@ -380,7 +380,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; # ifdef CONFIG_USART5_RXDMA @@ -390,7 +390,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static struct stm32_serial_s g_usart1priv = { .dev = @@ -452,7 +452,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static struct stm32_serial_s g_usart2priv = { .dev = @@ -514,7 +514,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static struct stm32_serial_s g_usart3priv = { .dev = @@ -576,7 +576,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static struct stm32_serial_s g_usart4priv = { .dev = @@ -642,7 +642,7 @@ static struct stm32_serial_s g_usart4priv = /* This describes the state of the STM32 USART5 port. */ -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 static struct stm32_serial_s g_usart5priv = { .dev = @@ -710,19 +710,19 @@ static struct stm32_serial_s g_usart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 [3] = &g_usart4priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 [4] = &g_usart5priv, #endif }; @@ -1005,7 +1005,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1047,31 +1047,31 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 case STM32_USART5_BASE: rcc_en = RCC_APB1ENR_USART5EN; regaddr = STM32_RCC_APB1ENR; @@ -1132,7 +1132,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1464,8 +1464,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1609,7 +1609,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE #warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN case TIOCSSINGLEWIRE: { @@ -1747,8 +1747,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1967,7 +1967,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2218,7 +2218,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2471,7 +2471,7 @@ void arm_serialinit(void) #if CONSOLE_USART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console USART to ttyS0 and exclude * it from initializing it further down */ @@ -2500,7 +2500,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index d286bb036d507..0d9d208c67fba 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -68,8 +68,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -83,7 +83,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -93,9 +93,9 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif @@ -216,29 +216,29 @@ static const struct uart_ops_s g_uart_ops = /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; #endif /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -293,7 +293,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -348,7 +348,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -403,7 +403,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static struct up_dev_s g_usart4priv = { .dev = @@ -460,16 +460,16 @@ static struct up_dev_s g_usart4priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 [3] = &g_usart4priv #endif }; @@ -738,7 +738,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -782,25 +782,25 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; @@ -865,7 +865,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1093,8 +1093,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1207,14 +1207,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -1237,7 +1237,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1390,8 +1390,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1590,7 +1590,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1966,7 +1966,7 @@ void arm_serialinit(void) #if CONSOLE_USART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1990,7 +1990,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index c23914442ca82..ae149747b0815 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -80,7 +80,7 @@ #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -129,10 +129,10 @@ /* SPI clocks */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#if defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) # define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -#elif defined(CONFIG_STM32F0L0G0_STM32G0) +#elif defined(CONFIG_STM32_STM32G0) # define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY @@ -157,10 +157,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -211,7 +211,7 @@ static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -247,7 +247,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords); -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange_nodma(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords); @@ -278,7 +278,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -318,10 +318,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F0L0G0_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -333,11 +333,11 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI1_COMMTYPE, + .config = CONFIG_STM32_SPI1_COMMTYPE, }; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -377,10 +377,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F0L0G0_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -390,11 +390,11 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI2_COMMTYPE, + .config = CONFIG_STM32_SPI2_COMMTYPE, }; #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -434,10 +434,10 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F0L0G0_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -447,7 +447,7 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI3_COMMTYPE, + .config = CONFIG_STM32_SPI3_COMMTYPE, }; #endif @@ -754,7 +754,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -787,7 +787,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -820,7 +820,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -835,7 +835,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -850,7 +850,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -870,7 +870,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -890,7 +890,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -941,7 +941,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -992,7 +992,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1008,7 +1008,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1495,7 +1495,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1604,7 +1604,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1622,7 +1622,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1684,7 +1684,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32F0L0G0_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1705,7 +1705,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1969,7 +1969,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2032,7 +2032,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2056,7 +2056,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2080,7 +2080,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2110,7 +2110,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) goto errout; } -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* SPI DMA supported only for full-duplex mode */ if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX) @@ -2131,4 +2131,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F0L0G0_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h index e6ea4bdc555bb..dd99c76575a22 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.h @@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,17 +146,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c index f3c76fa97e280..48a549aa41501 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim.c @@ -68,96 +68,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM * may also be defined to indicate that the timer is intended to be used * for pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32F0L0G0_TIMn is - * defined then CONFIG_STM32F0L0G0_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32F0L0G0_TIMn is defined then - * CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM1_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM1_DAC) || defined(CONFIG_STM32F0L0G0_TIM1_QE) -# undef CONFIG_STM32F0L0G0_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM2_DAC) || defined(CONFIG_STM32F0L0G0_TIM2_QE) -# undef CONFIG_STM32F0L0G0_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM3_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM3_DAC) || defined(CONFIG_STM32F0L0G0_TIM3_QE) -# undef CONFIG_STM32F0L0G0_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F0L0G0_TIM4_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM4_DAC) || defined(CONFIG_STM32F0L0G0_TIM4_QE) -# undef CONFIG_STM32F0L0G0_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM5_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM5_DAC) || defined(CONFIG_STM32F0L0G0_TIM5_QE) -# undef CONFIG_STM32F0L0G0_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F0L0G0_TIM6_PWM) || defined(CONFIG_STM32F0L0G0_TIM6_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM6_DAC) || defined(CONFIG_STM32F0L0G0_TIM6_QE) -# undef CONFIG_STM32F0L0G0_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32F0L0G0_TIM7_PWM) || defined(CONFIG_STM32F0L0G0_TIM7_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM7_DAC) || defined(CONFIG_STM32F0L0G0_TIM7_QE) -# undef CONFIG_STM32F0L0G0_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F0L0G0_TIM8_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM8_DAC) || defined(CONFIG_STM32F0L0G0_TIM8_QE) -# undef CONFIG_STM32F0L0G0_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F0L0G0_TIM12_PWM) || defined(CONFIG_STM32F0L0G0_TIM12_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM12_DAC) || defined(CONFIG_STM32F0L0G0_TIM12_QE) -# undef CONFIG_STM32F0L0G0_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F0L0G0_TIM13_PWM) || defined(CONFIG_STM32F0L0G0_TIM13_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM13_DAC) || defined(CONFIG_STM32F0L0G0_TIM13_QE) -# undef CONFIG_STM32F0L0G0_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM14_DAC) || defined(CONFIG_STM32F0L0G0_TIM14_QE) -# undef CONFIG_STM32F0L0G0_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM15_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM15_DAC) || defined(CONFIG_STM32F0L0G0_TIM15_QE) -# undef CONFIG_STM32F0L0G0_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM16_DAC) || defined(CONFIG_STM32F0L0G0_TIM16_QE) -# undef CONFIG_STM32F0L0G0_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) || defined(CONFIG_STM32F0L0G0_TIM17_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM17_DAC) || defined(CONFIG_STM32F0L0G0_TIM17_QE) -# undef CONFIG_STM32F0L0G0_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32F0L0G0_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) @@ -165,35 +165,35 @@ # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) @@ -201,37 +201,37 @@ # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -241,13 +241,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -324,7 +324,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .ackint = &stm32_tim_ackint }; -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -332,7 +332,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -341,7 +341,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -350,7 +350,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -359,7 +359,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -368,7 +368,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -377,7 +377,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -386,7 +386,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -395,7 +395,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -404,7 +404,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -413,7 +413,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -422,7 +422,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -431,7 +431,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -440,7 +440,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -582,47 +582,47 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB2_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -680,47 +680,47 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB2_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -789,52 +789,52 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1_BRK; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -960,16 +960,16 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -# if defined(CONFIG_STM32F0L0G0_TIM8) +# if defined(CONFIG_STM32_TIM8) || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE # endif ) { stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } -#endif /* CONFIG_STM32F0L0G0_TIM1 || CONFIG_STM32F0L0G0_TIM8 */ +#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */ return OK; } @@ -1065,7 +1065,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1099,7 +1099,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1159,7 +1159,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1174,7 +1174,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1189,7 +1189,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1209,7 +1209,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1224,7 +1224,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1308,85 +1308,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1418,72 +1418,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1499,4 +1499,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F0L0G0_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c index 25e8257960468..dbb558fa81b68 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c @@ -61,13 +61,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -143,7 +143,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -247,7 +247,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -559,72 +559,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c index 5a0737c414442..9a92038c40141 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c @@ -47,9 +47,9 @@ * (when CLKSOURCE = 0). ..." */ -#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK) +#if defined(CONFIG_STM32_SYSTICK_CORECLK) # define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ -#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16) +#elif defined(CONFIG_STM32_SYSTICK_CORECLK_DIV16) # define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ #endif @@ -137,7 +137,7 @@ void up_timer_initialize(void) * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." */ -#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK +#ifdef CONFIG_STM32_SYSTICK_CORECLK putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h index 92e2e7ceb777f..9ebcefc8fc5a9 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/stm32_uart.h @@ -41,29 +41,29 @@ * device. */ -#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8) -# undef CONFIG_STM32F0L0G0_USART8 +#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_USART8) +# undef CONFIG_STM32_USART8 #endif -#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7) -# undef CONFIG_STM32F0L0G0_USART7 +#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_USART7) +# undef CONFIG_STM32_USART7 #endif -#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6) -# undef CONFIG_STM32F0L0G0_USART6 +#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 #endif -#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5) -# undef CONFIG_STM32F0L0G0_USART5 +#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_USART5) +# undef CONFIG_STM32_USART5 #endif -#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4) -# undef CONFIG_STM32F0L0G0_USART4 +#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_USART4) +# undef CONFIG_STM32_USART4 #endif -#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3) -# undef CONFIG_STM32F0L0G0_USART3 +#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32F0L0G0_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32F0L0G0_USART1 +# undef CONFIG_STM32_USART1 #endif /* USART 3-8 are multiplexed to the same interrupt. Current interrupt @@ -72,128 +72,128 @@ * issue in the future. */ -#if defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART4 -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART8 +#if defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART4 +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART8 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \ - defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \ - defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \ - defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART4) || \ + defined(CONFIG_STM32_USART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_USART7) || defined(CONFIG_STM32_USART8) # define HAVE_USART 1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32F0L0G0_USART1) -# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART2) -# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER +#if !defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART4_SERIALDRIVER +# undef CONFIG_STM32_USART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER +#if !defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART5_SERIALDRIVER +# undef CONFIG_STM32_USART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER +#if !defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART7_SERIALDRIVER +# undef CONFIG_STM32_USART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART8) -# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER +#if !defined(CONFIG_STM32_USART8) +# undef CONFIG_STM32_USART8_SERIALDRIVER +# undef CONFIG_STM32_USART8_1WIREDRIVER #endif /* Check 1-Wire and U(S)ART conflicts */ -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER +#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER +#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER +#if defined(CONFIG_STM32_USART4_1WIREDRIVER) && defined(CONFIG_STM32_USART4_SERIALDRIVER) +# error Both CONFIG_STM32_USART4_1WIREDRIVER and CONFIG_STM32_USART4_SERIALDRIVER defined +# undef CONFIG_STM32_USART4_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER +#if defined(CONFIG_STM32_USART5_1WIREDRIVER) && defined(CONFIG_STM32_USART5_SERIALDRIVER) +# error Both CONFIG_STM32_USART5_1WIREDRIVER and CONFIG_STM32_USART5_SERIALDRIVER defined +# undef CONFIG_STM32_USART5_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER +#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER +#if defined(CONFIG_STM32_USART7_1WIREDRIVER) && defined(CONFIG_STM32_USART7_SERIALDRIVER) +# error Both CONFIG_STM32_USART7_1WIREDRIVER and CONFIG_STM32_USART7_SERIALDRIVER defined +# undef CONFIG_STM32_USART7_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER +#if defined(CONFIG_STM32_USART8_1WIREDRIVER) && defined(CONFIG_STM32_USART8_SERIALDRIVER) +# error Both CONFIG_STM32_USART8_1WIREDRIVER and CONFIG_STM32_USART8_SERIALDRIVER defined +# undef CONFIG_STM32_USART8_1WIREDRIVER #endif /* Is the serial driver enabled? */ -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_USART4_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART7_SERIALDRIVER) || defined(CONFIG_STM32_USART8_SERIALDRIVER) # define HAVE_SERIALDRIVER 1 #endif /* Is the 1-Wire driver? */ -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_USART4_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART7_1WIREDRIVER) || defined(CONFIG_STM32_USART8_1WIREDRIVER) # define HAVE_1WIREDRIVER 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -203,7 +203,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -213,7 +213,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -223,7 +223,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -233,7 +233,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -243,7 +243,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -253,7 +253,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART7_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -264,7 +264,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART8_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -304,35 +304,35 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER +#ifndef CONFIG_STM32_USART4_SERIALDRIVER # undef CONFIG_USART4_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER +#ifndef CONFIG_STM32_USART5_SERIALDRIVER # undef CONFIG_USART5_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER +#ifndef CONFIG_STM32_USART7_SERIALDRIVER # undef CONFIG_USART7_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER +#ifndef CONFIG_STM32_USART8_SERIALDRIVER # undef CONFIG_USART8_RXDMA #endif @@ -370,21 +370,21 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) +#elif defined(CONFIG_STM32_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) +#elif defined(CONFIG_STM32_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) +#elif defined(CONFIG_STM32_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) +#elif defined(CONFIG_STM32_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c index 9cfd7df85bda0..d98ef7274af32 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c @@ -55,7 +55,7 @@ #include "stm32_gpio.h" #include "stm32_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +# undef CONFIG_STM32_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -350,7 +350,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_dumpep(int epno); @@ -598,7 +598,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -656,7 +656,7 @@ static uint16_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -673,7 +673,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -3885,4 +3885,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/stm32f0l0g0/stm32_wdg.h index 1d688da6b3898..96ce766df5585 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ b/arch/arm/src/stm32f0l0g0/stm32_wdg.h @@ -69,7 +69,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -90,7 +90,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c index b483d8637d305..ec620d4953825 100644 --- a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c @@ -114,31 +114,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -165,67 +165,67 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR_FDCANEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_APB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; @@ -252,55 +252,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -364,7 +364,7 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Configure FDCAN1 clock source */ regval = getreg32(STM32_RCC_CCIPR1); diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c index ff387fbe10a4a..018b81897df45 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c @@ -44,7 +44,7 @@ /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48 # define STM32_USE_HSI48 # endif @@ -107,25 +107,25 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; @@ -152,121 +152,121 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 /* Timer 4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* Timer 14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CEC +#ifdef CONFIG_STM32_CEC /* CEC interface clock enable */ regval |= RCC_APB1ENR_CECEN; @@ -293,67 +293,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGCOMPEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART6 +#ifdef CONFIG_STM32_USART6 /* USART 6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART7 +#ifdef CONFIG_STM32_USART7 /* USART 7 clock enable */ regval |= RCC_APB2ENR_USART7EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART8 +#ifdef CONFIG_STM32_USART8 /* USART 8 clock enable */ regval |= RCC_APB2ENR_USART8EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Timer 1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* Timer 15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* Timer 16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* Timer 17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; @@ -379,7 +379,7 @@ static inline void rcc_enableapb2(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c index ab65b569e9674..6516b14f98cba 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data @@ -299,7 +299,7 @@ bool stm32_pwr_getwuf(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE +#ifdef CONFIG_STM32_ENERGYLITE void stm32_pwr_setvos(uint16_t vos) { uint16_t regval; @@ -391,6 +391,6 @@ void stm32_pwr_disablepvd(void) stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); } -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ +#endif /* CONFIG_STM32_ENERGYLITE */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c index 162a715f142cd..0e8b03e12efdc 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Functions @@ -93,4 +93,4 @@ void stm32_pwr_setvos(uint16_t vos) /* TODO Other stm32_pwr_* functions need to be implemented */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c index b12d4ea61baac..8933230be5f3e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c @@ -124,37 +124,37 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -181,91 +181,91 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPUSART1 +#ifdef CONFIG_STM32_LPUSART1 /* USART 5 clock enable */ regval |= RCC_APB1ENR_LPUSART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* LPTIM2 clock enable */ regval |= RCC_APB1ENR_LPTIM2EN; @@ -292,55 +292,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -407,14 +407,14 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR uint32_t pwr_vos; #endif uint32_t flash_ws; @@ -451,7 +451,7 @@ static void stm32_stdclockconfig(void) if (STM32_SYSCLK_FREQUENCY > 16000000) { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE1; #endif @@ -470,7 +470,7 @@ static void stm32_stdclockconfig(void) } else { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE2; #endif @@ -484,11 +484,11 @@ static void stm32_stdclockconfig(void) } } -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR stm32_pwr_setvos(pwr_vos); #endif -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -626,8 +626,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -638,7 +638,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c index 201619738e26a..1acb1b4a597e5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c @@ -63,55 +63,55 @@ #define FLASH_BLOCK_SIZE _K(2) #define FLASH_PAGE_SIZE 8 -#if !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE) +#if !defined(CONFIG_STM32_FLASH_CONFIG_4) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_6) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE) # error "No valid flash configuration was defined." #endif -#ifdef CONFIG_STM32F0L0G0_FLASH_OVERRIDE -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_E -# if defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_4) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_6) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_8) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_B) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_C) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_E) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_E +#ifdef CONFIG_STM32_FLASH_OVERRIDE +# undef CONFIG_STM32_FLASH_CONFIG_4 +# undef CONFIG_STM32_FLASH_CONFIG_6 +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_4) +# define CONFIG_STM32_FLASH_CONFIG_4 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_6) +# define CONFIG_STM32_FLASH_CONFIG_6 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # else # error "Invalid flash configuration override provided" # endif #endif -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) +#if defined(CONFIG_STM32_FLASH_CONFIG_4) # define FLASH_NBLOCKS 8 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) +#elif defined(CONFIG_STM32_FLASH_CONFIG_6) # define FLASH_NBLOCKS 16 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) +#elif defined(CONFIG_STM32_FLASH_CONFIG_8) # define FLASH_NBLOCKS 32 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) # define FLASH_NBLOCKS 64 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define FLASH_NBLOCKS 128 # ifdef CONFIG_ARCH_CHIP_STM32G0 # define FLASH_DUAL_BANK 1 # define FLASH_BANK2_BASE 0x08020000 # endif -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define FLASH_NBLOCKS 256 # ifdef CONFIG_ARCH_CHIP_STM32G0 # define FLASH_DUAL_BANK 1 @@ -421,12 +421,12 @@ static void flash_lock_opt(void) static int flash_verify_blocknum(size_t block) { #ifdef FLASH_DUAL_BANK -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) if ((block < 0 || block > 63) && (block < 256 || block > 319)) { return -EFAULT; } -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) if ((block < 0 || block > 127) && (block < 256 || block > 383)) { return -EFAULT; diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c index 558ee7a23287c..6e7b9a92f9d4a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c @@ -51,10 +51,10 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 -# ifndef CONFIG_STM32F0L0G0_VREFINT +# ifndef CONFIG_STM32_VREFINT # error VREFINT must be enabled if HSI48 used # endif # endif @@ -133,31 +133,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; @@ -184,115 +184,115 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR_LCDEN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C 3 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; @@ -319,37 +319,37 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM21 +#ifdef CONFIG_STM32_TIM21 /* TIM21 Timer clock enable */ regval |= RCC_APB2ENR_TIM21EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM22 +#ifdef CONFIG_STM32_TIM22 /* TIM22 Timer clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; @@ -448,11 +448,11 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -504,7 +504,7 @@ static void stm32_stdclockconfig(void) stm32_pwr_setvos(pwr_vos); -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -683,8 +683,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -695,7 +695,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -722,7 +722,7 @@ static void stm32_stdclockconfig(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT static void vrefint_enable(void) { uint32_t regval = 0; @@ -759,7 +759,7 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT vrefint_enable(); #endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig index 29a75f2172428..a9c565cda4266 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig @@ -48,11 +48,11 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig index 5fd878ff4ff73..6b40188837b4e 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index bd5efbbb3c5ac..d7167b38ab31a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -55,9 +55,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=1024 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig index 7ed1d73f33808..c200442001979 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h index 7ce26a908b00c..95e19a5a6c293 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h @@ -87,7 +87,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt index 133c3298bce49..4770af26d5f88 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs index c1646dd2d1cd1..55c1d27f870da 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 04013570d18bf..81c81c06f1d51 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -137,7 +137,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c index c28639ad262a3..36d2d48f60e71 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c @@ -36,7 +36,7 @@ #include "stm32.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) /**************************************************************************** * Pre-processor Definitions @@ -130,4 +130,4 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */ +#endif /* CONFIG_ADC && CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c index 3df42fb83cb73..ce025e3b964df 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c @@ -70,7 +70,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c index 9cd2d49b180cd..152c4cc463c30 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c @@ -97,13 +97,13 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif } diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c index 5e5040b0a86d0..7b42fb7e3ce13 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-l072z-lrwan1.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -117,7 +117,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -168,9 +168,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -182,6 +182,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#endif /* CONFIG_STM32F0L0G0_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig index c2ff70981676b..d7d1b1380ecca 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig @@ -46,16 +46,16 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY=10 -CONFIG_STM32F0L0G0_ADC1_TIMTRIG=3 -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_ADC=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=10 +CONFIG_STM32_ADC1_TIMTRIG=3 +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_ADCSCOPE=y CONFIG_SYSTEM_ADCSCOPE_FETCH_INTERVAL=0 CONFIG_SYSTEM_ADCSCOPE_SERIAL_PATH="/dev/ttyS0" diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig index effe787fe7515..6f04583925bfe 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig @@ -72,20 +72,20 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXMBCLIENT=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig index af2948dd839e9..ede50792f32d5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig @@ -38,7 +38,7 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c index b12a1c64a71d5..67acc29262f07 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c index 574a196b77861..139d760fc25fc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG # include #endif @@ -77,7 +77,7 @@ int stm32_bringup(void) { int ret; -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig index e8640c01a5c45..af46d19b5c7fe 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig @@ -42,10 +42,10 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig index 0be70e4919560..9a9e901e2bd7e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig @@ -47,11 +47,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 CONFIG_START_MONTH=10 CONFIG_START_YEAR=2014 -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_FDCAN_SOCKET=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig index c3a1f4f8b40f5..8728028d0dc4e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig @@ -69,21 +69,21 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=2 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_PULSECOUNT=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=2 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PULSECOUNT=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig index ed0012322cc6f..49856182e0058 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig @@ -38,7 +38,7 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt index 163b6d6bb7c73..eacf44fab2591 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) + if(CONFIG_STM32_FDCAN_SOCKET) list(APPEND SRCS stm32_cansock.c) endif() endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs index aa1ef14621960..b6701ee29bf87 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) CSRCS += stm32_cansock.c endif endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h index c802a74b0171b..f7ab2300b193d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h @@ -116,7 +116,7 @@ int stm32_adc_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(void); #endif @@ -128,7 +128,7 @@ int stm32_can_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET int stm32_cansock_setup(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c index ceb6af10047d6..29e95219a8e08 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c index ba1c4751664b2..eb5bb09a60f32 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c @@ -39,7 +39,7 @@ # include #endif -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG # include #endif @@ -85,7 +85,7 @@ int stm32_bringup(void) #endif int ret; -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); @@ -150,7 +150,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /* Initialize CAN and register the CAN driver. */ ret = stm32_can_setup(); @@ -160,7 +160,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /* Initialize CAN socket interface */ ret = stm32_cansock_setup(); diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig index fe6bd5a96bce0..b5de6c951e8d5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig @@ -50,8 +50,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h index fc01e4546cb0c..c8098bc38de67 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h index 6fa9242000a11..36016f917cc98 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F072RB GPIOs ******************************************************/ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c index b742e7e62ecf6..dbb0d70b4b831 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c @@ -40,7 +40,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig index 039c992186b98..10d566c6b7dbf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig @@ -52,8 +52,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig index 6637887a09c0c..aac6d73808468 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h index 8c99f86513f12..dd2355bc204e8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt index bfafa31ee78a0..afd6342087a89 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs index b455d3605ef0e..82b838efb8113 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h index d4798c5bd8799..fadc808cd3833 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F091RC GPIOs ******************************************************/ @@ -126,7 +126,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c index 3c92121c7d10d..57014d141dfc2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c index e94166da23c19..0fc2cab2ae5f3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-f091rc.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -90,7 +90,7 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ } /**************************************************************************** @@ -119,7 +119,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -170,9 +170,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -184,6 +184,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 2f5e5cf0859f3..9b43266c33578 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -58,47 +58,47 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM15=y -CONFIG_STM32F0L0G0_TIM15_CH1OUT=y -CONFIG_STM32F0L0G0_TIM15_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM15_PWM=y -CONFIG_STM32F0L0G0_TIM16=y -CONFIG_STM32F0L0G0_TIM16_CH1OUT=y -CONFIG_STM32F0L0G0_TIM16_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM16_PWM=y -CONFIG_STM32F0L0G0_TIM17=y -CONFIG_STM32F0L0G0_TIM17_CH1OUT=y -CONFIG_STM32F0L0G0_TIM17_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM17_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_CH1OUT=y -CONFIG_STM32F0L0G0_TIM1_CH2OUT=y -CONFIG_STM32F0L0G0_TIM1_CH3OUT=y -CONFIG_STM32F0L0G0_TIM1_CH4OUT=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM1_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_CH1OUT=y -CONFIG_STM32F0L0G0_TIM3_CH2OUT=y -CONFIG_STM32F0L0G0_TIM3_CH3OUT=y -CONFIG_STM32F0L0G0_TIM3_CH4OUT=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM3_PWM=y -CONFIG_STM32F0L0G0_TIM6=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM15=y +CONFIG_STM32_TIM15_CH1OUT=y +CONFIG_STM32_TIM15_CHANNEL1=y +CONFIG_STM32_TIM15_PWM=y +CONFIG_STM32_TIM16=y +CONFIG_STM32_TIM16_CH1OUT=y +CONFIG_STM32_TIM16_CHANNEL1=y +CONFIG_STM32_TIM16_PWM=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM17_CH1OUT=y +CONFIG_STM32_TIM17_CHANNEL1=y +CONFIG_STM32_TIM17_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CH4OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_CHANNEL3=y +CONFIG_STM32_TIM3_CHANNEL4=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c index 7783acec8ab67..5fc389ad0669c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c index 4d21f1918aec3..975cd5aeb1c7b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c @@ -101,10 +101,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif } @@ -177,7 +177,7 @@ int stm32_bringup(void) #ifdef CONFIG_TIMER /* Initialize basic timers */ -#if defined(CONFIG_STM32F0L0G0_TIM6) +#if defined(CONFIG_STM32_TIM6) syslog(LOG_ERR, "Init timer\n"); ret = stm32_timer_driver_setup("/dev/timer0", 6); if (ret < 0) @@ -187,7 +187,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM7) +#if defined(CONFIG_STM32_TIM7) ret = stm32_timer_driver_setup("/dev/timer1", 7); if (ret < 0) { diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c index 939713a65cb8a..b81ff3aa9b6a2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -100,7 +100,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -116,7 +116,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -132,7 +132,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) +#if defined(CONFIG_STM32_TIM14_PWM) pwm = stm32_pwminitialize(14); if (!pwm) { @@ -148,7 +148,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32_pwminitialize(15); if (!pwm) { @@ -164,7 +164,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32_pwminitialize(16); if (!pwm) { @@ -180,7 +180,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM17_PWM) pwm = stm32_pwminitialize(17); if (!pwm) { diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig index ee39c1d282180..58d337a3690d7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig @@ -42,8 +42,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c index a0104c3a648f4..14706cd0ce53a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig index d56da04bd24d0..565ff0d9dd1dc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig @@ -48,9 +48,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig index e85080bc6dd61..539f7b5141c82 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -50,18 +50,18 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_CONTINUOUS=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32F0L0G0_ADC_LL_OPS=y -CONFIG_STM32F0L0G0_ADC_OVERSAMPLE=y -CONFIG_STM32F0L0G0_ADC_OVSR=7 -CONFIG_STM32F0L0G0_ADC_OVSS=4 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_CONTINUOUS=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_OVERSAMPLE=y +CONFIG_STM32_ADC_OVSR=7 +CONFIG_STM32_ADC_OVSS=4 +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig index 5ac96442f86b0..5eea859d573e5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig @@ -42,8 +42,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c index 8d345718a0614..b1f9be4fd7243 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c @@ -36,7 +36,7 @@ #include "stm32.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c index 97a7c428eba35..e882e5d161749 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig index 3daccc627d569..c04c43cd46e47 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig index 085ba16e7d1f2..fc8331e8670e4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h index cd1539a76b303..d24c64eaaf4d8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h @@ -88,7 +88,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt index c14a6c3588178..ac95ed5c073dc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs index bd4f63065bd7d..ff5d2d230eb14 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h index 7e17a772c3682..90410fded75cb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h @@ -140,7 +140,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c index ce6e4324bde83..a08ebff39304d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c @@ -70,7 +70,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c index eb49b42280431..2481cdfb428cf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "stm32_spi.h" #include "nucleo-l073rz.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0G0_SPI2) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI2) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c index e9d0a74aae1d2..a9495e3544c7d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-l073rz.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_WL_NRF24L01 /* Configure the SPI-based NRF24L01 chip select GPIO */ @@ -99,16 +99,16 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure the SPI-based MFRC522 chip select GPIO */ # ifdef CONFIG_CL_MFRC522 stm32_configgpio(GPIO_MFRC522_CS); # endif -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ } /**************************************************************************** @@ -137,7 +137,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,9 +209,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -256,6 +256,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ #endif diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig index 7539573f8bebb..22a9310041d59 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig @@ -37,8 +37,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h index 4436101e931c3..0975e6956195d 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt index 185c0672fedfa..091c56d51df1b 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs index 520a4c8e8917b..b991bc06e471b 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h index 42d17d21bc050..5c74903ff1f6b 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig index 476c53cd1787f..7fc5f309f92a9 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig @@ -37,8 +37,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h index 3ccd8972dfe2d..06932bb64ee68 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt index 0475024980bd0..ac55fa30c7416 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs index 2963ffd2ae229..b71427a76278a 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h index f085bb693bd16..db6fe74ca2982 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig index 3835900807616..693e2684eb63e 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig @@ -47,8 +47,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig index a5ed5ebad7a6d..727e0620e56f2 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig @@ -69,10 +69,10 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_SPI1_COMMTYPE=1 -CONFIG_STM32F0L0G0_USART3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI1_COMMTYPE=1 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c index fbd8501ea9f4f..9fd6f2becdcc3 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c index 21acd958ab7a2..1dce5040dd370 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c @@ -39,7 +39,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F0L0G0_I2C1 +#ifndef CONFIG_STM32_I2C1 # error I2C1 must be enabled! #endif diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c index fcac1bef78e58..07037ab3d6bb8 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c @@ -46,10 +46,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -68,7 +68,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -110,7 +110,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,7 +183,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #if defined(CONFIG_LCD_SSD1306_SPI) @@ -197,14 +197,14 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig index 4510918393862..f761d37e14ea2 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig @@ -41,8 +41,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h index 59333f53c8c9d..5cc344752dcbd 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h @@ -83,7 +83,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE From c607e60972fd0715dee98169707ba29b7d9116f0 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 12/52] !arm/stm32f7: use common STM32 Kconfig symbols BREAKING CHANGE: STM32F7 Kconfig symbols were renamed from CONFIG_STM32F7_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_STM32F7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../guides/port_drivers_to_stm32f7.rst | 12 +- .../stm32f7/boards/nucleo-f722ze/index.rst | 4 +- .../stm32f7/boards/nucleo-f746zg/index.rst | 4 +- .../stm32f7/boards/nucleo-f767zi/index.rst | 4 +- .../stm32f7/boards/stm32f769i-disco/index.rst | 6 +- Documentation/platforms/arm/stm32f7/index.rst | 96 +- arch/arm/src/stm32f7/CMakeLists.txt | 54 +- arch/arm/src/stm32f7/Kconfig | 7552 ++--------------- arch/arm/src/stm32f7/Make.defs | 52 +- arch/arm/src/stm32f7/stm32_bbsram.h | 8 +- arch/arm/src/stm32f7/stm32_foc.c | 26 +- arch/arm/src/stm32f7/stm32_i2s.c | 18 +- arch/arm/src/stm32f7/stm32_pwm.h | 2 +- arch/arm/src/stm32f7/stm32_rcc.c | 8 +- arch/arm/src/stm32f7/stm32_rcc.h | 14 +- arch/arm/src/stm32f7/stm32_sai.c | 90 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 2 +- boards/arm/stm32f7/common/Kconfig | 106 +- boards/arm/stm32f7/common/src/CMakeLists.txt | 10 +- boards/arm/stm32f7/common/src/Make.defs | 10 +- boards/arm/stm32f7/nucleo-f722ze/Kconfig | 10 +- .../nucleo-f722ze/configs/can/defconfig | 13 +- .../nucleo-f722ze/configs/cansock/defconfig | 15 +- .../nucleo-f722ze/configs/composite/defconfig | 9 +- .../nucleo-f722ze/configs/nsh/defconfig | 7 +- .../stm32f7/nucleo-f722ze/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f722ze/src/Make.defs | 4 +- boards/arm/stm32f7/nucleo-f746zg/Kconfig | 10 +- .../nucleo-f746zg/configs/evalos/defconfig | 7 +- .../nucleo-f746zg/configs/note/defconfig | 81 +- .../nucleo-f746zg/configs/nsh/defconfig | 9 +- .../nucleo-f746zg/configs/pysim/defconfig | 83 +- .../stm32f7/nucleo-f746zg/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f746zg/src/Make.defs | 4 +- boards/arm/stm32f7/nucleo-f767zi/Kconfig | 10 +- .../nucleo-f767zi/configs/evalos/defconfig | 9 +- .../nucleo-f767zi/configs/netnsh/defconfig | 19 +- .../nucleo-f767zi/configs/nsh/defconfig | 1 + .../stm32f7/nucleo-f767zi/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f767zi/src/Make.defs | 4 +- boards/arm/stm32f7/steval-eth001v1/Kconfig | 4 +- .../steval-eth001v1/configs/foc_b16/defconfig | 23 +- .../steval-eth001v1/configs/foc_f32/defconfig | 23 +- .../steval-eth001v1/configs/nsh/defconfig | 3 +- .../steval-eth001v1/src/CMakeLists.txt | 2 +- .../arm/stm32f7/steval-eth001v1/src/Make.defs | 2 +- .../stm32f746-ws/configs/nsh/defconfig | 19 +- .../stm32f7/stm32f746-ws/src/CMakeLists.txt | 4 +- boards/arm/stm32f7/stm32f746-ws/src/Make.defs | 4 +- boards/arm/stm32f7/stm32f746g-disco/Kconfig | 2 +- .../stm32f746g-disco/configs/audio/defconfig | 15 +- .../stm32f746g-disco/configs/fb/defconfig | 15 +- .../stm32f746g-disco/configs/lvgl/defconfig | 19 +- .../stm32f746g-disco/configs/netnsh/defconfig | 21 +- .../stm32f746g-disco/configs/nsh/defconfig | 3 +- .../stm32f746g-disco/configs/nxdemo/defconfig | 15 +- .../stm32f746g-disco/configs/nxterm/defconfig | 15 +- .../stm32f746g-disco/src/CMakeLists.txt | 10 +- .../stm32f7/stm32f746g-disco/src/Make.defs | 10 +- .../stm32f769i-disco/configs/netnsh/defconfig | 39 +- .../stm32f769i-disco/configs/nsh/defconfig | 3 +- .../stm32f769i-disco/src/CMakeLists.txt | 2 +- .../stm32f7/stm32f769i-disco/src/Make.defs | 2 +- .../configs/dualcdcacm/defconfig | 5 +- .../configs/f7corecomp/defconfig | 17 +- .../configs/i2s/defconfig | 17 +- .../configs/meadow_os/defconfig | 5 +- .../configs/nsh/defconfig | 3 +- .../configs/projectlab/defconfig | 9 +- .../configs/sdram/defconfig | 7 +- .../configs/usbnsh/defconfig | 7 +- .../stm32f777zit6-meadow/src/CMakeLists.txt | 6 +- .../stm32f777zit6-meadow/src/Make.defs | 8 +- 75 files changed, 1239 insertions(+), 7489 deletions(-) diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index 0d552320695c8..e7c04a2f3e3bd 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -262,7 +262,7 @@ the buffers to the Cortex-M7 D-Cache line size: #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) - #ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC + #ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -274,10 +274,10 @@ the buffers to the Cortex-M7 D-Cache line size: #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) - #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) - #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) + #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NRXDESC) + #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NTXDESC) - #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) + #define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -366,8 +366,8 @@ Here is an example where the RX descriptors are invalidated: for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { ... diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst index 7beb7bb52a087..0243fbc5dec89 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst @@ -177,7 +177,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -213,7 +213,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst index f9ce45c6e3b74..f010732432a12 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst @@ -219,7 +219,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -255,7 +255,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst index ef64085ad76b3..addc01caee40b 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst @@ -221,7 +221,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -257,7 +257,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst index d510c3e498131..dbe20d4247b5f 100644 --- a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst @@ -129,9 +129,9 @@ configuration no builtin applications are selected. And these for enabling the STM32 timer PWM channel: - CONFIG_STM32F7_TIM1=y - CONFIG_STM32F7_TIM1_PWM=y - CONFIG_STM32F7_TIM1_CHANNEL=4 + CONFIG_STM32_TIM1=y + CONFIG_STM32_TIM1_PWM=y + CONFIG_STM32_TIM1_CHANNEL=4 nsh-ehternet ------------ diff --git a/Documentation/platforms/arm/stm32f7/index.rst b/Documentation/platforms/arm/stm32f7/index.rst index 5669353e6a07f..6f525e8e2fe6b 100644 --- a/Documentation/platforms/arm/stm32f7/index.rst +++ b/Documentation/platforms/arm/stm32f7/index.rst @@ -106,7 +106,7 @@ managed with dtcm_malloc(), dtcm_free(), etc. In order to use FMC SRAM, the following additional things need to be present in the NuttX configuration file: -- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the +- CONFIG_STM32_FMC_SRAM - Indicates that SRAM is available via the FMC (as opposed to an LCD or FLASH). - CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex) @@ -123,10 +123,10 @@ present in the NuttX configuration file: Clock ----- -- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock +- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock configuration features.:: - CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n - CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops @@ -134,23 +134,23 @@ Timers ------ Timer devices may be used for different purposes. One special purpose is -to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn +to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn is defined (as above) then the following may also be defined to indicate that the timer is intended to be used for pulsed output modulation, ADC conversion, or DAC conversion. Note that ADC/DAC require two definition: Not only do you have to assign the timer (n) for used by the ADC or DAC, but then you also have to configure which ADC or DAC (m) it is assigned to.: -- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 -- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 -- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 +- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 +- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 +- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 +- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 +- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 For each timer that is enabled for PWM usage, we need the following additional configuration settings: -- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} +- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} NOTE: The STM32 timers are each capable of generating different signals on each of the four channels with different duty cycles. That capability is @@ -206,11 +206,11 @@ CAN - CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined. -- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 +- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 -- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 +- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 -- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an +- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an dump of all CAN registers. CAN SocketCAN @@ -221,12 +221,12 @@ TODO SPI --- -- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI +- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI support. Non-interrupt-driven, poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance. - Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT. +- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. SDIO ---- @@ -238,41 +238,41 @@ ETH Options: -- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board +- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board -- CONFIG_STM32F7_MII - Support Ethernet MII interface +- CONFIG_STM32_MII - Support Ethernet MII interface -- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface +- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface -- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface +- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface -- CONFIG_STM32F7_RMII - Support Ethernet RMII interface +- CONFIG_STM32_RMII - Support Ethernet RMII interface -- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode +- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode -- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select full duplex mode. Default: half-duplex -- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select 100 MBps speed. Default: 10 Mbps -- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is defined. The PHY status register address may diff from PHY to PHY. This configuration sets the address of the PHY status register. -- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides bit mask indicating 10 or 100MBps speed. -- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the speed bit(s) indicating 100MBps speed. -- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is defined. This provide bit mask indicating full or half duplex modes. -- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the mode bits indicating full duplex mode. -- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported +- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported but some hooks are indicated with this condition. USB OTG FS @@ -284,30 +284,30 @@ Pre-requisites: - CONFIG_USBDEV - Enable USB device support - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block -- CONFIG_STM32F7_SYSCFG - Needed +- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block +- CONFIG_STM32_SYSCFG - Needed - CONFIG_SCHED_WORKQUEUE - Worker thread support is required Options: -- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. +- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) -- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO +- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit +- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 +- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 -- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever +- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever want to do that? -- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access +- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB +- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB packets. Depends on CONFIG_DEBUG_FEATURES. USB OTG HS @@ -353,16 +353,16 @@ Available for some Nucleo boards. The builtin SPI test facility can be enabled with the following settings:: - +CONFIG_STM32F7_SPI=y - +CONFIG_STM32F7_SPI1=y - +CONFIG_STM32F7_SPI2=y - +CONFIG_STM32F7_SPI3=y + +CONFIG_STM32_SPI=y + +CONFIG_STM32_SPI1=y + +CONFIG_STM32_SPI2=y + +CONFIG_STM32_SPI3=y - +# CONFIG_STM32F7_SPI_INTERRUPTS is not set - +# CONFIG_STM32F7_SPI1_DMA is not set - +# CONFIG_STM32F7_SPI2_DMA is not set - +# CONFIG_STM32F7_SPI3_DMA is not set - # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# CONFIG_STM32_SPI_INTERRUPTS is not set + +# CONFIG_STM32_SPI1_DMA is not set + +# CONFIG_STM32_SPI2_DMA is not set + +# CONFIG_STM32_SPI3_DMA is not set + # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_NUCLEO_SPI_TEST=y +CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 89cca465803d9..c352c7cf3a1e2 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -37,13 +37,13 @@ list( stm32_uid.c stm32_waste.c) -if(CONFIG_STM32F7_TICKLESS_TIMER) +if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32F7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -55,7 +55,7 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32F7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() @@ -66,11 +66,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32F7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -83,27 +83,31 @@ if(CONFIG_STM32F7_RTC) endif() endif() -if(CONFIG_STM32F7_IWDG OR CONFIG_STM32F7_RTC_LSICLOCK) +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_fmc.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32F7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F7_I2S) +if(CONFIG_STM32_I2S) list(APPEND SRCS stm32_i2s.c) endif() -if(CONFIG_STM32F7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -120,25 +124,25 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32F7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F7_QUADSPI) +if(CONFIG_STM32_QUADSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) endif() endif() -if(CONFIG_STM32F7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -146,19 +150,19 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32_dumpgpio.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32F7_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() -if(CONFIG_STM32F7_DMA2D) +if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() @@ -166,19 +170,19 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32F7_CAN_SOCKET) +if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_can_sock.c) endif() -if(CONFIG_STM32F7_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32_sai.c) endif() -if(CONFIG_STM32F7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -186,7 +190,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index ec6c5361ede17..b8203336b2fde 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -7,6 +7,47 @@ if ARCH_CHIP_STM32F7 comment "STM32 F7 Configuration Options" +config STM32_F7_PERIPHERALS + bool + default ARCH_CHIP_STM32F7 + select STM32_HAVE_ADC1 + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC2_DMA + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC3_DMA + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHRNET + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 if !STM32_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_FLASH_ART_ACCELERATOR + select STM32_HAVE_SDMMC2_DMAPRIO + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 F7 Chip Selection" default ARCH_CHIP_STM32F746NG @@ -14,7494 +55,1167 @@ choice config ARCH_CHIP_STM32F722RC bool "STM32F722RC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722RE bool "STM32F722RE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VC bool "STM32F722VC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VE bool "STM32F722VE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZC bool "STM32F722ZC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZE bool "STM32F722ZE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IC bool "STM32F722IC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IE bool "STM32F722IE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RC bool "STM32F723RC" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RE bool "STM32F723RE" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VC bool "STM32F723VC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VE bool "STM32F723VE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZC bool "STM32F723ZC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZE bool "STM32F723ZE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IC bool "STM32F723IC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IE bool "STM32F723IE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F745VG bool "STM32F745VG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745VE bool "STM32F745VE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IG bool "STM32F745IG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IE bool "STM32F745IE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZE bool "STM32F745ZE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZG bool "STM32F745ZG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BG bool "STM32F746BG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VG bool "STM32F746VG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VE bool "STM32F746VE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BE bool "STM32F746BE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZG bool "STM32F746ZG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IE bool "STM32F746IE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NG bool "STM32F746NG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NE bool "STM32F746NE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZE bool "STM32F746ZE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IG bool "STM32F746IG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756NG bool "STM32F756NG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756BG bool "STM32F756BG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756IG bool "STM32F756IG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756VG bool "STM32F756VG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756ZG bool "STM32F756ZG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F765NI bool "STM32F765NI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VI bool "STM32F765VI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VG bool "STM32F765VG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BI bool "STM32F765BI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765NG bool "STM32F765NG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZG bool "STM32F765ZG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZI bool "STM32F765ZI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765IG bool "STM32F765IG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BG bool "STM32F765BG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765II bool "STM32F765II" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NG bool "STM32F767NG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767IG bool "STM32F767IG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VG bool "STM32F767VG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZG bool "STM32F767ZG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NI bool "STM32F767NI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VI bool "STM32F767VI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767BG bool "STM32F767BG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZI bool "STM32F767ZI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767II bool "STM32F767II" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BI bool "STM32F769BI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769II bool "STM32F769II" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BG bool "STM32F769BG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NI bool "STM32F769NI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769AI bool "STM32F769AI" - select STM32F7_STM32F769AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NG bool "STM32F769NG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769IG bool "STM32F769IG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777ZI bool "STM32F777ZI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777VI bool "STM32F777VI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777NI bool "STM32F777NI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777BI bool "STM32F777BI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777II bool "STM32F777II" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F778AI bool "STM32F778AI" - select STM32F7_STM32F778AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F778AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779II bool "STM32F779II" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779NI bool "STM32F779NI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779BI bool "STM32F779BI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779AI bool "STM32F779AI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection -config STM32F7_STM32F72XX - bool - default n - -config STM32F7_STM32F73XX - bool - default n - -config STM32F7_STM32F74XX - bool - default n - -config STM32F7_STM32F75XX - bool - default n - -config STM32F7_STM32F76XX - bool - default n - -config STM32F7_STM32F77XX - bool - default n +config STM32_STM32F72XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F73XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F74XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F75XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F76XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + +config STM32_STM32F77XX + bool + default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 config STM32F7_IO_CONFIG_R + # Package designator R bool default n config STM32F7_IO_CONFIG_V + # Package designator V bool default n config STM32F7_IO_CONFIG_I + # Package designator I bool default n config STM32F7_IO_CONFIG_Z + # Package designator Z bool default n config STM32F7_IO_CONFIG_N + # Package designator N bool default n config STM32F7_IO_CONFIG_B + # Package designator B bool default n config STM32F7_IO_CONFIG_A + # Package designator A bool default n -config STM32F7_STM32F722XX +config STM32_STM32F722XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_EXTERNAL_ULPI + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_EXTERNAL_ULPI -config STM32F7_STM32F723XX +config STM32_STM32F723XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R -config STM32F7_STM32F745XX +config STM32_STM32F745XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F746XX +config STM32_STM32F746XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - select STM32F7_HAVE_EXTERNAL_ULPI - select STM32F7_HAVE_SAI1 - select STM32F7_HAVE_SAI2 - -config STM32F7_STM32F756XX - bool - default n - select STM32F7_STM32F75XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + select STM32_HAVE_EXTERNAL_ULPI + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + +config STM32_STM32F756XX + bool + default n + select STM32_STM32F75XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F765XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F765XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG # data sheet says yes, Product matrix says no - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F767XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG # data sheet says yes, Product matrix says no + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F767XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F768XX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F768XX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F768AX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F768AX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F769XX - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F769XX + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F769AX # Revisit When parts released - bool - default n - select STM32F7_STM32F76XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F769AX # Revisit When parts released + bool + default n + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F777XX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F777XX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F778XX # Revisit when parts released - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F778XX # Revisit when parts released + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F778AX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F778AX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F779XX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F779XX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_STM32F779AX - bool - default n - select STM32F7_STM32F77XX + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + +config STM32_STM32F779AX + bool + default n + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_FLASH_CONFIG_E - bool - default n - -config STM32F7_FLASH_CONFIG_G - bool - default n - -config STM32F7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32F7 - default STM32F7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F7 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32F7xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32F7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32F7_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F7_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F7_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32F7_FLASH_ART_ACCELERATOR - bool "Flash ART Accelerator" - default n - ---help--- - ART Accelerator on the flash memory ITCM interface accelerates code execution - with a system of instruction prefetch and cache lines. - - Enable if code and/or read-only data is accessed through ITCM bus instead of - AXIM bus. - -config STM32F7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_FMC - bool - default n - -config STM32F7_HAVE_ETHRNET - bool - default n - -config STM32F7_HAVE_PHY_POLLED - bool - default n - -config STM32F7_HAVE_RNG - bool - default n - -config STM32F7_HAVE_SPI4 - bool - default n - -config STM32F7_HAVE_SPI5 - bool - default n - -config STM32F7_HAVE_SPI6 - bool - default n - -config STM32F7_HAVE_SDMMC2 - bool - default n - -config STM32F7_HAVE_ADC1_DMA - bool - default n - -config STM32F7_HAVE_ADC2_DMA - bool - default n - -config STM32F7_HAVE_ADC3_DMA - bool - default n - -config STM32F7_HAVE_CAN2 - bool - default n - -config STM32F7_HAVE_CAN3 - bool - default n - -config STM32F7_HAVE_DCMI - bool - default n - -config STM32F7_HAVE_DSIHOST - bool - default n - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_DMA2D - bool - default n - -config STM32F7_HAVE_JPEG - bool - default n - -config STM32F7_HAVE_CRYP - bool - default n - -config STM32F7_HAVE_HASH - bool - default n - -config STM32F7_HAVE_DFSDM1 - bool - default n - -config STM32F7_HAVE_INTERNAL_ULPI - bool - default n - -config STM32F7_HAVE_EXTERNAL_ULPI - bool - default n - -config STM32F7_I2S - bool - default n - select STM32F7_SPI_DMA - -config STM32F7_HAVE_SAI1 - bool - default n - -config STM32F7_HAVE_SAI2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32F7_ADC - bool - default n - -config STM32F7_CAN - bool - default n - -config STM32F7_DAC - bool - default n - -config STM32F7_DMA - bool - default n - -config STM32F7_I2C - bool - default n - -config STM32F7_SAI - bool - default n - -config STM32F7_SDMMC - bool - default n - -config STM32F7_SPI - bool - default n - -config STM32F7_SPI_DMA - bool - default n - -config STM32F7_TIM - bool - default n - -config STM32F7_PWM - bool - default n - -config STM32F7_USART - bool - default n - -# These are the peripheral selections proper - -config STM32F7_ADC1 - bool "ADC1" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 - -config STM32F7_ADC2 - bool "ADC2" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 - -config STM32F7_ADC3 - bool "ADC3" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC3_DMA if STM32F7_DMA2 - -config STM32F7_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F7_CAN1 - bool "CAN1" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN2 - bool "CAN2" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN3 - bool "CAN3" - default n - select CAN - select STM32F7_CAN - depends on STM32F7_HAVE_CAN3 - -config STM32F7_CEC - bool "CEC" - default n - depends on STM32F7_VALUELINE - -config STM32F7_CRC - bool "CRC" - default n - -config STM32F7_CRYP - bool "CRYP" - depends on STM32F7_HAVE_CRYP - default n - -config STM32F7_DFSDM1 - bool "DFSDM1" - default n - depends on STM32F7_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 - -config STM32F7_DMA1 - bool "DMA1" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DMA2 - bool "DMA2" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DAC1 - bool "DAC1" - default n - select STM32F7_DAC - -config STM32F7_DAC2 - bool "DAC2" - default n - select STM32F7_DAC - -config STM32F7_DCMI - bool "DCMI" - default n - depends on STM32F7_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32F7_DSIHOST - bool "DSIHOST" - default n - depends on STM32F7_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI - compliant displays. - -config STM32F7_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32F7_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - -config STM32F7_JPEG - bool "JPEG" - default n - depends on STM32F7_HAVE_JPEG - ---help--- - The JPEG codec provides an fast and simple hardware compressor and - decompressor of JPEG images with full management of JPEG headers. - -config STM32F7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32F7_HAVE_ETHRNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32F7_HAVE_PHY_POLLED - -config STM32F7_FMC - bool "FMC" - depends on STM32F7_HAVE_FMC - default n - -config STM32F7_HASH - bool "HASH" - default n - depends on STM32F7_HAVE_HASH - select ARCH_HAVE_HASH - -config STM32F7_CEC - bool "HDMI-CEC" - default n - -config STM32F7_I2C1 - bool "I2C1" - default n - select STM32F7_I2C - -config STM32F7_I2C2 - bool "I2C2" - default n - select STM32F7_I2C - -config STM32F7_I2C3 - bool "I2C3" - default n - select STM32F7_I2C - -config STM32F7_I2C4 - bool "I2C4" - default n - select STM32F7_I2C - -config STM32F7_LPTIM1 - bool "Low-power timer 1" - default n - -config STM32F7_LTDC - bool "LTDC" - default n - select FB - depends on STM32F7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - With the STM32F7x8/9, the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32F7_DSIHOST and STM32F7_LTDC_USE_DSI. - -config STM32F7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_OTGFSHS - bool "OTG FS/HS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_QUADSPI - bool "QuadSPI" - default n - -config STM32F7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32F7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32F7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32F7_RTC - bool "RTC" - default n - select RTC - -config STM32F7_PWR - bool "PWR" - default n - -config STM32F7_RNG - bool "RNG" - default n - depends on STM32F7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F7_I2S1 - bool "I2S1" - default n - depends on !STM32F7_SPI1 - select STM32F7_I2S - -config STM32F7_I2S2 - bool "I2S2" - default n - depends on !STM32F7_SPI2 - select STM32F7_I2S - -config STM32F7_I2S3 - bool "I2S3" - default n - depends on !STM32F7_SPI3 - select STM32F7_I2S - -config STM32F7_SAI1 - bool "SAI1" - default n - depends on STM32F7_HAVE_SAI1 - -config STM32F7_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI2 - bool "SAI2" - default n - select STM32F7_HAVE_SAI2 - -config STM32F7_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SDMMC1 - bool "SDMMC1" - default n - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SDMMC2 - bool "SDMMC2" - default n - depends on STM32F7_HAVE_SDMMC2 - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SPDIFRX - bool "SPDIFRX" - default n - -config STM32F7_SPI1 - bool "SPI1" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI2 - bool "SPI2" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI3 - bool "SPI3" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI4 - bool "SPI4" - default n - depends on STM32F7_HAVE_SPI4 - select SPI - select STM32F7_SPI - -config STM32F7_SPI5 - bool "SPI5" - default n - depends on STM32F7_HAVE_SPI5 - select SPI - select STM32F7_SPI - -config STM32F7_SPI6 - bool "SPI6" - default n - depends on STM32F7_HAVE_SPI6 - select SPI - select STM32F7_SPI - -config STM32F7_SYSCFG - bool "SYSCFG" - default y - -config STM32F7_TIM1 - bool "TIM1" - default n - select STM32F7_TIM - -config STM32F7_TIM2 - bool "TIM2" - default n - select STM32F7_TIM - -config STM32F7_TIM3 - bool "TIM3" - default n - select STM32F7_TIM - -config STM32F7_TIM4 - bool "TIM4" - default n - select STM32F7_TIM - -config STM32F7_TIM5 - bool "TIM5" - default n - select STM32F7_TIM - -config STM32F7_TIM6 - bool "TIM6" - default n - select STM32F7_TIM - -config STM32F7_TIM7 - bool "TIM7" - default n - select STM32F7_TIM - -config STM32F7_TIM8 - bool "TIM8" - default n - select STM32F7_TIM - -config STM32F7_TIM9 - bool "TIM9" - default n - select STM32F7_TIM - -config STM32F7_TIM10 - bool "TIM10" - default n - select STM32F7_TIM - -config STM32F7_TIM11 - bool "TIM11" - default n - select STM32F7_TIM - -config STM32F7_TIM12 - bool "TIM12" - default n - select STM32F7_TIM - -config STM32F7_TIM13 - bool "TIM13" - default n - select STM32F7_TIM - -config STM32F7_TIM14 - bool "TIM14" - default n - select STM32F7_TIM - -config STM32F7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32F7_USART - -config STM32F7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32F7_USART - -config STM32F7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F7_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32F7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -menu "OTG Configuration" - depends on STM32F7_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - -menu "U[S]ART Configuration" - depends on STM32F7_USART - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32F7_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32F7_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32F7_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32F7_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32F7_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32F7_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32F7_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32F7_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config STM32F7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32F7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32F7_USART && SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32F7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32F7_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32F7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32F7_USART && STM32F7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32F7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32F7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F7 serial driver. - -config STM32F7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32F7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32F7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32F7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -if PM - -config STM32F7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "STM32F7_OTG_HS Configuration" - depends on STM32F7_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32F7_NO_ULPI - -config STM32F7_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32F7_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32F7_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -config STM32F7_EXTERNAL_RAM - bool "External RAM on FMC" - default n - depends on STM32F7_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SDRAM, external RAM may be available through the FMC. - -menu "QuadSPI Configuration" - depends on STM32F7_QUADSPI - -config STM32F7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32F7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32F7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32F7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32F7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32F7_QSPI_DMA - bool "DMA" - depends on STM32F7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32F7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32F7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32F7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32F7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32F7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32F7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32F7_DMA - ---help--- - 'Highest' priority. - -config STM32F7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32F7_DMA - ---help--- - 'High' priority. - -config STM32F7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32F7_DMA - ---help--- - 'Medium' priority. - -config STM32F7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32F7_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32F7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32F7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32F7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32F7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32F7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - -menu "SPI Configuration" - depends on STM32F7_SPI - -config STM32F7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32F7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32F7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32F7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32F7_SPI1 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32F7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32F7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32F7_SPI2 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32F7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32F7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32F7_SPI3 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32F7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32F7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32F7_SPI4 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32F7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32F7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32F7_SPI5 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32F7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32F7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32F7_SPI6 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32F7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # "SPI Configuration" - -menu "I2S Configuration" - depends on STM32F7_I2S - -config STM32F7_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -if STM32F7_I2S1 - -comment "I2S1 Configuration" - -config STM32F7_I2S1_MCK - bool "I2S1_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S1_RX - bool "Enable I2S1 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S1_TX - bool "Enable I2S1 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S1_DATALEN - int "I2S1 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S1 - -if STM32F7_I2S2 - -comment "I2S2 Configuration" - -config STM32F7_I2S2_MCK - bool "I2S2_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S2_RX - bool "Enable I2S2 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S2_TX - bool "Enable I2S2 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S2_DATALEN - int "I2S2 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S2 - -if STM32F7_I2S3 - -comment "I2S3 Configuration" - -config STM32F7_I2S3_MCK - bool "I2S3_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S3_RX - bool "Enable I2S3 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S3_TX - bool "Enable I2S3 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S3_DATALEN - int "I2S3 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S3 - -config STM32F7_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32F7_I2C - -config STM32F7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "SD/MMC Configuration" - depends on STM32F7_SDMMC - -config STM32F7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32F7_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32F7_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32F7_SDMMC1 - -config STM32F7_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32F7_SDMMC2 - -config STM32F7_SDMMC2_DMAPRIO - hex "SDMMC2 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC2 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32F7_BKPSRAM - -config STM32F7_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32F7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32F7_BBSRAM - -config STM32F7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32F7_BBSRAM - -endif # STM32F7_BKPSRAM - -config STM32F7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32F7_RTC - -config STM32F7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32F7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32F7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32F7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32F7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -endif # STM32F7_RTC_LSECLOCK - -endmenu # RTC Configuration - -config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32F7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32F7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32F7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32F7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32F7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32F7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32F7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32F7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32F7_TIM1 - select STM32F7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM1_PWM - -config STM32F7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32F7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32F7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM1_CHANNEL6 - -config STM32F7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM1_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM1_CHANNEL = 1 - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 1 - -if STM32F7_TIM1_CHANNEL = 2 - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 2 - -if STM32F7_TIM1_CHANNEL = 3 - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 3 - -if STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM1_PWM - -config STM32F7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32F7_TIM2 - select STM32F7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM2_PWM - -config STM32F7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM2_CHANNEL4 - -config STM32F7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM2_CHANNEL = 1 - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL = 1 - -if STM32F7_TIM2_CHANNEL = 2 - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL = 2 - -if STM32F7_TIM2_CHANNEL = 3 - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL = 3 - -if STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM2_PWM - -config STM32F7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32F7_TIM3 - select STM32F7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM3_PWM - -config STM32F7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM3_CHANNEL4 - -config STM32F7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM3_CHANNEL = 1 - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL = 1 - -if STM32F7_TIM3_CHANNEL = 2 - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL = 2 - -if STM32F7_TIM3_CHANNEL = 3 - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL = 3 - -if STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM3_PWM - -config STM32F7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32F7_TIM4 - select STM32F7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM4_PWM - -config STM32F7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM4_CHANNEL4 - -config STM32F7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM4_CHANNEL = 1 - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL = 1 - -if STM32F7_TIM4_CHANNEL = 2 - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL = 2 - -if STM32F7_TIM4_CHANNEL = 3 - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL = 3 - -if STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM4_PWM - -config STM32F7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32F7_TIM5 - select STM32F7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM5_PWM - -config STM32F7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM5_CHANNEL4 - -config STM32F7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM5_CHANNEL = 1 - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL = 1 - -if STM32F7_TIM5_CHANNEL = 2 - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL = 2 - -if STM32F7_TIM5_CHANNEL = 3 - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL = 3 - -if STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM5_PWM - -config STM32F7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32F7_TIM8 - select STM32F7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM8_PWM - -config STM32F7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32F7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32F7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM8_CHANNEL6 - -config STM32F7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM8_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM8_CHANNEL = 1 - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 1 - -if STM32F7_TIM8_CHANNEL = 2 - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 2 - -if STM32F7_TIM8_CHANNEL = 3 - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 3 - -if STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM8_PWM - -config STM32F7_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32F7_TIM9 - select STM32F7_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM9_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM9_CHANNEL2 - -config STM32F7_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM9_CHANNEL = 1 - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL = 1 - -if STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM9_PWM - -config STM32F7_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32F7_TIM10 - select STM32F7_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM10_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM10_CHANNEL1 - -config STM32F7_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM10_PWM - -config STM32F7_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32F7_TIM11 - select STM32F7_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM11_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM11_CHANNEL1 - -config STM32F7_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM11_PWM - -config STM32F7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32F7_TIM12 - select STM32F7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM12_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM12_CHANNEL2 - -config STM32F7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM12_CHANNEL = 1 - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL = 1 - -if STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM12_PWM - -config STM32F7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32F7_TIM13 - select STM32F7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM13_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM13_CHANNEL1 - -config STM32F7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM13_PWM - -config STM32F7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32F7_TIM14 - select STM32F7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM14_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM14_CHANNEL1 - -config STM32F7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM14_PWM - -config STM32F7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32F7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32F7_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32F7_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32F7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32F7_TIM1 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32F7_TIM8 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32F7_TIM8_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM8_PULSECOUNT -config STM32F7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32F7_TIM1 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32F7_TIM1_ADC1 - depends on STM32F7_TIM1_ADC - -config STM32F7_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32F7_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32F7_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32F7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32F7_TIM2 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32F7_TIM2_ADC1 - depends on STM32F7_TIM2_ADC - -config STM32F7_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32F7_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32F7_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32F7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32F7_TIM3 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32F7_TIM3_ADC1 - depends on STM32F7_TIM3_ADC - -config STM32F7_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32F7_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32F7_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32F7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32F7_TIM4 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32F7_TIM4_ADC1 - depends on STM32F7_TIM4_ADC - -config STM32F7_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32F7_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32F7_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32F7_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32F7_TIM5 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM5 ADC channel" - default STM32F7_TIM5_ADC1 - depends on STM32F7_TIM5_ADC - -config STM32F7_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32F7_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32F7_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -config STM32F7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32F7_TIM8 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32F7_TIM8_ADC1 - depends on STM32F7_TIM8_ADC - -config STM32F7_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32F7_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32F7_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32F7_HAVE_ADC1_TIMER - bool - -config STM32F7_HAVE_ADC2_TIMER - bool - -config STM32F7_HAVE_ADC3_TIMER - bool - -config STM32F7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32F7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32F7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32F7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32F7_TIM1 && STM32F7_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32F7_TIM1_DAC1 - depends on STM32F7_TIM1_DAC - -config STM32F7_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32F7_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32F7_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32F7_TIM2 && STM32F7_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32F7_TIM2_DAC1 - depends on STM32F7_TIM2_DAC - -config STM32F7_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32F7_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32F7_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32F7_TIM3 && STM32F7_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32F7_TIM3_DAC1 - depends on STM32F7_TIM3_DAC - -config STM32F7_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32F7_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32F7_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32F7_TIM4 && STM32F7_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32F7_TIM4_DAC1 - depends on STM32F7_TIM4_DAC - -config STM32F7_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32F7_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32F7_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32F7_TIM5 && STM32F7_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32F7_TIM5_DAC1 - depends on STM32F7_TIM5_DAC - -config STM32F7_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32F7_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32F7_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32F7_TIM6 && STM32F7_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32F7_TIM6_DAC1 - depends on STM32F7_TIM6_DAC - -config STM32F7_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32F7_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32F7_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32F7_TIM7 && STM32F7_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32F7_TIM7_DAC1 - depends on STM32F7_TIM7_DAC - -config STM32F7_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32F7_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32F7_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32F7_TIM8 && STM32F7_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32F7_TIM8_DAC1 - depends on STM32F7_TIM8_DAC - -config STM32F7_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32F7_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32F7_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32F7_TIM9 && STM32F7_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM9 DAC channel" - default STM32F7_TIM9_DAC1 - depends on STM32F7_TIM9_DAC - -config STM32F7_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32F7_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -config STM32F7_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32F7_TIM10 && STM32F7_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM10 DAC channel" - default STM32F7_TIM10_DAC1 - depends on STM32F7_TIM10_DAC - -config STM32F7_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32F7_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -config STM32F7_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32F7_TIM11 && STM32F7_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM11 DAC channel" - default STM32F7_TIM11_DAC1 - depends on STM32F7_TIM11_DAC - -config STM32F7_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32F7_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -config STM32F7_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32F7_TIM12 && STM32F7_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM12 DAC channel" - default STM32F7_TIM12_DAC1 - depends on STM32F7_TIM12_DAC - -config STM32F7_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32F7_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -config STM32F7_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32F7_TIM13 && STM32F7_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM13 DAC channel" - default STM32F7_TIM13_DAC1 - depends on STM32F7_TIM13_DAC - -config STM32F7_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32F7_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -config STM32F7_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32F7_TIM14 && STM32F7_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM14 DAC channel" - default STM32F7_TIM14_DAC1 - depends on STM32F7_TIM14_DAC - -config STM32F7_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32F7_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -config STM32F7_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32F7_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32F7_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32F7_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32F7_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32F7_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32F7_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32F7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32F7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32F7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32F7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32F7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32F7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32F7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32F7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32F7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32F7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32F7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32F7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32F7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32F7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32F7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32F7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32F7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32F7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32F7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32F7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32F7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32F7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32F7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32F7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32F7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32F7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32F7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32F7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32F7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32F7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32F7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32F7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32F7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32F7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32F7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32F7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32F7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32F7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32F7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32F7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32F7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32F7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32F7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32F7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32F7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32F7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32F7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32F7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32F7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32F7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32F7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32F7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32F7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32F7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32F7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32F7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32F7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32F7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32F7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32F7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32F7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32F7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32F7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32F7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32F7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32F7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32F7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32F7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32F7_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32F7_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32F7_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32F7_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32F7_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32F7_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32F7_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32F7_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32F7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32F7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32F7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32F7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32F7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32F7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32F7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32F7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "CAN driver configuration" - depends on STM32F7_CAN - -choice - prompt "CAN character driver or SocketCAN support" - default STM32F7_CAN_CHARDRIVER - -config STM32F7_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F7_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -config STM32F7_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32F7_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined. - -config STM32F7_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32F7_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN3_BAUD - int "CAN3 BAUD" - default 250000 - depends on STM32F7_CAN3 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32F7_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32F7_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "ADC Configuration" - depends on STM32F7_ADC - -config STM32F7_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32F7_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32F7_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32F7_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32F7_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32F7_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32F7_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32F7_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32F7_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32F7_ADC1_DMA - bool "ADC1 DMA" - depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32F7_ADC1 - default STM32F7_ADC1_DMA - default n - -config STM32F7_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32F7_ADC1_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32F7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32F7_ADC1 && STM32F7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC2_DMA - bool "ADC2 DMA" - depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32F7_ADC2 - default STM32F7_ADC2_DMA - -config STM32F7_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32F7_ADC2_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32F7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32F7_ADC2 && STM32F7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC3_DMA - bool "ADC3 DMA" - depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32F7_ADC3 - default STM32F7_ADC3_DMA - -config STM32F7_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32F7_ADC3_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32F7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32F7_ADC3 && STM32F7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32F7_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32F7_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32F7_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32F7_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32F7_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32F7_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32F7_ADC1 && !STM32F7_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32F7_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32F7_ADC2 && !STM32F7_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32F7_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32F7_ADC3 && !STM32F7_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32F7_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32F7_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32F7_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32F7_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32F7_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32F7_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -endmenu # "ADC Configuration" - -menu "Ethernet MAC configuration" - depends on STM32F7_ETHMAC - -config STM32F7_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32F7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32F7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32F7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32F7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32F7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32F7_MII_EXTCLK - depends on STM32F7_MII - -config STM32F7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32F7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32F7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32F7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32F7_ETHFD - bool "Full duplex" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32F7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32F7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32F7_AUTONEG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32F7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32F7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32F7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32F7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32F7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32F7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32F7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32F7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32F7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32F7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32F7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32F7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32F7_RMII - bool - default !STM32F7_MII - -choice - prompt "RMII clock configuration" - default STM32F7_RMII_EXTCLK - depends on STM32F7_RMII - -config STM32F7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32F7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32F7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32F7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -if STM32F7_LTDC - -menu "LTDC Configuration" - -config STM32F7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32F7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32F7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32F7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32F7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32F7_LTDC_DITHER - bool "Dither support" - default n - -config STM32F7_LTDC_DITHER_RED - depends on STM32F7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32F7_LTDC_DITHER_GREEN - depends on STM32F7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32F7_LTDC_DITHER_BLUE - depends on STM32F7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32F7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32F7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32F7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32F7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32F7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32F7_LTDC_L1_RGB565 - -config STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32F7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32F7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32F7_LTDC_L2 - -config STM32F7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32F7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32F7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32F7_LTDC_L2_RGB565 - -config STM32F7_LTDC_L2_L8 - depends on STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32F7_LTDC_L2_AL44 - depends on STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32F7_LTDC_L2_AL88 - depends on STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32F7_LTDC_L2_RGB565 - depends on STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32F7_LTDC_L2_ARGB4444 - depends on STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32F7_LTDC_L2_ARGB1555 - depends on STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32F7_LTDC_L2_RGB888 - depends on STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32F7_LTDC_L2_ARGB8888 - depends on STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32F7_LTDC_L2 - -config STM32F7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32F7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32F7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32F7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu - -endif # STM32F7_LTDC - -if STM32F7_DMA2D - -menu "DMA2D Configuration" - -config STM32F7_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32F7_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32F7_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32F7_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC. - -config STM32F7_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32F7_DMA2D_L8 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32F7_DMA2D_AL44 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32F7_DMA2D_AL88 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32F7_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32F7_LTDC_L1_RGB565 - default y - -config STM32F7_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32F7_LTDC_L1_ARGB4444 - default y - -config STM32F7_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32F7_LTDC_L1_ARGB15555 - default y - -config STM32F7_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32F7_LTDC_L1_RGB888 - default y - -config STM32F7_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32F7_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32F7_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32F7_DMA2D - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32F7_TIM1 || STM32F7_TIM2 || STM32F7_TIM3 || STM32F7_TIM4 || STM32F7_TIM5 || STM32F7_TIM8 - -config STM32F7_TIM1_QE - bool "TIM1" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32F7_TIM1_QE - -config STM32F7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM2_QE - bool "TIM2" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32F7_TIM2_QE - -config STM32F7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM3_QE - bool "TIM3" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32F7_TIM3_QE - -config STM32F7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM4_QE - bool "TIM4" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32F7_TIM4_QE - -config STM32F7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM5_QE - bool "TIM5" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32F7_TIM5_QE - -config STM32F7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM8_QE - bool "TIM8" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32F7_TIM8_QE - -config STM32F7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F7_QENCODER_SAMPLE_FDTS_4 - -config STM32F7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel event count" - default STM32F7_QENCODER_SAMPLE_EVENT_6 - -config STM32F7_QENCODER_SAMPLE_EVENT_1 - depends on STM32F7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F7_QENCODER_SAMPLE_EVENT_2 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F7_QENCODER_SAMPLE_EVENT_4 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F7_QENCODER_SAMPLE_EVENT_5 - depends on STM32F7_QENCODER_SAMPLE_FDTS_16 || STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F7_QENCODER_SAMPLE_FDTS && !STM32F7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32F7_SAI - -choice - prompt "Operation mode" - default STM32F7_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32F7_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32F7_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32F7_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32F7_SAI1_BOTH_ASYNC - depends on STM32F7_SAI1_A && STM32F7_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32F7_SAI2_BOTH_ASYNC - depends on STM32F7_SAI2_A && STM32F7_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - -menuconfig STM32F7_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32F7_PWM_MULTICHAN - select STM32F7_PWM_LL_OPS - select STM32F7_ADC_LL_OPS - select STM32F7_ADC_CHANGE_SAMPLETIME - select STM32F7_ADC_NO_STARTUP_CONV - -if STM32F7_FOC - -config STM32F7_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32F7_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -choice - prompt "FOC ADC trigger selection" - default STM32F7_FOC_ADC_TRGO - -config STM32F7_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32F7_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on !STM32F7_FOC_FOC1 - select STM32F7_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -if STM32F7_FOC_FOC0 - -choice - prompt "FOC0 device ADC selection" - default STM32F7_FOC_FOC0_ADC1 - -config STM32F7_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC0 - -if STM32F7_FOC_FOC1 - -choice - prompt "FOC1 device ADC selection" - default STM32F7_FOC_FOC1_ADC2 - -config STM32F7_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC1 - -config STM32F7_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32F7_FOC_USE_TIM1 - bool - default n - select STM32F7_TIM1 - select STM32F7_TIM1_PWM - select STM32F7_TIM1_CHANNEL1 - select STM32F7_TIM1_CHANNEL2 - select STM32F7_TIM1_CHANNEL3 - select STM32F7_TIM1_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1OUT - select STM32F7_TIM1_CH2OUT - select STM32F7_TIM1_CH3OUT - select STM32F7_TIM1_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32F7_FOC_USE_TIM8 - bool - default n - select STM32F7_TIM8 - select STM32F7_TIM8_PWM - select STM32F7_TIM8_CHANNEL1 - select STM32F7_TIM8_CHANNEL2 - select STM32F7_TIM8_CHANNEL3 - select STM32F7_TIM8_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1OUT - select STM32F7_TIM8_CH2OUT - select STM32F7_TIM8_CH3OUT - select STM32F7_TIM8_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32F7_FOC_USE_ADC1 - bool - default n - select STM32F7_ADC1 - select STM32F7_ADC1_SCAN - select STM32F7_ADC1_JEXTSEL - -config STM32F7_FOC_USE_ADC2 - bool - default n - select STM32F7_ADC2 - select STM32F7_ADC2_SCAN - select STM32F7_ADC2_JEXTSEL - -config STM32F7_FOC_USE_ADC3 - bool - default n - select STM32F7_ADC3 - select STM32F7_ADC3_SCAN - select STM32F7_ADC3_JEXTSEL + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_USART1_RXDMA if STM32_DMA2 + select STM32_HAVE_USART1_TXDMA if STM32_DMA2 + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 + select STM32_HAVE_USART2_TXDMA if STM32_DMA1 + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 + select STM32_HAVE_USART3_TXDMA if STM32_DMA1 + select STM32_HAVE_UART4_RXDMA if STM32_DMA1 + select STM32_HAVE_UART4_TXDMA if STM32_DMA1 + select STM32_HAVE_UART5_RXDMA if STM32_DMA1 + select STM32_HAVE_UART5_TXDMA if STM32_DMA1 + select STM32_HAVE_USART6_RXDMA if STM32_DMA2 + select STM32_HAVE_USART6_TXDMA if STM32_DMA2 + select STM32_HAVE_UART7_RXDMA if STM32_DMA1 + select STM32_HAVE_UART7_TXDMA if STM32_DMA1 + select STM32_HAVE_UART8_RXDMA if STM32_DMA1 + select STM32_HAVE_UART8_TXDMA if STM32_DMA1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -endif #STM32F7_FOC endif # ARCH_CHIP_STM32F7 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 04f0514666b05..1afb883a71723 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -39,7 +39,7 @@ else CHIP_CSRCS += stm32_tickless.c endif -ifeq ($(CONFIG_STM32F7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -51,11 +51,11 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32F7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif @@ -66,11 +66,11 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32F7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -83,27 +83,27 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F7_I2S),y) +ifeq ($(CONFIG_STM32_I2S),y) CHIP_CSRCS += stm32_i2s.c endif -ifeq ($(CONFIG_STM32F7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -122,25 +122,25 @@ endif endif endif -ifeq ($(CONFIG_STM32F7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F7_QUADSPI),y) +ifeq ($(CONFIG_STM32_QUADSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c endif endif -ifeq ($(CONFIG_STM32F7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -148,19 +148,19 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32_dumpgpio.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32F7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif -ifeq ($(CONFIG_STM32F7_DMA2D),y) +ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif @@ -168,26 +168,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CHIP_CSRCS += stm32_can_sock.c endif -ifeq ($(CONFIG_STM32F7_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32_sai.c endif -ifeq ($(CONFIG_STM32F7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32F7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CHIP_CSRCS += stm32_foc.c endif diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index a660e0e02b97f..8cce7cdf69ea4 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) -# define STM32_BBSRAM_SIZE 4096 +# define STM32F7_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif @@ -55,11 +55,11 @@ # define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 9a3e4e3e17cdd..727ed62ff19d0 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -45,7 +45,7 @@ #include #include -#include "stm32_foc_m3m4_v1.h" +#include "stm32_foc.h" #include "hardware/stm32_dbgmcu.h" @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -392,38 +392,38 @@ #ifdef CONFIG_STM32_FOC_FOC0 # ifdef CONFIG_STM32_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC +# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC +# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC +# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC +# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif #ifdef CONFIG_STM32_FOC_FOC1 # ifdef CONFIG_STM32_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC +# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC +# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC +# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC +# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; } /* Write all registers at once */ diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 3aa1ef321d4ee..2ea56947173ea 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -232,9 +232,9 @@ #endif #if CONFIG_STM32_I2S1_DATALEN == 8 -# define STM32_I2S1_DATAMASK 0 +# define STM32F7_I2S1_DATAMASK 0 #elif CONFIG_STM32_I2S1_DATALEN == 16 -# define STM32_I2S1_DATAMASK 1 +# define STM32F7_I2S1_DATAMASK 1 #elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S1_DATALEN #else @@ -242,9 +242,9 @@ #endif #if CONFIG_STM32_I2S2_DATALEN == 8 -# define STM32_I2S2_DATAMASK 0 +# define STM32F7_I2S2_DATAMASK 0 #elif CONFIG_STM32_I2S2_DATALEN == 16 -# define STM32_I2S2_DATAMASK 1 +# define STM32F7_I2S2_DATAMASK 1 #elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S2_DATALEN #else @@ -252,9 +252,9 @@ #endif #if CONFIG_STM32_I2S3_DATALEN == 8 -# define STM32_I2S3_DATAMASK 0 +# define STM32F7_I2S3_DATAMASK 0 #elif CONFIG_STM32_I2S3_DATALEN == 16 -# define STM32_I2S3_DATAMASK 1 +# define STM32F7_I2S3_DATAMASK 1 #elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S3_DATALEN #else @@ -2486,7 +2486,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32_I2S2_DATAMASK; + priv->align = STM32F7_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S1 */ @@ -2551,7 +2551,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32_I2S2_DATAMASK; + priv->align = STM32F7_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S2 */ @@ -2616,7 +2616,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32_I2S3_DATAMASK; + priv->align = STM32F7_I2S3_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 0aa3aed6d7143..7b41058c32a45 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -321,7 +321,7 @@ #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32_PWM_MULTICHAN */ +#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index 3ce0a726002e2..b0c35860a24fb 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configurationfile. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -111,7 +111,7 @@ void stm32_clockconfig(void) stm32_pwr_initbkp(false); #endif -#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -151,7 +151,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index e96050d0cea19..2bf57bb9855ab 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -147,7 +147,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,9 +164,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index c037660ac41da..02dca95fe5c0f 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -107,14 +107,14 @@ #endif #ifdef CONFIG_STM32_SAI1 -#ifndef STM32_SAI1_FREQUENCY -# error "Please define STM32_SAI1_FREQUENCY in board.h" +#ifndef STM32F7_SAI1_FREQUENCY +# error "Please define STM32F7_SAI1_FREQUENCY in board.h" #endif #endif #ifdef CONFIG_STM32_SAI2 -#ifndef STM32_SAI2_FREQUENCY -# error "Please define STM32_SAI1_FREQUENCY in board.h" +#ifndef STM32F7_SAI2_FREQUENCY +# error "Please define STM32F7_SAI1_FREQUENCY in board.h" #endif #endif @@ -278,9 +278,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32_SAI1_A_BASE, + .base = STM32F7_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32_SAI1_FREQUENCY, + .frequency = STM32F7_SAI1_FREQUENCY, #ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -299,9 +299,9 @@ static struct stm32f7_sai_s g_sai1a_priv = static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32_SAI1_B_BASE, + .base = STM32F7_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32_SAI1_FREQUENCY, + .frequency = STM32F7_SAI1_FREQUENCY, #ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -322,9 +322,9 @@ static struct stm32f7_sai_s g_sai1b_priv = static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32_SAI2_A_BASE, + .base = STM32F7_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32_SAI2_FREQUENCY, + .frequency = STM32F7_SAI2_FREQUENCY, #ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -343,9 +343,9 @@ static struct stm32f7_sai_s g_sai2a_priv = static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32_SAI2_B_BASE, + .base = STM32F7_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32_SAI2_FREQUENCY, + .frequency = STM32F7_SAI2_FREQUENCY, #ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32_SAI_CR1_OFFSET), - sai_getreg(priv, STM32_SAI_CR2_OFFSET), - sai_getreg(priv, STM32_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), + sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), + sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32_SAI_IM_OFFSET), - sai_getreg(priv, STM32_SAI_SR_OFFSET), - sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32F7_SAI_IM_OFFSET), + sai_getreg(priv, STM32F7_SAI_SR_OFFSET), + sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); #else /* GCR */ #ifdef CONFIG_STM32_SAI1 - uint32_t gcr = getreg32(STM32_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); + uint32_t gcr = getreg32(STM32F7_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32F7_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1528,28 +1528,28 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index ab98d258eea1d..0042ed990e3dc 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -669,7 +669,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index c997b8e8b74f0..2a2346e41c230 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -664,7 +664,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index a7046107ba069..83f5630e0b8dc 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -684,7 +684,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig index 2d926e6634d73..8be75fe61735a 100644 --- a/boards/arm/stm32f7/common/Kconfig +++ b/boards/arm/stm32f7/common/Kconfig @@ -3,178 +3,178 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config STM32F7_ROMFS +config STM32_ROMFS bool "Automount baked-in ROMFS image" default n depends on FS_ROMFS ---help--- - Select STM32F7_ROMFS_IMAGEFILE, STM32F7_ROMFS_DEV_MINOR, STM32F7_ROMFS_MOUNTPOINT + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT -config STM32F7_ROMFS_DEV_MINOR +config STM32_ROMFS_DEV_MINOR int "Minor for the block device backing the data" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default 64 -config STM32F7_ROMFS_MOUNTPOINT +config STM32_ROMFS_MOUNTPOINT string "Mountpoint of the custom romfs image" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "/rom" -config STM32F7_ROMFS_IMAGEFILE +config STM32_ROMFS_IMAGEFILE string "ROMFS image file to include into build" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "../../../rom.img" -config STM32F7_SPI_TEST +config STM32_SPI_TEST bool "Enable SPI test" default n ---help--- Enable Spi test - initialize and configure SPI to send - STM32F7_SPI_TEST_MESSAGE text. The text is sent on the + STM32_SPI_TEST_MESSAGE text. The text is sent on the selected SPI Buses with the configured parameters. Note the CS lines will not be asserted. -if STM32F7_SPI_TEST +if STM32_SPI_TEST -config STM32F7_SPI_TEST_MESSAGE +config STM32_SPI_TEST_MESSAGE string "Text to Send on SPI Bus(es)" default "Hello World" - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Text to sent on SPI bus(es) -config STM32F7_SPI1_TEST +config STM32_SPI1_TEST bool "Test SPI bus 1" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 1 -if STM32F7_SPI1_TEST +if STM32_SPI1_TEST -config STM32F7_SPI1_TEST_FREQ +config STM32_SPI1_TEST_FREQ int "SPI 1 Clock Freq in Hz" default 1000000 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 Clock Freq -config STM32F7_SPI1_TEST_BITS +config STM32_SPI1_TEST_BITS int "SPI 1 number of bits" default 8 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 bit length choice prompt "SPI BUS 1 Clock Mode" - default STM32F7_SPI1_TEST_MODE3 + default STM32_SPI1_TEST_MODE3 ---help--- Sets SPI 1 clock mode -config STM32F7_SPI1_TEST_MODE0 +config STM32_SPI1_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI1_TEST_MODE1 +config STM32_SPI1_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI1_TEST_MODE2 +config STM32_SPI1_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI1_TEST_MODE3 +config STM32_SPI1_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 1 Clock Mode" -endif # STM32F7_SPI1_TEST +endif # STM32_SPI1_TEST -config STM32F7_SPI2_TEST +config STM32_SPI2_TEST bool "Test SPI bus 2" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 2 -if STM32F7_SPI2_TEST +if STM32_SPI2_TEST -config STM32F7_SPI2_TEST_FREQ +config STM32_SPI2_TEST_FREQ int "SPI 2 Clock Freq in Hz" default 12000000 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 Clock Freq -config STM32F7_SPI2_TEST_BITS +config STM32_SPI2_TEST_BITS int "SPI 2 number of bits" default 8 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 bit length choice prompt "SPI BUS 2 Clock Mode" - default STM32F7_SPI2_TEST_MODE3 + default STM32_SPI2_TEST_MODE3 ---help--- Sets SPI 2 clock mode -config STM32F7_SPI2_TEST_MODE0 +config STM32_SPI2_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI2_TEST_MODE1 +config STM32_SPI2_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI2_TEST_MODE2 +config STM32_SPI2_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI2_TEST_MODE3 +config STM32_SPI2_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 2 Clock Mode" -endif # STM32F7_SPI2_TEST +endif # STM32_SPI2_TEST -config STM32F7_SPI3_TEST +config STM32_SPI3_TEST bool "Test SPI bus 3" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 3 -if STM32F7_SPI3_TEST +if STM32_SPI3_TEST -config STM32F7_SPI3_TEST_FREQ +config STM32_SPI3_TEST_FREQ int "SPI 3 Clock Freq in Hz" default 40000000 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 Clock Freq -config STM32F7_SPI3_TEST_BITS +config STM32_SPI3_TEST_BITS int "SPI 3 number of bits" default 8 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 bit length choice prompt "SPI BUS 3 Clock Mode" - default STM32F7_SPI3_TEST_MODE3 + default STM32_SPI3_TEST_MODE3 ---help--- Sets SPI 3 clock mode -config STM32F7_SPI3_TEST_MODE0 +config STM32_SPI3_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI3_TEST_MODE1 +config STM32_SPI3_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI3_TEST_MODE2 +config STM32_SPI3_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI3_TEST_MODE3 +config STM32_SPI3_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 3 Clock Mode" -endif # STM32F7_SPI3_TEST -endif # STM32F7_SPI_TEST +endif # STM32_SPI3_TEST +endif # STM32_SPI_TEST diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt index f653591bd15e9..d4b612a0f4b2c 100644 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ b/boards/arm/stm32f7/common/src/CMakeLists.txt @@ -34,16 +34,16 @@ if(CONFIG_AUDIO_CS4344) list(APPEND SRCS stm32_cs4344.c) endif() -if(CONFIG_STM32F7_CAN) - if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can_setup.c) endif() - if(CONFIG_STM32F7_CAN_SOCKET) + if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_cansock_setup.c) endif() endif() -if(CONFIG_STM32F7_ROMFS) +if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() @@ -51,7 +51,7 @@ if(CONFIG_BOARDCTL_RESET) list(APPEND SRCS stm32_reset.c) endif() -if(CONFIG_STM32F7_SPI_TEST) +if(CONFIG_STM32_SPI_TEST) list(APPEND SRCS stm32_spitest.c) endif() diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs index 04321561a588b..0a4f96c20c4eb 100644 --- a/boards/arm/stm32f7/common/src/Make.defs +++ b/boards/arm/stm32f7/common/src/Make.defs @@ -34,16 +34,16 @@ ifeq ($(CONFIG_AUDIO_CS4344),y) CSRCS += stm32_cs4344.c endif -ifeq ($(CONFIG_STM32F7_CAN),y) -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CSRCS += stm32_can_setup.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CSRCS += stm32_cansock_setup.c endif endif -ifeq ($(CONFIG_STM32F7_ROMFS),y) +ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif @@ -51,7 +51,7 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += stm32_reset.c endif -ifeq ($(CONFIG_STM32F7_SPI_TEST),y) +ifeq ($(CONFIG_STM32_SPI_TEST),y) CSRCS += stm32_spitest.c endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/Kconfig b/boards/arm/stm32f7/nucleo-f722ze/Kconfig index 60ec42530ca0c..884622e3a10b8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/Kconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F722ZE_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F722ZE_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F722ZE_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig index 59f5aaad34ef0..1cb4871af1a92 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -46,12 +47,12 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig index c03ccde370cb4..59a299a009383 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_SOCKET=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig index f856c74056476..c5ade09840d2a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -70,10 +71,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig index 2e7c9a4dabd62..d1dd0b02677db 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -42,9 +43,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt index f8b17eb732e90..030ab2e985056 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs index 084c954afc3c9..d39777f15f48e 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/Kconfig b/boards/arm/stm32f7/nucleo-f746zg/Kconfig index c1d96afcf0bcd..d59a47ec85b41 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/Kconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F746ZG_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F746ZG_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F746ZG_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig index d32e6ac0e4cdf..95125cef76058 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -52,9 +53,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig index 0112b71b52d77..0997aceb7edba 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -95,46 +96,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NOTE=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig index ae9b97ca15ce3..c1b3531bf8a6a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,10 +44,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_DTCMEXCLUDE=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig index 291c438c26cd2..fe194da3bafe0 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig @@ -6,7 +6,7 @@ # modifications. # # CONFIG_NDEBUG is not set -# CONFIG_STM32F7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=16 CONFIG_ANALOG=y @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -91,46 +92,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt index 73a308ecf1c88..1c42f13728819 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs index 92eaf789e5872..78a75d54df0c4 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/Kconfig b/boards/arm/stm32f7/nucleo-f767zi/Kconfig index e8eb80d5fab6a..e01d882951fa5 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/Kconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F767ZI_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F767ZI_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F767ZI_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig index 3baad155b05b7..93030ce725802 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -55,10 +56,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig index 6ddfdc068527d..240cfc4a2e93f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,15 +63,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig index bc43b47e6f84b..c78a21c59fa35 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt index 28d7f560bef67..b9e35dee70508 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs index b4c24d64fec26..77197f80a79e0 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/steval-eth001v1/Kconfig b/boards/arm/stm32f7/steval-eth001v1/Kconfig index 6d1513de7bcc5..64f4caa11eb29 100644 --- a/boards/arm/stm32f7/steval-eth001v1/Kconfig +++ b/boards/arm/stm32f7/steval-eth001v1/Kconfig @@ -5,12 +5,12 @@ if ARCH_BOARD_STEVAL_ETH001V1 -if STM32F7_FOC +if STM32_FOC config BOARD_STM32F7_STEVALETH001V1_FOC_VBUS bool "STEVAL-ETH001V1 board VBUS sense" default n -endif # STM32F7_FOC +endif # STM32_FOC endif # ARCH_BOARD_STEVAL_ETH001V1 diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig index 89261567704a3..04b8ea48f2c33 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig index 2d3229bf10e2e..244c71c100b45 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig index cf898372ae82d..4e4dea5daa432 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt index 0082f8f94996b..fb3a6271dbe90 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt +++ b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs index ace68763fc406..6d4a16a40b5d8 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs +++ b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CSRCS += stm32_foc.c endif diff --git a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig index 378ee084c7f8b..30bf96e0d37bc 100644 --- a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746-ws" CONFIG_ARCH_BOARD_STM32F746_WS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746IG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_INTERRUPTSTACK=2600 @@ -75,15 +76,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_DMACAPABLE=y -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SDMMC1=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_SPI1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt index 973faf1d30432..00b881c28cf6a 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt @@ -22,11 +22,11 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_dma_alloc.c) -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs index 80e52803544eb..67df23791a92a 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_dma_alloc.c -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index 40785710b6d8e..8db1185d95b9a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32F7_QUADSPI + select STM32_QUADSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index 0205e65dc256e..59a85748ed622 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_SAI2=y -CONFIG_STM32F7_SAI2_A=y -CONFIG_STM32F7_SAI2_B=y -CONFIG_STM32F7_SAI2_B_SYNC_WITH_A=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_SAI2=y +CONFIG_STM32_SAI2_A=y +CONFIG_STM32_SAI2_B=y +CONFIG_STM32_SAI2_B_SYNC_WITH_A=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 1a6201d978f27..f437e6b8e7165 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -8,13 +8,14 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,11 +49,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index cb454fadbe662..4783972604f05 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -9,13 +9,14 @@ # CONFIG_LV_BUILD_EXAMPLES is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,13 +62,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STM32F746GDISCO_TOUCHSCREEN_SWAPXY=y -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index a72895966d05c..ea305fd81647f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,16 +62,16 @@ CONFIG_RR_INTERVAL=20 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index b7d6e8247b10a..870f454c8061e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index bef22e038407a..3ac4ed78996c0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -9,13 +9,14 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,11 +58,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index b1d0a83557572..59395d2b919fb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -10,13 +10,14 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -50,11 +51,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt index fa3921f051cc2..3b1baaf5cb3d0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() @@ -56,13 +56,13 @@ if(CONFIG_MTD_N25QXXX) list(APPEND SRCS stm32_n25q.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs index ddc33cdca5ba3..bfa456fb8a532 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs @@ -42,11 +42,11 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif @@ -58,13 +58,13 @@ ifeq ($(CONFIG_MTD_N25QXXX),y) CSRCS += stm32_n25q.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 74e1fa7b56801..a6feb52f19f0f 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,25 +58,25 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_BKPSRAM=y -CONFIG_STM32F7_CEC=y -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_I2C4=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x18 -CONFIG_STM32F7_PHYSR_100HD=0x8 -CONFIG_STM32F7_PHYSR_10FD=0x14 -CONFIG_STM32F7_PHYSR_10HD=0x4 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x1C -CONFIG_STM32F7_RNG=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_BKPSRAM=y +CONFIG_STM32_CEC=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1C +CONFIG_STM32_RNG=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index 0f40ae305257a..df8d9cd8a8431 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,7 +39,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt index b41627ab51855..1c726649844fe 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs index 82a79440d22a7..dacf581a7a28c 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs @@ -42,7 +42,7 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig index cf9cf1cb87d21..104b3eec356d3 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -45,8 +46,8 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 0361ac3973f4a..9da945aff6e96 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,14 +63,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_SDMMC2_SDIO_MODE=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index 2a5630c8763f9..d49ba47815bcf 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -88,14 +89,14 @@ CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_I2S2=y -CONFIG_STM32F7_I2S2_MCK=y -CONFIG_STM32F7_I2S2_TX=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S2=y +CONFIG_STM32_I2S2_MCK=y +CONFIG_STM32_I2S2_TX=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" CONFIG_SYSLOG_MAX_CHANNELS=2 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig index 8f9a71be40497..b5f1c6d5b171f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,8 +49,8 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 CONFIG_USBDEV=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig index b63aa4ec89f9b..290478e8ab3bd 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -36,7 +37,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index e4d37559d9d58..dd681d42bb6cc 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -64,10 +65,10 @@ CONFIG_SENSORS_BMI270=y CONFIG_SENSORS_BMI270_I2C=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig index 26e856613c856..aac213c9285b0 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,9 +39,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 6fb257d819b01..58b13ee72e00f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -54,9 +55,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt index a22e8a9afed18..a1c6ad74cb798 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt @@ -44,13 +44,13 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs index 8d6ef41b3a6f9..8b662918a3f55 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs @@ -47,13 +47,13 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif @@ -65,7 +65,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32F7_SDMMC2),y) +ifeq ($(CONFIG_STM32_SDMMC2),y) CSRCS += stm32_sdmmc.c endif From 1d672d2b9502bc759d19ddb397adece3ad09c1a6 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:38 +0200 Subject: [PATCH 13/52] !arm/stm32h5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32H5 Kconfig symbols were renamed from CONFIG_STM32H5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32h5/boards/nucleo-h563zi/index.rst | 8 +- Documentation/platforms/arm/stm32h5/index.rst | 2 +- arch/arm/src/stm32f7/stm32_bbsram.h | 8 +- arch/arm/src/stm32f7/stm32_foc.c | 24 +- arch/arm/src/stm32f7/stm32_i2s.c | 18 +- arch/arm/src/stm32f7/stm32_pwm.h | 2 +- arch/arm/src/stm32f7/stm32_sai.c | 90 +- arch/arm/src/stm32h5/CMakeLists.txt | 34 +- arch/arm/src/stm32h5/Kconfig | 6253 +---------------- arch/arm/src/stm32h5/Make.defs | 36 +- arch/arm/src/stm32h5/stm32_adc.c | 4 +- arch/arm/src/stm32h5/stm32_serial.c | 4 +- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 2 +- boards/arm/stm32h5/nucleo-h563zi/Kconfig | 2 +- .../nucleo-h563zi/configs/adc/defconfig | 5 +- .../configs/adc_watchdog/defconfig | 15 +- .../nucleo-h563zi/configs/dts/defconfig | 7 +- .../nucleo-h563zi/configs/fdcan1/defconfig | 9 +- .../nucleo-h563zi/configs/nsh/defconfig | 3 +- .../nucleo-h563zi/configs/nshusbnet/defconfig | 7 +- .../nucleo-h563zi/configs/pwm/defconfig | 9 +- .../nucleo-h563zi/configs/usbmsc/defconfig | 7 +- .../nucleo-h563zi/configs/usbnsh/defconfig | 5 +- .../stm32h5/nucleo-h563zi/src/CMakeLists.txt | 6 +- boards/arm/stm32h5/nucleo-h563zi/src/Makefile | 8 +- 25 files changed, 254 insertions(+), 6314 deletions(-) diff --git a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst index b6e324ef32c91..0ff9e56e127b3 100644 --- a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst +++ b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst @@ -182,7 +182,7 @@ This configuration enables USB Host support with the Mass Storage Class USB mass-storage device (e.g. a USB flash drive) to the board's USB-C connector. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_MSC`` — USB Mass Storage Class host driver - ``CONFIG_USBHOST_HUB`` — USB hub support - ``CONFIG_FS_FAT`` — FAT filesystem for mounting the storage device @@ -196,7 +196,7 @@ configured in this build. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** @@ -214,7 +214,7 @@ full networking support and the CDC-ECM USB Ethernet host driver. It is intended to test USB Host operation with a USB-to-Ethernet adapter that uses the CDC-ECM (Ethernet Control Model) protocol. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_CDCECM`` — USB CDC-ECM Ethernet host driver - ``CONFIG_USBHOST_COMPOSITE`` — composite USB device support - ``CONFIG_USBHOST_HUB`` — USB hub support @@ -233,7 +233,7 @@ verify network connectivity. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index 882a75ea5e4d7..fb49d8558da88 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -95,7 +95,7 @@ capable of operating as a device or host. Pre-requisites: - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32H5_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode +- CONFIG_STM32_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE. HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode. diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 8cce7cdf69ea4..a660e0e02b97f 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif @@ -55,11 +55,11 @@ # define CONFIG_STM32_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 727ed62ff19d0..5932b37c80d13 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -392,38 +392,38 @@ #ifdef CONFIG_STM32_FOC_FOC0 # ifdef CONFIG_STM32_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif #ifdef CONFIG_STM32_FOC_FOC1 # ifdef CONFIG_STM32_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 2ea56947173ea..3aa1ef321d4ee 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -232,9 +232,9 @@ #endif #if CONFIG_STM32_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 +# define STM32_I2S1_DATAMASK 0 #elif CONFIG_STM32_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 +# define STM32_I2S1_DATAMASK 1 #elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S1_DATALEN #else @@ -242,9 +242,9 @@ #endif #if CONFIG_STM32_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 +# define STM32_I2S2_DATAMASK 0 #elif CONFIG_STM32_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 +# define STM32_I2S2_DATAMASK 1 #elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S2_DATALEN #else @@ -252,9 +252,9 @@ #endif #if CONFIG_STM32_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 +# define STM32_I2S3_DATAMASK 0 #elif CONFIG_STM32_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 +# define STM32_I2S3_DATAMASK 1 #elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 # error Invalid value for CONFIG_STM32_I2S3_DATALEN #else @@ -2486,7 +2486,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S1 */ @@ -2551,7 +2551,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S2 */ @@ -2616,7 +2616,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } #endif /* CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 7b41058c32a45..0aa3aed6d7143 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -321,7 +321,7 @@ #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 02dca95fe5c0f..c037660ac41da 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -107,14 +107,14 @@ #endif #ifdef CONFIG_STM32_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif #ifdef CONFIG_STM32_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif @@ -278,9 +278,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -299,9 +299,9 @@ static struct stm32f7_sai_s g_sai1a_priv = static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -322,9 +322,9 @@ static struct stm32f7_sai_s g_sai1b_priv = static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -343,9 +343,9 @@ static struct stm32f7_sai_s g_sai2a_priv = static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ #ifdef CONFIG_STM32_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1528,28 +1528,28 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 37874fe58c99d..854b218996875 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -24,7 +24,7 @@ set(SRCS) # Common ARM and Cortex-M33 files -if(CONFIG_STM32H5_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -44,7 +44,7 @@ list( stm32_lsi.c stm32_uid.c) -if(CONFIG_STM32H5_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() @@ -56,7 +56,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H5_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() @@ -64,55 +64,55 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_fdcan.c) endif() -if(CONFIG_STM32H5_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32H5_ICACHE) +if(CONFIG_STM32_ICACHE) list(APPEND SRCS stm32_icache.c) endif() -if(CONFIG_STM32H5_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H5_QSPI1) +if(CONFIG_STM32_QSPI1) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H5_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H5_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() -if(CONFIG_STM32H5_USBFS) +if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32_usbfs.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usbdrdhost.c) endif() -if(CONFIG_STM32H5_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() -if(CONFIG_STM32H5_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -122,7 +122,7 @@ endif() # Required chip type specific files -if(CONFIG_STM32H5_STM32H5XXXX) +if(CONFIG_STM32_STM32H5XXXX) list(APPEND SRCS stm32h5xx_rcc.c) endif() diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 14730b3b84ee8..b7b5d76bc7ad0 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -7,6 +7,28 @@ if ARCH_CHIP_STM32H5 comment "STM32H5 Configuration Options" +config STM32_H5_PERIPHERALS + bool + default y + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_RNG + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_DTS + select STM32_HAVE_QSPI1 + select STM32_HAVE_USBFS_MODE + select STM32_HAVE_USBDRD_HOST + select STM32_HAVE_ADC_H5 + select STM32_HAVE_USART_H5 + select STM32_HAVE_I2C_H5 + choice prompt "STM32 H5 Chip Selection" default ARCH_CHIP_STM32H563ZI @@ -15,11 +37,11 @@ choice config ARCH_CHIP_STM32H563ZI bool "STM32H563ZI" select ARCH_CORTEXM33 - select STM32H5_STM32H5XXXX - select STM32H5_STM32H56XXX - select STM32H5_STM32H563XX - select STM32H5_STM32H5X3XX - select STM32H5_FLASH_CONFIG_I + select STM32_STM32H5XXXX + select STM32_STM32H56XXX + select STM32_STM32H563XX + select STM32_STM32H5X3XX + select STM32_FLASH_CONFIG_I select STM32H5_IO_CONFIG_Z ---help--- STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -28,6212 +50,121 @@ endchoice # STM32 H5 Chip Selection # Chip families: -config STM32H5_STM32H5XXXX +config STM32_STM32H5XXXX bool default n select ARCH_HAVE_FPU - select STM32H5_HAVE_ICACHE - -config STM32H5_STM32H56XXX - bool - default n - select STM32H5_HAVE_FDCAN1 - select STM32H5_HAVE_FDCAN2 - select STM32H5_HAVE_LPUART1 - select STM32H5_HAVE_USART1 - select STM32H5_HAVE_USART2 - select STM32H5_HAVE_USART3 - select STM32H5_HAVE_UART4 - select STM32H5_HAVE_UART5 - select STM32H5_HAVE_USART6 - select STM32H5_HAVE_UART7 - select STM32H5_HAVE_UART8 - select STM32H5_HAVE_UART9 - select STM32H5_HAVE_USART10 - select STM32H5_HAVE_USART11 - select STM32H5_HAVE_UART12 - select STM32H5_HAVE_SPI4 - select STM32H5_HAVE_SPI5 - select STM32H5_HAVE_SPI6 - select STM32H5_HAVE_I2C4 - select STM32H5_HAVE_USBFS - select STM32H5_HAVE_HSI48 - select STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_STM32H563XX + select STM32_HAVE_ICACHE + +config STM32_STM32H56XXX + bool + default n + select STM32_HAVE_CORDIC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART4_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART5_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART6_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART7_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART8_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_UART9 + select STM32_HAVE_USART10 + select STM32_HAVE_USART11 + select STM32_HAVE_UART12 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2C4 + select STM32_HAVE_USBFS + select STM32_HAVE_HSI48 + select STM32_HAVE_ICACHE_REMAP + +config STM32_STM32H563XX # STM32H552 and STM32H562 devices documented in RM0439 bool default n - select STM32H5_HAVE_ETHERNET - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H5 - default STM32H5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32H5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32H5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32H5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32H5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32H5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32H5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32H5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32H5_FLASH_CONFIG_B - bool - default n - depends on STM32H5_STM32H50XXX - -config STM32H5_FLASH_CONFIG_C - bool - default n - depends on STM32H5_STM32H52XXX - -config STM32H5_FLASH_CONFIG_E - bool - default n - depends on STM32H5_STM32H52XXX || STM32H5_STM32H53XXX - -config STM32H5_FLASH_CONFIG_G - bool - default n - depends on STM32H5_STM32H56XXX + select STM32_HAVE_ETHERNET -config STM32H5_FLASH_CONFIG_I - bool - default n - depends on STM32H5_STM32H56XXX || STM32H5_STM32H57XXX # Pin/package configurations config STM32H5_IO_CONFIG_K + # Package designator K bool default n config STM32H5_IO_CONFIG_T + # Package designator T bool default n config STM32H5_IO_CONFIG_C + # Package designator C bool default n config STM32H5_IO_CONFIG_R + # Package designator R bool default n config STM32H5_IO_CONFIG_J + # Package designator J bool default n config STM32H5_IO_CONFIG_M + # Package designator M bool default n config STM32H5_IO_CONFIG_V + # Package designator V bool default n config STM32H5_IO_CONFIG_Q + # Package designator Q bool default n config STM32H5_IO_CONFIG_Z + # Package designator Z bool default n config STM32H5_IO_CONFIG_A + # Package designator A bool default n comment "STM32H5 SRAM2 Options" -config STM32H5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32H5_SRAM2_INIT - -config STM32H5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - If the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32H5_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -comment "STM32H5 Peripherals" - -menu "STM32H5 Peripheral Selection" - -# These "hidden" settings determine if a peripheral option is available -# for the selected MCU - -config STM32H5_HAVE_ETHERNET - bool - default n - -config STM32H5_HAVE_PHY_POLLED - bool - default n - -config STM32H5_HAVE_FDCAN1 - bool - default n - -config STM32H5_HAVE_FDCAN2 - bool - default n - -config STM32H5_HAVE_HSI48 - bool - default n - -config STM32H5_HAVE_ICACHE - bool - default n - -config STM32H5_HAVE_I2C4 - bool - default n - -config STM32H5_HAVE_LPUART1 - bool - default n - -config STM32H5_HAVE_SPI5 - bool - default n - -config STM32H5_HAVE_SPI6 - bool - default n - -config STM32H5_HAVE_USART1 - bool - default n - -config STM32H5_HAVE_USART2 - bool - default n - -config STM32H5_HAVE_USART3 - bool - default n - -config STM32H5_HAVE_UART4 - bool - default n - -config STM32H5_HAVE_UART5 - bool - default n - -config STM32H5_HAVE_USART6 - bool - default n - -config STM32H5_HAVE_UART7 - bool - default n - -config STM32H5_HAVE_UART8 - bool - default n - -config STM32H5_HAVE_UART9 - bool - default n - -config STM32H5_HAVE_USART10 - bool - default n - -config STM32H5_HAVE_USART11 - bool - default n - -config STM32H5_HAVE_UART12 - bool - default n - -config STM32H5_HAVE_USBFS - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H5_ADC - bool - default n - -config STM32H5_DMA - bool - default n - -config STM32H5_FDCAN - bool - default n - -config STM32H5_PWM - bool - default n - -config STM32H5_SPI - bool - default n - -config STM32H5_SPI_DMA - bool - default n - -config STM32H5_TIM - bool - default n - -config STM32H5_USART - bool - default n - -# These are the peripheral selections proper - -config STM32H5_ADC1 - bool "ADC1" - default n - select STM32H5_ADC - -config STM32H5_ADC2 - bool "ADC2" - default n - select STM32H5_ADC - -config STM32H5_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -config STM32H5_DMA1 - bool "DMA1" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DMA2 - bool "DMA2" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DTS - bool "DTS" - default n - ---help--- - Enable support for the on‑die digital temperature sensor (DTS) - built into STM32H5 devices. When enabled, the driver will register - a `/dev/sensor_tempX` device using the common NuttX sensor framework. - -config STM32H5_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H5_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H5_HAVE_PHY_POLLED - -config STM32H5_FDCAN1 - bool "FDCAN1" - default n - depends on STM32H5_HAVE_FDCAN1 - select STM32H5_FDCAN - -config STM32H5_FDCAN2 - bool "FDCAN2" - default n - depends on STM32H5_HAVE_FDCAN2 - select STM32H5_FDCAN - -config STM32H5_ICACHE - bool "ICACHE" - default n - depends on STM32H5_HAVE_ICACHE - -config STM32H5_QSPI1 - bool "QSPI1" - default n - -menu "U[S]ART/LPUART Selection" - -config STM32H5_UART4 - bool "UART4" - default n - depends on STM32H5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART5 - bool "UART5" - default n - depends on STM32H5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART7 - bool "UART7" - default n - depends on STM32H5_HAVE_UART7 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART8 - bool "UART8" - default n - depends on STM32H5_HAVE_UART8 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART9 - bool "UART9" - default n - depends on STM32H5_HAVE_UART9 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART12 - bool "UART12" - default n - depends on STM32H5_HAVE_UART12 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART1 - bool "USART1" - default n - depends on STM32H5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART2 - bool "USART2" - default n - depends on STM32H5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART3 - bool "USART3" - default n - depends on STM32H5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART6 - bool "USART6" - default n - depends on STM32H5_HAVE_USART6 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART10 - bool "USART10" - default n - depends on STM32H5_HAVE_USART10 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART11 - bool "USART11" - default n - depends on STM32H5_HAVE_USART11 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_LPUART1 - bool "LPUART1" - default n - depends on STM32H5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -endmenu # U[S]ART/LPUART Selection - -menu "I2C Selection" - -config STM32H5_I2C - bool - default n - -config STM32H5_I2C1 - bool "I2C1" - default n - select STM32H5_I2C - -config STM32H5_I2C2 - bool "I2C2" - default n - select STM32H5_I2C - -config STM32H5_I2C3 - bool "I2C3" - default n - select STM32H5_I2C - -config STM32H5_I2C4 - bool "I2C4" - default n - depends on STM32H5_HAVE_I2C4 - select STM32H5_I2C - -endmenu # I2C Selection - -menu "SPI Selection" - -config STM32H5_SPI1 - bool "SPI1" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI2 - bool "SPI2" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI3 - bool "SPI3" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI4 - bool "SPI4" - default n - depends on STM32H5_HAVE_SPI4 - select SPI - select STM32H5_SPI - -config STM32H5_SPI5 - bool "SPI5" - default n - depends on STM32H5_HAVE_SPI5 - select SPI - select STM32H5_SPI - -config STM32H5_SPI6 - bool "SPI6" - default n - depends on STM32H5_HAVE_SPI6 - select SPI - select STM32H5_SPI - -endmenu # SPI Selection - -menu "STM32H5 Timer Selection" - -config STM32H5_TIM1 - bool "TIM1" - default n - select STM32H5_TIM - -config STM32H5_TIM2 - bool "TIM2" - default n - select STM32H5_TIM - -config STM32H5_TIM3 - bool "TIM3" - default n - select STM32H5_TIM - -config STM32H5_TIM4 - bool "TIM4" - default n - select STM32H5_TIM - -config STM32H5_TIM5 - bool "TIM5" - default n - select STM32H5_TIM - -config STM32H5_TIM6 - bool "TIM6" - default n - select STM32H5_TIM - -config STM32H5_TIM7 - bool "TIM7" - default n - select STM32H5_TIM - -config STM32H5_TIM8 - bool "TIM8" - default n - select STM32H5_TIM - -config STM32H5_TIM12 - bool "TIM12" - default n - select STM32H5_TIM - -config STM32H5_TIM13 - bool "TIM13" - default n - select STM32H5_TIM - -config STM32H5_TIM14 - bool "TIM14" - default n - select STM32H5_TIM - -config STM32H5_TIM15 - bool "TIM15" - default n - select STM32H5_TIM - -config STM32H5_TIM16 - bool "TIM16" - default n - select STM32H5_TIM - -config STM32H5_TIM17 - bool "TIM17" - default n - select STM32H5_TIM - -endmenu # STM32H5 Timer Selection - -choice STM32H5_USBFS_MODE - prompt "USB FS Mode" - depends on STM32H5_HAVE_USBFS - default STM32H5_USBFS_NONE - ---help--- - Select the operating mode for the USB_DRD_FS peripheral. - The hardware supports Device or Host, but not simultaneously. - -config STM32H5_USBFS_NONE - bool "Disabled" - -config STM32H5_USBFS - bool "USB Device" - select USBDEV - -config STM32H5_USBFS_HOST - bool "USB Host" - select USBHOST_HAVE_ASYNCH - select USBHOST - ---help--- - Enable USB host mode for USB_DRD_FS peripheral. - -endchoice - -endmenu # STM32H5 Peripheral Selection - -menu "DTS Configuration" - depends on STM32H5_DTS - -config STM32H5_DTS_REFCLK_LSE - bool "Use LSE (32.768 kHz crystal) as DTS reference clock" - default n - ---help--- - Select the low‑speed external (LSE) oscillator as the reference clock - for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will - measure FM(T) pulses over N LSE cycles. - - If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference - (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the - calibration prescaler ≤ 1 MHz. - -config STM32H5_DTS_SMP_TIME - int "DTS sampling time (TS1_SMP_TIME[3:0])" - default 1 - range 1 15 - ---help--- - Number of reference‑clock cycles (PCLK or LSE) counted per - DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). - -config STM32H5_DTS_TRIGGER - int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" - default 0 - ---help--- - If non‑zero, DTS will start measurements on the rising edge of - the selected hardware line. Values match RM0481 Table 275: - 0=Software Trigger, 1=LPTIM1_CH1,  - 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. - -config STM32H5_DTS_LOW_THRESHOLD - int "DTS low‑threshold (°C)" - default 0 - ---help--- - The temperature (in whole °C) below which the DTS window comparator will - assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0. - -config STM32H5_DTS_HIGH_THRESHOLD - int "DTS high‑threshold (°C)" - default 100 - ---help--- - The temperature (in whole °C) above which the DTS window comparator will - assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. - -config STM32H5_DTS_ITEN_ITEF - bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)" - default y - ---help--- - Enable the synchronous “end of measurement” interrupt for the - digital temperature sensor. When set, the driver will attach - and unmask TS1_ITEF and will call your ISR on every fresh sample. - -config STM32H5_DTS_ITEN_ITLF - bool "Enable DTS low‑threshold interrupt (TS1_ITLF)" - default n - ---help--- - Enable the synchronous “low threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITLF so you can get notified whenever the measured value - drops below your programmed low‑threshold. - -config STM32H5_DTS_ITEN_ITHF - bool "Enable DTS high‑threshold interrupt (TS1_ITHF)" - default n - ---help--- - Enable the synchronous “high threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITHF so you can get notified whenever the measured value - exceeds your programmed high‑threshold. - -config STM32H5_DTS_AITEN_AITEF - bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous end‑of‑measurement interrupt. This will - set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup - event when a conversion completes (in Stop/Sleep modes). - -config STM32H5_DTS_AITEN_AITLF - bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous low‑threshold comparator interrupt. This - will set TS1_AITLEN in DTS_ITENR and generate a wakeup event - when the measurement drops below your low threshold. - -config STM32H5_DTS_AITEN_AITHF - bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous high‑threshold comparator interrupt. This - will set TS1_AITHEN in DTS_ITENR and generate a wakeup event - when the measurement exceeds your high threshold. - -endmenu # DTS Configuration - -config STM32H5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -menu "ICACHE Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_MONITOR_EN - bool "Enable ICACHE Hit/Miss Counters" - default n - -config STM32H5_ICACHE_DIRECT - bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" - default n - -menu "ICACHE Interrupt Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_INV_INT - bool "Enable interrupts on full invalidation completion." - default n - -config STM32H5_ICACHE_ERR_INT - bool "Enable interrupts on occurrences of cache errors." - default n - -endmenu # ICACHE Interrupt Configuration - -menu "ICACHE Region Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_REGION0 - bool "Enable Configuration of ICACHE Region 0" - default n - -config STM32H5_ICACHE_REGION1 - bool "Enable Configuration of ICACHE Region 1" - default n - -config STM32H5_ICACHE_REGION2 - bool "Enable Configuration of ICACHE Region 2" - default n - -config STM32H5_ICACHE_REGION3 - bool "Enable Configuration of ICACHE Region 3" - default n - -menu "Region 0 Configuration" - depends on STM32H5_ICACHE_REGION0 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION0_BADDR - hex "ICACHE Region 0 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 0. - -config STM32H5_ICACHE_REGION0_RSIZE - int "ICACHE Region 0 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set the size of Region 0. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION0_REMAPADDR - hex "ICACHE Region 0 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [31:21] of ICACHE Region 0 Remap Address.. - -config STM32H5_ICACHE_REGION0_MSTSEL - int "ICACHE Region 0 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select ICACHE Region 0 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION0_HBURST - int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 0 Configuration - -menu "Region 1 Configuration" - depends on STM32H5_ICACHE_REGION1 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION1_BADDR - hex "ICACHE Region 1 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 1. - -config STM32H5_ICACHE_REGION1_RSIZE - int "ICACHE Region 1 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set the size of Region 1. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION1_REMAPADDR - hex "ICACHE Region 1 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [31:21] of ICACHE Region 1 Remap Address.. - -config STM32H5_ICACHE_REGION1_MSTSEL - int "ICACHE Region 1 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select ICACHE Region 1 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION1_HBURST - int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 1 Configuration - -menu "Region 2 Configuration" - depends on STM32H5_ICACHE_REGION2 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION2_BADDR - hex "ICACHE Region 2 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 2. - -config STM32H5_ICACHE_REGION2_RSIZE - int "ICACHE Region 2 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set the size of Region 2. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION2_REMAPADDR - hex "ICACHE Region 2 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [31:21] of ICACHE Region 2 Remap Address.. - -config STM32H5_ICACHE_REGION2_MSTSEL - int "ICACHE Region 2 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select ICACHE Region 2 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION2_HBURST - int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 2 Configuration - -menu "Region 3 Configuration" - depends on STM32H5_ICACHE_REGION3 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION3_BADDR - hex "ICACHE Region 3 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 3. - -config STM32H5_ICACHE_REGION3_RSIZE - int "ICACHE Region 3 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set the size of Region 3. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION3_REMAPADDR - hex "ICACHE Region 3 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [31:21] of ICACHE Region 3 Remap Address.. - -config STM32H5_ICACHE_REGION3_MSTSEL - int "ICACHE Region 3 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select ICACHE Region 3 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION3_HBURST - int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 3 Configuration - -endmenu # ICACHE Region Configuration - -endmenu # ICACHE Configuration - -config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "ADC Configuration" - depends on STM32H5_ADC - -config STM32H5_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H5_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32H5_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC1_DMA - bool "ADC1 DMA Enable" - depends on STM32H5_ADC1 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC1_DMA_CFG - bool "ADC1 DMA configuration" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default n - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32H5_ADC1_OVERSAMPLE - bool "Enable ADC1 hardware oversampling support" - depends on STM32H5_ADC1 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC1_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC1_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_WDG1 - bool "Enable STM32H5 ADC1 Watchdog 1" - depends on STM32H5_ADC1 - default n - ---help--- - Enable STM32H5 ADC1 Watchdog 1. - -config STM32H5_ADC1_WDG1_FLT - int "Set ADC1 Watchdog 1 Filter" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC1_WDG1_LOWTHRESH - int "Set ADC1 Watchdog 1 Low Threshold" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC1_WDG1_HIGHTHRESH - int "Set ADC1 Watchdog 1 High Threshold" - depends on STM32H5_ADC1_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC1_WDG1_SGL - bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" - depends on STM32H5_ADC1_WDG1 - default n - ---help--- - This option determines if ADC1 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC1_WDG1_CHAN - int "STM32H5 ADC1 Watchdog 1 Channel Selection" - depends on STM32H5_ADC1_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC1 Watchdog 1. - -config STM32H5_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32H5_ADC2 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC2_DMA - bool "ADC2 DMA Enable" - depends on STM32H5_ADC2 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H5_ADC2 && STM32H5_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32H5_ADC2_DMA && STM32H5_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32H5_ADC2_OVERSAMPLE - bool "Enable ADC2 hardware oversampling support" - depends on STM32H5_ADC2 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC2_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC2_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_WDG1 - bool "Enable STM32H5 ADC2 Watchdog 1" - depends on STM32H5_ADC2 - default n - ---help--- - Enable STM32H5 ADC2 Watchdog 1. - -config STM32H5_ADC2_WDG1_FLT - int "Set ADC2 Watchdog 1 Filter" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC2_WDG1_LOWTHRESH - int "Set ADC2 Watchdog 1 Low Threshold" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC2_WDG1_HIGHTHRESH - int "Set ADC2 Watchdog 1 High Threshold" - depends on STM32H5_ADC2_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC2_WDG1_SGL - bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" - depends on STM32H5_ADC2_WDG1 - default n - ---help--- - This option determines if ADC2 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC2_WDG1_CHAN - int "STM32H5 ADC2 Watchdog 1 Channel Selection" - depends on STM32H5_ADC2_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC2 Watchdog 1. - -endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32H5_SPI - -config STM32H5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be too high in - the interrupt driven case. - -config STM32H5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H5_SPI1 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H5_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H5_SPI2 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H5_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H5_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H5_SPI3 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H5_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H5_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H5_SPI4 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H5_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H5_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H5_SPI5 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H5_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H5_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H5_SPI6 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H5_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H5_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H5_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H5_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H5_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H5_TIM1 - select STM32H5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM1_PWM - -config STM32H5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H5_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM1_CHANNEL6 - -config STM32H5_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM1_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM1_CHANNEL = 1 - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 1 - -if STM32H5_TIM1_CHANNEL = 2 - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 2 - -if STM32H5_TIM1_CHANNEL = 3 - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 3 - -if STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM1_PWM - -config STM32H5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H5_TIM2 - select STM32H5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM2_PWM - -config STM32H5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM2_CHANNEL4 - -config STM32H5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM2_CHANNEL = 1 - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL = 1 - -if STM32H5_TIM2_CHANNEL = 2 - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL = 2 - -if STM32H5_TIM2_CHANNEL = 3 - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL = 3 - -if STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM2_PWM - -config STM32H5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H5_TIM3 - select STM32H5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM3_PWM - -config STM32H5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM3_CHANNEL4 - -config STM32H5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM3_CHANNEL = 1 - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL = 1 - -if STM32H5_TIM3_CHANNEL = 2 - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL = 2 - -if STM32H5_TIM3_CHANNEL = 3 - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL = 3 - -if STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM3_PWM - -config STM32H5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H5_TIM4 - select STM32H5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM4_PWM - -config STM32H5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM4_CHANNEL4 - -config STM32H5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM4_CHANNEL = 1 - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL = 1 - -if STM32H5_TIM4_CHANNEL = 2 - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL = 2 - -if STM32H5_TIM4_CHANNEL = 3 - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL = 3 - -if STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM4_PWM - -config STM32H5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H5_TIM5 - select STM32H5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM5_PWM - -config STM32H5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM5_CHANNEL4 - -config STM32H5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM5_CHANNEL = 1 - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL = 1 - -if STM32H5_TIM5_CHANNEL = 2 - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL = 2 - -if STM32H5_TIM5_CHANNEL = 3 - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL = 3 - -if STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM5_PWM - -config STM32H5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H5_TIM8 - select STM32H5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM8_PWM - -config STM32H5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H5_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H5_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM8_CHANNEL6 - -config STM32H5_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM8_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM8_CHANNEL = 1 - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 1 - -if STM32H5_TIM8_CHANNEL = 2 - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 2 - -if STM32H5_TIM8_CHANNEL = 3 - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 3 - -if STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM8_PWM - -config STM32H5_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H5_TIM12 - select STM32H5_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM12_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM12_CHANNEL2 - -config STM32H5_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM12_CHANNEL = 1 - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL = 1 - -if STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM12_PWM - -config STM32H5_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H5_TIM13 - select STM32H5_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM13_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM13_CHANNEL1 - -config STM32H5_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM13_PWM - -config STM32H5_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H5_TIM14 - select STM32H5_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM14_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM14_CHANNEL1 - -config STM32H5_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM14_PWM - -config STM32H5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H5_TIM15 - select STM32H5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM15_PWM - -config STM32H5_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H5_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM15_CHANNEL2 - -config STM32H5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM15_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM15_CHANNEL = 1 - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 1 - -if STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM15_PWM - -config STM32H5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H5_TIM16 - select STM32H5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM16_PWM - -config STM32H5_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H5_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM16_CHANNEL1 - -config STM32H5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM16_PWM - -config STM32H5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H5_TIM17 - select STM32H5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM17_PWM - -config STM32H5_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H5_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM17_CHANNEL1 - -config STM32H5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM17_PWM - -config STM32H5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H5_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H5_TIM1 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H5_TIM8 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H5_TIM8_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM8_PULSECOUNT -config STM32H5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H5_TIM1 && STM32H5_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H5_TIM1_ADC1 - depends on STM32H5_TIM1_ADC - -config STM32H5_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H5_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -endchoice - -config STM32H5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H5_TIM2 && STM32H5_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H5_TIM2_ADC1 - depends on STM32H5_TIM2_ADC - -config STM32H5_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H5_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -endchoice - -config STM32H5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H5_TIM3 && STM32H5_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H5_TIM3_ADC1 - depends on STM32H5_TIM3_ADC - -config STM32H5_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H5_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -endchoice - -config STM32H5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H5_TIM4 && STM32H5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H5_TIM4_ADC1 - depends on STM32H5_TIM4_ADC - -config STM32H5_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H5_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -endchoice - -config STM32H5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H5_TIM6 && STM32H5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H5_TIM6_ADC1 - depends on STM32H5_TIM6_ADC - -config STM32H5_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H5_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -endchoice - -config STM32H5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H5_TIM8 && STM32H5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H5_TIM8_ADC1 - depends on STM32H5_TIM8_ADC - -config STM32H5_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H5_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -endchoice - -config STM32H5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H5_TIM15 && STM32H5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H5_TIM15_ADC1 - depends on STM32H5_TIM15_ADC - -config STM32H5_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H5_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -endchoice - -config STM32H5_HAVE_ADC1_TIMER - bool - -config STM32H5_HAVE_ADC2_TIMER - bool - -config STM32H5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32H5_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32H5_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32H5_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32H5_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32H5_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32H5_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32H5_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32H5_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM15_CAP - bool "TIM15 Capture" - default n - depends on STM32H5_TIM15 - ---help--- - Reserve timer 15 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM16_CAP - bool "TIM16 Capture" - default n - depends on STM32H5_TIM16 - ---help--- - Reserve timer 16 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM17_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM17 - ---help--- - Reserve timer 17 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32H5_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H5_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H5_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H5_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H5_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H5_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H5_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H5_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H5_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H5_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H5_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H5_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H5_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H5_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H5_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H5_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H5_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H5_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H5_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H5_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H5_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H5_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H5_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H5_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H5_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H5_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H5_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H5_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H5_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H5_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H5_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H5_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H5_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H5_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H5_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H5_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H5_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H5_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H5_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H5_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H5_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H5_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H5_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H5_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H5_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H5_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H5_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H5_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H5_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H5_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H5_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H5_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H5_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H5_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H5_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H5_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H5_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H5_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H5_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H5_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H5_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H5_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H5_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H5_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H5_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H5_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H5_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H5_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H5_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H5_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H5_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H5_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H5_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H5_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H5_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H5_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H5_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H5_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H5_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H5_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H5_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H5_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H5_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H5_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H5_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H5_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H5_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H5_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -comment "USB Device Configuration" - -menu "USB Full Speed Device Configuration" - depends on STM32H5_USBFS - -config STM32H5_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32H5_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -comment "USB Host Configuration" - -menu "USB Full Speed Host Configuration" - depends on STM32H5_USBFS_HOST - -config STM32H5_USBDRD_NCHANNELS - int "Number of host channels" - default 8 - range 1 8 - depends on STM32H5_USBFS_HOST - ---help--- - Number of USB host channels to use. - -config STM32H5_USBDRD_DESCSIZE - int "Descriptor buffer size" - default 128 - depends on STM32H5_USBFS_HOST - ---help--- - Size of descriptor/request buffers. - -endmenu - -config STM32H5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32H5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32H5_LPUART1_SERIALDRIVER - depends on STM32H5_LPUART1 - -config STM32H5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32H5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 RX DMA" - default n - depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - default n - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - default n - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - depends on LPUART1_RS485 - bool "Unconfigure LPUART1 DIR pin on close" - default n - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32H5_USART1_SERIALDRIVER - depends on STM32H5_USART1 - -config STM32H5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32H5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 RX DMA" - default n - depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -config USART1_UNCONFIG_DIR_ON_CLOSE - depends on USART1_RS485 - bool "Unconfigure USART1 DIR pin on close" - default n - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32H5_USART2_SERIALDRIVER - depends on STM32H5_USART2 - -config STM32H5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32H5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 RX DMA" - default n - depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - default n - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - default n - -config USART2_UNCONFIG_DIR_ON_CLOSE - depends on USART2_RS485 - bool "Unconfigure USART2 DIR pin on close" - default n - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32H5_USART3_SERIALDRIVER - depends on STM32H5_USART3 - -config STM32H5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32H5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 RX DMA" - default n - depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - default n - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - default n - -config USART3_UNCONFIG_DIR_ON_CLOSE - depends on USART3_RS485 - bool "Unconfigure USART3 DIR pin on close" - default n - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32H5_UART4_SERIALDRIVER - depends on STM32H5_UART4 - -config STM32H5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32H5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 RX DMA" - default n - depends on STM32H5_UART4 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - default n - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - default n - -config UART4_UNCONFIG_DIR_ON_CLOSE - depends on UART4_RS485 - bool "Unconfigure UART4 DIR pin on close" - default n - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32H5_UART5_SERIALDRIVER - depends on STM32H5_UART5 - -config STM32H5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32H5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 RX DMA" - default n - depends on STM32H5_UART5 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - default n - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - default n - -config UART5_UNCONFIG_DIR_ON_CLOSE - depends on UART5_RS485 - bool "Unconfigure UART5 DIR pin on close" - default n - -endif # UART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32H5_USART6_SERIALDRIVER - depends on STM32H5_USART6 - -config STM32H5_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART6 Driver Configuration - -if USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32H5_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 RX DMA" - default n - depends on STM32H5_USART6 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - default n - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - default n - -config USART6_UNCONFIG_DIR_ON_CLOSE - depends on USART6_RS485 - bool "Unconfigure USART6 DIR pin on close" - default n - -endif # USART6_SERIALDRIVER - -if UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32H5_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 RX DMA" - default n - depends on STM32H5_UART7 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - default n - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - default n - -config UART7_UNCONFIG_DIR_ON_CLOSE - depends on UART7_RS485 - bool "Unconfigure UART7 DIR pin on close" - default n - -endif # UART7_SERIALDRIVER - -if UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32H5_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 RX DMA" - default n - depends on STM32H5_UART8 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - default n - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - default n - -config UART8_UNCONFIG_DIR_ON_CLOSE - depends on UART8_RS485 - bool "Unconfigure UART8 DIR pin on close" - default n - -endif # UART8_SERIALDRIVER - -if UART9_SERIALDRIVER - -config UART9_RS485 - bool "RS-485 on UART9" - default n - depends on STM32H5_UART9 - ---help--- - Enable RS-485 interface on UART9. Your board config will have to - provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be - used with UART9_RXDMA. - -config UART9_RS485_DIR_POLARITY - int "UART9 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART9_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART9_RXDMA - bool "UART9 RX DMA" - default n - depends on STM32H5_UART9 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - default n - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - default n - -config UART9_UNCONFIG_DIR_ON_CLOSE - depends on UART9_RS485 - bool "Unconfigure UART9 DIR pin on close" - default n - -endif # UART9_SERIALDRIVER - -if USART10_SERIALDRIVER - -config USART10_RS485 - bool "RS-485 on USART10" - default n - depends on STM32H5_USART10 - ---help--- - Enable RS-485 interface on USART10. Your board config will have to - provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be - used with USART10_RXDMA. - -config USART10_RS485_DIR_POLARITY - int "USART10 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART10_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART10_RXDMA - bool "USART10 RX DMA" - default n - depends on STM32H5_USART10 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - default n - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - default n - -config USART10_UNCONFIG_DIR_ON_CLOSE - depends on USART10_RS485 - bool "Unconfigure USART10 DIR pin on close" - default n - -endif # USART10_SERIALDRIVER - -if USART11_SERIALDRIVER - -config USART11_RS485 - bool "RS-485 on USART11" - default n - depends on STM32H5_USART11 - ---help--- - Enable RS-485 interface on USART11. Your board config will have to - provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be - used with USART11_RXDMA. - -config USART11_RS485_DIR_POLARITY - int "USART11 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART11_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART11_RXDMA - bool "USART11 RX DMA" - default n - depends on STM32H5_USART11 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - default n - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - default n - -config USART11_UNCONFIG_DIR_ON_CLOSE - depends on USART11_RS485 - bool "Unconfigure USART11 DIR pin on close" - default n - -endif # USART11_SERIALDRIVER - -if UART12_SERIALDRIVER - -config UART12_RS485 - bool "RS-485 on UART12" - default n - depends on STM32H5_UART12 - ---help--- - Enable RS-485 interface on UART12. Your board config will have to - provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be - used with UART12_RXDMA. - -config UART12_RS485_DIR_POLARITY - int "UART12 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART12_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART12_RXDMA - bool "UART12 RX DMA" - default n - depends on STM32H5_UART12 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - default n - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - default n - -config UART12_UNCONFIG_DIR_ON_CLOSE - depends on UART12_RS485 - bool "Unconfigure UART12 DIR pin on close" - default n - -endif # UART12_SERIALDRIVER - -if STM32H5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32H5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || USART6_RXDMA || USART10_RXDMA || \ - USART11_RXDMA || UART4_RXDMA || UART5_RXDMA || UART7_RXDMA || UART8_RXDMA || \ - UART9_RXDMA || UART12_RXDMA || LPUART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32H5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32H5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H5_USART && STM32H5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver. - -config STM32H5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H5 serial driver. - -config STM32H5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H5 serial driver. - -if PM - -config STM32H5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32H5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "Ethernet MAC Configuration" - depends on STM32H5_ETHMAC - -config STM32H5_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 0 - -config STM32H5_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. - If STM32H5_PHYINIT is defined in the configuration then the board specific logic - must provide stm32_phyinitialize(); The STM32 Ethernet driver will call this - function one time before it first uses the PHY. - -config STM32H5_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H5_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the PHY for status. - -config STM32H5_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H5_MII_EXTCLK - depends on STM32H5_MII - -config STM32H5_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MC01 to clock the MII interface. - -config STM32H5_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MC02 to clock the MII interface. - -config STM32H5_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32H5_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H5_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H5_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H5_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - default n - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32H5_ETHFD - bool "Full duplex" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H5_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H5_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H5_AUTONEG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H5_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H5_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H5_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H5_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H5_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H5_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H5_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H5_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H5_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H5_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H5_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H5_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H5_RMII - bool - default !STM32H5_MII - -choice - prompt "RMII clock configuration" - default STM32H5_RMII_EXTCLK - depends on STM32H5_RMII - -config STM32H5_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H5_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H5_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H5_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H5_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC Configuration - -menu "FDCAN driver configuration" - depends on STM32H5_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32H5_FDCAN_CHARDRIVER - -config STM32H5_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32H5_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32H5_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32H5_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32H5_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32H5_FDCAN1_ISO11898_1 - -config STM32H5_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32H5_FDCAN1_CLASSIC - -config STM32H5_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -menu "FDCAN1 Bit Timing" - -config STM32H5_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32H5_FDCAN1 is defined. - -config STM32H5_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - -config STM32H5_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 Bit Timing - -config STM32H5_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32H5_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32H5_FDCAN2_ISO11898_1 - -config STM32H5_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32H5_FDCAN2_CLASSIC - -config STM32H5_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -menu "FDCAN2 Bit Timing" - -config STM32H5_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32H5_FDCAN2 is defined. - -config STM32H5_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - -config STM32H5_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 Bit Timing - -config STM32H5_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -endmenu # FDCAN2 device driver options - -endmenu # "FDCAN driver configuration" - -menu "I2C Configuration" - depends on STM32H5_I2C - -menu "Clock Selection" - -choice - depends on STM32H5_I2C1 - prompt "I2C1 Input Clock Selection" - default STM32H5_I2C1_CLK_PCLK1 - -config STM32H5_I2C1_CLK_CSI - bool "CSI" - -config STM32H5_I2C1_CLK_HSI - bool "HSI" - -config STM32H5_I2C1_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C1_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C1 Input Clock Selection - -choice - depends on STM32H5_I2C2 - prompt "I2C2 Input Clock Selection" - default STM32H5_I2C2_CLK_PCLK1 - -config STM32H5_I2C2_CLK_CSI - bool "CSI" - -config STM32H5_I2C2_CLK_HSI - bool "HSI" - -config STM32H5_I2C2_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C2_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C2 Input Clock Selection - -choice - depends on STM32H5_I2C3 - prompt "I2C3 Input Clock Selection" - default STM32H5_I2C3_CLK_PCLK3 - -config STM32H5_I2C3_CLK_CSI - bool "CSI" - -config STM32H5_I2C3_CLK_HSI - bool "HSI" - -config STM32H5_I2C3_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C3_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C3 Input Clock Selection - -choice - depends on STM32H5_I2C4 - prompt "I2C4 Input Clock Selection" - default STM32H5_I2C4_CLK_PCLK3 - -config STM32H5_I2C4_CLK_CSI - bool "CSI" - -config STM32H5_I2C4_CLK_HSI - bool "HSI" - -config STM32H5_I2C4_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C4_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C4 Input Clock Selection - -endmenu # Clock Selection - -menu "Rise/Fall Override" - -config STM32H5_I2C1_RF_OVERRIDE - bool "I2C1" - default n - depends on STM32H5_I2C1 - -config STM32H5_I2C2_RF_OVERRIDE - bool "I2C2" - default n - depends on STM32H5_I2C2 - -config STM32H5_I2C3_RF_OVERRIDE - bool "I2C3" - default n - depends on STM32H5_I2C3 - -config STM32H5_I2C4_RF_OVERRIDE - bool "I2C4" - default n - depends on STM32H5_I2C4 - -menu "Rise/Fall Values" - -config STM32H5_I2C1_RISE - int "I2C1 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C1_FALL - int "I2C1 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C2_RISE - int "I2C2 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C2_FALL - int "I2C2 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C3_RISE - int "I2C3 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C3_FALL - int "I2C3 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C4_RISE - int "I2C4 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -config STM32H5_I2C4_FALL - int "I2C4 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -endmenu # Rise/Fall Values - -endmenu # Rise/Fall Override - -menu "Filtering" - -menu "Digital Filters" - -config STM32H5_I2C1_DNF - int "I2C1 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_DNF - int "I2C2 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_DNF - int "I2C3 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_DNF - int "I2C4 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C4 - -endmenu # Digital Filters - -menu "Analog Filters" - -config STM32H5_I2C1_ANFOFF - int "Turn off I2C1 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_ANFOFF - int "Turn off I2C2 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_ANFOFF - int "Turn off I2C3 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_ANFOFF - int "Turn off I2C4 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C4 - -endmenu # Analog Filters - -endmenu # Filtering - -config STM32H5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H5_I2C - -config STM32H5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H5_I2C - -config STM32H5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "QuadSPI Configuration" - depends on STM32H5_QSPI1 - -config STM32H5_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H5 QSPI peripheral requires the size of the Flash be specified - -config STM32H5_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 32 - ---help--- - The STM32H5 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H5_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 5 - range 1 64 - ---help--- - The STM32H5 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H5_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H5_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H5_QSPI_DMA - bool "DMA" - depends on STM32H5_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32H5_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H5_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H5_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32H5_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H5_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H5_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H5_DMA - ---help--- - 'Highest' priority. - -config STM32H5_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H5_DMA - ---help--- - 'High' priority. - -config STM32H5_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H5_DMA - ---help--- - 'Medium' priority. - -config STM32H5_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H5_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32H5_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H5_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H5_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H5_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H5_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - endif # ARCH_CHIP_STM32H5 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index ca7e9a796197c..2b6cb685043ef 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -29,7 +29,7 @@ HEAD_ASRC = include armv8-m/Make.defs -ifeq ($(CONFIG_STM32H5_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -44,7 +44,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32H5_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif @@ -52,7 +52,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H5_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif @@ -60,64 +60,64 @@ ifeq ($(CONFIG_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H5_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CHIP_CSRCS += stm32_fdcan.c endif -ifeq ($(CONFIG_STM32H5_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H5_ICACHE),y) +ifeq ($(CONFIG_STM32_ICACHE),y) CHIP_CSRCS += stm32_icache.c endif -ifeq ($(CONFIG_STM32H5_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H5_QSPI1),y) +ifeq ($(CONFIG_STM32_QSPI1),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H5_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H5_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32H5_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32_usbfs.c endif -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) +ifeq ($(CONFIG_STM32_USBFS_HOST),y) CHIP_CSRCS += stm32_usbdrdhost.c endif -ifeq ($(CONFIG_STM32H5_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif -ifeq ($(CONFIG_STM32H5_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H5_DTS),y) +ifeq ($(CONFIG_STM32_DTS),y) CHIP_CSRCS += stm32_dts.c endif -ifeq ($(CONFIG_STM32H5_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H5_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif # Required chip type specific files -ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y) +ifeq ($(CONFIG_STM32_STM32H5XXXX),y) CHIP_CSRCS += stm32h5xx_rcc.c endif diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index 7d2136db6c694..fe6c6aa3cb935 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -272,7 +272,7 @@ static const struct adc_ops_s g_adcops = # define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ CONFIG_STM32_ADC1_DMA_BATCH) -# ifdef CONFIG_STM32_ADC1_DMA_CFG +# ifdef CONFIG_STM32_ADC_H5_ADC1_DMA_CFG # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2) # else # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE) @@ -327,7 +327,7 @@ static struct stm32_dev_s g_adcpriv1 = .r_chanbuffer = g_adc1_chanbuffer, .r_dmabuffer = g_adc1_dmabuffer, .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, -# ifdef CONFIG_STM32_ADC1_DMA_CFG +# ifdef CONFIG_STM32_ADC_H5_ADC1_DMA_CFG .circular = true, # else .circular = false, diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index b327ff266f548..708809add24fc 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -387,7 +387,7 @@ static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H7_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; # ifdef CONFIG_UART7_RXDMA @@ -419,7 +419,7 @@ static char g_usart11rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H12_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static char g_uart12rxbuffer[CONFIG_UART12_RXBUFSIZE]; static char g_uart12txbuffer[CONFIG_UART12_TXBUFSIZE]; # ifdef CONFIG_UART12_RXDMA diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 1a55c06229f3e..033a384c188ba 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -33,7 +33,7 @@ #include "stm32_pwr.h" #include "stm32_flash.h" #include "stm32_rcc.h" -#include "stm32_hsi48_m0_v1.h" +#include "stm32_hsi48.h" /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig index e0838b56a45b9..875646f6c5c45 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/Kconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/Kconfig @@ -5,7 +5,7 @@ if ARCH_BOARD_NUCLEO_H563ZI -config STM32H5_USE_HSE +config STM32_USE_HSE bool "Use on-board HSE" default n ---help--- diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig index 47aa7fb2cfe23..0b0e405f95008 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,8 +49,8 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig index f5fde0ba1a74c..27f2e6708bbc3 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,13 +50,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_ADC1_DMA=y -CONFIG_STM32H5_ADC1_DMA_CFG=y -CONFIG_STM32H5_ADC1_WDG1=y -CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH=2048 -CONFIG_STM32H5_DMA1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_WDG1=y +CONFIG_STM32_ADC1_WDG1_HIGHTHRESH=2048 +CONFIG_STM32_ADC_H5_ADC1_DMA_CFG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig index 23e83ae917777..343a78089465d 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -43,9 +44,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SENSORS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_DTS=y -CONFIG_STM32H5_DTS_SMP_TIME=15 -CONFIG_STM32H5_USART3=y +CONFIG_STM32_DTS=y +CONFIG_STM32_DTS_SMP_TIME=15 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SENSORTEST=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig index d6a00523dbb80..dbd9341b0a6a0 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_FDCAN1=y -CONFIG_STM32H5_FDCAN1_FD=y -CONFIG_STM32H5_FDCAN1_LOOPBACK=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_FD=y +CONFIG_STM32_FDCAN1_LOOPBACK=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig index d2a59492c4b05..70c92e4427832 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -42,7 +43,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig index 1c47ce601a8d7..e4316e5ec38e8 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -58,9 +59,9 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig index 3b73e316f4e90..7b29390dc44db 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_TIM1=y -CONFIG_STM32H5_TIM1_CH1OUT=y -CONFIG_STM32H5_TIM1_PWM=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TIMER=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig index e2a645bc025a6..0e375794ff15f 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,9 +48,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig index 6772b433f1f1e..7d01dc6fdeeab 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -48,7 +49,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt index 7dca629677e6b..7a979d50c302b 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt +++ b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt @@ -36,15 +36,15 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile index 015b4463999df..bf97497b3048a 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile @@ -39,19 +39,19 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H5_DTS),y) +ifeq ($(CONFIG_STM32_DTS),y) CSRCS += stm32_dts.c endif -ifeq ($(CONFIG_STM32H5_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32H5_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) +ifeq ($(CONFIG_STM32_USBFS_HOST),y) CSRCS += stm32_usb.c endif From 34058184426fab8420658ad0e2b26fd112417b39 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 14/52] !arm/stm32h7: use common STM32 Kconfig symbols BREAKING CHANGE: STM32H7 Kconfig symbols were renamed from CONFIG_STM32H7_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_STM32H7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../boards/linum-stm32h753bi/index.rst | 2 +- Documentation/platforms/arm/stm32h7/index.rst | 2 +- arch/arm/include/stm32h7/chip.h | 30 +- arch/arm/include/stm32h7/irq.h | 2 +- arch/arm/src/stm32h7/CMakeLists.txt | 60 +- arch/arm/src/stm32h7/Kconfig | 6519 +---------------- arch/arm/src/stm32h7/Make.defs | 62 +- .../stm32h7/hardware/stm32h7x3xx_memorymap.h | 2 +- arch/arm/src/stm32h7/stm32_aes.h | 2 +- arch/arm/src/stm32h7/stm32_allocateheap.c | 10 +- .../arm/src/stm32h7/stm32_capture_lowerhalf.c | 2 +- arch/arm/src/stm32h7/stm32_dualcore.c | 14 +- arch/arm/src/stm32h7/stm32_dualcore.h | 4 +- arch/arm/src/stm32h7/stm32_hsem.c | 6 +- arch/arm/src/stm32h7/stm32_ltdc.h | 4 +- arch/arm/src/stm32h7/stm32_rcc.c | 16 +- arch/arm/src/stm32h7/stm32_rcc.h | 14 +- arch/arm/src/stm32h7/stm32_rptun.c | 20 +- arch/arm/src/stm32h7/stm32_start.c | 14 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 2 +- .../configs/buzzer/defconfig | 15 +- .../configs/eeprom/defconfig | 9 +- .../linum-stm32h753bi/configs/leds/defconfig | 7 +- .../configs/littlefs/defconfig | 11 +- .../linum-stm32h753bi/configs/lvgl/defconfig | 23 +- .../configs/mfrc522/defconfig | 9 +- .../configs/modbus_master/defconfig | 11 +- .../configs/modbus_slave/defconfig | 11 +- .../configs/netnsh/defconfig | 25 +- .../linum-stm32h753bi/configs/nsh/defconfig | 7 +- .../linum-stm32h753bi/configs/nxffs/defconfig | 11 +- .../configs/qencoder/defconfig | 11 +- .../linum-stm32h753bi/configs/rndis/defconfig | 11 +- .../configs/sdcard/defconfig | 11 +- .../linum-stm32h753bi/configs/sdram/defconfig | 9 +- .../configs/socketcan/defconfig | 7 +- .../linum-stm32h753bi/configs/tone/defconfig | 19 +- .../configs/usbmsc-sdcard/defconfig | 15 +- .../configs/usbnsh/defconfig | 11 +- .../configs/zmodem/defconfig | 13 +- .../linum-stm32h753bi/src/CMakeLists.txt | 6 +- .../stm32h7/linum-stm32h753bi/src/Makefile | 6 +- .../nucleo-h723zg/configs/netnsh/defconfig | 27 +- .../nucleo-h723zg/configs/nsh/defconfig | 9 +- .../nucleo-h723zg/configs/oa_tc6/defconfig | 11 +- .../stm32h7/nucleo-h723zg/src/CMakeLists.txt | 4 +- boards/arm/stm32h7/nucleo-h723zg/src/Makefile | 4 +- .../nucleo-h743zi/configs/capture/defconfig | 7 +- .../nucleo-h743zi/configs/composite/defconfig | 9 +- .../nucleo-h743zi/configs/elf/defconfig | 5 +- .../configs/mcuboot-app/defconfig | 21 +- .../configs/mcuboot-loader/defconfig | 5 +- .../nucleo-h743zi/configs/netnsh/defconfig | 23 +- .../nucleo-h743zi/configs/nsh/defconfig | 3 +- .../configs/nxboot-app/defconfig | 5 +- .../configs/nxboot-loader/defconfig | 5 +- .../configs/nxlines_oled/defconfig | 5 +- .../configs/otg_fs_host/defconfig | 7 +- .../nucleo-h743zi/configs/pwm/defconfig | 31 +- .../nucleo-h743zi/configs/rndis/defconfig | 7 +- .../stm32h7/nucleo-h743zi/src/CMakeLists.txt | 6 +- boards/arm/stm32h7/nucleo-h743zi/src/Makefile | 6 +- .../nucleo-h743zi2/configs/jumbo/defconfig | 27 +- .../nucleo-h743zi2/configs/netnsh/defconfig | 23 +- .../nucleo-h743zi2/configs/nsh/defconfig | 3 +- .../nucleo-h743zi2/configs/pysim/defconfig | 53 +- .../configs/socketcan/defconfig | 7 +- .../stm32h7/nucleo-h743zi2/src/CMakeLists.txt | 2 +- .../arm/stm32h7/nucleo-h743zi2/src/Makefile | 2 +- boards/arm/stm32h7/nucleo-h745zi/Kconfig | 2 +- .../nucleo-h745zi/configs/nsh_cm4/defconfig | 3 +- .../configs/nsh_cm4_rptun/defconfig | 1 + .../nucleo-h745zi/configs/nsh_cm7/defconfig | 3 +- .../configs/nsh_cm7_rptun/defconfig | 3 +- .../nucleo-h745zi/configs/pysim_cm7/defconfig | 53 +- .../arm/stm32h7/nucleo-h745zi/include/board.h | 2 +- .../stm32h7/nucleo-h745zi/scripts/flash.ld | 4 +- .../stm32h7/nucleo-h745zi/scripts/flash_m4.ld | 6 +- boards/arm/stm32h7/nucleo-h745zi/src/Makefile | 2 +- .../nucleo-h745zi/src/stm32_autoleds.c | 2 +- .../stm32h7/nucleo-h745zi/src/stm32_bringup.c | 6 +- .../nucleo-h753zi/configs/crypto/defconfig | 5 +- .../nucleo-h753zi/configs/jumbo/defconfig | 23 +- .../nucleo-h753zi/configs/netnsh/defconfig | 23 +- .../nucleo-h753zi/configs/nsh/defconfig | 3 +- .../nucleo-h753zi/configs/pysim/defconfig | 53 +- .../nucleo-h753zi/configs/socketcan/defconfig | 7 +- .../stm32h7/nucleo-h753zi/src/CMakeLists.txt | 2 +- boards/arm/stm32h7/nucleo-h753zi/src/Makefile | 2 +- .../openh743i/configs/composite_fs/defconfig | 7 +- .../openh743i/configs/composite_hs/defconfig | 11 +- .../stm32h7/openh743i/configs/nsh/defconfig | 3 +- .../configs/usbdev_hs_host_fs/defconfig | 13 +- .../arm/stm32h7/openh743i/src/CMakeLists.txt | 2 +- boards/arm/stm32h7/openh743i/src/Makefile | 2 +- .../portenta-h7/configs/jumbo_cm7/defconfig | 7 +- .../portenta-h7/configs/nsh_cm7/defconfig | 3 +- .../arm/stm32h7/portenta-h7/include/board.h | 2 +- .../arm/stm32h7/portenta-h7/scripts/flash.ld | 4 +- .../stm32h7/portenta-h7/scripts/flash_m4.ld | 6 +- .../stm32h7/portenta-h7/src/stm32_autoleds.c | 2 +- .../stm32h745i-disco/configs/lvgl/defconfig | 27 +- .../stm32h745i-disco/configs/netnsh/defconfig | 29 +- .../stm32h745i-disco/configs/nsh/defconfig | 9 +- .../configs/nsh_cm4/defconfig | 7 +- .../configs/nsh_cm4_rptun/defconfig | 5 +- .../configs/nsh_cm7/defconfig | 7 +- .../configs/nsh_cm7_rptun/defconfig | 7 +- .../configs/touchtest/defconfig | 11 +- .../stm32h7/stm32h745i-disco/scripts/flash.ld | 6 +- .../stm32h745i-disco/scripts/flash_m4.ld | 6 +- .../stm32h745i-disco/src/CMakeLists.txt | 4 +- .../arm/stm32h7/stm32h745i-disco/src/Makefile | 4 +- .../stm32h745i-disco/src/stm32_bringup.c | 6 +- .../stm32h747i-disco/configs/nsh/defconfig | 5 +- .../stm32h747i-disco/src/CMakeLists.txt | 6 +- .../arm/stm32h7/stm32h747i-disco/src/Makefile | 6 +- .../stm32h750b-dk/configs/lvgl/defconfig | 23 +- .../stm32h7/stm32h750b-dk/scripts/flash.ld | 6 +- .../stm32h7/stm32h750b-dk/scripts/flash_m4.ld | 6 +- .../stm32h7/stm32h750b-dk/src/CMakeLists.txt | 4 +- boards/arm/stm32h7/stm32h750b-dk/src/Makefile | 4 +- .../stm32h7/stm32h750b-dk/src/stm32_bringup.c | 6 +- .../weact-stm32h743/configs/nsh/defconfig | 3 +- .../weact-stm32h743/configs/sdcard/defconfig | 9 +- .../weact-stm32h743/configs/st7735/defconfig | 5 +- .../weact-stm32h743/configs/usbnsh/defconfig | 7 +- .../weact-stm32h743/src/CMakeLists.txt | 2 +- .../arm/stm32h7/weact-stm32h743/src/Makefile | 2 +- .../weact-stm32h750/configs/nsh/defconfig | 3 +- .../weact-stm32h750/configs/sdcard/defconfig | 9 +- .../weact-stm32h750/configs/st7735/defconfig | 5 +- .../weact-stm32h750/configs/usbnsh/defconfig | 7 +- .../weact-stm32h750/src/CMakeLists.txt | 6 +- .../arm/stm32h7/weact-stm32h750/src/Makefile | 2 +- 135 files changed, 1063 insertions(+), 6820 deletions(-) diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index bcba3e81df6da..0adfaf5562541 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -721,7 +721,7 @@ After that check if your PC recognized the usb driver:: [27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk [27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. -**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c +**OBS:** This example disable the macro CONFIG_STM32_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c netnsh ------ diff --git a/Documentation/platforms/arm/stm32h7/index.rst b/Documentation/platforms/arm/stm32h7/index.rst index b042e33c30ce5..61e1f4387be2a 100644 --- a/Documentation/platforms/arm/stm32h7/index.rst +++ b/Documentation/platforms/arm/stm32h7/index.rst @@ -114,7 +114,7 @@ The selection of the core for which the image is build is made using options: - ``CONFIG_ARCH_CHIP_STM32H7_CORTEXM4`` - selects Cortex-M4 core Support for the CM7 core is always enabled, support for the CM4 core is controlled -with the ``CONFIG_STM32H7_CORTEXM4_ENABLED`` option. +with the ``CONFIG_STM32_CORTEXM4_ENABLED`` option. Interprocessor communication between cores is realized with the NuttX RPTUN device based on the OpenAMP framework. ``HSEM`` is used for synchronization and diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 08492c3184b25..841d6a506a878 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -122,20 +122,20 @@ /* Peripherals */ -# if defined(CONFIG_STM32_IO_CONFIG_A) +# if defined(CONFIG_STM32H7_IO_CONFIG_A) # define STM32_NGPIO (10) /* GPIOA-GPIOJ */ -# elif defined(CONFIG_STM32_IO_CONFIG_B) +# elif defined(CONFIG_STM32H7_IO_CONFIG_B) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32_IO_CONFIG_I) +# elif defined(CONFIG_STM32H7_IO_CONFIG_I) # define STM32_NGPIO (9) /* GPIOA-GPIOI */ -# elif defined(CONFIG_STM32_IO_CONFIG_V) +# elif defined(CONFIG_STM32H7_IO_CONFIG_V) # define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ -# elif defined(CONFIG_STM32_IO_CONFIG_X) +# elif defined(CONFIG_STM32H7_IO_CONFIG_X) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32_IO_CONFIG_Z) +# elif defined(CONFIG_STM32H7_IO_CONFIG_Z) # define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else -# error CONFIG_STM32_IO_CONFIG_x Not Set +# error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif # define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ @@ -174,22 +174,22 @@ /* Peripherals */ -# if defined(CONFIG_STM32_IO_CONFIG_A) +# if defined(CONFIG_STM32H7_IO_CONFIG_A) # define STM32_NGPIO (10) /* GPIOA-GPIOJ */ -# elif defined(CONFIG_STM32_IO_CONFIG_B) +# elif defined(CONFIG_STM32H7_IO_CONFIG_B) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32_IO_CONFIG_I) +# elif defined(CONFIG_STM32H7_IO_CONFIG_I) # define STM32_NGPIO (9) /* GPIOA-GPIOI */ -# elif defined(CONFIG_STM32_IO_CONFIG_L) +# elif defined(CONFIG_STM32H7_IO_CONFIG_L) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32_IO_CONFIG_V) +# elif defined(CONFIG_STM32H7_IO_CONFIG_V) # define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ -# elif defined(CONFIG_STM32_IO_CONFIG_X) +# elif defined(CONFIG_STM32H7_IO_CONFIG_X) # define STM32_NGPIO (11) /* GPIOA-GPIOK */ -# elif defined(CONFIG_STM32_IO_CONFIG_Z) +# elif defined(CONFIG_STM32H7_IO_CONFIG_Z) # define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else -# error CONFIG_STM32_IO_CONFIG_x Not Set +# error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif # define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h index bdbdd2e214731..24cfc5f4add09 100644 --- a/arch/arm/include/stm32h7/irq.h +++ b/arch/arm/include/stm32h7/irq.h @@ -76,7 +76,7 @@ #elif defined(CONFIG_STM32_STM32H7B3XX) # include #elif defined(CONFIG_STM32_STM32H7X5XX) -# if CONFIG_ARCH_CHIP_STM32_CORTEXM7 +# if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # include # else # include diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index eb5a4218c2203..a0664d6adae66 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -35,7 +35,7 @@ list( stm32_serial.c stm32_uid.c) -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -43,7 +43,7 @@ if(CONFIG_ARCH_STM32H7_DUALCORE) list(APPEND SRCS stm32_dualcore.c) endif() -if(CONFIG_STM32H7_HSEM) +if(CONFIG_STM32_HSEM) list(APPEND SRCS stm32_hsem.c) endif() @@ -57,7 +57,7 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32H7_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) endif() @@ -73,47 +73,51 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32H7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H7_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_fdcan_sock.c) endif() -if(CONFIG_STM32H7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32H7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32H7_IWDG OR CONFIG_STM32H7_RTC_LSICLOCK) +if(CONFIG_STM32_RNG) + list(APPEND SRCS stm32_rng.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32H7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32H7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32H7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32H7_QUADSPI) +if(CONFIG_STM32_QUADSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -126,7 +130,7 @@ if(CONFIG_STM32H7_RTC) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -134,7 +138,7 @@ if(CONFIG_SPI_SLAVE) list(APPEND SRCS stm32_spi_slave.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -142,7 +146,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H7_TIMX_CAP) +if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -150,7 +154,7 @@ if(CONFIG_CAPTURE) list(APPEND SRCS stm32_capture_lowerhalf.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() @@ -169,15 +173,15 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32H7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H7_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() -if(CONFIG_STM32H7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -185,7 +189,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32H7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -204,12 +208,20 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32H7_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32H7_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() +if(CONFIG_STM32_CRYP AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_aes.c) +endif() + +if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_crypto.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 4f1c6eaaa173f..5316a69a910d1 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -7,6 +7,42 @@ if ARCH_CHIP_STM32H7 comment "STM32 H7 Configuration Options" +config STM32_H7_PERIPHERALS + bool + default y + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_HSEM + select STM32_HAVE_CSI + select STM32_HAVE_HSI48 + select STM32_HAVE_MDMA + select STM32_HAVE_BDMA + select STM32_HAVE_OTG_H7 + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_FDCAN_H7 + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 H7 Chip Selection" default ARCH_CHIP_STM32H743ZI @@ -14,34 +50,34 @@ choice config ARCH_CHIP_STM32H723VG bool "STM32H723VG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H723ZG bool "STM32H723ZG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H743AG bool "STM32H743AG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -49,8 +85,8 @@ config ARCH_CHIP_STM32H743AG config ARCH_CHIP_STM32H743AI bool "STM32H743AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -58,8 +94,8 @@ config ARCH_CHIP_STM32H743AI config ARCH_CHIP_STM32H743BG bool "STM32H743BG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -67,8 +103,8 @@ config ARCH_CHIP_STM32H743BG config ARCH_CHIP_STM32H743BI bool "STM32H743BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -76,8 +112,8 @@ config ARCH_CHIP_STM32H743BI config ARCH_CHIP_STM32H743IG bool "STM32H743IG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -85,8 +121,8 @@ config ARCH_CHIP_STM32H743IG config ARCH_CHIP_STM32H743II bool "STM32H743II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -94,8 +130,8 @@ config ARCH_CHIP_STM32H743II config ARCH_CHIP_STM32H743VG bool "STM32H743VG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -103,8 +139,8 @@ config ARCH_CHIP_STM32H743VG config ARCH_CHIP_STM32H743VI bool "STM32H743VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -112,8 +148,8 @@ config ARCH_CHIP_STM32H743VI config ARCH_CHIP_STM32H743XG bool "STM32H743XG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -121,8 +157,8 @@ config ARCH_CHIP_STM32H743XG config ARCH_CHIP_STM32H743XI bool "STM32H743XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -130,8 +166,8 @@ config ARCH_CHIP_STM32H743XI config ARCH_CHIP_STM32H743ZG bool "STM32H743ZG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -139,8 +175,8 @@ config ARCH_CHIP_STM32H743ZG config ARCH_CHIP_STM32H743ZI bool "STM32H743ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -148,8 +184,8 @@ config ARCH_CHIP_STM32H743ZI config ARCH_CHIP_STM32H745BG bool "STM32H745BG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -157,8 +193,8 @@ config ARCH_CHIP_STM32H745BG config ARCH_CHIP_STM32H745BI bool "STM32H745BI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -166,8 +202,8 @@ config ARCH_CHIP_STM32H745BI config ARCH_CHIP_STM32H745IG bool "STM32H745IG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -175,8 +211,8 @@ config ARCH_CHIP_STM32H745IG config ARCH_CHIP_STM32H745II bool "STM32H745II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -184,8 +220,8 @@ config ARCH_CHIP_STM32H745II config ARCH_CHIP_STM32H745XG bool "STM32H745XG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -193,8 +229,8 @@ config ARCH_CHIP_STM32H745XG config ARCH_CHIP_STM32H745XI bool "STM32H745XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -202,8 +238,8 @@ config ARCH_CHIP_STM32H745XI config ARCH_CHIP_STM32H745ZG bool "STM32H745ZG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -211,8 +247,8 @@ config ARCH_CHIP_STM32H745ZG config ARCH_CHIP_STM32H745ZI bool "STM32H745ZI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -220,165 +256,186 @@ config ARCH_CHIP_STM32H745ZI config ARCH_CHIP_STM32H747XI bool "STM32H747XI" - select STM32H7_STM32H7X7XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X7XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_SMPS + select STM32_HAVE_SMPS ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM TFBGA240 config ARCH_CHIP_STM32H750VB bool "STM32H750VB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100 config ARCH_CHIP_STM32H750ZB bool "STM32H750ZB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H750IB bool "STM32H750IB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176 or UFBGA176+25 config ARCH_CHIP_STM32H750XB bool "STM32H750XB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240+25 config ARCH_CHIP_STM32H753AI bool "STM32H753AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 config ARCH_CHIP_STM32H753BI bool "STM32H753BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP208 config ARCH_CHIP_STM32H753II bool "STM32H753II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H753VI bool "STM32H753VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 config ARCH_CHIP_STM32H753XI bool "STM32H753XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 config ARCH_CHIP_STM32H753ZI bool "STM32H753ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H7B3LI bool "STM32H7B3LI" - select STM32H7_STM32H7B3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7B3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_L - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_CRYP + select STM32_HAVE_SMPS + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1376 Kb SRAM, with cryptographic accelerator, TFBGA225 config ARCH_CHIP_STM32H755II bool "STM32H755II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H755XI bool "STM32H755XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 + select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART1_TXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART2_TXDMA if STM32_DMA1 + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART3_TXDMA if STM32_DMA1 + select STM32_HAVE_UART4_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART4_TXDMA if STM32_DMA1 + select STM32_HAVE_UART5_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART5_TXDMA if STM32_DMA1 + select STM32_HAVE_USART6_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_USART6_TXDMA if STM32_DMA2 + select STM32_HAVE_UART7_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART7_TXDMA if STM32_DMA1 + select STM32_HAVE_UART8_RXDMA if STM32_DMA1 || STM32_DMA2 + select STM32_HAVE_UART8_TXDMA if STM32_DMA1 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 endchoice # STM32 H7 Chip Selection -config STM32H7_HAVE_SMPS - bool - default n - -config STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - default n - -config STM32H7_PWR_DIRECT_SMPS_SUPPLY +config STM32_PWR_DIRECT_SMPS_SUPPLY bool "Use direct SMPS supply mode" - depends on STM32H7_HAVE_SMPS + depends on STM32_HAVE_SMPS default n -config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY +config STM32_PWR_EXTERNAL_SOURCE_SUPPLY bool "Use external source as power supply" default n ---help--- @@ -386,8 +443,8 @@ config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY choice prompt "STM32 H7 Power Supply Selection" - default STM32H7_PWR_DEFAULT_SUPPLY - depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY + default STM32_PWR_DEFAULT_SUPPLY + depends on STM32_HAVE_SMPS && !STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY ---help--- The STM32H7x5 and STM32H7x7 support power supply configurations for the VCORE core domain and an external supply, by configuring the SMPS step-down converter and voltage regulator. @@ -395,15 +452,15 @@ choice Currently the only supported modes are Direct SMPS supply and LDO supply. -config STM32H7_PWR_DEFAULT_SUPPLY +config STM32_PWR_DEFAULT_SUPPLY bool "Default" -config STM32H7_PWR_LDO_SUPPLY +config STM32_PWR_LDO_SUPPLY bool "Use LDO supply mode" endchoice # "STM32 H7 Power Supply Selection" -config STM32H7_PWR_IGNORE_ACTVOSRDY +config STM32_PWR_IGNORE_ACTVOSRDY bool "Ignore PWR_CSR1_ACTVOSRDY bit" default n ---help--- @@ -411,38 +468,45 @@ config STM32H7_PWR_IGNORE_ACTVOSRDY This is workaround for Renode simulation that doesn't implement this feature. config STM32H7_IO_CONFIG_A + # Package designator A bool default n config STM32H7_IO_CONFIG_B + # Package designator B bool default n config STM32H7_IO_CONFIG_I + # Package designator I bool default n config STM32H7_IO_CONFIG_L + # Package designator L bool default n config STM32H7_IO_CONFIG_V + # Package designator V bool default n config STM32H7_IO_CONFIG_X + # Package designator X bool default n config STM32H7_IO_CONFIG_Z + # Package designator Z bool default n config ARCH_STM32H7_DUALCORE bool default n - select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED - select STM32H7_HAVE_CM4 + select STM32_HSEM if !STM32_CORTEXM4_DISABLED + select STM32_HAVE_CM4 choice prompt "STM32 H7 Core selection" @@ -463,141 +527,166 @@ config ARCH_CHIP_STM32H7_CORTEXM4 endchoice # STM32 H7 Core selection -config STM32H7_STM32H7X0XX +config STM32_STM32H7X0XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X3XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7X3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7B3XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7B3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X5XX + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG + +config STM32_STM32H7X5XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_RNG - -config STM32H7_STM32H7X7XX + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_SMPS + select STM32_HAVE_RNG + +config STM32_STM32H7X7XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF - select STM32H7_HAVE_GPIOG - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF + select STM32_HAVE_GPIOG + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG # The reduced SRAM configuration STM32H72X and STM32H73X -config STM32H7_STM32H72XXX_OR_STM32H73XXX - bool - default n - -config STM32H7_FLASH_CONFIG_B +config STM32_STM32H72XXX_OR_STM32H73XXX bool default n -config STM32H7_FLASH_CONFIG_G - bool - default n - -config STM32H7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H7 - default STM32H7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H7 series parts numbering (sans the package type) ends with a - letter that designates the FLASH size. - - Designator Size in KiB - B 128 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - - If the STM32H743ZI is chosen, the Flash configuration would be - 'I', if a variant of the part is released in the future one - could simply select another designator here. - - If an STM32H7xxx Series parts is chosen the default Flash - configuration will be set herein and can be changed. - -config STM32H7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H7_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32H7_FLASH_OVERRIDE_G - bool "G 1048KiB" - -config STM32H7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" -config STM32H7_FLASH_CR_PSIZE +config STM32_FLASH_CR_PSIZE int "Flash program size width" depends on ARCH_CHIP_STM32H7 default 3 @@ -611,7 +700,7 @@ config STM32H7_FLASH_CR_PSIZE 2: 32 bits 3: 64 bits (default) -config STM32H7_AXI_SRAM_CORRUPTION_WAR +config STM32_AXI_SRAM_CORRUPTION_WAR bool "Errata 2.2.9 Reading from AXI SRAM data read corruption Workaround" default y ---help--- @@ -631,47 +720,36 @@ if ARCH_STM32H7_DUALCORE if ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM4_ENABLED +config STM32_CORTEXM4_ENABLED bool "Enable support for M4 core" default y -config STM32H7_CORTEXM7_BOOTM4 +config STM32_CORTEXM7_BOOTM4 bool "Boot M4 core" - select STM32H7_SYSCFG - default y if STM32H7_CORTEXM4_ENABLED + select STM32_SYSCFG + default y if STM32_CORTEXM4_ENABLED default n endif # ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM7_FLASH_SIZE +config STM32_CORTEXM7_FLASH_SIZE int "Flash reserved for M7 core" - default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default 2097152 -config STM32H7_CORTEXM7_SHMEM +config STM32_CORTEXM7_SHMEM bool select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7 - default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default y if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default n -config STM32H7_SHMEM_SRAM3 +config STM32_SHMEM_SRAM3 bool "Use SRAM3 as shared memory" - depends on STM32H7_CORTEXM7_SHMEM + depends on STM32_CORTEXM7_SHMEM default y endif # ARCH_STM32H7_DUALCORE -config STM32_HAVE_OTA_PARTITION - bool - default n - -config STM32H7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - menu "Application Image Configuration" choice prompt "Application Image Format" @@ -711,5945 +789,22 @@ endchoice # Application Image Format endmenu # Application Image Configuration -menu "STM32H7 Peripheral Selection" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32H7_HAVE_CM4 - bool - default n - -config STM32H7_HAVE_LTDC - bool - default n - -config STM32H7_HAVE_ETHERNET - bool - default n - -config STM32H7_HAVE_PHY_POLLED - bool - default n - -config STM32H7_HAVE_FMC - bool - default n - -config STM32H7_HAVE_GPIOF - bool - default n - -config STM32H7_HAVE_GPIOG - bool - default n - -config STM32H7_HAVE_SPI4 - bool - default n - -config STM32H7_HAVE_SPI5 - bool - default n - -config STM32H7_HAVE_SPI6 - bool - default n - -config STM32H7_HAVE_FDCAN1 - bool - default n - -config STM32H7_HAVE_FDCAN2 - bool - default n - -config STM32H7_HAVE_FDCAN3 - bool - default n - -config STM32H7_HAVE_RNG - bool - default n - -config STM32H7_HAVE_CRYP - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H7_ADC - bool - default n - -config STM32H7_FDCAN - bool - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - select NET_CAN_EXTID - select NET_CAN_HAVE_TX_DEADLINE - default n - -config STM32H7_DAC - bool - default n - -config STM32H7_DMA - bool - default n - -config STM32H7_I2C - bool - default n - -config STM32H7_SAI - bool - default n - -config STM32H7_SDMMC - bool - default n - -config STM32H7_SPI - bool - default n - -config STM32H7_SPI_DMA - bool - default n - -config STM32H7_TIM - bool - default n - -config STM32H7_LPTIM - bool - default n - -config STM32H7_HSEM - bool "Hardware semaphore" - default n - -config STM32H7_RTC - bool "RTC" - default n - select RTC - -config STM32H7_CSI - bool "CSI Low-speed internal oscillator (4MHz)" - default n - -config STM32H7_HSI48 - bool "HSI48 High-speed 48MHz internal oscillator" - default n - -config STM32H7_PWR - bool "PWR" - default n - -config STM32H7_PWM - bool - default n - -config STM32H7_USART - bool - default n - -# These are the peripheral selections proper -config STM32H7_ADC1 - bool "ADC1" - default n - select STM32H7_ADC - -config STM32H7_ADC2 - bool "ADC2" - default n - select STM32H7_ADC - -config STM32H7_ADC3 - bool "ADC3" - default n - select STM32H7_ADC - -config STM32H7_RNG - bool "RNG" - default n - depends on STM32H7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32H7_CRC - bool "CRC" - default n - -config STM32H7_CRYP - bool "CRYP" - default n - depends on STM32H7_HAVE_CRYP - -config STM32H7_BKPSRAM - bool "Enable BKP RAM Domain" - select STM32H7_PWR - default n - -config STM32H7_DMA1 - bool "DMA1" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_DMA2 - bool "DMA2" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_MDMA - bool "MDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_BDMA - bool "BDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H7_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H7_HAVE_PHY_POLLED - -config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC +config STM32_BYPASS_CLOCKCONFIG + bool "Bypass clock configuration" + depends on ARCH_STM32H7_DUALCORE + default n if ARCH_CHIP_STM32H7_CORTEXM7 + default y if ARCH_CHIP_STM32H7_CORTEXM4 ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32H7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTGHS - bool "OTG FS/HS" - default n - depends on EXPERIMENTAL - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTG_SOFOUTPUT - bool "OTG SOF output" - default n - -config STM32H7_OTG_USBREGEN - bool "Enable USB voltage regulator" - default n - -config STM32H7_QUADSPI - bool "QuadSPI" - default n - -config STM32H7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32H7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32H7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32H7_SDMMC1 - bool "SDMMC1" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_SDMMC2 - bool "SDMMC2" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32H7_WWDG - bool "WWDG" - default n - select WATCHDOG - -menu "STM32H7 FDCAN Selection" - -config STM32H7_FDCAN1 - bool "FDCAN1" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN2 - bool "FDCAN2" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN3 - bool "FDCAN3" - default n - select STM32H7_FDCAN - -endmenu # STM32H7 FDCAN Selection - -menu "STM32H7 I2C Selection" - -config STM32H7_I2C1 - bool "I2C1" - default n - select STM32H7_I2C - -config STM32H7_I2C2 - bool "I2C2" - default n - select STM32H7_I2C - -config STM32H7_I2C3 - bool "I2C3" - default n - select STM32H7_I2C - -config STM32H7_I2C4 - bool "I2C4" - default n - select STM32H7_I2C - -endmenu # STM32H7 I2C Selection + Bypass clock configuration. For dual core chips only one core + should configure clocks -config STM32H7_LTDC - bool "LTDC" +config STM32_SRAM4EXCLUDE + bool "Exclude SRAM4 from the heap" + default y if RPTUN default n - select FB - depends on STM32H7_HAVE_LTDC ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32H7 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - In some STM32H7 devices the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32H7_DSIHOST and STM32H7_LTDC_USE_DSI. - -menu "STM32H7 SPI Selection" - -config STM32H7_SPI1 - bool "SPI1" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI2 - bool "SPI2" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI3 - bool "SPI3" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI4 - bool "SPI4" - default n - depends on STM32H7_HAVE_SPI4 - select SPI - select STM32H7_SPI - -config STM32H7_SPI5 - bool "SPI5" - default n - depends on STM32H7_HAVE_SPI5 - select SPI - select STM32H7_SPI - -config STM32H7_SPI6 - bool "SPI6" - default n - depends on STM32H7_HAVE_SPI6 - select SPI - select STM32H7_SPI - -endmenu # STM32H7 SPI Selection - -config STM32H7_SYSCFG - bool "SYSCFG" - default y - -menu "STM32H7 Timer Selection" - -config STM32H7_TIM1 - bool "TIM1" - default n - select STM32H7_TIM - -config STM32H7_TIM2 - bool "TIM2" - default n - select STM32H7_TIM - -config STM32H7_TIM3 - bool "TIM3" - default n - select STM32H7_TIM - -config STM32H7_TIM4 - bool "TIM4" - default n - select STM32H7_TIM - -config STM32H7_TIM5 - bool "TIM5" - default n - select STM32H7_TIM - -config STM32H7_TIM6 - bool "TIM6" - default n - select STM32H7_TIM - -config STM32H7_TIM7 - bool "TIM7" - default n - select STM32H7_TIM - -config STM32H7_TIM8 - bool "TIM8" - default n - select STM32H7_TIM - -config STM32H7_TIM12 - bool "TIM12" - default n - select STM32H7_TIM - -config STM32H7_TIM13 - bool "TIM13" - default n - select STM32H7_TIM - -config STM32H7_TIM14 - bool "TIM14" - default n - select STM32H7_TIM - -config STM32H7_TIM15 - bool "TIM15" - default n - select STM32H7_TIM - -config STM32H7_TIM16 - bool "TIM16" - default n - select STM32H7_TIM - -config STM32H7_TIM17 - bool "TIM17" - default n - select STM32H7_TIM - -endmenu # STM32H7 Timer Selection - -menu "STM32H7 Low-power Timer Selection" - -config STM32H7_LPTIM1 - bool "LPTIM1" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM2 - bool "LPTIM2" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM3 - bool "LPTIM3" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM4 - bool "LPTIM4" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM5 - bool "LPTIM5" - default n - select STM32H7_LPTIM - -endmenu # STM32H7 Low-power Timer Selection - -menu "STM32H7 U[S]ART Selection" - -config STM32H7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32H7_USART - -config STM32H7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32H7_USART - -endmenu # STM32H7 U[S]ART Selection -endmenu # STM32H7 Peripheral Selection - -config STM32H7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - select STM32H7_CSI - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V - -menu "OTG_HS Configuration" - depends on STM32H7_OTGHS - -config STM32H7_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32H7_OTGHS_NO_ULPI - -config STM32H7_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means the OTG_HS - peripheral must use the internal full-speed PHY and will be limited to - full-speed mode. - -config STM32H7_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -menu "I2C Configuration" - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H7_I2C - -config STM32H7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "OTG Configuration" - depends on STM32H7_OTGFS || STM32H7_OTGHS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -choice - prompt "STM32H7 OTGFS role" - depends on STM32H7_OTGFS - default STM32H7_OTGFS_USBDEV if USBDEV - default STM32H7_OTGFS_HOST if !USBDEV && USBHOST - -config STM32H7_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32H7_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32H7_OTGHS - default STM32H7_OTGHS_USBDEV if USBDEV - -config STM32H7_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -menu "SPI Configuration" - depends on STM32H7_SPI - -config STM32H7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32H7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H7_SPI1 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H7_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H7_SPI2 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H7_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H7_SPI3 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H7_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H7_SPI4 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H7_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H7_SPI5 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H7_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H7_SPI6 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H7_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "U[S]ART Configuration" - depends on STM32H7_USART - -if STM32H7_USART1 - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART1 - -if STM32H7_USART2 - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART2 - -if STM32H7_USART3 - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXFIFO_THRES - int "USART3 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART3 - -if STM32H7_UART4 - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXFIFO_THRES - int "UART4 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART4 - -if STM32H7_UART5 - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXFIFO_THRES - int "UART5 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART5 - -if STM32H7_USART6 - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXFIFO_THRES - int "USART6 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART - -if STM32H7_UART7 - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXFIFO_THRES - int "UART7 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART7 - -if STM32H7_UART8 - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXFIFO_THRES - int "UART8 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART8 - -config STM32H7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H7 serial driver. - -config STM32H7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H7 serial driver. - -config STM32H7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H7 serial driver. - -if PM - -config STM32H7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32H7_ADC - -config STM32H7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H7_ADC1_DMA - bool "ADC1 DMA (not supported yet)" - depends on STM32H7_ADC1 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H7_ADC1 && STM32H7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC2_DMA - bool "ADC2 DMA (not supported yet)" - depends on STM32H7_ADC2 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H7_ADC2 && STM32H7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC3_DMA - bool "ADC3 DMA (not supported yet)" - depends on STM32H7_ADC3 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32H7_ADC3 && STM32H7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -endmenu # ADC Configuration - -menu "SD/MMC Configuration" - depends on STM32H7_SDMMC - -config STM32H7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32H7_SDMMC_IDMA - bool "Support IDMA data transfers" - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32H7_SDMMC1 - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32H7_SDMMC2 - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32H7_BKPSRAM - -config STM32H7_BBSRAM - bool "BBSRAM File Support" - default n - select ARM_MPU - -config STM32H7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32H7_BBSRAM - -config STM32H7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32H7_BBSRAM - -endif # STM32H7_BKPSRAM - -config STM32H7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32H7_RTC - -config STM32H7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32H7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32H7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32H7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32H7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the correct* values from low to high. To - avoid damaging the crystal, we want to use the lowest setting that - gets the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - *It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - - WARNING this RUN setting does not appear to work! It appears - that the LSEDRV bits cannot be changed once the OSC is running. - -endif # STM32H7_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "QuadSPI Configuration" - depends on STM32H7_QUADSPI - -config STM32H7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H7 QSPI peripheral requires the size of the Flash be specified - -config STM32H7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32H7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32H7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H7_QSPI_DMA - bool "DMA" - depends on STM32H7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice # Transfer technique - -choice - prompt "Bank selection" - default STM32H7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice # Bank selection - -choice - prompt "DMA Priority" - default STM32H7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H7_DMA - ---help--- - 'Highest' priority. - -config STM32H7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H7_DMA - ---help--- - 'High' priority. - -config STM32H7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H7_DMA - ---help--- - 'Medium' priority. - -config STM32H7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H7_DMA - ---help--- - 'Low' priority. - -endchoice # DMA Priority - -config STM32H7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu # QuadSPI Configuration - -config STM32H7_BYPASS_CLOCKCONFIG - bool "Bypass clock configuration" - depends on ARCH_STM32H7_DUALCORE - default n if ARCH_CHIP_STM32H7_CORTEXM7 - default y if ARCH_CHIP_STM32H7_CORTEXM4 - ---help--- - Bypass clock configuration. For dual core chips only one core - should configure clocks - -config STM32H7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32H7_SRAM4EXCLUDE - bool "Exclude SRAM4 from the heap" - default y if RPTUN - default n - ---help--- - Exclude SRAM4 from the HEAP in order to use this 64 KB region - for other uses, such as DMA buffers, etc. - -config STM32H7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32H7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32H7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32H7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H7_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H7_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H7_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H7_TIM1 - select STM32H7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM1_PWM - -config STM32H7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM1_CHANNEL6 - -config STM32H7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM1_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM1_CHANNEL = 1 - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 1 - -if STM32H7_TIM1_CHANNEL = 2 - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 2 - -if STM32H7_TIM1_CHANNEL = 3 - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 3 - -if STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM1_PWM - -config STM32H7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H7_TIM2 - select STM32H7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM2_PWM - -config STM32H7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM2_CHANNEL4 - -config STM32H7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM2_CHANNEL = 1 - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL = 1 - -if STM32H7_TIM2_CHANNEL = 2 - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL = 2 - -if STM32H7_TIM2_CHANNEL = 3 - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL = 3 - -if STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM2_PWM - -config STM32H7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H7_TIM3 - select STM32H7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM3_PWM - -config STM32H7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM3_CHANNEL4 - -config STM32H7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM3_CHANNEL = 1 - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL = 1 - -if STM32H7_TIM3_CHANNEL = 2 - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL = 2 - -if STM32H7_TIM3_CHANNEL = 3 - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL = 3 - -if STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM3_PWM - -config STM32H7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H7_TIM4 - select STM32H7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM4_PWM - -config STM32H7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM4_CHANNEL4 - -config STM32H7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM4_CHANNEL = 1 - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL = 1 - -if STM32H7_TIM4_CHANNEL = 2 - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL = 2 - -if STM32H7_TIM4_CHANNEL = 3 - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL = 3 - -if STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM4_PWM - -config STM32H7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H7_TIM5 - select STM32H7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM5_PWM - -config STM32H7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM5_CHANNEL4 - -config STM32H7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM5_CHANNEL = 1 - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL = 1 - -if STM32H7_TIM5_CHANNEL = 2 - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL = 2 - -if STM32H7_TIM5_CHANNEL = 3 - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL = 3 - -if STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM5_PWM - -config STM32H7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H7_TIM8 - select STM32H7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM8_PWM - -config STM32H7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM8_CHANNEL6 - -config STM32H7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM8_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM8_CHANNEL = 1 - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 1 - -if STM32H7_TIM8_CHANNEL = 2 - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 2 - -if STM32H7_TIM8_CHANNEL = 3 - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 3 - -if STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM8_PWM - -config STM32H7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H7_TIM12 - select STM32H7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM12_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM12_CHANNEL2 - -config STM32H7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM12_CHANNEL = 1 - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL = 1 - -if STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM12_PWM - -config STM32H7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H7_TIM13 - select STM32H7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM13_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM13_CHANNEL1 - -config STM32H7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM13_PWM - -config STM32H7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H7_TIM14 - select STM32H7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM14_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM14_CHANNEL1 - -config STM32H7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM14_PWM - -config STM32H7_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H7_TIM15 - select STM32H7_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM15_PWM - -config STM32H7_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H7_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM15_CHANNEL2 - -config STM32H7_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM15_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM15_CHANNEL = 1 - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 1 - -if STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM15_PWM - -config STM32H7_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H7_TIM16 - select STM32H7_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM16_PWM - -config STM32H7_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H7_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM16_CHANNEL1 - -config STM32H7_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM16_PWM - -config STM32H7_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H7_TIM17 - select STM32H7_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM17_PWM - -config STM32H7_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H7_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM17_CHANNEL1 - -config STM32H7_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM17_PWM - -config STM32H7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H7_TIM1 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H7_TIM8 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H7_TIM8_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM8_PULSECOUNT -config STM32H7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H7_TIM1 && STM32H7_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H7_TIM1_ADC1 - depends on STM32H7_TIM1_ADC - -config STM32H7_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H7_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32H7_TIM1_ADC3 - bool "Use TIM1 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice # Select ADC for use with TIM1 - -config STM32H7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H7_TIM2 && STM32H7_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H7_TIM2_ADC1 - depends on STM32H7_TIM2_ADC - -config STM32H7_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H7_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32H7_TIM2_ADC3 - bool "Use TIM2 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice # Select ADC for use with TIM2 - -config STM32H7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H7_TIM3 && STM32H7_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H7_TIM3_ADC1 - depends on STM32H7_TIM3_ADC - -config STM32H7_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H7_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32H7_TIM3_ADC3 - bool "Use TIM3 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice # Select ADC for use with TIM3 - -config STM32H7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H7_TIM4 && STM32H7_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H7_TIM4_ADC1 - depends on STM32H7_TIM4_ADC - -config STM32H7_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H7_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32H7_TIM4_ADC3 - bool "Use TIM4 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice # Select ADC for use with TIM4 - -config STM32H7_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H7_TIM6 && STM32H7_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H7_TIM6_ADC1 - depends on STM32H7_TIM6_ADC - -config STM32H7_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H7_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32H7_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice # Select ADC for use with TIM6 - -config STM32H7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H7_TIM8 && STM32H7_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H7_TIM8_ADC1 - depends on STM32H7_TIM8_ADC - -config STM32H7_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H7_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32H7_TIM8_ADC3 - bool "Use TIM8 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice # Select ADC for use with TIM8 - -config STM32H7_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H7_TIM15 && STM32H7_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H7_TIM15_ADC1 - depends on STM32H7_TIM15_ADC - -config STM32H7_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H7_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32H7_TIM15_ADC3 - bool "Use TIM15 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice # Select ADC for use with TIM15 - -config STM32H7_HAVE_ADC1_TIMER - bool - -config STM32H7_HAVE_ADC2_TIMER - bool - -config STM32H7_HAVE_ADC3_TIMER - bool - -config STM32H7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32H7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_TIMX_CAP - default n - bool "Helpers for Capture Drivers" - -config STM32H7_TIM1_CAP - bool "TIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM1 - ---help--- - Reserve timer 1 for use by the capture driver. - -if STM32H7_TIM1_CAP - -config STM32H7_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM1. - -config STM32H7_TIM1_CLOCK - int "TIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM1_CAP - -config STM32H7_TIM8_CAP - bool "TIM8 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM8 - ---help--- - Reserve timer 8 for use by the capture driver. - -if STM32H7_TIM8_CAP - -config STM32H7_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM8. - -config STM32H7_TIM8_CLOCK - int "TIM8 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM8_CAP - -# -# General-Purpose Timers (4 Channels) -# - -config STM32H7_TIM2_CAP - bool "TIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM2 - ---help--- - Reserve timer 2 for use by the capture driver. - -if STM32H7_TIM2_CAP - -config STM32H7_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM2. - -config STM32H7_TIM2_CLOCK - int "TIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM2_CAP - -config STM32H7_TIM3_CAP - bool "TIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM3 - ---help--- - Reserve timer 3 for use by the capture driver. - -if STM32H7_TIM3_CAP - -config STM32H7_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM3. - -config STM32H7_TIM3_CLOCK - int "TIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM3_CAP - -config STM32H7_TIM4_CAP - bool "TIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM4 - ---help--- - Reserve timer 4 for use by the capture driver. - -if STM32H7_TIM4_CAP - -config STM32H7_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM4. - -config STM32H7_TIM4_CLOCK - int "TIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM4_CAP - -config STM32H7_TIM5_CAP - bool "TIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM5 - ---help--- - Reserve timer 5 for use by the capture driver. - -if STM32H7_TIM5_CAP - -config STM32H7_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM5. - -config STM32H7_TIM5_CLOCK - int "TIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM5_CAP - -# -# General-Purpose Timers (2 Channels) -# - -config STM32H7_TIM12_CAP - bool "TIM12 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM12 - ---help--- - Reserve timer 12 for use by the capture driver. - -if STM32H7_TIM12_CAP - -config STM32H7_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM12. - -config STM32H7_TIM12_CLOCK - int "TIM12 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM12_CAP - -config STM32H7_TIM15_CAP - bool "TIM15 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -if STM32H7_TIM15_CAP - -config STM32H7_TIM15_CHANNEL - int "TIM15 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM15. - -config STM32H7_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM15_CAP - -# -# General-Purpose Timers (1 Channel) -# - -config STM32H7_TIM13_CAP - bool "TIM13 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM13 - ---help--- - Reserve timer 13 for use by the capture driver. - -if STM32H7_TIM13_CAP - -config STM32H7_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM13. - -config STM32H7_TIM13_CLOCK - int "TIM13 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM13_CAP - -config STM32H7_TIM14_CAP - bool "TIM14 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM14 - ---help--- - Reserve timer 14 for use by the capture driver. - -if STM32H7_TIM14_CAP - -config STM32H7_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM14. - -config STM32H7_TIM14_CLOCK - int "TIM14 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM14_CAP - -config STM32H7_TIM16_CAP - bool "TIM16 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -if STM32H7_TIM16_CAP - -config STM32H7_TIM16_CHANNEL - int "TIM16 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM16. - -config STM32H7_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM16_CAP - -config STM32H7_TIM17_CAP - bool "TIM17 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -if STM32H7_TIM17_CAP - -config STM32H7_TIM17_CHANNEL - int "TIM17 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM17. - -config STM32H7_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM17_CAP - -# -# Low-Power Timers -# - -config STM32H7_LPTIM1_CAP - bool "LPTIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM1 - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -if STM32H7_LPTIM1_CAP - -config STM32H7LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32H7LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM1_CAP - -config STM32H7_LPTIM2_CAP - bool "LPTIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM2 - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -if STM32H7_LPTIM2_CAP - -config STM32H7LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32H7LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM2_CAP - -config STM32H7_LPTIM3_CAP - bool "LPTIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM3 - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -if STM32H7_LPTIM3_CAP - -config STM32H7LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32H7LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM3_CAP - -config STM32H7_LPTIM4_CAP - bool "LPTIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM4 - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -if STM32H7_LPTIM4_CAP - -config STM32H7LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32H7LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM4_CAP - -config STM32H7_LPTIM5_CAP - bool "LPTIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM5 - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -if STM32H7_LPTIM5_CAP - -config STM32H7LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32H7LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM5_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32H7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H7_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H7_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H7_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H7_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H7_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H7_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H7_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H7_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H7_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H7_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H7_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H7_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "Ethernet MAC configuration" - depends on STM32H7_ETHMAC - -config STM32H7_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32H7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32H7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32H7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32H7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H7_MII_EXTCLK - depends on STM32H7_MII - -config STM32H7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32H7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32H7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # MII clock configuration - -config STM32H7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H7_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H7_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H7_ETHFD - bool "Full duplex" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H7_AUTONEG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H7_RMII - bool - default !STM32H7_MII - -choice - prompt "RMII clock configuration" - default STM32H7_RMII_EXTCLK - depends on STM32H7_RMII - -config STM32H7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H7_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC configuration - -if STM32H7_LTDC - -menu "LTDC Configuration" - -config STM32H7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32H7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32H7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32H7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32H7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32H7_LTDC_DITHER - bool "Dither support" - default n - -config STM32H7_LTDC_DITHER_RED - depends on STM32H7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32H7_LTDC_DITHER_GREEN - depends on STM32H7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32H7_LTDC_DITHER_BLUE - depends on STM32H7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32H7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32H7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32H7_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while the display is being refreshed. - This configuration requires two framebuffers: one active and one inactive. - When the display refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -config STM32H7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32H7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32H7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32H7_LTDC_L1_RGB565 - -config STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32H7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32H7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32H7_LTDC_L2 - -config STM32H7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32H7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32H7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32H7_LTDC_L2_RGB565 - -config STM32H7_LTDC_L2_L8 - depends on STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32H7_LTDC_L2_AL44 - depends on STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32H7_LTDC_L2_AL88 - depends on STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32H7_LTDC_L2_RGB565 - depends on STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32H7_LTDC_L2_ARGB4444 - depends on STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32H7_LTDC_L2_ARGB1555 - depends on STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32H7_LTDC_L2_RGB888 - depends on STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32H7_LTDC_L2_ARGB8888 - depends on STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32H7_LTDC_L2 - -config STM32H7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32H7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32H7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32H7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu # LTDC Configuration - -endif # STM32H7_LTDC - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32H7_TIM1 || STM32H7_TIM2 || STM32H7_TIM3 || STM32H7_TIM4 || STM32H7_TIM5 || STM32H7_TIM8 - -config STM32H7_TIM1_QE - bool "TIM1" - default n - depends on STM32H7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32H7_TIM1_QE - -config STM32H7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM1_QE - -config STM32H7_TIM2_QE - bool "TIM2" - default n - depends on STM32H7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32H7_TIM2_QE - -config STM32H7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM2_QE - -config STM32H7_TIM3_QE - bool "TIM3" - default n - depends on STM32H7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32H7_TIM3_QE - -config STM32H7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM3_QE - -config STM32H7_TIM4_QE - bool "TIM4" - default n - depends on STM32H7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32H7_TIM4_QE - -config STM32H7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM4_QE - -config STM32H7_TIM5_QE - bool "TIM5" - default n - depends on STM32H7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32H7_TIM5_QE - -config STM32H7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM5_QE - -config STM32H7_TIM8_QE - bool "TIM8" - default n - depends on STM32H7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32H7_TIM8_QE - -config STM32H7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM8_QE - -config STM32H7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32H7_QENCODER_SAMPLE_FDTS_4 - -config STM32H7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32H7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32H7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32H7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32H7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32H7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice # Input channel sampling frequency - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel event count" - default STM32H7_QENCODER_SAMPLE_EVENT_6 - -config STM32H7_QENCODER_SAMPLE_EVENT_1 - depends on STM32H7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32H7_QENCODER_SAMPLE_EVENT_2 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32H7_QENCODER_SAMPLE_EVENT_4 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32H7_QENCODER_SAMPLE_EVENT_5 - depends on STM32H7_QENCODER_SAMPLE_FDTS_16 || STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32H7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32H7_QENCODER_SAMPLE_FDTS && !STM32H7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32H7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32H7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice # Input channel event count - -endmenu # QEncoder Driver - -menu "FDCAN Driver Configuration" - depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3 - -menu "FDCAN1 Configuration" - depends on STM32H7_FDCAN1 - -config FDCAN1_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN1_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN1_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN1 - -menu "FDCAN2 Configuration" - depends on STM32H7_FDCAN2 - -config FDCAN2_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN2_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN2_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN2 - -menu "FDCAN3 Configuration" - depends on STM32H7_FDCAN3 - -config FDCAN3_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 1000000 - -config FDCAN3_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 1000000 - -config FDCAN3_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN3 - -config STM32H7_FDCAN_REGDEBUG - bool "Enable register dump debugging" - depends on DEBUG_NET_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO. - -config STM32H7_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - - TODO: Enable separately for FDCAN1 and FDCAN2 - -choice - prompt "FDCAN Loopback Mode" - depends on STM32H7_FDCAN_LOOPBACK - default STM32H7_FDCAN_LOOPBACK_INTERNAL - -config STM32H7_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32H7_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - default STM32H7_FDCAN_LPWORK - -config STM32H7_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32H7_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -endmenu # FDCAN Driver + Exclude SRAM4 from the HEAP in order to use this 64 KB region + for other uses, such as DMA buffers, etc. menu "Progmem MTD configuration" @@ -6665,7 +820,7 @@ config STM32_PROGMEM_OTA_PARTITION select MTD_BYTE_WRITE select MTD_PARTITION select MTD_PROGMEM - select STM32H7_PROGMEM + select STM32_PROGMEM ---help--- Initialize an MTD driver for the Flash, which will add an entry at /dev for application access from userspace. diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 73f9b13979a72..21944591be786 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -27,7 +27,7 @@ include armv7-m/Make.defs -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -35,7 +35,7 @@ ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y) CHIP_CSRCS += stm32_dualcore.c endif -ifeq ($(CONFIG_STM32H7_HSEM),y) +ifeq ($(CONFIG_STM32_HSEM),y) CHIP_CSRCS += stm32_hsem.c endif @@ -55,7 +55,7 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32H7_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c endif @@ -71,51 +71,51 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32H7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H7_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CHIP_CSRCS += stm32_fdcan_sock.c endif -ifeq ($(CONFIG_STM32H7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32H7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32H7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32H7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32H7_QUADSPI),y) +ifeq ($(CONFIG_STM32_QUADSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -128,7 +128,7 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif @@ -136,7 +136,7 @@ ifeq ($(CONFIG_SPI_SLAVE),y) CHIP_CSRCS += stm32_spi_slave.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -144,7 +144,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_TIMX_CAP),y) +ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -152,7 +152,7 @@ ifeq ($(CONFIG_CAPTURE),y) CHIP_CSRCS += stm32_capture_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif @@ -171,23 +171,23 @@ endif endif endif -ifeq ($(CONFIG_STM32H7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H7_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32_lptim.c endif -ifeq ($(CONFIG_STM32H7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32H7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -206,22 +206,22 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32H7_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32H7_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -#ifeq ($(CONFIG_STM32H7_HASH),y) -#CHIP_CSRCS += stm32_hash.c -#endif - -ifeq ($(CONFIG_STM32H7_CRYP),y) +ifeq ($(CONFIG_STM32_CRYP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_aes.c endif +endif ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_crypto.c endif +endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 96eb849ca33b1..1e3737d13e3e0 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -63,7 +63,7 @@ #define STM32_DTCRAM_BASE 0x20000000 /* 0x20000000-0x2001ffff: DTCM-RAM on TCM interface */ #define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */ # ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */ diff --git a/arch/arm/src/stm32h7/stm32_aes.h b/arch/arm/src/stm32h7/stm32_aes.h index ad9595d946a50..207bcad7262d7 100644 --- a/arch/arm/src/stm32h7/stm32_aes.h +++ b/arch/arm/src/stm32h7/stm32_aes.h @@ -37,7 +37,7 @@ * variants include CRYP */ -#ifdef CONFIG_STM32H7_HAVE_CRYP +#ifdef CONFIG_STM32_HAVE_CRYP # include "hardware/stm32h7xxxx_cryp.h" #else # error "Unknown chip for AES" diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 824be376db5d6..ab77f78604da4 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -47,16 +47,16 @@ #include "hardware/stm32_memorymap.h" #include "stm32_mpuinit.h" -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # include "stm32_dtcm.h" #endif -#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fmc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ !defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support disabled */ @@ -116,7 +116,7 @@ # define SRAM123_START STM32_SRAM123_BASE # define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) -#elif defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support enabled */ @@ -129,7 +129,7 @@ # undef SRAM123_START # undef SRAM123_END -#elif defined(CONFIG_ARCH_CHIP_STM32_CORTEXM4) +#elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) /* Configuration for M4 core support enabled */ diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 0b08b7b8d9d4e..79ee35e30224e 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -37,7 +37,7 @@ #include -#include "stm32_capture_m3m4_v1.h" +#include "stm32_capture.h" #if defined(CONFIG_CAPTURE) diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 145e1cb6a4668..d0b3d84148f95 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -40,7 +40,7 @@ /* Check CM4 core configuration */ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # if defined(CONFIG_ARMV7M_DCACHE) || defined(CONFIG_ARMV7M_DTCM) || \ defined(CONFIG_ARMV7M_ICACHE) # error Invalid configuration for CM4 core @@ -51,9 +51,9 @@ * Private Functions ****************************************************************************/ -#if (defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \ - defined(CONFIG_ARCH_CHIP_STM32_CORTEXM4) + defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) /**************************************************************************** * Name: stm32_cm4_boot @@ -77,7 +77,7 @@ static bool stm32_cm4_boot(void) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** * Name: stm32_cm4_busywait_lock_sem @@ -104,7 +104,7 @@ static void stm32_cpu2sem_wait(void) } #endif -#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** @@ -133,7 +133,7 @@ static void stm32_cpu2sem_take(void) * Public Functions ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** @@ -175,7 +175,7 @@ void stm32_start_cm4(void) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** * Name: stm32_waitfor_cm7 * diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index 21dd549499bb2..9a8973b6ccb0d 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -50,7 +50,7 @@ extern "C" #define EXTERN extern #endif -#if defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** @@ -64,7 +64,7 @@ extern "C" void stm32_start_cm4(void); #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** * Name: stm32_waitfor_cm7 * diff --git a/arch/arm/src/stm32h7/stm32_hsem.c b/arch/arm/src/stm32h7/stm32_hsem.c index 401591f477a51..480223220f3fc 100644 --- a/arch/arm/src/stm32h7/stm32_hsem.c +++ b/arch/arm/src/stm32h7/stm32_hsem.c @@ -234,7 +234,7 @@ bool stm32_hsem_take(uint8_t id) /* Take semaphore */ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 return (getreg32(STM32_HSEM_RLRX(id)) == ((HSEM_COREID_CPU1 << HSEM_SEMX_COREID_SHIFT) | HSEM_SEMX_LOCK)); #else @@ -253,7 +253,7 @@ bool stm32_hsem_take(uint8_t id) void stm32_hsem_free(uint8_t id) { -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 putreg32((HSEM_COREID_CPU1 << HSEM_CR_COREID_SHIFT) , STM32_HSEM_RX(id)); #else putreg32((HSEM_COREID_CPU2 << HSEM_CR_COREID_SHIFT) , STM32_HSEM_RX(id)); @@ -278,7 +278,7 @@ void stm32_hsem_init(void) /* Set block id */ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 dev->block = 0; dev->irq = STM32_IRQ_HSEM0; #else diff --git a/arch/arm/src/stm32h7/stm32_ltdc.h b/arch/arm/src/stm32h7/stm32_ltdc.h index 93d0ed6531edb..cd95f6da700f8 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.h +++ b/arch/arm/src/stm32h7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32H7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index d8611b0f388bf..dcb7abdbe985e 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -86,9 +86,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -112,7 +112,7 @@ void stm32_clockconfig(void) stm32_pwr_initbkp(false); # endif -# if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) +# if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -153,9 +153,9 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,7 +168,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h index a39962ef5753a..8dfaf0eb65400 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.h +++ b/arch/arm/src/stm32h7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -157,7 +157,7 @@ void stm32_stdclockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -174,9 +174,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 14a1a225df4a0..c46354c4569e0 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_OPENAMP_CACHE) # error CONFIG_OPENAMP_CACHE must be set # endif @@ -119,7 +119,7 @@ static int stm32_rptun_register_callback(struct rptun_dev_s *dev, rptun_callback_t callback, void *arg); -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 static void stm32_rptun_reset(struct rptun_dev_s *dev, int value); static void stm32_rptun_panic(struct rptun_dev_s *dev); #endif @@ -138,13 +138,13 @@ static const struct rptun_ops_s g_stm32_rptun_ops = .stop = stm32_rptun_stop, .notify = stm32_rptun_notify, .register_callback = stm32_rptun_register_callback, -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 .reset = stm32_rptun_reset, .panic = stm32_rptun_panic #endif }; -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /* Allocate shared memory on the CM7 core side */ static struct stm32_rptun_shmem_s g_shmem __attribute__((section(".shmem"))); @@ -185,7 +185,7 @@ stm32_rptun_get_resource(struct rptun_dev_s *dev) return &priv->shmem->rsc.rsc_tbl_hdr; } -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 priv->shmem = &g_shmem; #else priv->shmem = (struct stm32_rptun_shmem_s *)VRING_SHMEM; @@ -297,7 +297,7 @@ static int stm32_rptun_stop(struct rptun_dev_s *dev) static int stm32_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid) { -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /* Notify slave that RX is ready */ stm32_hsem_signal(RPTUN_HSEM_CHAN_SLAVE_RX); @@ -327,7 +327,7 @@ static int stm32_rptun_register_callback(struct rptun_dev_s *dev, return 0; } -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /**************************************************************************** * Name: stm32_rptun_reset ****************************************************************************/ @@ -352,7 +352,7 @@ static void stm32_rptun_panic(struct rptun_dev_s *dev) } #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /**************************************************************************** * Name: stm32_hsem_master_callback ****************************************************************************/ @@ -480,7 +480,7 @@ int stm32_rptun_init(const char *cpuname) stm32_hsem_init(); -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /* The CM7 core always master */ memset(&g_shmem, 0, sizeof(struct stm32_rptun_shmem_s)); @@ -491,7 +491,7 @@ int stm32_rptun_init(const char *cpuname) /* Configure HSEM */ -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 stm32_rptun_hsem_cm7(dev); #else stm32_rptun_hsem_cm4(dev); diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index b2f89d5fc9d94..fa55412dc064b 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -47,7 +47,7 @@ #include "stm32_lowputc.h" #include "stm32_start.h" -#ifdef CONFIG_ARCH_STM32_DUALCORE +#ifdef CONFIG_ARCH_STM32H7_DUALCORE # include "stm32_dualcore.h" #endif @@ -117,7 +117,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE; void __start(void) noinstrument_function; #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /**************************************************************************** * Name: stm32_tcmenable * @@ -192,7 +192,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /* Wait for CM7 initialization done */ stm32_waitfor_cm7(); @@ -251,7 +251,7 @@ void __start(void) stm32_lowsetup(); showprogress('A'); -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /* Enable/disable tightly coupled memories */ stm32_tcmenable(); @@ -262,7 +262,7 @@ void __start(void) stm32_boardinitialize(); showprogress('B'); -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 /* Enable I- and D-Caches */ up_enable_icache(); @@ -303,8 +303,8 @@ void __start(void) showprogress('\r'); showprogress('\n'); -#if defined(CONFIG_ARCH_STM32_DUALCORE) && \ - defined(CONFIG_ARCH_CHIP_STM32_CORTEXM7) && \ +#if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \ + defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Start CM4 core after clock configuration is done */ diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index d8d998f713d74..c65bc2feeda73 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -326,7 +326,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic clock enable */ regval |= RCC_AHB2ENR_CRYPTEN; diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig index 81256b344b366..6c5b66cd26959 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,13 +48,13 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig index 5ead89d6a20dc..007834df6637b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig index 2f5b1ee1c58e2..dad3146608797 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -50,9 +51,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index ef1fdd8f3fa13..7b2e63c57f640 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -57,11 +58,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig index 0478f18677610..676f5681af176 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig @@ -6,13 +6,14 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,14 +67,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xC0600000 -CONFIG_STM32H7_LTDC_FB_SIZE=2097152 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xC0600000 +CONFIG_STM32_LTDC_FB_SIZE=2097152 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig index 5f25013c7d1b1..a1d0ec0844fe7 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig index 6486a55fbbb22..8f04d2c7ab6c3 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,11 +61,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig index 2579b2ca842aa..8498dcc669e02 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig index 8d434e7ed5ea7..0f07506b59bb2 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,18 +70,18 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_PHYSR=30 -CONFIG_STM32H7_PHYSR_100FD=0x6 -CONFIG_STM32H7_PHYSR_100HD=0x2 -CONFIG_STM32H7_PHYSR_10FD=0x5 -CONFIG_STM32H7_PHYSR_10HD=0x1 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x7 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RMII_MCO1=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYSR=30 +CONFIG_STM32_PHYSR_100FD=0x6 +CONFIG_STM32_PHYSR_100HD=0x2 +CONFIG_STM32_PHYSR_10FD=0x5 +CONFIG_STM32_PHYSR_10HD=0x1 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x7 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_MCO1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig index 293a768c652ec..4f5046b5bf403 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,9 +46,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index c04492147c903..f358b89c9249a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_QUADSPI=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_NXFFS=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig index 790cb3c5968ed..483c66da52433 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,11 +49,11 @@ CONFIG_SENSORS_QENCODER=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM5=y -CONFIG_STM32H7_TIM5_QE=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM5_QE=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig index c50bb27796069..ccccc22e495df 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -68,11 +69,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig index 3dbb6830e6954..f341419ebfccd 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,11 +59,11 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig index b7502e7c4a2c9..3578ec87beb2d 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig index f79049ddbd2c2..7ef37a7cbf763 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,9 +67,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig index 7f6c62f7326f6..2dec3ec83891d 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,15 +56,15 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ONESHOT=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM17=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig index 0c36755c1c72a..3a56b8e9afa90 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig @@ -8,11 +8,12 @@ # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_SDMMC_IDMA is not set +# CONFIG_STM32_SDMMC_IDMA is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,12 +61,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig index 77d040d77ad81..3772f3440ed27 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -49,11 +50,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig index 12364f56d134b..e2faa065b1b7a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,12 +66,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_ZMODEM=y CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index d0d7904d73a2b..e4b1d4e927545 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -30,11 +30,11 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userled.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -70,7 +70,7 @@ if(CONFIG_CL_MFRC522) list(APPEND SRCS stm32_mfrc522.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile index c2ae5df6f581a..56336dc4c5ab3 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile @@ -32,11 +32,11 @@ else endif endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif @@ -68,7 +68,7 @@ ifeq ($(CONFIG_CL_MFRC522),y) CSRCS += stm32_mfrc522.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig index 9008dcbeb9583..68f4df61d6500 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,19 +68,19 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig index bd2ea04db96f7..3c0284fa3b793 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig index 314c36575b7f0..47a638c77ada6 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,11 +74,11 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING6=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt index f27901f9491cb..45813c92cc5f6 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile index dedc375fb9c05..f57fd57f3068b 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig index 3596119057564..2ffafc58713c2 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,9 +44,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CAP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CAP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig index 81c3cdcdab630..b36d0f21e255b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,10 +76,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 2fa4212858e45..27247352da03f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,9 +55,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y CONFIG_STM32_ROMFS=y CONFIG_STM32_ROMFS_IMAGEFILE="../../apps/examples/elf/main/elf_romfs.img" +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TLS_NELEM=4 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index 6966a2baf2025..e5d2f3e188fa4 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,18 +74,18 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index 73d680b2e78cd..e8889b2c6e2a7 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,10 +56,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig index 67f590adaf0aa..ec57eb558ba55 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 7fe65a420a164..788de2f32ef0c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 7afab9a891584..6ad0662ee2446 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,10 +55,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_NXBOOT=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index 108860120e5ea..10e1dee8be13a 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,10 +57,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_NXBOOT=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index 8f193c58d45ab..86c0aa28e5dab 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,8 +60,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig index 258614328286d..5977b0463baea 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 36c6b375d46e0..e43edd2ca1ddd 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,21 +46,21 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_CH1NOUT=y -CONFIG_STM32H7_TIM1_CH1OUT=y -CONFIG_STM32H7_TIM1_CH2NOUT=y -CONFIG_STM32H7_TIM1_CH2OUT=y -CONFIG_STM32H7_TIM1_CH3NOUT=y -CONFIG_STM32H7_TIM1_CH3OUT=y -CONFIG_STM32H7_TIM1_CH4OUT=y -CONFIG_STM32H7_TIM1_CHANNEL1=y -CONFIG_STM32H7_TIM1_CHANNEL2=y -CONFIG_STM32H7_TIM1_CHANNEL3=y -CONFIG_STM32H7_TIM1_CHANNEL4=y -CONFIG_STM32H7_TIM1_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig index 9060c7e249b52..914de95443f0f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,9 +70,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt index d4e92b8f5ed14..4967d7e733d79 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -72,7 +72,7 @@ if(CONFIG_LCD_SSD1306) list(APPEND SRCS stm32_ssd1306.c) endif() -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_progmem.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile index 985900a61a9d7..bf54e0db6ef46 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile @@ -42,11 +42,11 @@ ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -74,7 +74,7 @@ ifeq ($(CONFIG_LCD_SSD1306),y) CSRCS += stm32_ssd1306.c endif -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CSRCS += stm32_progmem.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index 23c77196423b0..436b8c8c378d4 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -104,19 +105,19 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_TIM8=y -CONFIG_STM32H7_TIM8_PULSECOUNT=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig index 42df2d25cf260..c5bbd8b5b2747 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig index 238e410712d45..66ec35fe74b38 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index 1148378b85553..2f4276ac9c9c0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig index 5eb5fce08d013..68c89eacc79d3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt index ce26e66e8cc9d..1d7544f8cdba1 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile index 9991b451550b5..f05dd5b891c96 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/Kconfig b/boards/arm/stm32h7/nucleo-h745zi/Kconfig index bff59a181839a..bdc477c0e3970 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/Kconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/Kconfig @@ -11,7 +11,7 @@ choice config NUCLEOH745ZI_SMPS bool "Internal SMPS only (default)" - select STM32H7_PWR_DIRECT_SMPS_SUPPLY + select STM32_PWR_DIRECT_SMPS_SUPPLY config NUCLEOH745ZI_LDO bool "Internal LDO only" diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig index 4d056b4494f3b..66d8897395cf1 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,6 +39,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig index f404c9aca7cc4..f339a51f05253 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig index a4a5abb06fc0e..5aed179743265 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig index 32deeca58262e..b64fcb0e0aa8f 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,7 +49,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig index 5876e49c1e4e4..2d7fa0de5d037 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h index d0315dac37f77..5ac9a8b7a4690 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h @@ -153,7 +153,7 @@ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) #else # define STM32_CPUCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 1) diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld index c4bf2bd60d66d..56c5da03c479d 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld @@ -22,7 +22,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -40,7 +40,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld index b24bcef0596ff..7c33bec3bd892 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile index df3be92d50930..37c9b6b815dc6 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile @@ -34,7 +34,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c index 4dcddeb88b7c2..ddc8f1d668ccb 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_autoleds.c @@ -39,7 +39,7 @@ #ifdef CONFIG_ARCH_LEDS -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # error autoleds not supported for M4 core now #endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a782f7371941f..aa9ab6abbc6de 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -62,11 +62,11 @@ void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -105,7 +105,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig index e36ef99884439..9f75e257f097e 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,8 +48,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_CRYP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_CRYP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_CRYPTO=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig index 4482d9ba53b8a..64f82396477a6 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -103,17 +104,17 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig index 6d3d69392c974..690987ab92fcd 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig index 4e017f8e0db0a..d4005fc697a06 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig index 6851a571ec6db..d6e8735235260 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig index 602d566130dda..f9643ef1a1a8f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt index 73ac7a500a71d..8e61aeb5382f1 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile index 0f164c5b1a4d1..e310e6c8a8efa 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig index ad92a680c9987..8bca88575835d 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,9 +76,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig index 42eadf579ad14..5cf6dd2376c6b 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -72,11 +73,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig index 51e03a5d33f8d..e3de0edfcdef4 100644 --- a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig index 5122941e7e509..6c37d27f4ad3a 100644 --- a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,12 +56,12 @@ CONFIG_STACK_USAGE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_OTGFS_HOST=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_HOST=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt index d6e3a6040cbf4..7e8e6aa233421 100644 --- a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt +++ b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Makefile index eda04e7c3af25..c9f0115dbabde 100644 --- a/boards/arm/stm32h7/openh743i/src/Makefile +++ b/boards/arm/stm32h7/openh743i/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig index c8778936d3ef9..f324baba7d729 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,9 +57,9 @@ CONFIG_SIGNAL_FD=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C1=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_I2CTOOL=y diff --git a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig index e3c035673f464..8b65fcd4526bd 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/portenta-h7/include/board.h b/boards/arm/stm32h7/portenta-h7/include/board.h index 4ce9460b7e92b..14d214598f0d3 100644 --- a/boards/arm/stm32h7/portenta-h7/include/board.h +++ b/boards/arm/stm32h7/portenta-h7/include/board.h @@ -150,7 +150,7 @@ #define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) #define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) #else # define STM32_CPUCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 1) diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld index ad17d4464f008..b6cbb61a0c105 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld @@ -28,7 +28,7 @@ # define FLASH_START 0x08000000 #endif -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -46,7 +46,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld index c8122812f9406..8627f09500480 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c b/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c index 131b0ccc5b21e..686f4d5245474 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_autoleds.c @@ -39,7 +39,7 @@ #ifdef CONFIG_ARCH_LEDS -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # error autoleds not supported for M4 core now #endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig index 5690c750d3736..e1284a69ff073 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig @@ -6,15 +6,16 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,15 +66,15 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0x24020000 -CONFIG_STM32H7_LTDC_FB_SIZE=261120 -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0x24020000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig index a8fe4e516efa7..ea4a80f74f384 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig @@ -6,11 +6,12 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -63,19 +64,19 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_MII=y -CONFIG_STM32H7_PHYADDR=1 -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FMC=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYADDR=1 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig index c138b61ca0154..28dcea36030b6 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -41,9 +42,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig index b1c3acf72f095..d4f0bbb49a957 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,9 +39,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_UART7=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_UART7=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART7_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig index d3dd2789880b0..35697fcdf3714 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -43,7 +44,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig index e02a55c70a6d2..dcee32242f047 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,9 +43,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig index 52f90e5c3f8c3..9ee4b9596d6ab 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig index d187e442ce272..665a08ff3b2ac 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig @@ -6,12 +6,13 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,10 +52,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld index e0f982d7c648d..3ed5b169c6c90 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld @@ -97,7 +97,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -115,7 +115,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -192,7 +192,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld index 74787002507c2..98296d3ffd1f5 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt index 424170bc1a1db..bb605d54ac719 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt @@ -28,7 +28,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -44,7 +44,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile index 59db9b7cd6a76..13359572cb5d9 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile @@ -30,7 +30,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -46,7 +46,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c index 2b575ec3398e3..def80baa81051 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c @@ -92,11 +92,11 @@ static void convert_lcd_rgb565(void) void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -140,7 +140,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 43a7a87143ca3..3ddf480334a8c 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h747i-disco" CONFIG_ARCH_BOARD_STM32H747I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -44,7 +45,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt index 2aff1364c448c..4583b43c5e703 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,7 +48,7 @@ if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile index 788e0f0d91f20..2f0eaeee20ff8 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif @@ -50,7 +50,7 @@ ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig index f4913aa50bb86..66fe8ef9f0554 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig @@ -6,14 +6,15 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h750b-dk" CONFIG_ARCH_BOARD_STM32H750B_DK=y CONFIG_ARCH_BOARD_STM32H750B_DK_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750XB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,14 +68,14 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xd0000000 -CONFIG_STM32H7_LTDC_FB_SIZE=522240 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xd0000000 +CONFIG_STM32_LTDC_FB_SIZE=522240 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld index eae68e2f5a1a0..d08b0b9d47522 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld @@ -95,7 +95,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -114,7 +114,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -191,7 +191,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld index ed39a30ec56d0..d6f3372fd3723 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld @@ -20,9 +20,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -32,7 +32,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt index d89067b817f11..4424e92766119 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt @@ -26,7 +26,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -42,7 +42,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile index 7dec83d2100fc..942bfb9fd3e9e 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile +++ b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile @@ -28,7 +28,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -44,7 +44,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c index d4e536b774474..8282101411b50 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c @@ -90,11 +90,11 @@ static void convert_lcd_rgb565(void) void rpmsg_serialinit(void) { -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 uart_rpmsg_init("cm4", "proxy", 4096, false); #endif -#ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM4 +#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE uart_rpmsg_init("cm7", "proxy", 4096, true); # else @@ -138,7 +138,7 @@ int stm32_bringup(void) #endif /* CONFIG_FS_PROCFS */ #ifdef CONFIG_RPTUN -# ifdef CONFIG_ARCH_CHIP_STM32_CORTEXM7 +# ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 stm32_rptun_init("cm4"); # else stm32_rptun_init("cm7"); diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig index 3a3b4caf7f828..3ed170d4ccea1 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig index bb9f06926d9f7..52d6fd71d4d24 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,10 +59,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig index 5aedb0aeceee3..fc9b8d1a0175f 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,8 +56,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig index 537159322559c..e2a79412f1c59 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,9 +48,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt index af3c82ac515ef..6f41b679d009e 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt @@ -34,7 +34,7 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Makefile index 3d686ef415e02..0bbd3d18694dd 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h743/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig index 70ab99d673af9..edb8697b24eeb 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig index d1fa7662bd6d8..ffe5056a9843d 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,10 +60,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig index 5098495e7f2a6..df870df8aefb9 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,8 +57,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig index f8e8e73032111..bb2110e286298 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt index 6c5220cccc2ab..2d99034462275 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt @@ -34,15 +34,15 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Makefile b/boards/arm/stm32h7/weact-stm32h750/src/Makefile index 80033455ab338..083f46024de37 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h750/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif From 9dd9cc5d33455ace84bba6588fd0448d1beb749f Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:39 +0200 Subject: [PATCH 15/52] !arm/stm32l4: use common STM32 Kconfig symbols BREAKING CHANGE: STM32L4 Kconfig symbols were renamed from CONFIG_STM32L4_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32l4/boards/nucleo-l496zg/index.rst | 2 +- .../boards/stm32l476vg-disco/index.rst | 2 +- .../boards/stm32l4r9ai-disco/index.rst | 8 +- Documentation/platforms/arm/stm32l4/index.rst | 6 +- arch/arm/src/stm32l4/CMakeLists.txt | 46 +- arch/arm/src/stm32l4/Kconfig | 6327 ++--------------- arch/arm/src/stm32l4/Make.defs | 48 +- arch/arm/src/stm32l4/hardware/stm32l4_adc.h | 6 +- arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h | 6 +- arch/arm/src/stm32l4/hardware/stm32l4_flash.h | 6 +- .../src/stm32l4/hardware/stm32l4_memorymap.h | 6 +- arch/arm/src/stm32l4/hardware/stm32l4_pwr.h | 6 +- .../arm/src/stm32l4/hardware/stm32l4_usbdev.h | 6 +- arch/arm/src/stm32l4/stm32l4_adc.h | 6 +- arch/arm/src/stm32l4/stm32l4_can.h | 6 +- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 6 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 6 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 6 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 6 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 6 +- arch/arm/src/stm32l4/stm32l4_pwm.h | 6 +- arch/arm/src/stm32l4/stm32l4_qspi.h | 6 +- arch/arm/src/stm32l4/stm32l4_rtc.h | 6 +- arch/arm/src/stm32l4/stm32l4_usbhost.h | 6 +- boards/arm/stm32l4/b-l475e-iot01a/Kconfig | 4 +- .../b-l475e-iot01a/configs/nsh/defconfig | 5 +- .../configs/spirit-6lowpan/defconfig | 5 +- .../configs/spirit-starhub/defconfig | 5 +- .../configs/spirit-starpoint/defconfig | 5 +- boards/arm/stm32l4/nucleo-l432kc/Kconfig | 22 +- .../nucleo-l432kc/configs/nsh/defconfig | 19 +- .../nucleo-l432kc/configs/spwm/defconfig | 25 +- .../nucleo-l432kc/configs/wgen/defconfig | 35 +- .../stm32l4/nucleo-l432kc/src/CMakeLists.txt | 4 +- boards/arm/stm32l4/nucleo-l432kc/src/Makefile | 4 +- .../nucleo-l452re/configs/nsh/defconfig | 29 +- .../nucleo-l476rg/configs/nsh/defconfig | 19 +- .../nucleo-l476rg/configs/nxdemo/defconfig | 21 +- .../nucleo-l496zg/configs/nsh/defconfig | 59 +- .../stm32l4/nucleo-l496zg/src/CMakeLists.txt | 4 +- boards/arm/stm32l4/nucleo-l496zg/src/Makefile | 4 +- .../steval-stlcs01v1/configs/lwl/defconfig | 3 +- .../steval-stlcs01v1/configs/usbnsh/defconfig | 7 +- .../steval-stlcs01v1/src/CMakeLists.txt | 2 +- .../arm/stm32l4/steval-stlcs01v1/src/Makefile | 2 +- .../stm32l476-mdk/configs/nsh/defconfig | 17 +- .../stm32l4/stm32l476-mdk/src/CMakeLists.txt | 2 +- boards/arm/stm32l4/stm32l476-mdk/src/Makefile | 2 +- .../stm32l476vg-disco/configs/knsh/defconfig | 19 +- .../stm32l476vg-disco/configs/nsh/defconfig | 19 +- .../stm32l4/stm32l476vg-disco/src/Makefile | 4 +- .../stm32l4r9ai-disco/configs/knsh/defconfig | 23 +- .../stm32l4r9ai-disco/configs/nsh/defconfig | 25 +- .../stm32l4/stm32l4r9ai-disco/src/Makefile | 10 +- 54 files changed, 735 insertions(+), 6210 deletions(-) diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst index 0080c9db8d29e..89df8dc28f4f3 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst @@ -153,7 +153,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L4_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst index f3eb6fc33a360..c1d763f67d797 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst @@ -468,7 +468,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings:: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst index ddec498f57da6..b87198bfdd5a1 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst @@ -130,7 +130,7 @@ Pins and Connectors:: To configure USART1 as the console:: - CONFIG_STM32L4_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -172,7 +172,7 @@ Pins and Connectors:: To configure USART2 as the console:: - CONFIG_STM32L4_USART2=y + CONFIG_STM32_USART2=y CONFIG_USART2_SERIALDRIVER=y CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USART2_RXBUFSIZE=256 @@ -192,7 +192,7 @@ Pins and Connectors:: To configure USART4 as the console:: - CONFIG_STM32L4_UART4=y + CONFIG_STM32_UART4=y CONFIG_USART4_SERIALDRIVER=y CONFIG_USART4_SERIAL_CONSOLE=y CONFIG_USART4_RXBUFSIZE=512 @@ -357,7 +357,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings: (TODO: need to test!):: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/index.rst b/Documentation/platforms/arm/stm32l4/index.rst index 6be0b2f932cc8..2e8e1080c39dd 100644 --- a/Documentation/platforms/arm/stm32l4/index.rst +++ b/Documentation/platforms/arm/stm32l4/index.rst @@ -28,9 +28,9 @@ STM32L4X6 Yes RM0351 STM32L4XR Yes RM0432 (STM32L4+) ============ ======= ====== ================================ -[1]: Please avoid depending on CONFIG_STM32L4_STM32L4X1 and -CONFIG_STM32L4_STM32L4X2 as the MCUs are of the same subfamily -as CONFIG_STM32L4_STM32L4X3. +[1]: Please avoid depending on CONFIG_STM32_STM32L4X1 and +CONFIG_STM32_STM32L4X2 as the MCUs are of the same subfamily +as CONFIG_STM32_STM32L4X3. Peripheral Support ================== diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 040c98142bcd8..f27e4933b240e 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -58,11 +58,11 @@ else() list(APPEND SRCS stm32l4_tickless.c) endif() -if(CONFIG_STM32L4_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32L4_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32l4_freerun.c) endif() @@ -70,37 +70,37 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() -if(CONFIG_STM32L4_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32l4_hsi48.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32l4_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32l4_dac.c) endif() -if(CONFIG_STM32L4_DFSDM) +if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32l4_dfsdm.c) endif() -if(CONFIG_STM32L4_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32l4_dma.c) endif() if(CONFIG_USBDEV) - if(CONFIG_STM32L4_USBFS) + if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32l4_usbdev.c) endif() - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfsdev.c) endif() endif() if(CONFIG_USBHOST) - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfshost.c) endif() endif() @@ -124,11 +124,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32L4_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32l4_exti_pwr.c) endif() -if(CONFIG_STM32L4_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32l4_exti_alarm.c) endif() @@ -144,23 +144,23 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32l4_dumpgpio.c) endif() -if(CONFIG_STM32L4_COMP) +if(CONFIG_STM32_COMP) list(APPEND SRCS stm32l4_comp.c stm32l4_exti_comp.c) endif() -if(CONFIG_STM32L4_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32l4_rng.c) endif() -if(CONFIG_STM32L4_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32l4_sai.c) endif() -if(CONFIG_STM32L4_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32l4_lptim.c) endif() -if(CONFIG_STM32L4_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() @@ -172,27 +172,27 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32l4_qencoder.c) endif() -if(CONFIG_STM32L4_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32l4_qspi.c) endif() -if(CONFIG_STM32L4_CAN) +if(CONFIG_STM32_CAN) list(APPEND SRCS stm32l4_can.c) endif() -if(CONFIG_STM32L4_FIREWALL) +if(CONFIG_STM32_FIREWALL) list(APPEND SRCS stm32l4_firewall.c) endif() -if(CONFIG_STM32L4_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32l4_iwdg.c) endif() -if(CONFIG_STM32L4_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32l4_sdmmc.c) endif() -if(CONFIG_STM32L4_1WIREDRIVER) +if(CONFIG_STM32_1WIREDRIVER) list(APPEND SRCS stm32l4_1wire.c) endif() diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index b6d2bb1fb804c..39f391f230f20 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -7,6 +7,31 @@ if ARCH_CHIP_STM32L4 comment "STM32L4 Configuration Options" +config STM32_L4_PERIPHERALS + bool + default ARCH_CHIP_STM32L4 + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_RNG + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_SWPMI + select STM32_HAVE_FIREWALL + select STM32_HAVE_LPTIM_CHANNEL + select STM32_HAVE_TIM_ADC_CHANNEL + select STM32_HAVE_ADC_L4 + select STM32_HAVE_DAC_LL_OPS + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 L4 Chip Selection" default ARCH_CHIP_STM32L476RG @@ -14,544 +39,544 @@ choice config ARCH_CHIP_STM32L412KB bool "STM32L412KB" - select STM32L4_STM32L412XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L412XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 40 Kb SRAM config ARCH_CHIP_STM32L432KB bool "STM32L432KB" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L432KC bool "STM32L432KC" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CB bool "STM32L433CB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CC bool "STM32L433CC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RB bool "STM32L433RB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RC bool "STM32L433RC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433VC bool "STM32L433VC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L442KC bool "STM32L442KC" - select STM32L4_STM32L442XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L442XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443CC bool "STM32L443CC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443RC bool "STM32L443RC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443VC bool "STM32L443VC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L451CC bool "STM32L451CC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451CE bool "STM32L451CE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RC bool "STM32L451RC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RE bool "STM32L451RE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VC bool "STM32L451VC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VE bool "STM32L451VE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CC bool "STM32L452CC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CE bool "STM32L452CE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RC bool "STM32L452RC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RE bool "STM32L452RE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VC bool "STM32L452VC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VE bool "STM32L452VE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462CE bool "STM32L462CE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462RE bool "STM32L462RE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462VE bool "STM32L462VE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L475RG bool "STM32L475RG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RE bool "STM32L475RE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RC bool "STM32L475RC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475VG bool "STM32L475VG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VE bool "STM32L475VE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VC bool "STM32L475VC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L476JG bool "STM32L476JG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476JE bool "STM32L476JE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RG bool "STM32L476RG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RE bool "STM32L476RE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486RG bool "STM32L486RG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486JG bool "STM32L486JG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486VG bool "STM32L486VG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486QG bool "STM32L486QG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486ZG bool "STM32L486ZG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L496RE bool "STM32L496RE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496RG bool "STM32L496RG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VE bool "STM32L496VE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VG bool "STM32L496VG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZE bool "STM32L496ZE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZG bool "STM32L496ZG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496AG bool "STM32L496AG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6RG bool "STM32L4A6RG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6VG bool "STM32L4A6VG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6QG bool "STM32L4A6QG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6ZG bool "STM32L4A6ZG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6AG bool "STM32L4A6AG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4R5VG bool "STM32L4R5VG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QG bool "STM32L4R5QG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZG bool "STM32L4R5ZG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AG bool "STM32L4R5AG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5VI bool "STM32L4R5VI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QI bool "STM32L4R5QI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZI bool "STM32L4R5ZI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AI bool "STM32L4R5AI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VG bool "STM32L4R9VG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZG bool "STM32L4R9ZG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AG bool "STM32L4R9AG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VI bool "STM32L4R9VI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZI bool "STM32L4R9ZI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AI bool "STM32L4R9AI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM @@ -560,5924 +585,406 @@ endchoice # STM32 L4 Chip Selection # Chip product lines -config STM32L4_STM32L4X1 +config STM32_STM32L4X1 # STM32L4x1 Access Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). # # Note: This is _not_ for STM32L471xx (documented in RM0392). bool default n - select STM32L4_STM32L4X3 + select STM32_STM32L4X3 -config STM32L4_STM32L4X2 +config STM32_STM32L4X2 # STM32L4x2 USB Device Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_USBFS + select STM32_STM32L4X3 + select STM32_HAVE_USBFS -config STM32L4_STM32L4X3 +config STM32_STM32L4X3 # STM32L4 devices documented in RM0394, regardless of what ST's # marketing calls them. bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 if !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2) - select STM32L4_HAVE_HSI48 - -config STM32L4_STM32L4X5 + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_LCD if !(STM32_STM32L4X1 || STM32_STM32L4X2) + select STM32_HAVE_HSI48 + +config STM32_STM32L4X5 # STM32L4 USB OTG Lines (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_QSPI - -config STM32L4_STM32L4X6 + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_DFSDM1 + select STM32_HAVE_QSPI + +config STM32_STM32L4X6 # STM32L4x6 (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_LCD - select STM32L4_HAVE_QSPI - -config STM32L4_STM32L4XR + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_LCD + select STM32_HAVE_QSPI + +config STM32_STM32L4XR # STM32L4+ (documented in RM0432) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 - select STM32L4_HAVE_DMAMUX + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2C4 + select STM32_HAVE_DCMI + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMAMUX # Chip subfamilies: -config STM32L4_STM32L412XX +config STM32_STM32L412XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 -config STM32L4_STM32L422XX +config STM32_STM32L422XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L431XX +config STM32_STM32L431XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) + select STM32_STM32L4X1 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) -config STM32L4_STM32L432XX +config STM32_STM32L432XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L433XX +config STM32_STM32L433XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L442XX +config STM32_STM32L442XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L443XX +config STM32_STM32L443XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_AES + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L451XX +config STM32_STM32L451XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X1 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L452XX +config STM32_STM32L452XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L462XX +config STM32_STM32L462XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L471XX +config STM32_STM32L471XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 # TODO -config STM32L4_STM32L475XX - bool - default n - select STM32L4_STM32L4X5 - -config STM32L4_STM32L476XX - bool - default n - select STM32L4_STM32L4X6 - -config STM32L4_STM32L486XX - bool - default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_AES - -config STM32L4_STM32L496XX - bool - default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_CAN2 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 - -config STM32L4_STM32L4A6XX +config STM32_STM32L475XX bool default n - select STM32L4_STM32L496XX - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4X5 -config STM32L4_STM32L4R5XX +config STM32_STM32L476XX bool default n - select STM32L4_STM32L4XR + select STM32_STM32L4X6 -config STM32L4_STM32L4S5XX +config STM32_STM32L486XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4X6 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R7XX +config STM32_STM32L496XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D + select STM32_STM32L4X6 + select STM32_HAVE_I2C4 + select STM32_HAVE_CAN2 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 -config STM32L4_STM32L4S7XX +config STM32_STM32L4A6XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L496XX + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R9XX +config STM32_STM32L4R5XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC - -config STM32L4_STM32L4S9XX - bool - default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L4 - default STM32L4_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L4 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L476VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L4xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L4_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L4_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L4_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L4_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L4_FLASH_OVERRIDE_E - bool "E 512 KB" + select STM32_STM32L4XR -config STM32L4_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L4_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L4_FLASH_CONFIG_8 +config STM32_STM32L4S5XX bool default n - depends on STM32L4_STM32L412XX + select STM32_STM32L4XR + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_FLASH_CONFIG_B +config STM32_STM32L4R7XX bool default n - depends on STM32L4_STM32L4X1 || STM32L4_STM32L4X3 + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 -config STM32L4_FLASH_CONFIG_C +config STM32_STM32L4S7XX bool default n - depends on !STM32L4_STM32L496XX + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_FLASH_CONFIG_E +config STM32_STM32L4R9XX bool default n + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC -config STM32L4_FLASH_CONFIG_G +config STM32_STM32L4S9XX bool default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX -config STM32L4_FLASH_CONFIG_I - bool - default n - depends on STM32L4_STM32L4XR # Pin/package configurations config STM32L4_IO_CONFIG_K + # Package designator K bool default n config STM32L4_IO_CONFIG_T + # Package designator T bool default n config STM32L4_IO_CONFIG_C + # Package designator C bool default n config STM32L4_IO_CONFIG_R + # Package designator R bool default n config STM32L4_IO_CONFIG_J + # Package designator J bool default n config STM32L4_IO_CONFIG_M + # Package designator M bool default n config STM32L4_IO_CONFIG_V + # Package designator V bool default n config STM32L4_IO_CONFIG_Q + # Package designator Q bool default n config STM32L4_IO_CONFIG_Z + # Package designator Z bool default n config STM32L4_IO_CONFIG_A + # Package designator A bool default n comment "STM32L4 SRAM2 and SRAM3 Options" -config STM32L4_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L4_SRAM2_INIT - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L4_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32L4_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32L4_STM32L4XR - default y - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -comment "STM32L4 Peripherals" - -menu "STM32L4 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32L4_HAVE_ADC2 - bool - default n - -config STM32L4_HAVE_ADC3 - bool - default n - -config STM32L4_HAVE_AES - bool - default n - -config STM32L4_HAVE_CAN2 - bool - default n - -config STM32L4_HAVE_COMP - bool - default n - -config STM32L4_HAVE_DAC2 - bool - default n - -config STM32L4_HAVE_DCMI - bool - default n - -config STM32L4_HAVE_DFSDM1 - bool - default n - -config STM32L4_HAVE_DMA2D - bool - default n - -config STM32L4_HAVE_DMAMUX - bool - default n - -config STM32L4_HAVE_FSMC - bool - default n - -config STM32L4_HAVE_HASH - bool - default n - -config STM32L4_HAVE_HSI48 - bool - default n - -config STM32L4_HAVE_I2C4 - bool - default n - -config STM32L4_HAVE_LCD - bool - default n - -config STM32L4_HAVE_LTDC - bool - default n - -config STM32L4_HAVE_LPTIM1 - bool - default n - -config STM32L4_HAVE_LPTIM2 - bool - default n - -config STM32L4_HAVE_OTGFS - bool - default n - -config STM32L4_HAVE_USBFS - bool - default n - -config STM32L4_HAVE_SAI1 - bool - default n - -config STM32L4_HAVE_SAI2 - bool - default n - -config STM32L4_RTC - bool "RTC" - default n - select RTC - -config STM32L4_HAVE_SDMMC1 - bool - default n - -config STM32L4_HAVE_TIM3 - bool - default n - -config STM32L4_HAVE_TIM4 - bool - default n - -config STM32L4_HAVE_TIM5 - bool - default n - -config STM32L4_HAVE_TIM7 - bool - default n - -config STM32L4_HAVE_TIM8 - bool - default n - -config STM32L4_HAVE_TIM17 - bool - default n - -config STM32L4_HAVE_LPUART1 - bool - default n - -config STM32L4_HAVE_USART1 - bool - default n - -config STM32L4_HAVE_USART2 - bool - default n - -config STM32L4_HAVE_USART3 - bool - default n - -config STM32L4_HAVE_UART4 - bool - default n - -config STM32L4_HAVE_UART5 - bool - default n - -config STM32L4_HAVE_QSPI - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L4_ADC - bool - default n - -config STM32L4_CAN - bool - default n - -config STM32L4_DAC - bool - default n - -config STM32L4_DFSDM - bool - default n - -config STM32L4_DMAMUX - bool - default n - depends on STM32L4_HAVE_DMAMUX - -config STM32L4_DMA - bool - default n - select STM32L4_DMAMUX if STM32L4_HAVE_DMAMUX - -config STM32L4_I2C - bool - default n - -config STM32L4_SAI - bool - default n - -config STM32L4_SPI - bool - default n - -config STM32L4_PWM - bool - default n - -config STM32L4_USART - bool - default n - -config STM32L4_LPTIM - bool - default n - -config STM32L4_SDMMC - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32L4_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32L4_HAVE_DMAMUX - select STM32L4_DMAMUX - -config STM32L4_DMA1 - bool "DMA1" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_DMA2 - bool "DMA2" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_CRC - bool "CRC" - default n - -config STM32L4_TSC - bool "TSC" - default n - -comment "AHB2 Peripherals" - -config STM32L4_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - depends on STM32L4_HAVE_OTGFS - -config STM32L4_ADC1 - bool "ADC1" - default n - select STM32L4_ADC - -config STM32L4_ADC2 - bool "ADC2" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC2 - -config STM32L4_ADC3 - bool "ADC3" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC3 - -config STM32L4_AES - bool "AES" - default n - depends on STM32L4_HAVE_AES - -config STM32L4_DCMI - bool "DCMI" - default n - depends on STM32L4_HAVE_DCMI - -config STM32L4_DMA2D - bool "DMA2D" - default n - depends on STM32L4_HAVE_DMA2D - -config STM32L4_HASH - bool "HASH" - default n - depends on STM32L4_HAVE_HASH - -config STM32L4_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -comment "AHB3 Peripherals" - -config STM32L4_FSMC - bool "FSMC" - default n - depends on STM32L4_HAVE_FSMC - -config STM32L4_QSPI - bool "QuadSPI" - default n - depends on STM32L4_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -if STM32L4_QSPI - -config STM32L4_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483647 - ---help--- - The STM32L4 QSPI peripheral requires the size of the Flash be specified - -config STM32L4_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32L4 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32L4_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32L4 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32L4_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32L4_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32L4_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32L4_QSPI_DMA - bool "DMA" - depends on STM32L4_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "DMA Channel" - default STM32L4_QSPI_DMA_CHAN_1_5 - depends on STM32L4_DMA - ---help--- - You can choose between two DMA channels for use with QSPI: - either DMA1 channel 5, or DMA2 channel 7. - If you only see one choice here, it is probably because - you have not also enabled the associated DMA controller. - -config STM32L4_QSPI_DMA_CHAN_1_5 - bool "DMA1 Channel 5" - depends on STM32L4_DMA1 && !STM32L4_DMAMUX - ---help--- - Use DMA1 channel 5 for QSPI. - -config STM32L4_QSPI_DMA_CHAN_2_7 - bool "DMA2 Channel 7" - depends on STM32L4_DMA2 && !STM32L4_DMAMUX - ---help--- - Use DMA2 channel 7 for QSPI. - -endchoice - -choice - prompt "DMA Priority" - default STM32L4_QSPI_DMAPRIORITY_MEDIUM - depends on STM32L4_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32L4_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32L4_DMA - ---help--- - 'Highest' priority. - -config STM32L4_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32L4_DMA - ---help--- - 'High' priority. - -config STM32L4_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32L4_DMA - ---help--- - 'Medium' priority. - -config STM32L4_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32L4_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32L4_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32L4_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32L4_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32L4_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32L4_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endif - -comment "APB1 Peripherals" - -config STM32L4_PWR - bool "PWR" - default n - -config STM32L4_TIM2 - bool "TIM2" - default n - -config STM32L4_TIM3 - bool "TIM3" - default n - depends on STM32L4_HAVE_TIM3 - -config STM32L4_TIM4 - bool "TIM4" - default n - depends on STM32L4_HAVE_TIM4 - -config STM32L4_TIM5 - bool "TIM5" - default n - depends on STM32L4_HAVE_TIM5 - -config STM32L4_TIM6 - bool "TIM6" - default n - -config STM32L4_TIM7 - bool "TIM7" - default n - depends on STM32L4_HAVE_TIM7 - -config STM32L4_LCD - bool "LCD" - default n - depends on STM32L4_HAVE_LCD - -config STM32L4_SPI2 - bool "SPI2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select SPI - select STM32L4_SPI - -config STM32L4_SPI3 - bool "SPI3" - default n - select SPI - select STM32L4_SPI - -config STM32L4_LPUART1 - bool "LPUART1" - default n - depends on STM32L4_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART2 - bool "USART2" - default n - depends on STM32L4_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART3 - bool "USART3" - default n - depends on STM32L4_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART4 - bool "UART4" - default n - depends on STM32L4_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART5 - bool "UART5" - default n - depends on STM32L4_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_I2C1 - bool "I2C1" - default n - select STM32L4_I2C - -config STM32L4_I2C2 - bool "I2C2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_I2C - -config STM32L4_I2C3 - bool "I2C3" - default n - select STM32L4_I2C - -config STM32L4_I2C4 - bool "I2C4" - default n - select STM32L4_I2C - depends on STM32L4_HAVE_I2C4 - -config STM32L4_CAN1 - bool "CAN1" - default n - select CAN - select STM32L4_CAN - -config STM32L4_CAN2 - bool "CAN2" - default n - select CAN - select STM32L4_CAN - depends on STM32L4_HAVE_CAN2 - -config STM32L4_DAC1 - bool "DAC1" - default n - select STM32L4_DAC - -config STM32L4_DAC2 - bool "DAC2" - default n - select STM32L4_DAC - depends on STM32L4_HAVE_DAC2 - -config STM32L4_OPAMP - bool "OPAMP" - default n - -config STM32L4_LPTIM1 - bool "LPTIM1" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM1 - -config STM32L4_LPUART1 - bool "LPUART1" - default n - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - -config STM32L4_SWPMI - bool "SWPMI" - default n - -config STM32L4_LPTIM2 - bool "LPTIM2" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM2 - -config STM32L4_USBFS - bool "USB FS" - default n - depends on STM32L4_HAVE_USBFS - select USBDEV - -comment "APB2 Peripherals" - -config STM32L4_SYSCFG - bool "SYSCFG" - default y - -config STM32L4_FIREWALL - bool "FIREWALL" - default y - depends on STM32L4_SYSCFG - -config STM32L4_SDMMC1 - bool "SDMMC1" - default n - select ARCH_HAVE_SDIO - select SCHED_HPWORK - select STM32L4_SAI1PLL - select STM32L4_SDMMC - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - depends on STM32L4_HAVE_SDMMC1 - -config STM32L4_TIM1 - bool "TIM1" - default n - -config STM32L4_SPI1 - bool "SPI1" - default n - select SPI - select STM32L4_SPI - -config STM32L4_TIM8 - bool "TIM8" - default n - depends on STM32L4_HAVE_TIM8 - -config STM32L4_USART1 - bool "USART1" - default n - depends on STM32L4_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_TIM15 - bool "TIM15" - default n - -config STM32L4_TIM16 - bool "TIM16" - default n - -config STM32L4_TIM17 - bool "TIM17" - default n - depends on STM32L4_HAVE_TIM17 - -config STM32L4_COMP - bool "COMP" - default n - select COMP - depends on STM32L4_HAVE_COMP - -config STM32L4_SAI1 - bool "SAI1" - default n - depends on STM32L4_HAVE_SAI1 - -config STM32L4_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI2 - bool "SAI2" - default n - depends on STM32L4_HAVE_SAI2 - -config STM32L4_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_DFSDM1 - bool "DFSDM1" - default n - depends on STM32L4_HAVE_DFSDM1 - -comment "Other Peripherals" - -config STM32L4_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32L4_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32L4_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32L4_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L4_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 || STM32L4_STM32L4XR - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -choice - prompt "JTAG Configuration" - default STM32L4_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32L4_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32L4_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32L4_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32L4_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L4_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L4_RTC - -config STM32L4_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L4_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L4_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L4_RTC_LSECLOCK - depends on STM32L4_RTC - -config STM32L4_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L4_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L4_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L4_RTC_LSECLOCK - -config STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32L4_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L4_ONESHOT - bool - default y - -config STM32L4_FREERUN - bool - default y - -config STM32L4_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L4_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L4_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L4_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L4_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L4_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L4_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L4_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L4_LPTIM1_CLK_APB1 - -config STM32L4_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L4_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L4_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L4_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L4_LPTIM1_PWM - -config STM32L4_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L4_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L4_LPTIM2_CLK_APB1 - -config STM32L4_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L4_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L4_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L4_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32L4_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L4_TIM1 - select STM32L4_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM1_PWM - -config STM32L4_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32L4_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L4_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM1_CHANNEL4 - -config STM32L4_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM1_CHANNEL = 1 - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 1 - -if STM32L4_TIM1_CHANNEL = 2 - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 2 - -if STM32L4_TIM1_CHANNEL = 3 - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 3 - -if STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM1_PWM - -config STM32L4_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L4_TIM2 - select STM32L4_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM2_PWM - -config STM32L4_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM2_CHANNEL4 - -config STM32L4_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM2_CHANNEL = 1 - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL = 1 - -if STM32L4_TIM2_CHANNEL = 2 - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL = 2 - -if STM32L4_TIM2_CHANNEL = 3 - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL = 3 - -if STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM2_PWM - -config STM32L4_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L4_TIM3 - select STM32L4_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM3_PWM - -config STM32L4_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM3_CHANNEL4 - -config STM32L4_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM3_CHANNEL = 1 - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL = 1 - -if STM32L4_TIM3_CHANNEL = 2 - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL = 2 - -if STM32L4_TIM3_CHANNEL = 3 - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL = 3 - -if STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM3_PWM - -config STM32L4_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L4_TIM4 - select STM32L4_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM4_PWM - -config STM32L4_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM4_CHANNEL4 - -config STM32L4_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM4_CHANNEL = 1 - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL = 1 - -if STM32L4_TIM4_CHANNEL = 2 - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL = 2 - -if STM32L4_TIM4_CHANNEL = 3 - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL = 3 - -if STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM4_PWM - -config STM32L4_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L4_TIM5 - select STM32L4_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM5_PWM - -config STM32L4_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM5_CHANNEL4 - -config STM32L4_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM5_CHANNEL = 1 - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL = 1 - -if STM32L4_TIM5_CHANNEL = 2 - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL = 2 - -if STM32L4_TIM5_CHANNEL = 3 - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL = 3 - -if STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM5_PWM - -config STM32L4_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L4_TIM8 - select STM32L4_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM8_PWM - -config STM32L4_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM8_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32L4_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L4_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM8_CHANNEL4 - -config STM32L4_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM8_CHANNEL = 1 - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 1 - -if STM32L4_TIM8_CHANNEL = 2 - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 2 - -if STM32L4_TIM8_CHANNEL = 3 - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 3 - -if STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM8_PWM - -config STM32L4_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L4_TIM15 - select STM32L4_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM15_PWM - -config STM32L4_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32L4_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM15_CHANNEL2 - -config STM32L4_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM15_CHANNEL2 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32L4_TIM15_CHANNEL = 1 - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 1 - -if STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM15_PWM - -config STM32L4_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L4_TIM16 - select STM32L4_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM16_PWM - -config STM32L4_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32L4_TIM16_TDTS - int "TIM16 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM16_CHANNEL1 - -config STM32L4_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM16_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM16_PWM - -config STM32L4_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L4_TIM17 - select STM32L4_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM17_PWM - -config STM32L4_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32L4_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM17_CHANNEL1 - -config STM32L4_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM17_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM17_PWM - -if STM32L4_LPTIM1_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL1 - bool "LPTIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM1_CHANNEL1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM1_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL - int "LPTIM1 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM1_CHANNEL = 1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM1_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM1_PWM - -if STM32L4_LPTIM2_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL1 - bool "LPTIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM2_CHANNEL1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM2_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM2_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL - int "LPTIM2 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM2_CHANNEL = 1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM2_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L4_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L4_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32L4_TIM1 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32L4_TIM8 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32L4_TIM8_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM8_PULSECOUNT -config STM32L4_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L4_TIM1 && STM32L4_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM1_ADC1 - depends on STM32L4_TIM1_ADC - -config STM32L4_TIM1_ADC1 - bool "TIM1 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L4_TIM1_ADC2 - bool "TIM1 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L4_TIM1_ADC3 - bool "TIM1 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L4_TIM1_ADC_CHAN - int "TIM1 channel" - default 1 - range 1 4 - depends on STM32L4_TIM1_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L4_TIM2 && STM32L4_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM2_ADC1 - depends on STM32L4_TIM2_ADC - -config STM32L4_TIM2_ADC1 - bool "TIM2 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L4_TIM2_ADC2 - bool "TIM2 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L4_TIM2_ADC3 - bool "TIM2 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L4_TIM2_ADC_CHAN - int "TIM2 channel" - default 1 - range 1 4 - depends on STM32L4_TIM2_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L4_TIM3 && STM32L4_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM3_ADC1 - depends on STM32L4_TIM3_ADC - -config STM32L4_TIM3_ADC1 - bool "TIM3 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L4_TIM3_ADC2 - bool "TIM3 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L4_TIM3_ADC3 - bool "TIM3 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L4_TIM3_ADC_CHAN - int "TIM3 channel" - default 1 - range 1 4 - depends on STM32L4_TIM3_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L4_TIM4 && STM32L4_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM4_ADC1 - depends on STM32L4_TIM4_ADC - -config STM32L4_TIM4_ADC1 - bool "TIM4 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L4_TIM4_ADC2 - bool "TIM4 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L4_TIM4_ADC3 - bool "TIM4 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L4_TIM4_ADC_CHAN - int "TIM4 channel" - default 1 - range 1 4 - depends on STM32L4_TIM4_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L4_TIM6 && STM32L4_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM6_ADC1 - depends on STM32L4_TIM6_ADC - -config STM32L4_TIM6_ADC1 - bool "TIM6 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L4_TIM6_ADC2 - bool "TIM6 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L4_TIM6_ADC3 - bool "TIM6 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L4_TIM6_ADC_CHAN - int "TIM6 channel" - default 1 - range 1 4 - depends on STM32L4_TIM6_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L4_TIM8 && STM32L4_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM8_ADC1 - depends on STM32L4_TIM8_ADC - -config STM32L4_TIM8_ADC1 - bool "TIM8 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L4_TIM8_ADC2 - bool "TIM8 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L4_TIM8_ADC3 - bool "TIM8 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L4_TIM8_ADC_CHAN - int "TIM8 channel" - default 1 - range 1 4 - depends on STM32L4_TIM8_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L4_TIM15 && STM32L4_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM15_ADC1 - depends on STM32L4_TIM15_ADC - -config STM32L4_TIM15_ADC1 - bool "TIM15 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L4_TIM15_ADC2 - bool "TIM15 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L4_TIM15_ADC3 - bool "TIM15 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L4_TIM15_ADC_CHAN - int "TIM15 channel" - default 1 - range 1 4 - depends on STM32L4_TIM15_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_HAVE_ADC1_TIMER - bool - -config STM32L4_HAVE_ADC2_TIMER - bool - -config STM32L4_HAVE_ADC3_TIMER - bool - -config STM32L4_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L4_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L4_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L4_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L4_TIM1 && STM32L4_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L4_TIM1_DAC1 - depends on STM32L4_TIM1_DAC - -config STM32L4_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L4_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L4_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L4_TIM2 && STM32L4_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L4_TIM2_DAC1 - depends on STM32L4_TIM2_DAC - -config STM32L4_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L4_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L4_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L4_TIM3 && STM32L4_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L4_TIM3_DAC1 - depends on STM32L4_TIM3_DAC - -config STM32L4_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L4_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L4_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L4_TIM4 && STM32L4_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L4_TIM4_DAC1 - depends on STM32L4_TIM4_DAC - -config STM32L4_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L4_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L4_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L4_TIM5 && STM32L4_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L4_TIM5_DAC1 - depends on STM32L4_TIM5_DAC - -config STM32L4_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L4_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L4_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L4_TIM6 && STM32L4_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L4_TIM6_DAC1 - depends on STM32L4_TIM6_DAC - -config STM32L4_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L4_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L4_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L4_TIM7 && STM32L4_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L4_TIM7_DAC1 - depends on STM32L4_TIM7_DAC - -config STM32L4_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L4_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L4_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L4_TIM8 && STM32L4_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L4_TIM8_DAC1 - depends on STM32L4_TIM8_DAC - -config STM32L4_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L4_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L4_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L4_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L4_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L4_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L4_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L4_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L4_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32L4 TIMx Outputs Configuration" - -config STM32L4_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32L4_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32L4_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32L4_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32L4_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32L4_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32L4_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32L4_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32L4_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32L4_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32L4_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32L4_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32L4_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32L4_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32L4_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32L4_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32L4_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32L4_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32L4_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32L4_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32L4_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32L4_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32L4_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32L4_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32L4_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32L4_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32L4_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32L4_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32L4_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32L4_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32L4_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32L4_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32L4_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32L4_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32L4_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32L4_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32L4_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32L4_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32L4_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32L4_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32L4_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32L4_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32L4_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32L4_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32L4_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32L4_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32L4_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32L4_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32L4_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32L4_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32L4_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32L4_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32L4_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32L4_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32L4_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32L4_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32L4_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32L4_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32L4_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32L4_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32L4_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32L4_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32L4_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32L4_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32L4_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32L4_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32L4_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32L4_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32L4_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32L4_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32L4_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32L4_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32L4_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32L4_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32L4_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32L4_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32L4_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32L4_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32L4_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32L4_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32L4_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32L4_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32L4_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32L4_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32L4_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32L4_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32L4_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32L4_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32L4_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32L4_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32L4_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32L4_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32L4_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32L4_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32L4_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32L4_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32L4 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L4_ADC - -config STM32L4_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32L4_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32L4_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32L4_ADC_SMPR - int "ADC sample time" - default 0 - range 0 7 - ---help--- - ADC sample time - 0 - 2.5 ADC clock cycles - 1 - 6.5 ADC clock cycles - 2 - 12.5 ADC clock cycles - 3 - 24.5 ADC clock cycles - 4 - 47.5 ADC clock cycles - 5 - 92.5 ADC clock cycles - 6 - 247.5 ADC clock cycles - 7 - 640.5 ADC clock cycles - -config STM32L4_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32L4_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32L4_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32L4_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32L4_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L4_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32L4_ADC1_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32L4_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32L4_ADC1 && STM32L4_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L4_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32L4_ADC2_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32L4_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC2 && STM32L4_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L4_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32L4_ADC3_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32L4_ADC3_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC3 && STM32L4_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC1_INJ_CHAN - int "ADC1 configured injected channels" - depends on STM32L4_ADC1 - range 0 4 - default 0 - ---help--- - Number of configured ADC1 injected channels. - -config STM32L4_ADC2_INJ_CHAN - int "ADC2 configured injected channels" - depends on STM32L4_ADC2 - range 0 4 - default 0 - ---help--- - Number of configured ADC2 injected channels. - -config STM32L4_ADC3_INJ_CHAN - int "ADC3 configured injected channels" - depends on STM32L4_ADC3 - range 0 4 - default 0 - ---help--- - Number of configured ADC3 injected channels. - -config STM32L4_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L4_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L4_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -menu "STM32L4 ADCx triggering Configuration" - -config STM32L4_ADC1_EXTTRIG - int "ADC1 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_EXTTRIG > 0 - -config STM32L4_ADC1_EXTSEL - int "ADC1 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC2_EXTTRIG - int "ADC2 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_EXTTRIG > 0 - -config STM32L4_ADC2_EXTSEL - int "ADC2 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC3_EXTTRIG - int "ADC3 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_EXTTRIG > 0 - -config STM32L4_ADC3_EXTSEL - int "ADC3 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -if STM32L4_ADC1_INJ_CHAN > 0 - -config STM32L4_ADC1_JEXTTRIG - int "ADC1 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_JEXTTRIG > 0 - -config STM32L4_ADC1_JEXTSEL - int "ADC1 External Trigger Selection for injected group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC2_INJ_CHAN > 0 - -config STM32L4_ADC2_JEXTTRIG - int "ADC2 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_JEXTTRIG > 0 - -config STM32L4_ADC2_JEXTSEL - int "ADC2 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC3_INJ_CHAN > 0 - -config STM32L4_ADC3_JEXTTRIG - int "ADC3 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_JEXTTRIG > 0 - -config STM32L4_ADC3_JEXTSEL - int "ADC3 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -endmenu #STM32L4 ADCx triggering Configuration - -endmenu - -menu "DAC Configuration" - depends on STM32L4_DAC - -config STM32L4_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L4_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC1_DMA - -config STM32L4_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L4_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L4_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L4_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L4_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L4_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC2_DMA - -config STM32L4_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L4_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L4_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L4_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32L4_DAC_LL_OPS - bool "DAC low-level operations" - default n - ---help--- - Enable low-level DAC ops. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L4_DFSDM1 - -config STM32L4_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L4_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L4_SERIALDRIVER - bool - -config STM32L4_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L4_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L4_LPUART1_SERIALDRIVER - depends on STM32L4_LPUART1 - -config STM32L4_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L4_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L4_LPUART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L4_USART1_SERIALDRIVER - depends on STM32L4_USART1 - -config STM32L4_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L4_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L4_USART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L4_USART2_SERIALDRIVER - depends on STM32L4_USART2 - -config STM32L4_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L4_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L4_USART2 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L4_USART3_SERIALDRIVER - depends on STM32L4_USART3 - -config STM32L4_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L4_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L4_USART3 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L4_UART4_SERIALDRIVER - depends on STM32L4_UART4 - -config STM32L4_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L4_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L4_UART4 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L4_UART5_SERIALDRIVER - depends on STM32L4_UART5 - -config STM32L4_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L4_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L4_UART5 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L4_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L4_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L4_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L4_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L4_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L4_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L4_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L4_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L4_USART && STM32L4_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L4 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L4_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L4_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L4 serial driver. - -config STM32L4_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L4_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L4 serial driver. - -config STM32L4_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L4_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L4 serial driver. - -if PM - -config STM32L4_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L4_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L4_SPI - -config STM32L4_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L4_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L4_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L4_I2C - -config STM32L4_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L4_SDMMC - -config STM32L4_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L4_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L4_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L4_SDMMC1 - -config STM32L4_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L4_CAN1 || STM32L4_CAN2 - -config STM32L4_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L4_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L4_CAN1 is defined. - -config STM32L4_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L4_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L4_CAN2 is defined. - -config STM32L4_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L4_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L4_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L4_TIM1 || STM32L4_TIM2 || STM32L4_TIM3 || STM32L4_TIM4 || STM32L4_TIM5 || STM32L4_TIM8 - -config STM32L4_TIM1_QE - bool "TIM1" - default n - depends on STM32L4_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L4_TIM1_QE - -config STM32L4_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM2_QE - bool "TIM2" - default n - depends on STM32L4_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L4_TIM2_QE - -config STM32L4_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM3_QE - bool "TIM3" - default n - depends on STM32L4_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L4_TIM3_QE - -config STM32L4_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM4_QE - bool "TIM4" - default n - depends on STM32L4_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L4_TIM4_QE - -config STM32L4_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM5_QE - bool "TIM5" - default n - depends on STM32L4_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L4_TIM5_QE - -config STM32L4_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM8_QE - bool "TIM8" - default n - depends on STM32L4_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L4_TIM8_QE - -config STM32L4_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L4_QENCODER_SAMPLE_FDTS_4 - -config STM32L4_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L4_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L4_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L4_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L4_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L4_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel event count" - default STM32L4_QENCODER_SAMPLE_EVENT_6 - -config STM32L4_QENCODER_SAMPLE_EVENT_1 - depends on STM32L4_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L4_QENCODER_SAMPLE_EVENT_2 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L4_QENCODER_SAMPLE_EVENT_4 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L4_QENCODER_SAMPLE_EVENT_5 - depends on STM32L4_QENCODER_SAMPLE_FDTS_16 || STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L4_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L4_QENCODER_SAMPLE_FDTS && !STM32L4_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L4_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L4_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L4_SAI - -choice - prompt "Operation mode" - default STM32L4_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L4_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L4_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L4_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L4_SAI1_BOTH_ASYNC - depends on STM32L4_SAI1_A && STM32L4_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L4_SAI2_BOTH_ASYNC - depends on STM32L4_SAI2_A && STM32L4_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L4 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 3d981681ff023..d7609705c50fb 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -50,11 +50,11 @@ else CHIP_CSRCS += stm32l4_tickless.c endif -ifeq ($(CONFIG_STM32L4_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32L4_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32l4_freerun.c endif @@ -62,37 +62,37 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif -ifeq ($(CONFIG_STM32L4_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32l4_hsi48.c endif -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32l4_adc.c endif -ifeq ($(CONFIG_STM32L4_DAC),y) +ifeq ($(CONFIG_STM32_DAC),y) CHIP_CSRCS += stm32l4_dac.c endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) +ifeq ($(CONFIG_STM32_DFSDM),y) CHIP_CSRCS += stm32l4_dfsdm.c endif -ifeq ($(CONFIG_STM32L4_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32l4_dma.c endif ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32L4_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32l4_usbdev.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfsdev.c endif endif ifeq ($(CONFIG_USBHOST),y) -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfshost.c endif endif @@ -116,11 +116,11 @@ CHIP_CSRCS += stm32l4_pminitialize.c endif endif -ifeq ($(CONFIG_STM32L4_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32l4_exti_pwr.c endif -ifeq ($(CONFIG_STM32L4_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32l4_exti_alarm.c endif @@ -137,27 +137,27 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32l4_dumpgpio.c endif -ifeq ($(CONFIG_STM32L4_COMP),y) +ifeq ($(CONFIG_STM32_COMP),y) CHIP_CSRCS += stm32l4_comp.c stm32l4_exti_comp.c endif -ifeq ($(CONFIG_STM32L4_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32l4_rng.c endif -ifeq ($(CONFIG_STM32L4_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif -ifeq ($(CONFIG_STM32L4_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32l4_lptim.c endif -ifeq ($(CONFIG_STM32L4_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_STM32L4_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32l4_pulsecount.c endif @@ -165,26 +165,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32l4_qencoder.c endif -ifeq ($(CONFIG_STM32L4_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c endif -ifeq ($(CONFIG_STM32L4_CAN),y) +ifeq ($(CONFIG_STM32_CAN),y) CHIP_CSRCS += stm32l4_can.c endif -ifeq ($(CONFIG_STM32L4_FIREWALL),y) +ifeq ($(CONFIG_STM32_FIREWALL),y) CHIP_CSRCS += stm32l4_firewall.c endif -ifeq ($(CONFIG_STM32L4_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32l4_iwdg.c endif -ifeq ($(CONFIG_STM32L4_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CHIP_CSRCS += stm32l4_sdmmc.c endif -ifeq ($(CONFIG_STM32L4_1WIREDRIVER),y) +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) CHIP_CSRCS += stm32l4_1wire.c endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index 6c57bb1f099dd..edd726b262648 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H /**************************************************************************** * Included Files @@ -612,4 +612,4 @@ # define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index 0393e70882e28..e64073321a201 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H /**************************************************************************** * Included Files @@ -471,4 +471,4 @@ #define DFSDM_CNVTIMR_CNVCNT_SHIFT (4) /* Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK */ #define DFSDM_CNVTIMR_CNVCNT_MASK (~0xfu) -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_DFSDM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index f338d5cb69269..7a14fe18fb8dc 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H /**************************************************************************** * Included Files @@ -311,4 +311,4 @@ # define FLASH_CFGR_LVEN (1 << 0) /* Bit 0: Low voltage enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index 6c374c5295c1a..7adfe4082c203 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -232,4 +232,4 @@ #define STM32_SCS_BASE 0xe000e000 #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index 3031f5fcf8d55..09be34e1e027e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H /**************************************************************************** * Included Files @@ -212,4 +212,4 @@ # define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */ #endif -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index 3a5a79c698a8e..e3adb9b3109dc 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H /**************************************************************************** * Included Files @@ -252,4 +252,4 @@ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ #endif /* CONFIG_STM32_STM32L4X2 */ -#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index 2584166f1882e..da39bab518e9e 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32L4_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H /**************************************************************************** * Included Files @@ -626,4 +626,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf, #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_ADC_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 2ba3530405420..1a4d5e9731578 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32L4_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H /**************************************************************************** * Included Files @@ -124,4 +124,4 @@ struct can_dev_s *stm32_caninitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 33f09fdffc702..aa0768b5a3cd9 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H -#define __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H /**************************************************************************** * Included Files @@ -332,4 +332,4 @@ struct adc_dev_s *stm32_dfsdm_initialize(int intf, #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_DFSDM */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_DFSDM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index ee546e37c1961..c1aeacf7afdcb 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H /**************************************************************************** * Included Files @@ -141,4 +141,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #endif #endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_FREERUN_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index 6c6bee8d2e0d7..de78d9f6be944 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H /**************************************************************************** * Included Files @@ -93,4 +93,4 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_HSI48_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 16b15a75a5f8e..d8e77479d2080 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H /**************************************************************************** * Included Files @@ -195,4 +195,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, #endif #endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_ONESHOT_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index 7d91fee2009c8..9a930afa96238 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H /**************************************************************************** * Included Files @@ -117,4 +117,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 5df747e22295c..71fa1ed14689a 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32L4_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H /* The STM32L4 does not have dedicated PWM hardware. Rather, pulsed output * control is a capability of the STM32L4 timers. The logic in this file @@ -1074,4 +1074,4 @@ struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_TIMx_PWM */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index d81c8b573709f..3e6f059093630 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H -#define __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H /**************************************************************************** * Included Files @@ -127,4 +127,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_QSPI */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_QSPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 92e214791ae26..af354a7bd7d72 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -24,8 +24,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32L4_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H #include #include @@ -313,4 +313,4 @@ struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_RTC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index a0fa0b24f9c24..d38e24247ceda 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H -#define __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H +#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H +#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H /**************************************************************************** * Included Files @@ -205,4 +205,4 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS && CONFIG_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_USBHOST_H */ +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig index bc12730b68138..43733a0c041cd 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig @@ -8,8 +8,8 @@ if ARCH_BOARD_B_L475E_IOT01A config B_L475E_IOT01A_MTD_FLASH bool "MTD driver for external 64Mbits flash memory" default n - select STM32L4_DMA1 - select STM32L4_QSPI + select STM32_DMA1 + select STM32_QSPI select MTD select MTD_MX25RXX select MTD_SMART diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig index 7fbc7b18e1f88..39a2d9d018f1f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -40,8 +41,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32L4_QSPI_FLASH_SIZE=8388608 -CONFIG_STM32L4_USART1=y +CONFIG_STM32_QSPI_FLASH_SIZE=8388608 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig index 180321aac4b50..3ad6b86f7b6a3 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -85,8 +86,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig index 63f9c072fd5c6..fe4ac62a657d6 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -76,8 +77,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig index fd31a0624c1b8..de16e10426d22 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -87,8 +88,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/Kconfig b/boards/arm/stm32l4/nucleo-l432kc/Kconfig index 7ed758a07d748..ba154e7dd9494 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/Kconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/Kconfig @@ -6,13 +6,13 @@ if ARCH_BOARD_NUCLEO_L432KC menu "U[S]ART Pin Layouts" - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_LPUART1 + depends on STM32_USART1 || STM32_USART2 || STM32_LPUART1 comment "USART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART1 + depends on !STM32_USART1 choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 RX pin" default ARCH_BOARD_USART1_RX_PA10 ---help--- @@ -29,7 +29,7 @@ config ARCH_BOARD_USART1_RX_PB7 endchoice choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 TX pin" default ARCH_BOARD_USART1_TX_PA9 ---help--- @@ -46,10 +46,10 @@ config ARCH_BOARD_USART1_TX_PB6 endchoice comment "USART2 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART2 + depends on !STM32_USART2 choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 RX pin" default ARCH_BOARD_USART2_RX_PA15 ---help--- @@ -66,7 +66,7 @@ config ARCH_BOARD_USART2_RX_PA15 endchoice choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 TX pin" default ARCH_BOARD_USART2_TX_PA2 ---help--- @@ -79,10 +79,10 @@ config ARCH_BOARD_USART2_TX_PA2 endchoice comment "LPUART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_LPUART1 + depends on !STM32_LPUART1 choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 RX pin" default ARCH_BOARD_LPUART1_RX_PA3 ---help--- @@ -94,7 +94,7 @@ config ARCH_BOARD_LPUART1_RX_PA3 endchoice choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 TX pin" default ARCH_BOARD_LPUART1_TX_PA2 ---help--- @@ -142,7 +142,7 @@ config NUCLEOL432KC_SPWM_PHASE_NUM endif menuconfig NUCLEOL432KC_DAC_WGEN - depends on (STM32L4_DAC_LL_OPS) && (STM32L4_DAC1_DMA) && (STM32L4_TIM2_DAC) + depends on (STM32_DAC_LL_OPS) && (STM32_DAC1_DMA) && (STM32_TIM2_DAC) bool "Sinusoidal DAC wave generator example" default n diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig index a897ae2145b2c..dbc3a0ea493d7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig index 91ef99032a184..19d272a0fd50e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig @@ -5,11 +5,12 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_STM32L4_SYSCFG is not set +# CONFIG_STM32_SYSCFG is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_HIPRI_INTERRUPT=y @@ -36,17 +37,17 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWM_LL_OPS=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_CH1NOUT=y -CONFIG_STM32L4_TIM1_CH1OUT=y -CONFIG_STM32L4_TIM1_PWM=y -CONFIG_STM32L4_TIM6=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_READLINE=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig index 433b98f9aab67..498038354779f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,23 +48,23 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DAC1_DMA=y -CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE=40 -CONFIG_STM32L4_DAC1_TIMER=2 -CONFIG_STM32L4_DAC1_TIMER_FREQUENCY=2000 -CONFIG_STM32L4_DAC_LL_OPS=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM2=y -CONFIG_STM32L4_TIM2_DAC=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1_DMA=y +CONFIG_STM32_DAC1_DMA_BUFFER_SIZE=40 +CONFIG_STM32_DAC1_TIMER=2 +CONFIG_STM32_DAC1_TIMER_FREQUENCY=2000 +CONFIG_STM32_DAC_LL_OPS=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_DAC=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt index 4a419a020455d..374e99abc251b 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_DEV_GPIO) list(APPEND SRCS stm32_gpio.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32_dac.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile b/boards/arm/stm32l4/nucleo-l432kc/src/Makefile index 10e16a6729f53..6f1745c753a13 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l432kc/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += stm32_gpio.c endif -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32L4_DAC),y) +ifeq ($(CONFIG_STM32_DAC),y) CSRCS += stm32_dac.c endif diff --git a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig index 98f401ba27ac3..096df36781741 100644 --- a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l452re" CONFIG_ARCH_BOARD_NUCLEO_L452RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L452RE=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,20 +57,20 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig index 4850d96906598..09c040793ff80 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig index 648c01ff163cf..f71159d49eb92 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -53,16 +54,16 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_CMDDATA=y CONFIG_START_YEAR=2017 -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig index 9a6ea2b69d599..71cee2c8a19c6 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l496zg" CONFIG_ARCH_BOARD_NUCLEO_L496ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L496ZG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -57,35 +58,35 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_ADC1_EXTTRIG=1 -CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY=1000 -CONFIG_STM32L4_ADC2=y -CONFIG_STM32L4_ADC2_DMA=y -CONFIG_STM32L4_ADC3=y -CONFIG_STM32L4_ADC3_DMA=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_FSMC=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C2=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_I2C4=y -CONFIG_STM32L4_LPUART1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_ADC=y -CONFIG_STM32L4_USART2=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_EXTTRIG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1000 +CONFIG_STM32_ADC2=y +CONFIG_STM32_ADC2_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_DMA=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt index 3e922a252e9ef..fb76edca235e3 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt @@ -42,7 +42,7 @@ endif() if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) - if(CONFIG_STM32L4_DFSDM) + if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32_dfsdm.c) endif() endif() @@ -55,7 +55,7 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile b/boards/arm/stm32l4/nucleo-l496zg/src/Makefile index 5170327a0612b..4516af4433cb7 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l496zg/src/Makefile @@ -44,7 +44,7 @@ endif ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c - ifeq ($(CONFIG_STM32L4_DFSDM),y) + ifeq ($(CONFIG_STM32_DFSDM),y) CSRCS += stm32_dfsdm.c endif endif @@ -57,7 +57,7 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig index 135cc3d507056..fb9fe5e39144a 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -37,7 +38,7 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig index 8a7ad6bdecd6c..a5db2db05187d 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -40,9 +41,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_OTGFS=y -CONFIG_STM32L4_SAI1PLL=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SAI1PLL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt index 88aa47097ced8..2a3de594681ee 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_ARCH_LEDS) list(APPEND SRCS stm32_autoleds.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile b/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile index e46d406cb3eb9..80a41f0fa3875 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile @@ -28,7 +28,7 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig index 875e7b30a1792..a3ccc532ef2a9 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476-mdk" CONFIG_ARCH_BOARD_STM32L476_MDK=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,14 +49,14 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt index f47dc052ac4dc..5390a86c1210e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt +++ b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_userleds.c) -if(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile b/boards/arm/stm32l4/stm32l476-mdk/src/Makefile index 0aba6ed8c09d0..66a39c742290b 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile +++ b/boards/arm/stm32l4/stm32l476-mdk/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_userleds.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig index 9ee1fcccd70b7..8e0327c72286a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -52,15 +53,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig index 9bab580b6f0a9..8f07bd33dcf5d 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,15 +56,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile index a2438eee63bd8..aa94c8d033ccd 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig index 020cf49a74023..9c6cfd36dfa3a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,17 +56,17 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig index b2e29c4a53539..ca695bde26d45 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,18 +57,18 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile index 47936292ad5fb..377448e664a8f 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif @@ -39,10 +39,10 @@ CSRCS += stm32_buttons.c endif ifeq ($(CONFIG_ADC),y) -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) +ifeq ($(CONFIG_STM32_DFSDM),y) CSRCS += stm32_dfsdm.c endif endif @@ -51,11 +51,11 @@ ifeq ($(CONFIG_DAC),y) CSRCS += stm32_dac.c endif -ifeq ($(CONFIG_STM32L4_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif From 2f6988ab0a0fecb4c6589ce089bfd82147b1cbeb Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:41 +0200 Subject: [PATCH 16/52] !arm/stm32l5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32L5 Kconfig symbols were renamed from CONFIG_STM32L5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32l5/boards/nucleo-l552ze/index.rst | 4 +- .../stm32l5/boards/stm32l562e-dk/index.rst | 8 +- arch/arm/src/stm32l5/CMakeLists.txt | 2 +- arch/arm/src/stm32l5/Kconfig | 3232 +---------------- arch/arm/src/stm32l5/Make.defs | 2 +- arch/arm/src/stm32l5/hardware/stm32l5_flash.h | 6 +- arch/arm/src/stm32l5/hardware/stm32l5_spi.h | 6 +- .../nucleo-l552ze/configs/nsh/defconfig | 7 +- .../stm32l562e-dk/configs/nsh/defconfig | 5 +- 9 files changed, 57 insertions(+), 3215 deletions(-) diff --git a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst index fcc67d7977d2c..663867803175e 100644 --- a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst @@ -104,7 +104,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L5_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 @@ -126,7 +126,7 @@ Solder Bridges (active by default on Nucleo-L552ZE-Q):: Use make menuconfig to configure LPUART1 as the console:: - CONFIG_STM32L5_LPUART1=y + CONFIG_STM32_LPUART1=y CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_RXBUFSIZE=256 CONFIG_LPUART1_TXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst index 6769e7af2288e..ddba39b1801f0 100644 --- a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst @@ -84,7 +84,7 @@ the STLINK Virtual COM Port. Use make menuconfig to configure USART1 as the console:: - CONFIG_STM32L5_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -220,9 +220,9 @@ NOTES: output on USART1, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART1=y - CONFIG_STM32L5_USART1_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index 18f0fdaf03cf9..4f10e5e8aa18e 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -61,7 +61,7 @@ endif() # Required chip type specific files -if(CONFIG_STM32L5_STM32L562XX) +if(CONFIG_STM32_STM32L562XX) list(APPEND SRCS stm32l562xx_rcc.c) endif() diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 4a7589a116ad5..bece5610c34cf 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -7,6 +7,15 @@ if ARCH_CHIP_STM32L5 comment "STM32L5 Configuration Options" +config STM32_L5_PERIPHERALS + bool + default y + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + choice prompt "STM32 L5 Chip Selection" default ARCH_CHIP_STM32L552ZE @@ -14,16 +23,16 @@ choice config ARCH_CHIP_STM32L552ZE bool "STM32L552ZE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Z ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM config ARCH_CHIP_STM32L562QE bool "STM32L562QE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Q ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -32,3243 +41,74 @@ endchoice # STM32 L5 Chip Selection # Chip families: -config STM32L5_STM32L562XX - # STM32L552 and STM32L562 devices documented in RM0439 +# STM32L552 and STM32L562 devices documented in RM0439 +config STM32_STM32L562XX bool default n select ARCH_HAVE_FPU - select STM32L5_HAVE_LPUART1 - select STM32L5_HAVE_USART1 - select STM32L5_HAVE_USART2 - select STM32L5_HAVE_USART3 - select STM32L5_HAVE_UART4 - select STM32L5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L5 - default STM32L5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32L5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L5_FLASH_CONFIG_8 - bool - default n - depends on STM32L5_STM32L512XX - -config STM32L5_FLASH_CONFIG_B - bool - default n - depends on STM32L5_STM32L5X1 || STM32L5_STM32L5X3 - -config STM32L5_FLASH_CONFIG_C - bool - default n - depends on !STM32L5_STM32L596XX - -config STM32L5_FLASH_CONFIG_E - bool - default n + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX -config STM32L5_FLASH_CONFIG_G - bool - default n - depends on STM32L5_STM32L5X5 || STM32L5_STM32L5X6 - -config STM32L5_FLASH_CONFIG_I - bool - default n - depends on STM32L5_STM32L5XR # Pin/package configurations config STM32L5_IO_CONFIG_K + # Package designator K bool default n config STM32L5_IO_CONFIG_T + # Package designator T bool default n config STM32L5_IO_CONFIG_C + # Package designator C bool default n config STM32L5_IO_CONFIG_R + # Package designator R bool default n config STM32L5_IO_CONFIG_J + # Package designator J bool default n config STM32L5_IO_CONFIG_M + # Package designator M bool default n config STM32L5_IO_CONFIG_V + # Package designator V bool default n config STM32L5_IO_CONFIG_Q + # Package designator Q bool default n config STM32L5_IO_CONFIG_Z + # Package designator Z bool default n config STM32L5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32L5 SRAM2 Options" - -config STM32L5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L5_SRAM2_INIT - ---help--- - The STM32L5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -comment "STM32L5 Peripherals" - -menu "STM32L5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32L5_HAVE_LPUART1 - bool - default n - -config STM32L5_HAVE_USART1 - bool - default n - -config STM32L5_HAVE_USART2 - bool - default n - -config STM32L5_HAVE_USART3 - bool - default n - -config STM32L5_HAVE_UART4 - bool - default n - -config STM32L5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L5_SPI - bool - default n - -config STM32L5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -comment "AHB2 Peripherals" - -comment "AHB3 Peripherals" - -comment "APB1 Peripherals" - -config STM32L5_PWR - bool "PWR" - default n - -config STM32L5_RTC - bool "RTC" - default n - -config STM32L5_SPI2 - bool "SPI2" - default n - select SPI - select STM32L5_SPI - -config STM32L5_SPI3 - bool "SPI3" - default n - select SPI - select STM32L5_SPI - -config STM32L5_LPUART1 - bool "LPUART1" - default n - depends on STM32L5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART2 - bool "USART2" - default n - depends on STM32L5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART3 - bool "USART3" - default n - depends on STM32L5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART4 - bool "UART4" - default n - depends on STM32L5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART5 - bool "UART5" - default n - depends on STM32L5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -comment "APB2 Peripherals" - -config STM32L5_SYSCFG - bool "SYSCFG" - default y - -config STM32L5_SPI1 - bool "SPI1" - default n - select SPI - select STM32L5_SPI - -config STM32L5_USART1 - bool "USART1" - default n - depends on STM32L5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -endmenu - -config STM32L5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L5_HAVE_SAI2 - ---help--- - The STM32L5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L5_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L5_RTC - -config STM32L5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L5_RTC_LSECLOCK - depends on STM32L5_RTC - -config STM32L5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L5_RTC_LSECLOCK - -config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32L5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L5_ONESHOT - bool - default y - -config STM32L5_FREERUN - bool - default y - -config STM32L5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L5_LPTIM1_CLK_APB1 - -config STM32L5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L5_LPTIM1_PWM - -config STM32L5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L5_LPTIM2_CLK_APB1 - -config STM32L5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L5_LPTIM2_PWM - -config STM32L5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L5_TIM1 - select PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM1_PWM - -config STM32L5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM1_CHANNEL5 - -config STM32L5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM1_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM1_PWM - -config STM32L5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L5_TIM2 - select PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM2_PWM - -config STM32L5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM2_CHANNEL5 - -config STM32L5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM2_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM2_PWM - -config STM32L5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L5_TIM3 - select PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM3_PWM - -config STM32L5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM3_CHANNEL5 - -config STM32L5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM3_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM3_PWM - -config STM32L5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L5_TIM4 - select PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM4_PWM - -config STM32L5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM4_CHANNEL5 - -config STM32L5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM4_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM4_PWM - -config STM32L5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L5_TIM5 - select PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM5_PWM - -config STM32L5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM5_CHANNEL5 - -config STM32L5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM5_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM5_PWM - -config STM32L5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L5_TIM8 - select PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM8_PWM - -config STM32L5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM8_CHANNEL5 - -config STM32L5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM8_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM8_PWM - -config STM32L5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L5_TIM15 - select PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM15_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM15_CHANNEL2 - -config STM32L5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM15_CHANNEL2 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32L5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM15_PWM - -config STM32L5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L5_TIM16 - select PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM16_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM16_CHANNEL1 - -config STM32L5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM16_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM16_PWM - -config STM32L5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L5_TIM17 - select PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM17_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM17_CHANNEL1 - -config STM32L5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM17_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM17_PWM - -config STM32L5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L5_TIM1 && STM32L5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32L5_TIM1_ADC1 - depends on STM32L5_TIM1_ADC - -config STM32L5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L5_TIM2 && STM32L5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32L5_TIM2_ADC1 - depends on STM32L5_TIM2_ADC - -config STM32L5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L5_TIM3 && STM32L5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32L5_TIM3_ADC1 - depends on STM32L5_TIM3_ADC - -config STM32L5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L5_TIM4 && STM32L5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32L5_TIM4_ADC1 - depends on STM32L5_TIM4_ADC - -config STM32L5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L5_TIM6 && STM32L5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32L5_TIM6_ADC1 - depends on STM32L5_TIM6_ADC - -config STM32L5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L5_TIM8 && STM32L5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32L5_TIM8_ADC1 - depends on STM32L5_TIM8_ADC - -config STM32L5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L5_TIM15 && STM32L5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32L5_TIM15_ADC1 - depends on STM32L5_TIM15_ADC - -config STM32L5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L5_HAVE_ADC1_TIMER - bool - -config STM32L5_HAVE_ADC2_TIMER - bool - -config STM32L5_HAVE_ADC3_TIMER - bool - -config STM32L5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L5_TIM1 && STM32L5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L5_TIM1_DAC1 - depends on STM32L5_TIM1_DAC - -config STM32L5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L5_TIM2 && STM32L5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L5_TIM2_DAC1 - depends on STM32L5_TIM2_DAC - -config STM32L5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L5_TIM3 && STM32L5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L5_TIM3_DAC1 - depends on STM32L5_TIM3_DAC - -config STM32L5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L5_TIM4 && STM32L5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L5_TIM4_DAC1 - depends on STM32L5_TIM4_DAC - -config STM32L5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L5_TIM5 && STM32L5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L5_TIM5_DAC1 - depends on STM32L5_TIM5_DAC - -config STM32L5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L5_TIM6 && STM32L5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L5_TIM6_DAC1 - depends on STM32L5_TIM6_DAC - -config STM32L5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L5_TIM7 && STM32L5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L5_TIM7_DAC1 - depends on STM32L5_TIM7_DAC - -config STM32L5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L5_TIM8 && STM32L5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L5_TIM8_DAC1 - depends on STM32L5_TIM8_DAC - -config STM32L5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L5_ADC - -config STM32L5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L5_ADC1 && STM32L5_DFSDM1 && (STM32L5_STM32L596XX || STM32L5_STM32L5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L5_ADC2 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L5_ADC3 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32L5_DAC - -config STM32L5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC1_DMA - -config STM32L5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC2_DMA - -config STM32L5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L5_DFSDM1 - -config STM32L5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L5_SERIALDRIVER - bool - -config STM32L5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L5_LPUART1_SERIALDRIVER - depends on STM32L5_LPUART1 - -config STM32L5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L5_LPUART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L5_USART1_SERIALDRIVER - depends on STM32L5_USART1 - -config STM32L5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L5_USART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L5_USART2_SERIALDRIVER - depends on STM32L5_USART2 - -config STM32L5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L5_USART2 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L5_USART3_SERIALDRIVER - depends on STM32L5_USART3 - -config STM32L5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L5_USART3 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L5_UART4_SERIALDRIVER - depends on STM32L5_UART4 - -config STM32L5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L5_UART4 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L5_UART5_SERIALDRIVER - depends on STM32L5_UART5 - -config STM32L5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L5_UART5 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L5_USART1 || STM32L5_USART2 || STM32L5_USART3 || STM32L5_UART4 || STM32L5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L5_USART && STM32L5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L5 serial driver. - -config STM32L5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L5 serial driver. - -config STM32L5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L5 serial driver. - -if PM - -config STM32L5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L5_SPI - -config STM32L5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L5_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L5_I2C - -config STM32L5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L5_SDMMC - -config STM32L5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L5_SDMMC1 - -config STM32L5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L5_CAN1 || STM32L5_CAN2 - -config STM32L5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L5_CAN1 is defined. - -config STM32L5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L5_CAN2 is defined. - -config STM32L5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L5_TIM1 || STM32L5_TIM2 || STM32L5_TIM3 || STM32L5_TIM4 || STM32L5_TIM5 || STM32L5_TIM8 - -config STM32L5_TIM1_QE - bool "TIM1" - default n - depends on STM32L5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L5_TIM1_QE - -config STM32L5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM2_QE - bool "TIM2" - default n - depends on STM32L5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L5_TIM2_QE - -config STM32L5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM3_QE - bool "TIM3" - default n - depends on STM32L5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L5_TIM3_QE - -config STM32L5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM4_QE - bool "TIM4" - default n - depends on STM32L5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L5_TIM4_QE - -config STM32L5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM5_QE - bool "TIM5" - default n - depends on STM32L5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L5_TIM5_QE - -config STM32L5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM8_QE - bool "TIM8" - default n - depends on STM32L5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L5_TIM8_QE - -config STM32L5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L5_QENCODER_SAMPLE_FDTS_4 - -config STM32L5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel event count" - default STM32L5_QENCODER_SAMPLE_EVENT_6 - -config STM32L5_QENCODER_SAMPLE_EVENT_1 - depends on STM32L5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L5_QENCODER_SAMPLE_EVENT_2 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L5_QENCODER_SAMPLE_EVENT_4 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L5_QENCODER_SAMPLE_EVENT_5 - depends on STM32L5_QENCODER_SAMPLE_FDTS_16 || STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L5_QENCODER_SAMPLE_FDTS && !STM32L5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L5_SAI - -choice - prompt "Operation mode" - default STM32L5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L5_SAI1_BOTH_ASYNC - depends on STM32L5_SAI1_A && STM32L5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L5_SAI2_BOTH_ASYNC - depends on STM32L5_SAI2_A && STM32L5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L5 diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index e9f17420e4ccf..4c69a8265bc2b 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -56,6 +56,6 @@ endif # Required chip type specific files -ifeq ($(CONFIG_STM32L5_STM32L562XX),y) +ifeq ($(CONFIG_STM32_STM32L562XX),y) CHIP_CSRCS += stm32l562xx_rcc.c endif diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index a5618fbecc200..ba67ec89f81b7 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H /**************************************************************************** * Included Files @@ -259,4 +259,4 @@ #define FLASH_OPTR_RDP_NSDBG (0x55 << FLASH_OPTR_RDP_SHIFT) #define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_FLASH_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index 5f7f9e8abe2be..1e8eba96ff992 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H /**************************************************************************** * Included Files @@ -164,4 +164,4 @@ # define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_SPI_H */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig index 14235ae113610..f92e3c47ba9e2 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig +++ b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-l552ze" CONFIG_ARCH_BOARD_NUCLEO_L552ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L552ZE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,9 +50,9 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_LPUART1=y -CONFIG_STM32L5_RTC=y -CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig index 2edfa787c5e64..6f19b7f98747e 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig +++ b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig @@ -10,9 +10,10 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l562e-dk" CONFIG_ARCH_BOARD_STM32L562E_DK=y -CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L562QE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,7 +45,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y From 7cda36c763f436983ebad7e95d2f0b2a58d13e1c Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 17/52] !arm/stm32u5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32U5 Kconfig symbols were renamed from CONFIG_STM32U5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32u5/boards/b-u585i-iot02a/index.rst | 6 +- arch/arm/src/stm32u5/Kconfig | 3628 +---------------- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 44 +- arch/arm/src/stm32u5/stm32_tim.c | 332 +- .../b-u585i-iot02a/configs/nsh/defconfig | 9 +- .../stm32u5/b-u585i-iot02a/src/CMakeLists.txt | 2 +- .../arm/stm32u5/b-u585i-iot02a/src/Makefile | 2 +- .../b-u585i-iot02a/src/stm32_clockconfig.c | 2 +- .../nucleo-u5a5zj-q/configs/nsh/defconfig | 17 +- .../nucleo-u5a5zj-q/src/CMakeLists.txt | 2 +- .../arm/stm32u5/nucleo-u5a5zj-q/src/Makefile | 2 +- .../nucleo-u5a5zj-q/src/stm32_clockconfig.c | 2 +- 12 files changed, 339 insertions(+), 3709 deletions(-) diff --git a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst index 38846fffccc57..60af81e77fa91 100644 --- a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst +++ b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst @@ -102,9 +102,9 @@ NOTES: output on USART3, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART3=y - CONFIG_STM32L5_USART3_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART3=y + CONFIG_STM32_USART3_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 0a6b6cff64f4f..0f90a5c3ef66c 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -7,6 +7,65 @@ if ARCH_CHIP_STM32U5 comment "STM32U5 Configuration Options" +config STM32_U5_PERIPHERALS + bool + default y + select STM32_HAVE_COMP + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA2D + select STM32_HAVE_FMAC + select STM32_HAVE_FSMC + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OTGFS if STM32_STM32U535XX || CONFIG_STM32_STM32U545XX || STM32_STM32U575XX || STM32_STM32U585XX + select STM32_HAVE_RNG + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_GPADMA1 + select STM32_HAVE_MDF1 + select STM32_HAVE_FLASH + select STM32_HAVE_RAMCFG + select STM32_HAVE_GTZC1 + select STM32_HAVE_GTZC2 + select STM32_HAVE_DCACHE1 + select STM32_HAVE_SRAM1 + select STM32_HAVE_SRAM2 + select STM32_HAVE_SRAM3 + select STM32_HAVE_SRAM5 + select STM32_HAVE_DCMI_PSSI + select STM32_HAVE_PKA + select STM32_HAVE_SAES + select STM32_HAVE_OCTOSPIM + select STM32_HAVE_OTFDEC1 + select STM32_HAVE_OTFDEC2 + select STM32_HAVE_OCTOSPI1 + select STM32_HAVE_OCTOSPI2 + select STM32_HAVE_LPGPIO1 + select STM32_HAVE_LPDMA1 + select STM32_HAVE_ADF1 + select STM32_HAVE_UCPD1 + select STM32_HAVE_VREF + select STM32_HAVE_RTCAPB + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 U5 Chip Selection" default ARCH_CHIP_STM32U585AI @@ -14,15 +73,15 @@ choice config ARCH_CHIP_STM32U585AI bool "STM32U585AI" - select STM32U5_STM32U585XX - select STM32U5_FLASH_CONFIG_I + select STM32_STM32U585XX + select STM32_FLASH_CONFIG_I select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 2048 Kb FLASH, 768 Kb SRAM config ARCH_CHIP_STM32U5A5ZJT bool "STM32U5A5ZJT" - select STM32U5_STM32U5A5XX + select STM32_STM32U5A5XX select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 4096 Kb FLASH, 2500 Kb SRAM, tqfp144 @@ -31,3551 +90,120 @@ endchoice # STM32 U5 Chip Selection # Chip families: -config STM32U5_STM32U5A5XX - # STM32U575 and STM32U585 devices documented in RM0456 +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U5A5XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -config STM32U5_STM32U585XX - # STM32U575 and STM32U585 devices documented in RM0456 + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C5 + select STM32_HAVE_I2C6 + +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U585XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32U5 - default STM32U5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32U5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32U585AI is chosen, the Flash configuration would be 'I', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32U5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32U5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32U5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32U5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32U5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32U5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32U5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32U5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32U5_FLASH_CONFIG_8 - bool - default n - -config STM32U5_FLASH_CONFIG_B - bool - default n - -config STM32U5_FLASH_CONFIG_C - bool - default n - -config STM32U5_FLASH_CONFIG_E - bool - default n - -config STM32U5_FLASH_CONFIG_G - bool - default n + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX + select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32U5_FLASH_CONFIG_I - bool - default n # Pin/package configurations config STM32U5_IO_CONFIG_K + # Package designator K bool default n config STM32U5_IO_CONFIG_T + # Package designator T bool default n config STM32U5_IO_CONFIG_C + # Package designator C bool default n config STM32U5_IO_CONFIG_R + # Package designator R bool default n config STM32U5_IO_CONFIG_J + # Package designator J bool default n config STM32U5_IO_CONFIG_M + # Package designator M bool default n config STM32U5_IO_CONFIG_V + # Package designator V bool default n config STM32U5_IO_CONFIG_Q + # Package designator Q bool default n config STM32U5_IO_CONFIG_Z + # Package designator Z bool default n config STM32U5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32U5 Peripherals" - -menu "STM32U5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32U5_HAVE_LPUART1 - bool - default n - -config STM32U5_HAVE_USART1 - bool - default n - -config STM32U5_HAVE_USART2 - bool - default n - -config STM32U5_HAVE_USART3 - bool - default n - -config STM32U5_HAVE_UART4 - bool - default n - -config STM32U5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32U5_SPI - bool - default n - -config STM32U5_PWM - bool - default n - -config STM32U5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32U5_GPADMA1 - bool "GPADMA1" - default n - -config STM32U5_CORDIC - bool "CORDIC" - default n - -config STM32U5_FMAC - bool "FMAC" - default n - -config STM32U5_MDF1 - bool "MDF1" - default n - -config STM32U5_FLASH - bool "FLASH" - default n - -config STM32U5_CRC - bool "CRC" - default n - -config STM32U5_TSC - bool "TSC" - default n - -config STM32U5_RAMCFG - bool "RAMCFG" - default n - -config STM32U5_DMA2D - bool "DMA2D" - default n - -config STM32U5_GTZC1 - bool "GTZC1" - default n - -config STM32U5_BKPSRAM - bool "BKPSRAM" - default n - -config STM32U5_DCACHE1 - bool "DCACHE1" - default n - -config STM32U5_SRAM1 - bool "SRAM1" - default y - -config STM32U5_SRAM2 - bool "SRAM2" - default n - -config STM32U5_SRAM3 - bool "SRAM3" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -config STM32U5_SRAM5 - bool "SRAM5" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -comment "SRAM Options" - -config STM32U5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - depends on STM32U5_SRAM2 - select STM32U5_SRAM2_INIT - ---help--- - The STM32U5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32U5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - depends on STM32U5_SRAM2 - ---help--- - The STM32U5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32U5_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32U5_SRAM3 - default n - -config STM32U5_SRAM5_HEAP - bool "SRAM5 is used for heap" - depends on STM32U5_SRAM5 - default n - -comment "AHB2 Peripherals" - -config STM32U5_ADC1 - bool "ADC1" - default n - -config STM32U5_DCMI_PSSI - bool "DCMI_PSSI" - default n - -config STM32U5_OTGFS - bool "OTG FS" - depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX || STM32U5_STM32U575XX || STM32U5_STM32U585XX - default n - -config STM32U5_OTGHS - bool "OTG HS" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - -config STM32U5_AES - bool "AES" - default n - -config STM32U5_HASH - bool "HASH" - default n - -config STM32U5_RNG - bool "RNG" - default n - -config STM32U5_PKA - bool "PKA" - default n - -config STM32U5_SAES - bool "SAES" - default n - -config STM32U5_OCTOSPIM - bool "OCTOSPIM" - default n - -config STM32U5_OTFDEC1 - bool "OTFDEC1" - default n - -config STM32U5_OTFDEC2 - bool "OTFDEC2" - default n - -config STM32U5_SDMMC1 - bool "SDMMC1" - default n - -config STM32U5_SDMMC2 - bool "SDMMC2" - default n - -config STM32U5_FSMC - bool "FSMC" - default n - -config STM32U5_OCTOSPI1 - bool "OCTOSPI1" - default n - -config STM32U5_OCTOSPI2 - bool "OCTOSPI2" - default n - -comment "AHB3 Peripherals" - -config STM32U5_LPGPIO1 - bool "LPGPIO1" - default n - -config STM32U5_PWR - bool "PWR" - default n - -config STM32U5_ADC4 - bool "ADC4" - default n - -config STM32U5_DAC1 - bool "DAC1" - default n - -config STM32U5_LPDMA1 - bool "LPDMA1" - default n - -config STM32U5_ADF1 - bool "ADF1" - default n - -config STM32U5_GTZC2 - bool "GTZC2" - default n - -comment "APB1 Peripherals" - -config STM32U5_TIM2 - bool "TIM2" - default n - -config STM32U5_TIM3 - bool "TIM3" - default n - -config STM32U5_TIM4 - bool "TIM4" - default n - -config STM32U5_TIM5 - bool "TIM5" - default n - -config STM32U5_TIM6 - bool "TIM6" - default n - -config STM32U5_TIM7 - bool "TIM7" - default n - -config STM32U5_WWDG - bool "WWDG" - default n - -config STM32U5_SPI2 - bool "SPI2" - default n - select SPI - select STM32U5_SPI - -config STM32U5_USART2 - bool "USART2" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_I2C1 - bool "I2C1" - default n - select STM32U5_I2C - -config STM32U5_I2C2 - bool "I2C2" - default n - select STM32U5_I2C - -config STM32U5_I2C3 - bool "I2C3" - default n - select STM32U5_I2C - -config STM32U5_I2C4 - bool "I2C4" - default n - select STM32U5_I2C - -config STM32U5_I2C5 - bool "I2C5" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_I2C6 - bool "I2C6" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_CRS - bool "CRS" - default n - -config STM32U5_LPTIM2 - bool "LPTIM2" - default n - -config STM32U5_FDCAN1 - bool "FDCAN1" - default n - -config STM32U5_UCPD1 - bool "UCPD1" - default n - -comment "APB2 Peripherals" - -config STM32U5_TIM1 - bool "TIM1" - default n - -config STM32U5_SPI1 - bool "SPI1" - default n - select SPI - select STM32U5_SPI - -config STM32U5_TIM8 - bool "TIM8" - default n - -config STM32U5_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_TIM15 - bool "TIM15" - default n - -config STM32U5_TIM16 - bool "TIM16" - default n - -config STM32U5_TIM17 - bool "TIM17" - default n - -config STM32U5_SAI1 - bool "SAI1" - default n - -config STM32U5_SAI2 - bool "SAI2" - default n - -comment "APB3 Peripherals" - -config STM32U5_SYSCFG - bool "SYSCFG" - default y - -config STM32U5_SPI3 - bool "SPI3" - default n - select SPI - select STM32U5_SPI - -config STM32U5_LPUART1 - bool "LPUART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_LPTIM1 - bool "LPTIM1" - default n - -config STM32U5_LPTIM3 - bool "LPTIM3" - default n - -config STM32U5_LPTIM4 - bool "LPTIM4" - default n - -config STM32U5_OPAMP - bool "OPAMP" - default n - -config STM32U5_COMP - bool "COMP" - default n - -config STM32U5_VREF - bool "VREF" - default n - -config STM32U5_RTCAPB - bool "RTCAPB" - default n - -endmenu - -config STM32U5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32U5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32U5_HAVE_SAI2 - ---help--- - The STM32U5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "RTC Configuration" - depends on STM32U5_RTC - -config STM32U5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32U5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32U5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32U5_RTC_LSECLOCK - depends on STM32U5_RTC - -config STM32U5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32U5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32U5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32U5_RTC_LSECLOCK - -config STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32U5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32U5_ONESHOT - bool - default y - -config STM32U5_FREERUN - bool - default y - -config STM32U5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32U5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32U5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32U5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32U5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32U5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32U5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32U5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32U5_LPTIM1_CLK_APB1 - -config STM32U5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32U5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32U5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32U5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32U5_LPTIM1_PWM - -config STM32U5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32U5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32U5_LPTIM2_CLK_APB1 - -config STM32U5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32U5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32U5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32U5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32U5_LPTIM2_PWM - -config STM32U5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32U5_TIM1 - select STM32U5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM1_PWM - -config STM32U5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32U5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM1_CHANNEL5 - -config STM32U5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM1_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM1_PWM - -config STM32U5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32U5_TIM2 - select STM32U5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM2_PWM - -config STM32U5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM2_CHANNEL5 - -config STM32U5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM2_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM2_PWM - -config STM32U5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32U5_TIM3 - select STM32U5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM3_PWM - -config STM32U5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM3_CHANNEL5 - -config STM32U5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM3_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM3_PWM - -config STM32U5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32U5_TIM4 - select STM32U5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM4_PWM - -config STM32U5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM4_CHANNEL5 - -config STM32U5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM4_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM4_PWM - -config STM32U5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32U5_TIM5 - select STM32U5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM5_PWM - -config STM32U5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM5_CHANNEL5 - -config STM32U5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM5_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM5_PWM - -config STM32U5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32U5_TIM8 - select STM32U5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM8_PWM - -config STM32U5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32U5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM8_CHANNEL5 - -config STM32U5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM8_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM8_PWM - -config STM32U5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32U5_TIM15 - select STM32U5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM15_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM15_CHANNEL2 - -config STM32U5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM15_CHANNEL2 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32U5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM15_PWM - -config STM32U5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32U5_TIM16 - select STM32U5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM16_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM16_CHANNEL1 - -config STM32U5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM16_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM16_PWM - -config STM32U5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32U5_TIM17 - select STM32U5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM17_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM17_CHANNEL1 - -config STM32U5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM17_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM17_PWM - -config STM32U5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32U5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32U5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32U5_TIM1 && STM32U5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32U5_TIM1_ADC1 - depends on STM32U5_TIM1_ADC - -config STM32U5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32U5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32U5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32U5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32U5_TIM2 && STM32U5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32U5_TIM2_ADC1 - depends on STM32U5_TIM2_ADC - -config STM32U5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32U5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32U5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32U5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32U5_TIM3 && STM32U5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32U5_TIM3_ADC1 - depends on STM32U5_TIM3_ADC - -config STM32U5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32U5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32U5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32U5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32U5_TIM4 && STM32U5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32U5_TIM4_ADC1 - depends on STM32U5_TIM4_ADC - -config STM32U5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32U5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32U5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32U5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32U5_TIM6 && STM32U5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32U5_TIM6_ADC1 - depends on STM32U5_TIM6_ADC - -config STM32U5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32U5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32U5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32U5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32U5_TIM8 && STM32U5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32U5_TIM8_ADC1 - depends on STM32U5_TIM8_ADC - -config STM32U5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32U5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32U5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32U5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32U5_TIM15 && STM32U5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32U5_TIM15_ADC1 - depends on STM32U5_TIM15_ADC - -config STM32U5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32U5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32U5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32U5_HAVE_ADC1_TIMER - bool - -config STM32U5_HAVE_ADC2_TIMER - bool - -config STM32U5_HAVE_ADC3_TIMER - bool - -config STM32U5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32U5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32U5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32U5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32U5_TIM1 && STM32U5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32U5_TIM1_DAC1 - depends on STM32U5_TIM1_DAC - -config STM32U5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32U5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32U5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32U5_TIM2 && STM32U5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32U5_TIM2_DAC1 - depends on STM32U5_TIM2_DAC - -config STM32U5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32U5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32U5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32U5_TIM3 && STM32U5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32U5_TIM3_DAC1 - depends on STM32U5_TIM3_DAC - -config STM32U5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32U5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32U5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32U5_TIM4 && STM32U5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32U5_TIM4_DAC1 - depends on STM32U5_TIM4_DAC - -config STM32U5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32U5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32U5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32U5_TIM5 && STM32U5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32U5_TIM5_DAC1 - depends on STM32U5_TIM5_DAC - -config STM32U5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32U5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32U5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32U5_TIM6 && STM32U5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32U5_TIM6_DAC1 - depends on STM32U5_TIM6_DAC - -config STM32U5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32U5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32U5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32U5_TIM7 && STM32U5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32U5_TIM7_DAC1 - depends on STM32U5_TIM7_DAC - -config STM32U5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32U5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32U5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32U5_TIM8 && STM32U5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32U5_TIM8_DAC1 - depends on STM32U5_TIM8_DAC - -config STM32U5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32U5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32U5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32U5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32U5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32U5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32U5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32U5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32U5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32U5_ADC - -config STM32U5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32U5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32U5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32U5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32U5_ADC1 && STM32U5_DFSDM1 && (STM32U5_STM32U596XX || STM32U5_STM32U5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32U5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32U5_ADC2 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32U5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32U5_ADC3 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32U5_DAC - -config STM32U5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32U5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC1_DMA - -config STM32U5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32U5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32U5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32U5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32U5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32U5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC2_DMA - -config STM32U5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32U5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32U5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32U5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32U5_DFSDM1 - -config STM32U5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32U5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32U5_SERIALDRIVER - bool - -config STM32U5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32U5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32U5_LPUART1_SERIALDRIVER - depends on STM32U5_LPUART1 - -config STM32U5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32U5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32U5_LPUART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32U5_USART1_SERIALDRIVER - depends on STM32U5_USART1 - -config STM32U5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32U5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32U5_USART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32U5_USART2_SERIALDRIVER - depends on STM32U5_USART2 - -config STM32U5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32U5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32U5_USART2 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32U5_USART3_SERIALDRIVER - depends on STM32U5_USART3 - -config STM32U5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32U5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32U5_USART3 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32U5_UART4_SERIALDRIVER - depends on STM32U5_UART4 - -config STM32U5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32U5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32U5_UART4 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32U5_UART5_SERIALDRIVER - depends on STM32U5_UART5 - -config STM32U5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32U5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32U5_UART5 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32U5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32U5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32U5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32U5_USART1 || STM32U5_USART2 || STM32U5_USART3 || STM32U5_UART4 || STM32U5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32U5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32U5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32U5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32U5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32U5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32U5_USART && STM32U5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32U5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32U5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32U5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32U5 serial driver. - -config STM32U5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32U5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32U5 serial driver. - -config STM32U5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32U5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32U5 serial driver. - -if PM - -config STM32U5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32U5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32U5_SPI - -config STM32U5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32U5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32U5_SPI_INTERRUPT. - -endmenu - -config STM32U5_I2C - bool - default n - -menu "I2C Configuration" - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32U5_I2C - -config STM32U5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32U5_SDMMC - -config STM32U5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32U5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32U5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32U5_SDMMC1 - -config STM32U5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32U5_CAN1 || STM32U5_CAN2 - -config STM32U5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32U5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32U5_CAN1 is defined. - -config STM32U5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32U5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32U5_CAN2 is defined. - -config STM32U5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32U5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32U5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32U5_TIM1 || STM32U5_TIM2 || STM32U5_TIM3 || STM32U5_TIM4 || STM32U5_TIM5 || STM32U5_TIM8 - -config STM32U5_TIM1_QE - bool "TIM1" - default n - depends on STM32U5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32U5_TIM1_QE - -config STM32U5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM2_QE - bool "TIM2" - default n - depends on STM32U5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32U5_TIM2_QE - -config STM32U5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM3_QE - bool "TIM3" - default n - depends on STM32U5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32U5_TIM3_QE - -config STM32U5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM4_QE - bool "TIM4" - default n - depends on STM32U5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32U5_TIM4_QE - -config STM32U5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM5_QE - bool "TIM5" - default n - depends on STM32U5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32U5_TIM5_QE - -config STM32U5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM8_QE - bool "TIM8" - default n - depends on STM32U5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32U5_TIM8_QE - -config STM32U5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32U5_QENCODER_SAMPLE_FDTS_4 - -config STM32U5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32U5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32U5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32U5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32U5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32U5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel event count" - default STM32U5_QENCODER_SAMPLE_EVENT_6 - -config STM32U5_QENCODER_SAMPLE_EVENT_1 - depends on STM32U5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32U5_QENCODER_SAMPLE_EVENT_2 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32U5_QENCODER_SAMPLE_EVENT_4 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32U5_QENCODER_SAMPLE_EVENT_5 - depends on STM32U5_QENCODER_SAMPLE_FDTS_16 || STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32U5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32U5_QENCODER_SAMPLE_FDTS && !STM32U5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32U5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32U5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32U5_SAI - -choice - prompt "Operation mode" - default STM32U5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32U5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32U5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32U5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32U5_SAI1_BOTH_ASYNC - depends on STM32U5_SAI1_A && STM32U5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32U5_SAI2_BOTH_ASYNC - depends on STM32U5_SAI2_A && STM32U5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32U5 diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 3cb7aec33dcc3..45fb42dedce68 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) -#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) -#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) -#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) -#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) -#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) -#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) -#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) -#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) -#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) -#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) +#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) +#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) +#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) +#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) +#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) +#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) +#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) +#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) +#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) +#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) +#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 66879e72e8a2a..090ed0cb4d573 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -305,16 +305,16 @@ static const struct stm32_tim_ops_s stm32_tim_ops = struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32_tim_priv_s stm32_tim8_priv = struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32_tim_priv_s stm32_tim15_priv = struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32_tim_priv_s stm32_tim16_priv = struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, + .mode = STM32U5_TIM_MODE_UNUSED, + .base = STM32U5_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32_TIM_CH_MODE_MASK) + if (mode & STM32U5_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE +#if STM32U5_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE #endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE +#if STM32U5_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE #endif -#if STM32_NBTIM > 0 +#if STM32U5_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32_TIM_MODE_MASK) + switch (mode & STM32U5_TIM_MODE_MASK) { - case STM32_TIM_MODE_DISABLED: + case STM32U5_TIM_MODE_DISABLED: val = 0; break; - case STM32_TIM_MODE_DOWN: + case STM32U5_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32_TIM_MODE_UP: + case STM32U5_TIM_MODE_UP: break; - case STM32_TIM_MODE_UPDOWN: + case STM32U5_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32_TIM_MODE_PULSE: + case STM32U5_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); -#if STM32_NATIM > 0 +#if STM32U5_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: + case STM32U5_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: + case STM32U5_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: + case STM32U5_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: + case STM32U5_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: + case STM32U5_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: + case STM32U5_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: + case STM32U5_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: + case STM32U5_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: + case STM32U5_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: + case STM32U5_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: + case STM32U5_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: + case STM32U5_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: + case STM32U5_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: + case STM32U5_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: + case STM32U5_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: + case STM32U5_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: + case STM32U5_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: + case STM32U5_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: + case STM32U5_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: + case STM32U5_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: + case STM32U5_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: + case STM32U5_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: + case STM32U5_TIM2_BASE: #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: + case STM32U5_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE +#if STM32U5_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE #endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE +#if STM32U5_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE #endif -#if STM32_NBTIM > 0 +#if STM32U5_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32_TIM_CH_MODE_MASK) + switch (mode & STM32U5_TIM_CH_MODE_MASK) { - case STM32_TIM_CH_DISABLED: + case STM32U5_TIM_CH_DISABLED: break; - case STM32_TIM_CH_OUTPWM: + case STM32U5_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32_TIM_CH_POLARITY_NEG) + if (mode & STM32U5_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: + case STM32U5_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: + case STM32U5_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: + case STM32U5_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: + case STM32U5_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: + case STM32U5_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: + case STM32U5_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: + case STM32U5_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: + case STM32U5_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: + case STM32U5_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; + case STM32U5_TIM1_BASE: + vectorno = STM32U5_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; + case STM32U5_TIM2_BASE: + vectorno = STM32U5_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; + case STM32U5_TIM3_BASE: + vectorno = STM32U5_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; + case STM32U5_TIM4_BASE: + vectorno = STM32U5_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; + case STM32U5_TIM5_BASE: + vectorno = STM32U5_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; + case STM32U5_TIM6_BASE: + vectorno = STM32U5_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; + case STM32U5_TIM7_BASE: + vectorno = STM32U5_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; + case STM32U5_TIM8_BASE: + vectorno = STM32U5_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; + case STM32U5_TIM15_BASE: + vectorno = STM32U5_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; + case STM32U5_TIM16_BASE: + vectorno = STM32U5_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; + case STM32U5_TIM17_BASE: + vectorno = STM32U5_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) #ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32U5_TIM1_BASE: + modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32U5_TIM2_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32U5_TIM3_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32U5_TIM4_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32U5_TIM5_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32U5_TIM6_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32U5_TIM7_BASE: + modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32U5_TIM8_BASE: + modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32U5_TIM15_BASE: + modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32U5_TIM16_BASE: + modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32U5_TIM17_BASE: + modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; return OK; } diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig index 74b6940237b58..eabf176d3fde5 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig +++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-u585i-iot02a" CONFIG_ARCH_BOARD_B_U585I_IOT02A=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U585AI=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SPI1=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SPITOOL=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt index a845f39aefe01..150aef2e64720 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile index 0a32978916af9..915275f7e6f75 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c index fb7cc8153096e..378c5ec51c799 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c @@ -38,7 +38,7 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig index a489a5a0284cf..62d5aa14537ff 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-u5a5zj-q" CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_CHIP_STM32U5A5ZJT=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,14 +48,14 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SRAM2=y -CONFIG_STM32U5_SRAM2_HEAP=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_SRAM3_HEAP=y -CONFIG_STM32U5_SRAM5=y -CONFIG_STM32U5_SRAM5_HEAP=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SRAM2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_SRAM3_HEAP=y +CONFIG_STM32_SRAM5=y +CONFIG_STM32_SRAM5_HEAP=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt index fa6b58b12dc9d..0ab477f594668 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile index 1fa94c46e61d5..93d9723add326 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c index bfeb3ec7d5746..976a515f7b4e3 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c @@ -38,7 +38,7 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ From db91e3b1e505798243a9ccbd59e1912139b5696b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:42 +0200 Subject: [PATCH 18/52] !arm/stm32wb: use common STM32 Kconfig symbols BREAKING CHANGE: STM32WB Kconfig symbols were renamed from CONFIG_STM32WB_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- arch/arm/include/stm32wb/chip.h | 18 +- arch/arm/src/stm32wb/CMakeLists.txt | 18 +- arch/arm/src/stm32wb/Kconfig | 1129 ++--------------- arch/arm/src/stm32wb/Make.defs | 18 +- arch/arm/src/stm32wb/hardware/stm32wb_flash.h | 54 +- arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 160 +-- arch/arm/src/stm32wb/hardware/stm32wb_i2c.h | 72 +- arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 50 +- .../src/stm32wb/hardware/stm32wbxx_pinmap.h | 86 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 92 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 6 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 6 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 1 + arch/arm/src/stm32wb/stm32wb_rtc.h | 12 +- arch/arm/src/stm32wb/stm32wb_timerisr.c | 4 +- .../stm32wb/flipperzero/configs/nsh/defconfig | 11 +- .../nucleo-wb55rg/configs/ble/defconfig | 11 +- .../nucleo-wb55rg/configs/nimble/defconfig | 11 +- .../nucleo-wb55rg/configs/nsh/defconfig | 9 +- 19 files changed, 430 insertions(+), 1338 deletions(-) diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 8d933ab8957fa..6945832aab647 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -53,7 +53,7 @@ # define STM32_NI2C 2 /* I2C1, I2C3 */ # define STM32_NUSBOTG 1 /* USB 2.0 FS */ # define STM32_NCMP 2 /* Two Comparators */ -# if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +# if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define STM32_NSPI 3 /* SPI1-2, QSPI */ # else # define STM32_NSPI 2 /* SPI1, QSPI */ @@ -74,7 +74,7 @@ # define STM32_NLPUART 0 /* No LPUART */ #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define STM32_NCAPSENSE 18 /* Capacitive sensing channels */ #else # define STM32_NCAPSENSE 0 /* No Capacitive sensing */ @@ -100,15 +100,15 @@ #define STM32_NRNG 1 /* Random number generator (RNG) */ #define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ -#if defined(CONFIG_STM32_IO_CONFIG_C) +#if defined(CONFIG_STM32WB_IO_CONFIG_C) # define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */ -#elif defined(CONFIG_STM32_IO_CONFIG_C_48E) +#elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E) # define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */ -#elif defined(CONFIG_STM32_IO_CONFIG_C_49) +#elif defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define STM32_NGPIO 25 /* GPIO[A,B,C,H] */ -#elif defined(CONFIG_STM32_IO_CONFIG_R) +#elif defined(CONFIG_STM32WB_IO_CONFIG_R) # define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ -#elif defined(CONFIG_STM32_IO_CONFIG_V) +#elif defined(CONFIG_STM32WB_IO_CONFIG_V) # define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ #else # error "Unsupported STM32WB chip" @@ -147,12 +147,12 @@ # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) #elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \ - && defined(CONFIG_STM32_IO_CONFIG_C) + && defined(CONFIG_STM32WB_IO_CONFIG_C) # define STM32_SRAM1_SIZE (64*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) #elif defined(CONFIG_STM32_STM32WB55) && \ - (defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V)) + (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) # define STM32_SRAM1_SIZE (192*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 79f82cf8573c4..c9646782740b8 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -55,11 +55,11 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32WB_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32WB_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32wb_freerun.c) endif() @@ -67,11 +67,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() -if(CONFIG_STM32WB_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32wb_rcc_hsi48.c) endif() -if(CONFIG_STM32WB_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32wb_dma.c) endif() @@ -84,11 +84,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32WB_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32wb_exti_pwr.c) endif() -if(CONFIG_STM32WB_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32wb_exti_alarm.c) endif() @@ -100,15 +100,15 @@ if(CONFIG_STM32WB_RTC) endif() endif() -if(CONFIG_STM32WB_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wb_ipcc.c) endif() -if(CONFIG_STM32WB_MBOX) +if(CONFIG_STM32_MBOX) list(APPEND SRCS stm32wb_mbox.c) endif() -if(CONFIG_STM32WB_BLE) +if(CONFIG_STM32_BLE) list(APPEND SRCS stm32wb_blehci.c) endif() diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index aba177dfed921..f9cdaae492a86 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -7,6 +7,23 @@ if ARCH_CHIP_STM32WB comment "STM32WB Configuration Options" +config STM32_WB_PERIPHERALS + bool + default ARCH_CHIP_STM32WB + select STM32_HAVE_BLE + select STM32_HAVE_DMA1 + select STM32_HAVE_MBOX + select STM32_HAVE_SRAM2A + select STM32_HAVE_SRAM2B + select STM32_HAVE_I2C1 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 if STM32_HAVE_LPUART + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART1_RXDMA if STM32_DMA + choice prompt "STM32 WB Chip Selection" default ARCH_CHIP_STM32WB55RG @@ -14,129 +31,129 @@ choice config ARCH_CHIP_STM32WB10CC bool "STM32WB10CC" - select STM32WB_STM32WB10 + select STM32_STM32WB10 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB15CC bool "STM32WB15CC" - select STM32WB_STM32WB15 + select STM32_STM32WB15 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB30CE bool "STM32WB30CE" - select STM32WB_STM32WB30 + select STM32_STM32WB30 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB50CG bool "STM32WB50CG" - select STM32WB_STM32WB50 + select STM32_STM32WB50 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CC bool "STM32WB35CC" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CE bool "STM32WB35CE" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CC bool "STM32WB55CC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RC bool "STM32WB55RC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VC bool "STM32WB55VC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CE bool "STM32WB55CE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RE bool "STM32WB55RE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VE bool "STM32WB55VE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VY bool "STM32WB55VY" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_Y_640 + select STM32_FLASH_CONFIG_Y ---help--- STM32 WB Cortex M4, 640 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CG bool "STM32WB55CG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RG bool "STM32WB55RG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VG bool "STM32WB55VG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM @@ -144,137 +161,82 @@ endchoice # STM32 WB Chip Selection # Chip product lines -config STM32WB_STM32WB10 +config STM32_STM32WB10 # STM32WB10 Value Line bool default n - select STM32WB_HAVE_TSC + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC -config STM32WB_STM32WB15 +config STM32_STM32WB15 # STM32WB15 Standard Line bool default n - select STM32WB_HAVE_TSC - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC + select STM32_HAVE_LPUART + select STM32_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE -config STM32WB_STM32WB30 +config STM32_STM32WB30 # STM32WB30 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB50 +config STM32_STM32WB50 # STM32WB50 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB35 +config STM32_STM32WB35 # STM32WB35 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_SMPS - -config STM32WB_STM32WB55 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_SMPS + +config STM32_STM32WB55 # STM32WB55 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_LCD - select STM32WB_HAVE_SMPS - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WB - default STM32WB_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WB series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 or 320 - E 512 - Y 640 - G 1024 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32WB Chip Selection. - - Examples: - If the STM32WB55RG is chosen, the Flash configuration would be 'G', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32WB Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WB_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WB_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32WB_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32WB_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32WB_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32WB_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WB_FLASH_CONFIG_C_256 - bool - default n - -config STM32WB_FLASH_CONFIG_C_320 - bool - default n - -config STM32WB_FLASH_CONFIG_E_512 - bool - default n - -config STM32WB_FLASH_CONFIG_Y_640 - bool - default n + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_LPUART + select STM32_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_LCD + select STM32_HAVE_SMPS -config STM32WB_FLASH_CONFIG_G_1024 - bool - default n # Pin/package configurations @@ -282,13 +244,13 @@ config STM32WB_IO_CONFIG_C # UFQFPN48 package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_48E # UFQFPN48E package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_49 # WLCSP49 package @@ -299,889 +261,14 @@ config STM32WB_IO_CONFIG_R # VFQFPN68 package bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_V # WLCSP100 and UFBGA129 packages bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE - -comment "STM32WB SRAM2a and SRAM2b Options" - -config STM32WB_SRAM2A_HEAP - bool "SRAM2a is used for heap" - default n - -config STM32WB_SRAM2A_USER_BASE_OFFSET - int "SRAM2a user application base offset" - default 2048 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The beginning part of the SRAM2a memory can be used by RF stack. The - available space for the user application can be obtained from the - release notes for STM32WB coprocessor wireless binaries. - -config STM32WB_SRAM2A_USER_SIZE - int "SRAM2a user application size" - default 8192 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The ending part of the SRAM2a memory contains a secure section, which - cannot be read nor written by CPU1. The secure start address for the - SRAM2a memory can be read from the SBRSA option byte. When CPU2 update - support required, there must be some free sectors just below the secure - memory to support CPU2 firmware updates requiring more sectors to be - secure. - -config STM32WB_SRAM2A_INIT - bool "SRAM2a is initialized to zero" - default y - depends on STM32WB_SRAM2A_HEAP - ---help--- - The STM32WB SRAM2a region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2a is being retained in Standby mode, this may be - undesirable (because it will destroy the contents). In that case, the board - should handle the initialization itself at the appropriate time. - -config STM32WB_SRAM2B_HEAP - bool "SRAM2b is used for heap" - default n - -config STM32WB_SRAM2B_USER_SIZE - int "SRAM2b user application size" - default 32768 - range 0 32768 - depends on STM32WB_SRAM2B_HEAP - ---help--- - For any CPU2 firmware supporting the BLE protocol the ending part of - the SRAM2b memory contains a secure section, which cannot be read nor - written by CPU1. The secure start address for the SRAM2b memory can be - read from the SNBRSA option byte. When CPU2 update support required, - there must be some free sectors just below the secure memory to support - CPU2 firmware updates requiring more sectors to be secure. The SRAM2b - memory is all secure for any CPU2 firmware supporting the Thread protocol. - -config STM32WB_SRAM2B_INIT - bool "SRAM2b is initialized to zero" - default y - depends on STM32WB_SRAM2B_HEAP - ---help--- - The STM32WB SRAM2b region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - -comment "STM32WB Peripherals" - -menu "STM32WB Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WB_GPIO_HAVE_PORTD - bool - default n - -config STM32WB_GPIO_HAVE_PORTE - bool - default n - -config STM32WB_HAVE_COMP - bool - default n - -config STM32WB_HAVE_LPUART - bool - default n - -config STM32WB_HAVE_DMA2 - bool - default n - -config STM32WB_HAVE_TIM16 - bool - default n - -config STM32WB_HAVE_TIM17 - bool - default n - -config STM32WB_HAVE_SPI2 - bool - default n - -config STM32WB_HAVE_I2C3 - bool - default n - -config STM32WB_HAVE_SAI - bool - default n - -config STM32WB_HAVE_LCD - bool - default n - -config STM32WB_HAVE_TSC - bool - default n - -config STM32WB_HAVE_USB - bool - default n - -config STM32WB_HAVE_QSPI - bool - default n - -config STM32WB_HAVE_SMPS - bool - default n - -# These are the peripheral selections proper - -config STM32WB_RTC - bool "RTC" - default n - select RTC - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WB_ADC - bool - default n - -config STM32WB_DMAMUX - bool - default n - -config STM32WB_DMA - bool - default n - select STM32WB_DMAMUX - -config STM32WB_IPCC - bool - default n - -config STM32WB_I2C - bool - default n - -config STM32WB_SAI - bool - default n - -config STM32WB_SPI - bool - default n - -config STM32WB_USART - bool - default n - -config STM32WB_LPTIM - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32WB_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_DMA2 - bool "DMA2" - default n - depends on STM32WB_HAVE_DMA2 - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_CRC - bool "CRC" - default n - -comment "APB1 Peripherals" - -config STM32WB_PWR - bool "PWR" - default n - -config STM32WB_TIM2 - bool "TIM2" - default n - -config STM32WB_SPI2 - bool "SPI2" - default n - depends on STM32WB_HAVE_SPI2 - select SPI - select STM32WB_SPI - -config STM32WB_LPTIM1 - bool "LPTIM1" - default n - select STM32WB_LPTIM - -config STM32WB_LPTIM2 - bool "LPTIM2" - default n - select STM32WB_LPTIM - -config STM32WB_LPUART1 - bool "LPUART1" - default n - depends on STM32WB_HAVE_LPUART - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - select STM32WB_USART - -config STM32WB_I2C1 - bool "I2C1" - default n - select I2C - select STM32WB_I2C - -config STM32WB_I2C3 - bool "I2C3" - default n - depends on STM32WB_HAVE_I2C3 - select I2C - select STM32WB_I2C - -comment "APB2 Peripherals" - -config STM32WB_SYSCFG - bool "SYSCFG" - default y - -config STM32WB_TIM1 - bool "TIM1" - default n - -config STM32WB_SPI1 - bool "SPI1" - default n - select SPI - select STM32WB_SPI - -config STM32WB_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WB_USART - -config STM32WB_TIM16 - bool "TIM16" - default n - depends on STM32WB_HAVE_TIM16 - -config STM32WB_TIM17 - bool "TIM17" - default n - depends on STM32WB_HAVE_TIM17 - -endmenu - -config STM32WB_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32WB clock configuration. - -config STM32WB_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32WB_RTC - -config STM32WB_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32WB_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32WB_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32WB_RTC_LSECLOCK - depends on STM32WB_RTC - -config STM32WB_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32WB_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32WB_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32WB_RTC_LSECLOCK - -config STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32WB_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32WB_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32WB_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32WB_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32WB_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32WB_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32WB_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -endmenu # Timer Configuration - -config STM32WB_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WB_LPUART1 || STM32WB_USART1 - -choice - prompt "LPUART1 Driver Configuration" - default STM32WB_LPUART1_SERIALDRIVER - depends on STM32WB_LPUART1 - -config STM32WB_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32WB_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32WB_LPUART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32WB_USART1_SERIALDRIVER - depends on STM32WB_USART1 - -config STM32WB_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32WB_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32WB_USART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -if STM32WB_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32WB_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32WB_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32WB_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32WB_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32WB_USART1 - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32WB have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32WB_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32WB_USART1 - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32WB manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32WB_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32WB_USART1 && STM32WB_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32WB U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32WB_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32WB serial driver. - -config STM32WB_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32WB serial driver. - -config STM32WB_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32WB_USART1 - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32WB serial driver. - -if PM - -config STM32WB_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endif # STM32WB_SERIALDRIVER - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WB_SPI1 || STM32WB_SPI2 - -config STM32WB_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WB_SPI_DMA - bool "SPI DMA" - depends on STM32WB_DMA - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32WB_SPI_INTERRUPT. - -endmenu - -config STM32WB_MBOX - bool - default n - select STM32WB_IPCC - -menuconfig STM32WB_BLE - bool "BLE" - default n - select STM32WB_MBOX - ---help--- - Enable BLE support. - -if STM32WB_BLE - -config STM32WB_BLE_C2HOST - bool "Enable CPU2 HOST stack" - default n - ---help--- - The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and - control it using vendor ACL protocol. However, it is not expected to enable - this option in the current implementation. - -config STM32WB_BLE_MAX_CONN - int "Maximum BLE simultaneous connections" - range 1 8 - default 2 - -config STM32WB_BLE_GATT_MAX_ATTR_NUM - int "GATT attributes max count" - range 9 255 - default 64 - -config STM32WB_BLE_GATT_MAX_SVC_NUM - int "GATT services max count" - range 2 64 - default 8 - -config STM32WB_BLE_GATT_ATTR_BUF_SIZE - int "GATT attributes storage buf size" - default 1344 - ---help--- - Size of the storage area for attribute values. Hardcoded in CPU2 firmware. - -config STM32WB_BLE_DLE - bool "Support Data Length Extension (DLE)" - default y - -config STM32WB_BLE_MAX_ATT_MTU - int "Maximum supported attribute MTU" - range 23 512 - default 156 - -config STM32WB_BLE_SLAVE_SCA - int "Sleep clock accuracy in slave mode [PPM]" - default 500 - ---help--- - Sleep clock accuracy (ppm value) in slave mode. - -choice - prompt "Sleep clock accuracy in master mode" - default STM32WB_BLE_MASTER_SCA_0 - ---help--- - Sleep clock accuracy in master mode. - -config STM32WB_BLE_MASTER_SCA_0 - bool "251-500 ppm" - -config STM32WB_BLE_MASTER_SCA_1 - bool "151-250 ppm" - -config STM32WB_BLE_MASTER_SCA_2 - bool "101-150 ppm" - -config STM32WB_BLE_MASTER_SCA_3 - bool "76-100 ppm" - -config STM32WB_BLE_MASTER_SCA_4 - bool "51-75 ppm" - -config STM32WB_BLE_MASTER_SCA_5 - bool "31-50 ppm" - -config STM32WB_BLE_MASTER_SCA_6 - bool "21-30 ppm" - -config STM32WB_BLE_MASTER_SCA_7 - bool "0-20 ppm" - -endchoice # Sleep clock accuracy in master mode - -config STM32WB_BLE_MASTER_SCA - int - default 7 if STM32WB_BLE_MASTER_SCA_7 - default 6 if STM32WB_BLE_MASTER_SCA_6 - default 5 if STM32WB_BLE_MASTER_SCA_5 - default 4 if STM32WB_BLE_MASTER_SCA_4 - default 3 if STM32WB_BLE_MASTER_SCA_3 - default 2 if STM32WB_BLE_MASTER_SCA_2 - default 1 if STM32WB_BLE_MASTER_SCA_1 - default 0 - -choice - prompt "Low speed clock source" - default STM32WB_BLE_LS_CLK_SRC_LSE - ---help--- - Low speed 32 kHz clock source. - -config STM32WB_BLE_LS_CLK_SRC_LSE - bool "LSE" - -config STM32WB_BLE_LS_CLK_SRC_HSE - bool "HSE" - -endchoice # Low speed clock source - -config STM32WB_BLE_LS_CLK_SRC - int - default 1 if STM32WB_BLE_LS_CLKSRC_HSE - default 0 - -config STM32WB_BLE_MAX_CONN_EVT_LENGTH - hex "Max connection event length" - default 0xffffffff - ---help--- - Maximum duration of a slave connection event in units of 625/256us (~2.44us). - -config STM32WB_BLE_HSE_STARTUP - hex "HSE startup time" - default 0x148 - ---help--- - HSE startup time in units of 625/256us (~2.44us). - -config STM32WB_BLE_VITERBI - bool "Enable Viterbi algorithm" - default y - ---help--- - Enable Viterbi algorithm implementation - -config STM32WB_BLE_MAX_INITOR_COC_NUM - int "Max number of connection-oriented channels" - range 0 64 - default 32 - ---help--- - Maximum number of connection-oriented channels in initiator mode. - -config STM32WB_BLE_SVC_CHANGED_CHAR - bool "Enable service changed characteristic" - default n - -config STM32WB_BLE_WRITABLE_DEVICE_NAME - bool "Writable device name" - default y - -config STM32WB_BLE_CHAN_SEL_ALG2 - bool "Enable channel selection algorithm 2" - default n - -choice - prompt "Power class" - default STM32WB_BLE_POWER_CLASS_2_3 - -config STM32WB_BLE_POWER_CLASS_2_3 - bool "Power Class 2-3" - -config STM32WB_BLE_POWER_CLASS_1 - bool "Power Class 1" - -endchoice # Power class - -config STM32WB_BLE_MIN_TX_POWER - int "Minimum transmit power [dBm]" - range -127 20 - default 0 - -config STM32WB_BLE_MAX_TX_POWER - int "Maximum transmit power [dBm]" - range -127 20 - default 0 - -choice - prompt "AGC RSSI model" - default STM32WB_BLE_AGC_RSSI_LEGACY - -config STM32WB_BLE_AGC_RSSI_LEGACY - bool "AGC RSSI Legacy" - -config STM32WB_BLE_AGC_RSSI_IMPROVED - bool "AGC RSSI Improved" - -endchoice # AGC RSSI model - -config STM32WB_BLE_ADVERTISING - bool "Support advertising" - default y - -config STM32WB_BLE_SCANNING - bool "Support scanning" - default y - -config STM32WB_BLE_LE_2M_PHY - bool "Support LE 2M PHY" - default y - -config STM32WB_BLE_LE_CODED_PHY - bool "Support LE Coded PHY" - default STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - depends on STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - -config STM32WB_BLE_FICR_STATIC_ADDR - bool "Configure factory generated static random address" - default n - -config STM32WB_BLE_PUB_ADDR - hex "Configure BT public address" - default 0x0000000000 - -endif # STM32WB_BLE - -if STM32WB_MBOX - -config STM32WB_MBOX_TX_CMD_QUEUE_LEN - int "Mailbox TX command queue length" - default 2 - -config STM32WB_MBOX_RX_EVT_QUEUE_LEN - int "Mailbox RX event queue length" - default 5 - -endif # STM32WB_MBOX + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE endif # ARCH_CHIP_STM32WB diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index a8ff0d7afa91d..2bf29ecfd1414 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -50,11 +50,11 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32WB_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32WB_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32wb_freerun.c endif @@ -62,11 +62,11 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif -ifeq ($(CONFIG_STM32WB_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32wb_rcc_hsi48.c endif -ifeq ($(CONFIG_STM32WB_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32wb_dma.c endif @@ -79,11 +79,11 @@ CHIP_CSRCS += stm32wb_pminitialize.c endif endif -ifeq ($(CONFIG_STM32WB_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32wb_exti_pwr.c endif -ifeq ($(CONFIG_STM32WB_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32wb_exti_alarm.c endif @@ -95,15 +95,15 @@ CHIP_CSRCS += stm32wb_rtc.c stm32wb_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32WB_IPCC),y) +ifeq ($(CONFIG_STM32_IPCC),y) CHIP_CSRCS += stm32wb_ipcc.c endif -ifeq ($(CONFIG_STM32WB_MBOX),y) +ifeq ($(CONFIG_STM32_MBOX),y) CHIP_CSRCS += stm32wb_mbox.c endif -ifeq ($(CONFIG_STM32WB_BLE),y) +ifeq ($(CONFIG_STM32_BLE),y) CHIP_CSRCS += stm32wb_blehci.c endif diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 74ead7ff2ba1b..ee55e17fd9acd 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H /**************************************************************************** * Included Files @@ -51,37 +51,37 @@ */ #if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32_FLASH_OVERRIDE_C_256) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ !defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) && \ - !defined(CONFIG_STM32_FLASH_OVERRIDE_E_512) && \ - !defined(CONFIG_STM32_FLASH_OVERRIDE_Y_640) && \ - !defined(CONFIG_STM32_FLASH_OVERRIDE_G_1024) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_C_256) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_Y) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ !defined(CONFIG_STM32_FLASH_CONFIG_C_320) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_E_512) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_Y_640) && \ - !defined(CONFIG_STM32_FLASH_CONFIG_G_1024) + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_Y) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) # error "Flash size not defined" #endif /* Override of the Flash has been chosen */ #if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32_FLASH_CONFIG_C_256 +# undef CONFIG_STM32_FLASH_CONFIG_C # undef CONFIG_STM32_FLASH_CONFIG_C_320 -# undef CONFIG_STM32_FLASH_CONFIG_E_512 -# undef CONFIG_STM32_FLASH_CONFIG_Y_640 -# undef CONFIG_STM32_FLASH_CONFIG_G_1024 -# if defined(CONFIG_STM32_FLASH_OVERRIDE_C_256) -# define CONFIG_STM32_FLASH_CONFIG_C_256 +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_Y +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C # elif defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) # define CONFIG_STM32_FLASH_CONFIG_C_320 -# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E_512) -# define CONFIG_STM32_FLASH_CONFIG_E_512 -# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y_640) -# define CONFIG_STM32_FLASH_CONFIG_Y_640 -# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G_1024) -# define CONFIG_STM32_FLASH_CONFIG_G_1024 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y) +# define CONFIG_STM32_FLASH_CONFIG_Y +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif @@ -89,15 +89,15 @@ #define STM32_FLASH_PAGESIZE 4096 -#if defined(CONFIG_STM32_FLASH_CONFIG_C_256) /* 256 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 64 #elif defined(CONFIG_STM32_FLASH_CONFIG_C_320) /* 320 kB */ # define STM32_FLASH_NPAGES 80 -#elif defined(CONFIG_STM32_FLASH_CONFIG_E_512) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 128 -#elif defined(CONFIG_STM32_FLASH_CONFIG_Y_640) /* 640 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_Y) /* 640 kB */ # define STM32_FLASH_NPAGES 160 -#elif defined(CONFIG_STM32_FLASH_CONFIG_G_1024) /* 1 MB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ # define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" @@ -358,4 +358,4 @@ # define FLASH_SRRVR_C2OPT_SRAM (0 << 31) /* 0: SBRV offset addresses SRAM1/2, starting from 0x20000000 */ # define FLASH_SRRVR_C2OPT_FLASH (1 << 31) /* 1: SBRV offset addresses Flash, starting from 0x08000000 */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index f105f98b5aaab..ccecaaa1003e6 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H /**************************************************************************** * Pre-processor Definitions @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) -#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) -#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) -#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) -#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) -#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) -#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) -#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) -#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) -#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) - -#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) -#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) -#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) -#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) -#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) -#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) -#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) -#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) -#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) -#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) - -#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) -#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) -#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) -#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) -#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) -#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) -#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) -#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) -#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) -#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) +#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) +#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) +#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) +#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) +#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) +#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) +#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) +#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) +#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) +#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) +#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) + +#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) +#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) +#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) +#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) +#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) +#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) +#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) +#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) +#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) +#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) +#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) + +#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) +#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) +#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) +#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) +#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) +#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) +#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) +#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) +#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) +#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) +#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) #if defined(CONFIG_STM32_GPIO_HAVE_PORTD) -# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) -# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) +# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) +# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) +# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) +# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) +# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) +# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) +# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) +# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) +# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) +# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) #endif #if defined(CONFIG_STM32_GPIO_HAVE_PORTE) -# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) -# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) -# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) -# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) -# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) -# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) -# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) -# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) -# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) -# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) +# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) +# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) +# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) +# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) +# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) +# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) +# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) +# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) +# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) #endif -#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) -#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) -#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) -#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) -#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) -#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) -#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) -#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) -#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) -#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) +#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) +#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) +#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) +#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) +#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) +#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) +#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) +#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) +#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) +#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -318,4 +318,4 @@ #define GPIO_BRR_RESET(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index f5ee36a162cb5..bbf14328e84a1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H /**************************************************************************** * Pre-processor Definitions @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) -#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) -#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) -#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) -#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) -#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) -#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) -#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) -#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) -#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) -#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) +#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) +#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) +#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) +#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) +#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) +#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) +#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) +#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) +#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) +#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) +#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) #ifdef CONFIG_STM32_HAVE_I2C3 -# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) -# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) -# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) -# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) -# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) -# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) -# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) -# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) -# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) +# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) +# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) +# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) +# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) +# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) +# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) +# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) +# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) +# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) +# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) +# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -219,4 +219,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_I2C_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index f1d417c62db02..43b8dd5758df1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H +#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H /**************************************************************************** * Included Files @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32_SPI_CLK_MAX 32000000ul +#define STM32WB_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) -#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) -#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) -#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) -#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) -#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) -#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) +#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) +#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) +#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) +#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) +#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) +#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) +#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) #if CONFIG_STM32_HAVE_SPI2 -# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) -# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) -# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) -# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) -# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) -# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) -# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) +# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) +# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) +# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) +# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) +# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) +# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) +# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -150,4 +150,4 @@ # define SPI_SR_FTLVL_HALF (0x2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ # define SPI_SR_FTLVL_FULL (0x3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h index d511cb6d39eea..7c9a15dd0451f 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h @@ -62,7 +62,7 @@ # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN4_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) -#elif defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#elif defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_ADC1_IN1_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) @@ -84,7 +84,7 @@ # define GPIO_ADC1_IN16_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_ADC1_IN13_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) # define GPIO_ADC1_IN14_0 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) #endif @@ -106,7 +106,7 @@ #define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN0) #define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN0) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_COMP1_INP_3 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) # define GPIO_COMP1_INM_5 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) # define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN10) @@ -124,7 +124,7 @@ #define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN7) #define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN5) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) #endif @@ -141,7 +141,7 @@ #define GPIO_I2C1_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN14) #define GPIO_I2C1_SMBA_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN5) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9) #endif @@ -151,7 +151,7 @@ #define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7) #define GPIO_I2C3_SMBA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN2) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_I2C3_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12) # define GPIO_I2C3_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11) # define GPIO_I2C3_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN14) @@ -169,7 +169,7 @@ #define GPIO_JTCK_SWCLK_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14) #define GPIO_NJTRST_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_JTDO_SWO_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3) # define GPIO_JTDI_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15) #endif @@ -185,12 +185,12 @@ #define GPIO_QSPI_BK1_IO2_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN7) #define GPIO_QSPI_BK1_IO3_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_QSPI_NCS_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN11) # define GPIO_QSPI_CLK_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN10) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_QSPI_NCS_3 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN3) # define GPIO_QSPI_BK1_IO0_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN4) # define GPIO_QSPI_BK1_IO1_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN5) @@ -205,7 +205,7 @@ #define GPIO_RTC_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN2) #define GPIO_RTC_TAMP2_0 (GPIO_PORTA | GPIO_PIN0) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_RTC_OUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13) # define GPIO_RTC_REFIN_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15) # define GPIO_RTC_TS_0 (GPIO_PORTC | GPIO_PIN13) @@ -239,7 +239,7 @@ #define GPIO_SAI1_PDMDI2_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN9) #define GPIO_SAI1_PDMDI2_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_SAI1_FS_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN12) # define GPIO_SAI1_SCK_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN10) # define GPIO_SAI1_SCK_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN13) @@ -249,7 +249,7 @@ # define GPIO_SAI1_PDMDI1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTC | GPIO_PIN3) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_SAI1_SD_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTD | GPIO_PIN6) # define GPIO_SAI1_MCLK_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTE | GPIO_PIN2) # define GPIO_SAI1_SCK_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTC | GPIO_PIN9) @@ -272,7 +272,7 @@ #define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11) #define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN15) # define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) #endif @@ -299,7 +299,7 @@ #define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14) #define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN2) -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_SPI2_SCK_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN3) # define GPIO_SPI2_MOSI_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN4) # define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) @@ -326,11 +326,11 @@ #define GPIO_TIM1_CH4IN_0 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11) #define GPIO_TIM1_CH4OUT_0 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TIM1_BKIN1_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TIM1_BKIN1_5 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) @@ -338,7 +338,7 @@ # define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN0) # define GPIO_TIM1_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN14) # define GPIO_TIM1_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN14) @@ -351,7 +351,7 @@ # define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) #endif -#if defined(CONFIG_STM32_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) # define GPIO_TIM1_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN14) # define GPIO_TIM1_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN14) #endif @@ -369,7 +369,7 @@ #define GPIO_TIM2_CH4IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN3) #define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_TIM2_ETR_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN15) # define GPIO_TIM2_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15) # define GPIO_TIM2_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15) @@ -377,14 +377,14 @@ # define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10) # define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10) # define GPIO_TIM2_CH4IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN11) # define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11) #endif -#if defined(CONFIG_STM32_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) # define GPIO_TIM2_CH1IN_4 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN15) # define GPIO_TIM2_CH1OUT_4 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15) # define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN12) @@ -403,7 +403,7 @@ #define GPIO_TIM16_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN6) #define GPIO_TIM16_CH1N_0 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6) -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TIM16_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN0) # define GPIO_TIM16_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN0) #endif @@ -415,7 +415,7 @@ #define GPIO_TIM17_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7) #define GPIO_TIM17_CH1N_0 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TIM17_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN1) # define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1) #endif @@ -428,7 +428,7 @@ #define GPIO_LPTIM1_IN1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5) #define GPIO_LPTIM1_IN2_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_LPTIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3) # define GPIO_LPTIM1_IN1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0) # define GPIO_LPTIM1_OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1) @@ -440,12 +440,12 @@ #define GPIO_LPTIM2_OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8) #define GPIO_LPTIM2_IN1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN1) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_LPTIM2_ETR_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN3) # define GPIO_LPTIM2_IN1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN0) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_LPTIM2_ETR_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN11) # define GPIO_LPTIM2_OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN13) # define GPIO_LPTIM2_IN1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN12) @@ -455,20 +455,20 @@ #if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_SYNC_2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN2) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) || defined(CONFIG_STM32_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) || defined(CONFIG_STM32WB_IO_CONFIG_C_48E) # define GPIO_TSC_G1_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN12) # define GPIO_TSC_G1_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G1_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN14) # define GPIO_TSC_G1_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN15) #endif @@ -478,46 +478,46 @@ #define GPIO_TSC_G2_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN6) #define GPIO_TSC_G2_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN7) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_TSC_G3_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN15) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G3_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN10) # define GPIO_TSC_G3_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN11) # define GPIO_TSC_G3_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN12) #endif -#if defined(CONFIG_STM32_IO_CONFIG_C_48E) +#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E) # define GPIO_TSC_G3_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) # define GPIO_TSC_G3_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN1) #endif -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G4_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN6) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G4_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN7) # define GPIO_TSC_G4_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN8) # define GPIO_TSC_G4_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN9) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G5_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN4) # define GPIO_TSC_G5_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN5) # define GPIO_TSC_G5_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN6) # define GPIO_TSC_G5_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN7) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G6_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN10) # define GPIO_TSC_G6_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN11) # define GPIO_TSC_G6_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN12) # define GPIO_TSC_G6_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN13) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN0) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN1) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2) @@ -543,12 +543,12 @@ /* Trace port */ -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TRACED1_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) # define GPIO_TRACED3_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12) #endif -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TRACECK_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2) # define GPIO_TRACED0_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN9) # define GPIO_TRACED2_0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2) @@ -566,7 +566,7 @@ #define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN4) #define GPIO_USART1_RTS_DE_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12) -#if !defined(CONFIG_STM32_IO_CONFIG_C_49) +#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49) # define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif @@ -579,7 +579,7 @@ #define GPIO_LPUART1_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6) #define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN1) -#if defined(CONFIG_STM32_IO_CONFIG_R) || defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_LPUART1_TX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN11) # define GPIO_LPUART1_TX_4 (GPIO_ALT | GPIO_AF8 | GPIO_PORTC | GPIO_PIN1) # define GPIO_LPUART1_RX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN10) @@ -599,7 +599,7 @@ #define GPIO_USB_DP_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12) #define GPIO_USB_NOE_1 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN13) -#if defined(CONFIG_STM32_IO_CONFIG_V) +#if defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9) #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 3df0927bd0e03..ca6d39fa974bc 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,61 +45,61 @@ /* HCI event header fields helpers */ -#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32_BLE_PREP_WRITE_NUM \ - STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) +#define STM32WB_BLE_PREP_WRITE_NUM \ + STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) -#define STM32_C2_MEM_BLOCK_NUM \ - STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ +#define STM32WB_C2_MEM_BLOCK_NUM \ + STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ CONFIG_STM32_BLE_MAX_CONN, \ - STM32_BLE_PREP_WRITE_NUM) + STM32WB_BLE_PREP_WRITE_NUM) #ifdef CONFIG_STM32_BLE_C2HOST -# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST +# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL #endif #ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR -# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif #ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME -# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif #ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 -# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif #ifdef CONFIG_STM32_BLE_POWER_CLASS_1 -# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32_BLE_INIT_OPTIONS \ - (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ - STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ - STM32_BLE_POWER_CLASS) +#define STM32WB_BLE_INIT_OPTIONS \ + (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ + STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ + STM32WB_BLE_POWER_CLASS) #ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED -# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** @@ -200,21 +200,21 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) switch (evt->type) { - case STM32_MBOX_HCIEVT: + case STM32WB_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,29 +247,29 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32_MBOX_HCIACL: + case STM32WB_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32_MBOX_SYSEVT: + case STM32WB_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) { stm32_blehci_bleinit(); } break; - case STM32_MBOX_SYSACK: + case STM32WB_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); @@ -304,8 +304,8 @@ static void stm32_blehci_bleinit(void) .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, .max_conn = CONFIG_STM32_BLE_MAX_CONN, .dle_enable = CONFIG_STM32_BLE_DLE, - .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32_C2_MEM_BLOCK_NUM, + .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, @@ -313,12 +313,12 @@ static void stm32_blehci_bleinit(void) .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, .viterbi_enable = CONFIG_STM32_BLE_VITERBI, - .options = STM32_BLE_INIT_OPTIONS, + .options = STM32WB_BLE_INIT_OPTIONS, .hw_version = 0, .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, - .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI + .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index 82bb66d54d3d3..ae4dd49ba9c3a 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H +#define __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H /**************************************************************************** * Included Files @@ -159,4 +159,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #endif #endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_FREERUN_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 21343fad3b4f7..9b02e37ca1cd4 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H +#define __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H /**************************************************************************** * Included Files @@ -195,4 +195,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, #endif #endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_ONESHOT_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index 75d766426b163..7fbbbd8ab19e4 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -29,6 +29,7 @@ #include +#include "arm_internal.h" #include "chip.h" #include "hardware/stm32wb_rcc.h" diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index a59d829100e83..23d8cbfb8aec1 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -24,8 +24,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32WB_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H +#define __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H #include #include @@ -38,9 +38,9 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ #if !defined(CONFIG_STM32_RTC_MAGIC) @@ -57,7 +57,7 @@ #define RTC_MAGIC CONFIG_STM32_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -314,4 +314,4 @@ struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_RTC_H */ +#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_RTC_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index ea28a500667ed..a56b2f75f8fa4 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -59,9 +59,9 @@ #undef CONFIG_STM32_SYSTICK_HCLKd8 #ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value diff --git a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig index c127e72875f9b..d1a1619b32a13 100644 --- a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig +++ b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="flipperzero" CONFIG_ARCH_BOARD_FLIPPERZERO=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_ST7565_MIRROR_Y=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_SPI2=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig index ff3325b96d84c..cb0bc5bb9134e 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -41,11 +42,11 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig index 7e9dcb33872da..73b3510b415fa 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig index 0738f6cea5820..cdd024ed73b32 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -30,10 +31,10 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y From 7b3435c8d0abf5c0b107a637727a425bf89589a0 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:43 +0200 Subject: [PATCH 19/52] !arm/stm32wl5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32WL5 Kconfig symbols were renamed from CONFIG_STM32WL5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. Signed-off-by: raiden00pl --- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 44 +- arch/arm/src/stm32u5/stm32_tim.c | 332 +++++++-------- arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 154 +++---- arch/arm/src/stm32wb/hardware/stm32wb_i2c.h | 66 +-- arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 44 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 92 ++-- arch/arm/src/stm32wb/stm32wb_rtc.h | 6 +- arch/arm/src/stm32wb/stm32wb_timerisr.c | 4 +- arch/arm/src/stm32wl5/CMakeLists.txt | 2 +- arch/arm/src/stm32wl5/Kconfig | 393 +----------------- arch/arm/src/stm32wl5/Make.defs | 2 +- .../src/stm32wl5/hardware/stm32wl5_flash.h | 6 +- arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h | 6 +- boards/arm/stm32wl5/nucleo-wl55jc/Kconfig | 12 +- .../nucleo-wl55jc/configs/demo/defconfig | 3 +- .../nucleo-wl55jc/configs/fb/defconfig | 9 +- .../nucleo-wl55jc/configs/nsh/defconfig | 3 +- 17 files changed, 412 insertions(+), 766 deletions(-) diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 45fb42dedce68..3cb7aec33dcc3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 090ed0cb4d573..66879e72e8a2a 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -305,16 +305,16 @@ static const struct stm32_tim_ops_s stm32_tim_ops = struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32_tim_priv_s stm32_tim8_priv = struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32_tim_priv_s stm32_tim15_priv = struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32_tim_priv_s stm32_tim16_priv = struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) #ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index ccecaaa1003e6..180972f07a7bb 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) - -#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) + +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) #if defined(CONFIG_STM32_GPIO_HAVE_PORTD) -# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) -# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif #if defined(CONFIG_STM32_GPIO_HAVE_PORTE) -# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) #endif -#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index bbf14328e84a1..a16c5a97dffe8 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) -#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) -#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) -#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) -#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) -#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) -#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) -#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) -#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) -#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) +#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) #ifdef CONFIG_STM32_HAVE_I2C3 -# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) -# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) -# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) -# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) -# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) -# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) -# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) -# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) -# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) -# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) +# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index 43b8dd5758df1..fd433817a3d02 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32WB_SPI_CLK_MAX 32000000ul +#define STM32_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) -#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) -#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) -#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) -#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) -#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) -#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) +#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #if CONFIG_STM32_HAVE_SPI2 -# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) -# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) -# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) -# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) -# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) -# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) -# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index ca6d39fa974bc..3df0927bd0e03 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,61 +45,61 @@ /* HCI event header fields helpers */ -#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32WB_BLE_PREP_WRITE_NUM \ - STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) +#define STM32_BLE_PREP_WRITE_NUM \ + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) -#define STM32WB_C2_MEM_BLOCK_NUM \ - STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ +#define STM32_C2_MEM_BLOCK_NUM \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ CONFIG_STM32_BLE_MAX_CONN, \ - STM32WB_BLE_PREP_WRITE_NUM) + STM32_BLE_PREP_WRITE_NUM) #ifdef CONFIG_STM32_BLE_C2HOST -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif #ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif #ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif #ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif #ifdef CONFIG_STM32_BLE_POWER_CLASS_1 -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32WB_BLE_INIT_OPTIONS \ - (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ - STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ - STM32WB_BLE_POWER_CLASS) +#define STM32_BLE_INIT_OPTIONS \ + (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ + STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ + STM32_BLE_POWER_CLASS) #ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** @@ -200,21 +200,21 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) switch (evt->type) { - case STM32WB_MBOX_HCIEVT: + case STM32_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,29 +247,29 @@ static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32WB_MBOX_HCIACL: + case STM32_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32WB_MBOX_SYSEVT: + case STM32_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { stm32_blehci_bleinit(); } break; - case STM32WB_MBOX_SYSACK: + case STM32_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); @@ -304,8 +304,8 @@ static void stm32_blehci_bleinit(void) .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, .max_conn = CONFIG_STM32_BLE_MAX_CONN, .dle_enable = CONFIG_STM32_BLE_DLE, - .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, + .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32_C2_MEM_BLOCK_NUM, .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, @@ -313,12 +313,12 @@ static void stm32_blehci_bleinit(void) .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, .viterbi_enable = CONFIG_STM32_BLE_VITERBI, - .options = STM32WB_BLE_INIT_OPTIONS, + .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, - .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI + .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 23d8cbfb8aec1..500d5dfcd4d41 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -38,9 +38,9 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ #if !defined(CONFIG_STM32_RTC_MAGIC) @@ -57,7 +57,7 @@ #define RTC_MAGIC CONFIG_STM32_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index a56b2f75f8fa4..ea28a500667ed 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -59,9 +59,9 @@ #undef CONFIG_STM32_SYSTICK_HCLKd8 #ifdef CONFIG_STM32_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index 86a13b68e1ef9..cfee3e8c42e38 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -42,7 +42,7 @@ set(SRCS stm32wl5_timerisr.c stm32wl5_spi.c) -if(CONFIG_STM32WL5_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wl5_ipcc.c) endif() diff --git a/arch/arm/src/stm32wl5/Kconfig b/arch/arm/src/stm32wl5/Kconfig index 99e5a6cd68b26..eee194b3ad43b 100644 --- a/arch/arm/src/stm32wl5/Kconfig +++ b/arch/arm/src/stm32wl5/Kconfig @@ -7,6 +7,11 @@ if ARCH_CHIP_STM32WL5 comment "STM32WL5 Configuration Options" +config STM32_WL5_PERIPHERALS + bool + default ARCH_CHIP_STM32WL5 + select STM32_HAVE_SYSCFG + choice prompt "STM32 WL5 Chip Selection" default ARCH_CHIP_STM32WL55JC_CPU1 @@ -14,396 +19,34 @@ choice config ARCH_CHIP_STM32WL55JC_CPU1 bool "STM32WL55JC (cpu1)" - select STM32WL5_STM32WL5XXX_CPU1 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU1 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M4 (cpu1), 256kiB FLASH, 64kiB SRAM config ARCH_CHIP_STM32WL55JC_CPU2 bool "STM32WL55JC (cpu2)" - select STM32WL5_STM32WL5XXX_CPU2 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU2 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M0 (cpu2), 256kiB FLASH, 64kiB SRAM - endchoice # STM32 WL5 Chip Selection # Chip product lines -config STM32WL5_STM32WL5XXX +config STM32_STM32WL5XXX bool -config STM32WL5_STM32WL5XXX_CPU1 +config STM32_STM32WL5XXX_CPU1 bool default y - select STM32WL5_HAVE_USART1 - select STM32WL5_HAVE_USART2 - select STM32WL5_HAVE_LPUART1 - select STM32WL5_HAVE_SPI1 - select STM32WL5_HAVE_SPI2S2 - - -comment "STM32WL5 Peripherals" - -menu "STM32WL5 Peripheral Support" - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WL5 - default STM32WL5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WL5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32WL55JC is chosen, the Flash configuration would be 'C', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32WL5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WL5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WL5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32WL5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32WL5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32WL5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32WL5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WL5_FLASH_CONFIG_8 - bool - default n - -config STM32WL5_FLASH_CONFIG_B - bool - default n - -config STM32WL5_FLASH_CONFIG_C - bool - default n - -config STM32WL5_FLASH_CONFIG_E - bool - default n - -config STM32WL5_FLASH_CONFIG_G - bool - default n - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WL5_HAVE_USART1 - bool - default n - -config STM32WL5_HAVE_USART2 - bool - default n - -config STM32WL5_HAVE_LPUART1 - bool - default n - -config STM32WL5_HAVE_SPI1 - bool - default n - -config STM32WL5_HAVE_SPI2S2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WL5_USART - bool - default n - -config STM32WL5_SPI - bool - default n - -config STM32WL5_SPI_DMA - bool - default n - -# These are the peripheral selections proper - -comment "APB1 Peripherals" - -config STM32WL5_USART2 - bool "USART2" - default n - depends on STM32WL5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_LPUART1 - bool "LPUART1" - default n - depends on STM32WL5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI2S2 - bool "SPI2S2" - default n - depends on STM32WL5_HAVE_SPI2S2 - select STM32WL5_SPI - -comment "APB2 Peripherals" - -config STM32WL5_SYSCFG - bool "SYSCFG" - default y - -config STM32WL5_USART1 - bool "USART1" - default n - depends on STM32WL5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI1 - bool "SPI1" - default n - depends on STM32WL5_HAVE_SPI1 - select STM32WL5_SPI - -comment "AHB3 Peripherals" - -config STM32WL5_IPCC - bool "IPCC" - select IPCC - default n - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -endmenu # STM32WL5 Peripheral Support - - -config STM32WL5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WL5_USART - -choice - prompt "USART1 Driver Configuration" - default STM32WL5_USART1_SERIALDRIVER - depends on STM32WL5_USART1 - -config STM32WL5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -choice - prompt "USART2 Driver Configuration" - default STM32WL5_USART2_SERIALDRIVER - depends on STM32WL5_USART2 - -config STM32WL5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -choice - prompt "LPUART1 Driver Configuration" - default STM32WL5_LPUART1_SERIALDRIVER - depends on STM32WL5_LPUART1 - -config STM32WL5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WL5_SPI - -config STM32WL5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WL5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32WL5_SPI1 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32WL5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32WL5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32WL5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32WL5_SPI2S2_DMA - bool "SPI2S2 DMA" - default n - depends on STM32WL5_SPI2 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32WL5_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -endmenu # SPI Configuration - -menu "IPCC Configuration" - depends on STM32WL5_IPCC - -config STM32WL5_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - ---help--- - Size of the receive buffer. Another CPU will write to this - buffer and currently running CPU will read from it. - -config STM32WL5_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - ---help--- - Size of the send buffer. Another CPU will read from this - buffer and currently running CPU will write to it. - -config STM32WL5_IPCC_CHAN2 - bool "Enable channel 2" - default n - -if STM32WL5_IPCC_CHAN2 - -config STM32WL5_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32WL5_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32WL5_IPCC_CHAN3 - bool "Enable channel 3" - default n - -if STM32WL5_IPCC_CHAN3 - -config STM32WL5_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32WL5_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32WL5_IPCC_CHAN4 - bool "Enable channel 4" - default n - -if STM32WL5_IPCC_CHAN4 - -config STM32WL5_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32WL5_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32WL5_IPCC_CHAN5 - bool "Enable channel 5" - default n - -if STM32WL5_IPCC_CHAN5 - -config STM32WL5_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32WL5_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32WL5_IPCC_CHAN6 - bool "Enable channel 6" - default n - -if STM32WL5_IPCC_CHAN6 - -config STM32WL5_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32WL5_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32WL5_IPCC_CHAN2 -endif # STM32WL5_IPCC_CHAN3 -endif # STM32WL5_IPCC_CHAN4 -endif # STM32WL5_IPCC_CHAN5 -endif # STM32WL5_IPCC_CHAN6 - -endmenu # IPCC Configuration + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_LPUART1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2S2 endif # ARCH_CHIP_STM32WL5 diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index fc265b697ae57..e0df51091d07c 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -36,6 +36,6 @@ CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c -CSRCS-$(CONFIG_STM32WL5_IPCC) = stm32wl5_ipcc.c +CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c CHIP_CSRCS += $(CSRCS-y) diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index c47fa47585ced..808f6fb5a3cb6 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H /**************************************************************************** * Included Files @@ -301,4 +301,4 @@ #define FLASH_C2CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */ #define FLASH_C2CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */ -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index 79da83f3530ba..9e3afea3506bc 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H +#define __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H /**************************************************************************** * Included Files @@ -276,4 +276,4 @@ # define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_SPI_H */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig index 411801e17de7f..f66ff2ef2e61f 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig @@ -24,7 +24,7 @@ config ARCH_BOARD_ENABLE_CPU2 menuconfig ARCH_BOARD_IPCC bool "Enabled IPCC" select IPCC - select STM32WL5_IPCC + select STM32_IPCC default n ---help--- Enables IPCC (inter processor communication controller) @@ -52,7 +52,7 @@ config ARCH_BOARD_IPCC_CHAN1_TXBUF config ARCH_BOARD_IPCC_CHAN2 bool "Enable channel 2" default n - select STM32WL5_IPCC_CHAN2 + select STM32_IPCC_CHAN2 if ARCH_BOARD_IPCC_CHAN2 @@ -69,7 +69,7 @@ config ARCH_BOARD_IPCC_CHAN2_TXBUF config ARCH_BOARD_IPCC_CHAN3 bool "Enable channel 3" default n - select STM32WL5_IPCC_CHAN3 + select STM32_IPCC_CHAN3 if ARCH_BOARD_IPCC_CHAN3 @@ -86,7 +86,7 @@ config ARCH_BOARD_IPCC_CHAN3_TXBUF config ARCH_BOARD_IPCC_CHAN4 bool "Enable channel 4" default n - select STM32WL5_IPCC_CHAN4 + select STM32_IPCC_CHAN4 if ARCH_BOARD_IPCC_CHAN4 @@ -103,7 +103,7 @@ config ARCH_BOARD_IPCC_CHAN4_TXBUF config ARCH_BOARD_IPCC_CHAN5 bool "Enable channel 5" default n - select STM32WL5_IPCC_CHAN5 + select STM32_IPCC_CHAN5 if ARCH_BOARD_IPCC_CHAN5 @@ -120,7 +120,7 @@ config ARCH_BOARD_IPCC_CHAN5_TXBUF config ARCH_BOARD_IPCC_CHAN6 bool "Enable channel 6" default n - select STM32WL5_IPCC_CHAN6 + select STM32_IPCC_CHAN6 if ARCH_BOARD_IPCC_CHAN6 diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig index 1074e1f8d0ba1..7a097b223f4bc 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_ARCH_IRQBUTTONS=y @@ -48,7 +49,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_CFGDATA=y CONFIG_SYSTEM_NSH=y CONFIG_USERLED=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig index 3c5150dc6a9f5..ebc8bd12c3a94 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -33,9 +34,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_SPI=y CONFIG_SPI_DRIVER=y -CONFIG_STM32WL5_LPUART1=y -CONFIG_STM32WL5_SPI1=y -CONFIG_STM32WL5_SPI2S2=y -CONFIG_STM32WL5_USART1=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2S2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig index 9318532b4a1d9..7a7e9b2a68bc1 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-wl55jc" CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -20,5 +21,5 @@ CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_NSH=y From a2c74a207888ad638e94bc06fb25f4da6fae97f7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 20 May 2026 11:41:02 +0200 Subject: [PATCH 20/52] !arm/stm32n6: use common STM32 Kconfig symbols BREAKING CHANGE: STM32N6 Kconfig symbols were renamed from CONFIG_STM32N6_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 1 + arch/arm/src/stm32n6/CMakeLists.txt | 4 +- arch/arm/src/stm32n6/Kconfig | 81 +++---------------- arch/arm/src/stm32n6/Make.defs | 2 +- arch/arm/src/stm32n6/stm32_serial.c | 30 +++---- arch/arm/src/stm32n6/stm32_start.c | 4 +- arch/arm/src/stm32n6/stm32_uart.h | 10 +-- arch/arm/src/stm32n6/stm32n6xx_rcc.c | 2 +- .../nucleo-n657x0-q/configs/leds/defconfig | 1 + .../nucleo-n657x0-q/configs/nsh/defconfig | 3 +- .../nucleo-n657x0-q/configs/ostest/defconfig | 3 +- 11 files changed, 41 insertions(+), 100 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36c1510839b6f..603dab1a96506 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -687,6 +687,7 @@ config ARCH_CHIP_STM32H5 config ARCH_CHIP_STM32N6 bool "STMicro STM32 N6" + select ARCH_CHIP_STM32 select ARCH_CORTEXM55 select ARCH_HAVE_FPU select ARCH_HAVE_MPU diff --git a/arch/arm/src/stm32n6/CMakeLists.txt b/arch/arm/src/stm32n6/CMakeLists.txt index afb34a68903ba..cd2b788424dfa 100644 --- a/arch/arm/src/stm32n6/CMakeLists.txt +++ b/arch/arm/src/stm32n6/CMakeLists.txt @@ -39,13 +39,13 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_STM32N6_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() # Chip-specific RCC -if(CONFIG_STM32N6_STM32N6XXXX) +if(CONFIG_STM32_STM32N6XXXX) list(APPEND SRCS stm32n6xx_rcc.c) endif() diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 2e362795f5c79..4cbd4470f7745 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -1,27 +1,18 @@ -# arch/arm/src/stm32n6/Kconfig # -# SPDX-License-Identifier: Apache-2.0 +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. # -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. if ARCH_CHIP_STM32N6 comment "STM32N6 Configuration Options" -config STM32N6_STM32N6XXXX +config STM32_N6_PERIPHERALS + bool + default y + select STM32_HAVE_USART1 + +config STM32_STM32N6XXXX bool default y @@ -32,66 +23,12 @@ choice config ARCH_CHIP_STM32N657X0 bool "STM32N657X0" - select STM32N6_STM32N6XXXX + select STM32_STM32N6XXXX endchoice menu "STM32N6 Peripheral Selection" -config STM32N6_USART1 - bool "USART1" - default n - select STM32N6_USART - select USART1_SERIALDRIVER - select STM32N6_USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config STM32N6_USART1_SERIALDRIVER - bool - default n - -config STM32N6_USART - bool - -if STM32N6_USART - -config STM32N6_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32N6_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to - another UART. This option disables that reordering so port names - stay stable when the console is moved. - -config STM32N6_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable this option to use software RTS flow control rather than - the hardware RTS line. Useful in cases where the silicon RTS - behaviour does not match the application's needs. - -config STM32N6_SERIALBRK_BSDCOMPAT - bool "Use GPIO to send Break" - default n - ---help--- - Enable this option to send break by reconfiguring TX as a GPIO - held low for the requested duration, matching BSD-compatible - semantics. - -config STM32N6_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # STM32N6_USART - if USART1_SERIALDRIVER config USART1_UNCONFIG_RX_ON_CLOSE diff --git a/arch/arm/src/stm32n6/Make.defs b/arch/arm/src/stm32n6/Make.defs index cecd24bbf69b7..7be078fc1ef00 100644 --- a/arch/arm/src/stm32n6/Make.defs +++ b/arch/arm/src/stm32n6/Make.defs @@ -38,7 +38,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32N6_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 75dc8c8c857bd..7b053b9820f03 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -62,8 +62,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32N6_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32N6_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -82,7 +82,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -210,14 +210,14 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif /* This describes the state of the STM32N6 USART1 port. */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -276,7 +276,7 @@ static struct stm32_serial_s g_usart1priv = static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [0] = &g_usart1priv, #endif }; @@ -542,7 +542,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -679,7 +679,7 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr_set = STM32_RCC_APB2ENSR; @@ -752,7 +752,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32N6_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -967,8 +967,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32N6_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32N6_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1321,7 +1321,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1434,7 +1434,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS uint16_t ie = priv->ie | USART_CR1_TXEIE; -# ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -1679,7 +1679,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1703,7 +1703,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index 3c7664921bb21..c0f29e74371d7 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -205,7 +205,7 @@ void __start_c(void) STM32_RCC_BUSLPENSR); putreg32(RCC_MEMLPENR_ALLAXISRAM | RCC_MEMLPENR_CACHEAXIRAMLPEN, STM32_RCC_MEMLPENSR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 putreg32(RCC_APB2LPENR_USART1LPEN, STM32_RCC_APB2LPENSR); #endif @@ -233,7 +233,7 @@ void __start_c(void) (void)getreg32(STM32_SYSCFG_VDDCCCR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 /* Route USART1's kernel clock to HSI so the BRR computation is * independent of any later SYSCLK changes. */ diff --git a/arch/arm/src/stm32n6/stm32_uart.h b/arch/arm/src/stm32n6/stm32_uart.h index 2726f7fffaf25..248e3f7d0af3e 100644 --- a/arch/arm/src/stm32n6/stm32_uart.h +++ b/arch/arm/src/stm32n6/stm32_uart.h @@ -40,20 +40,20 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32N6_USART1) -# undef CONFIG_STM32N6_USART1_SERIALDRIVER -# undef CONFIG_STM32N6_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32N6_USART1) +#if defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32N6_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 #else diff --git a/arch/arm/src/stm32n6/stm32n6xx_rcc.c b/arch/arm/src/stm32n6/stm32n6xx_rcc.c index e1615178a7652..e6ec3cad06790 100644 --- a/arch/arm/src/stm32n6/stm32n6xx_rcc.c +++ b/arch/arm/src/stm32n6/stm32n6xx_rcc.c @@ -93,7 +93,7 @@ static inline void rcc_enableapb2(void) { uint32_t regval = 0; -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig index c5fb9d9dcbd32..ce019ad2d4ff5 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig index f18c05e1d6240..0f35eb8c02444 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -27,6 +28,6 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig index 9e14513b6c7a4..772fa00937f52 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -30,7 +31,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TESTING_OSTEST=y CONFIG_USART1_SERIAL_CONSOLE=y From f8d09c935a534d29395a3b2fb4b897954a9f3616 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 21/52] docs/stm32: update common Kconfig references Update shared STM32 documentation references after moving common options to the shared STM32 Kconfig namespace. Signed-off-by: raiden00pl --- Documentation/components/drivers/character/timers/capture.rst | 2 +- Documentation/guides/renode.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/components/drivers/character/timers/capture.rst b/Documentation/components/drivers/character/timers/capture.rst index 026174e83a1f5..50208b54f37da 100644 --- a/Documentation/components/drivers/character/timers/capture.rst +++ b/Documentation/components/drivers/character/timers/capture.rst @@ -109,7 +109,7 @@ To enable the capture driver, enable the following configuration options: * ``CONFIG_CAPTURE`` - Enable the capture driver framework * ``CONFIG_CAPTURE_NOTIFY`` - Enable signal notification support for edge events * ``CONFIG_FAKE_CAPTURE`` - Enable fake capture driver for testing (generates 10Hz signal with 50% duty cycle) -* ``CONFIG_STM32H7_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) +* ``CONFIG_STM32_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) The ``CONFIG_CAPTURE`` option enables the lower-half driver and registers the ``/dev/capture`` device. diff --git a/Documentation/guides/renode.rst b/Documentation/guides/renode.rst index b3918d2e8ca8b..ccafddf944fb7 100644 --- a/Documentation/guides/renode.rst +++ b/Documentation/guides/renode.rst @@ -119,7 +119,7 @@ nucleo-h743zi ============= Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable -it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``. +it with ``CONFIG_STM32_PWR_IGNORE_ACTVOSRDY=y``. Renode script:: From a2cfc0865906530d8738298bdf4ba0888a5fb569 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 19:12:20 +0200 Subject: [PATCH 22/52] !arm/stm32: move duplicate Kconfig definitions to common BREAKING CHANGE: Duplicate STM32 Kconfig option definitions moved into arch/arm/src/common/stm32. Move duplicated non-ARCH STM32 Kconfig definitions out of the family Kconfig files and into common/stm32. Keep one definition per moved symbol in common/stm32. Use hidden family and symbol availability guards so the user-visible definitions keep the type/prompt line first without repeating config names. Leave driver-owned serial DMA prompts to the generic serial Kconfig to avoid duplicate menu entries. Out-of-tree Kconfig files that source family-local duplicate definitions must source the common STM32 Kconfig definitions instead. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig | 7644 ++++++++++++++++++++- arch/arm/src/stm32/Kconfig | 10221 +++++----------------------- arch/arm/src/stm32f0l0g0/Kconfig | 2308 +------ 3 files changed, 9342 insertions(+), 10831 deletions(-) diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 9d915d742888b..432dd225eb399 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -14,7 +14,67 @@ config STM32_1WIREDRIVER config STM32_HCIUART bool -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. +config STM32_COMMON_LEGACY + bool + default y if ARCH_CHIP_STM32F1 + default y if ARCH_CHIP_STM32F2 + default y if ARCH_CHIP_STM32F3 + default y if ARCH_CHIP_STM32F4 + default y if ARCH_CHIP_STM32G4 + default y if ARCH_CHIP_STM32L1 + +config STM32_COMMON_F0_L0_G0_C0 + bool + default y if ARCH_CHIP_STM32F0 + default y if ARCH_CHIP_STM32L0 + default y if ARCH_CHIP_STM32G0 + default y if ARCH_CHIP_STM32C0 + +config STM32_COMMON_F7_H7 + bool + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_COMMON_H7_H5 + bool + default y if ARCH_CHIP_STM32H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_F7_H7_H5 + bool + default y if STM32_COMMON_F7_H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_L4_L5_U5 + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L5_U5 + bool + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L4_H5_L5_U5 + bool + default y if STM32_COMMON_L4_L5_U5 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_FULL_FEATURED + bool + default y if STM32_COMMON_LEGACY + default y if STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_COMMON_SRAM2_OPTIONS + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 + choice prompt "JTAG Configuration" default STM32_JTAG_DISABLE @@ -35,7 +95,6 @@ config STM32_JTAG_SW_ENABLE bool "Set JTAG-DP disabled and SW-DP enabled" endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM1 ADC channel" depends on STM32_TIM1_ADC @@ -63,7 +122,6 @@ config STM32_TIM1_ADC3 Reserve TIM1 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM2 ADC channel" depends on STM32_TIM2_ADC @@ -91,7 +149,6 @@ config STM32_TIM2_ADC3 Reserve TIM2 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM3 ADC channel" depends on STM32_TIM3_ADC @@ -119,7 +176,6 @@ config STM32_TIM3_ADC3 Reserve TIM3 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM4 ADC channel" depends on STM32_TIM4_ADC @@ -147,7 +203,6 @@ config STM32_TIM4_ADC3 Reserve TIM4 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM5 ADC channel" depends on STM32_TIM5_ADC @@ -175,7 +230,6 @@ config STM32_TIM5_ADC3 Reserve TIM5 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM8 ADC channel" depends on STM32_TIM8_ADC @@ -203,7 +257,6 @@ config STM32_TIM8_ADC3 Reserve TIM8 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM1 DAC channel" depends on STM32_TIM1_DAC @@ -220,7 +273,6 @@ config STM32_TIM1_DAC2 Reserve TIM1 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM2 DAC channel" depends on STM32_TIM2_DAC @@ -237,7 +289,6 @@ config STM32_TIM2_DAC2 Reserve TIM2 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM3 DAC channel" depends on STM32_TIM3_DAC @@ -254,7 +305,6 @@ config STM32_TIM3_DAC2 Reserve TIM3 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM4 DAC channel" depends on STM32_TIM4_DAC @@ -271,7 +321,6 @@ config STM32_TIM4_DAC2 Reserve TIM4 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM5 DAC channel" depends on STM32_TIM5_DAC @@ -288,7 +337,6 @@ config STM32_TIM5_DAC2 Reserve TIM5 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM6 DAC channel" depends on STM32_TIM6_DAC @@ -305,7 +353,6 @@ config STM32_TIM6_DAC2 Reserve TIM6 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM7 DAC channel" depends on STM32_TIM7_DAC @@ -322,7 +369,6 @@ config STM32_TIM7_DAC2 Reserve TIM7 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM8 DAC channel" depends on STM32_TIM8_DAC @@ -339,7 +385,6 @@ config STM32_TIM8_DAC2 Reserve TIM8 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM9 DAC channel" depends on STM32_TIM9_DAC @@ -356,7 +401,6 @@ config STM32_TIM9_DAC2 Reserve TIM9 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM10 DAC channel" depends on STM32_TIM10_DAC @@ -373,7 +417,6 @@ config STM32_TIM10_DAC2 Reserve TIM10 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM11 DAC channel" depends on STM32_TIM11_DAC @@ -390,7 +433,6 @@ config STM32_TIM11_DAC2 Reserve TIM11 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM12 DAC channel" depends on STM32_TIM12_DAC @@ -407,7 +449,6 @@ config STM32_TIM12_DAC2 Reserve TIM12 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM13 DAC channel" depends on STM32_TIM13_DAC @@ -424,7 +465,6 @@ config STM32_TIM13_DAC2 Reserve TIM13 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Select TIM14 DAC channel" depends on STM32_TIM14_DAC @@ -441,7 +481,6 @@ config STM32_TIM14_DAC2 Reserve TIM14 to trigger DAC2 endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "USART1 Driver Configuration" depends on STM32_USART1 @@ -463,7 +502,6 @@ config STM32_USART1_HCIUART depends on WIRELESS_BLUETOOTH endchoice # USART1 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "USART2 Driver Configuration" depends on STM32_USART2 @@ -485,7 +523,6 @@ config STM32_USART2_HCIUART depends on WIRELESS_BLUETOOTH endchoice # USART2 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "USART3 Driver Configuration" depends on STM32_USART3 @@ -507,7 +544,6 @@ config STM32_USART3_HCIUART depends on WIRELESS_BLUETOOTH endchoice # USART3 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "UART4 Driver Configuration" depends on STM32_UART4 @@ -524,7 +560,6 @@ config STM32_UART4_1WIREDRIVER select STM32_1WIREDRIVER endchoice # UART1 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "UART5 Driver Configuration" depends on STM32_UART5 @@ -541,7 +576,6 @@ config STM32_UART5_1WIREDRIVER select STM32_1WIREDRIVER endchoice # UART5 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "USART6 Driver Configuration" depends on STM32_USART6 @@ -563,7 +597,6 @@ config STM32_USART6_HCIUART depends on WIRELESS_BLUETOOTH endchoice # USART6 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "LPUART1 Driver Configuration" depends on STM32_LPUART1 @@ -580,7 +613,190 @@ config STM32_LPUART1_1WIREDRIVER select STM32_1WIREDRIVER endchoice # LPUART1 Driver Configuration -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +choice + prompt "UART8 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART choice prompt "RTC clock source" depends on STM32_RTC @@ -602,7 +818,6 @@ config STM32_RTC_HSECLOCK Drive the RTC with the HSE clock, divided down to 1MHz. endchoice # RTC clock source -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "MII clock configuration" depends on STM32_MII @@ -635,7 +850,6 @@ config STM32_MII_EXTCLK clock. Default: Use MC0[1] endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "RMII clock configuration" depends on STM32_RMII @@ -668,7 +882,7 @@ config STM32_RMII_EXTCLK clock. Default: Use MC0[1] endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + choice prompt "CAN character driver or SocketCAN support" depends on STM32_CAN @@ -684,7 +898,7 @@ config STM32_CAN_SOCKET select NET_CAN_HAVE_ERRORS endchoice # CAN character driver or SocketCAN support -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + choice prompt "FDCAN character driver or SocketCAN support" depends on STM32_FDCAN @@ -701,10 +915,11 @@ config STM32_FDCAN_SOCKET select NET_CAN_HAVE_CANFD endchoice # FDCAN character driver or SocketCAN support -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + +if STM32_FDCAN1 + choice prompt "FDCAN1 frame format" - depends on STM32_FDCAN1 default STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_ISO11898_1 @@ -715,13 +930,12 @@ config STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN1 frame format -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + choice prompt "FDCAN1 mode" - depends on STM32_FDCAN1 default STM32_FDCAN1_CLASSIC config STM32_FDCAN1_CLASSIC @@ -739,13 +953,16 @@ config STM32_FDCAN1_FD_BRS bool "CAN FD with fast bit rate switching" depends on CAN_FD || NET_CAN_CANFD ---help--- - Enable CAN FD mode with fast bit rate switching mode. + Enable CAN FD mode with fast bit rate switching mode. endchoice # FDCAN1 mode -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + choice prompt "FDCAN2 frame format" - depends on STM32_FDCAN2 default STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_ISO11898_1 @@ -756,13 +973,12 @@ config STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN2 frame format -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + choice prompt "FDCAN2 mode" - depends on STM32_FDCAN2 default STM32_FDCAN2_CLASSIC config STM32_FDCAN2_CLASSIC @@ -783,7 +999,8 @@ config STM32_FDCAN2_FD_BRS Enable CAN FD mode with fast bit rate switching mode. endchoice # FDCAN2 mode -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. + +endif # STM32_FDCAN2 choice prompt "Layer 1 color format" depends on STM32_LTDC @@ -822,7 +1039,6 @@ config STM32_LTDC_L1_ARGB8888 depends on !STM32_FB_CMAP endchoice # Layer 1 color format -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Layer 2 (top layer) color format" depends on STM32_LTDC && STM32_LTDC_L2 @@ -861,7 +1077,6 @@ config STM32_LTDC_L2_ARGB8888 depends on STM32_LTDC_L1_ARGB8888 endchoice # Layer 2 color format -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Input channel sampling frequency" depends on STM32_QENCODER_FILTER @@ -890,7 +1105,6 @@ config STM32_QENCODER_SAMPLE_FDTS_32 bool "fDTS/32" endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "Input channel event count" depends on STM32_QENCODER_FILTER @@ -922,7 +1136,6 @@ config STM32_QENCODER_SAMPLE_EVENT_8 depends on !STM32_QENCODER_SAMPLE_FDTS endchoice -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "FOC ADC trigger selection" depends on STM32_FOC @@ -943,7 +1156,6 @@ config STM32_FOC_ADC_TRGO It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). endchoice # "FOC ADC trigger selection" -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "FOC0 device ADC selection" depends on STM32_FOC_FOC0 @@ -970,7 +1182,6 @@ config STM32_FOC_FOC0_ADC4 select STM32_FOC_USE_ADC4 endchoice # "FOC0 device ADC selection" -# Moved from arch/arm/src/stm32/Kconfig and shared by STM32 families. choice prompt "FOC1 device ADC selection" depends on STM32_FOC_FOC1 @@ -997,7 +1208,6 @@ config STM32_FOC_FOC1_ADC4 select STM32_FOC_USE_ADC4 endchoice # "FOC0 device ADC selection" -# Moved from arch/arm/src/stm32f0l0g0/Kconfig and shared by STM32 families. choice prompt "Override Flash Size Designator" default STM32_FLASH_OVERRIDE_DEFAULT @@ -1076,7 +1286,6 @@ config STM32_FLASH_OVERRIDE_G_1024 bool "G 1024 KB" endchoice # Override Flash Size Designator -# Moved from arch/arm/src/stm32f0l0g0/Kconfig and shared by STM32 families. choice prompt "Select TIM15 ADC channel" depends on STM32_TIM15_ADC @@ -1104,7 +1313,6 @@ config STM32_TIM15_ADC3 Reserve TIM15 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "Transfer technique" depends on STM32_QSPI @@ -1131,7 +1339,6 @@ config STM32_QSPI_DMA Use DMA to improve QSPI transfer performance. endchoice -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "Bank selection" depends on STM32_QSPI @@ -1151,7 +1358,6 @@ config STM32_QSPI_MODE_DUAL bool "Dual Bank" endchoice -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "DMA Priority" depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA @@ -1188,7 +1394,6 @@ config STM32_QSPI_DMAPRIORITY_LOW 'Low' priority. endchoice -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "Operation mode" depends on STM32_SAI @@ -1213,7 +1418,6 @@ config STM32_SAI_DMA Use DMA to improve SAI transfer performance. endchoice # Operation mode -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "SAI1 synchronization enable" depends on STM32_SAI1_A && STM32_SAI1_B @@ -1232,7 +1436,6 @@ config STM32_SAI1_B_SYNC_WITH_A bool "Block B is synchronous with Block A" endchoice # SAI1 synchronization enable -# Moved from arch/arm/src/stm32f7/Kconfig and shared by STM32 families. choice prompt "SAI2 synchronization enable" depends on STM32_SAI2_A && STM32_SAI2_B @@ -1251,11 +1454,6 @@ config STM32_SAI2_B_SYNC_WITH_A bool "Block B is synchronous with Block A" endchoice # SAI2 synchronization enable -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. choice prompt "Select ADC for use with TIM6" depends on STM32_TIM6_ADC @@ -1283,9 +1481,6 @@ config STM32_TIM6_ADC3 Reserve TIM6 to trigger ADC3 endchoice -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32h5/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. choice prompt "LPTIM1 clock source" default STM32_LPTIM1_CLK_APB1 @@ -1303,7 +1498,6 @@ config STM32_LPTIM1_CLK_HSI bool "Clock LPTIM1 from HSI" endchoice -# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. choice prompt "LPTIM2 clock source" default STM32_LPTIM2_CLK_APB1 @@ -1321,6 +1515,7316 @@ config STM32_LPTIM2_CLK_HSI bool "Clock LPTIM2 from HSI" endchoice -# Moved from arch/arm/src/stm32l4/Kconfig and shared by STM32 families. -# Moved from arch/arm/src/stm32l5/Kconfig and shared by STM32 families. + + +config STM32_TIM_PWM_COMMON + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_TIM_PWM_NO_F0_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_TIM_PWM_ADVANCED_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_SINGLECHAN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_INTERNAL_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 + +config STM32_TIM_PWM_STM32PWM_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + bool + default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_CHMODE_LEGACY_COMMON + bool + default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 + +config STM32_TIM_PWM_CHMODE_LIMITED_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_ADC_TIMTRIG_TRGO2_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_ADC_TIMTRIG_TRGO_COMMON + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_PWM_MULTICHAN_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_SPI_CORE_DMA_CAPABLE + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_RTC_MAGIC_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC + default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC + +config STM32_ADC1_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC1_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC2_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER + +config STM32_ADC2_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER + +config STM32_ADC3_TIMER_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_QENCODER_MAIN + bool + default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_QENCODER_16BIT_CAPABLE + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_LPTIM1_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + +config STM32_ADC1_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP + +config STM32_ADC2_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC3_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX + + +config STM32_FLASH_CONFIG_4 + bool + +config STM32_FLASH_CONFIG_6 + bool + +config STM32_FLASH_CONFIG_8 + bool + +config STM32_FLASH_CONFIG_B + bool + +config STM32_FLASH_CONFIG_C + bool + +config STM32_FLASH_CONFIG_D + bool + +config STM32_FLASH_CONFIG_E + bool + +config STM32_FLASH_CONFIG_F + bool + +config STM32_FLASH_CONFIG_G + bool + +config STM32_FLASH_CONFIG_I + bool + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + +config STM32_VALUELINE + bool + select STM32_HAVE_USART3 if STM32_COMMON_LEGACY + select STM32_HAVE_UART4 if STM32_COMMON_LEGACY + select STM32_HAVE_UART5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY + select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 + select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_SYSCFG + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TSC + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC1_DMA + bool + +config STM32_HAVE_ADC2_DMA + bool + +config STM32_HAVE_ADC3_DMA + bool + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_COMP1 + bool + +config STM32_HAVE_COMP2 + bool + +config STM32_HAVE_COMP3 + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_QSPI + bool + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_OPAMP1 + bool + +config STM32_HAVE_OPAMP2 + bool + +config STM32_HAVE_OPAMP3 + bool + +config STM32_HAVE_OPAMP4 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +config STM32_ADC1 + bool "ADC1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC2 + bool "ADC2" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC3 + bool "ADC3" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC4 + bool "ADC4" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if STM32_COMMON_LEGACY + select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_COMP1 + bool "COMP1" + depends on STM32_HAVE_COMP1 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + depends on STM32_HAVE_COMP2 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 + +config STM32_BKP + bool "BKP" + depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_AES + bool "128-bit AES" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CEC + bool "CEC" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 + +config STM32_CRC + bool "CRC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +config STM32_CRYP + bool "CRYP" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH + +config STM32_DMA1 + bool "DMA1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +config STM32_RTC + bool "RTC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB + select RTC if !ARCH_CHIP_STM32L5 + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_PWR + bool "PWR" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_IWDG + bool "IWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +config STM32_ADC + bool + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_SPI + bool + +config STM32_SPI_DMA + bool "SPI DMA" + depends on STM32_SPI_CORE_DMA_CAPABLE + ---help--- + Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_I2C + bool + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_TIM + bool + +config STM32_PWM + bool + +config STM32_COMP + bool "COMP" + depends on STM32_HAVE_COMP + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +config STM32_OPAMP + bool "OPAMP" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) + select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) + select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_TIM_PWM_SINGLECHAN_COMMON + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_PWM_MULTICHAN_CAPABLE + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_PULSECOUNT + bool + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_HAVE_ADC1_TIMER + bool + +config STM32_HAVE_ADC2_TIMER + bool + +config STM32_HAVE_ADC3_TIMER + bool + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_TIMER_CAPABLE + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_USART + bool + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +#if STM32_I2S + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_RTC_MAGIC_CAPABLE + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + depends on STM32_CAN + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + depends on STM32_CAN + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on STM32_CAN && DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC3_JEXTSEL + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_LCD + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_IO_CONFIG_R + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_V + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_I + bool + +config STM32_IO_CONFIG_Z + bool + +config STM32_IO_CONFIG_B + bool + +config STM32_IO_CONFIG_A + bool + +config STM32_HAVE_PHY_POLLED + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_HASH + bool + +config STM32_HAVE_DFSDM1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +config STM32_SAI + bool + +menu "SDIO Configuration" + depends on STM32_COMMON_LEGACY && STM32_SDIO + +config STM32_SDIO_CARD + bool "SDIO Card support" + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # SDIO Configuration + +config STM32_SDMMC + bool + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +config STM32_QUADSPI + bool "QuadSPI" + depends on STM32_COMMON_F7_H7 + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +endif # STM32_SDMMC + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + depends on STM32_COMMON_F7_H7 + ---help--- + Enables special, board-specific STM32 clock configuration. + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +config STM32_HAVE_SMPS + bool + +config STM32_HAVE_ETHERNET + bool + +config STM32_LPTIM + bool + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_IO_CONFIG_K + bool + +config STM32_IO_CONFIG_T + bool + +config STM32_IO_CONFIG_C + bool + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_J + bool + +config STM32_IO_CONFIG_M + bool + +config STM32_IO_CONFIG_Q + bool + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_HAVE_COMP + bool + +config STM32_HAVE_USART1 + bool + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 1 + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 1 + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_IPCC + bool "IPCC" + depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index dd3ca73b81c47..2de02dd875b1f 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -5,6 +5,26 @@ comment "STM32 Configuration Options" +config STM32_COMMON_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 + select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX + select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) + select STM32_HAVE_DMA2D if STM32_STM32F429 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD if STM32_STM32L15XX + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX + select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX + select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "STM32 Chip Selection" default ARCH_CHIP_STM32F103ZE @@ -1210,41 +1230,9 @@ endchoice config STM32_FLASH_CONFIG_DEFAULT bool -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - config STM32_FLASH_CONFIG_Z bool -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - - -# This is really 15XX/16XX, but we treat the two the same. config STM32_STM32L15XX bool default n @@ -1255,6 +1243,7 @@ config STM32_STM32L15XX select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM9 @@ -1270,12 +1259,6 @@ config STM32_STM32L15XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_ENERGYLITE - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - config STM32_STM32F10XX bool default n @@ -1283,6 +1266,7 @@ config STM32_STM32F10XX select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_IP_DBGMCU_V1 select STM32_HAVE_IP_TIMERS_V1 @@ -1291,25 +1275,6 @@ config STM32_STM32F10XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - config STM32_CONNECTIVITYLINE bool default n @@ -1318,6 +1283,7 @@ config STM32_CONNECTIVITYLINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1336,6 +1302,7 @@ config STM32_PERFORMANCELINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1363,6 +1330,7 @@ config STM32_HIGHDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1378,6 +1346,7 @@ config STM32_MEDIUMDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1393,6 +1362,7 @@ config STM32_LOWDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1414,6 +1384,7 @@ config STM32_STM32F20XX select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1463,6 +1434,7 @@ config STM32_STM32F30XX select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 @@ -1508,6 +1480,7 @@ config STM32_STM32F33XX select STM32_HAVE_OPAMP2 select STM32_HAVE_CCM select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM15 @@ -1535,6 +1508,7 @@ config STM32_STM32F37XX select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1595,6 +1569,7 @@ config STM32_STM32F401 select STM32_STM32F4XXX select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1612,6 +1587,7 @@ config STM32_STM32F410 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM9 @@ -1624,6 +1600,7 @@ config STM32_STM32F411 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1675,6 +1652,7 @@ config STM32_STM32F405 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1749,6 +1727,7 @@ config STM32_STM32F427 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1794,6 +1773,7 @@ config STM32_STM32F429 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -2120,14 +2100,6 @@ config STM32_STM32G474V select STM32_HAVE_UART4 select STM32_HAVE_UART5 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available @@ -2145,18 +2117,6 @@ config STM32_HAVE_OVERDRIVE bool default n -config STM32_HAVE_AES - bool - default n - -config STM32_HAVE_CRYP - bool - default n - -config STM32_HAVE_CCM - bool - default n - config STM32_HAVE_DMA1_CHAN8 bool default n @@ -2165,9325 +2125,2516 @@ config STM32_HAVE_DMA2_CHAN678 bool default n -config STM32_HAVE_DMAMUX - bool - default n - config STM32_HAVE_UCPD bool default n -config STM32_HAVE_USBDEV +config STM32_HAVE_FMAC bool default n -config STM32_HAVE_USBFS +config STM32_HAVE_IOCOMPENSATION bool default n -config STM32_HAVE_OTGFS +config STM32_HAVE_HRTIM1 bool default n -config STM32_HAVE_FMC +config STM32_HAVE_HRTIM1_PLLCLK bool default n -config STM32_HAVE_FMAC +config STM32_HAVE_TIM18 bool default n -config STM32_HAVE_FSMC +config STM32_HAVE_TIM19 bool default n -config STM32_HAVE_FDCAN1 +config STM32_HAVE_TIM20 bool default n -config STM32_HAVE_FDCAN2 +config STM32_HAVE_ADC1 bool - default n + default y -config STM32_HAVE_FDCAN3 +config STM32_HAVE_ADC4 bool default n -config STM32_HAVE_IOCOMPENSATION +config STM32_HAVE_ADC5 bool default n -config STM32_HAVE_HRTIM1 +config STM32_HAVE_ADC4_DMA bool default n -config STM32_HAVE_HRTIM1_PLLCLK +config STM32_HAVE_ADC5_DMA bool default n -config STM32_HAVE_LTDC +config STM32_HAVE_SDADC1 bool default n -config STM32_HAVE_USART2 +config STM32_HAVE_SDADC2 bool default n -config STM32_HAVE_USART3 +config STM32_HAVE_SDADC3 bool default n -config STM32_HAVE_UART4 +config STM32_HAVE_SDADC1_DMA bool default n -config STM32_HAVE_UART5 +config STM32_HAVE_SDADC2_DMA bool default n -config STM32_HAVE_USART6 +config STM32_HAVE_SDADC3_DMA bool default n -config STM32_HAVE_UART7 +config STM32_HAVE_COMP4 bool default n -config STM32_HAVE_UART8 +config STM32_HAVE_COMP5 bool default n -config STM32_HAVE_TIM1 +config STM32_HAVE_COMP6 bool default n -config STM32_HAVE_TIM2 +config STM32_HAVE_COMP7 bool default n -config STM32_HAVE_TIM3 +config STM32_HAVE_CORDIC bool default n -config STM32_HAVE_TIM4 +config STM32_HAVE_DAC3 bool default n -config STM32_HAVE_TIM5 +config STM32_HAVE_DAC4 bool default n -config STM32_HAVE_TIM6 +config STM32_HAVE_ETHMAC bool default n -config STM32_HAVE_TIM7 +config STM32_HAVE_I2C1 bool default n -config STM32_HAVE_TIM8 +config STM32_HAVE_I2S3 bool default n -config STM32_HAVE_TIM9 +config STM32_HAVE_OPAMP5 bool default n -config STM32_HAVE_TIM10 +config STM32_HAVE_OPAMP6 bool default n -config STM32_HAVE_TIM11 - bool - default n +# These are STM32 peripherals IP blocks -config STM32_HAVE_TIM12 +config STM32_HAVE_IP_DBGMCU_V1 bool default n -config STM32_HAVE_TIM13 +config STM32_HAVE_IP_DBGMCU_V2 bool default n -config STM32_HAVE_TIM14 +config STM32_HAVE_IP_DBGMCU_V3 bool default n -config STM32_HAVE_TIM15 +config STM32_HAVE_IP_I2C_V1 bool default n -config STM32_HAVE_TIM16 +config STM32_HAVE_IP_I2C_V2 bool default n -config STM32_HAVE_TIM17 +config STM32_HAVE_IP_DMA_V1 bool default n -config STM32_HAVE_TIM18 +config STM32_HAVE_IP_DMA_V2 bool default n -config STM32_HAVE_TIM19 +config STM32_HAVE_IP_TIMERS_V1 bool default n -config STM32_HAVE_TIM20 +config STM32_HAVE_IP_TIMERS_V2 bool default n -config STM32_HAVE_TSC +config STM32_HAVE_IP_TIMERS_V3 bool default n -config STM32_HAVE_ADC1 - bool - default y - -config STM32_HAVE_ADC2 +config STM32_HAVE_IP_ADC_V1 bool default n -config STM32_HAVE_ADC3 +config STM32_HAVE_IP_ADC_V1_BASIC bool default n + select STM32_HAVE_IP_ADC_V1 -config STM32_HAVE_ADC4 +config STM32_HAVE_IP_ADC_V2 bool default n -config STM32_HAVE_ADC5 +config STM32_HAVE_IP_ADC_V2_BASIC bool default n + select STM32_HAVE_IP_ADC_V2 -config STM32_HAVE_ADC1_DMA +config STM32_HAVE_IP_COMP_V1 bool default n -config STM32_HAVE_ADC2_DMA +config STM32_HAVE_IP_COMP_V2 bool default n -config STM32_HAVE_ADC3_DMA +config STM32_HAVE_IP_DAC_V1 bool default n -config STM32_HAVE_ADC4_DMA +config STM32_HAVE_IP_DAC_V2 bool default n -config STM32_HAVE_ADC5_DMA - bool - default n +# These are the peripheral selections proper -config STM32_HAVE_SDADC1 - bool +config STM32_ADC5 + bool "ADC5" default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_HAVE_ADC5_DMA if STM32_DMA2 + select STM32_HAVE_ADC5_DMA if STM32_DMAMUX -config STM32_HAVE_SDADC2 - bool +config STM32_SDADC1 + bool "SDADC1" default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC1_DMA if STM32_DMA2 -config STM32_HAVE_SDADC3 - bool +config STM32_SDADC2 + bool "SDADC2" default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC2_DMA if STM32_DMA2 -config STM32_HAVE_SDADC1_DMA - bool +config STM32_SDADC3 + bool "SDADC3" default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_HAVE_SDADC3_DMA if STM32_DMA2 -config STM32_HAVE_SDADC2_DMA - bool +config STM32_COMP3 + bool "COMP3" default n + select STM32_COMP + depends on STM32_HAVE_COMP3 -config STM32_HAVE_SDADC3_DMA - bool +config STM32_COMP4 + bool "COMP4" default n + select STM32_COMP + depends on STM32_HAVE_COMP4 -config STM32_HAVE_CAN1 - bool +config STM32_COMP5 + bool "COMP5" default n + select STM32_COMP + depends on STM32_HAVE_COMP5 -config STM32_HAVE_CAN2 - bool +config STM32_COMP6 + bool "COMP6" default n + select STM32_COMP + depends on STM32_HAVE_COMP6 -config STM32_HAVE_COMP1 - bool +config STM32_COMP7 + bool "COMP7" default n + select STM32_COMP + depends on STM32_HAVE_COMP7 -config STM32_HAVE_COMP2 - bool +config STM32_CCMDATARAM + bool "CMD/DATA RAM" default n + depends on STM32_STM32F4XXX -config STM32_HAVE_COMP3 - bool - default n +if STM32_DAC1 -config STM32_HAVE_COMP4 - bool +config STM32_DAC1CH1 + bool "DAC1CH1" default n -config STM32_HAVE_COMP5 - bool +config STM32_DAC1CH2 + bool "DAC1CH2" default n -config STM32_HAVE_COMP6 - bool - default n +endif #STM32_DAC1 -config STM32_HAVE_COMP7 - bool - default n +if STM32_DAC2 -config STM32_HAVE_CORDIC - bool +config STM32_DAC2CH1 + bool "DAC2CH1" default n -config STM32_HAVE_CRS - bool - default n +endif #STM32_DAC2 -config STM32_HAVE_DAC1 - bool +config STM32_DAC3 + bool "DAC3" default n + depends on STM32_HAVE_DAC3 + select STM32_DAC -config STM32_HAVE_DAC2 - bool - default n +if STM32_DAC3 -config STM32_HAVE_DAC3 - bool +config STM32_DAC3CH1 + bool "DAC3CH1 Internal" default n -config STM32_HAVE_DAC4 - bool +config STM32_DAC3CH2 + bool "DAC3CH2 Internal" default n -config STM32_HAVE_QSPI - bool - default n +endif #STM32_DAC3 -config STM32_HAVE_RNG - bool +config STM32_DAC4 + bool "DAC4" default n + depends on STM32_HAVE_DAC4 + select STM32_DAC -config STM32_HAVE_ETHMAC - bool - default n +if STM32_DAC4 -config STM32_HAVE_I2C1 - bool +config STM32_DAC4CH1 + bool "DAC4CH1 Internal" default n -config STM32_HAVE_I2C2 - bool +config STM32_DAC4CH2 + bool "DAC4CH2 Internal" default n -config STM32_HAVE_I2C3 - bool - default n +endif #STM32_DAC4 -config STM32_HAVE_I2C4 +config STM32_HRTIM bool default n -config STM32_HAVE_LPTIM1 - bool +config STM32_HRTIM1 + bool "HRTIM1" default n + depends on STM32_HAVE_HRTIM1 + select STM32_HRTIM -config STM32_HAVE_LPUART1 - bool - default n +if STM32_HRTIM1 -config STM32_HAVE_SPI1 - bool +config STM32_HRTIM_MASTER + bool "HRTIM MASTER" default n + ---help--- + Enable HRTIM Master Timer -config STM32_HAVE_SPI2 - bool +config STM32_HRTIM_TIMA + bool "HRTIM TIMA" default n + ---help--- + Enable HRTIM Timer A -config STM32_HAVE_SPI3 - bool +config STM32_HRTIM_TIMB + bool "HRTIM TIMB" default n + ---help--- + Enable HRTIM Timer B -config STM32_HAVE_I2S3 - bool +config STM32_HRTIM_TIMC + bool "HRTIM TIMC" default n + ---help--- + Enable HRTIM Timer C -config STM32_HAVE_SPI4 - bool +config STM32_HRTIM_TIMD + bool "HRTIM TIMD" default n + ---help--- + Enable HRTIM Timer D -config STM32_HAVE_SPI5 - bool +config STM32_HRTIM_TIME + bool "HRTIM TIME" default n + ---help--- + Enable HRTIM Timer E -config STM32_HAVE_SPI6 - bool - default n +endif # STM32_HRTIM -config STM32_HAVE_SAIPLL - bool +config STM32_I2C1_SLAVE + bool "I2C1 Slave" default n + depends on !STM32_I2C1 && I2C_SLAVE + select STM32_I2C_SLAVE -config STM32_HAVE_I2SPLL - bool +config STM32_I2C2_SLAVE + bool "I2C2 Slave" default n + depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE + select STM32_I2C_SLAVE -config STM32_HAVE_OPAMP1 - bool +config STM32_I2C3_SLAVE + bool "I2C3 Slave" default n + depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE + select STM32_I2C_SLAVE -config STM32_HAVE_OPAMP2 - bool +config STM32_OPAMP1 + bool "OPAMP1" default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP1 -config STM32_HAVE_OPAMP3 - bool +config STM32_OPAMP2 + bool "OPAMP2" default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP2 -config STM32_HAVE_OPAMP4 - bool +config STM32_OPAMP3 + bool "OPAMP3" default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP3 -config STM32_HAVE_OPAMP5 - bool +config STM32_OPAMP4 + bool "OPAMP4" default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP4 -config STM32_HAVE_OPAMP6 - bool +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" default n + depends on STM32_HAVE_UCPD + select USBDEV -# These are STM32 peripherals IP blocks +if STM32_LCD -config STM32_HAVE_IP_DBGMCU_V1 - bool - default n +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK -config STM32_HAVE_IP_DBGMCU_V2 - bool - default n +config LCD_LSICLOCK + bool "Internal Low Speed Clock" -config STM32_HAVE_IP_DBGMCU_V3 - bool - default n +config LCD_LSECLOCK + bool "External Low Speed Clock" -config STM32_HAVE_IP_I2C_V1 - bool - default n +config LCD_HSECLOCK + bool "External High Speed Clock" -config STM32_HAVE_IP_I2C_V2 - bool - default n +endchoice +endif # STM32_LCD -config STM32_HAVE_IP_DMA_V1 - bool - default n +endmenu -config STM32_HAVE_IP_DMA_V2 +config STM32_SDADC bool default n -config STM32_HAVE_IP_TIMERS_V1 +config STM32_I2C_SLAVE bool default n -config STM32_HAVE_IP_TIMERS_V2 +config STM32_CAP bool default n -config STM32_HAVE_IP_TIMERS_V3 - bool +config STM32_NOEXT_VECTORS + bool "Disable the ARMv7-M EXT vectors" default n + ---help--- + Sometimes you may not need any Vector support beyond SysTick + and wish to save memory. This applies only to ARMv7-M architectures. -config STM32_HAVE_IP_ADC_V1 - bool - default n +menu "Alternate Pin Mapping" + depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 +choice + prompt "CAN1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_CAN1 + default STM32_CAN1_NO_REMAP -config STM32_HAVE_IP_ADC_V2 - bool - default n +config STM32_CAN1_NO_REMAP + bool "No pin remapping" -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 +config STM32_CAN1_REMAP1 + bool "CAN1 alternate pin remapping #1" -config STM32_HAVE_IP_COMP_V1 - bool - default n +config STM32_CAN1_REMAP2 + bool "CAN1 alternate pin remapping #2" -config STM32_HAVE_IP_COMP_V2 - bool - default n +endchoice -config STM32_HAVE_IP_DAC_V1 - bool +config STM32_CAN2_REMAP + bool "CAN2 Alternate Pin Mapping" default n + depends on STM32_CONNECTIVITYLINE && STM32_CAN2 -config STM32_HAVE_IP_DAC_V2 - bool +config STM32_CEC_REMAP + bool "CEC Alternate Pin Mapping" default n + depends on STM32_STM32F10XX && STM32_CEC -# These are the peripheral selections proper - -config STM32_ADC1 - bool "ADC1" +config STM32_ETH_REMAP + bool "Ethernet Alternate Pin Mapping" default n - select STM32_ADC - select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2 - select STM32_HAVE_ADC1_DMA if STM32_DMAMUX + depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC -config STM32_ADC2 - bool "ADC2" +config STM32_I2C1_REMAP + bool "I2C1 Alternate Pin Mapping" default n - select STM32_ADC - depends on STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA if STM32_DMA2 - select STM32_HAVE_ADC2_DMA if STM32_DMAMUX + depends on STM32_STM32F10XX && STM32_I2C1 -config STM32_ADC3 - bool "ADC3" +config STM32_SPI1_REMAP + bool "SPI1 Alternate Pin Mapping" default n - select STM32_ADC - depends on STM32_HAVE_ADC3 - select STM32_HAVE_ADC3_DMA if STM32_DMA2 - select STM32_HAVE_ADC3_DMA if STM32_DMAMUX + depends on STM32_STM32F10XX && STM32_SPI1 -config STM32_ADC4 - bool "ADC4" +config STM32_SPI3_REMAP + bool "SPI3 Alternate Pin Mapping" default n - select STM32_ADC - depends on STM32_HAVE_ADC4 - select STM32_HAVE_ADC4_DMA if STM32_DMA2 - select STM32_HAVE_ADC4_DMA if STM32_DMAMUX + depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE -config STM32_ADC5 - bool "ADC5" +config STM32_I2S3_REMAP + bool "I2S3 Alternate Pin Mapping" default n - select STM32_ADC - depends on STM32_HAVE_ADC5 - select STM32_HAVE_ADC5_DMA if STM32_DMA2 - select STM32_HAVE_ADC5_DMA if STM32_DMAMUX + depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE -config STM32_SDADC1 - bool "SDADC1" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC1_DMA if STM32_DMA2 +choice + prompt "TIM1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM1 + default STM32_TIM1_NO_REMAP -config STM32_SDADC2 - bool "SDADC2" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC2_DMA if STM32_DMA2 +config STM32_TIM1_NO_REMAP + bool "No pin remapping" -config STM32_SDADC3 - bool "SDADC3" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC3 - select STM32_HAVE_SDADC3_DMA if STM32_DMA2 +config STM32_TIM1_FULL_REMAP + bool "Full pin remapping" -config STM32_COMP1 - bool "COMP1" - default n - select STM32_COMP - depends on STM32_HAVE_COMP1 +config STM32_TIM1_PARTIAL_REMAP + bool "Partial pin remapping" -config STM32_COMP2 - bool "COMP2" - default n - select STM32_COMP - depends on STM32_HAVE_COMP2 +endchoice -config STM32_COMP3 - bool "COMP3" - default n - select STM32_COMP - depends on STM32_HAVE_COMP3 +choice + prompt "TIM2 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM2 + default STM32_TIM2_NO_REMAP -config STM32_COMP4 - bool "COMP4" - default n - select STM32_COMP - depends on STM32_HAVE_COMP4 +config STM32_TIM2_NO_REMAP + bool "No pin remapping" -config STM32_COMP5 - bool "COMP5" - default n - select STM32_COMP - depends on STM32_HAVE_COMP5 +config STM32_TIM2_FULL_REMAP + bool "Full pin remapping" -config STM32_COMP6 - bool "COMP6" - default n - select STM32_COMP - depends on STM32_HAVE_COMP6 +config STM32_TIM2_PARTIAL_REMAP_1 + bool "Partial pin remapping #1" -config STM32_COMP7 - bool "COMP7" - default n - select STM32_COMP - depends on STM32_HAVE_COMP7 +config STM32_TIM2_PARTIAL_REMAP_2 + bool "Partial pin remapping #2" -config STM32_CORDIC - bool "CORDIC Accelerator" - default n - depends on STM32_HAVE_CORDIC - depends on MATH_CORDIC_USE_Q31 +endchoice -config STM32_BKP - bool "BKP" - default n - depends on STM32_STM32F10XX +choice + prompt "TIM3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM3 + default STM32_TIM3_NO_REMAP -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX +config STM32_TIM3_NO_REMAP + bool "No pin remapping" -config STM32_CAN1 - bool "CAN1" - default n - select STM32_CAN - depends on STM32_HAVE_CAN1 +config STM32_TIM3_FULL_REMAP + bool "Full pin remapping" -config STM32_CAN2 - bool "CAN2" - default n - select STM32_CAN - depends on STM32_HAVE_CAN2 +config STM32_TIM3_PARTIAL_REMAP + bool "Partial pin remapping" -config STM32_CCMDATARAM - bool "CMD/DATA RAM" - default n - depends on STM32_STM32F4XXX +endchoice -config STM32_AES - bool "128-bit AES" +config STM32_TIM4_REMAP + bool "TIM4 Alternate Pin Mapping" default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST + depends on STM32_STM32F10XX && STM32_TIM4 -config STM32_CEC - bool "CEC" +config STM32_TIM9_REMAP + bool "TIM9 Alternate Pin Mapping" default n - depends on STM32_VALUELINE + depends on STM32_STM32F10XX && STM32_TIM9 -config STM32_CRC - bool "CRC" +config STM32_TIM10_REMAP + bool "TIM10 Alternate Pin Mapping" default n + depends on STM32_STM32F10XX && STM32_TIM10 -config STM32_CRS - bool "CRS (Clock Recovery System)" +config STM32_TIM11_REMAP + bool "TIM11 Alternate Pin Mapping" default n - depends on STM32_HAVE_CRS + depends on STM32_STM32F10XX && STM32_TIM11 -config STM32_CRYP - bool "CRYP" +config STM32_TIM12_REMAP + bool "TIM12 Alternate Pin Mapping" default n - depends on STM32_HAVE_CRYP + depends on STM32_STM32F10XX && STM32_TIM12 -config STM32_DMA1 - bool "DMA1" +config STM32_TIM13_REMAP + bool "TIM13 Alternate Pin Mapping" default n - select STM32_DMA - select ARCH_DMA + depends on STM32_STM32F10XX && STM32_TIM13 -config STM32_DMA2 - bool "DMA2" +config STM32_TIM14_REMAP + bool "TIM14 Alternate Pin Mapping" default n - select STM32_DMA - select ARCH_DMA - depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) + depends on STM32_STM32F10XX && STM32_TIM14 -config STM32_DMAMUX1 - bool "DMAMUX1" +config STM32_TIM15_REMAP + bool "TIM15 Alternate Pin Mapping" default n - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX + depends on STM32_STM32F10XX && STM32_TIM15 -config STM32_DAC1 - bool "DAC1" +config STM32_TIM16_REMAP + bool "TIM16 Alternate Pin Mapping" default n - depends on STM32_HAVE_DAC1 - select STM32_DAC + depends on STM32_STM32F10XX && STM32_TIM16 -if STM32_DAC1 +config STM32_TIM17_REMAP + bool "TIM17 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM17 -config STM32_DAC1CH1 - bool "DAC1CH1" +config STM32_USART1_REMAP + bool "USART1 Alternate Pin Mapping" default n + depends on STM32_STM32F10XX && STM32_USART1 -config STM32_DAC1CH2 - bool "DAC1CH2" +config STM32_USART2_REMAP + bool "USART2 Alternate Pin Mapping" default n + depends on STM32_STM32F10XX && STM32_USART2 -endif #STM32_DAC1 +choice + prompt "USART3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_USART3 + default STM32_USART3_NO_REMAP -config STM32_DAC2 - bool "DAC2" - default n - depends on STM32_HAVE_DAC2 - select STM32_DAC +config STM32_USART3_NO_REMAP + bool "No pin remapping" -if STM32_DAC2 +config STM32_USART3_FULL_REMAP + bool "Full pin remapping" -config STM32_DAC2CH1 - bool "DAC2CH1" - default n +config STM32_USART3_PARTIAL_REMAP + bool "Partial pin remapping" -endif #STM32_DAC2 +endchoice -config STM32_DAC3 - bool "DAC3" - default n - depends on STM32_HAVE_DAC3 - select STM32_DAC +endmenu -if STM32_DAC3 +config STM32_FLASH_ICACHE + bool "Enable FLASH Instruction Cache" + default y + depends on STM32_HAVE_FLASH_ICACHE + ---help--- + Enable the FLASH instruction cache. -config STM32_DAC3CH1 - bool "DAC3CH1 Internal" +config STM32_FLASH_DCACHE + bool "Enable FLASH Data Cache" + default y + depends on STM32_HAVE_FLASH_DCACHE + ---help--- + Enable the FLASH data cache. + +config STM32_FORCEPOWER + bool "Force power" default n + ---help--- + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). -config STM32_DAC3CH2 - bool "DAC3CH2 Internal" +config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" default n + ---help--- + Enables special, board-specific STM32 clock configuration. -endif #STM32_DAC3 +config STM32_SAIPLL + bool "SAIPLL" + default n + depends on STM32_HAVE_SAIPLL + ---help--- + The STM32F446 has a separate PLL for the SAI block. + Set this true and provide configuration parameters in + board.h to use this PLL. -config STM32_DAC4 - bool "DAC4" +config STM32_I2SPLL + bool "I2SPLL" default n - depends on STM32_HAVE_DAC4 - select STM32_DAC + depends on STM32_HAVE_I2SPLL + ---help--- + The STM32F446 has a separate PLL for the I2S block. + Set this true and provide configuration parameters in + board.h to use this PLL. -if STM32_DAC4 +config STM32_CCMEXCLUDE + bool "Exclude CCM SRAM from the heap" + default ARCH_DMA || LIBC_ARCH_ELF + depends on STM32_HAVE_CCM + ---help--- + Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA + and (2) it appears to be impossible to execute ELF modules from CCM + RAM. -config STM32_DAC4CH1 - bool "DAC4CH1 Internal" +config STM32_CCM_PROCFS + bool "CCM PROCFS support" default n + depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER + ---help--- + Select to build in support for /proc/ccm. Reading from /proc/ccm + will provide statistics about CCM memory use similar to what you + would get from mallinfo() for the user heap. -config STM32_DAC4CH2 - bool "DAC4CH2 Internal" - default n +menu "Timer Configuration" + depends on STM32_TIM -endif #STM32_DAC4 +config STM32_HAVE_ADC4_TIMER + bool -config STM32_DCMI - bool "DCMI" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX +config STM32_HAVE_ADC5_TIMER + bool -config STM32_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32_HAVE_ETHMAC - select NETDEVICES - select ARCH_HAVE_PHY +if STM32_TIM9_CAP -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN +config STM32_TIM9_CLOCK + int "TIM9 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. -config STM32_FDCAN2 - bool "FDCAN2" - default n - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN +endif # STM32_TIM9_CAP -config STM32_FDCAN3 - bool "FDCAN3" - default n - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN +if STM32_TIM10_CAP -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC +config STM32_TIM10_CLOCK + int "TIM10 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. -config STM32_FMC - bool "FMC" - default n - depends on STM32_HAVE_FMC +endif # STM32_TIM10_CAP -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - default n - depends on STM32_HAVE_FMAC +if STM32_TIM11_CAP -config STM32_HASH - bool "HASH" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX +config STM32_TIM11_CLOCK + int "TIM11 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. -config STM32_HRTIM - bool - default n +endif # STM32_TIM11_CAP -config STM32_HRTIM1 - bool "HRTIM1" - default n - depends on STM32_HAVE_HRTIM1 - select STM32_HRTIM +endmenu # Timer Configuration -if STM32_HRTIM1 +menu "HRTIM Configuration" + depends on STM32_HRTIM -config STM32_HRTIM_MASTER - bool "HRTIM MASTER" +config STM32_HRTIM_DISABLE_CHARDRV + bool "HRTIM Disable Character Driver" default n ---help--- - Enable HRTIM Master Timer + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. -config STM32_HRTIM_TIMA - bool "HRTIM TIMA" +config STM32_HRTIM_NO_ENABLE_TIMERS + bool "Do not enable HRTIM timers at startup" default n ---help--- - Enable HRTIM Timer A + Do not enable HRTIM timers at startup -config STM32_HRTIM_TIMB - bool "HRTIM TIMB" +menuconfig STM32_HRTIM_ADC + bool "HRTIM ADC Triggering" default n ---help--- - Enable HRTIM Timer B + Enable HRTIM ADC Triggering support. -config STM32_HRTIM_TIMC - bool "HRTIM TIMC" - default n - ---help--- - Enable HRTIM Timer C +if STM32_HRTIM_ADC -config STM32_HRTIM_TIMD - bool "HRTIM TIMD" +config STM32_HRTIM_ADC1_TRG1 + bool "HRTIM ADC1 Trigger 1" default n - ---help--- - Enable HRTIM Timer D -config STM32_HRTIM_TIME - bool "HRTIM TIME" +config STM32_HRTIM_ADC1_TRG2 + bool "HRTIM ADC1 Trigger 2" default n - ---help--- - Enable HRTIM Timer E -endif # STM32_HRTIM - -config STM32_I2C1 - bool "I2C1" +config STM32_HRTIM_ADC1_TRG3 + bool "HRTIM ADC1 Trigger 3" default n - select STM32_I2C -config STM32_I2C2 - bool "I2C2" +config STM32_HRTIM_ADC1_TRG4 + bool "HRTIM ADC1 Trigger 4" default n - depends on STM32_HAVE_I2C2 - select STM32_I2C -config STM32_I2C3 - bool "I2C3" +config STM32_HRTIM_ADC2_TRG1 + bool "HRTIM ADC2 Trigger 1" default n - depends on STM32_HAVE_I2C3 - select STM32_I2C -config STM32_I2C1_SLAVE - bool "I2C1 Slave" +config STM32_HRTIM_ADC2_TRG2 + bool "HRTIM ADC2 Trigger 2" default n - depends on !STM32_I2C1 && I2C_SLAVE - select STM32_I2C_SLAVE -config STM32_I2C2_SLAVE - bool "I2C2 Slave" +config STM32_HRTIM_ADC2_TRG3 + bool "HRTIM ADC2 Trigger 3" default n - depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE - select STM32_I2C_SLAVE -config STM32_I2C3_SLAVE - bool "I2C3 Slave" +config STM32_HRTIM_ADC2_TRG4 + bool "HRTIM ADC2 Trigger 4" default n - depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE - select STM32_I2C_SLAVE -config STM32_LPTIM1 - bool "LPTIM1" +endif # STM32_HRTIM_ADC + +config STM32_HRTIM_DAC + bool "HRTIM DAC Triggering" default n - depends on STM32_HAVE_LPTIM1 + ---help--- + Enable HRTIM DAC Triggering support. -config STM32_LPUART1 - bool "LPUART1" +config STM32_HRTIM_PWM + bool "HRTIM PWM Outputs" default n - depends on STM32_HAVE_LPUART1 - select STM32_USART + ---help--- + Enable HRTIM PWM Outputs support. -config STM32_LTDC - bool "LTDC" +config STM32_HRTIM_CAP + bool "HRTIM Capture" default n - select FB - depends on STM32_HAVE_LTDC ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. + Enable HRTIM Capture support. -config STM32_DMA2D - bool "DMA2D" +config STM32_HRTIM_INTERRUPTS + bool "HRTIM Interrupts" default n - select FB - select FB_OVERLAY - depends on STM32_STM32F429 ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. + Enable HRTIM Interrupts support. -config STM32_OPAMP1 - bool "OPAMP1" +config STM32_HRTIM_BURST + bool "HRTIM Burst Mode" + depends on STM32_HRTIM_PWM default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP1 + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. -config STM32_OPAMP2 - bool "OPAMP2" +config STM32_HRTIM_DEADTIME + bool "HRTIM Dead-time" + depends on STM32_HRTIM_PWM default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP2 + ---help--- + Enable HRTIM Deadtime support for PWM outputs. -config STM32_OPAMP3 - bool "OPAMP3" +config STM32_HRTIM_PUSHPULL + bool "HRTIM Push-Pull Mode" + depends on STM32_HRTIM_PWM default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP3 + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. -config STM32_OPAMP4 - bool "OPAMP4" +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP4 + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. -config STM32_RTC - bool "RTC" +config STM32_HRTIM_DMA + bool "HRTIM DMA" default n - select RTC -config STM32_OTGFS - bool "OTG FS" +config STM32_HRTIM_DMABURST + bool "HRTIM DMA Burst" default n - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if STM32_USBHOST -config STM32_OTGHS - bool "OTG HS" +config STM32_HRTIM_AUTODELAY + bool "HRTIM Autodelay" + depends on STM32_HRTIM_PWM default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - select USBHOST_HAVE_ASYNCH if STM32_USBHOST -config STM32_PWR - bool "PWR" +menuconfig STM32_HRTIM_EVENTS + bool "HRTIM Events Configuration" default n + ---help--- + Enable HRTIM Events support. + +if STM32_HRTIM_EVENTS -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI +config STM32_HRTIM_EEV1 + bool "HRTIM EEV1" default n -config STM32_RNG - bool "RNG" +config STM32_HRTIM_EEV2 + bool "HRTIM EEV2" default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG -# REVISIT: There are some lower-end STM32F401 parts without SDIO too. Others? +config STM32_HRTIM_EEV3 + bool "HRTIM EEV3" + default n -config STM32_SDIO - bool "SDIO" +config STM32_HRTIM_EEV4 + bool "HRTIM EEV4" default n - depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT -config STM32_SPI1 - bool "SPI1" +config STM32_HRTIM_EEV5 + bool "HRTIM EEV5" default n - select SPI - select STM32_SPI -config STM32_SPI2 - bool "SPI2" +config STM32_HRTIM_EEV6 + bool "HRTIM EEV6" default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI -config STM32_SPI3 - bool "SPI3" +config STM32_HRTIM_EEV7 + bool "HRTIM EEV7" default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI -config STM32_I2S3 - bool "I2S3" +config STM32_HRTIM_EEV8 + bool "HRTIM EEV8" default n - depends on STM32_HAVE_I2S3 - select I2S - select STM32_I2S -config STM32_SPI4 - bool "SPI4" +config STM32_HRTIM_EEV9 + bool "HRTIM EEV9" default n - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI -config STM32_SPI5 - bool "SPI5" +config STM32_HRTIM_EEV10 + bool "HRTIM EEV10" default n - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI -config STM32_SPI6 - bool "SPI6" +endif # STM32_HRTIM_EVENTS + +menuconfig STM32_HRTIM_FAULTS + bool "HRTIM Faults Configuration" default n - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI + ---help--- + Enable HRTIM Faults support. -config STM32_SYSCFG - bool "SYSCFG" - default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G4XXX || STM32_CONNECTIVITYLINE +if STM32_HRTIM_FAULTS -config STM32_TIM1 - bool "TIM1" +config STM32_HRTIM_FAULT1 + bool "HRTIM Fault 1" default n - depends on STM32_HAVE_TIM1 - select STM32_TIM -config STM32_TIM2 - bool "TIM2" +config STM32_HRTIM_FAULT2 + bool "HRTIM Fault 2" default n - select STM32_TIM -config STM32_TIM3 - bool "TIM3" +config STM32_HRTIM_FAULT3 + bool "HRTIM Fault 3" default n - depends on STM32_HAVE_TIM3 - select STM32_TIM -config STM32_TIM4 - bool "TIM4" +config STM32_HRTIM_FAULT4 + bool "HRTIM Fault 4" default n - depends on STM32_HAVE_TIM4 - select STM32_TIM -config STM32_TIM5 - bool "TIM5" +endif # STM32_HRTIM_FAULTS + +config STM32_HRTIM_CLK_FROM_PLL + bool "HRTIM Clock from PLL" default n - depends on STM32_HAVE_TIM5 - select STM32_TIM + depends on STM32_HAVE_HRTIM1_PLLCLK + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. + +menu "HRTIM Master Configuration" + depends on STM32_HRTIM_MASTER -config STM32_TIM6 - bool "TIM6" +config STM32_HRTIM_MASTER_DAC + bool "HRTIM Master DAC Triggering" default n - depends on STM32_HAVE_TIM6 - select STM32_TIM + depends on STM32_HRTIM_DAC -config STM32_TIM7 - bool "TIM7" +config STM32_HRTIM_MASTER_DMA + bool "HRTIM MASTER DMA" default n - depends on STM32_HAVE_TIM7 - select STM32_TIM + depends on STM32_HRTIM_DMA -config STM32_TIM8 - bool "TIM8" +config STM32_HRTIM_MASTER_IRQ + bool "HRTIM MASTER Interrupts" default n - depends on STM32_HAVE_TIM8 - select STM32_TIM + depends on STM32_HRTIM_INTERRUPTS + +endmenu # "HRTIM Master Configuration" -config STM32_TIM9 - bool "TIM9" +menu "HRTIM Timer A Configuration" + depends on STM32_HRTIM_TIMA + +config STM32_HRTIM_TIMA_CAP + bool "HRTIM TIMA Capture" default n - depends on STM32_HAVE_TIM9 - select STM32_TIM + depends on STM32_HRTIM_CAPTURE -config STM32_TIM10 - bool "TIM10" +config STM32_HRTIM_TIMA_DAC + bool "HRTIM TIMA DAC Triggering" default n - depends on STM32_HAVE_TIM10 - select STM32_TIM + depends on STM32_HRTIM_DAC -config STM32_TIM11 - bool "TIM11" +config STM32_HRTIM_TIMA_DMA + bool "HRTIM TIMA DMA" default n - depends on STM32_HAVE_TIM11 - select STM32_TIM + depends on STM32_HRTIM_DMA -config STM32_TIM12 - bool "TIM12" +config STM32_HRTIM_TIMA_IRQ + bool "HRTIM TIMA Interrupts" default n - depends on STM32_HAVE_TIM12 - select STM32_TIM + depends on STM32_HRTIM_INTERRUPTS -config STM32_TIM13 - bool "TIM13" +config STM32_HRTIM_TIMA_PWM + bool "HRTIM TIMA PWM Outputs" default n - depends on STM32_HAVE_TIM13 - select STM32_TIM + depends on STM32_HRTIM_PWM -config STM32_TIM14 - bool "TIM14" +config STM32_HRTIM_TIMA_PWM_CH1 + bool "HRTIM TIMA PWM Output 1" default n - depends on STM32_HAVE_TIM14 - select STM32_TIM + depends on STM32_HRTIM_TIMA_PWM -config STM32_TIM15 - bool "TIM15" +config STM32_HRTIM_TIMA_PWM_CH2 + bool "HRTIM TIMA PWM Output 2" default n - depends on STM32_HAVE_TIM15 - select STM32_TIM + depends on STM32_HRTIM_TIMA_PWM -config STM32_TIM16 - bool "TIM16" +config STM32_HRTIM_TIMA_BURST + bool "HRTIM TIMA Burst" default n - depends on STM32_HAVE_TIM16 - select STM32_TIM + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) -config STM32_TIM17 - bool "TIM17" +config STM32_HRTIM_TIMA_BURST_CH1 + bool "HRTIM TIMA Output 1 Burst Mode" default n - depends on STM32_HAVE_TIM17 - select STM32_TIM + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) -config STM32_TSC - bool "TSC" +config STM32_HRTIM_TIMA_BURST_CH2 + bool "HRTIM TIMA Output 2 Burst Mode" default n - depends on STM32_HAVE_TSC + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) -config STM32_USART1 - bool "USART1" +config STM32_HRTIM_TIMA_CHOP + bool "HRTIM TIMA PWM Chopper" default n - select STM32_USART + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) -config STM32_USART2 - bool "USART2" +config STM32_HRTIM_TIMA_DT + bool "HRTIM TIMA PWM Dead-time" default n - select STM32_USART + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) -config STM32_USART3 - bool "USART3" +config STM32_HRTIM_TIMA_PSHPLL + bool "HRTIM TIMA PWM Push-pull mode" default n - depends on STM32_HAVE_USART3 - select STM32_USART + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) + +endmenu # "HRTIM Timer A Configuration" -config STM32_UART4 - bool "UART4" +menu "HRTIM Timer B Configuration" + depends on STM32_HRTIM_TIMB + +config STM32_HRTIM_TIMB_CAP + bool "HRTIM TIMB Capture" default n - depends on STM32_HAVE_UART4 - select STM32_USART + depends on STM32_HRTIM_CAPTURE -config STM32_UART5 - bool "UART5" +config STM32_HRTIM_TIMB_DAC + bool "HRTIM TIMB DAC Triggering" default n - depends on STM32_HAVE_UART5 - select STM32_USART + depends on STM32_HRTIM_DAC -config STM32_USART6 - bool "USART6" +config STM32_HRTIM_TIMB_DMA + bool "HRTIM TIMB DMA" default n - depends on STM32_HAVE_USART6 - select STM32_USART + depends on STM32_HRTIM_DMA -config STM32_UART7 - bool "UART7" +config STM32_HRTIM_TIMB_IRQ + bool "HRTIM TIMB Interrupts" default n - depends on STM32_HAVE_UART7 - select STM32_USART + depends on STM32_HRTIM_INTERRUPTS -config STM32_UART8 - bool "UART8" +config STM32_HRTIM_TIMB_PWM + bool "HRTIM TIMB PWM Outputs" default n - depends on STM32_HAVE_UART8 - select STM32_USART + depends on STM32_HRTIM_PWM -config STM32_USB - bool "USB Device" +config STM32_HRTIM_TIMB_PWM_CH1 + bool "HRTIM TIMB PWM Output 1" default n - depends on STM32_HAVE_USBDEV - select USBDEV + depends on STM32_HRTIM_TIMB_PWM -config STM32_USBFS - bool "USB Full Speed Device" +config STM32_HRTIM_TIMB_PWM_CH2 + bool "HRTIM TIMB PWM Output 2" default n - depends on STM32_HAVE_USBFS - select USBDEV + depends on STM32_HRTIM_TIMB_PWM -config STM32_UCPD - bool "UCPD (USB Type C Power Delivery)" +config STM32_HRTIM_TIMB_BURST + bool "HRTIM TIMB Burst" default n - depends on STM32_HAVE_UCPD - select USBDEV + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) -config STM32_LCD - bool "Segment LCD" +config STM32_HRTIM_TIMB_BURST_CH1 + bool "HRTIM TIMB Output 1 Burst Mode" default n - depends on STM32_STM32L15XX + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) -# -# STM32 LCD Clock Selection -# - -if STM32_LCD +config STM32_HRTIM_TIMB_BURST_CH2 + bool "HRTIM TIMB Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) -choice - prompt "Segment LCD Clock Source" - default LCD_LSECLOCK +config STM32_HRTIM_TIMB_CHOP + bool "HRTIM TIMB PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) -config LCD_LSICLOCK - bool "Internal Low Speed Clock" +config STM32_HRTIM_TIMB_DT + bool "HRTIM TIMB PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) -config LCD_LSECLOCK - bool "External Low Speed Clock" +config STM32_HRTIM_TIMB_PSHPLL + bool "HRTIM TIMB PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) -config LCD_HSECLOCK - bool "External High Speed Clock" +endmenu # "HRTIM Timer B Configuration" -endchoice -endif # STM32_LCD +menu "HRTIM Timer C Configuration" + depends on STM32_HRTIM_TIMC -config STM32_IWDG - bool "IWDG" +config STM32_HRTIM_TIMC_CAP + bool "HRTIM TIMC Capture" default n - select WATCHDOG + depends on STM32_HRTIM_CAPTURE -config STM32_WWDG - bool "WWDG" +config STM32_HRTIM_TIMC_DAC + bool "HRTIM TIMC DAC Triggering" default n - select WATCHDOG + depends on STM32_HRTIM_DAC -endmenu +config STM32_HRTIM_TIMC_DMA + bool "HRTIM TIMC DMA" + default n + depends on STM32_HRTIM_DMA -config STM32_ADC - bool +config STM32_HRTIM_TIMC_IRQ + bool "HRTIM TIMC Interrupts" default n + depends on STM32_HRTIM_INTERRUPTS -config STM32_SDADC - bool +config STM32_HRTIM_TIMC_PWM + bool "HRTIM TIMC PWM Outputs" default n + depends on STM32_HRTIM_PWM -config STM32_DAC - bool +config STM32_HRTIM_TIMC_PWM_CH1 + bool "HRTIM TIMC PWM Output 1" default n + depends on STM32_HRTIM_TIMC_PWM -config STM32_DMA - bool +config STM32_HRTIM_TIMC_PWM_CH2 + bool "HRTIM TIMC PWM Output 2" default n + depends on STM32_HRTIM_TIMC_PWM -config STM32_DMAMUX - bool +config STM32_HRTIM_TIMC_BURST + bool "HRTIM TIMC Burst" default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) -config STM32_SPI - bool +config STM32_HRTIM_TIMC_BURST_CH1 + bool "HRTIM TIMC Output 1 Burst Mode" default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) -config STM32_SPI_DMA - bool +config STM32_HRTIM_TIMC_BURST_CH2 + bool "HRTIM TIMC Output 2 Burst Mode" default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) -config STM32_I2S - bool +config STM32_HRTIM_TIMC_CHOP + bool "HRTIM TIMC PWM Chopper" default n - select STM32_SPI_DMA + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) -config STM32_I2C - bool +config STM32_HRTIM_TIMC_DT + bool "HRTIM TIMC PWM Dead-time" default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) -config STM32_I2C_SLAVE - bool +config STM32_HRTIM_TIMC_PSHPLL + bool "HRTIM TIMC PWM Push-pull mode" default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) -config STM32_CAN - bool +endmenu # "HRTIM Timer C Configuration" + +menu "HRTIM Timer D Configuration" + depends on STM32_HRTIM_TIMD + +config STM32_HRTIM_TIMD_CAP + bool "HRTIM TIMD Capture" default n + depends on STM32_HRTIM_CAPTURE -config STM32_FDCAN - bool +config STM32_HRTIM_TIMD_DAC + bool "HRTIM TIMD DAC Triggering" default n + depends on STM32_HRTIM_DAC -config STM32_TIM - bool +config STM32_HRTIM_TIMD_DMA + bool "HRTIM TIMD DMA" default n + depends on STM32_HRTIM_DMA -config STM32_PWM - bool +config STM32_HRTIM_TIMD_IRQ + bool "HRTIM TIMD Interrupts" default n + depends on STM32_HRTIM_INTERRUPTS -config STM32_CAP - bool +config STM32_HRTIM_TIMD_PWM + bool "HRTIM TIMD PWM Outputs" default n + depends on STM32_HRTIM_PWM -config STM32_COMP - bool +config STM32_HRTIM_TIMD_PWM_CH1 + bool "HRTIM TIMD PWM Output 1" default n - depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX + depends on STM32_HRTIM_TIMD_PWM -config STM32_OPAMP - bool +config STM32_HRTIM_TIMD_PWM_CH2 + bool "HRTIM TIMD PWM Output 2" default n + depends on STM32_HRTIM_TIMD_PWM -config STM32_NOEXT_VECTORS - bool "Disable the ARMv7-M EXT vectors" +config STM32_HRTIM_TIMD_BURST + bool "HRTIM TIMD Burst" default n - ---help--- - Sometimes you may not need any Vector support beyond SysTick - and wish to save memory. This applies only to ARMv7-M architectures. + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" +config STM32_HRTIM_TIMD_BURST_CH1 + bool "HRTIM TIMD Output 1 Burst Mode" default n - depends on STM32_HAVE_IOCOMPENSATION - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. +config STM32_HRTIM_TIMD_BURST_CH2 + bool "HRTIM TIMD Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) -menu "Alternate Pin Mapping" - depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE +config STM32_HRTIM_TIMD_CHOP + bool "HRTIM TIMD PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) -choice - prompt "CAN1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_CAN1 - default STM32_CAN1_NO_REMAP +config STM32_HRTIM_TIMD_DT + bool "HRTIM TIMD PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) -config STM32_CAN1_NO_REMAP - bool "No pin remapping" +config STM32_HRTIM_TIMD_PSHPLL + bool "HRTIM TIMD PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) -config STM32_CAN1_REMAP1 - bool "CAN1 alternate pin remapping #1" +endmenu # "HRTIM Timer D Configuration" -config STM32_CAN1_REMAP2 - bool "CAN1 alternate pin remapping #2" +menu "HRTIM Timer E Configuration" + depends on STM32_HRTIM_TIME -endchoice +config STM32_HRTIM_TIME_CAP + bool "HRTIM TIME Capture" + default n + depends on STM32_HRTIM_CAPTURE -config STM32_CAN2_REMAP - bool "CAN2 Alternate Pin Mapping" +config STM32_HRTIM_TIME_DAC + bool "HRTIM TIME DAC Triggering" default n - depends on STM32_CONNECTIVITYLINE && STM32_CAN2 + depends on STM32_HRTIM_DAC -config STM32_CEC_REMAP - bool "CEC Alternate Pin Mapping" +config STM32_HRTIM_TIME_DMA + bool "HRTIM TIME DMA" default n - depends on STM32_STM32F10XX && STM32_CEC + depends on STM32_HRTIM_DMA -config STM32_ETH_REMAP - bool "Ethernet Alternate Pin Mapping" +config STM32_HRTIM_TIME_IRQ + bool "HRTIM TIME Interrupts" default n - depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC + depends on STM32_HRTIM_INTERRUPTS -config STM32_I2C1_REMAP - bool "I2C1 Alternate Pin Mapping" +config STM32_HRTIM_TIME_PWM + bool "HRTIM TIME PWM Outputs" default n - depends on STM32_STM32F10XX && STM32_I2C1 + depends on STM32_HRTIM_PWM -config STM32_SPI1_REMAP - bool "SPI1 Alternate Pin Mapping" +config STM32_HRTIM_TIME_PWM_CH1 + bool "HRTIM TIME PWM Output 1" default n - depends on STM32_STM32F10XX && STM32_SPI1 + depends on STM32_HRTIM_TIME_PWM -config STM32_SPI3_REMAP - bool "SPI3 Alternate Pin Mapping" +config STM32_HRTIM_TIME_PWM_CH2 + bool "HRTIM TIME PWM Output 2" default n - depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE + depends on STM32_HRTIM_TIME_PWM -config STM32_I2S3_REMAP - bool "I2S3 Alternate Pin Mapping" +config STM32_HRTIM_TIME_BURST + bool "HRTIM TIME Burst" default n - depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) -choice - prompt "TIM1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM1 - default STM32_TIM1_NO_REMAP +config STM32_HRTIM_TIME_BURST_CH1 + bool "HRTIM TIME Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) -config STM32_TIM1_NO_REMAP - bool "No pin remapping" +config STM32_HRTIM_TIME_BURST_CH2 + bool "HRTIM TIME Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) -config STM32_TIM1_FULL_REMAP - bool "Full pin remapping" +config STM32_HRTIM_TIME_CHOP + bool "HRTIM TIME PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) -config STM32_TIM1_PARTIAL_REMAP - bool "Partial pin remapping" +config STM32_HRTIM_TIME_DT + bool "HRTIM TIME PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) -endchoice +config STM32_HRTIM_TIME_PSHPLL + bool "HRTIM TIME PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) -choice - prompt "TIM2 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM2 - default STM32_TIM2_NO_REMAP +endmenu # "HRTIM Timer E Configuration" -config STM32_TIM2_NO_REMAP - bool "No pin remapping" +endmenu # "HRTIM Configuration" -config STM32_TIM2_FULL_REMAP - bool "Full pin remapping" +menu "ADC Configuration" + depends on STM32_ADC -config STM32_TIM2_PARTIAL_REMAP_1 - bool "Partial pin remapping #1" - -config STM32_TIM2_PARTIAL_REMAP_2 - bool "Partial pin remapping #2" - -endchoice - -choice - prompt "TIM3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM3 - default STM32_TIM3_NO_REMAP - -config STM32_TIM3_NO_REMAP - bool "No pin remapping" - -config STM32_TIM3_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -config STM32_TIM4_REMAP - bool "TIM4 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM4 - -config STM32_TIM9_REMAP - bool "TIM9 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM9 - -config STM32_TIM10_REMAP - bool "TIM10 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM10 - -config STM32_TIM11_REMAP - bool "TIM11 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM11 - -config STM32_TIM12_REMAP - bool "TIM12 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM12 - -config STM32_TIM13_REMAP - bool "TIM13 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM13 - -config STM32_TIM14_REMAP - bool "TIM14 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM14 - -config STM32_TIM15_REMAP - bool "TIM15 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM15 - -config STM32_TIM16_REMAP - bool "TIM16 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM16 - -config STM32_TIM17_REMAP - bool "TIM17 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM17 - -config STM32_USART1_REMAP - bool "USART1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART1 - -config STM32_USART2_REMAP - bool "USART2 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART2 - -choice - prompt "USART3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_USART3 - default STM32_USART3_NO_REMAP - -config STM32_USART3_NO_REMAP - bool "No pin remapping" - -config STM32_USART3_FULL_REMAP - bool "Full pin remapping" - -config STM32_USART3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -endmenu - -config STM32_FLASH_ICACHE - bool "Enable FLASH Instruction Cache" - default y - depends on STM32_HAVE_FLASH_ICACHE - ---help--- - Enable the FLASH instruction cache. - -config STM32_FLASH_DCACHE - bool "Enable FLASH Data Cache" - default y - depends on STM32_HAVE_FLASH_DCACHE - ---help--- - Enable the FLASH data cache. - -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config STM32_FORCEPOWER - bool "Force power" - default n - ---help--- - Timer and I2C devices may need to the following to force power to be applied - unconditionally at power up. (Otherwise, the device is powered when it is - initialized). - -config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_SAIPLL - bool "SAIPLL" - default n - depends on STM32_HAVE_SAIPLL - ---help--- - The STM32F446 has a separate PLL for the SAI block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_I2SPLL - bool "I2SPLL" - default n - depends on STM32_HAVE_I2SPLL - ---help--- - The STM32F446 has a separate PLL for the I2S block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_CCMEXCLUDE - bool "Exclude CCM SRAM from the heap" - default ARCH_DMA || LIBC_ARCH_ELF - depends on STM32_HAVE_CCM - ---help--- - Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA - and (2) it appears to be impossible to execute ELF modules from CCM - RAM. - -config STM32_CCM_PROCFS - bool "CCM PROCFS support" - default n - depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER - ---help--- - Select to build in support for /proc/ccm. Reading from /proc/ccm - will provide statistics about CCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - default n - depends on STM32_FSMC || STM32_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - -menu "Timer Configuration" - depends on STM32_TIM - -if SCHED_TICKLESS - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM1_CHANNEL6 - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM1_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM1_CHANNEL = 1 - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 1 - -if STM32_TIM1_CHANNEL = 2 - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 2 - -if STM32_TIM1_CHANNEL = 3 - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 3 - -if STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM2_CHANNEL = 1 - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL = 1 - -if STM32_TIM2_CHANNEL = 2 - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL = 2 - -if STM32_TIM2_CHANNEL = 3 - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL = 3 - -if STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM3_CHANNEL = 1 - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL = 1 - -if STM32_TIM3_CHANNEL = 2 - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL = 2 - -if STM32_TIM3_CHANNEL = 3 - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL = 3 - -if STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32_TIM4 - select STM32_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM4_PWM - -config STM32_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM4_CHANNEL4 - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM4_CHANNEL = 1 - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL = 1 - -if STM32_TIM4_CHANNEL = 2 - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL = 2 - -if STM32_TIM4_CHANNEL = 3 - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL = 3 - -if STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM4_PWM - -config STM32_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32_TIM5 - select STM32_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM5_PWM - -config STM32_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM5_CHANNEL4 - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM5_CHANNEL = 1 - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL = 1 - -if STM32_TIM5_CHANNEL = 2 - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL = 2 - -if STM32_TIM5_CHANNEL = 3 - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL = 3 - -if STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM5_PWM - -config STM32_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32_TIM8 - select STM32_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM8_PWM - -config STM32_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM8_CHANNEL6 - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM8_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM8_CHANNEL = 1 - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 1 - -if STM32_TIM8_CHANNEL = 2 - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 2 - -if STM32_TIM8_CHANNEL = 3 - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 3 - -if STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM8_PWM - -config STM32_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32_TIM9 - select STM32_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM9_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM9_CHANNEL2 - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM9_CHANNEL = 1 - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL = 1 - -if STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM9_PWM - -config STM32_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32_TIM10 - select STM32_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM10_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM10_CHANNEL1 - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM10_PWM - -config STM32_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32_TIM11 - select STM32_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM11_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM11_CHANNEL1 - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM11_PWM - -config STM32_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32_TIM12 - select STM32_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM12_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM12_CHANNEL2 - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM12_CHANNEL = 1 - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL = 1 - -if STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM12_PWM - -config STM32_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32_TIM13 - select STM32_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM13_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM13_CHANNEL1 - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM13_PWM - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM15_CHANNEL = 1 - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 1 - -if STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32_TIM8 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32_TIM4 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32_TIM5 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32_TIM8 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32_TIM9 && STM32_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32_TIM10 && STM32_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32_TIM11 && STM32_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32_TIM12 && STM32_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32_TIM13 && STM32_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32_TIM14 && STM32_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - - -config STM32_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32_TIM1 - select STM32_CAP - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM1_CAP - -config STM32_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM1_CAP - -config STM32_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32_TIM2 - select STM32_CAP - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM2_CAP - -config STM32_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM2_CAP - -config STM32_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32_TIM3 - select STM32_CAP - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM3_CAP - -config STM32_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM3_CAP - -config STM32_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32_TIM4 - select STM32_CAP - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM4_CAP - -config STM32_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM4_CAP - -config STM32_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32_TIM5 - select STM32_CAP - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM5_CAP - -config STM32_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM5_CAP - -config STM32_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32_TIM8 - select STM32_CAP - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM8_CAP - -config STM32_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM8_CAP - -config STM32_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32_TIM9 - select STM32_CAP - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM9_CAP - -config STM32_TIM9_CHANNEL - int "TIM9 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM9 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM9_CLOCK - int "TIM9 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM9_CAP - -config STM32_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32_TIM10 - select STM32_CAP - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM10_CAP - -config STM32_TIM10_CHANNEL - int "TIM10 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM10 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM10_CLOCK - int "TIM10 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM10_CAP - -config STM32_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32_TIM11 - select STM32_CAP - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM11_CAP - -config STM32_TIM11_CHANNEL - int "TIM11 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM11 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM11_CLOCK - int "TIM11 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM11_CAP - -config STM32_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32_TIM12 - select STM32_CAP - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM12_CAP - -config STM32_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM12 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM12_CAP - -config STM32_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32_TIM13 - select STM32_CAP - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM13_CAP - -config STM32_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM13 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM13_CAP - -config STM32_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32_TIM14 - select STM32_CAP - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM14_CAP - -config STM32_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM14 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM14_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "HRTIM Configuration" - depends on STM32_HRTIM - -config STM32_HRTIM_DISABLE_CHARDRV - bool "HRTIM Disable Character Driver" - default n - ---help--- - In most cases we do not need HRTIM Character Driver, so we can disable it - and save some memory. - -config STM32_HRTIM_NO_ENABLE_TIMERS - bool "Do not enable HRTIM timers at startup" - default n - ---help--- - Do not enable HRTIM timers at startup - -menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Triggering" - default n - ---help--- - Enable HRTIM ADC Triggering support. - -if STM32_HRTIM_ADC - -config STM32_HRTIM_ADC1_TRG1 - bool "HRTIM ADC1 Trigger 1" - default n - -config STM32_HRTIM_ADC1_TRG2 - bool "HRTIM ADC1 Trigger 2" - default n - -config STM32_HRTIM_ADC1_TRG3 - bool "HRTIM ADC1 Trigger 3" - default n - -config STM32_HRTIM_ADC1_TRG4 - bool "HRTIM ADC1 Trigger 4" - default n - -config STM32_HRTIM_ADC2_TRG1 - bool "HRTIM ADC2 Trigger 1" - default n - -config STM32_HRTIM_ADC2_TRG2 - bool "HRTIM ADC2 Trigger 2" - default n - -config STM32_HRTIM_ADC2_TRG3 - bool "HRTIM ADC2 Trigger 3" - default n - -config STM32_HRTIM_ADC2_TRG4 - bool "HRTIM ADC2 Trigger 4" - default n - -endif # STM32_HRTIM_ADC - -config STM32_HRTIM_DAC - bool "HRTIM DAC Triggering" - default n - ---help--- - Enable HRTIM DAC Triggering support. - -config STM32_HRTIM_PWM - bool "HRTIM PWM Outputs" - default n - ---help--- - Enable HRTIM PWM Outputs support. - -config STM32_HRTIM_CAP - bool "HRTIM Capture" - default n - ---help--- - Enable HRTIM Capture support. - -config STM32_HRTIM_INTERRUPTS - bool "HRTIM Interrupts" - default n - ---help--- - Enable HRTIM Interrupts support. - -config STM32_HRTIM_BURST - bool "HRTIM Burst Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Burst Mode support for PWM outputs. - -config STM32_HRTIM_DEADTIME - bool "HRTIM Dead-time" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Deadtime support for PWM outputs. - -config STM32_HRTIM_PUSHPULL - bool "HRTIM Push-Pull Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Push-Pull Mode support for PWM outputs. - -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Chopper Mode for PWM outputs. - -config STM32_HRTIM_DMA - bool "HRTIM DMA" - default n - -config STM32_HRTIM_DMABURST - bool "HRTIM DMA Burst" - default n - -config STM32_HRTIM_AUTODELAY - bool "HRTIM Autodelay" - depends on STM32_HRTIM_PWM - default n - -menuconfig STM32_HRTIM_EVENTS - bool "HRTIM Events Configuration" - default n - ---help--- - Enable HRTIM Events support. - -if STM32_HRTIM_EVENTS - -config STM32_HRTIM_EEV1 - bool "HRTIM EEV1" - default n - -config STM32_HRTIM_EEV2 - bool "HRTIM EEV2" - default n - -config STM32_HRTIM_EEV3 - bool "HRTIM EEV3" - default n - -config STM32_HRTIM_EEV4 - bool "HRTIM EEV4" - default n - -config STM32_HRTIM_EEV5 - bool "HRTIM EEV5" - default n - -config STM32_HRTIM_EEV6 - bool "HRTIM EEV6" - default n - -config STM32_HRTIM_EEV7 - bool "HRTIM EEV7" - default n - -config STM32_HRTIM_EEV8 - bool "HRTIM EEV8" - default n - -config STM32_HRTIM_EEV9 - bool "HRTIM EEV9" - default n - -config STM32_HRTIM_EEV10 - bool "HRTIM EEV10" - default n - -endif # STM32_HRTIM_EVENTS - -menuconfig STM32_HRTIM_FAULTS - bool "HRTIM Faults Configuration" - default n - ---help--- - Enable HRTIM Faults support. - -if STM32_HRTIM_FAULTS - -config STM32_HRTIM_FAULT1 - bool "HRTIM Fault 1" - default n - -config STM32_HRTIM_FAULT2 - bool "HRTIM Fault 2" - default n - -config STM32_HRTIM_FAULT3 - bool "HRTIM Fault 3" - default n - -config STM32_HRTIM_FAULT4 - bool "HRTIM Fault 4" - default n - -endif # STM32_HRTIM_FAULTS - -config STM32_HRTIM_CLK_FROM_PLL - bool "HRTIM Clock from PLL" - default n - depends on STM32_HAVE_HRTIM1_PLLCLK - ---help--- - Set PLL as the clock source for HRTIM. - This configuration requires the following conditions: - 1) system clock is PLL, - 2) SYSCLK and PCLK2 ratio must be 1 o 2. - -menu "HRTIM Master Configuration" - depends on STM32_HRTIM_MASTER - -config STM32_HRTIM_MASTER_DAC - bool "HRTIM Master DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_MASTER_DMA - bool "HRTIM MASTER DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_MASTER_IRQ - bool "HRTIM MASTER Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -endmenu # "HRTIM Master Configuration" - -menu "HRTIM Timer A Configuration" - depends on STM32_HRTIM_TIMA - -config STM32_HRTIM_TIMA_CAP - bool "HRTIM TIMA Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMA_DAC - bool "HRTIM TIMA DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMA_DMA - bool "HRTIM TIMA DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMA_IRQ - bool "HRTIM TIMA Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMA_PWM - bool "HRTIM TIMA PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMA_PWM_CH1 - bool "HRTIM TIMA PWM Output 1" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_PWM_CH2 - bool "HRTIM TIMA PWM Output 2" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_BURST - bool "HRTIM TIMA Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_BURST_CH1 - bool "HRTIM TIMA Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) - -config STM32_HRTIM_TIMA_BURST_CH2 - bool "HRTIM TIMA Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) - -config STM32_HRTIM_TIMA_CHOP - bool "HRTIM TIMA PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_DT - bool "HRTIM TIMA PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_PSHPLL - bool "HRTIM TIMA PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) - -endmenu # "HRTIM Timer A Configuration" - -menu "HRTIM Timer B Configuration" - depends on STM32_HRTIM_TIMB - -config STM32_HRTIM_TIMB_CAP - bool "HRTIM TIMB Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMB_DAC - bool "HRTIM TIMB DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMB_DMA - bool "HRTIM TIMB DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMB_IRQ - bool "HRTIM TIMB Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMB_PWM - bool "HRTIM TIMB PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMB_PWM_CH1 - bool "HRTIM TIMB PWM Output 1" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_PWM_CH2 - bool "HRTIM TIMB PWM Output 2" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_BURST - bool "HRTIM TIMB Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_BURST_CH1 - bool "HRTIM TIMB Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) - -config STM32_HRTIM_TIMB_BURST_CH2 - bool "HRTIM TIMB Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) - -config STM32_HRTIM_TIMB_CHOP - bool "HRTIM TIMB PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_DT - bool "HRTIM TIMB PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_PSHPLL - bool "HRTIM TIMB PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) - -endmenu # "HRTIM Timer B Configuration" - -menu "HRTIM Timer C Configuration" - depends on STM32_HRTIM_TIMC - -config STM32_HRTIM_TIMC_CAP - bool "HRTIM TIMC Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMC_DAC - bool "HRTIM TIMC DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMC_DMA - bool "HRTIM TIMC DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMC_IRQ - bool "HRTIM TIMC Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMC_PWM - bool "HRTIM TIMC PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMC_PWM_CH1 - bool "HRTIM TIMC PWM Output 1" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_PWM_CH2 - bool "HRTIM TIMC PWM Output 2" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_BURST - bool "HRTIM TIMC Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_BURST_CH1 - bool "HRTIM TIMC Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) - -config STM32_HRTIM_TIMC_BURST_CH2 - bool "HRTIM TIMC Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) - -config STM32_HRTIM_TIMC_CHOP - bool "HRTIM TIMC PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_DT - bool "HRTIM TIMC PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_PSHPLL - bool "HRTIM TIMC PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) - -endmenu # "HRTIM Timer C Configuration" - -menu "HRTIM Timer D Configuration" - depends on STM32_HRTIM_TIMD - -config STM32_HRTIM_TIMD_CAP - bool "HRTIM TIMD Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMD_DAC - bool "HRTIM TIMD DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMD_DMA - bool "HRTIM TIMD DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMD_IRQ - bool "HRTIM TIMD Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMD_PWM - bool "HRTIM TIMD PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMD_PWM_CH1 - bool "HRTIM TIMD PWM Output 1" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_PWM_CH2 - bool "HRTIM TIMD PWM Output 2" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_BURST - bool "HRTIM TIMD Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_BURST_CH1 - bool "HRTIM TIMD Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - -config STM32_HRTIM_TIMD_BURST_CH2 - bool "HRTIM TIMD Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) - -config STM32_HRTIM_TIMD_CHOP - bool "HRTIM TIMD PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_DT - bool "HRTIM TIMD PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_PSHPLL - bool "HRTIM TIMD PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) - -endmenu # "HRTIM Timer D Configuration" - -menu "HRTIM Timer E Configuration" - depends on STM32_HRTIM_TIME - -config STM32_HRTIM_TIME_CAP - bool "HRTIM TIME Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIME_DAC - bool "HRTIM TIME DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIME_DMA - bool "HRTIM TIME DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIME_IRQ - bool "HRTIM TIME Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIME_PWM - bool "HRTIM TIME PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIME_PWM_CH1 - bool "HRTIM TIME PWM Output 1" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_PWM_CH2 - bool "HRTIM TIME PWM Output 2" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_BURST - bool "HRTIM TIME Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_BURST_CH1 - bool "HRTIM TIME Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) - -config STM32_HRTIM_TIME_BURST_CH2 - bool "HRTIM TIME Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) - -config STM32_HRTIM_TIME_CHOP - bool "HRTIM TIME PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_DT - bool "HRTIM TIME PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_PSHPLL - bool "HRTIM TIME PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) - -endmenu # "HRTIM Timer E Configuration" - -endmenu # "HRTIM Configuration" - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC4_RESOLUTION - int "ADC4 resolution" - depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC5_RESOLUTION - int "ADC5 resolution" - depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32_ADC1 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC1_DMA - default n - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on STM32_ADC2 && STM32_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32_ADC2 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC2_DMA - default n - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on STM32_ADC3 && STM32_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32_ADC3 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC3_DMA - default n - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC4_DMA - bool "ADC4 DMA" - depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC4_DMA_CFG - int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode - -config STM32_ADC4_DMA_BATCH - int "ADC4 DMA number of conversions" - depends on STM32_ADC4 && STM32_ADC4_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_ANIOC_TRIGGER - int "ADC4 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC4 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC5_DMA - bool "ADC5 DMA" - depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC5_DMA_CFG - int "ADC5 DMA configuration" - depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode - -config STM32_ADC5_DMA_BATCH - int "ADC5 DMA number of conversions" - depends on STM32_ADC5 && STM32_ADC5_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32_ADC4_INJECTED_CHAN - int "ADC4 injected channels" - depends on STM32_ADC4 - range 0 4 - default 0 - ---help--- - Support for ADC4 injected channels. - -config STM32_ADC5_INJECTED_CHAN - int "ADC5 injected channels" - depends on STM32_ADC5 - range 0 4 - default 0 - ---help--- - Support for ADC5 injected channels. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32_ADC2 && !STM32_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32_ADC3 && !STM32_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32_ADC4_EXTSEL - bool "ADC4 external trigger for regular group" - depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER - default n - ---help--- - Enable EXTSEL for ADC4. - -config STM32_ADC5_EXTSEL - bool "ADC5 external trigger for regular group" - depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER - default n - ---help--- - Enable EXTSEL for ADC5. - -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -config STM32_ADC4_JEXTSEL - bool "ADC4 external trigger for injected group" - depends on STM32_ADC4 - default n - ---help--- - Enable JEXTSEL for ADC4. - -config STM32_ADC5_JEXTSEL - bool "ADC5 external trigger for injected group" - depends on STM32_ADC5 - default n - ---help--- - Enable JEXTSEL for ADC5. - -endmenu - -menu "COMP Configuration" - depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 - -config STM32_COMP1_OUT - bool "COMP1 GPIO Output" - depends on STM32_COMP1 - default n - ---help--- - Enables COMP1 output. - -config STM32_COMP1_INM - int "COMP1 inverting input assignment" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects COMP1 inverting input pin. - -config STM32_COMP1_INP - int "COMP1 non-inverting input assignment" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 non-inverting input pin. - -config STM32_COMP1_POL - int "COMP1 polarity" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 output polarity. - -config STM32_COMP1_HYST - int "COMP1 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP1. - -config STM32_COMP1_BLANKSEL - int "COMP1 blanking signal select" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP1. - -config STM32_COMP1_LOCK - int "COMP1 COMP_CxCSR register lock" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP2_OUT - bool "COMP2 GPIO Output" - depends on STM32_COMP2 - default n - ---help--- - Enables COMP2 output. - -config STM32_COMP2_INM - int "COMP2 inverting input assignment" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects COMP2 inverting input pin. - -config STM32_COMP2_INP - int "COMP2 non-inverting input assignment" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 non-inverting input pin. - -config STM32_COMP2_POL - int "COMP2 polarity" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 output polarity. - -config STM32_COMP2_HYST - int "COMP2 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP2. - -config STM32_COMP2_BLANKSEL - int "COMP2 blanking signal select" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP2. - -config STM32_COMP2_LOCK - int "COMP2 COMP_CxCSR register lock" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP3_OUT - bool "COMP3 GPIO Output" - depends on STM32_COMP3 - default n - ---help--- - Enables COMP3 output. - -config STM32_COMP3_INM - int "COMP3 inverting input assignment" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects COMP3 inverting input pin. - -config STM32_COMP3_INP - int "COMP3 non-inverting input assignment" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 non-inverting input pin. - -config STM32_COMP3_POL - int "COMP3 polarity" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 output polarity. - -config STM32_COMP3_HYST - int "COMP3 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP3. - -config STM32_COMP3_BLANKSEL - int "COMP3 blanking signal select" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP3. - -config STM32_COMP3_LOCK - int "COMP3 COMP_CxCSR register lock" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP4_OUT - bool "COMP4 GPIO Output" - depends on STM32_COMP4 - default n - ---help--- - Enables COMP4 output. - -config STM32_COMP4_INM - int "COMP4 inverting input assignment" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects COMP4 inverting input pin. - -config STM32_COMP4_INP - int "COMP4 non-inverting input assignment" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 non-inverting input pin. - -config STM32_COMP4_POL - int "COMP4 polarity" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 output polarity. - -config STM32_COMP4_HYST - int "COMP4 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP4. - -config STM32_COMP4_BLANKSEL - int "COMP4 blanking signal select" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP4. - -config STM32_COMP4_LOCK - int "COMP4 COMP_CxCSR register lock" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP5_OUT - bool "COMP5 GPIO Output" - depends on STM32_COMP5 - default n - ---help--- - Enables COMP5 output. - -config STM32_COMP5_INM - int "COMP5 inverting input assignment" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects COMP5 inverting input pin. - -config STM32_COMP5_INP - int "COMP5 non-inverting input assignment" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 non-inverting input pin. - -config STM32_COMP5_POL - int "COMP5 polarity" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 output polarity. - -config STM32_COMP5_HYST - int "COMP5 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP5. - -config STM32_COMP5_BLANKSEL - int "COMP5 blanking signal select" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP5. - -config STM32_COMP5_LOCK - int "COMP5 COMP_CxCSR register lock" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP6_OUT - bool "COMP6 GPIO Output" - depends on STM32_COMP6 - default n - ---help--- - Enables COMP6 output. - -config STM32_COMP6_INM - int "COMP6 inverting input assignment" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects COMP6 inverting input pin. - -config STM32_COMP6_INP - int "COMP6 non-inverting input assignment" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 non-inverting input pin. - -config STM32_COMP6_POL - int "COMP6 polarity" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 output polarity. - -config STM32_COMP6_HYST - int "COMP6 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP6. - -config STM32_COMP6_BLANKSEL - int "COMP6 blanking signal select" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP6. - -config STM32_COMP6_LOCK - int "COMP6 COMP_CxCSR register lock" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP7_OUT - bool "COMP7 GPIO Output" - depends on STM32_COMP7 - default n - ---help--- - Enables COMP7 output. - -config STM32_COMP7_INM - int "COMP7 inverting input assignment" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects COMP7 inverting input pin. - -config STM32_COMP7_INP - int "COMP7 non-inverting input assignment" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 non-inverting input pin. - -config STM32_COMP7_POL - int "COMP7 polarity" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 output polarity. - -config STM32_COMP7_HYST - int "COMP7 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP7. - -config STM32_COMP7_BLANKSEL - int "COMP7 blanking signal select" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP7. - -config STM32_COMP7_LOCK - int "COMP7 COMP_CxCSR register lock" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -endmenu - -menu "SDADC Configuration" - depends on STM32_SDADC - -config STM32_SDADC1_DMA - bool "SDADC1 DMA" - depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC2_DMA - bool "SDADC2 DMA" - depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC3_DMA - bool "SDADC3 DMA" - depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -menu "DAC Configuration" - depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 - -config STM32_DAC1CH1_MODE - int "DAC1CH1 channel mode" - depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH1_DMA - bool "DAC1CH1 DMA" - depends on STM32_DAC1CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH1_DMA - -config STM32_DAC1CH1_DMA_BUFFER_SIZE - int "DAC1CH1 DMA buffer size" - default 256 - -config STM32_DAC1CH1_DMA_EXTERNAL - bool "DAC1CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH1_HRTIM_TRG1 - bool "DAC1CH1 HRTIM Trigger 1" - default n - -config STM32_DAC1CH1_HRTIM_TRG2 - bool "DAC1CH1 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH1_TIMER - int "DAC1CH1 timer" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH1_TIMER_FREQUENCY - int "DAC1CH1 timer frequency" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC1CH2_MODE - int "DAC1CH2 channel mode" - depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH2_DMA - bool "DAC1CH2 DMA" - depends on STM32_DAC1CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH2_DMA - -config STM32_DAC1CH2_DMA_BUFFER_SIZE - int "DAC1CH2 DMA buffer size" - default 256 - -config STM32_DAC1CH2_DMA_EXTERNAL - bool "DAC1CH2 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH2_HRTIM_TRG1 - bool "DAC1CH2 HRTIM Trigger 1" - default n - -config STM32_DAC1CH2_HRTIM_TRG2 - bool "DAC1CH2 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH2_TIMER - int "DAC1CH2 timer" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH2_TIMER_FREQUENCY - int "DAC1CH2 timer frequency" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC2CH1_MODE - int "DAC2CH1 channel mode" - depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC2CH1_DMA - bool "DAC2CH1 DMA" - depends on STM32_DAC2CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC2CH1_DMA - -config STM32_DAC2CH1_DMA_BUFFER_SIZE - int "DAC2CH1 DMA buffer size" - default 256 - -config STM32_DAC2CH1_DMA_EXTERNAL - bool "DAC2CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC2CH1_HRTIM_TRG3 - bool "DAC2CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC2CH1_TIMER - int "DAC2CH1 timer" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC2CH1_TIMER_FREQUENCY - int "DAC2CH1 timer frequency" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH1_MODE - int "DAC3CH1 channel mode" - depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH1_DMA - bool "DAC3CH1 DMA" - depends on STM32_DAC3CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH1_DMA - -config STM32_DAC3CH1_DMA_BUFFER_SIZE - int "DAC3CH1 DMA buffer size" - default 256 - -config STM32_DAC3CH1_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH1_HRTIM_TRG3 - bool "DAC3CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH1_TIMER - int "DAC3CH1 timer" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH1_TIMER_FREQUENCY - int "DAC3CH1 timer frequency" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH2_MODE - int "DAC3CH2 channel mode" - depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH2_DMA - bool "DAC3CH2 DMA" - depends on STM32_DAC3CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH2_DMA - -config STM32_DAC3CH2_DMA_BUFFER_SIZE - int "DAC3CH2 DMA buffer size" - default 256 - -config STM32_DAC3CH2_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH2_HRTIM_TRG3 - bool "DAC3CH2 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH2_TIMER - int "DAC3CH2 timer" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH2_TIMER_FREQUENCY - int "DAC3CH2 timer frequency" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - -endif - -endmenu - -config STM32_USART - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -config STM32_HCIUART - bool - default n - -config STM32_HCIUART_RXDMA - bool - default n - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - - -if STM32_USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART1_SERIALDRIVER - -if STM32_USART1_HCIUART - -config STM32_HCIUART1_RXBUFSIZE - int "HCI UART1 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART1_TXBUFSIZE - int "HCI UART1 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART1_BAUD - int "HCI UART1 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART1_RXDMA - bool "HCI UART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART1_HCIUART - - -if STM32_USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART2_SERIALDRIVER - -if STM32_USART2_HCIUART - -config STM32_HCIUART2_RXBUFSIZE - int "HCI UART2 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART2_TXBUFSIZE - int "HCI UART2 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART2_BAUD - int "HCI UART2 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART2_RXDMA - bool "HCI UART2 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART2_HCIUART - - -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART3_SERIALDRIVER - -if STM32_USART3_HCIUART - -config STM32_HCIUART3_RXBUFSIZE - int "HCI UART3 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART3_TXBUFSIZE - int "HCI UART3 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART3_BAUD - int "HCI UART3 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART3_RXDMA - bool "HCI UART3 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART3_HCIUART - - -if STM32_UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART4_SERIALDRIVER - - -if STM32_UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART5_SERIALDRIVER - - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART6_SERIALDRIVER - -if STM32_USART6_HCIUART - -config STM32_HCIUART6_RXBUFSIZE - int "HCI UART6 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART6_TXBUFSIZE - int "HCI UART6 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART6_BAUD - int "HCI UART6 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART6_RXDMA - bool "HCI UART6 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART6_HCIUART - -choice - prompt "UART7 Driver Configuration" - default STM32_UART7_SERIALDRIVER - depends on STM32_UART7 - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART7_SERIALDRIVER - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - default STM32_UART8_SERIALDRIVER - depends on STM32_UART8 - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART8_SERIALDRIVER - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - - -if STM32_LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config LPUART1_TXDMA - bool "LPUART1 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_LPUART1_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -endmenu # Serial Driver Configuration - -menu "HCI UART Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_HCIUART_RXDMA_BUFSIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - depends on STM32_HCIUART_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_HCIUART_RXDMAPRIO - hex "HCI UART DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - depends on STM32_HCIUART_RXDMA - ---help--- - Select HCI UART DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_HCIUART_SW_RXFLOW - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Current STM32 have - broken HW based RTS behavior (they assert nRTS after every byte - received) Enable this setting workaround this issue by using - software based management of RTS - - If HCI UART DMA is enabled, this is probably the better selection - as well. In that case, the Rx DMA buffer will avoid Rx overrun due - to short, bursty activity. Software RTS management will probably - result in overall better throughput and should still avoid Rx data - overrun conditions. - -config STM32_HCIUART_UPPER_WATERMARK - int "RTS flow control upper watermark (%)" - default 75 - range 2 100 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be asserted - when this amount of Rx data has been buffered. The amount is - expressed as a percentage of the Rx buffer size. - -config STM32_HCIUART_LOWER_WATERMARK - int "RTS flow control lower watermark (%)" - default 25 - range 1 99 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be de-asserted - when there is less than this amount ofdata in the Rx buffere. The - amount is expressed as a percentage of the Rx buffer size. - -endmenu # HCI UART Driver Configuration - -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC default 0 - depends on STM32_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA + range 0 3 ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC default 0 - depends on STM32_SPI5_DMA + range 0 3 ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32_SPI6_DMA - bool "SPI6 DMA" +config STM32_ADC4_DMA + bool "ADC4 DMA" + depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA default n - depends on STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" +config STM32_ADC4_DMA_CFG + int "ADC4 DMA configuration" + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC + range 0 1 default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # SPI Configuration - -menu "I2S Configuration" - depends on STM32_I2S3 - -config STM32_I2S_MCK - bool "I2S_MCK" - default n - ---help--- - TBD. - -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -comment "I2S3 Configuration" - -config STM32_I2S3_DATALEN - int "Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -#if STM32_I2S -config STM32_I2S3_RX - bool "Enable I2S receiver" - default n ---help--- - Enable I2S receipt logic + 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode -config STM32_I2S3_TX - bool "Enable I2S transmitter" - default n +config STM32_ADC4_DMA_BATCH + int "ADC4 DMA number of conversions" + depends on STM32_ADC4 && STM32_ADC4_DMA + default 1 ---help--- - Enable I2S transmission logic + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n +config STM32_ADC4_ANIOC_TRIGGER + int "ADC4 software trigger (ANIOC_TRIGGER) configuration" + depends on STM32_ADC4 + range 1 3 + default 3 ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA default n ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_ALT - bool "Alternate I2C implementation" - default STM32_PERFORMANCELINE - depends on !STM32_STM32F30XX - ---help--- - This selection enables an alternative I2C driver. This alternate - driver implements some rather complex workarounds for errata against - the STM32 F103 "Performance Line". This selection is an option - because: (1) It has not yet been fully verified and (2) It is not - certain that he scope of this workaround is needed only for the F103. - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. -config STM32_I2CTIMEOSEC - int "Timeout seconds" +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC + range 0 1 default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2C_DUTY16_9 - bool "Frequency with Tlow/Thigh = 16/9" - default n - depends on STM32_I2C - -config STM32_I2C_DMA - bool "I2C DMA Support" - default n - depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED ---help--- - This option enables the DMA for I2C transfers. - Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the - I2C dma streams, else the default priority level is set to medium. - -endmenu - -menu "I2C Slave Configuration" - depends on STM32_I2C_SLAVE - -config STM32_I2C_SLAVE_DEFAULT_TX - hex "Default TX byte to be sent when the TX buffer is empty" - default 0xFF + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode -config STM32_I2C_SLAVE_USEWQ - bool "Use work queue to delegate the isr completion status" - default n +config STM32_ADC5_DMA_BATCH + int "ADC5 DMA number of conversions" + depends on STM32_ADC5 && STM32_ADC5_DMA + default 1 ---help--- - With the current upperhalf I2C slave driver implementation, the user - should delegate the callback completion status using a work queue. - However, work queues introduce a delay, so in certain scenarios - it is better to use a custom driver without using a work queue. + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. -config STM32_I2C_SLAVE_RETRANSFER - bool "The frame is retransferred when stop is issued beforehand" - default n +config STM32_ADC4_INJECTED_CHAN + int "ADC4 injected channels" + depends on STM32_ADC4 + range 0 4 + default 0 ---help--- - If stop is issued before the whole frame is transferred, - the tx pointer is reset to 0. - -endmenu + Support for ADC4 injected channels. -menu "SDIO Configuration" - depends on STM32_SDIO +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. -config STM32_SDIO_CARD - bool "SDIO Card support" +config STM32_ADC4_EXTSEL + bool "ADC4 external trigger for regular group" + depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER default n ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) + Enable EXTSEL for ADC4. -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER default n ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. + Enable EXTSEL for ADC5. -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 +config STM32_ADC4_JEXTSEL + bool "ADC4 external trigger for injected group" + depends on STM32_ADC4 + default n ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + Enable JEXTSEL for ADC4. -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n ---help--- - Select SDIO DMA priority. + Enable JEXTSEL for ADC5. - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. +endmenu - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. +menu "COMP Configuration" + depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + depends on STM32_COMP1 default n ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu + Enables COMP1 output. -if STM32_BKPSRAM +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. -config STM32_BBSRAM - bool "BBSRAM File Support" - default n +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 +config STM32_COMP1_POL + int "COMP1 polarity" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. -endif # STM32_BKPSRAM +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. -config STM32_HAVE_RTC_COUNTER - bool - default n +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + depends on STM32_COMP2 default n + ---help--- + Enables COMP2 output. -menu "RTC Configuration" - depends on STM32_RTC - -config STM32_RTC_MAGIC_REG - int "BKP register" +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + depends on STM32_COMP2 + range 0 7 default 0 - range 0 19 - depends on !STM32_HAVE_RTC_COUNTER ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup + Selects COMP2 inverting input pin. -config STM32_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - depends on !STM32_HAVE_RTC_COUNTER +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + depends on STM32_COMP2 + range 0 1 + default 0 ---help--- - Value used as Magic to determine if the RTC is already setup + Selects COMP2 non-inverting input pin. -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - depends on !STM32_HAVE_RTC_COUNTER +config STM32_COMP2_POL + int "COMP2 polarity" + depends on STM32_COMP2 + range 0 1 + default 0 ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set + Selects COMP2 output polarity. -endmenu # RTC configuration +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. -menu "Ethernet MAC configuration" - depends on STM32_ETHMAC +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. -config STM32_PHYADDR - int "PHY address" - default 1 +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + depends on STM32_COMP2 + range 0 1 + default 0 ---help--- - The 5-bit address of the PHY on the board. Default: 1 + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_PHYINIT - bool "Board-specific PHY Initialization" +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + depends on STM32_COMP3 default n ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. + Enables COMP3 output. -config STM32_MII - bool "Use MII interface" - default n +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + depends on STM32_COMP3 + range 0 7 + default 0 ---help--- - Support Ethernet MII interface. + Selects COMP3 inverting input pin. +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. -config STM32_AUTONEG - bool "Use autonegotiation" - default y +config STM32_COMP3_POL + int "COMP3 polarity" + depends on STM32_COMP3 + range 0 1 + default 0 ---help--- - Use PHY autonegotiation to determine speed and mode + Selects COMP3 output polarity. -config STM32_ETHFD - bool "Full duplex" - default n - depends on !STM32_AUTONEG +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP3 + range 0 7 + default 0 ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex + Selects the hysteresis of the COMP3. -config STM32_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32_AUTONEG +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + depends on STM32_COMP3 + range 0 7 + default 0 ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps + Selects the blanking signal for comparator COMP3. -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32_AUTONEG +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + depends on STM32_COMP3 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + depends on STM32_COMP4 default n - depends on STM32_AUTONEG ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + depends on STM32_COMP4 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. + Selects COMP4 non-inverting input pin. -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG +config STM32_COMP4_POL + int "COMP4 polarity" + depends on STM32_COMP4 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. + Selects COMP4 output polarity. -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP4 + range 0 7 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. + Selects the hysteresis of the COMP4. -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + depends on STM32_COMP4 + range 0 7 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. + Selects the blanking signal for comparator COMP4. -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + depends on STM32_COMP4 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + depends on STM32_COMP5 + default n ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. + Enables COMP5 output. -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + depends on STM32_COMP5 + range 0 7 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. + Selects COMP5 inverting input pin. -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + depends on STM32_COMP5 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. + Selects COMP5 non-inverting input pin. -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG +config STM32_COMP5_POL + int "COMP5 polarity" + depends on STM32_COMP5 + range 0 1 + default 0 ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. + Selects COMP5 output polarity. -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - default n +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP5 + range 0 7 + default 0 ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. + Selects the hysteresis of the COMP5. -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + depends on STM32_COMP5 + range 0 7 + default 0 ---help--- - Enables Precision Time Protocol (PTP) hardware timer. + Selects the blanking signal for comparator COMP5. -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_ETH_PTP - default n +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + depends on STM32_COMP5 + range 0 1 + default 0 ---help--- - Enables pulse-per-second output on GPIO pin. + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_ETH_PTP +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + depends on STM32_COMP6 default n ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. + Enables COMP6 output. -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + depends on STM32_COMP6 + range 0 7 + default 0 ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - + Selects COMP6 inverting input pin. -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + depends on STM32_COMP6 + range 0 1 + default 0 ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_OTGFS || STM32_OTGHS - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_OTGFS && STM32_USBHOST + Selects COMP6 non-inverting input pin. -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 +config STM32_COMP6_POL + int "COMP6 polarity" + depends on STM32_COMP6 + range 0 1 + default 0 ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + Selects COMP6 output polarity. -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP6 + range 0 7 + default 0 ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + Selects the hysteresis of the COMP6. -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + depends on STM32_COMP6 + range 0 7 + default 0 ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + Selects the blanking signal for comparator COMP6. -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + depends on STM32_COMP6 + range 0 1 + default 0 ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + depends on STM32_COMP7 default n ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB HS Host Configuration" - depends on STM32_OTGHS && STM32_USBHOST + Enables COMP7 output. -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + depends on STM32_COMP7 + range 0 7 + default 0 ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + Selects COMP7 inverting input pin. -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + depends on STM32_COMP7 + range 0 1 + default 0 ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + Selects COMP7 non-inverting input pin. -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 +config STM32_COMP7_POL + int "COMP7 polarity" + depends on STM32_COMP7 + range 0 1 + default 0 ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + Selects COMP7 output polarity. -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP7 + range 0 7 + default 0 ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 + Selects the hysteresis of the COMP7. -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + depends on STM32_COMP7 + range 0 7 + default 0 ---help--- - Enable SOF interrupts. Why would you ever want to do that? + Selects the blanking signal for comparator COMP7. -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + depends on STM32_COMP7 + range 0 1 + default 0 ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock endmenu -menu "USB Host Debug Configuration" - depends on STM32_USBHOST - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. +menu "SDADC Configuration" + depends on STM32_SDADC -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA default n - depends on STM32_USBHOST && DEBUG_USB_INFO ---help--- - Dump all incoming and outgoing USB packets. - -endmenu - -comment "USB Device Configuration" - -menu "USB Full Speed Debug Configuration" - depends on STM32_USBFS + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA default n - depends on STM32_USBFS && DEBUG_USB_INFO ---help--- - Enable very low-level register access debug. - -endmenu - -menu "OTG Configuration" - depends on STM32_OTGFS + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA default n ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. endmenu -config STM32_USB_ITRMP - bool "Re-map USB interrupt" - default STM32_CAN1 - depends on STM32_USB && STM32_STM32F30XX - ---help--- - The legacy USB in the F1 series shared interrupt lines with USB - device and CAN1. In the F3 series, a hardware options was added to - either retain the legacy F1 behavior or to map the USB interrupts to - their own dedicated vectors. The option is available only for the - F3 family and selects the use of the dedicated USB interrupts. - -menu "CAN driver configuration" - depends on STM32_CAN - - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 +menu "DAC Configuration" + depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - default 7 +config STM32_DAC1CH1_MODE + int "DAC1CH1 channel mode" + depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 + default 0 + range 0 7 ---help--- - The number of CAN time quanta in segment 2. Default: 7 + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO +config STM32_DAC1CH1_DMA + bool "DAC1CH1 DMA" + depends on STM32_DAC1CH1 default n ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu # "CAN driver configuration" - -menu "FDCAN driver configuration" - depends on STM32_FDCAN + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. +if STM32_DAC1CH1_DMA -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" +config STM32_DAC1CH1_DMA_EXTERNAL + bool "DAC1CH1 DMA External Trigger" default n -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - - +if STM32_HRTIM_DAC -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" +config STM32_DAC1CH1_HRTIM_TRG1 + bool "DAC1CH1 HRTIM Trigger 1" default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +config STM32_DAC1CH1_HRTIM_TRG2 + bool "DAC1CH1 HRTIM Trigger 2" + default n -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +endif # STM32_HRTIM_DAC -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS +config STM32_DAC1CH1_TIMER + int "DAC1CH1 timer" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + range 2 8 -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). +config STM32_DAC1CH1_TIMER_FREQUENCY + int "DAC1CH1 timer frequency" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + default 0 -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +endif -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS +config STM32_DAC1CH2_MODE + int "DAC1CH2 channel mode" + depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 + default 0 + range 0 7 ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS +config STM32_DAC1CH2_DMA + bool "DAC1CH2 DMA" + depends on STM32_DAC1CH2 + default n ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. -endmenu # FDCAN1 device driver options +if STM32_DAC1CH2_DMA -menu "FDCAN2 device driver options" - depends on STM32_FDCAN2 +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 +config STM32_DAC1CH2_DMA_EXTERNAL + bool "DAC1CH2 DMA External Trigger" + default n +if STM32_HRTIM_DAC -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" +config STM32_DAC1CH2_HRTIM_TRG1 + bool "DAC1CH2 HRTIM Trigger 1" default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. -comment "Nominal Bit Timing" - -config STM32_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. +config STM32_DAC1CH2_HRTIM_TRG2 + bool "DAC1CH2 HRTIM Trigger 2" + default n -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +endif # STM32_HRTIM_DAC -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +config STM32_DAC1CH2_TIMER + int "DAC1CH2 timer" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + range 2 8 -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +config STM32_DAC1CH2_TIMER_FREQUENCY + int "DAC1CH2 timer frequency" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + default 0 -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN2_FD_BRS +endif -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN2_FD_BRS +config STM32_DAC2CH1_MODE + int "DAC2CH1 channel mode" + depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 + default 0 + range 0 7 ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS +config STM32_DAC2CH1_DMA + bool "DAC2CH1 DMA" + depends on STM32_DAC2CH1 + default n ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +if STM32_DAC2CH1_DMA -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 -endmenu # FDCAN2 device driver options +config STM32_DAC2CH1_DMA_EXTERNAL + bool "DAC2CH1 DMA External Trigger" + default n -menu "FDCAN3 device driver options" - depends on STM32_FDCAN3 +if STM32_HRTIM_DAC -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 +config STM32_DAC2CH1_HRTIM_TRG3 + bool "DAC2CH1 HRTIM Trigger 3" + default n -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format +endif # STM32_HRTIM_DAC -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 +config STM32_DAC2CH1_TIMER + int "DAC2CH1 timer" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + range 2 8 -endchoice # FDCAN3 frame format +config STM32_DAC2CH1_TIMER_FREQUENCY + int "DAC2CH1 timer frequency" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC +endif -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" +config STM32_DAC3CH1_MODE + int "DAC3CH1 channel mode" + depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 + default 0 + range 0 7 ---help--- - Enable Classic CAN mode + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD +config STM32_DAC3CH1_DMA + bool "DAC3CH1 DMA" + depends on STM32_DAC3CH1 + default n ---help--- - Enable CAN FD mode + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. +if STM32_DAC3CH1_DMA -endchoice # FDCAN3 mode +config STM32_DAC3CH1_DMA_BUFFER_SIZE + int "DAC3CH1 DMA buffer size" + default 256 -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" +config STM32_DAC3CH1_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. -comment "Nominal Bit Timing" +if STM32_HRTIM_DAC -config STM32_FDCAN3_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. +config STM32_DAC3CH1_HRTIM_TRG3 + bool "DAC3CH1 HRTIM Trigger 3" + default n -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +endif # STM32_HRTIM_DAC -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +config STM32_DAC3CH1_TIMER + int "DAC3CH1 timer" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + range 2 8 -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +config STM32_DAC3CH1_TIMER_FREQUENCY + int "DAC3CH1 timer frequency" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN3_FD_BRS +endif -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN3_FD_BRS +config STM32_DAC3CH2_MODE + int "DAC3CH2 channel mode" + depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 + default 0 + range 0 7 ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS +config STM32_DAC3CH2_DMA + bool "DAC3CH2 DMA" + depends on STM32_DAC3CH2 + default n ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). +if STM32_DAC3CH2_DMA -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. +config STM32_DAC3CH2_DMA_BUFFER_SIZE + int "DAC3CH2 DMA buffer size" + default 256 -endmenu # FDCAN3 device driver options +config STM32_DAC3CH2_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n -endmenu # "FDCAN driver configuration" +if STM32_HRTIM_DAC -if STM32_LTDC +config STM32_DAC3CH2_HRTIM_TRG3 + bool "DAC3CH2 HRTIM Trigger 3" + default n -menu "LTDC Configuration" +endif # STM32_HRTIM_DAC -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y +config STM32_DAC3CH2_TIMER + int "DAC3CH2 timer" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + range 2 8 -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 +config STM32_DAC3CH2_TIMER_FREQUENCY + int "DAC3CH2 timer frequency" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. +endif -config STM32_LTDC_DITHER - bool "Dither support" +endmenu + +config STM32_HCIUART_RXDMA + bool default n -config STM32_LTDC_DITHER_RED - depends on STM32_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. +menu "U[S]ART Configuration" + depends on STM32_USART -config STM32_LTDC_DITHER_GREEN - depends on STM32_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. +comment "U[S]ART Device Configuration" -config STM32_LTDC_DITHER_BLUE - depends on STM32_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. +if STM32_USART1_HCIUART -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 +config STM32_HCIUART1_RXBUFSIZE + int "HCI UART1 Rx buffer size" + default 80 ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 +config STM32_HCIUART1_TXBUFSIZE + int "HCI UART1 Transmit buffer size" + default 80 ---help--- - Must be the whole size of the active LTDC layer. + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y +config STM32_HCIUART1_BAUD + int "HCI UART1 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 +config STM32_HCIUART1_RXDMA + bool "HCI UART1 Rx DMA" + default n + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 +endif # STM32_USART1_HCIUART +if STM32_USART2_HCIUART -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y +config STM32_HCIUART2_RXBUFSIZE + int "HCI UART2 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received -if STM32_LTDC_L2 +config STM32_HCIUART2_TXBUFSIZE + int "HCI UART2 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 +config STM32_HCIUART2_BAUD + int "HCI UART2 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y +config STM32_HCIUART2_RXDMA + bool "HCI UART2 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 +endif # STM32_USART2_HCIUART +if STM32_USART3_HCIUART -endif # STM32_LTDC_L2 +config STM32_HCIUART3_RXBUFSIZE + int "HCI UART3 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP +config STM32_HCIUART3_TXBUFSIZE + int "HCI UART3 Transmit buffer size" + default 80 ---help--- - Enabling color map support is necessary for LTDC L8 format. + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32_FB_CMAP - select FB_TRANSPARENCY +config STM32_HCIUART3_BAUD + int "HCI UART3 initial BAUD rate" + default 115200 ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on DEBUG_INFO && DEBUG_LCD +config STM32_HCIUART3_RXDMA + bool "HCI UART3 Rx DMA" default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA ---help--- - Output detailed register-level LTDC device debug information. -endmenu - -endif # STM32_LTDC - -if STM32_DMA2D + In high data rate usage, Rx DMA may eliminate Rx overrun errors -menu "DMA2D Configuration" +endif # STM32_USART3_HCIUART -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. +if STM32_USART6_HCIUART -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n +config STM32_HCIUART6_RXBUFSIZE + int "HCI UART6 Rx buffer size" + default 80 ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 +config STM32_HCIUART6_TXBUFSIZE + int "HCI UART6 Transmit buffer size" + default 80 ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 +config STM32_HCIUART6_BAUD + int "HCI UART6 initial BAUD rate" + default 115200 ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 +config STM32_HCIUART6_RXDMA + bool "HCI UART6 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32_DMA2D_L8 - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32_DMA2D_AL44 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32_DMA2D_AL88 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y + In high data rate usage, Rx DMA may eliminate Rx overrun errors -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y +endif # STM32_USART6_HCIUART -endmenu +if STM32_LPUART1_SERIALDRIVER -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD +config LPUART1_TXDMA + bool "LPUART1 Tx DMA" default n + depends on STM32_DMA1 ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32_DMA2D - -config STM32_QE - bool - default n - -menu "STM32 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 + In high data rate usage, Tx DMA may reduce CPU load -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n +endif # STM32_LPUART1_SERIALDRIVER -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n +menu "HCI UART Driver Configuration" + depends on STM32_SERIALDRIVER -config STM32_TIM1_QE - bool "TIM1 QE" - default n - depends on STM32_TIM1 - select STM32_QE +config STM32_HCIUART_RXDMA_BUFSIZE + int "Rx DMA buffer size" + default 32 + range 32 4096 + depends on STM32_HCIUART_RXDMA ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32_TIM1_QE + The DMA buffer size when using RX DMA to emulate a FIFO. -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. -endif + Value given here will be rounded up to next multiple of 4 bytes. -config STM32_TIM2_QE - bool "TIM2 QE" - default n - depends on STM32_TIM2 - select STM32_QE +config STM32_HCIUART_RXDMAPRIO + hex "HCI UART DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_HCIUART_RXDMA ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32_TIM2_QE + Select HCI UART DMA priority. -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. -endif + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. -config STM32_TIM3_QE - bool "TIM3 QE" +config STM32_HCIUART_SW_RXFLOW + bool "Use Software UART RTS flow control" default n - depends on STM32_TIM3 - select STM32_QE ---help--- - Reserve TIM3 for use by QEncoder. + Enable UART RTS flow control using Software. Current STM32 have + broken HW based RTS behavior (they assert nRTS after every byte + received) Enable this setting workaround this issue by using + software based management of RTS -if STM32_TIM3_QE + If HCI UART DMA is enabled, this is probably the better selection + as well. In that case, the Rx DMA buffer will avoid Rx overrun due + to short, bursty activity. Software RTS management will probably + result in overall better throughput and should still avoid Rx data + overrun conditions. -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 +config STM32_HCIUART_UPPER_WATERMARK + int "RTS flow control upper watermark (%)" + default 75 + range 2 100 + depends on STM32_HCIUART_SW_RXFLOW ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif + If software RTS flow control is enable, then RTS will be asserted + when this amount of Rx data has been buffered. The amount is + expressed as a percentage of the Rx buffer size. -config STM32_TIM4_QE - bool "TIM4 QE" - default n - depends on STM32_TIM4 - select STM32_QE +config STM32_HCIUART_LOWER_WATERMARK + int "RTS flow control lower watermark (%)" + default 25 + range 1 99 + depends on STM32_HCIUART_SW_RXFLOW ---help--- - Reserve TIM4 for use by QEncoder. + If software RTS flow control is enable, then RTS will be de-asserted + when there is less than this amount ofdata in the Rx buffere. The + amount is expressed as a percentage of the Rx buffer size. -if STM32_TIM4_QE +endmenu # HCI UART Driver Configuration -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. +endmenu # U[S]ART Configuration -endif +menu "I2S Configuration" + depends on STM32_I2S3 -config STM32_TIM5_QE - bool "TIM5 QE" +config STM32_I2S_MCK + bool "I2S_MCK" default n - depends on STM32_TIM5 - select STM32_QE ---help--- - Reserve TIM5 for use by QEncoder. + TBD. -if STM32_TIM5_QE +comment "I2S3 Configuration" -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. +endmenu # I2S Configuration -endif +menu "I2C Configuration" + depends on STM32_I2C -config STM32_TIM8_QE - bool "TIM8 QE" - default n - depends on STM32_TIM8 - select STM32_QE +config STM32_I2C_ALT + bool "Alternate I2C implementation" + default STM32_PERFORMANCELINE + depends on !STM32_STM32F30XX ---help--- - Reserve TIM8 for use by QEncoder. + This selection enables an alternative I2C driver. This alternate + driver implements some rather complex workarounds for errata against + the STM32 F103 "Performance Line". This selection is an option + because: (1) It has not yet been fully verified and (2) It is not + certain that he scope of this workaround is needed only for the F103. -if STM32_TIM8_QE +config STM32_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9" + default n + depends on STM32_I2C -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - default 1 +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - - + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. endmenu -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV +menu "I2C Slave Configuration" + depends on STM32_I2C_SLAVE -if STM32_FOC +config STM32_I2C_SLAVE_DEFAULT_TX + hex "Default TX byte to be sent when the TX buffer is empty" + default 0xFF -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" +config STM32_I2C_SLAVE_USEWQ + bool "Use work queue to delegate the isr completion status" default n - depends on STM32_HAVE_TIM1 - select STM32_FOC_USE_TIM1 ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation + With the current upperhalf I2C slave driver implementation, the user + should delegate the callback completion status using a work queue. + However, work queues introduce a delay, so in certain scenarios + it is better to use a custom driver without using a work queue. -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" +config STM32_I2C_SLAVE_RETRANSFER + bool "The frame is retransferred when stop is issued beforehand" default n - depends on STM32_HAVE_TIM8 - select STM32_FOC_USE_TIM8 ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - - -if STM32_FOC_FOC0 - - -endif # STM32_FOC_FOC0 - -if STM32_FOC_FOC1 - + If stop is issued before the whole frame is transferred, + the tx pointer is reset to 0. -endif # STM32_FOC_FOC1 +endmenu -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" +config STM32_HAVE_RTC_COUNTER + bool default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) -# hidden variables and automatic configuration +comment "USB Device Configuration" -config STM32_FOC_USE_TIM1 - bool - default n - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - default n - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - default n - select STM32_ADC1 - select STM32_ADC1_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL +config STM32_USB_ITRMP + bool "Re-map USB interrupt" + default STM32_CAN1 + depends on STM32_USB && STM32_STM32F30XX + ---help--- + The legacy USB in the F1 series shared interrupt lines with USB + device and CAN1. In the F3 series, a hardware options was added to + either retain the legacy F1 behavior or to map the USB interrupts to + their own dedicated vectors. The option is available only for the + F3 family and selects the use of the dedicated USB interrupts. -config STM32_FOC_USE_ADC2 +config STM32_QE bool default n - select STM32_ADC2 - select STM32_ADC2_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL -config STM32_FOC_USE_ADC3 - bool - default n - select STM32_ADC3 - select STM32_ADC3_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL +if STM32_FOC config STM32_FOC_USE_ADC4 bool diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 40cddb539a162..f001d7bf8f315 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -5,6 +5,17 @@ comment "STM32F0/L0/G0 Configuration Options" +config STM32_F0L0G0_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + select STM32_HAVE_COMP + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "ST STM32F0/L0/G0 Chip Selection" default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 @@ -643,86 +654,6 @@ config ARCH_CHIP_STM32G0B1VE select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - config ARCH_CHIP_STM32L053C8 bool "STM32L053C8" select ARCH_CHIP_STM32L053XX @@ -1115,51 +1046,10 @@ endchoice # ST STM32F0/L0/G0/C0 Chip Selection # Flash configurations -config STM32_FLASH_CONFIG_4 - bool - default n - -config STM32_FLASH_CONFIG_6 - bool - default n - -config STM32_FLASH_CONFIG_8 - bool - default n - -config STM32_FLASH_CONFIG_B - bool - default n - -config STM32_FLASH_CONFIG_C - bool - default n - -config STM32_FLASH_CONFIG_D - bool - default n - -config STM32_FLASH_CONFIG_E - bool - default n - -config STM32_FLASH_CONFIG_F - bool - default n - -config STM32_FLASH_CONFIG_G - bool - default n - -config STM32_FLASH_CONFIG_I - bool - default n - config STM32_FLASH_OVERRIDE bool "Override Flash Designator" default n - config STM32_STM32F0 bool default n @@ -1197,6 +1087,7 @@ config STM32_STM32L0 bool default n select STM32_ENERGYLITE + select STM32_HAVE_LCD select STM32_HAVE_VREFINT select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 @@ -1228,16 +1119,20 @@ config STM32_STM32F04X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 config STM32_STM32F05X bool default n select STM32_STM32F0 + select STM32_HAVE_DMA2 config STM32_STM32F07X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 config STM32_STM32F09X bool @@ -1429,12 +1324,6 @@ config STM32_STM32G0C1 select STM32_HAVE_CEC select STM32_HAVE_HSI48 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - config STM32_ACCESSLINE bool default n @@ -1457,10 +1346,6 @@ config STM32_USBLINE select STM32_HAVE_SPI2 select STM32_HAVE_USBDEV -config STM32_ENERGYLITE - bool - default n - config ARCH_CHIP_STM32L053XX bool select STM32_STM32L0 @@ -1517,24 +1402,6 @@ config ARCH_CHIP_STM32C092XX select STM32_HAVE_USART4 select STM32_HAVE_FDCAN1 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -config STM32_PROGMEM - bool "Flash PROGMEM support" - default n - depends on ARCH_HAVE_PROGMEM - select MTD - select MTD_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - choice prompt "SysTick clock source" default STM32_SYSTICK_CORECLK @@ -1552,38 +1419,10 @@ menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available # for the selected MCU -config STM32_HAVE_AES - bool - default n - config STM32_HAVE_VREFINT bool default n -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_HSI48 - bool - default n - -config STM32_HAVE_LCD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_USART3 - bool - default n - config STM32_HAVE_USART4 bool default n @@ -1592,10 +1431,6 @@ config STM32_HAVE_USART5 bool default n -config STM32_HAVE_USART6 - bool - default n - config STM32_HAVE_USART7 bool default n @@ -1604,2009 +1439,126 @@ config STM32_HAVE_USART8 bool default n -config STM32_HAVE_LPUART1 - bool - default n - config STM32_HAVE_LPUART2 bool default n -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 +config STM32_HAVE_ADC_OVERSAMPLE bool - default n + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 -config STM32_HAVE_TIM3 +config STM32_HAVE_CEC bool default n -config STM32_HAVE_TIM4 +config STM32_HAVE_SDIO bool default n -config STM32_HAVE_TIM6 +config STM32_HAVE_I2S2 bool default n -config STM32_HAVE_TIM7 +config STM32_HAVE_UCPD1 bool default n -config STM32_HAVE_TIM14 +config STM32_HAVE_UCPD2 bool default n -config STM32_HAVE_TIM15 - bool - default n +# These are STM32 peripherals IP blocks -config STM32_HAVE_TIM16 +config STM32_HAVE_IP_USART_V1 bool default n -config STM32_HAVE_TIM17 +config STM32_HAVE_IP_USART_V2 bool default n -config STM32_HAVE_TSC +config STM32_HAVE_IP_EXTI_V1 bool default n -config STM32_HAVE_ADC1_DMA +config STM32_HAVE_IP_EXTI_V2 bool default n -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 +# These are the peripheral selections proper -config STM32_HAVE_CEC - bool +config STM32_VREFINT + bool "Enable VREFINT" default n + depends on STM32_HAVE_VREFINT -config STM32_HAVE_CAN1 - bool +config STM32_USART4 + bool "USART4" default n + depends on STM32_HAVE_USART4 + select STM32_USART -config STM32_HAVE_COMP1 - bool +config STM32_USART5 + bool "USART5" default n + depends on STM32_HAVE_USART5 + select STM32_USART -config STM32_HAVE_COMP2 - bool +config STM32_USART7 + bool "USART7" default n + depends on STM32_HAVE_USART7 + select STM32_USART -config STM32_HAVE_COMP3 - bool +config STM32_USART8 + bool "USART8" default n + depends on STM32_HAVE_USART8 + select STM32_USART -config STM32_HAVE_DAC1 - bool - default n +endmenu # STM32 Peripheral Support -config STM32_HAVE_DMAMUX - bool - default n +menu "ADC Configuration" + depends on STM32_ADC -config STM32_HAVE_DMA2 - bool +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. -config STM32_HAVE_RNG - bool - default n +if STM32_ADC_OVERSAMPLE -config STM32_HAVE_CRS - bool +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). -config STM32_HAVE_I2C2 - bool - default n +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× -config STM32_HAVE_I2C3 - bool - default n +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - -config STM32_HAVE_SDIO - bool - default n - -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - -config STM32_HAVE_I2S2 - bool - default n - -config STM32_HAVE_UCPD1 - bool - default n - -config STM32_HAVE_UCPD2 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_USART_V1 - bool - default n - -config STM32_HAVE_IP_USART_V2 - bool - default n - -config STM32_HAVE_IP_EXTI_V1 - bool - default n - -config STM32_HAVE_IP_EXTI_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - -config STM32_COMP1 - bool "COMP1" - default n - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - depends on STM32_HAVE_COMP2 - -config STM32_BKP - bool "BKP" - default n - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32_CAN1 - bool "CAN1" - default n - select CAN - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - -config STM32_VREFINT - bool "Enable VREFINT" - default n - depends on STM32_HAVE_VREFINT - -config STM32_CEC - bool "CEC" - default n - depends on STM32_HAVE_CEC - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32_DMA - -config STM32_DMA2 - bool "DMA2" - default n - depends on STM32_HAVE_DMA2 - select ARCH_DMA - select STM32_DMA - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_HAVE_HASH - -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - -config STM32_PWR - bool "PWR" - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32_SDIO - bool "SDIO" - default n - depends on STM32_HAVE_SDIO - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - depends on STM32_HAVE_TIM2 - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - -config STM32_USART4 - bool "USART4" - default n - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - default n - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - -config STM32_USART7 - bool "USART7" - default n - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - default n - depends on STM32_HAVE_USART8 - select STM32_USART - -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_HAVE_LCD - select USBDEV - -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu # STM32 Peripheral Support - -config STM32_COMP - bool - default n - -config STM32_ADC - bool - default n - -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool - default n - -config STM32_I2C - bool - default n - -config STM32_CAN - bool - default n - -config STM32_PWM - bool - default n - -config STM32_USART - bool - default n - -config STM32_TIM - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -menu "Timer Configuration" - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - ---help--- - Reserve timer 1 for use by the pulse count driver. - - Timer devices may be used for different purposes. If STM32_TIM1 - is defined then this option may also be defined to indicate that TIM1 is - intended to generate a fixed number of output pulses. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 && !STM32_TIM1_PULSECOUNT - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM1 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - depends on STM32_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for output usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM1_QE - bool "TIM1 Quadrature Encoder" - default n - depends on STM32_TIM1 - ---help--- - Reserve TIM1 for use by Quadrature Encoder. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM2 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM2_QE - bool "TIM2 Quadrature Encoder" - default n - depends on STM32_TIM2 - ---help--- - Reserve TIM2 for use by Quadrature Encoder. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM3 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM3_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM3 - ---help--- - Reserve TIM3 for use by Quadrature Encoder. - -config STM32_TIM4_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM4 - ---help--- - Reserve TIM4 for use by Quadrature Encoder. - -menu "STM32F0L0G0 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - depends on STM32_TIM1_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - depends on STM32_TIM2_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM3_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM4_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32F0L0G0 QEncoder input" - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - - - -endmenu # STM32F0L0G0 QEncoder Driver - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output channels per timer. - -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - -config STM32_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. - This option must match with the MCU's supported EXTSEL. - -endmenu # Timer Configuration - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - - - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -endmenu # "FDCAN driver configuration" - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - - -if STM32_USART1_SERIALDRIVER - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART1_SERIALDRIVER - - -if STM32_USART2_SERIALDRIVER - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART2_SERIALDRIVER - - -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART3_SERIALDRIVER - -choice - prompt "USART4 Driver Configuration" - default STM32_USART4_SERIALDRIVER - depends on STM32_USART4 - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -if STM32_USART4_SERIALDRIVER - -config USART4_RS485 - bool "RS-485 on USART4" - default n - ---help--- - Enable RS-485 interface on USART4. Your board config will have to - provide GPIO_USART4_RS485_DIR pin definition. - -config USART4_RS485_DIR_POLARITY - int "USART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART4_SERIALDRIVER - -choice - prompt "USART5 Driver Configuration" - default STM32_USART5_SERIALDRIVER - depends on STM32_USART5 - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -if STM32_USART5_SERIALDRIVER - -config USART5_RS485 - bool "RS-485 on USART5" - default n - ---help--- - Enable RS-485 interface on USART5. Your board config will have to - provide GPIO_USART5_RS485_DIR pin definition. - -config USART5_RS485_DIR_POLARITY - int "USART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART5_SERIALDRIVER - - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART6_SERIALDRIVER - -choice - prompt "USART7 Driver Configuration" - default STM32_USART7_SERIALDRIVER - depends on STM32_USART7 - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -if STM32_USART7_SERIALDRIVER - -config USART7_RS485 - bool "RS-485 on USART7" - default n - ---help--- - Enable RS-485 interface on USART7. Your board config will have to - provide GPIO_USART7_RS485_DIR pin definition. - -config USART7_RS485_DIR_POLARITY - int "USART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART7_SERIALDRIVER - -choice - prompt "USART8 Driver Configuration" - default STM32_USART8_SERIALDRIVER - depends on STM32_USART8 - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -if STM32_USART8_SERIALDRIVER - -config USART8_RS485 - bool "RS-485 on USART8" - default n - ---help--- - Enable RS-485 interface on USART8. Your board config will have to - provide GPIO_USART8_RS485_DIR pin definition. - -config USART8_RS485_DIR_POLARITY - int "USART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART8_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. - -endmenu # Serial Driver Configuration - -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM - -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 if STM32_ADC1_DMA - default 1 if !STM32_ADC1_DMA - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. +endif # STM32_ADC_OVERSAMPLE config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" @@ -3619,99 +1571,3 @@ config STM32_ADC1_CONTINUOUS the same time endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # SPI Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -endmenu #I2C Configuration From ef1b453dc9aa4af46437affe494f00d4716404d1 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 20 May 2026 15:19:00 +0200 Subject: [PATCH 23/52] !arch/stm32: move common options to common/stm32 BREAKING CHANGE: Common STM32 Kconfig options moved to arch/arm/src/common/stm32. Out-of-tree family Kconfig files must source the common STM32 Kconfig files from their new path. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig | 709 ++++++++++++++++++++++++++++++ arch/arm/src/stm32/Kconfig | 233 ---------- arch/arm/src/stm32f0l0g0/Kconfig | 39 -- arch/arm/src/stm32n6/Kconfig | 16 - 4 files changed, 709 insertions(+), 288 deletions(-) diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 432dd225eb399..633bd210f96f5 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -75,6 +75,11 @@ config STM32_COMMON_SRAM2_OPTIONS default y if ARCH_CHIP_STM32L5 default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 +config STM32_COMMON_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + choice prompt "JTAG Configuration" default STM32_JTAG_DISABLE @@ -1777,6 +1782,9 @@ config STM32_DFU Configure and position code for use with the STMicro DFU bootloader. Do not select this option if you will load code using JTAG/SWM. +# These hidden settings determine whether a peripheral option is available +# for the selected MCU. Family Kconfigs select these from chip data. + config STM32_HAVE_AES bool @@ -1900,6 +1908,12 @@ config STM32_HAVE_ADC2 config STM32_HAVE_ADC3 bool +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + config STM32_HAVE_ADC1_DMA bool @@ -1909,12 +1923,31 @@ config STM32_HAVE_ADC2_DMA config STM32_HAVE_ADC3_DMA bool +config STM32_HAVE_ADC4_DMA + bool + +config STM32_HAVE_ADC5_DMA + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_ADC4_TIMER + bool + +config STM32_HAVE_ADC5_TIMER + bool + config STM32_HAVE_CAN1 bool config STM32_HAVE_CAN2 bool +config STM32_HAVE_CAN3 + bool + config STM32_HAVE_COMP1 bool @@ -1924,24 +1957,194 @@ config STM32_HAVE_COMP2 config STM32_HAVE_COMP3 bool +config STM32_HAVE_COMP4 + bool + +config STM32_HAVE_COMP5 + bool + +config STM32_HAVE_COMP6 + bool + +config STM32_HAVE_COMP7 + bool + config STM32_HAVE_CRS bool +config STM32_HAVE_CEC + bool + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_JPEG + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_HRTIM1_PLLCLK + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_SDADC1_DMA + bool + +config STM32_HAVE_SDADC2_DMA + bool + +config STM32_HAVE_SDADC3_DMA + bool + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_DBGMCU_V1 + bool + +config STM32_HAVE_IP_DBGMCU_V2 + bool + +config STM32_HAVE_IP_DBGMCU_V3 + bool + +config STM32_HAVE_IP_I2C_V1 + bool + +config STM32_HAVE_IP_I2C_V2 + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_TIMERS_V1 + bool + +config STM32_HAVE_IP_TIMERS_V2 + bool + +config STM32_HAVE_IP_TIMERS_V3 + bool + +config STM32_HAVE_IP_ADC_V1 + bool + +config STM32_HAVE_IP_ADC_V1_BASIC + bool + select STM32_HAVE_IP_ADC_V1 + +config STM32_HAVE_IP_ADC_V2 + bool + +config STM32_HAVE_IP_ADC_V2_BASIC + bool + select STM32_HAVE_IP_ADC_V2 + +config STM32_HAVE_IP_COMP_V1 + bool + +config STM32_HAVE_IP_COMP_V2 + bool + +config STM32_HAVE_IP_DAC_V1 + bool + +config STM32_HAVE_IP_DAC_V2 + bool + +config STM32_HAVE_IP_USART_V1 + bool + +config STM32_HAVE_IP_USART_V2 + bool + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + config STM32_HAVE_FMAC bool +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_DMA1_CHAN8 + bool + +config STM32_HAVE_DMA2_CHAN678 + bool + +config STM32_HAVE_UCPD + bool + config STM32_HAVE_DAC1 bool config STM32_HAVE_DAC2 bool +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + config STM32_HAVE_QSPI bool config STM32_HAVE_RNG bool +config STM32_HAVE_VREFINT + bool + config STM32_HAVE_I2C1 bool @@ -1966,6 +2169,9 @@ config STM32_HAVE_LPTIM1 config STM32_HAVE_LPUART1 bool +config STM32_HAVE_LPUART2 + bool + config STM32_HAVE_SPI1 bool @@ -1978,6 +2184,12 @@ config STM32_HAVE_SPI3 config STM32_HAVE_I2S3 bool +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + config STM32_HAVE_SPI4 bool @@ -2005,9 +2217,82 @@ config STM32_HAVE_OPAMP3 config STM32_HAVE_OPAMP4 bool +config STM32_HAVE_OPAMP5 + bool + +config STM32_HAVE_OPAMP6 + bool + config STM32_HAVE_IOCOMPENSATION bool +config STM32_HAVE_ICACHE + bool + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_LPUART + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_USB + bool + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_ADC1 + bool + default y if STM32_COMMON_LEGACY + config STM32_ADC1 bool "ADC1" depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 @@ -2070,6 +2355,12 @@ config STM32_CAN2 select STM32_CAN select CAN if !STM32_COMMON_LEGACY +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + config STM32_AES bool "128-bit AES" depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 @@ -2131,6 +2422,13 @@ config STM32_DCMI modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + config STM32_ETHMAC bool "Ethernet MAC" depends on STM32_HAVE_ETHERNET @@ -2174,6 +2472,13 @@ config STM32_HASH depends on STM32_HAVE_HASH select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + config STM32_I2C1 bool "I2C1" depends on STM32_HAVE_I2C1 @@ -2204,6 +2509,30 @@ config STM32_LPUART1 select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + config STM32_LTDC bool "LTDC" depends on STM32_HAVE_LTDC @@ -2284,12 +2613,31 @@ config STM32_SPI3 select SPI select STM32_SPI +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + config STM32_I2S3 bool "I2S3" depends on STM32_HAVE_I2S3 select I2S if STM32_COMMON_LEGACY select STM32_I2S +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + config STM32_SPI4 bool "SPI4" depends on STM32_HAVE_SPI4 @@ -5800,6 +6148,43 @@ config STM32_ADC_CHANGE_SAMPLETIME ---help--- Enable ADC sample time configuration (SMPRx registers). +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + config STM32_ADC1_DMA bool "ADC1 DMA" depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA @@ -6358,6 +6743,162 @@ config STM32_PM_SERIAL_ACTIVITY PM activity reported to power management logic on every serial interrupt. +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + config STM32_SPI_INTERRUPTS bool "Interrupt driver SPI" depends on STM32_SPI @@ -6456,6 +6997,21 @@ config STM32_SPI6_DMA ---help--- Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + config STM32_I2S_MAXINFLIGHT int "I2S queue size" depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) @@ -6474,6 +7030,64 @@ config STM32_I2S3_DATALEN Data width in bits. This is a default value and may be change via the I2S interface +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + #if STM32_I2S config STM32_I2S3_RX @@ -6975,6 +7589,13 @@ config STM32_CAN2_BAUD ---help--- CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + config STM32_CAN_TSEG1 int "TSEG1 quanta" depends on STM32_CAN @@ -8827,4 +9448,92 @@ config STM32_IPCC character device stream driver to exchange data between CM0 and CM4. +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 + endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 2de02dd875b1f..b8bcda25eeeb8 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2102,229 +2102,6 @@ config STM32_STM32G474V menu "STM32 Peripheral Support" -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_FLASH_ICACHE - bool - default n - -config STM32_HAVE_FLASH_DCACHE - bool - default n - -config STM32_HAVE_OVERDRIVE - bool - default n - -config STM32_HAVE_DMA1_CHAN8 - bool - default n - -config STM32_HAVE_DMA2_CHAN678 - bool - default n - -config STM32_HAVE_UCPD - bool - default n - -config STM32_HAVE_FMAC - bool - default n - -config STM32_HAVE_IOCOMPENSATION - bool - default n - -config STM32_HAVE_HRTIM1 - bool - default n - -config STM32_HAVE_HRTIM1_PLLCLK - bool - default n - -config STM32_HAVE_TIM18 - bool - default n - -config STM32_HAVE_TIM19 - bool - default n - -config STM32_HAVE_TIM20 - bool - default n - -config STM32_HAVE_ADC1 - bool - default y - -config STM32_HAVE_ADC4 - bool - default n - -config STM32_HAVE_ADC5 - bool - default n - -config STM32_HAVE_ADC4_DMA - bool - default n - -config STM32_HAVE_ADC5_DMA - bool - default n - -config STM32_HAVE_SDADC1 - bool - default n - -config STM32_HAVE_SDADC2 - bool - default n - -config STM32_HAVE_SDADC3 - bool - default n - -config STM32_HAVE_SDADC1_DMA - bool - default n - -config STM32_HAVE_SDADC2_DMA - bool - default n - -config STM32_HAVE_SDADC3_DMA - bool - default n - -config STM32_HAVE_COMP4 - bool - default n - -config STM32_HAVE_COMP5 - bool - default n - -config STM32_HAVE_COMP6 - bool - default n - -config STM32_HAVE_COMP7 - bool - default n - -config STM32_HAVE_CORDIC - bool - default n - -config STM32_HAVE_DAC3 - bool - default n - -config STM32_HAVE_DAC4 - bool - default n - -config STM32_HAVE_ETHMAC - bool - default n - -config STM32_HAVE_I2C1 - bool - default n - -config STM32_HAVE_I2S3 - bool - default n - -config STM32_HAVE_OPAMP5 - bool - default n - -config STM32_HAVE_OPAMP6 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_DBGMCU_V1 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V2 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V3 - bool - default n - -config STM32_HAVE_IP_I2C_V1 - bool - default n - -config STM32_HAVE_IP_I2C_V2 - bool - default n - -config STM32_HAVE_IP_DMA_V1 - bool - default n - -config STM32_HAVE_IP_DMA_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V1 - bool - default n - -config STM32_HAVE_IP_TIMERS_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V3 - bool - default n - -config STM32_HAVE_IP_ADC_V1 - bool - default n - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - default n - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - default n - -config STM32_HAVE_IP_COMP_V2 - bool - default n - -config STM32_HAVE_IP_DAC_V1 - bool - default n - -config STM32_HAVE_IP_DAC_V2 - bool - default n - # These are the peripheral selections proper config STM32_ADC5 @@ -2834,12 +2611,6 @@ config STM32_CCM_PROCFS menu "Timer Configuration" depends on STM32_TIM -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - if STM32_TIM9_CAP config STM32_TIM9_CLOCK @@ -4613,10 +4384,6 @@ config STM32_I2C_SLAVE_RETRANSFER endmenu -config STM32_HAVE_RTC_COUNTER - bool - default n - comment "USB Device Configuration" config STM32_USB_ITRMP diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index f001d7bf8f315..3680c9a8ac3ba 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -1521,45 +1521,6 @@ endmenu # STM32 Peripheral Support menu "ADC Configuration" depends on STM32_ADC -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" default n diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 4cbd4470f7745..b90a6b0663c17 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -27,20 +27,4 @@ config ARCH_CHIP_STM32N657X0 endchoice -menu "STM32N6 Peripheral Selection" - -if USART1_SERIALDRIVER - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -endif # USART1_SERIALDRIVER - -endmenu - endif # ARCH_CHIP_STM32N6 From 7459655a6ddd501f8d69d0f4bfcd4932898ff904 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 21:05:28 +0200 Subject: [PATCH 24/52] !arch/stm32: move peripheral options to common/stm32 BREAKING CHANGE: STM32 peripheral Kconfig options moved to arch/arm/src/common/stm32. Out-of-tree Kconfig files must update source paths and symbol references to the common STM32 option location. Signed-off-by: raiden00pl --- .../nuttx_initialization_sequence.rst | 2 +- arch/arm/src/common/stm32/Kconfig | 9572 +---------------- arch/arm/src/common/stm32/Kconfig.adc | 990 ++ arch/arm/src/common/stm32/Kconfig.ble | 221 + arch/arm/src/common/stm32/Kconfig.cache | 240 + arch/arm/src/common/stm32/Kconfig.can | 63 + arch/arm/src/common/stm32/Kconfig.comp | 402 + arch/arm/src/common/stm32/Kconfig.dac | 366 + arch/arm/src/common/stm32/Kconfig.dfsdm | 45 + arch/arm/src/common/stm32/Kconfig.dma | 123 + arch/arm/src/common/stm32/Kconfig.dts | 101 + arch/arm/src/common/stm32/Kconfig.eth | 293 + arch/arm/src/common/stm32/Kconfig.fdcan | 520 + arch/arm/src/common/stm32/Kconfig.flash | 164 + arch/arm/src/common/stm32/Kconfig.foc | 197 + arch/arm/src/common/stm32/Kconfig.gpio | 11 + arch/arm/src/common/stm32/Kconfig.have | 1144 ++ arch/arm/src/common/stm32/Kconfig.hciuart | 292 + arch/arm/src/common/stm32/Kconfig.hrtim | 588 + arch/arm/src/common/stm32/Kconfig.i2c | 309 + arch/arm/src/common/stm32/Kconfig.ipcc | 91 + arch/arm/src/common/stm32/Kconfig.lpuart | 70 + arch/arm/src/common/stm32/Kconfig.ltdc | 235 + arch/arm/src/common/stm32/Kconfig.memory | 171 + arch/arm/src/common/stm32/Kconfig.periph | 1283 +++ arch/arm/src/common/stm32/Kconfig.qspi | 173 + arch/arm/src/common/stm32/Kconfig.rtc | 93 + arch/arm/src/common/stm32/Kconfig.sai | 88 + arch/arm/src/common/stm32/Kconfig.sdadc | 42 + arch/arm/src/common/stm32/Kconfig.sdio | 153 + arch/arm/src/common/stm32/Kconfig.spi | 300 + arch/arm/src/common/stm32/Kconfig.system | 107 + arch/arm/src/common/stm32/Kconfig.tim | 4210 ++++++++ arch/arm/src/common/stm32/Kconfig.uart | 1250 +++ arch/arm/src/common/stm32/Kconfig.usb | 255 + arch/arm/src/stm32/Kconfig | 2327 ---- arch/arm/src/stm32f0l0g0/Kconfig | 119 - arch/arm/src/stm32f7/Kconfig | 20 - arch/arm/src/stm32h5/Kconfig | 8 - arch/arm/src/stm32h5/stm32_adc.c | 5 +- arch/arm/src/stm32h7/Kconfig | 19 +- arch/arm/src/stm32l4/Kconfig | 5 - arch/arm/src/stm32l5/Kconfig | 5 - arch/arm/src/stm32u5/Kconfig | 5 - arch/arm/src/stm32wb/Kconfig | 1 - .../configs/adc_watchdog/defconfig | 2 +- .../nucleo-h723zg/configs/netnsh/defconfig | 2 +- .../nucleo-h723zg/configs/nsh/defconfig | 2 +- .../nucleo-h723zg/configs/oa_tc6/defconfig | 2 +- .../configs/mcuboot-app/defconfig | 2 +- .../configs/mcuboot-loader/defconfig | 2 +- .../configs/nxboot-app/defconfig | 2 +- .../configs/nxboot-loader/defconfig | 2 +- .../nucleo-n657x0-q/configs/leds/defconfig | 2 +- 54 files changed, 14729 insertions(+), 11967 deletions(-) create mode 100644 arch/arm/src/common/stm32/Kconfig.adc create mode 100644 arch/arm/src/common/stm32/Kconfig.ble create mode 100644 arch/arm/src/common/stm32/Kconfig.cache create mode 100644 arch/arm/src/common/stm32/Kconfig.can create mode 100644 arch/arm/src/common/stm32/Kconfig.comp create mode 100644 arch/arm/src/common/stm32/Kconfig.dac create mode 100644 arch/arm/src/common/stm32/Kconfig.dfsdm create mode 100644 arch/arm/src/common/stm32/Kconfig.dma create mode 100644 arch/arm/src/common/stm32/Kconfig.dts create mode 100644 arch/arm/src/common/stm32/Kconfig.eth create mode 100644 arch/arm/src/common/stm32/Kconfig.fdcan create mode 100644 arch/arm/src/common/stm32/Kconfig.flash create mode 100644 arch/arm/src/common/stm32/Kconfig.foc create mode 100644 arch/arm/src/common/stm32/Kconfig.gpio create mode 100644 arch/arm/src/common/stm32/Kconfig.have create mode 100644 arch/arm/src/common/stm32/Kconfig.hciuart create mode 100644 arch/arm/src/common/stm32/Kconfig.hrtim create mode 100644 arch/arm/src/common/stm32/Kconfig.i2c create mode 100644 arch/arm/src/common/stm32/Kconfig.ipcc create mode 100644 arch/arm/src/common/stm32/Kconfig.lpuart create mode 100644 arch/arm/src/common/stm32/Kconfig.ltdc create mode 100644 arch/arm/src/common/stm32/Kconfig.memory create mode 100644 arch/arm/src/common/stm32/Kconfig.periph create mode 100644 arch/arm/src/common/stm32/Kconfig.qspi create mode 100644 arch/arm/src/common/stm32/Kconfig.rtc create mode 100644 arch/arm/src/common/stm32/Kconfig.sai create mode 100644 arch/arm/src/common/stm32/Kconfig.sdadc create mode 100644 arch/arm/src/common/stm32/Kconfig.sdio create mode 100644 arch/arm/src/common/stm32/Kconfig.spi create mode 100644 arch/arm/src/common/stm32/Kconfig.system create mode 100644 arch/arm/src/common/stm32/Kconfig.tim create mode 100644 arch/arm/src/common/stm32/Kconfig.uart create mode 100644 arch/arm/src/common/stm32/Kconfig.usb diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index d3255a5e8ca5c..d88f092dd4599 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -378,7 +378,7 @@ file and in that case those operations are not performed: * ``note_register()`` - Registers the standard ``/dev/note``. * ``arm_serialinit()`` - Initialize the **standard** serial driver - (found at ``nuttx/arch/arm/src/stm32/stm32_serial.c`` STM32 F4). + (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_usart_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 633bd210f96f5..1b0211bdd166d 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -2,18 +2,9 @@ # Common STM32 Kconfig options shared by STM32 families. # -menu "Common STM32 Configuration Options" +menu "STM32 Configuration Options" depends on ARCH_CHIP_STM32 -config STM32_SERIALDRIVER - bool - -config STM32_1WIREDRIVER - bool - -config STM32_HCIUART - bool - config STM32_COMMON_LEGACY bool default y if ARCH_CHIP_STM32F1 @@ -80,9460 +71,147 @@ config STM32_COMMON_USART_UNCONFIG_ON_CLOSE default y if ARCH_CHIP_STM32H5 default y if ARCH_CHIP_STM32N6 -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - - -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice -choice - prompt "Select TIM1 ADC channel" - depends on STM32_TIM1_ADC - default STM32_TIM1_ADC1 - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice -choice - prompt "Select TIM2 ADC channel" - depends on STM32_TIM2_ADC - default STM32_TIM2_ADC1 - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice -choice - prompt "Select TIM3 ADC channel" - depends on STM32_TIM3_ADC - default STM32_TIM3_ADC1 - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice -choice - prompt "Select TIM4 ADC channel" - depends on STM32_TIM4_ADC - default STM32_TIM4_ADC1 - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice -choice - prompt "Select TIM5 ADC channel" - depends on STM32_TIM5_ADC - default STM32_TIM5_ADC1 - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice -choice - prompt "Select TIM8 ADC channel" - depends on STM32_TIM8_ADC - default STM32_TIM8_ADC1 - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice -choice - prompt "Select TIM1 DAC channel" - depends on STM32_TIM1_DAC - default STM32_TIM1_DAC1 - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice -choice - prompt "Select TIM2 DAC channel" - depends on STM32_TIM2_DAC - default STM32_TIM2_DAC1 - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice -choice - prompt "Select TIM3 DAC channel" - depends on STM32_TIM3_DAC - default STM32_TIM3_DAC1 - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice -choice - prompt "Select TIM4 DAC channel" - depends on STM32_TIM4_DAC - default STM32_TIM4_DAC1 - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice -choice - prompt "Select TIM5 DAC channel" - depends on STM32_TIM5_DAC - default STM32_TIM5_DAC1 - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice -choice - prompt "Select TIM6 DAC channel" - depends on STM32_TIM6_DAC - default STM32_TIM6_DAC1 - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice -choice - prompt "Select TIM7 DAC channel" - depends on STM32_TIM7_DAC - default STM32_TIM7_DAC1 - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice -choice - prompt "Select TIM8 DAC channel" - depends on STM32_TIM8_DAC - default STM32_TIM8_DAC1 - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice -choice - prompt "Select TIM9 DAC channel" - depends on STM32_TIM9_DAC - default STM32_TIM9_DAC1 - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice -choice - prompt "Select TIM10 DAC channel" - depends on STM32_TIM10_DAC - default STM32_TIM10_DAC1 - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice -choice - prompt "Select TIM11 DAC channel" - depends on STM32_TIM11_DAC - default STM32_TIM11_DAC1 - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice -choice - prompt "Select TIM12 DAC channel" - depends on STM32_TIM12_DAC - default STM32_TIM12_DAC1 - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice -choice - prompt "Select TIM13 DAC channel" - depends on STM32_TIM13_DAC - default STM32_TIM13_DAC1 - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice -choice - prompt "Select TIM14 DAC channel" - depends on STM32_TIM14_DAC - default STM32_TIM14_DAC1 - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice -choice - prompt "USART1 Driver Configuration" - depends on STM32_USART1 - default STM32_USART1_SERIALDRIVER - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration -choice - prompt "USART2 Driver Configuration" - depends on STM32_USART2 - default STM32_USART2_SERIALDRIVER - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration -choice - prompt "USART3 Driver Configuration" - depends on STM32_USART3 - default STM32_USART3_SERIALDRIVER - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration -choice - prompt "UART4 Driver Configuration" - depends on STM32_UART4 - default STM32_UART4_SERIALDRIVER - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration -choice - prompt "UART5 Driver Configuration" - depends on STM32_UART5 - default STM32_UART5_SERIALDRIVER - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration -choice - prompt "USART6 Driver Configuration" - depends on STM32_USART6 - default STM32_USART6_SERIALDRIVER - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration -choice - prompt "LPUART1 Driver Configuration" - depends on STM32_LPUART1 - default STM32_LPUART1_SERIALDRIVER - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -choice - prompt "USART4 Driver Configuration" - depends on STM32_USART4 - default STM32_USART4_SERIALDRIVER - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -choice - prompt "USART5 Driver Configuration" - depends on STM32_USART5 - default STM32_USART5_SERIALDRIVER - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -choice - prompt "USART7 Driver Configuration" - depends on STM32_USART7 - default STM32_USART7_SERIALDRIVER - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -choice - prompt "USART8 Driver Configuration" - depends on STM32_USART8 - default STM32_USART8_SERIALDRIVER - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -choice - prompt "UART7 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART7 - default STM32_UART7_SERIALDRIVER - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. +source "arch/arm/src/common/stm32/Kconfig.have" -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors +source "arch/arm/src/common/stm32/Kconfig.periph" -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART8 - default STM32_UART8_SERIALDRIVER - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART -choice - prompt "RTC clock source" - depends on STM32_RTC - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source -choice - prompt "MII clock configuration" - depends on STM32_MII - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_MII_EXTCLK - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice -choice - prompt "RMII clock configuration" - depends on STM32_RMII - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_RMII_EXTCLK - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 +menu "ADC Configuration" + depends on STM32_ADC +source "arch/arm/src/common/stm32/Kconfig.adc" +endmenu # ADC Configuration -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] +menu "SDADC Configuration" + depends on STM32_SDADC +source "arch/arm/src/common/stm32/Kconfig.sdadc" +endmenu # SDADC Configuration -endchoice +menu "Cache Configuration" +source "arch/arm/src/common/stm32/Kconfig.cache" +endmenu # Cache Configuration -choice - prompt "CAN character driver or SocketCAN support" +menu "CAN Configuration" depends on STM32_CAN - default STM32_CAN_CHARDRIVER - -config STM32_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support +source "arch/arm/src/common/stm32/Kconfig.can" +endmenu # CAN Configuration -choice - prompt "FDCAN character driver or SocketCAN support" +menu "FDCAN Configuration" depends on STM32_FDCAN - default STM32_FDCAN_CHARDRIVER - -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -if STM32_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 - -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC - -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 - -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -endif # STM32_FDCAN2 -choice - prompt "Layer 1 color format" +source "arch/arm/src/common/stm32/Kconfig.fdcan" +endmenu # FDCAN Configuration + +menu "DAC Configuration" + depends on STM32_DAC +source "arch/arm/src/common/stm32/Kconfig.dac" +endmenu # DAC Configuration + +menu "DFSDM Configuration" + depends on STM32_DFSDM1 || STM32_MDF1 || STM32_ADF1 +source "arch/arm/src/common/stm32/Kconfig.dfsdm" +endmenu # DFSDM Configuration + +menu "DMA Configuration" + depends on STM32_DMA || STM32_DMA2D +source "arch/arm/src/common/stm32/Kconfig.dma" +endmenu # DMA Configuration + +menu "Ethernet Configuration" + depends on STM32_ETHMAC +source "arch/arm/src/common/stm32/Kconfig.eth" +endmenu # Ethernet Configuration + +menu "Flash Configuration" +source "arch/arm/src/common/stm32/Kconfig.flash" +endmenu # Flash Configuration + +menu "FOC Configuration" + depends on STM32_HAVE_COMMON_FOC +source "arch/arm/src/common/stm32/Kconfig.foc" +endmenu # FOC Configuration + +menu "GPIO Configuration" +source "arch/arm/src/common/stm32/Kconfig.gpio" +endmenu # GPIO Configuration + +menu "I2C Configuration" + depends on STM32_I2C +source "arch/arm/src/common/stm32/Kconfig.i2c" +endmenu # I2C Configuration + +menu "IPCC Configuration" + depends on STM32_IPCC || STM32_HAVE_HSEM +source "arch/arm/src/common/stm32/Kconfig.ipcc" +endmenu # IPCC Configuration + +menu "BLE Configuration" + depends on STM32_BLE || STM32_MBOX +source "arch/arm/src/common/stm32/Kconfig.ble" +endmenu # BLE Configuration + +menu "LTDC Configuration" depends on STM32_LTDC - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format -choice - prompt "Layer 2 (top layer) color format" - depends on STM32_LTDC && STM32_LTDC_L2 - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_LTDC_L1_L8 - -config STM32_LTDC_L2_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_LTDC_L1_AL44 +source "arch/arm/src/common/stm32/Kconfig.ltdc" +endmenu # LTDC Configuration -config STM32_LTDC_L2_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_LTDC_L1_AL88 +menu "Memory Configuration" +source "arch/arm/src/common/stm32/Kconfig.memory" +endmenu # Memory Configuration -config STM32_LTDC_L2_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 +menu "QSPI/OCTOSPI Configuration" + depends on STM32_QSPI || STM32_QSPI1 || STM32_OCTOSPI1 || STM32_OCTOSPI2 +source "arch/arm/src/common/stm32/Kconfig.qspi" +endmenu # QSPI/OCTOSPI Configuration -config STM32_LTDC_L2_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - -config STM32_LTDC_L2_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB1555 - -config STM32_LTDC_L2_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - -config STM32_LTDC_L2_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - -endchoice # Layer 2 color format -choice - prompt "Input channel sampling frequency" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_FDTS_4 - - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice -choice - prompt "Input channel event count" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_EVENT_6 - - -config STM32_QENCODER_SAMPLE_EVENT_1 - bool "1" - depends on STM32_QENCODER_SAMPLE_FDTS - -config STM32_QENCODER_SAMPLE_EVENT_2 - bool "2" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_4 - bool "4" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_5 - bool "5" - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - -config STM32_QENCODER_SAMPLE_EVENT_6 - bool "6" - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_8 - bool "8" - depends on !STM32_QENCODER_SAMPLE_FDTS - -endchoice -choice - prompt "FOC ADC trigger selection" - depends on STM32_FOC - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" -choice - prompt "FOC0 device ADC selection" - depends on STM32_FOC_FOC0 - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" -choice - prompt "FOC1 device ADC selection" - depends on STM32_FOC_FOC1 - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - -config STM32_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32_FLASH_OVERRIDE_I - bool "I 2048KiB" - -config STM32_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # Override Flash Size Designator -choice - prompt "Select TIM15 ADC channel" - depends on STM32_TIM15_ADC - default STM32_TIM15_ADC1 - -config STM32_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice -choice - prompt "Transfer technique" - depends on STM32_QSPI - default STM32_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - - -config STM32_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32_QSPI_DMA - bool "DMA" - depends on STM32_DMA - ---help--- - Use DMA to improve QSPI transfer performance. +menu "RTC Configuration" + depends on STM32_RTC +source "arch/arm/src/common/stm32/Kconfig.rtc" +endmenu # RTC Configuration -endchoice -choice - prompt "Bank selection" - depends on STM32_QSPI - default STM32_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. +menu "SAI Configuration" +source "arch/arm/src/common/stm32/Kconfig.sai" +endmenu # SAI Configuration +menu "SDIO/SDMMC Configuration" + depends on STM32_SDIO || STM32_SDMMC +source "arch/arm/src/common/stm32/Kconfig.sdio" +endmenu # SDIO/SDMMC Configuration -config STM32_QSPI_MODE_BANK1 - bool "Bank 1" +menu "COMP Configuration" + depends on STM32_COMP +source "arch/arm/src/common/stm32/Kconfig.comp" +endmenu # COMP Configuration -config STM32_QSPI_MODE_BANK2 - bool "Bank 2" +menu "DTS Configuration" + depends on STM32_DTS +source "arch/arm/src/common/stm32/Kconfig.dts" +endmenu # DTS Configuration -config STM32_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice -choice - prompt "DMA Priority" - depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA - default STM32_QSPI_DMAPRIORITY_MEDIUM - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - - -config STM32_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32_DMA - ---help--- - 'Highest' priority. - -config STM32_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32_DMA - ---help--- - 'High' priority. - -config STM32_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32_DMA - ---help--- - 'Medium' priority. - -config STM32_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32_DMA - ---help--- - 'Low' priority. - -endchoice -choice - prompt "Operation mode" - depends on STM32_SAI - default STM32_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - - -config STM32_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode -choice - prompt "SAI1 synchronization enable" - depends on STM32_SAI1_A && STM32_SAI1_B - default STM32_SAI1_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - - -config STM32_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable -choice - prompt "SAI2 synchronization enable" - depends on STM32_SAI2_A && STM32_SAI2_B - default STM32_SAI2_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - - -config STM32_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable -choice - prompt "Select ADC for use with TIM6" - depends on STM32_TIM6_ADC - default STM32_TIM6_ADC1 - -config STM32_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice -choice - prompt "LPTIM1 clock source" - default STM32_LPTIM1_CLK_APB1 - -config STM32_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" - -endchoice -choice - prompt "LPTIM2 clock source" - default STM32_LPTIM2_CLK_APB1 - -config STM32_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" - -endchoice - - -config STM32_TIM_PWM_COMMON - bool - default y if STM32_COMMON_FULL_FEATURED - -config STM32_TIM_PWM_NO_F0_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_TIM_PWM_ADVANCED_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_SINGLECHAN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_INTERNAL_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 - -config STM32_TIM_PWM_STM32PWM_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - -config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - bool - default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_CHMODE_LEGACY_COMMON - bool - default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 - -config STM32_TIM_PWM_CHMODE_LIMITED_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_ADC_TIMTRIG_TRGO2_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 - -config STM32_ADC_TIMTRIG_TRGO_COMMON - bool - default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 - -config STM32_PWM_MULTICHAN_L5_TIMERS - bool - default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM - default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM - default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM - default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM - default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS - -config STM32_SPI_CORE_DMA_CAPABLE - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 - default y if STM32_COMMON_F7_H7_H5 - default y if ARCH_CHIP_STM32WL5 - default y if STM32_COMMON_L4_L5_U5 && STM32_SPI - default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA - -config STM32_SPI_DMA_FAMILY_WL5 - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 - -config STM32_SPI_DMA_FAMILY - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 - -config STM32_RTC_MAGIC_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC - default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC - -config STM32_ADC1_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC1_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER - default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC2_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER - -config STM32_ADC2_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER - -config STM32_ADC3_TIMER_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER - -config STM32_QENCODER_TIMS_1_4 - bool - default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_QENCODER_TIMS_1_8 - bool - default y if STM32_QENCODER_TIMS_1_4 - default y if STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_MAIN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 - default y if STM32_COMMON_L4_L5_U5 - -config STM32_QENCODER_MAIN - bool - default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_STM32 - bool - default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_F0 - bool - default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 - -config STM32_QENCODER_16BIT_CAPABLE - bool - default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 - -config STM32_LPTIM1_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM1_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM2_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_LPTIM2_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_ADC1_DFSDM_L4_CHIP - bool - default y if STM32_STM32L496XX || STM32_STM32L4XR - -config STM32_ADC1_DFSDM_L5_CHIP - bool - default y if STM32_STM32L596XX || STM32_STM32L5XR - -config STM32_ADC1_DFSDM_U5_CHIP - bool - default y if STM32_STM32U596XX || STM32_STM32U5XR - -config STM32_ADC1_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP - -config STM32_ADC2_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX - -config STM32_ADC3_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX - - -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - -config STM32_ENERGYLITE - bool - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - -config STM32_VALUELINE - bool - select STM32_HAVE_USART3 if STM32_COMMON_LEGACY - select STM32_HAVE_UART4 if STM32_COMMON_LEGACY - select STM32_HAVE_UART5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY - select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 - select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 - -config STM32_DFU - bool "DFU bootloader" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -# These hidden settings determine whether a peripheral option is available -# for the selected MCU. Family Kconfigs select these from chip data. - -config STM32_HAVE_AES - bool - -config STM32_HAVE_CRYP - bool - -config STM32_HAVE_CCM - bool - -config STM32_HAVE_DMAMUX - bool - -config STM32_HAVE_USBDEV - bool - -config STM32_HAVE_USBFS - bool - -config STM32_HAVE_OTGFS - bool - -config STM32_HAVE_FMC - bool - -config STM32_HAVE_FSMC - bool - -config STM32_HAVE_SYSCFG - bool - -config STM32_HAVE_FDCAN1 - bool - -config STM32_HAVE_FDCAN2 - bool - -config STM32_HAVE_FDCAN3 - bool - -config STM32_HAVE_LTDC - bool - -config STM32_HAVE_USART2 - bool - -config STM32_HAVE_USART3 - bool - -config STM32_HAVE_UART4 - bool - -config STM32_HAVE_UART5 - bool - -config STM32_HAVE_USART6 - bool - -config STM32_HAVE_UART7 - bool - -config STM32_HAVE_UART8 - bool - -config STM32_HAVE_TIM1 - bool - -config STM32_HAVE_TIM2 - bool - -config STM32_HAVE_TIM3 - bool - -config STM32_HAVE_TIM4 - bool - -config STM32_HAVE_TIM5 - bool - -config STM32_HAVE_TIM6 - bool - -config STM32_HAVE_TIM7 - bool - -config STM32_HAVE_TIM8 - bool - -config STM32_HAVE_TIM9 - bool - -config STM32_HAVE_TIM10 - bool - -config STM32_HAVE_TIM11 - bool - -config STM32_HAVE_TIM12 - bool - -config STM32_HAVE_TIM13 - bool - -config STM32_HAVE_TIM14 - bool - -config STM32_HAVE_TIM15 - bool - -config STM32_HAVE_TIM16 - bool - -config STM32_HAVE_TIM17 - bool - -config STM32_HAVE_TSC - bool - -config STM32_HAVE_ADC2 - bool - -config STM32_HAVE_ADC3 - bool - -config STM32_HAVE_ADC4 - bool - -config STM32_HAVE_ADC5 - bool - -config STM32_HAVE_ADC1_DMA - bool - -config STM32_HAVE_ADC2_DMA - bool - -config STM32_HAVE_ADC3_DMA - bool - -config STM32_HAVE_ADC4_DMA - bool - -config STM32_HAVE_ADC5_DMA - bool - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_HAVE_CAN1 - bool - -config STM32_HAVE_CAN2 - bool - -config STM32_HAVE_CAN3 - bool - -config STM32_HAVE_COMP1 - bool - -config STM32_HAVE_COMP2 - bool - -config STM32_HAVE_COMP3 - bool - -config STM32_HAVE_COMP4 - bool - -config STM32_HAVE_COMP5 - bool - -config STM32_HAVE_COMP6 - bool - -config STM32_HAVE_COMP7 - bool - -config STM32_HAVE_CRS - bool - -config STM32_HAVE_CEC - bool - -config STM32_HAVE_CORDIC - bool - -config STM32_HAVE_DSIHOST - bool - -config STM32_HAVE_JPEG - bool - -config STM32_HAVE_INTERNAL_ULPI - bool - -config STM32_HAVE_EXTERNAL_ULPI - bool - -config STM32_HAVE_HRTIM1 - bool - -config STM32_HAVE_HRTIM1_PLLCLK - bool - -config STM32_HAVE_TIM18 - bool - -config STM32_HAVE_TIM19 - bool - -config STM32_HAVE_TIM20 - bool - -config STM32_HAVE_SDADC1 - bool - -config STM32_HAVE_SDADC2 - bool - -config STM32_HAVE_SDADC3 - bool - -config STM32_HAVE_SDADC1_DMA - bool - -config STM32_HAVE_SDADC2_DMA - bool - -config STM32_HAVE_SDADC3_DMA - bool - -config STM32_HAVE_SDIO - bool - -config STM32_HAVE_UCPD1 - bool - -config STM32_HAVE_UCPD2 - bool - -config STM32_HAVE_RTC_COUNTER - bool - -config STM32_HAVE_IP_DBGMCU_V1 - bool - -config STM32_HAVE_IP_DBGMCU_V2 - bool - -config STM32_HAVE_IP_DBGMCU_V3 - bool - -config STM32_HAVE_IP_I2C_V1 - bool - -config STM32_HAVE_IP_I2C_V2 - bool - -config STM32_HAVE_IP_DMA_V1 - bool - -config STM32_HAVE_IP_DMA_V2 - bool - -config STM32_HAVE_IP_TIMERS_V1 - bool - -config STM32_HAVE_IP_TIMERS_V2 - bool - -config STM32_HAVE_IP_TIMERS_V3 - bool - -config STM32_HAVE_IP_ADC_V1 - bool - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - -config STM32_HAVE_IP_COMP_V2 - bool - -config STM32_HAVE_IP_DAC_V1 - bool - -config STM32_HAVE_IP_DAC_V2 - bool - -config STM32_HAVE_IP_USART_V1 - bool - -config STM32_HAVE_IP_USART_V2 - bool - -config STM32_HAVE_IP_EXTI_V1 - bool - -config STM32_HAVE_IP_EXTI_V2 - bool - -config STM32_HAVE_FMAC - bool - -config STM32_HAVE_FLASH_ICACHE - bool - -config STM32_HAVE_FLASH_DCACHE - bool - -config STM32_HAVE_OVERDRIVE - bool - -config STM32_HAVE_DMA1_CHAN8 - bool - -config STM32_HAVE_DMA2_CHAN678 - bool - -config STM32_HAVE_UCPD - bool - -config STM32_HAVE_DAC1 - bool - -config STM32_HAVE_DAC2 - bool - -config STM32_HAVE_DAC3 - bool - -config STM32_HAVE_DAC4 - bool - -config STM32_HAVE_QSPI - bool - -config STM32_HAVE_RNG - bool - -config STM32_HAVE_VREFINT - bool - -config STM32_HAVE_I2C1 - bool - -config STM32_HAVE_I2C2 - bool - -config STM32_HAVE_I2C3 - bool - -config STM32_HAVE_I2C4 - bool - -config STM32_HAVE_SDMMC1 - bool - -config STM32_HAVE_SDMMC2 - bool - -config STM32_HAVE_LPTIM1 - bool - -config STM32_HAVE_LPUART1 - bool - -config STM32_HAVE_LPUART2 - bool - -config STM32_HAVE_SPI1 - bool - -config STM32_HAVE_SPI2 - bool - -config STM32_HAVE_SPI3 - bool - -config STM32_HAVE_I2S3 - bool - -config STM32_HAVE_I2S2 - bool - -config STM32_HAVE_SPI2S2 - bool - -config STM32_HAVE_SPI4 - bool - -config STM32_HAVE_SPI5 - bool - -config STM32_HAVE_SPI6 - bool - -config STM32_HAVE_SAIPLL - bool - -config STM32_HAVE_I2SPLL - bool - -config STM32_HAVE_OPAMP1 - bool - -config STM32_HAVE_OPAMP2 - bool - -config STM32_HAVE_OPAMP3 - bool - -config STM32_HAVE_OPAMP4 - bool - -config STM32_HAVE_OPAMP5 - bool - -config STM32_HAVE_OPAMP6 - bool - -config STM32_HAVE_IOCOMPENSATION - bool - -config STM32_HAVE_ICACHE - bool - -config STM32_HAVE_ETHMAC - bool - -config STM32_HAVE_ETHRNET - bool - -config STM32_HAVE_LPUART - bool - -config STM32_HAVE_SAI - bool - -config STM32_HAVE_USB - bool - -config STM32_GPIO_HAVE_PORTD - bool - -config STM32_GPIO_HAVE_PORTE - bool - -config STM32_HAVE_GPIOF - bool - -config STM32_HAVE_GPIOG - bool - -config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - -config STM32_HAVE_OTA_PARTITION - bool - -config STM32_HAVE_CM4 - bool - -config STM32_HAVE_USART4 - bool - -config STM32_HAVE_USART5 - bool - -config STM32_HAVE_USART7 - bool - -config STM32_HAVE_USART8 - bool - -config STM32_HAVE_UART9 - bool - -config STM32_HAVE_USART10 - bool - -config STM32_HAVE_USART11 - bool - -config STM32_HAVE_UART12 - bool - -config STM32_HAVE_ADC1 - bool - default y if STM32_COMMON_LEGACY - -config STM32_ADC1 - bool "ADC1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - select STM32_ADC if !ARCH_CHIP_STM32U5 - select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC2 - bool "ADC2" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 - select STM32_ADC - select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC3 - bool "ADC3" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 - select STM32_ADC - select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC4 - bool "ADC4" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 - select STM32_ADC if STM32_COMMON_LEGACY - select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) - -config STM32_COMP1 - bool "COMP1" - depends on STM32_HAVE_COMP1 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - depends on STM32_HAVE_COMP2 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 - -config STM32_CORDIC - bool "CORDIC Accelerator" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 - -config STM32_BKP - bool "BKP" - depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select STM32_PWR if ARCH_CHIP_STM32H7 - -config STM32_CAN1 - bool "CAN1" - depends on STM32_HAVE_CAN1 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN2 - bool "CAN2" - depends on STM32_HAVE_CAN2 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN3 - bool "CAN3" - depends on STM32_HAVE_CAN3 - select STM32_CAN - select CAN - -config STM32_AES - bool "128-bit AES" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 - select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 - -config STM32_CRC - bool "CRC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB - -config STM32_CRS - bool "CRS (Clock Recovery System)" - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMA2 - bool "DMA2" - depends on STM32_HAVE_DMA2 - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMAMUX1 - bool "DMAMUX1" - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - depends on STM32_HAVE_DAC1 - select STM32_DAC if !ARCH_CHIP_STM32U5 - -config STM32_DAC2 - bool "DAC2" - depends on STM32_HAVE_DAC2 - select STM32_DAC - -config STM32_DCMI - bool "DCMI" - depends on STM32_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32_DSIHOST - bool "DSIHOST" - depends on STM32_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI DSI - compliant displays. - -config STM32_ETHMAC - bool "Ethernet MAC" - depends on STM32_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY - -config STM32_FDCAN1 - bool "FDCAN1" - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN if !ARCH_CHIP_STM32U5 - -config STM32_FDCAN2 - bool "FDCAN2" - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - depends on STM32_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - depends on STM32_HAVE_HASH - select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH - -config STM32_JPEG - bool "JPEG" - depends on STM32_HAVE_JPEG - ---help--- - The JPEG codec provides a hardware compressor and decompressor of JPEG - images with full management of JPEG headers. - -config STM32_I2C1 - bool "I2C1" - depends on STM32_HAVE_I2C1 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB - -config STM32_I2C2 - bool "I2C2" - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - depends on STM32_HAVE_I2C3 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 - -config STM32_LPTIM1 - bool "LPTIM1" - depends on STM32_HAVE_LPTIM1 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPUART1 - bool "LPUART1" - depends on STM32_HAVE_LPUART1 - select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY - select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART - -config STM32_VREFINT - bool "Enable VREFINT" - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - depends on STM32_HAVE_USART8 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - depends on STM32_HAVE_LTDC - select FB - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - depends on STM32_HAVE_DMA2D - select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - -config STM32_RTC - bool "RTC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB - select RTC if !ARCH_CHIP_STM32L5 - -config STM32_OTGFS - bool "OTG FS" - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGHS - bool "OTG HS" - depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGFSHS - bool "OTG FS/HS" - depends on ARCH_CHIP_STM32F7 - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32_PWR - bool "PWR" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -config STM32_RNG - bool "RNG" - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 - -config STM32_SDIO - bool "SDIO" - depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - depends on STM32_HAVE_SPI1 - select SPI if !ARCH_CHIP_STM32WL5 - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S1 - bool "I2S1" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 - select STM32_I2S - -config STM32_I2S2 - bool "I2S2" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 - select STM32_I2S - -config STM32_I2S3 - bool "I2S3" - depends on STM32_HAVE_I2S3 - select I2S if STM32_COMMON_LEGACY - select STM32_I2S - -config STM32_SPI2S2 - bool "SPI2S2" - depends on STM32_HAVE_SPI2S2 - select STM32_SPI - -config STM32_SPDIFRX - bool "SPDIFRX" - depends on ARCH_CHIP_STM32F7 - -config STM32_SPI4 - bool "SPI4" - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - depends on STM32_HAVE_SYSCFG - default y - -config STM32_TIM1 - bool "TIM1" - depends on STM32_HAVE_TIM1 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM2 - bool "TIM2" - depends on STM32_HAVE_TIM2 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM3 - bool "TIM3" - depends on STM32_HAVE_TIM3 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM4 - bool "TIM4" - depends on STM32_HAVE_TIM4 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM5 - bool "TIM5" - depends on STM32_HAVE_TIM5 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM6 - bool "TIM6" - depends on STM32_HAVE_TIM6 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM7 - bool "TIM7" - depends on STM32_HAVE_TIM7 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM8 - bool "TIM8" - depends on STM32_HAVE_TIM8 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM9 - bool "TIM9" - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - depends on STM32_HAVE_TIM15 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM16 - bool "TIM16" - depends on STM32_HAVE_TIM16 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM17 - bool "TIM17" - depends on STM32_HAVE_TIM17 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TSC - bool "TSC" - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - depends on STM32_HAVE_USART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART2 - bool "USART2" - depends on STM32_HAVE_USART2 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART3 - bool "USART3" - depends on STM32_HAVE_USART3 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART4 - bool "UART4" - depends on STM32_HAVE_UART4 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART5 - bool "UART5" - depends on STM32_HAVE_UART5 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART6 - bool "USART6" - depends on STM32_HAVE_USART6 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART7 - bool "UART7" - depends on STM32_HAVE_UART7 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART8 - bool "UART8" - depends on STM32_HAVE_UART8 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USB - bool "USB Device" - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - depends on STM32_HAVE_USBFS - select USBDEV - select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 - -config STM32_LCD - bool "Segment LCD" - depends on STM32_HAVE_LCD - select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD - -config STM32_IWDG - bool "IWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select WATCHDOG if !ARCH_CHIP_STM32U5 - -config STM32_ADC - bool - -config STM32_DAC - bool - -config STM32_DMA - bool - select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - select STM32_DMAMUX if ARCH_CHIP_STM32WB - -config STM32_DMAMUX - bool - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool "SPI DMA" - depends on STM32_SPI_CORE_DMA_CAPABLE - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_I2S - bool - select STM32_SPI_DMA if STM32_COMMON_LEGACY - select STM32_SPI_DMA if ARCH_CHIP_STM32F7 - -config STM32_I2C - bool - -config STM32_CAN - bool - -config STM32_FDCAN - bool - select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 - select NET_CAN_EXTID if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 - -config STM32_TIM - bool - -config STM32_PWM - bool - -config STM32_COMP - bool "COMP" - depends on STM32_HAVE_COMP - select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP - -config STM32_OPAMP - bool "OPAMP" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - depends on STM32_HAVE_IOCOMPENSATION - select STM32_CSI if ARCH_CHIP_STM32H7 - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY - default y - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) - select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) - select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 2 - range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - depends on STM32_ONESHOT - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default 1 - range 1 8 - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - depends on STM32_TIM1 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM1_MODE - int "TIM1 Mode" - depends on STM32_TIM1_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - depends on STM32_TIM1_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - depends on STM32_TIM2 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM2_MODE - int "TIM2 Mode" - depends on STM32_TIM2_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - depends on STM32_TIM2_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - depends on STM32_TIM3 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM3_MODE - int "TIM3 Mode" - depends on STM32_TIM3_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - depends on STM32_TIM3_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_PWM - bool "TIM4 PWM" - depends on STM32_TIM4 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM4_MODE - int "TIM4 Mode" - depends on STM32_TIM4_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - depends on STM32_TIM4_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_PWM - bool "TIM5 PWM" - depends on STM32_TIM5 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM5_MODE - int "TIM5 Mode" - depends on STM32_TIM5_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - depends on STM32_TIM5_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_PWM - bool "TIM8 PWM" - depends on STM32_TIM8 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM8_MODE - int "TIM8 Mode" - depends on STM32_TIM8_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - depends on STM32_TIM8_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_PWM - bool "TIM9 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 2. - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) - ---help--- - Enables channel 2 output. - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_PWM - bool "TIM10 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - depends on STM32_TIM10_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_PWM - bool "TIM11 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - depends on STM32_TIM11_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_PWM - bool "TIM12 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_PWM - bool "TIM13 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - depends on STM32_TIM13_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_PWM - bool "TIM14 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - depends on STM32_TIM14_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_PWM - bool "TIM15 PWM" - depends on STM32_TIM15 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 - depends on STM32_TIM_PWM_SINGLECHAN_COMMON - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_PWM - bool "TIM16 PWM" - depends on STM32_TIM16 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - depends on STM32_TIM16_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_PWM - bool "TIM17 PWM" - depends on STM32_TIM17 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - depends on STM32_TIM17_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - depends on STM32_PWM_MULTICHAN_CAPABLE - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PULSECOUNT - bool - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - depends on STM32_TIM1 - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - depends on STM32_TIM8 - depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) - ---help--- - Enable TRGO support for PWM driver - -config STM32_TIM1_ADC - bool "TIM1 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM2_ADC - bool "TIM2 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM3_ADC - bool "TIM3 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM4_ADC - bool "TIM4 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM5_ADC - bool "TIM5 ADC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM8_ADC - bool "TIM8 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - depends on STM32_ADC1_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - depends on STM32_ADC1_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - depends on STM32_ADC2_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - depends on STM32_ADC2_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - depends on STM32_ADC3_TIMER_CAPABLE - default 100 - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM2_DAC - bool "TIM2 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM3_DAC - bool "TIM3 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM4_DAC - bool "TIM4 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM5_DAC - bool "TIM5 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM6_DAC - bool "TIM6 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM7_DAC - bool "TIM7 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM8_DAC - bool "TIM8 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM9_DAC - bool "TIM9 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM10_DAC - bool "TIM10 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM11_DAC - bool "TIM11 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM12_DAC - bool "TIM12 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM13_DAC - bool "TIM13 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM14_DAC - bool "TIM14 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM1_CAP - bool "TIM1 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM2_CAP - bool "TIM2 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM3_CAP - bool "TIM3 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM4_CAP - bool "TIM4 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM5_CAP - bool "TIM5 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM8_CAP - bool "TIM8 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM9_CAP - bool "TIM9 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM10_CAP - bool "TIM10 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM11_CAP - bool "TIM11 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CAP - bool "TIM12 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM13_CAP - bool "TIM13 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM14_CAP - bool "TIM14 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output IDLE - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - depends on STM32_ADC - default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - depends on STM32_ADC - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - depends on STM32_ADC - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - depends on STM32_ADC - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2x - 1 -> 4x - 2 -> 8x - ... - 7 -> 256x - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) - default STM32_ADC1_DMA - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) - default STM32_ADC2_DMA - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) - default STM32_ADC3_DMA - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 0 - range 0 4 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 0 - range 0 4 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 0 - range 0 4 - ---help--- - Support for ADC3 injected channels. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER - ---help--- - Enable EXTSEL for ADC3. - -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - ---help--- - Enable JEXTSEL for ADC3. - -config STM32_USART - bool - -config USART1_RS485 - bool "RS-485 on USART1" - depends on STM32_USART1 && USART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -if USART1_RS485 - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART1_RS485 - -config USART1_RXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART2_RS485 - bool "RS-485 on USART2" - depends on STM32_USART2 && USART2_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -if USART2_RS485 - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART2_RS485 - -config USART2_RXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART3_RS485 - bool "RS-485 on USART3" - depends on STM32_USART3 && USART3_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -if USART3_RS485 - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART3_RS485 - -config USART3_RXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART4_RS485 - bool "RS-485 on UART4" - depends on STM32_UART4 && UART4_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -if UART4_RS485 - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART4_RS485 - -config UART4_RXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART5_RS485 - bool "RS-485 on UART5" - depends on STM32_UART5 && UART5_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -if UART5_RS485 - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART5_RS485 - -config UART5_RXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART6_RS485 - bool "RS-485 on USART6" - depends on STM32_USART6 && USART6_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -if USART6_RS485 - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART6_RS485 - -config USART6_RXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART7_RS485 - bool "RS-485 on UART7" - depends on STM32_UART7 && UART7_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -if UART7_RS485 - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART7_RS485 - -config UART7_RXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART8_RS485 - bool "RS-485 on UART8" - depends on STM32_UART8 && UART8_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -if UART8_RS485 - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART8_RS485 - -config UART8_RXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -if LPUART1_RS485 - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # LPUART1_RS485 - -config LPUART1_RXDMA - bool - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - depends on STM32_USART && SERIAL_RXDMA - range 32 4096 - default 32 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32_USART - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32_USART - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32_USART - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - depends on PM - depends on STM32_USART - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure LPUART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART2 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART3 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART4 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART5 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART6 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART7 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART8 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART9 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART10 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART11 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART12 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - depends on STM32_SPI - depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - depends on STM32_SPI && STM32_SPI1 - depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA - default 4 - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - depends on STM32_SPI && STM32_SPI2 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - depends on STM32_SPI && STM32_SPI3 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA - bool "SPI2S2 DMA" - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with - STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -config STM32_I2S3_DATALEN - int "Data width (bits)" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -config STM32_I2S1_MCK - bool "I2S1_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - TBD. - -config STM32_I2S1_RX - bool "Enable I2S1 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S receipt logic - -config STM32_I2S1_TX - bool "Enable I2S1 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S transmission logic - -config STM32_I2S1_DATALEN - int "I2S1 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S2_MCK - bool "I2S2_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - TBD. - -config STM32_I2S2_RX - bool "Enable I2S2 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S receipt logic - -config STM32_I2S2_TX - bool "Enable I2S2 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S transmission logic - -config STM32_I2S2_DATALEN - int "I2S2 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S3_MCK - bool "I2S3_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S3 - ---help--- - TBD. - -#if STM32_I2S - -config STM32_I2S3_RX - bool "Enable I2S receiver" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 1000 - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - default 0 - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_BBSRAM - bool "BBSRAM File Support" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM - select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - -config STM32_RTC_MAGIC_REG - int "BKP register" - depends on STM32_RTC_MAGIC_CAPABLE - default 0 - range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -if STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - ---help--- - Support Ethernet MII interface. - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -if !STM32_AUTONEG - -config STM32_ETHFD - bool "Full duplex" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -endif # !STM32_AUTONEG - -if STM32_AUTONEG - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -if !STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -endif # !STM32_PHYSR_ALTCONFIG - -if STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -endif # STM32_PHYSR_ALTCONFIG - -endif # STM32_AUTONEG - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - depends on STM32_COMMON_LEGACY - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endif # STM32_ETHMAC - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Dump all incoming and outgoing USB packets. - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -menu "STM32_OTG_HS Configuration" - depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32_NO_ULPI - -config STM32_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS - -endchoice # "ULPI Selection" - -endmenu # STM32_OTG_HS Configuration - -menu "OTG_HS Configuration" - depends on ARCH_CHIP_STM32H7 && STM32_OTGHS - -config STM32_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32_OTGHS_NO_ULPI - -config STM32_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means - the OTG_HS peripheral must use the internal full-speed PHY and will - be limited to full-speed mode. - -config STM32_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice # "ULPI Selection" - -endmenu # OTG_HS Configuration - -menu "OTG Configuration" - depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - -choice - prompt "STM32H7 OTGFS role" - depends on STM32_OTGFS - default STM32_OTGFS_USBDEV if USBDEV - default STM32_OTGFS_HOST if !USBDEV && USBHOST - -config STM32_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32_OTGHS - default STM32_OTGHS_USBDEV if USBDEV - -config STM32_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB FS Host Configuration - -menu "USB HS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB HS Host Configuration - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - depends on STM32_CAN1 - default 250000 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - depends on STM32_CAN2 - default 250000 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN3_BAUD - int "CAN3 BAUD" - depends on STM32_CAN3 - default 250000 - ---help--- - CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - depends on STM32_CAN - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - depends on STM32_CAN - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on STM32_CAN && DEBUG_CAN_INFO - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_REGDEBUG - bool "FDCAN register-level debug" - depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - depends on STM32_FDCAN - -config STM32_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - -choice - prompt "FDCAN Loopback Mode" - depends on STM32_FDCAN_LOOPBACK - default STM32_FDCAN_LOOPBACK_INTERNAL - -config STM32_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default STM32_FDCAN_LPWORK - -config STM32_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -if STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -config STM32_FDCAN1_BITRATE - int "FDCAN1 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 nominal bit timing" - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN1_AUTO_BIT_TIMING - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - default 2000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 data bit timing" - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -config STM32_FDCAN2_BITRATE - int "FDCAN2 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 nominal bit timing" - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN2_AUTO_BIT_TIMING - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - default 2000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 data bit timing" - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -endif # STM32_FDCAN2 - -if STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -config STM32_FDCAN3_BITRATE - int "FDCAN3 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -comment "FDCAN3 nominal bit timing" - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - default 2000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN3_FD_BRS - -comment "FDCAN3 data bit timing" - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN3_FD_BRS - -endif # STM32_FDCAN3 - -if STM32_LTDC - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - -config STM32_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - depends on ARCH_CHIP_STM32H7 - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while - the display is being refreshed. This configuration requires two - framebuffers: one active and one inactive. When the display - refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -if STM32_LTDC_DITHER - -config STM32_LTDC_DITHER_RED - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -endif # STM32_LTDC_DITHER - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - depends on STM32_FB_CMAP - default y - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 - ---help--- - Output detailed register-level LTDC device debug information. - -endif # STM32_LTDC - -if STM32_DMA2D - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -config STM32_DMA2D_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - default y - -config STM32_DMA2D_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - default y - -config STM32_DMA2D_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - ---help--- - Output detailed register-level DMA2D device debug information. - -endif # STM32_DMA2D - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_TIM1_QE - bool "TIM1 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QE - bool "TIM2 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QE - bool "TIM3 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QE - bool "TIM4 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM5_QE - bool "TIM5 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM5 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM5_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM8_QE - bool "TIM8 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM8 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM8_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - select STM32_ADC1 - select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - select STM32_ADC2 - select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - select STM32_ADC3 - select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - -config STM32_PROGMEM - bool "Flash PROGMEM support" - depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 - select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -config STM32_HAVE_HSI48 - bool - -config STM32_HAVE_LCD - bool - -config STM32_HAVE_DMA2 - bool - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM15_ADC - bool "TIM15 ADC" - depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_IO_CONFIG_R - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_V - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_I - bool - -config STM32_IO_CONFIG_Z - bool - -config STM32_IO_CONFIG_B - bool - -config STM32_IO_CONFIG_A - bool - -config STM32_HAVE_PHY_POLLED - bool - -config STM32_HAVE_DCMI - bool - -config STM32_HAVE_DMA2D - bool - -config STM32_HAVE_HASH - bool - -config STM32_HAVE_DFSDM1 - bool - -config STM32_HAVE_SAI1 - bool - -config STM32_HAVE_SAI2 - bool - -config STM32_SAI - bool - -menu "SDIO Configuration" - depends on STM32_COMMON_LEGACY && STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDIO Configuration - -config STM32_SDMMC - bool - -config STM32_DFSDM1 - bool "DFSDM1" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 - -config STM32_I2C4 - bool "I2C4" - depends on STM32_HAVE_I2C4 - select STM32_I2C - -config STM32_QUADSPI - bool "QuadSPI" - depends on STM32_COMMON_F7_H7 - -config STM32_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - depends on STM32_COMMON_F7_H7 && USBDEV - -config STM32_SAI1 - bool "SAI1" - depends on STM32_HAVE_SAI1 - -config STM32_SAI1_A - bool "SAI1 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI1_B - bool "SAI1 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2 - bool "SAI2" - depends on STM32_HAVE_SAI2 - -config STM32_SAI2_A - bool "SAI2 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2_B - bool "SAI2 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SDMMC1 - bool "SDMMC1" - depends on STM32_HAVE_SDMMC1 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 - select SCHED_HPWORK if ARCH_CHIP_STM32L4 - select STM32_SAI1PLL if ARCH_CHIP_STM32L4 - -config STM32_SDMMC2 - bool "SDMMC2" - depends on STM32_HAVE_SDMMC2 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 - -config STM32_SDMMC_IDMA - bool "Support IDMA data transfers" - depends on ARCH_CHIP_STM32H7 && STM32_SDMMC - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -config STM32_USART_INVERT - bool "Signal Invert Support" - depends on STM32_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32_USART_SWAP - bool "Swap RX/TX pins support" +menu "U[S]ART Configuration" depends on STM32_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -config STM32_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 16777216 - range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 4 - range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - default 1 - range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -config STM32_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA - default 4 - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -config STM32_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -if STM32_SDMMC - -config STM32_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32_SDMMC_DMA - bool "Support DMA data transfers" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA - select SDIO_DMA - ---help--- - Support DMA data transfers. - -config STM32_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 - default 0x00010000 if ARCH_CHIP_STM32F7 - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - depends on STM32_SDMMC1 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endif # STM32_SDMMC - -config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - depends on STM32_COMMON_F7_H7 - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM - default LIBC_ARCH_ELF - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -config STM32_PHY_POLLING - bool "Support network monitoring by polling the PHY" - depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32_LTDC_USE_DSI - bool "Use DSI as display connection" - depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32_HAVE_SMPS - bool - -config STM32_HAVE_ETHERNET - bool - -config STM32_LPTIM - bool - -config STM32_LPTIM2 - bool "LPTIM2" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPTIM3 - bool "LPTIM3" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM4 - bool "LPTIM4" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM5 - bool "LPTIM5" - depends on ARCH_CHIP_STM32H7 - select STM32_LPTIM - -config STM32_SPI4_COMMTYPE - int "SPI4 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI5_COMMTYPE - int "SPI5 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI6_COMMTYPE - int "SPI6 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_TIM6_ADC - bool "TIM6 ADC" - depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIMX_CAP - bool "Helpers for Capture Drivers" - depends on ARCH_CHIP_STM32H7 - default n - -config STM32_TIM15_CAP - bool "TIM15 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM15 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -config STM32_TIM16_CAP - bool "TIM16 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM16 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -config STM32_TIM17_CAP - bool "TIM17 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM17 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -config STM32_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CAP - bool "LPTIM1 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -config STM32_LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM2_CAP - bool "LPTIM2 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -config STM32_LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32_LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32_LPTIM3_CAP - bool "LPTIM3 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -config STM32_LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32_LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM4_CAP - bool "LPTIM4 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -config STM32_LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32_LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM5_CAP - bool "LPTIM5 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -config STM32_LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32_LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_ETH_NRXDESC - int "Number of RX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32_ETH_NTXDESC - int "Number of TX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32_NO_PHY - bool "MAC has no PHY" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - -config STM32_IO_CONFIG_K - bool - -config STM32_IO_CONFIG_T - bool - -config STM32_IO_CONFIG_C - bool - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_J - bool - -config STM32_IO_CONFIG_M - bool - -config STM32_IO_CONFIG_Q - bool - -config STM32_SRAM2_HEAP - bool "SRAM2 is used for heap" - depends on STM32_COMMON_SRAM2_OPTIONS - select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_SRAM2_INIT - bool "SRAM2 is initialized to zero" - depends on STM32_COMMON_SRAM2_OPTIONS - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) - default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_HAVE_COMP - bool - -config STM32_HAVE_USART1 - bool - -config STM32_SAI1PLL - bool "SAI1PLL" - depends on STM32_COMMON_L4_L5_U5 - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_SAI2PLL - bool "SAI2PLL" - depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT - default 2 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32_TICKLESS_FREERUN - int "Tickless free-running timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN - default 5 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -config STM32_LPTIM1_PWM - bool "LPTIM1 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM2_PWM - bool "LPTIM2 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - depends on STM32_LPTIM1_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - depends on STM32_LPTIM1_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - depends on STM32_LPTIM2_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - depends on STM32_LPTIM2_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -config STM32_DAC1_DMA - bool "DAC1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC1_TIMER - int "DAC1 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - range 2 8 - -config STM32_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 1 - -config STM32_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32_DAC2_DMA - bool "DAC2 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC2_TIMER - int "DAC2 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 0 - range 2 8 - -config STM32_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 1 - -config STM32_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -config STM32_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_IPCC - bool "IPCC" - depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 - select IPCC if ARCH_CHIP_STM32WL5 - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -config STM32_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the receive buffer. Another CPU will write to this buffer and - the currently running CPU will read from it. - -config STM32_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the send buffer. Another CPU will read from this buffer and - the currently running CPU will write to it. - -config STM32_IPCC_CHAN2 - bool "Enable channel 2" - depends on STM32_IPCC - -if STM32_IPCC_CHAN2 - -config STM32_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32_IPCC_CHAN3 - bool "Enable channel 3" - -if STM32_IPCC_CHAN3 - -config STM32_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32_IPCC_CHAN4 - bool "Enable channel 4" - -if STM32_IPCC_CHAN4 - -config STM32_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32_IPCC_CHAN5 - bool "Enable channel 5" - -if STM32_IPCC_CHAN5 - -config STM32_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32_IPCC_CHAN6 - bool "Enable channel 6" - -if STM32_IPCC_CHAN6 - -config STM32_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32_IPCC_CHAN2 -endif # STM32_IPCC_CHAN3 -endif # STM32_IPCC_CHAN4 -endif # STM32_IPCC_CHAN5 -endif # STM32_IPCC_CHAN6 +source "arch/arm/src/common/stm32/Kconfig.uart" +endmenu # U[S]ART Configuration + +menu "SPI/I2S Configuration" + depends on STM32_SPI || STM32_I2S +source "arch/arm/src/common/stm32/Kconfig.spi" +endmenu # SPI/I2S Configuration + +menu "System Configuration" +source "arch/arm/src/common/stm32/Kconfig.system" +endmenu # System Configuration + +menu "Timer Configuration" + depends on STM32_TIM || STM32_LPTIM +source "arch/arm/src/common/stm32/Kconfig.tim" +endmenu # Timer Configuration + +menu "HRTIM Configuration" + depends on STM32_HRTIM +source "arch/arm/src/common/stm32/Kconfig.hrtim" +endmenu # HRTIM Configuration + +menu "USB Configuration" + depends on STM32_USB || STM32_USBFS || STM32_OTGFS || STM32_OTGHS || STM32_OTGFSHS +source "arch/arm/src/common/stm32/Kconfig.usb" +endmenu # USB Configuration endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/common/stm32/Kconfig.adc b/arch/arm/src/common/stm32/Kconfig.adc new file mode 100644 index 0000000000000..afd9427f034f7 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.adc @@ -0,0 +1,990 @@ +# +# STM32 common ADC options. +# + +# STM32 ADC configuration options. + +# TODO: The options below are a special case for the legacy family-local +# stm32l4_adc.c driver (selected by STM32_HAVE_ADC_L4). They must be migrated +# to the common ADC interface used by stm32_adc_m3m4_v1v2.c (STM32_ADCx_EXTSEL / +# STM32_ADCx_JEXTSEL / STM32_ADCx_INJECTED_CHAN) and removed from here. + +# ADC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_ADC1_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC1_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7) && STM32_ADC1_HAVE_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC2_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_ADC2_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC2_HAVE_TIMER + +config STM32_ADC3_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC3_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC3_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC3_HAVE_TIMER + +config STM32_ADC1_HAVE_DMA + bool + default y if STM32_STM32C0 + default y if STM32_STM32F0 + default y if STM32_STM32F30XX + default y if STM32_STM32F33XX + default y if STM32_F7_PERIPHERALS + default y if STM32_STM32G0 + default y if STM32_STM32L0 + +config STM32_ADC2_HAVE_DMA + bool + default y if STM32_STM32F302 + default y if STM32_STM32F303 + default y if STM32_STM32F33XX + default y if STM32_F7_PERIPHERALS + +config STM32_ADC3_HAVE_DMA + bool + default y if STM32_F7_PERIPHERALS + +config STM32_ADC4_HAVE_DMA + bool + +config STM32_ADC5_HAVE_DMA + bool + +config STM32_ADC4_HAVE_TIMER + bool + +config STM32_ADC5_HAVE_TIMER + bool + +config STM32_ADC1_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP + +config STM32_ADC2_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC3_HAVE_OUTPUT_DFSDM + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC1_HAVE_TIMER + bool + +config STM32_ADC2_HAVE_TIMER + bool + +config STM32_ADC3_HAVE_TIMER + bool + +menu "STM32L4 ADC Configuration" + depends on STM32_HAVE_ADC_L4 && STM32_ADC + +config STM32_ADC_SMPR + int "ADC sample time" + default 0 + range 0 7 + ---help--- + ADC sample time + 0 - 2.5 ADC clock cycles + 1 - 6.5 ADC clock cycles + 2 - 12.5 ADC clock cycles + 3 - 24.5 ADC clock cycles + 4 - 47.5 ADC clock cycles + 5 - 92.5 ADC clock cycles + 6 - 247.5 ADC clock cycles + 7 - 640.5 ADC clock cycles + +config STM32_ADC1_INJ_CHAN + int "ADC1 configured injected channels" + depends on STM32_ADC1 + range 0 4 + default 0 + ---help--- + Number of configured ADC1 injected channels. + +config STM32_ADC2_INJ_CHAN + int "ADC2 configured injected channels" + depends on STM32_ADC2 + range 0 4 + default 0 + ---help--- + Number of configured ADC2 injected channels. + +config STM32_ADC3_INJ_CHAN + int "ADC3 configured injected channels" + depends on STM32_ADC3 + range 0 4 + default 0 + ---help--- + Number of configured ADC3 injected channels. + +menu "STM32L4 ADCx triggering Configuration" + +config STM32_ADC1_EXTTRIG + int "ADC1 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_EXTTRIG > 0 + +config STM32_ADC_L4_ADC1_EXTSEL + int "ADC1 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC2_EXTTRIG + int "ADC2 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_EXTTRIG > 0 + +config STM32_ADC_L4_ADC2_EXTSEL + int "ADC2 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC3_EXTTRIG + int "ADC3 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_EXTTRIG > 0 + +config STM32_ADC_L4_ADC3_EXTSEL + int "ADC3 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +if STM32_ADC1_INJ_CHAN > 0 + +config STM32_ADC1_JEXTTRIG + int "ADC1 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC1_JEXTSEL + int "ADC1 External Trigger Selection for injected group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC2_INJ_CHAN > 0 + +config STM32_ADC2_JEXTTRIG + int "ADC2 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC2_JEXTSEL + int "ADC2 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC3_INJ_CHAN > 0 + +config STM32_ADC3_JEXTTRIG + int "ADC3 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC3_JEXTSEL + int "ADC3 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +endmenu #STM32L4 ADCx triggering Configuration + +endmenu + +menu "ADC Configuration" + depends on STM32_HAVE_ADC_H5 && STM32_ADC + +config STM32_ADC1_OVERSAMPLE + bool "Enable ADC1 hardware oversampling support" + depends on STM32_ADC1 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC1_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC1_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_WDG1 + bool "Enable STM32H5 ADC1 Watchdog 1" + depends on STM32_ADC1 + default n + ---help--- + Enable STM32H5 ADC1 Watchdog 1. + +config STM32_ADC1_WDG1_FLT + int "Set ADC1 Watchdog 1 Filter" + depends on STM32_ADC1_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC1_WDG1_LOWTHRESH + int "Set ADC1 Watchdog 1 Low Threshold" + depends on STM32_ADC1_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC1_WDG1_HIGHTHRESH + int "Set ADC1 Watchdog 1 High Threshold" + depends on STM32_ADC1_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC1_WDG1_SGL + bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" + depends on STM32_ADC1_WDG1 + default n + ---help--- + This option determines if ADC1 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC1_WDG1_CHAN + int "STM32H5 ADC1 Watchdog 1 Channel Selection" + depends on STM32_ADC1_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC1 Watchdog 1. + +config STM32_ADC2_OVERSAMPLE + bool "Enable ADC2 hardware oversampling support" + depends on STM32_ADC2 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC2_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC2_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_WDG1 + bool "Enable STM32H5 ADC2 Watchdog 1" + depends on STM32_ADC2 + default n + ---help--- + Enable STM32H5 ADC2 Watchdog 1. + +config STM32_ADC2_WDG1_FLT + int "Set ADC2 Watchdog 1 Filter" + depends on STM32_ADC2_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC2_WDG1_LOWTHRESH + int "Set ADC2 Watchdog 1 Low Threshold" + depends on STM32_ADC2_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC2_WDG1_HIGHTHRESH + int "Set ADC2 Watchdog 1 High Threshold" + depends on STM32_ADC2_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC2_WDG1_SGL + bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" + depends on STM32_ADC2_WDG1 + default n + ---help--- + This option determines if ADC2 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC2_WDG1_CHAN + int "STM32H5 ADC2 Watchdog 1 Channel Selection" + depends on STM32_ADC2_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC2 Watchdog 1. + +endmenu # ADC Configuration + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_HAVE_TIMTRIG + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_HAVE_TIMTRIG && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_HAVE_IP_ADC_M0_V1 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_ADC1_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_ADC2_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_ADC3_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_ADC1_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_ADC2_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_ADC3_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_HAVE_OUTPUT_DFSDM + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC4_DMA + bool "ADC4 DMA" + depends on STM32_ADC4 && STM32_ADC4_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC4_DMA_CFG + int "ADC4 DMA configuration" + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode + +config STM32_ADC4_DMA_BATCH + int "ADC4 DMA number of conversions" + depends on STM32_ADC4 && STM32_ADC4_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_ANIOC_TRIGGER + int "ADC4 software trigger (ANIOC_TRIGGER) configuration" + depends on STM32_ADC4 + range 1 3 + default 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_ADC5_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode + +config STM32_ADC5_DMA_BATCH + int "ADC5 DMA number of conversions" + depends on STM32_ADC5 && STM32_ADC5_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_INJECTED_CHAN + int "ADC4 injected channels" + depends on STM32_ADC4 + range 0 4 + default 0 + ---help--- + Support for ADC4 injected channels. + +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. + +config STM32_ADC4_EXTSEL + bool "ADC4 external trigger for regular group" + depends on STM32_ADC4 && !STM32_ADC4_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC4. + +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_ADC5_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC5. + +config STM32_ADC4_JEXTSEL + bool "ADC4 external trigger for injected group" + depends on STM32_ADC4 + default n + ---help--- + Enable JEXTSEL for ADC4. + +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n + ---help--- + Enable JEXTSEL for ADC5. + +config STM32_ADC1_CONTINUOUS + bool "Enable ADC1 Continuous Conversion Mode" + default n + depends on STM32_ADC1 && STM32_HAVE_IP_ADC_M0_V1 + ---help--- + If enabled, the ADC will operate in continuous conversion mode. + Otherwise, it will perform single conversions. + Note: Continuous and discontinuous mode cannot be defined at + the same time diff --git a/arch/arm/src/common/stm32/Kconfig.ble b/arch/arm/src/common/stm32/Kconfig.ble new file mode 100644 index 0000000000000..dd91f1fe66233 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ble @@ -0,0 +1,221 @@ +# +# STM32 common BLE options. +# + +if STM32_BLE + +config STM32_BLE_C2HOST + bool "Enable CPU2 HOST stack" + default n + ---help--- + The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and + control it using vendor ACL protocol. However, it is not expected to enable + this option in the current implementation. + +config STM32_BLE_MAX_CONN + int "Maximum BLE simultaneous connections" + range 1 8 + default 2 + +config STM32_BLE_GATT_MAX_ATTR_NUM + int "GATT attributes max count" + range 9 255 + default 64 + +config STM32_BLE_GATT_MAX_SVC_NUM + int "GATT services max count" + range 2 64 + default 8 + +config STM32_BLE_GATT_ATTR_BUF_SIZE + int "GATT attributes storage buf size" + default 1344 + ---help--- + Size of the storage area for attribute values. Hardcoded in CPU2 firmware. + +config STM32_BLE_DLE + bool "Support Data Length Extension (DLE)" + default y + +config STM32_BLE_MAX_ATT_MTU + int "Maximum supported attribute MTU" + range 23 512 + default 156 + +config STM32_BLE_SLAVE_SCA + int "Sleep clock accuracy in slave mode [PPM]" + default 500 + ---help--- + Sleep clock accuracy (ppm value) in slave mode. + +choice + prompt "Sleep clock accuracy in master mode" + default STM32_BLE_MASTER_SCA_0 + ---help--- + Sleep clock accuracy in master mode. + +config STM32_BLE_MASTER_SCA_0 + bool "251-500 ppm" + +config STM32_BLE_MASTER_SCA_1 + bool "151-250 ppm" + +config STM32_BLE_MASTER_SCA_2 + bool "101-150 ppm" + +config STM32_BLE_MASTER_SCA_3 + bool "76-100 ppm" + +config STM32_BLE_MASTER_SCA_4 + bool "51-75 ppm" + +config STM32_BLE_MASTER_SCA_5 + bool "31-50 ppm" + +config STM32_BLE_MASTER_SCA_6 + bool "21-30 ppm" + +config STM32_BLE_MASTER_SCA_7 + bool "0-20 ppm" + +endchoice # Sleep clock accuracy in master mode + +config STM32_BLE_MASTER_SCA + int + default 7 if STM32_BLE_MASTER_SCA_7 + default 6 if STM32_BLE_MASTER_SCA_6 + default 5 if STM32_BLE_MASTER_SCA_5 + default 4 if STM32_BLE_MASTER_SCA_4 + default 3 if STM32_BLE_MASTER_SCA_3 + default 2 if STM32_BLE_MASTER_SCA_2 + default 1 if STM32_BLE_MASTER_SCA_1 + default 0 + +choice + prompt "Low speed clock source" + default STM32_BLE_LS_CLK_SRC_LSE + ---help--- + Low speed 32 kHz clock source. + +config STM32_BLE_LS_CLK_SRC_LSE + bool "LSE" + +config STM32_BLE_LS_CLK_SRC_HSE + bool "HSE" + +endchoice # Low speed clock source + +config STM32_BLE_LS_CLK_SRC + int + default 1 if STM32_BLE_LS_CLKSRC_HSE + default 0 + +config STM32_BLE_MAX_CONN_EVT_LENGTH + hex "Max connection event length" + default 0xffffffff + ---help--- + Maximum duration of a slave connection event in units of 625/256us (~2.44us). + +config STM32_BLE_HSE_STARTUP + hex "HSE startup time" + default 0x148 + ---help--- + HSE startup time in units of 625/256us (~2.44us). + +config STM32_BLE_VITERBI + bool "Enable Viterbi algorithm" + default y + ---help--- + Enable Viterbi algorithm implementation + +config STM32_BLE_MAX_INITOR_COC_NUM + int "Max number of connection-oriented channels" + range 0 64 + default 32 + ---help--- + Maximum number of connection-oriented channels in initiator mode. + +config STM32_BLE_SVC_CHANGED_CHAR + bool "Enable service changed characteristic" + default n + +config STM32_BLE_WRITABLE_DEVICE_NAME + bool "Writable device name" + default y + +config STM32_BLE_CHAN_SEL_ALG2 + bool "Enable channel selection algorithm 2" + default n + +choice + prompt "Power class" + default STM32_BLE_POWER_CLASS_2_3 + +config STM32_BLE_POWER_CLASS_2_3 + bool "Power Class 2-3" + +config STM32_BLE_POWER_CLASS_1 + bool "Power Class 1" + +endchoice # Power class + +config STM32_BLE_MIN_TX_POWER + int "Minimum transmit power [dBm]" + range -127 20 + default 0 + +config STM32_BLE_MAX_TX_POWER + int "Maximum transmit power [dBm]" + range -127 20 + default 0 + +choice + prompt "AGC RSSI model" + default STM32_BLE_AGC_RSSI_LEGACY + +config STM32_BLE_AGC_RSSI_LEGACY + bool "AGC RSSI Legacy" + +config STM32_BLE_AGC_RSSI_IMPROVED + bool "AGC RSSI Improved" + +endchoice # AGC RSSI model + +config STM32_BLE_ADVERTISING + bool "Support advertising" + default y + +config STM32_BLE_SCANNING + bool "Support scanning" + default y + +config STM32_BLE_LE_2M_PHY + bool "Support LE 2M PHY" + default y + +config STM32_BLE_LE_CODED_PHY + bool "Support LE Coded PHY" + default STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + depends on STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + +config STM32_BLE_FICR_STATIC_ADDR + bool "Configure factory generated static random address" + default n + +config STM32_BLE_PUB_ADDR + hex "Configure BT public address" + default 0x0000000000 + +endif # STM32_BLE + +if STM32_MBOX + +config STM32_MBOX_TX_CMD_QUEUE_LEN + int "Mailbox TX command queue length" + default 2 + +config STM32_MBOX_RX_EVT_QUEUE_LEN + int "Mailbox RX event queue length" + default 5 + +endif # STM32_MBOX diff --git a/arch/arm/src/common/stm32/Kconfig.cache b/arch/arm/src/common/stm32/Kconfig.cache new file mode 100644 index 0000000000000..c9ebbd5e29104 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.cache @@ -0,0 +1,240 @@ +# +# STM32 common CACHE options. +# + +# STM32 cache configuration options. + +menu "ICACHE Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_MONITOR_EN + bool "Enable ICACHE Hit/Miss Counters" + default n + +config STM32_ICACHE_DIRECT + bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" + default n + +menu "ICACHE Interrupt Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_INV_INT + bool "Enable interrupts on full invalidation completion." + default n + +config STM32_ICACHE_ERR_INT + bool "Enable interrupts on occurrences of cache errors." + default n + +endmenu # ICACHE Interrupt Configuration + +menu "ICACHE Region Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_REGION0 + bool "Enable Configuration of ICACHE Region 0" + default n + +config STM32_ICACHE_REGION1 + bool "Enable Configuration of ICACHE Region 1" + default n + +config STM32_ICACHE_REGION2 + bool "Enable Configuration of ICACHE Region 2" + default n + +config STM32_ICACHE_REGION3 + bool "Enable Configuration of ICACHE Region 3" + default n + +menu "Region 0 Configuration" + depends on STM32_ICACHE_REGION0 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION0_BADDR + hex "ICACHE Region 0 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 0. + +config STM32_ICACHE_REGION0_RSIZE + int "ICACHE Region 0 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION0 + ---help--- + Set the size of Region 0. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION0_REMAPADDR + hex "ICACHE Region 0 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [31:21] of ICACHE Region 0 Remap Address.. + +config STM32_ICACHE_REGION0_MSTSEL + int "ICACHE Region 0 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select ICACHE Region 0 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION0_HBURST + int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 0 Configuration + +menu "Region 1 Configuration" + depends on STM32_ICACHE_REGION1 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION1_BADDR + hex "ICACHE Region 1 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 1. + +config STM32_ICACHE_REGION1_RSIZE + int "ICACHE Region 1 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION1 + ---help--- + Set the size of Region 1. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION1_REMAPADDR + hex "ICACHE Region 1 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [31:21] of ICACHE Region 1 Remap Address.. + +config STM32_ICACHE_REGION1_MSTSEL + int "ICACHE Region 1 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select ICACHE Region 1 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION1_HBURST + int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 1 Configuration + +menu "Region 2 Configuration" + depends on STM32_ICACHE_REGION2 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION2_BADDR + hex "ICACHE Region 2 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 2. + +config STM32_ICACHE_REGION2_RSIZE + int "ICACHE Region 2 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION2 + ---help--- + Set the size of Region 2. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION2_REMAPADDR + hex "ICACHE Region 2 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [31:21] of ICACHE Region 2 Remap Address.. + +config STM32_ICACHE_REGION2_MSTSEL + int "ICACHE Region 2 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select ICACHE Region 2 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION2_HBURST + int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 2 Configuration + +menu "Region 3 Configuration" + depends on STM32_ICACHE_REGION3 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION3_BADDR + hex "ICACHE Region 3 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 3. + +config STM32_ICACHE_REGION3_RSIZE + int "ICACHE Region 3 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION3 + ---help--- + Set the size of Region 3. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION3_REMAPADDR + hex "ICACHE Region 3 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [31:21] of ICACHE Region 3 Remap Address.. + +config STM32_ICACHE_REGION3_MSTSEL + int "ICACHE Region 3 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select ICACHE Region 3 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION3_HBURST + int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 3 Configuration + +endmenu # ICACHE Region Configuration + +endmenu # ICACHE Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.can b/arch/arm/src/common/stm32/Kconfig.can new file mode 100644 index 0000000000000..c12794cb03fc4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.can @@ -0,0 +1,63 @@ +# +# STM32 common CAN options. +# + +# STM32 CAN configuration options. + +choice + prompt "CAN character driver or SocketCAN support" + depends on STM32_CAN + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + depends on STM32_CAN + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + depends on STM32_CAN + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on STM32_CAN && DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.comp b/arch/arm/src/common/stm32/Kconfig.comp new file mode 100644 index 0000000000000..7ab482fe729eb --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.comp @@ -0,0 +1,402 @@ +# +# STM32 common COMP options. +# + +# STM32 analog comparator (COMP) configuration options. + +menu "COMP Configuration" + depends on STM32_COMP && STM32_HAVE_IP_COMP_M3M4_V2 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + depends on STM32_COMP1 + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + depends on STM32_COMP1 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + depends on STM32_COMP1 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + depends on STM32_COMP2 + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + depends on STM32_COMP2 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + depends on STM32_COMP2 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + depends on STM32_COMP3 + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + depends on STM32_COMP3 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + depends on STM32_COMP3 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + depends on STM32_COMP4 + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + depends on STM32_COMP4 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + depends on STM32_COMP4 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + depends on STM32_COMP5 + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + depends on STM32_COMP5 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + depends on STM32_COMP5 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + depends on STM32_COMP6 + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + depends on STM32_COMP6 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + depends on STM32_COMP6 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + depends on STM32_COMP7 + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX && STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + depends on STM32_COMP7 + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + depends on STM32_COMP7 + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dac b/arch/arm/src/common/stm32/Kconfig.dac new file mode 100644 index 0000000000000..7e0d65af6f8ba --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dac @@ -0,0 +1,366 @@ +# +# STM32 common DAC options. +# + +# STM32 DAC configuration options. + +config STM32_DAC_LL_OPS + bool "DAC low-level operations" + depends on STM32_DAC + default n + ---help--- + Enable low-level DAC ops. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 1 + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 1 + +menu "DAC Configuration" + depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 + +config STM32_DAC1CH1_MODE + int "DAC1CH1 channel mode" + depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH1_DMA + bool "DAC1CH1 DMA" + depends on STM32_DAC1CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH1_DMA + +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 + +config STM32_DAC1CH1_DMA_EXTERNAL + bool "DAC1CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH1_HRTIM_TRG1 + bool "DAC1CH1 HRTIM Trigger 1" + default n + +config STM32_DAC1CH1_HRTIM_TRG2 + bool "DAC1CH1 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH1_TIMER + int "DAC1CH1 timer" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH1_TIMER_FREQUENCY + int "DAC1CH1 timer frequency" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC1CH2_MODE + int "DAC1CH2 channel mode" + depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH2_DMA + bool "DAC1CH2 DMA" + depends on STM32_DAC1CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH2_DMA + +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 + +config STM32_DAC1CH2_DMA_EXTERNAL + bool "DAC1CH2 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH2_HRTIM_TRG1 + bool "DAC1CH2 HRTIM Trigger 1" + default n + +config STM32_DAC1CH2_HRTIM_TRG2 + bool "DAC1CH2 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH2_TIMER + int "DAC1CH2 timer" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH2_TIMER_FREQUENCY + int "DAC1CH2 timer frequency" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC2CH1_MODE + int "DAC2CH1 channel mode" + depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC2CH1_DMA + bool "DAC2CH1 DMA" + depends on STM32_DAC2CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC2CH1_DMA + +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 + +config STM32_DAC2CH1_DMA_EXTERNAL + bool "DAC2CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC2CH1_HRTIM_TRG3 + bool "DAC2CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC2CH1_TIMER + int "DAC2CH1 timer" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC2CH1_TIMER_FREQUENCY + int "DAC2CH1 timer frequency" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH1_MODE + int "DAC3CH1 channel mode" + depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH1_DMA + bool "DAC3CH1 DMA" + depends on STM32_DAC3CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH1_DMA + +config STM32_DAC3CH1_DMA_BUFFER_SIZE + int "DAC3CH1 DMA buffer size" + default 256 + +config STM32_DAC3CH1_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH1_HRTIM_TRG3 + bool "DAC3CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH1_TIMER + int "DAC3CH1 timer" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH1_TIMER_FREQUENCY + int "DAC3CH1 timer frequency" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH2_MODE + int "DAC3CH2 channel mode" + depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH2_DMA + bool "DAC3CH2 DMA" + depends on STM32_DAC3CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH2_DMA + +config STM32_DAC3CH2_DMA_BUFFER_SIZE + int "DAC3CH2 DMA buffer size" + default 256 + +config STM32_DAC3CH2_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH2_HRTIM_TRG3 + bool "DAC3CH2 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH2_TIMER + int "DAC3CH2 timer" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH2_TIMER_FREQUENCY + int "DAC3CH2 timer frequency" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + +endif + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dfsdm b/arch/arm/src/common/stm32/Kconfig.dfsdm new file mode 100644 index 0000000000000..d29507d1707ab --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dfsdm @@ -0,0 +1,45 @@ +# +# STM32 common DFSDM options. +# + +# STM32 digital filter configuration options. + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.dma b/arch/arm/src/common/stm32/Kconfig.dma new file mode 100644 index 0000000000000..e4cd1add7ae65 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dma @@ -0,0 +1,123 @@ +# +# STM32 common DMA options. +# + +# STM32 DMA configuration options. + +# DMA per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_DMA1_HAVE_CHAN8 + bool + default y if STM32_STM32G47XX + +config STM32_DMA2_HAVE_CHAN678 + bool + default y if STM32_STM32G47XX + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. diff --git a/arch/arm/src/common/stm32/Kconfig.dts b/arch/arm/src/common/stm32/Kconfig.dts new file mode 100644 index 0000000000000..7ed7e0622c8a4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dts @@ -0,0 +1,101 @@ +# +# STM32 common DTS options. +# + +# STM32 Digital Temperature Sensor (DTS) configuration options. + +config STM32_DTS_REFCLK_LSE + bool "Use LSE (32.768 kHz crystal) as DTS reference clock" + default n + ---help--- + Select the low‑speed external (LSE) oscillator as the reference clock + for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will + measure FM(T) pulses over N LSE cycles. + + If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference + (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the + calibration prescaler ≤ 1 MHz. + +config STM32_DTS_SMP_TIME + int "DTS sampling time (TS1_SMP_TIME[3:0])" + default 1 + range 1 15 + ---help--- + Number of reference‑clock cycles (PCLK or LSE) counted per + DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). + +config STM32_DTS_TRIGGER + int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" + default 0 + ---help--- + If non‑zero, DTS will start measurements on the rising edge of + the selected hardware line. Values match RM0481 Table 275: + 0=Software Trigger, 1=LPTIM1_CH1,  + 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. + +config STM32_DTS_LOW_THRESHOLD + int "DTS low‑threshold (°C)" + default 0 + ---help--- + The temperature (in whole °C) below which the DTS window comparator will + assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0. + +config STM32_DTS_HIGH_THRESHOLD + int "DTS high‑threshold (°C)" + default 100 + ---help--- + The temperature (in whole °C) above which the DTS window comparator will + assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. + +config STM32_DTS_ITEN_ITEF + bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)" + default y + ---help--- + Enable the synchronous “end of measurement” interrupt for the + digital temperature sensor. When set, the driver will attach + and unmask TS1_ITEF and will call your ISR on every fresh sample. + +config STM32_DTS_ITEN_ITLF + bool "Enable DTS low‑threshold interrupt (TS1_ITLF)" + default n + ---help--- + Enable the synchronous “low threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITLF so you can get notified whenever the measured value + drops below your programmed low‑threshold. + +config STM32_DTS_ITEN_ITHF + bool "Enable DTS high‑threshold interrupt (TS1_ITHF)" + default n + ---help--- + Enable the synchronous “high threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITHF so you can get notified whenever the measured value + exceeds your programmed high‑threshold. + +config STM32_DTS_AITEN_AITEF + bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous end‑of‑measurement interrupt. This will + set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup + event when a conversion completes (in Stop/Sleep modes). + +config STM32_DTS_AITEN_AITLF + bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous low‑threshold comparator interrupt. This + will set TS1_AITLEN in DTS_ITENR and generate a wakeup event + when the measurement drops below your low threshold. + +config STM32_DTS_AITEN_AITHF + bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous high‑threshold comparator interrupt. This + will set TS1_AITHEN in DTS_ITENR and generate a wakeup event + when the measurement exceeds your high threshold. diff --git a/arch/arm/src/common/stm32/Kconfig.eth b/arch/arm/src/common/stm32/Kconfig.eth new file mode 100644 index 0000000000000..63344d7baff77 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.eth @@ -0,0 +1,293 @@ +# +# STM32 common ETH options. +# + +# PHY per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_PHY_HAVE_POLLED + bool + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_PHY_HAVE_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. diff --git a/arch/arm/src/common/stm32/Kconfig.fdcan b/arch/arm/src/common/stm32/Kconfig.fdcan new file mode 100644 index 0000000000000..9118b4a3800f9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.fdcan @@ -0,0 +1,520 @@ +# +# STM32 common FDCAN options. +# + +# STM32 FDCAN configuration options. + +menu "FDCAN Driver Configuration" + depends on STM32_HAVE_FDCAN_H7 && (STM32_FDCAN1 || STM32_FDCAN2 || STM32_FDCAN3) + +menu "FDCAN1 Configuration" + depends on STM32_FDCAN1 + +config FDCAN1_BITRATE + int "FDCAN1 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN1_ARBI_BITRATE + int "FDCAN1 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN1_DATA_BITRATE + int "FDCAN1 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN1 + +menu "FDCAN2 Configuration" + depends on STM32_FDCAN2 + +config FDCAN2_BITRATE + int "FDCAN2 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN2_ARBI_BITRATE + int "FDCAN2 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN2_DATA_BITRATE + int "FDCAN2 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN2 + +menu "FDCAN3 Configuration" + depends on STM32_FDCAN3 + +config FDCAN3_BITRATE + int "FDCAN3 CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN3_ARBI_BITRATE + int "FDCAN3 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN3_DATA_BITRATE + int "FDCAN3 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN3 + +endmenu # FDCAN Driver + +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support + +if STM32_FDCAN1 + +choice + prompt "FDCAN1 frame format" + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format + +choice + prompt "FDCAN1 mode" + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +choice + prompt "FDCAN2 frame format" + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format + +choice + prompt "FDCAN2 mode" + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode + +endif # STM32_FDCAN2 + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 diff --git a/arch/arm/src/common/stm32/Kconfig.flash b/arch/arm/src/common/stm32/Kconfig.flash new file mode 100644 index 0000000000000..8d18c20cf4651 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.flash @@ -0,0 +1,164 @@ +# +# STM32 common FLASH options. +# + +# STM32 flash configuration options. + +# Common STM32 flash size designator options. + +config STM32_FLASH_CONFIG_DEFAULT + bool "Default or device-derived flash size" + default n + +config STM32_FLASH_CONFIG_4 + bool "Flash size designator 4, 16 KiB" + default n + +config STM32_FLASH_CONFIG_6 + bool "Flash size designator 6, 32 KiB" + default n + +config STM32_FLASH_CONFIG_8 + bool "Flash size designator 8, 64 KiB" + default n + +config STM32_FLASH_CONFIG_B + bool "Flash size designator B, 128 KiB" + default n + +config STM32_FLASH_CONFIG_C + bool "Flash size designator C, 256 KiB" + default n + +config STM32_FLASH_CONFIG_C_320 + bool "STM32WB flash size designator C, 320 KiB variant" + default n + +config STM32_FLASH_CONFIG_D + bool "Flash size designator D, 384 KiB" + default n + +config STM32_FLASH_CONFIG_E + bool "Flash size designator E, 512 KiB" + default n + +config STM32_FLASH_CONFIG_F + bool "Flash size designator F, 768 KiB" + default n + +config STM32_FLASH_CONFIG_G + bool "Flash size designator G, 1024 KiB" + default n + +config STM32_FLASH_CONFIG_I + bool "Flash size designator I, 2048 KiB" + default n + +config STM32_FLASH_CONFIG_Y + bool "Flash size designator Y, 640 KiB" + default n + +config STM32_FLASH_CONFIG_Z + bool "Legacy STM32 flash size designator Z" + default n + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default y if ARCH_CHIP_STM32WL5 + default n + +choice + prompt "Override Flash Size Designator" + depends on STM32_FLASH_OVERRIDE + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32 parts numbering ends with a number or letter that designates + the internal FLASH size. Select "Default" to use the size from + the selected chip. Select another designator only when the part + variant differs from the listed chip selection. + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_Y + bool "Y 640KiB" + +endchoice # Override Flash Size Designator + +config STM32_FLASH_ART_ACCELERATOR + bool "Flash ART Accelerator" + depends on STM32_HAVE_FLASH_ART_ACCELERATOR + default n + ---help--- + ART Accelerator on the flash memory ITCM interface accelerates code execution + with a system of instruction prefetch and cache lines. + + Enable if code and/or read-only data is accessed through ITCM bus instead of + AXIM bus. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on STM32_FLASH_DCACHE && (STM32_STM32F20XX || STM32_STM32F4XXX || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR))) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_FLASH_ICACHE + bool "Enable FLASH Instruction Cache" + default y + depends on STM32_HAVE_FLASH_ICACHE + ---help--- + Enable the FLASH instruction cache. + +config STM32_FLASH_DCACHE + bool "Enable FLASH Data Cache" + default y + depends on STM32_HAVE_FLASH_DCACHE + ---help--- + Enable the FLASH data cache. diff --git a/arch/arm/src/common/stm32/Kconfig.foc b/arch/arm/src/common/stm32/Kconfig.foc new file mode 100644 index 0000000000000..79e61e292e415 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.foc @@ -0,0 +1,197 @@ +# +# STM32 common FOC options. +# + +config STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + bool + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC3_JEXTSEL + +# +# + +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_M3M4_V2 || ARCH_CHIP_STM32F7 || (STM32_HAVE_IP_ADC_M3M4_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" + +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_HAVE_COMMON_FOC || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM1 + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM8 + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +if STM32_FOC + +config STM32_FOC_USE_ADC4 + bool + default n + select STM32_ADC4 + select STM32_ADC3_JEXTSEL + +config STM32_FOC_G4_ADCCHAN0_WORKAROUND + bool "FOC G4 ADC channel 0 unwanted conversion workaround" + default n + depends on STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + ---help--- + Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 + conversion when a regular conversion is interrupted by an injected conversion. + This FOC implementation uses injected conversion to sample phase currents + and allows user to use regular conversion as an auxiliary analog conversion. + In this case, there is a certain probability that regular conversion will be + interrupted by an injected conversion that will lead to an incorrect reading + of phase currents. + + This workaround inserts a dummy conversion at the beginning of the injected + sequence. For more details look at the chip errata documents. + +endif #STM32_FOC diff --git a/arch/arm/src/common/stm32/Kconfig.gpio b/arch/arm/src/common/stm32/Kconfig.gpio new file mode 100644 index 0000000000000..17ee405e9e1c6 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.gpio @@ -0,0 +1,11 @@ +# +# STM32 common GPIO options. +# + +# STM32 GPIO configuration options. + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have new file mode 100644 index 0000000000000..781558cae1d30 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -0,0 +1,1144 @@ +# +# STM32 hidden hardware-capability flags (single source of truth). +# +# All STM32_HAVE_* / STM32_HAVE_IP_* symbols are defined here. They are +# prompt-less bool selectors describing what hardware exists on a chip and +# which IP-core version a peripheral uses. Family Kconfig files +# (arch/arm/src/stm32/Kconfig) "select" these symbols to describe their +# silicon; never add a prompt here. User-visible peripheral selection lives +# in Kconfig.periph and per-peripheral options in Kconfig.. +# +# Naming: an STM32_HAVE_IP__V symbol names the IP-core VERSION only; +# it must NOT encode the CPU core, because a given IP version is the same +# silicon regardless of whether it sits next to a Cortex-M0 or M3/M4 core (e.g. +# SPI v2 is SPI v2 on both STM32F0 and STM32F4). When a core-specific driver +# .c file or register header has to be chosen, use the standard NuttX core +# symbols (CONFIG_ARCH_CORTEXM0 for M0, CONFIG_ARCH_CORTEXM3 / ARCH_CORTEXM4 +# otherwise) -- not an STM32_HAVE_IP_* symbol. +# +# Two-level selection is intentional and must NOT be "cleaned up" as a +# duplicate: some peripherals use a "register-set" symbol that picks the +# hardware header (e.g. STM32_HAVE_IP_FLASH_M3M4_V1 -> hardware/stm32_flash.h, +# STM32_HAVE_IP_DMA_V1/_V2 -> hardware/stm32_dma.h) AND a separate +# "driver-variant" symbol that picks the .c file in Make.defs (e.g. +# STM32_HAVE_IP_FLASH_M3M4_F2F4, STM32_HAVE_IP_DMA_V2_STREAM). A family +# legitimately selects one of each. +# +# Within a single mutually-exclusive group (the #elif dispatch in +# hardware/stm32_.h and the else-if chain in Make.defs), a family must +# select exactly one member; the dispatch headers carry #error guards that +# enforce this at build time. +# + +# ADC capabilities + +config STM32_HAVE_ADC_TIMTRIG_TRGO2 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_ADC_TIMTRIG_TRGO + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_ADC_CHANNEL + bool + +config STM32_HAVE_ADC_L4 + bool + +config STM32_HAVE_ADC_H5 + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_IP_SDADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V1 + +config STM32_HAVE_IP_ADC_M3M4_V2 + bool + +config STM32_HAVE_IP_ADC_M3M4_V2_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V2 + +config STM32_HAVE_IP_ADC_M0_V1 + bool + +config STM32_HAVE_ADC1 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + +# BLE capabilities + +config STM32_HAVE_BLE + bool + +# CACHE capabilities + +config STM32_HAVE_DCACHE1 + bool + +config STM32_HAVE_ICACHE + bool + +# CAN capabilities + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M0_V1 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + bool + +# CEC capabilities + +config STM32_HAVE_CEC + bool + +# CLOCK capabilities + +config STM32_HAVE_CSI + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_IP_HSI48_M0_V1 + bool + +# COMP capabilities + +config STM32_HAVE_COMP1 + bool + +config STM32_HAVE_COMP2 + bool + +config STM32_HAVE_COMP3 + bool + +config STM32_HAVE_COMP4 + bool + +config STM32_HAVE_COMP5 + bool + +config STM32_HAVE_COMP6 + bool + +config STM32_HAVE_COMP7 + bool + +config STM32_HAVE_IP_COMP_M3M4_V1 + bool + +config STM32_HAVE_IP_COMP_M3M4_V2 + bool + +config STM32_HAVE_IP_COMP_M0_V1 + bool + +config STM32_HAVE_COMP + bool + default y if STM32_HAVE_COMP1 || STM32_HAVE_COMP2 || STM32_HAVE_COMP3 || STM32_HAVE_COMP4 || STM32_HAVE_COMP5 || STM32_HAVE_COMP6 || STM32_HAVE_COMP7 + +# CORDIC capabilities + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_IP_CORDIC_M3M4_V1 + bool + +# DAC capabilities + +config STM32_HAVE_DAC_LL_OPS + bool + +config STM32_HAVE_IP_DAC_M3M4_V1 + bool + +config STM32_HAVE_IP_DAC_M3M4_V2 + bool + +config STM32_HAVE_IP_DAC_M0_V1 + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +# DBGMCU capabilities + +config STM32_HAVE_IP_DBGMCU_M0_V1 + bool + +config STM32_HAVE_IP_DBGMCU_M3M4_V1 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + +config STM32_HAVE_IP_DBGMCU_M3M4_V2 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +config STM32_HAVE_IP_DBGMCU_M3M4_V3 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +# DCMI capabilities + +config STM32_HAVE_DCMI_PSSI + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_IP_DCMI_V1 + bool + +# DFSDM capabilities + +config STM32_HAVE_MDF1 + bool + +config STM32_HAVE_ADF1 + bool + +config STM32_HAVE_DFSDM1 + bool + +# DMA capabilities + +config STM32_HAVE_MDMA + bool + +config STM32_HAVE_BDMA + bool + +config STM32_HAVE_GPADMA1 + bool + +config STM32_HAVE_LPDMA1 + bool + +config STM32_HAVE_DMA1 + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_DMA_V1_7CH + bool + +config STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1_8CH + bool + +config STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V2_STREAM + bool + +config STM32_HAVE_IP_DMA2D_M3M4_V1 + bool + +# DTS capabilities + +config STM32_HAVE_DTS + bool + +# ETH capabilities + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_IP_ETHMAC_M3M4_V1 + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_ETHERNET + bool + +# FDCAN capabilities + +config STM32_HAVE_FDCAN_H7 + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + bool + +# FLASH capabilities + +config STM32_HAVE_FLASH_ART_ACCELERATOR + bool + +config STM32_HAVE_FLASH + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_IP_FLASH_M0_V1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_V1 + bool + +config STM32_HAVE_IP_FLASH_M0_G0C0 + bool + +config STM32_HAVE_IP_FLASH_M3M4_L1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F1F3 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F2F4 + bool + +config STM32_HAVE_IP_FLASH_M3M4_G4 + bool + +config STM32_HAVE_OTFDEC1 + bool + +config STM32_HAVE_OTFDEC2 + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +# FOC capabilities + +config STM32_HAVE_COMMON_FOC + bool + +# GPIO capabilities + +config STM32_HAVE_LPGPIO1 + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +# HRTIM capabilities + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_IP_HRTIM_M3M4_V1 + bool + +# I2C capabilities + +config STM32_HAVE_I2C_H5 + bool + +config STM32_HAVE_I2C5 + bool + +config STM32_HAVE_I2C6 + bool + +config STM32_HAVE_IP_I2C_M3M4_V1 + bool + +config STM32_HAVE_IP_I2C_M3M4_V2 + bool + +config STM32_HAVE_IP_I2C_M0_V1 + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +# IPCC capabilities + +config STM32_HAVE_HSEM + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_MBOX + bool + +# JPEG capabilities + +config STM32_HAVE_JPEG + bool + +# LPUART capabilities + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_LPUART + bool + +# LTDC capabilities + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_IP_LTDC_M3M4_V1 + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_LCD + bool + +# MEMORY capabilities + +config STM32_HAVE_RAMCFG + bool + +config STM32_HAVE_SRAM1 + bool + +config STM32_HAVE_SRAM2 + bool + +config STM32_HAVE_SRAM3 + bool + +config STM32_HAVE_SRAM5 + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_IP_CCM_M3M4_V1 + bool + +config STM32_HAVE_IP_FMC_M3M4_V1 + bool + +config STM32_HAVE_IP_FSMC_M3M4_V1 + bool + +config STM32_HAVE_IP_BBSRAM_M3M4_V1 + bool + +config STM32_HAVE_IP_BKP_M3M4_V1 + bool + +config STM32_HAVE_COMMON_WASTE + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_IP_DFUMODE_M3M4_V1 + bool + +config STM32_HAVE_SRAM2A + bool + +config STM32_HAVE_SRAM2B + bool + +# OPAMP capabilities + +config STM32_HAVE_OPAMP1 + bool + +config STM32_HAVE_OPAMP2 + bool + +config STM32_HAVE_OPAMP3 + bool + +config STM32_HAVE_OPAMP4 + bool + +config STM32_HAVE_OPAMP5 + bool + +config STM32_HAVE_OPAMP6 + bool + +config STM32_HAVE_IP_OPAMP_M3M4_V1 + bool + +# POWER capabilities + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_VREF + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_IP_PWR_M0_V1 + bool + +config STM32_HAVE_IP_PWR_G0 + bool + +config STM32_HAVE_IP_PWR_M3M4_V1 + bool + +config STM32_HAVE_SMPS + bool + +# QSPI capabilities + +config STM32_HAVE_QSPI1 + bool + +config STM32_HAVE_OCTOSPIM + bool + +config STM32_HAVE_OCTOSPI1 + bool + +config STM32_HAVE_OCTOSPI2 + bool + +config STM32_HAVE_QSPI + bool + +# RNG capabilities + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_IP_RNG_M0_V1 + bool + +config STM32_HAVE_IP_RNG_M3M4_V1 + bool + +# RTC capabilities + +config STM32_HAVE_RTC_MAGIC + bool + default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC + default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC + +config STM32_HAVE_RTCAPB + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M0_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_L1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_F4 + bool + +config STM32_HAVE_IP_RTC_M3M4_V1 + bool + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +# SAI capabilities + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_IP_I2S_M3M4_V1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +# SDIO capabilities + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_IP_SDIO_M3M4_V1 + bool + +# SECURITY capabilities + +config STM32_HAVE_FIREWALL + bool + +config STM32_HAVE_GTZC1 + bool + +config STM32_HAVE_GTZC2 + bool + +config STM32_HAVE_PKA + bool + +config STM32_HAVE_SAES + bool + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_IP_AES_M0_V1 + bool + +config STM32_HAVE_IP_AES_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_H7 + bool + +config STM32_HAVE_HASH + bool + +# SPI capabilities + +config STM32_HAVE_SPI_CORE_DMA + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_HAVE_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_HAVE_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_HAVE_IP_SPI_V1 + bool + +config STM32_HAVE_IP_SPI_V2 + bool + +config STM32_HAVE_IP_SPI_V3 + bool + +config STM32_HAVE_IP_SPI_V4 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +# SYSTEM capabilities + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_IP_GPIO_M0_V1 + bool + +config STM32_HAVE_IP_GPIO_M3M4_V1 + bool + + +config STM32_HAVE_SYSCFG + bool + default y if STM32_HAVE_COMP || STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + +config STM32_HAVE_IP_SYSCFG_M3M4_V1 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +# TIM capabilities + +config STM32_HAVE_TIM_PWM + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_HAVE_TIM_PWM_NO_F0 + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_ADVANCED + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_SINGLECHAN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_INTERNAL + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5 + +config STM32_HAVE_TIM_PWM_STM32PWM + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + bool + default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_CHMODE_LEGACY + bool + default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_M3M4_V2 + +config STM32_HAVE_TIM_PWM_CHMODE_LIMITED + bool + default y if STM32_HAVE_IP_TIMERS_M0_V1 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + bool + default y if STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_NOUT_REQUIRES_OUT + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_PWM_MULTICHAN + bool + default y if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM + default y if (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_HAVE_QENCODER_MAIN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_QENCODER_16BIT + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_HAVE_IP_TIMERS + select STM32_HAVE_TIM7 if STM32_HAVE_IP_TIMERS + +config STM32_HAVE_LPTIM_CHANNEL + bool + +config STM32_HAVE_IP_TIMERS + bool + default y if STM32_HAVE_IP_TIMERS_M3M4_V1 + default y if STM32_HAVE_IP_TIMERS_M3M4_V2 + default y if STM32_HAVE_IP_TIMERS_M3M4_V3 + default y if STM32_HAVE_IP_TIMERS_M0_V1 + +config STM32_HAVE_IP_TIMERS_M3M4_V1 + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V2 + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V3 + bool + +config STM32_HAVE_IP_TIMERS_M0_V1 + bool + +config STM32_HAVE_TIM_ADC_TRIGGER + bool + default y if STM32_HAVE_IP_ADC_M3M4_V1 + default y if STM32_HAVE_IP_ADC_M3M4_V2 + default y if STM32_HAVE_IP_ADC_M0_V1 + default y if STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_H5_L5_U5 + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_HAVE_TIM_DAC_TRIGGER + bool + default y if STM32_COMMON_LEGACY + default y if ARCH_CHIP_STM32F7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_IP_ONESHOT_M3M4_V1 + bool + +config STM32_HAVE_IP_FREERUN_M3M4_V1 + bool + +# TSC capabilities + +config STM32_HAVE_TSC + bool + +# UART capabilities + +config STM32_HAVE_SWPMI + bool + +config STM32_HAVE_USART_H5 + bool + +config STM32_HAVE_USART_RXFIFO_THRESHOLD + bool + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_IP_USART + bool + +config STM32_HAVE_IP_USART_V1 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V2 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V3 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V4 + bool + select STM32_HAVE_IP_USART + select STM32_HAVE_USART_RXFIFO_THRESHOLD + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_USART1 + bool + +# UID capabilities + +config STM32_HAVE_IP_UID_M0_V1 + bool + +config STM32_HAVE_IP_UID_M3M4_V1 + bool + +# USB capabilities + +config STM32_HAVE_USBFS_MODE + bool + +config STM32_HAVE_USBDRD_HOST + bool + +config STM32_HAVE_OTG_H7 + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_IP_USBDEV_M0_V1 + bool + +config STM32_HAVE_IP_USBDEV_M3M4_V1 + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_IP_USBFS_M3M4_V1 + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_IP_OTGFS_M3M4_V1 + bool + +config STM32_HAVE_IP_OTGHS_M3M4_V1 + bool + +config STM32_HAVE_COMMON_USBHOST_DEBUG + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_USB + bool + +# WDG capabilities + +config STM32_HAVE_IP_WDG_M0_V1 + bool + +config STM32_HAVE_IP_WDG_M3M4_V1 + bool diff --git a/arch/arm/src/common/stm32/Kconfig.hciuart b/arch/arm/src/common/stm32/Kconfig.hciuart new file mode 100644 index 0000000000000..81fb4fcb4483b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hciuart @@ -0,0 +1,292 @@ +# +# STM32 common HCI UART options. +# + +config STM32_HCIUART + bool + +config STM32_HCIUART_RXDMA + bool + +if STM32_USART1_HCIUART + +config STM32_HCIUART1_RXBUFSIZE + int "HCI UART1 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART1_TXBUFSIZE + int "HCI UART1 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART1_BAUD + int "HCI UART1 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART1_RXDMA + bool "HCI UART1 Rx DMA" + default n + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART1_HCIUART + +if STM32_USART2_HCIUART + +config STM32_HCIUART2_RXBUFSIZE + int "HCI UART2 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART2_TXBUFSIZE + int "HCI UART2 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART2_BAUD + int "HCI UART2 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART2_RXDMA + bool "HCI UART2 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART2_HCIUART + +if STM32_USART3_HCIUART + +config STM32_HCIUART3_RXBUFSIZE + int "HCI UART3 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART3_TXBUFSIZE + int "HCI UART3 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART3_BAUD + int "HCI UART3 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART3_RXDMA + bool "HCI UART3 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART3_HCIUART + +if STM32_USART6_HCIUART + +config STM32_HCIUART6_RXBUFSIZE + int "HCI UART6 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART6_TXBUFSIZE + int "HCI UART6 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART6_BAUD + int "HCI UART6 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART6_RXDMA + bool "HCI UART6 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART6_HCIUART + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + +menu "HCI UART Driver Configuration" + depends on STM32_SERIALDRIVER + +config STM32_HCIUART_RXDMA_BUFSIZE + int "Rx DMA buffer size" + default 32 + range 32 4096 + depends on STM32_HCIUART_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_HCIUART_RXDMAPRIO + hex "HCI UART DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_HCIUART_RXDMA + ---help--- + Select HCI UART DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_HCIUART_SW_RXFLOW + bool "Use Software UART RTS flow control" + default n + ---help--- + Enable UART RTS flow control using Software. Current STM32 have + broken HW based RTS behavior (they assert nRTS after every byte + received) Enable this setting workaround this issue by using + software based management of RTS + + If HCI UART DMA is enabled, this is probably the better selection + as well. In that case, the Rx DMA buffer will avoid Rx overrun due + to short, bursty activity. Software RTS management will probably + result in overall better throughput and should still avoid Rx data + overrun conditions. + +config STM32_HCIUART_UPPER_WATERMARK + int "RTS flow control upper watermark (%)" + default 75 + range 2 100 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be asserted + when this amount of Rx data has been buffered. The amount is + expressed as a percentage of the Rx buffer size. + +config STM32_HCIUART_LOWER_WATERMARK + int "RTS flow control lower watermark (%)" + default 25 + range 1 99 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be de-asserted + when there is less than this amount ofdata in the Rx buffere. The + amount is expressed as a percentage of the Rx buffer size. + +endmenu # HCI UART Driver Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.hrtim b/arch/arm/src/common/stm32/Kconfig.hrtim new file mode 100644 index 0000000000000..57170b0a60c88 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hrtim @@ -0,0 +1,588 @@ +# +# STM32 common HRTIM options. +# + +# STM32 HRTIM configuration options. + +# HRTIM per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_HRTIM1_HAVE_PLLCLK + bool + default y if STM32_STM32F33XX + +config STM32_HRTIM_DISABLE_CHARDRV + bool "HRTIM Disable Character Driver" + default n + ---help--- + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. + +config STM32_HRTIM_NO_ENABLE_TIMERS + bool "Do not enable HRTIM timers at startup" + default n + ---help--- + Do not enable HRTIM timers at startup + +menuconfig STM32_HRTIM_ADC + bool "HRTIM ADC Triggering" + default n + ---help--- + Enable HRTIM ADC Triggering support. + +if STM32_HRTIM_ADC + +config STM32_HRTIM_ADC1_TRG1 + bool "HRTIM ADC1 Trigger 1" + default n + +config STM32_HRTIM_ADC1_TRG2 + bool "HRTIM ADC1 Trigger 2" + default n + +config STM32_HRTIM_ADC1_TRG3 + bool "HRTIM ADC1 Trigger 3" + default n + +config STM32_HRTIM_ADC1_TRG4 + bool "HRTIM ADC1 Trigger 4" + default n + +config STM32_HRTIM_ADC2_TRG1 + bool "HRTIM ADC2 Trigger 1" + default n + +config STM32_HRTIM_ADC2_TRG2 + bool "HRTIM ADC2 Trigger 2" + default n + +config STM32_HRTIM_ADC2_TRG3 + bool "HRTIM ADC2 Trigger 3" + default n + +config STM32_HRTIM_ADC2_TRG4 + bool "HRTIM ADC2 Trigger 4" + default n + +endif # STM32_HRTIM_ADC + +config STM32_HRTIM_DAC + bool "HRTIM DAC Triggering" + default n + ---help--- + Enable HRTIM DAC Triggering support. + +config STM32_HRTIM_PWM + bool "HRTIM PWM Outputs" + default n + ---help--- + Enable HRTIM PWM Outputs support. + +config STM32_HRTIM_CAP + bool "HRTIM Capture" + default n + ---help--- + Enable HRTIM Capture support. + +config STM32_HRTIM_INTERRUPTS + bool "HRTIM Interrupts" + default n + ---help--- + Enable HRTIM Interrupts support. + +config STM32_HRTIM_BURST + bool "HRTIM Burst Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. + +config STM32_HRTIM_DEADTIME + bool "HRTIM Dead-time" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Deadtime support for PWM outputs. + +config STM32_HRTIM_PUSHPULL + bool "HRTIM Push-Pull Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. + +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. + +config STM32_HRTIM_DMA + bool "HRTIM DMA" + default n + +config STM32_HRTIM_DMABURST + bool "HRTIM DMA Burst" + default n + +config STM32_HRTIM_AUTODELAY + bool "HRTIM Autodelay" + depends on STM32_HRTIM_PWM + default n + +menuconfig STM32_HRTIM_EVENTS + bool "HRTIM Events Configuration" + default n + ---help--- + Enable HRTIM Events support. + +if STM32_HRTIM_EVENTS + +config STM32_HRTIM_EEV1 + bool "HRTIM EEV1" + default n + +config STM32_HRTIM_EEV2 + bool "HRTIM EEV2" + default n + +config STM32_HRTIM_EEV3 + bool "HRTIM EEV3" + default n + +config STM32_HRTIM_EEV4 + bool "HRTIM EEV4" + default n + +config STM32_HRTIM_EEV5 + bool "HRTIM EEV5" + default n + +config STM32_HRTIM_EEV6 + bool "HRTIM EEV6" + default n + +config STM32_HRTIM_EEV7 + bool "HRTIM EEV7" + default n + +config STM32_HRTIM_EEV8 + bool "HRTIM EEV8" + default n + +config STM32_HRTIM_EEV9 + bool "HRTIM EEV9" + default n + +config STM32_HRTIM_EEV10 + bool "HRTIM EEV10" + default n + +endif # STM32_HRTIM_EVENTS + +menuconfig STM32_HRTIM_FAULTS + bool "HRTIM Faults Configuration" + default n + ---help--- + Enable HRTIM Faults support. + +if STM32_HRTIM_FAULTS + +config STM32_HRTIM_FAULT1 + bool "HRTIM Fault 1" + default n + +config STM32_HRTIM_FAULT2 + bool "HRTIM Fault 2" + default n + +config STM32_HRTIM_FAULT3 + bool "HRTIM Fault 3" + default n + +config STM32_HRTIM_FAULT4 + bool "HRTIM Fault 4" + default n + +endif # STM32_HRTIM_FAULTS + +config STM32_HRTIM_CLK_FROM_PLL + bool "HRTIM Clock from PLL" + default n + depends on STM32_HRTIM1_HAVE_PLLCLK + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. + +menu "HRTIM Master Configuration" + depends on STM32_HRTIM_MASTER + +config STM32_HRTIM_MASTER_DAC + bool "HRTIM Master DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_MASTER_DMA + bool "HRTIM MASTER DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_MASTER_IRQ + bool "HRTIM MASTER Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +endmenu # "HRTIM Master Configuration" + +menu "HRTIM Timer A Configuration" + depends on STM32_HRTIM_TIMA + +config STM32_HRTIM_TIMA_CAP + bool "HRTIM TIMA Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMA_DAC + bool "HRTIM TIMA DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMA_DMA + bool "HRTIM TIMA DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMA_IRQ + bool "HRTIM TIMA Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMA_PWM + bool "HRTIM TIMA PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMA_PWM_CH1 + bool "HRTIM TIMA PWM Output 1" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_PWM_CH2 + bool "HRTIM TIMA PWM Output 2" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_BURST + bool "HRTIM TIMA Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_BURST_CH1 + bool "HRTIM TIMA Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) + +config STM32_HRTIM_TIMA_BURST_CH2 + bool "HRTIM TIMA Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) + +config STM32_HRTIM_TIMA_CHOP + bool "HRTIM TIMA PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_DT + bool "HRTIM TIMA PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_PSHPLL + bool "HRTIM TIMA PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) + +endmenu # "HRTIM Timer A Configuration" + +menu "HRTIM Timer B Configuration" + depends on STM32_HRTIM_TIMB + +config STM32_HRTIM_TIMB_CAP + bool "HRTIM TIMB Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMB_DAC + bool "HRTIM TIMB DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMB_DMA + bool "HRTIM TIMB DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMB_IRQ + bool "HRTIM TIMB Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMB_PWM + bool "HRTIM TIMB PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMB_PWM_CH1 + bool "HRTIM TIMB PWM Output 1" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_PWM_CH2 + bool "HRTIM TIMB PWM Output 2" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_BURST + bool "HRTIM TIMB Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_BURST_CH1 + bool "HRTIM TIMB Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) + +config STM32_HRTIM_TIMB_BURST_CH2 + bool "HRTIM TIMB Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) + +config STM32_HRTIM_TIMB_CHOP + bool "HRTIM TIMB PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_DT + bool "HRTIM TIMB PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_PSHPLL + bool "HRTIM TIMB PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) + +endmenu # "HRTIM Timer B Configuration" + +menu "HRTIM Timer C Configuration" + depends on STM32_HRTIM_TIMC + +config STM32_HRTIM_TIMC_CAP + bool "HRTIM TIMC Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMC_DAC + bool "HRTIM TIMC DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMC_DMA + bool "HRTIM TIMC DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMC_IRQ + bool "HRTIM TIMC Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMC_PWM + bool "HRTIM TIMC PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMC_PWM_CH1 + bool "HRTIM TIMC PWM Output 1" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_PWM_CH2 + bool "HRTIM TIMC PWM Output 2" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_BURST + bool "HRTIM TIMC Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_BURST_CH1 + bool "HRTIM TIMC Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) + +config STM32_HRTIM_TIMC_BURST_CH2 + bool "HRTIM TIMC Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) + +config STM32_HRTIM_TIMC_CHOP + bool "HRTIM TIMC PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_DT + bool "HRTIM TIMC PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_PSHPLL + bool "HRTIM TIMC PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) + +endmenu # "HRTIM Timer C Configuration" + +menu "HRTIM Timer D Configuration" + depends on STM32_HRTIM_TIMD + +config STM32_HRTIM_TIMD_CAP + bool "HRTIM TIMD Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMD_DAC + bool "HRTIM TIMD DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMD_DMA + bool "HRTIM TIMD DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMD_IRQ + bool "HRTIM TIMD Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMD_PWM + bool "HRTIM TIMD PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMD_PWM_CH1 + bool "HRTIM TIMD PWM Output 1" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_PWM_CH2 + bool "HRTIM TIMD PWM Output 2" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_BURST + bool "HRTIM TIMD Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_BURST_CH1 + bool "HRTIM TIMD Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) + +config STM32_HRTIM_TIMD_BURST_CH2 + bool "HRTIM TIMD Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) + +config STM32_HRTIM_TIMD_CHOP + bool "HRTIM TIMD PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_DT + bool "HRTIM TIMD PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_PSHPLL + bool "HRTIM TIMD PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) + +endmenu # "HRTIM Timer D Configuration" + +menu "HRTIM Timer E Configuration" + depends on STM32_HRTIM_TIME + +config STM32_HRTIM_TIME_CAP + bool "HRTIM TIME Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIME_DAC + bool "HRTIM TIME DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIME_DMA + bool "HRTIM TIME DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIME_IRQ + bool "HRTIM TIME Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIME_PWM + bool "HRTIM TIME PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIME_PWM_CH1 + bool "HRTIM TIME PWM Output 1" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_PWM_CH2 + bool "HRTIM TIME PWM Output 2" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_BURST + bool "HRTIM TIME Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_BURST_CH1 + bool "HRTIM TIME Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) + +config STM32_HRTIM_TIME_BURST_CH2 + bool "HRTIM TIME Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) + +config STM32_HRTIM_TIME_CHOP + bool "HRTIM TIME PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_DT + bool "HRTIM TIME PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_PSHPLL + bool "HRTIM TIME PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) + +endmenu # "HRTIM Timer E Configuration" diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c new file mode 100644 index 0000000000000..5f698da0f2ea2 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -0,0 +1,309 @@ +# +# STM32 common I2C options. +# + +# STM32 I2C configuration options. + +config STM32_I2C_SLAVE + bool + default n + +menu "I2C Configuration" + depends on STM32_HAVE_I2C_H5 && STM32_I2C + +menu "Clock Selection" + +choice + depends on STM32_I2C1 + prompt "I2C1 Input Clock Selection" + default STM32_I2C1_CLK_PCLK1 + +config STM32_I2C1_CLK_CSI + bool "CSI" + +config STM32_I2C1_CLK_HSI + bool "HSI" + +config STM32_I2C1_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C1_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C1 Input Clock Selection + +choice + depends on STM32_I2C2 + prompt "I2C2 Input Clock Selection" + default STM32_I2C2_CLK_PCLK1 + +config STM32_I2C2_CLK_CSI + bool "CSI" + +config STM32_I2C2_CLK_HSI + bool "HSI" + +config STM32_I2C2_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C2_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C2 Input Clock Selection + +choice + depends on STM32_I2C3 + prompt "I2C3 Input Clock Selection" + default STM32_I2C3_CLK_PCLK3 + +config STM32_I2C3_CLK_CSI + bool "CSI" + +config STM32_I2C3_CLK_HSI + bool "HSI" + +config STM32_I2C3_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C3_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C3 Input Clock Selection + +choice + depends on STM32_I2C4 + prompt "I2C4 Input Clock Selection" + default STM32_I2C4_CLK_PCLK3 + +config STM32_I2C4_CLK_CSI + bool "CSI" + +config STM32_I2C4_CLK_HSI + bool "HSI" + +config STM32_I2C4_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C4_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C4 Input Clock Selection + +endmenu # Clock Selection + +menu "Rise/Fall Override" + +config STM32_I2C1_RF_OVERRIDE + bool "I2C1" + default n + depends on STM32_I2C1 + +config STM32_I2C2_RF_OVERRIDE + bool "I2C2" + default n + depends on STM32_I2C2 + +config STM32_I2C3_RF_OVERRIDE + bool "I2C3" + default n + depends on STM32_I2C3 + +config STM32_I2C4_RF_OVERRIDE + bool "I2C4" + default n + depends on STM32_I2C4 + +menu "Rise/Fall Values" + +config STM32_I2C1_RISE + int "I2C1 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C1_FALL + int "I2C1 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C2_RISE + int "I2C2 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C2_FALL + int "I2C2 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C3_RISE + int "I2C3 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C3_FALL + int "I2C3 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C4_RISE + int "I2C4 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +config STM32_I2C4_FALL + int "I2C4 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +endmenu # Rise/Fall Values + +endmenu # Rise/Fall Override + +menu "Filtering" + +menu "Digital Filters" + +config STM32_I2C1_DNF + int "I2C1 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C1 + +config STM32_I2C2_DNF + int "I2C2 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C2 + +config STM32_I2C3_DNF + int "I2C3 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C3 + +config STM32_I2C4_DNF + int "I2C4 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C4 + +endmenu # Digital Filters + +menu "Analog Filters" + +config STM32_I2C1_ANFOFF + int "Turn off I2C1 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C1 + +config STM32_I2C2_ANFOFF + int "Turn off I2C2 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C2 + +config STM32_I2C3_ANFOFF + int "Turn off I2C3 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C3 + +config STM32_I2C4_ANFOFF + int "Turn off I2C4 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C4 + +endmenu # Analog Filters + +endmenu # Filtering + +endmenu # "I2C Configuration" + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_ALT + bool "Alternate I2C implementation" + default STM32F1_PERFORMANCELINE + depends on !STM32_STM32F30XX && STM32_COMMON_LEGACY + ---help--- + This selection enables an alternative I2C driver. This alternate + driver implements some rather complex workarounds for errata against + the STM32 F103 "Performance Line". This selection is an option + because: (1) It has not yet been fully verified and (2) It is not + certain that he scope of this workaround is needed only for the F103. + +config STM32_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9" + default n + depends on STM32_I2C && STM32_COMMON_LEGACY + +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. + +menu "I2C Slave Configuration" + depends on STM32_I2C_SLAVE + +config STM32_I2C_SLAVE_DEFAULT_TX + hex "Default TX byte to be sent when the TX buffer is empty" + default 0xFF + +config STM32_I2C_SLAVE_USEWQ + bool "Use work queue to delegate the isr completion status" + default n + ---help--- + With the current upperhalf I2C slave driver implementation, the user + should delegate the callback completion status using a work queue. + However, work queues introduce a delay, so in certain scenarios + it is better to use a custom driver without using a work queue. + +config STM32_I2C_SLAVE_RETRANSFER + bool "The frame is retransferred when stop is issued beforehand" + default n + ---help--- + If stop is issued before the whole frame is transferred, + the tx pointer is reset to 0. + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.ipcc b/arch/arm/src/common/stm32/Kconfig.ipcc new file mode 100644 index 0000000000000..da34bba96d277 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ipcc @@ -0,0 +1,91 @@ +# +# STM32 common IPCC options. +# + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 diff --git a/arch/arm/src/common/stm32/Kconfig.lpuart b/arch/arm/src/common/stm32/Kconfig.lpuart new file mode 100644 index 0000000000000..a0df333349769 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.lpuart @@ -0,0 +1,70 @@ +# +# STM32 common LPUART options. +# + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + depends on STM32_HAVE_IP_USART && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +if STM32_LPUART1_SERIALDRIVER + +config LPUART1_TXDMA + bool "LPUART1 Tx DMA" + default n + depends on STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +endif # STM32_LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 diff --git a/arch/arm/src/common/stm32/Kconfig.ltdc b/arch/arm/src/common/stm32/Kconfig.ltdc new file mode 100644 index 0000000000000..064c9270e722e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ltdc @@ -0,0 +1,235 @@ +# +# STM32 common LTDC options. +# + +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format + +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +# +# + +if STM32_LCD + +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK + +config LCD_LSICLOCK + bool "Internal Low Speed Clock" + +config LCD_LSECLOCK + bool "External Low Speed Clock" + +config LCD_HSECLOCK + bool "External High Speed Clock" + +endchoice +endif # STM32_LCD diff --git a/arch/arm/src/common/stm32/Kconfig.memory b/arch/arm/src/common/stm32/Kconfig.memory new file mode 100644 index 0000000000000..fdd9e013223c5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.memory @@ -0,0 +1,171 @@ +# +# STM32 common MEMORY options. +# + +# STM32 memory and SD/MMC configuration options. + +config STM32_SRAM5_HEAP + bool "SRAM5 is used for heap" + depends on STM32_SRAM5 + default n + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) + select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) + select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_CCMEXCLUDE + bool "Exclude CCM SRAM from the heap" + default ARCH_DMA || LIBC_ARCH_ELF + depends on STM32_HAVE_CCM + ---help--- + Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA + and (2) it appears to be impossible to execute ELF modules from CCM + RAM. + +config STM32_CCM_PROCFS + bool "CCM PROCFS support" + default n + depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER + ---help--- + Select to build in support for /proc/ccm. Reading from /proc/ccm + will provide statistics about CCM memory use similar to what you + would get from mallinfo() for the user heap. + +comment "STM32WB SRAM2a and SRAM2b Options" + depends on STM32_HAVE_SRAM2A || STM32_HAVE_SRAM2B + +config STM32_SRAM2A_HEAP + bool "SRAM2a is used for heap" + depends on STM32_HAVE_SRAM2A + default n + +config STM32_SRAM2A_USER_BASE_OFFSET + int "SRAM2a user application base offset" + default 2048 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The beginning part of the SRAM2a memory can be used by RF stack. The + available space for the user application can be obtained from the + release notes for STM32WB coprocessor wireless binaries. + +config STM32_SRAM2A_USER_SIZE + int "SRAM2a user application size" + default 8192 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The ending part of the SRAM2a memory contains a secure section, which + cannot be read nor written by CPU1. The secure start address for the + SRAM2a memory can be read from the SBRSA option byte. When CPU2 update + support required, there must be some free sectors just below the secure + memory to support CPU2 firmware updates requiring more sectors to be + secure. + +config STM32_SRAM2A_INIT + bool "SRAM2a is initialized to zero" + default y + depends on STM32_SRAM2A_HEAP + ---help--- + The STM32WB SRAM2a region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2a is being retained in Standby mode, this may be + undesirable (because it will destroy the contents). In that case, the board + should handle the initialization itself at the appropriate time. + +config STM32_SRAM2B_HEAP + bool "SRAM2b is used for heap" + depends on STM32_HAVE_SRAM2B + default n + +config STM32_SRAM2B_USER_SIZE + int "SRAM2b user application size" + default 32768 + range 0 32768 + depends on STM32_SRAM2B_HEAP + ---help--- + For any CPU2 firmware supporting the BLE protocol the ending part of + the SRAM2b memory contains a secure section, which cannot be read nor + written by CPU1. The secure start address for the SRAM2b memory can be + read from the SNBRSA option byte. When CPU2 update support required, + there must be some free sectors just below the secure memory to support + CPU2 firmware updates requiring more sectors to be secure. The SRAM2b + memory is all secure for any CPU2 firmware supporting the Thread protocol. + +config STM32_SRAM2B_INIT + bool "SRAM2b is initialized to zero" + default y + depends on STM32_SRAM2B_HEAP + ---help--- + The STM32WB SRAM2b region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph new file mode 100644 index 0000000000000..1098aed2cf295 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -0,0 +1,1283 @@ +# +# STM32 common peripheral selection options. +# + +menu "STM32 Peripheral Support" + +# hidden selectors + +config STM32_OPAMP + bool + depends on STM32_HAVE_IP_OPAMP_M3M4_V1 + select STM32_SYSCFG + +config STM32_COMP + bool + depends on STM32_HAVE_COMP + select STM32_SYSCFG + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +# peripheral enable selectors (set by the instance selections below) + +config STM32_ADC + bool + +config STM32_SDADC + bool + default n + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_I2C + bool + +config STM32_SPI + bool + +config STM32_TIM + bool + +config STM32_LPTIM + bool + +config STM32_HRTIM + bool + +config STM32_USART + bool + +config STM32_SERIALDRIVER + bool + +config STM32_SAI + bool + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_SDMMC + bool + +config STM32_DFSDM + bool + default n + +config STM32_MBOX + bool + depends on STM32_HAVE_MBOX + default n + select STM32_IPCC + +# DMA peripherals + +config STM32_MDMA + bool "MDMA" + default n + depends on STM32_HAVE_MDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_BDMA + bool "BDMA" + default n + depends on STM32_HAVE_BDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_GPADMA1 + depends on STM32_HAVE_GPADMA1 + bool "GPADMA1" + default n + +config STM32_LPDMA1 + depends on STM32_HAVE_LPDMA1 + bool "LPDMA1" + default n + +config STM32_DMA1 + bool "DMA1" + depends on STM32_HAVE_DMA1 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +# CLOCK peripherals + +config STM32_CSI + bool "CSI Low-speed internal oscillator (4MHz)" + depends on STM32_HAVE_CSI + default n + +config STM32_HSI48 + bool "HSI48 High-speed 48MHz internal oscillator" + depends on STM32_HAVE_HSI48 + default n + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +# POWER peripherals + +config STM32_VREF + depends on STM32_HAVE_VREF + bool "VREF" + default n + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_PWR + bool "PWR" + depends on STM32_COMMON_LEGACY || (STM32_COMMON_F0_L0_G0_C0 && !ARCH_CHIP_STM32C0) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB + +# MEMORY peripherals + +config STM32_RAMCFG + depends on STM32_HAVE_RAMCFG + bool "RAMCFG" + default n + +config STM32_SRAM1 + depends on STM32_HAVE_SRAM1 + bool "SRAM1" + default y + +config STM32_SRAM2 + depends on STM32_HAVE_SRAM2 + bool "SRAM2" + default n + +config STM32_SRAM3 + bool "SRAM3" + default n + depends on STM32_HAVE_SRAM3 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_SRAM5 + bool "SRAM5" + default n + depends on STM32_HAVE_SRAM5 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_BKP + bool "BKP" + depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_CCMDATARAM + bool "CMD/DATA RAM" + default n + depends on STM32_STM32F4XXX + +# FLASH peripherals + +config STM32_FLASH + depends on STM32_HAVE_FLASH + bool "FLASH" + default n + +# GPIO peripherals + +config STM32_LPGPIO1 + depends on STM32_HAVE_LPGPIO1 + bool "LPGPIO1" + default n + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +# SECURITY peripherals + +config STM32_FIREWALL + bool "FIREWALL" + default y + depends on STM32_HAVE_FIREWALL && STM32_SYSCFG + +config STM32_GTZC1 + depends on STM32_HAVE_GTZC1 + bool "GTZC1" + default n + +config STM32_GTZC2 + depends on STM32_HAVE_GTZC2 + bool "GTZC2" + default n + +config STM32_PKA + depends on STM32_HAVE_PKA + bool "PKA" + default n + +config STM32_SAES + depends on STM32_HAVE_SAES + bool "SAES" + default n + +config STM32_OTFDEC1 + depends on STM32_HAVE_OTFDEC1 + bool "OTFDEC1" + default n + +config STM32_OTFDEC2 + depends on STM32_HAVE_OTFDEC2 + bool "OTFDEC2" + default n + +config STM32_CRC + bool "CRC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB + +config STM32_AES + bool "128-bit AES" + depends on STM32_HAVE_IP_AES_M0_V1 || STM32_HAVE_IP_AES_M3M4_V1 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CRYP + bool "CRYP" + depends on STM32_HAVE_CRYP + depends on STM32_HAVE_IP_CRYPTO_M3M4_V1 || STM32_HAVE_IP_CRYPTO_H7 + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +# BLE peripherals + +menuconfig STM32_BLE + bool "BLE" + depends on STM32_HAVE_BLE + default n + select STM32_MBOX + ---help--- + Enable BLE support. + +# CACHE peripherals + +config STM32_ICACHE + bool "ICACHE" + default n + depends on STM32_HAVE_ICACHE + +config STM32_DCACHE1 + depends on STM32_HAVE_DCACHE1 + bool "DCACHE1" + default n + +# RTC peripherals + +config STM32_RTCAPB + depends on STM32_HAVE_RTCAPB + bool "RTCAPB" + default n + +config STM32_RTC + bool "RTC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB + select RTC if !ARCH_CHIP_STM32L5 + +# RNG peripherals + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +# WDG peripherals + +config STM32_IWDG + bool "IWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +# ADC peripherals + +config STM32_ADC1 + bool "ADC1" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_ADC1_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC1_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC2 + bool "ADC2" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_ADC2_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC2_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC3 + bool "ADC3" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_ADC3_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC3_HAVE_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC4 + bool "ADC4" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + select STM32_ADC4_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_ADC5 + bool "ADC5" + default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_ADC5_HAVE_DMA if STM32_DMA2 + select STM32_ADC5_HAVE_DMA if STM32_DMAMUX + +config STM32_SDADC1 + bool "SDADC1" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_SDADC1_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC2 + bool "SDADC2" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_SDADC2_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC3 + bool "SDADC3" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_SDADC3_HAVE_DMA if STM32_DMA2 + +# DAC peripherals + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DAC1CH1 + bool "DAC1CH1" + default n + depends on STM32_DAC1 + +config STM32_DAC1CH2 + bool "DAC1CH2" + default n + depends on STM32_DAC1 + +config STM32_DAC2CH1 + bool "DAC2CH1" + default n + depends on STM32_DAC2 + +config STM32_DAC3 + bool "DAC3" + default n + depends on STM32_HAVE_DAC3 + select STM32_DAC + +config STM32_DAC3CH1 + bool "DAC3CH1 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC3CH2 + bool "DAC3CH2 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC4 + bool "DAC4" + default n + depends on STM32_HAVE_DAC4 + select STM32_DAC + +config STM32_DAC4CH1 + bool "DAC4CH1 Internal" + default n + depends on STM32_DAC4 + +config STM32_DAC4CH2 + bool "DAC4CH2 Internal" + default n + depends on STM32_DAC4 + +# DFSDM peripherals + +config STM32_MDF1 + depends on STM32_HAVE_MDF1 + bool "MDF1" + default n + +config STM32_ADF1 + depends on STM32_HAVE_ADF1 + bool "ADF1" + default n + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +# CAN peripherals + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +# I2C peripherals + +config STM32_I2C5 + bool "I2C5" + depends on STM32_HAVE_I2C5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C6 + bool "I2C6" + depends on STM32_HAVE_I2C6 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +# +# + +config STM32_I2C1_SLAVE + bool "I2C1 Slave" + default n + depends on !STM32_I2C1 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C2_SLAVE + bool "I2C2 Slave" + default n + depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C3_SLAVE + bool "I2C3 Slave" + default n + depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE + select STM32_I2C_SLAVE + +# SPI peripherals + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +# SERIAL peripherals + +config STM32_UART9 + bool "UART9" + default n + depends on STM32_HAVE_UART9 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_UART12 + bool "UART12" + default n + depends on STM32_HAVE_UART12 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART10 + bool "USART10" + default n + depends on STM32_HAVE_USART10 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART11 + bool "USART11" + default n + depends on STM32_HAVE_USART11 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_SWPMI + bool "SWPMI" + depends on STM32_HAVE_SWPMI + default n + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +# TIM peripherals + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_HRTIM1 + bool "HRTIM1" + default n + depends on STM32_HAVE_HRTIM1 + select STM32_HRTIM + +config STM32_HRTIM_MASTER + bool "HRTIM MASTER" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Master Timer + +config STM32_HRTIM_TIMA + bool "HRTIM TIMA" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer A + +config STM32_HRTIM_TIMB + bool "HRTIM TIMB" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer B + +config STM32_HRTIM_TIMC + bool "HRTIM TIMC" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer C + +config STM32_HRTIM_TIMD + bool "HRTIM TIMD" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer D + +config STM32_HRTIM_TIME + bool "HRTIM TIME" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer E + +# USB peripherals + +choice STM32_USBFS_MODE + prompt "USB FS Mode" + depends on STM32_HAVE_USBFS_MODE && STM32_HAVE_USBFS + default STM32_USBFS_NONE + ---help--- + Select the operating mode for the USB_DRD_FS peripheral. + The hardware supports Device or Host, but not simultaneously. + +config STM32_USBFS_NONE + bool "Disabled" + +config STM32_USBFS_DEVICE + bool "USB Device" + select STM32_USBFS + select USBDEV + +config STM32_USBFS_HOST + bool "USB Host" + select USBHOST_HAVE_ASYNCH + select USBHOST + ---help--- + Enable USB host mode for USB_DRD_FS peripheral. + +endchoice + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" + default n + depends on STM32_HAVE_UCPD + select USBDEV + +config STM32_UCPD1 + depends on STM32_HAVE_UCPD1 + bool "UCPD1" + default n + +# CEC peripherals + +config STM32_CEC + bool "CEC" + depends on (STM32_COMMON_LEGACY && STM32F1_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC) || ARCH_CHIP_STM32F7 + +# SDIO peripherals + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +# SAI peripherals + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +# QSPI peripherals + +config STM32_QSPI1 + bool "QSPI1" + depends on STM32_HAVE_QSPI1 + default n + +config STM32_OCTOSPIM + depends on STM32_HAVE_OCTOSPIM + bool "OCTOSPIM" + default n + +config STM32_OCTOSPI1 + depends on STM32_HAVE_OCTOSPI1 + bool "OCTOSPI1" + default n + +config STM32_OCTOSPI2 + depends on STM32_HAVE_OCTOSPI2 + bool "OCTOSPI2" + default n + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI || STM32_COMMON_F7_H7 + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +# ETH peripherals + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_PHY_HAVE_POLLED if !STM32_COMMON_LEGACY + +# CORDIC peripherals + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on STM32_HAVE_IP_CORDIC_M3M4_V1 && MATH_CORDIC_USE_Q31 + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +# SENSOR peripherals + +config STM32_DTS + bool "DTS" + depends on STM32_HAVE_DTS + default n + ---help--- + Enable support for the on‑die digital temperature sensor (DTS) + built into STM32H5 devices. When enabled, the driver will register + a `/dev/sensor_tempX` device using the common NuttX sensor framework. + +config STM32_DCMI_PSSI + depends on STM32_HAVE_DCMI_PSSI + bool "DCMI_PSSI" + default n + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_COMP1 + bool "COMP1" + select STM32_COMP + depends on STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + select STM32_COMP + depends on STM32_HAVE_COMP2 + +config STM32_COMP3 + bool "COMP3" + default n + select STM32_COMP + depends on STM32_HAVE_COMP3 + +config STM32_COMP4 + bool "COMP4" + default n + select STM32_COMP + depends on STM32_HAVE_COMP4 + +config STM32_COMP5 + bool "COMP5" + default n + select STM32_COMP + depends on STM32_HAVE_COMP5 + +config STM32_COMP6 + bool "COMP6" + default n + select STM32_COMP + depends on STM32_HAVE_COMP6 + +config STM32_COMP7 + bool "COMP7" + default n + select STM32_COMP + depends on STM32_HAVE_COMP7 + +config STM32_OPAMP1 + bool "OPAMP1" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP1 + +config STM32_OPAMP2 + bool "OPAMP2" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP2 + +config STM32_OPAMP3 + bool "OPAMP3" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP3 + +config STM32_OPAMP4 + bool "OPAMP4" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP4 + +# IPCC peripherals + +config STM32_IPCC + bool "IPCC" + depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_HSEM + bool "Hardware semaphore" + depends on STM32_HAVE_HSEM + default n + +# Display peripherals + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +endmenu # STM32 Peripheral Support diff --git a/arch/arm/src/common/stm32/Kconfig.qspi b/arch/arm/src/common/stm32/Kconfig.qspi new file mode 100644 index 0000000000000..4150915fe4735 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.qspi @@ -0,0 +1,173 @@ +# +# STM32 common QSPI options. +# + +# STM32 QSPI/OCTOSPI configuration options. + +if STM32_HAVE_QSPI && (STM32_QSPI || STM32_QSPI1) + +choice + prompt "DMA Channel" + default STM32_QSPI_DMA_CHAN_1_5 + depends on STM32_DMA + ---help--- + You can choose between two DMA channels for use with QSPI: + either DMA1 channel 5, or DMA2 channel 7. + If you only see one choice here, it is probably because + you have not also enabled the associated DMA controller. + +config STM32_QSPI_DMA_CHAN_1_5 + bool "DMA1 Channel 5" + depends on STM32_DMA1 && !STM32_DMAMUX + ---help--- + Use DMA1 channel 5 for QSPI. + +config STM32_QSPI_DMA_CHAN_2_7 + bool "DMA2 Channel 7" + depends on STM32_DMA2 && !STM32_DMAMUX + ---help--- + Use DMA2 channel 7 for QSPI. + +endchoice + +endif + +choice + prompt "Transfer technique" + depends on STM32_QSPI || STM32_QSPI1 + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice + +choice + prompt "Bank selection" + depends on STM32_QSPI || STM32_QSPI1 + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice + +choice + prompt "DMA Priority" + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice + +config STM32_QUADSPI + bool "QuadSPI" + depends on STM32_COMMON_F7_H7 + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.rtc b/arch/arm/src/common/stm32/Kconfig.rtc new file mode 100644 index 0000000000000..b81e79860077e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.rtc @@ -0,0 +1,93 @@ +# +# STM32 common RTC options. +# + +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_HAVE_RTC_MAGIC + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_HAVE_RTC_MAGIC + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_HAVE_RTC_MAGIC + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. diff --git a/arch/arm/src/common/stm32/Kconfig.sai b/arch/arm/src/common/stm32/Kconfig.sai new file mode 100644 index 0000000000000..67a8c8ef710c4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sai @@ -0,0 +1,88 @@ +# +# STM32 common SAI options. +# + +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAIPLL + bool "SAIPLL" + default n + depends on STM32_HAVE_SAIPLL + ---help--- + The STM32F446 has a separate PLL for the SAI block. + Set this true and provide configuration parameters in + board.h to use this PLL. diff --git a/arch/arm/src/common/stm32/Kconfig.sdadc b/arch/arm/src/common/stm32/Kconfig.sdadc new file mode 100644 index 0000000000000..4053ae572b026 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdadc @@ -0,0 +1,42 @@ +# +# STM32 common SDADC options. +# + +# SDADC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_SDADC1_HAVE_DMA + bool + +config STM32_SDADC2_HAVE_DMA + bool + +config STM32_SDADC3_HAVE_DMA + bool + +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_SDADC1_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_SDADC2_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_SDADC3_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.sdio b/arch/arm/src/common/stm32/Kconfig.sdio new file mode 100644 index 0000000000000..3bf834a69393e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdio @@ -0,0 +1,153 @@ +# +# STM32 common SDIO options. +# + +# SDMMC per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_SDMMC2_HAVE_DMAPRIO + bool + default y if STM32_F7_PERIPHERALS + +config STM32_SDIO_CARD + bool "SDIO Card support" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_COMMON_LEGACY && STM32_SDIO + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_COMMON_LEGACY && STM32_SDIO + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDMMC2_DMAPRIO + hex "SDMMC2 DMA priority" + default 0x00010000 + depends on STM32_SDMMC2 && STM32_SDMMC2_HAVE_DMAPRIO + ---help--- + Select SDMMC2 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +endif # STM32_SDMMC diff --git a/arch/arm/src/common/stm32/Kconfig.spi b/arch/arm/src/common/stm32/Kconfig.spi new file mode 100644 index 0000000000000..cf360f805c926 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.spi @@ -0,0 +1,300 @@ +# +# STM32 common SPI options. +# + +config STM32_SPI_DMA + bool + depends on STM32_HAVE_SPI_CORE_DMA + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_HAVE_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +menu "I2S Configuration" + depends on STM32_I2S + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2SPLL + bool "I2SPLL" + default n + depends on STM32_HAVE_I2SPLL + ---help--- + The STM32F446 has a separate PLL for the I2S block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_I2S_MCK + bool "I2S_MCK" + depends on STM32_I2S3 + default n + ---help--- + TBD. + +endmenu # I2S Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system new file mode 100644 index 0000000000000..2398b1b534c78 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -0,0 +1,107 @@ +# +# STM32 common SYSTEM options. +# + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !(STM32F1_VALUELINE || STM32F0_VALUELINE) + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_NOEXT_VECTORS + bool "Disable the ARMv7-M EXT vectors" + default n + ---help--- + Sometimes you may not need any Vector support beyond SysTick + and wish to save memory. This applies only to ARMv7-M architectures. + +# Clock options + +choice + prompt "SysTick clock source" + depends on STM32_COMMON_F0_L0_G0_C0 + default STM32_SYSTICK_CORECLK + +config STM32_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config STM32_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + +config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + default n + ---help--- + Enables special, board-specific STM32 clock configuration. + +# Power options + +config STM32_FORCEPOWER + bool "Force power" + default n + ---help--- + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). + +# Debug MCU options + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + bool + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + bool diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim new file mode 100644 index 0000000000000..05d214b4c6833 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -0,0 +1,4210 @@ +# +# STM32 common TIM options. +# + +# STM32 timer configuration options. + +# LPTIM per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_LPTIM1_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_HAVE_CH1NOUT + bool + default y if STM32_LPTIM1_HAVE_CH1OUT && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1NOUT + bool + default y if STM32_LPTIM2_HAVE_CH1OUT && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_CAP + bool + default n + +config STM32_PULSECOUNT + bool + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_QE + bool + default n + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN + bool + default y if STM32_HAVE_QENCODER_MAIN && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_PWM + bool + +menu "Timer Configuration" + depends on STM32_HAVE_LPTIM_CHANNEL || STM32_HAVE_TIM_ADC_CHANNEL + +if STM32_LPTIM1_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM1_CHANNEL1 + bool "LPTIM1 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM1_PWM + +if STM32_LPTIM2_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM2_CHANNEL1 + bool "LPTIM2 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM2_PWM + +config STM32_TIM1_ADC_CHAN + int "TIM1 channel" + default 1 + range 1 4 + depends on STM32_TIM1_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM2_ADC_CHAN + int "TIM2 channel" + default 1 + range 1 4 + depends on STM32_TIM2_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM3_ADC_CHAN + int "TIM3 channel" + default 1 + range 1 4 + depends on STM32_TIM3_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM4_ADC_CHAN + int "TIM4 channel" + default 1 + range 1 4 + depends on STM32_TIM4_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM6_ADC_CHAN + int "TIM6 channel" + default 1 + range 1 4 + depends on STM32_TIM6_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM8_ADC_CHAN + int "TIM8 channel" + default 1 + range 1 4 + depends on STM32_TIM8_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM15_ADC_CHAN + int "TIM15 channel" + default 1 + range 1 4 + depends on STM32_TIM15_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +endmenu # Timer Configuration + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM5 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM9 && STM32_DAC + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM10 && STM32_DAC + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM11 && STM32_DAC + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM12 && STM32_DAC + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM13 && STM32_DAC + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM14 && STM32_DAC + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice + +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice + +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_HAVE_TIM_PWM_SINGLECHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_HAVE_IP_TIMERS && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_HAVE_IP_TIMERS && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_HAVE_IP_TIMERS && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_HAVE_IP_TIMERS && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +menu "Timer Configuration" + depends on STM32_TIM + +if STM32_TIM9_CAP + +config STM32_TIM9_CLOCK + int "TIM9 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM9_CAP + +if STM32_TIM10_CAP + +config STM32_TIM10_CLOCK + int "TIM10 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM10_CAP + +if STM32_TIM11_CAP + +config STM32_TIM11_CLOCK + int "TIM11 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM11_CAP + +endmenu # Timer Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.uart b/arch/arm/src/common/stm32/Kconfig.uart new file mode 100644 index 0000000000000..55834acea4d7f --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.uart @@ -0,0 +1,1250 @@ +# +# STM32 common SERIAL options. +# + +# STM32 USART/UART configuration options. + +# USART/UART per-instance capability flags +# (hidden; driven by default y if / peripheral selects, never by chip selectors) + +config STM32_USART1_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_WB_PERIPHERALS && (STM32_DMA) + +config STM32_USART1_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART2_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART2_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART3_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART3_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART4_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART4_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART5_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART5_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART6_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_USART6_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_UART7_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART7_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_1WIREDRIVER + bool + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration + +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration + +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration + +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration + +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +choice + prompt "UART8 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +if UART9_SERIALDRIVER + +config UART9_RS485 + bool "RS-485 on UART9" + default n + depends on STM32_UART9 + ---help--- + Enable RS-485 interface on UART9. Your board config will have to + provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be + used with UART9_RXDMA. + +config UART9_RS485_DIR_POLARITY + int "UART9 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART9_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART9_RXDMA + bool "UART9 RX DMA" + default n + depends on STM32_UART9 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART9_SERIALDRIVER + +if USART10_SERIALDRIVER + +config USART10_RS485 + bool "RS-485 on USART10" + default n + depends on STM32_USART10 + ---help--- + Enable RS-485 interface on USART10. Your board config will have to + provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be + used with USART10_RXDMA. + +config USART10_RS485_DIR_POLARITY + int "USART10 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART10_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART10_RXDMA + bool "USART10 RX DMA" + default n + depends on STM32_USART10 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART10_SERIALDRIVER + +if USART11_SERIALDRIVER + +config USART11_RS485 + bool "RS-485 on USART11" + default n + depends on STM32_USART11 + ---help--- + Enable RS-485 interface on USART11. Your board config will have to + provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be + used with USART11_RXDMA. + +config USART11_RS485_DIR_POLARITY + int "USART11 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART11_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART11_RXDMA + bool "USART11 RX DMA" + default n + depends on STM32_USART11 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART11_SERIALDRIVER + +if UART12_SERIALDRIVER + +config UART12_RS485 + bool "RS-485 on UART12" + default n + depends on STM32_UART12 + ---help--- + Enable RS-485 interface on UART12. Your board config will have to + provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be + used with UART12_RXDMA. + +config UART12_RS485_DIR_POLARITY + int "UART12 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART12_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART12_RXDMA + bool "UART12 RX DMA" + default n + depends on STM32_UART12 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART12_SERIALDRIVER + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART1_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART2_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +if STM32_USART3 + +config USART3_RXFIFO_THRES + int "USART3 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART3 + +if STM32_UART4 + +config UART4_RXFIFO_THRES + int "UART4 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART4 + +if STM32_UART5 + +config UART5_RXFIFO_THRES + int "UART5 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART5 + +if STM32_USART6 + +config USART6_RXFIFO_THRES + int "USART6 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART + +if STM32_UART7 + +config UART7_RXFIFO_THRES + int "UART7 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART7 + +if STM32_UART8 + +config UART8_RXFIFO_THRES + int "UART8 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART8 + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +source "arch/arm/src/common/stm32/Kconfig.lpuart" +source "arch/arm/src/common/stm32/Kconfig.hciuart" diff --git a/arch/arm/src/common/stm32/Kconfig.usb b/arch/arm/src/common/stm32/Kconfig.usb new file mode 100644 index 0000000000000..77093092736d0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.usb @@ -0,0 +1,255 @@ +# +# STM32 common USB options. +# + +# STM32 USB configuration options. + +comment "USB Device Configuration" + +comment "USB Host Configuration" + +menu "USB Full Speed Host Configuration" + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + +config STM32_USBDRD_NCHANNELS + int "Number of host channels" + default 8 + range 1 8 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Number of USB host channels to use. + +config STM32_USBDRD_DESCSIZE + int "Descriptor buffer size" + default 128 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Size of descriptor/request buffers. + +endmenu + +config STM32_OTG_SOFOUTPUT + bool "OTG SOF output" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_OTG_USBREGEN + bool "Enable USB voltage regulator" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +comment "USB Device Configuration" + +config STM32_USB_ITRMP + bool "Re-map USB interrupt" + default STM32_CAN1 + depends on STM32_USB && STM32_STM32F30XX + ---help--- + The legacy USB in the F1 series shared interrupt lines with USB + device and CAN1. In the F3 series, a hardware options was added to + either retain the legacy F1 behavior or to map the USB interrupts to + their own dedicated vectors. The option is available only for the + F3 family and selects the use of the dedicated USB interrupts. diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index b8bcda25eeeb8..f8c9957e95433 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2099,2330 +2099,3 @@ config STM32_STM32G474V select STM32_HAVE_SPI4 select STM32_HAVE_UART4 select STM32_HAVE_UART5 - -menu "STM32 Peripheral Support" - -# These are the peripheral selections proper - -config STM32_ADC5 - bool "ADC5" - default n - select STM32_ADC - depends on STM32_HAVE_ADC5 - select STM32_HAVE_ADC5_DMA if STM32_DMA2 - select STM32_HAVE_ADC5_DMA if STM32_DMAMUX - -config STM32_SDADC1 - bool "SDADC1" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC1_DMA if STM32_DMA2 - -config STM32_SDADC2 - bool "SDADC2" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC2_DMA if STM32_DMA2 - -config STM32_SDADC3 - bool "SDADC3" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC3 - select STM32_HAVE_SDADC3_DMA if STM32_DMA2 - -config STM32_COMP3 - bool "COMP3" - default n - select STM32_COMP - depends on STM32_HAVE_COMP3 - -config STM32_COMP4 - bool "COMP4" - default n - select STM32_COMP - depends on STM32_HAVE_COMP4 - -config STM32_COMP5 - bool "COMP5" - default n - select STM32_COMP - depends on STM32_HAVE_COMP5 - -config STM32_COMP6 - bool "COMP6" - default n - select STM32_COMP - depends on STM32_HAVE_COMP6 - -config STM32_COMP7 - bool "COMP7" - default n - select STM32_COMP - depends on STM32_HAVE_COMP7 - -config STM32_CCMDATARAM - bool "CMD/DATA RAM" - default n - depends on STM32_STM32F4XXX - -if STM32_DAC1 - -config STM32_DAC1CH1 - bool "DAC1CH1" - default n - -config STM32_DAC1CH2 - bool "DAC1CH2" - default n - -endif #STM32_DAC1 - -if STM32_DAC2 - -config STM32_DAC2CH1 - bool "DAC2CH1" - default n - -endif #STM32_DAC2 - -config STM32_DAC3 - bool "DAC3" - default n - depends on STM32_HAVE_DAC3 - select STM32_DAC - -if STM32_DAC3 - -config STM32_DAC3CH1 - bool "DAC3CH1 Internal" - default n - -config STM32_DAC3CH2 - bool "DAC3CH2 Internal" - default n - -endif #STM32_DAC3 - -config STM32_DAC4 - bool "DAC4" - default n - depends on STM32_HAVE_DAC4 - select STM32_DAC - -if STM32_DAC4 - -config STM32_DAC4CH1 - bool "DAC4CH1 Internal" - default n - -config STM32_DAC4CH2 - bool "DAC4CH2 Internal" - default n - -endif #STM32_DAC4 - -config STM32_HRTIM - bool - default n - -config STM32_HRTIM1 - bool "HRTIM1" - default n - depends on STM32_HAVE_HRTIM1 - select STM32_HRTIM - -if STM32_HRTIM1 - -config STM32_HRTIM_MASTER - bool "HRTIM MASTER" - default n - ---help--- - Enable HRTIM Master Timer - -config STM32_HRTIM_TIMA - bool "HRTIM TIMA" - default n - ---help--- - Enable HRTIM Timer A - -config STM32_HRTIM_TIMB - bool "HRTIM TIMB" - default n - ---help--- - Enable HRTIM Timer B - -config STM32_HRTIM_TIMC - bool "HRTIM TIMC" - default n - ---help--- - Enable HRTIM Timer C - -config STM32_HRTIM_TIMD - bool "HRTIM TIMD" - default n - ---help--- - Enable HRTIM Timer D - -config STM32_HRTIM_TIME - bool "HRTIM TIME" - default n - ---help--- - Enable HRTIM Timer E - -endif # STM32_HRTIM - -config STM32_I2C1_SLAVE - bool "I2C1 Slave" - default n - depends on !STM32_I2C1 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C2_SLAVE - bool "I2C2 Slave" - default n - depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C3_SLAVE - bool "I2C3 Slave" - default n - depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_OPAMP1 - bool "OPAMP1" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP1 - -config STM32_OPAMP2 - bool "OPAMP2" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP2 - -config STM32_OPAMP3 - bool "OPAMP3" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP3 - -config STM32_OPAMP4 - bool "OPAMP4" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP4 - -config STM32_UCPD - bool "UCPD (USB Type C Power Delivery)" - default n - depends on STM32_HAVE_UCPD - select USBDEV - -if STM32_LCD - -choice - prompt "Segment LCD Clock Source" - default LCD_LSECLOCK - -config LCD_LSICLOCK - bool "Internal Low Speed Clock" - -config LCD_LSECLOCK - bool "External Low Speed Clock" - -config LCD_HSECLOCK - bool "External High Speed Clock" - -endchoice -endif # STM32_LCD - -endmenu - -config STM32_SDADC - bool - default n - -config STM32_I2C_SLAVE - bool - default n - -config STM32_CAP - bool - default n - -config STM32_NOEXT_VECTORS - bool "Disable the ARMv7-M EXT vectors" - default n - ---help--- - Sometimes you may not need any Vector support beyond SysTick - and wish to save memory. This applies only to ARMv7-M architectures. - -menu "Alternate Pin Mapping" - depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE - -choice - prompt "CAN1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_CAN1 - default STM32_CAN1_NO_REMAP - -config STM32_CAN1_NO_REMAP - bool "No pin remapping" - -config STM32_CAN1_REMAP1 - bool "CAN1 alternate pin remapping #1" - -config STM32_CAN1_REMAP2 - bool "CAN1 alternate pin remapping #2" - -endchoice - -config STM32_CAN2_REMAP - bool "CAN2 Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_CAN2 - -config STM32_CEC_REMAP - bool "CEC Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_CEC - -config STM32_ETH_REMAP - bool "Ethernet Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC - -config STM32_I2C1_REMAP - bool "I2C1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2C1 - -config STM32_SPI1_REMAP - bool "SPI1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI1 - -config STM32_SPI3_REMAP - bool "SPI3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE - -config STM32_I2S3_REMAP - bool "I2S3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE - -choice - prompt "TIM1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM1 - default STM32_TIM1_NO_REMAP - -config STM32_TIM1_NO_REMAP - bool "No pin remapping" - -config STM32_TIM1_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM1_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -choice - prompt "TIM2 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM2 - default STM32_TIM2_NO_REMAP - -config STM32_TIM2_NO_REMAP - bool "No pin remapping" - -config STM32_TIM2_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM2_PARTIAL_REMAP_1 - bool "Partial pin remapping #1" - -config STM32_TIM2_PARTIAL_REMAP_2 - bool "Partial pin remapping #2" - -endchoice - -choice - prompt "TIM3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM3 - default STM32_TIM3_NO_REMAP - -config STM32_TIM3_NO_REMAP - bool "No pin remapping" - -config STM32_TIM3_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -config STM32_TIM4_REMAP - bool "TIM4 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM4 - -config STM32_TIM9_REMAP - bool "TIM9 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM9 - -config STM32_TIM10_REMAP - bool "TIM10 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM10 - -config STM32_TIM11_REMAP - bool "TIM11 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM11 - -config STM32_TIM12_REMAP - bool "TIM12 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM12 - -config STM32_TIM13_REMAP - bool "TIM13 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM13 - -config STM32_TIM14_REMAP - bool "TIM14 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM14 - -config STM32_TIM15_REMAP - bool "TIM15 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM15 - -config STM32_TIM16_REMAP - bool "TIM16 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM16 - -config STM32_TIM17_REMAP - bool "TIM17 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM17 - -config STM32_USART1_REMAP - bool "USART1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART1 - -config STM32_USART2_REMAP - bool "USART2 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART2 - -choice - prompt "USART3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_USART3 - default STM32_USART3_NO_REMAP - -config STM32_USART3_NO_REMAP - bool "No pin remapping" - -config STM32_USART3_FULL_REMAP - bool "Full pin remapping" - -config STM32_USART3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -endmenu - -config STM32_FLASH_ICACHE - bool "Enable FLASH Instruction Cache" - default y - depends on STM32_HAVE_FLASH_ICACHE - ---help--- - Enable the FLASH instruction cache. - -config STM32_FLASH_DCACHE - bool "Enable FLASH Data Cache" - default y - depends on STM32_HAVE_FLASH_DCACHE - ---help--- - Enable the FLASH data cache. - -config STM32_FORCEPOWER - bool "Force power" - default n - ---help--- - Timer and I2C devices may need to the following to force power to be applied - unconditionally at power up. (Otherwise, the device is powered when it is - initialized). - -config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_SAIPLL - bool "SAIPLL" - default n - depends on STM32_HAVE_SAIPLL - ---help--- - The STM32F446 has a separate PLL for the SAI block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_I2SPLL - bool "I2SPLL" - default n - depends on STM32_HAVE_I2SPLL - ---help--- - The STM32F446 has a separate PLL for the I2S block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_CCMEXCLUDE - bool "Exclude CCM SRAM from the heap" - default ARCH_DMA || LIBC_ARCH_ELF - depends on STM32_HAVE_CCM - ---help--- - Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA - and (2) it appears to be impossible to execute ELF modules from CCM - RAM. - -config STM32_CCM_PROCFS - bool "CCM PROCFS support" - default n - depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER - ---help--- - Select to build in support for /proc/ccm. Reading from /proc/ccm - will provide statistics about CCM memory use similar to what you - would get from mallinfo() for the user heap. - -menu "Timer Configuration" - depends on STM32_TIM - -if STM32_TIM9_CAP - -config STM32_TIM9_CLOCK - int "TIM9 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM9_CAP - -if STM32_TIM10_CAP - -config STM32_TIM10_CLOCK - int "TIM10 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM10_CAP - -if STM32_TIM11_CAP - -config STM32_TIM11_CLOCK - int "TIM11 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM11_CAP - -endmenu # Timer Configuration - -menu "HRTIM Configuration" - depends on STM32_HRTIM - -config STM32_HRTIM_DISABLE_CHARDRV - bool "HRTIM Disable Character Driver" - default n - ---help--- - In most cases we do not need HRTIM Character Driver, so we can disable it - and save some memory. - -config STM32_HRTIM_NO_ENABLE_TIMERS - bool "Do not enable HRTIM timers at startup" - default n - ---help--- - Do not enable HRTIM timers at startup - -menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Triggering" - default n - ---help--- - Enable HRTIM ADC Triggering support. - -if STM32_HRTIM_ADC - -config STM32_HRTIM_ADC1_TRG1 - bool "HRTIM ADC1 Trigger 1" - default n - -config STM32_HRTIM_ADC1_TRG2 - bool "HRTIM ADC1 Trigger 2" - default n - -config STM32_HRTIM_ADC1_TRG3 - bool "HRTIM ADC1 Trigger 3" - default n - -config STM32_HRTIM_ADC1_TRG4 - bool "HRTIM ADC1 Trigger 4" - default n - -config STM32_HRTIM_ADC2_TRG1 - bool "HRTIM ADC2 Trigger 1" - default n - -config STM32_HRTIM_ADC2_TRG2 - bool "HRTIM ADC2 Trigger 2" - default n - -config STM32_HRTIM_ADC2_TRG3 - bool "HRTIM ADC2 Trigger 3" - default n - -config STM32_HRTIM_ADC2_TRG4 - bool "HRTIM ADC2 Trigger 4" - default n - -endif # STM32_HRTIM_ADC - -config STM32_HRTIM_DAC - bool "HRTIM DAC Triggering" - default n - ---help--- - Enable HRTIM DAC Triggering support. - -config STM32_HRTIM_PWM - bool "HRTIM PWM Outputs" - default n - ---help--- - Enable HRTIM PWM Outputs support. - -config STM32_HRTIM_CAP - bool "HRTIM Capture" - default n - ---help--- - Enable HRTIM Capture support. - -config STM32_HRTIM_INTERRUPTS - bool "HRTIM Interrupts" - default n - ---help--- - Enable HRTIM Interrupts support. - -config STM32_HRTIM_BURST - bool "HRTIM Burst Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Burst Mode support for PWM outputs. - -config STM32_HRTIM_DEADTIME - bool "HRTIM Dead-time" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Deadtime support for PWM outputs. - -config STM32_HRTIM_PUSHPULL - bool "HRTIM Push-Pull Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Push-Pull Mode support for PWM outputs. - -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Chopper Mode for PWM outputs. - -config STM32_HRTIM_DMA - bool "HRTIM DMA" - default n - -config STM32_HRTIM_DMABURST - bool "HRTIM DMA Burst" - default n - -config STM32_HRTIM_AUTODELAY - bool "HRTIM Autodelay" - depends on STM32_HRTIM_PWM - default n - -menuconfig STM32_HRTIM_EVENTS - bool "HRTIM Events Configuration" - default n - ---help--- - Enable HRTIM Events support. - -if STM32_HRTIM_EVENTS - -config STM32_HRTIM_EEV1 - bool "HRTIM EEV1" - default n - -config STM32_HRTIM_EEV2 - bool "HRTIM EEV2" - default n - -config STM32_HRTIM_EEV3 - bool "HRTIM EEV3" - default n - -config STM32_HRTIM_EEV4 - bool "HRTIM EEV4" - default n - -config STM32_HRTIM_EEV5 - bool "HRTIM EEV5" - default n - -config STM32_HRTIM_EEV6 - bool "HRTIM EEV6" - default n - -config STM32_HRTIM_EEV7 - bool "HRTIM EEV7" - default n - -config STM32_HRTIM_EEV8 - bool "HRTIM EEV8" - default n - -config STM32_HRTIM_EEV9 - bool "HRTIM EEV9" - default n - -config STM32_HRTIM_EEV10 - bool "HRTIM EEV10" - default n - -endif # STM32_HRTIM_EVENTS - -menuconfig STM32_HRTIM_FAULTS - bool "HRTIM Faults Configuration" - default n - ---help--- - Enable HRTIM Faults support. - -if STM32_HRTIM_FAULTS - -config STM32_HRTIM_FAULT1 - bool "HRTIM Fault 1" - default n - -config STM32_HRTIM_FAULT2 - bool "HRTIM Fault 2" - default n - -config STM32_HRTIM_FAULT3 - bool "HRTIM Fault 3" - default n - -config STM32_HRTIM_FAULT4 - bool "HRTIM Fault 4" - default n - -endif # STM32_HRTIM_FAULTS - -config STM32_HRTIM_CLK_FROM_PLL - bool "HRTIM Clock from PLL" - default n - depends on STM32_HAVE_HRTIM1_PLLCLK - ---help--- - Set PLL as the clock source for HRTIM. - This configuration requires the following conditions: - 1) system clock is PLL, - 2) SYSCLK and PCLK2 ratio must be 1 o 2. - -menu "HRTIM Master Configuration" - depends on STM32_HRTIM_MASTER - -config STM32_HRTIM_MASTER_DAC - bool "HRTIM Master DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_MASTER_DMA - bool "HRTIM MASTER DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_MASTER_IRQ - bool "HRTIM MASTER Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -endmenu # "HRTIM Master Configuration" - -menu "HRTIM Timer A Configuration" - depends on STM32_HRTIM_TIMA - -config STM32_HRTIM_TIMA_CAP - bool "HRTIM TIMA Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMA_DAC - bool "HRTIM TIMA DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMA_DMA - bool "HRTIM TIMA DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMA_IRQ - bool "HRTIM TIMA Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMA_PWM - bool "HRTIM TIMA PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMA_PWM_CH1 - bool "HRTIM TIMA PWM Output 1" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_PWM_CH2 - bool "HRTIM TIMA PWM Output 2" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_BURST - bool "HRTIM TIMA Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_BURST_CH1 - bool "HRTIM TIMA Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) - -config STM32_HRTIM_TIMA_BURST_CH2 - bool "HRTIM TIMA Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) - -config STM32_HRTIM_TIMA_CHOP - bool "HRTIM TIMA PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_DT - bool "HRTIM TIMA PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_PSHPLL - bool "HRTIM TIMA PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) - -endmenu # "HRTIM Timer A Configuration" - -menu "HRTIM Timer B Configuration" - depends on STM32_HRTIM_TIMB - -config STM32_HRTIM_TIMB_CAP - bool "HRTIM TIMB Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMB_DAC - bool "HRTIM TIMB DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMB_DMA - bool "HRTIM TIMB DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMB_IRQ - bool "HRTIM TIMB Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMB_PWM - bool "HRTIM TIMB PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMB_PWM_CH1 - bool "HRTIM TIMB PWM Output 1" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_PWM_CH2 - bool "HRTIM TIMB PWM Output 2" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_BURST - bool "HRTIM TIMB Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_BURST_CH1 - bool "HRTIM TIMB Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) - -config STM32_HRTIM_TIMB_BURST_CH2 - bool "HRTIM TIMB Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) - -config STM32_HRTIM_TIMB_CHOP - bool "HRTIM TIMB PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_DT - bool "HRTIM TIMB PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_PSHPLL - bool "HRTIM TIMB PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) - -endmenu # "HRTIM Timer B Configuration" - -menu "HRTIM Timer C Configuration" - depends on STM32_HRTIM_TIMC - -config STM32_HRTIM_TIMC_CAP - bool "HRTIM TIMC Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMC_DAC - bool "HRTIM TIMC DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMC_DMA - bool "HRTIM TIMC DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMC_IRQ - bool "HRTIM TIMC Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMC_PWM - bool "HRTIM TIMC PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMC_PWM_CH1 - bool "HRTIM TIMC PWM Output 1" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_PWM_CH2 - bool "HRTIM TIMC PWM Output 2" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_BURST - bool "HRTIM TIMC Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_BURST_CH1 - bool "HRTIM TIMC Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) - -config STM32_HRTIM_TIMC_BURST_CH2 - bool "HRTIM TIMC Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) - -config STM32_HRTIM_TIMC_CHOP - bool "HRTIM TIMC PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_DT - bool "HRTIM TIMC PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_PSHPLL - bool "HRTIM TIMC PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) - -endmenu # "HRTIM Timer C Configuration" - -menu "HRTIM Timer D Configuration" - depends on STM32_HRTIM_TIMD - -config STM32_HRTIM_TIMD_CAP - bool "HRTIM TIMD Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMD_DAC - bool "HRTIM TIMD DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMD_DMA - bool "HRTIM TIMD DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMD_IRQ - bool "HRTIM TIMD Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMD_PWM - bool "HRTIM TIMD PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMD_PWM_CH1 - bool "HRTIM TIMD PWM Output 1" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_PWM_CH2 - bool "HRTIM TIMD PWM Output 2" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_BURST - bool "HRTIM TIMD Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_BURST_CH1 - bool "HRTIM TIMD Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - -config STM32_HRTIM_TIMD_BURST_CH2 - bool "HRTIM TIMD Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) - -config STM32_HRTIM_TIMD_CHOP - bool "HRTIM TIMD PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_DT - bool "HRTIM TIMD PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_PSHPLL - bool "HRTIM TIMD PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) - -endmenu # "HRTIM Timer D Configuration" - -menu "HRTIM Timer E Configuration" - depends on STM32_HRTIM_TIME - -config STM32_HRTIM_TIME_CAP - bool "HRTIM TIME Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIME_DAC - bool "HRTIM TIME DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIME_DMA - bool "HRTIM TIME DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIME_IRQ - bool "HRTIM TIME Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIME_PWM - bool "HRTIM TIME PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIME_PWM_CH1 - bool "HRTIM TIME PWM Output 1" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_PWM_CH2 - bool "HRTIM TIME PWM Output 2" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_BURST - bool "HRTIM TIME Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_BURST_CH1 - bool "HRTIM TIME Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) - -config STM32_HRTIM_TIME_BURST_CH2 - bool "HRTIM TIME Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) - -config STM32_HRTIM_TIME_CHOP - bool "HRTIM TIME PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_DT - bool "HRTIM TIME PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_PSHPLL - bool "HRTIM TIME PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) - -endmenu # "HRTIM Timer E Configuration" - -endmenu # "HRTIM Configuration" - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC4_RESOLUTION - int "ADC4 resolution" - depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC5_RESOLUTION - int "ADC5 resolution" - depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC4_DMA - bool "ADC4 DMA" - depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC4_DMA_CFG - int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode - -config STM32_ADC4_DMA_BATCH - int "ADC4 DMA number of conversions" - depends on STM32_ADC4 && STM32_ADC4_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_ANIOC_TRIGGER - int "ADC4 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC4 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC5_DMA - bool "ADC5 DMA" - depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC5_DMA_CFG - int "ADC5 DMA configuration" - depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode - -config STM32_ADC5_DMA_BATCH - int "ADC5 DMA number of conversions" - depends on STM32_ADC5 && STM32_ADC5_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_INJECTED_CHAN - int "ADC4 injected channels" - depends on STM32_ADC4 - range 0 4 - default 0 - ---help--- - Support for ADC4 injected channels. - -config STM32_ADC5_INJECTED_CHAN - int "ADC5 injected channels" - depends on STM32_ADC5 - range 0 4 - default 0 - ---help--- - Support for ADC5 injected channels. - -config STM32_ADC4_EXTSEL - bool "ADC4 external trigger for regular group" - depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER - default n - ---help--- - Enable EXTSEL for ADC4. - -config STM32_ADC5_EXTSEL - bool "ADC5 external trigger for regular group" - depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER - default n - ---help--- - Enable EXTSEL for ADC5. - -config STM32_ADC4_JEXTSEL - bool "ADC4 external trigger for injected group" - depends on STM32_ADC4 - default n - ---help--- - Enable JEXTSEL for ADC4. - -config STM32_ADC5_JEXTSEL - bool "ADC5 external trigger for injected group" - depends on STM32_ADC5 - default n - ---help--- - Enable JEXTSEL for ADC5. - -endmenu - -menu "COMP Configuration" - depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 - -config STM32_COMP1_OUT - bool "COMP1 GPIO Output" - depends on STM32_COMP1 - default n - ---help--- - Enables COMP1 output. - -config STM32_COMP1_INM - int "COMP1 inverting input assignment" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects COMP1 inverting input pin. - -config STM32_COMP1_INP - int "COMP1 non-inverting input assignment" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 non-inverting input pin. - -config STM32_COMP1_POL - int "COMP1 polarity" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 output polarity. - -config STM32_COMP1_HYST - int "COMP1 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP1. - -config STM32_COMP1_BLANKSEL - int "COMP1 blanking signal select" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP1. - -config STM32_COMP1_LOCK - int "COMP1 COMP_CxCSR register lock" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP2_OUT - bool "COMP2 GPIO Output" - depends on STM32_COMP2 - default n - ---help--- - Enables COMP2 output. - -config STM32_COMP2_INM - int "COMP2 inverting input assignment" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects COMP2 inverting input pin. - -config STM32_COMP2_INP - int "COMP2 non-inverting input assignment" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 non-inverting input pin. - -config STM32_COMP2_POL - int "COMP2 polarity" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 output polarity. - -config STM32_COMP2_HYST - int "COMP2 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP2. - -config STM32_COMP2_BLANKSEL - int "COMP2 blanking signal select" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP2. - -config STM32_COMP2_LOCK - int "COMP2 COMP_CxCSR register lock" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP3_OUT - bool "COMP3 GPIO Output" - depends on STM32_COMP3 - default n - ---help--- - Enables COMP3 output. - -config STM32_COMP3_INM - int "COMP3 inverting input assignment" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects COMP3 inverting input pin. - -config STM32_COMP3_INP - int "COMP3 non-inverting input assignment" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 non-inverting input pin. - -config STM32_COMP3_POL - int "COMP3 polarity" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 output polarity. - -config STM32_COMP3_HYST - int "COMP3 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP3. - -config STM32_COMP3_BLANKSEL - int "COMP3 blanking signal select" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP3. - -config STM32_COMP3_LOCK - int "COMP3 COMP_CxCSR register lock" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP4_OUT - bool "COMP4 GPIO Output" - depends on STM32_COMP4 - default n - ---help--- - Enables COMP4 output. - -config STM32_COMP4_INM - int "COMP4 inverting input assignment" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects COMP4 inverting input pin. - -config STM32_COMP4_INP - int "COMP4 non-inverting input assignment" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 non-inverting input pin. - -config STM32_COMP4_POL - int "COMP4 polarity" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 output polarity. - -config STM32_COMP4_HYST - int "COMP4 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP4. - -config STM32_COMP4_BLANKSEL - int "COMP4 blanking signal select" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP4. - -config STM32_COMP4_LOCK - int "COMP4 COMP_CxCSR register lock" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP5_OUT - bool "COMP5 GPIO Output" - depends on STM32_COMP5 - default n - ---help--- - Enables COMP5 output. - -config STM32_COMP5_INM - int "COMP5 inverting input assignment" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects COMP5 inverting input pin. - -config STM32_COMP5_INP - int "COMP5 non-inverting input assignment" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 non-inverting input pin. - -config STM32_COMP5_POL - int "COMP5 polarity" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 output polarity. - -config STM32_COMP5_HYST - int "COMP5 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP5. - -config STM32_COMP5_BLANKSEL - int "COMP5 blanking signal select" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP5. - -config STM32_COMP5_LOCK - int "COMP5 COMP_CxCSR register lock" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP6_OUT - bool "COMP6 GPIO Output" - depends on STM32_COMP6 - default n - ---help--- - Enables COMP6 output. - -config STM32_COMP6_INM - int "COMP6 inverting input assignment" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects COMP6 inverting input pin. - -config STM32_COMP6_INP - int "COMP6 non-inverting input assignment" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 non-inverting input pin. - -config STM32_COMP6_POL - int "COMP6 polarity" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 output polarity. - -config STM32_COMP6_HYST - int "COMP6 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP6. - -config STM32_COMP6_BLANKSEL - int "COMP6 blanking signal select" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP6. - -config STM32_COMP6_LOCK - int "COMP6 COMP_CxCSR register lock" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP7_OUT - bool "COMP7 GPIO Output" - depends on STM32_COMP7 - default n - ---help--- - Enables COMP7 output. - -config STM32_COMP7_INM - int "COMP7 inverting input assignment" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects COMP7 inverting input pin. - -config STM32_COMP7_INP - int "COMP7 non-inverting input assignment" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 non-inverting input pin. - -config STM32_COMP7_POL - int "COMP7 polarity" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 output polarity. - -config STM32_COMP7_HYST - int "COMP7 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP7. - -config STM32_COMP7_BLANKSEL - int "COMP7 blanking signal select" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP7. - -config STM32_COMP7_LOCK - int "COMP7 COMP_CxCSR register lock" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -endmenu - -menu "SDADC Configuration" - depends on STM32_SDADC - -config STM32_SDADC1_DMA - bool "SDADC1 DMA" - depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC2_DMA - bool "SDADC2 DMA" - depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC3_DMA - bool "SDADC3 DMA" - depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -menu "DAC Configuration" - depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 - -config STM32_DAC1CH1_MODE - int "DAC1CH1 channel mode" - depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH1_DMA - bool "DAC1CH1 DMA" - depends on STM32_DAC1CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH1_DMA - -config STM32_DAC1CH1_DMA_BUFFER_SIZE - int "DAC1CH1 DMA buffer size" - default 256 - -config STM32_DAC1CH1_DMA_EXTERNAL - bool "DAC1CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH1_HRTIM_TRG1 - bool "DAC1CH1 HRTIM Trigger 1" - default n - -config STM32_DAC1CH1_HRTIM_TRG2 - bool "DAC1CH1 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH1_TIMER - int "DAC1CH1 timer" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH1_TIMER_FREQUENCY - int "DAC1CH1 timer frequency" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC1CH2_MODE - int "DAC1CH2 channel mode" - depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH2_DMA - bool "DAC1CH2 DMA" - depends on STM32_DAC1CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH2_DMA - -config STM32_DAC1CH2_DMA_BUFFER_SIZE - int "DAC1CH2 DMA buffer size" - default 256 - -config STM32_DAC1CH2_DMA_EXTERNAL - bool "DAC1CH2 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH2_HRTIM_TRG1 - bool "DAC1CH2 HRTIM Trigger 1" - default n - -config STM32_DAC1CH2_HRTIM_TRG2 - bool "DAC1CH2 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH2_TIMER - int "DAC1CH2 timer" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH2_TIMER_FREQUENCY - int "DAC1CH2 timer frequency" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC2CH1_MODE - int "DAC2CH1 channel mode" - depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC2CH1_DMA - bool "DAC2CH1 DMA" - depends on STM32_DAC2CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC2CH1_DMA - -config STM32_DAC2CH1_DMA_BUFFER_SIZE - int "DAC2CH1 DMA buffer size" - default 256 - -config STM32_DAC2CH1_DMA_EXTERNAL - bool "DAC2CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC2CH1_HRTIM_TRG3 - bool "DAC2CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC2CH1_TIMER - int "DAC2CH1 timer" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC2CH1_TIMER_FREQUENCY - int "DAC2CH1 timer frequency" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH1_MODE - int "DAC3CH1 channel mode" - depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH1_DMA - bool "DAC3CH1 DMA" - depends on STM32_DAC3CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH1_DMA - -config STM32_DAC3CH1_DMA_BUFFER_SIZE - int "DAC3CH1 DMA buffer size" - default 256 - -config STM32_DAC3CH1_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH1_HRTIM_TRG3 - bool "DAC3CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH1_TIMER - int "DAC3CH1 timer" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH1_TIMER_FREQUENCY - int "DAC3CH1 timer frequency" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH2_MODE - int "DAC3CH2 channel mode" - depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH2_DMA - bool "DAC3CH2 DMA" - depends on STM32_DAC3CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH2_DMA - -config STM32_DAC3CH2_DMA_BUFFER_SIZE - int "DAC3CH2 DMA buffer size" - default 256 - -config STM32_DAC3CH2_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH2_HRTIM_TRG3 - bool "DAC3CH2 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH2_TIMER - int "DAC3CH2 timer" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH2_TIMER_FREQUENCY - int "DAC3CH2 timer frequency" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - -endif - -endmenu - -config STM32_HCIUART_RXDMA - bool - default n - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -if STM32_USART1_HCIUART - -config STM32_HCIUART1_RXBUFSIZE - int "HCI UART1 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART1_TXBUFSIZE - int "HCI UART1 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART1_BAUD - int "HCI UART1 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART1_RXDMA - bool "HCI UART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART1_HCIUART - -if STM32_USART2_HCIUART - -config STM32_HCIUART2_RXBUFSIZE - int "HCI UART2 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART2_TXBUFSIZE - int "HCI UART2 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART2_BAUD - int "HCI UART2 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART2_RXDMA - bool "HCI UART2 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART2_HCIUART - -if STM32_USART3_HCIUART - -config STM32_HCIUART3_RXBUFSIZE - int "HCI UART3 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART3_TXBUFSIZE - int "HCI UART3 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART3_BAUD - int "HCI UART3 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART3_RXDMA - bool "HCI UART3 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART3_HCIUART - -if STM32_USART6_HCIUART - -config STM32_HCIUART6_RXBUFSIZE - int "HCI UART6 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART6_TXBUFSIZE - int "HCI UART6 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART6_BAUD - int "HCI UART6 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART6_RXDMA - bool "HCI UART6 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART6_HCIUART - -if STM32_LPUART1_SERIALDRIVER - -config LPUART1_TXDMA - bool "LPUART1 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_LPUART1_SERIALDRIVER - -menu "HCI UART Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_HCIUART_RXDMA_BUFSIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - depends on STM32_HCIUART_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_HCIUART_RXDMAPRIO - hex "HCI UART DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - depends on STM32_HCIUART_RXDMA - ---help--- - Select HCI UART DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_HCIUART_SW_RXFLOW - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Current STM32 have - broken HW based RTS behavior (they assert nRTS after every byte - received) Enable this setting workaround this issue by using - software based management of RTS - - If HCI UART DMA is enabled, this is probably the better selection - as well. In that case, the Rx DMA buffer will avoid Rx overrun due - to short, bursty activity. Software RTS management will probably - result in overall better throughput and should still avoid Rx data - overrun conditions. - -config STM32_HCIUART_UPPER_WATERMARK - int "RTS flow control upper watermark (%)" - default 75 - range 2 100 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be asserted - when this amount of Rx data has been buffered. The amount is - expressed as a percentage of the Rx buffer size. - -config STM32_HCIUART_LOWER_WATERMARK - int "RTS flow control lower watermark (%)" - default 25 - range 1 99 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be de-asserted - when there is less than this amount ofdata in the Rx buffere. The - amount is expressed as a percentage of the Rx buffer size. - -endmenu # HCI UART Driver Configuration - -endmenu # U[S]ART Configuration - -menu "I2S Configuration" - depends on STM32_I2S3 - -config STM32_I2S_MCK - bool "I2S_MCK" - default n - ---help--- - TBD. - -comment "I2S3 Configuration" - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_ALT - bool "Alternate I2C implementation" - default STM32_PERFORMANCELINE - depends on !STM32_STM32F30XX - ---help--- - This selection enables an alternative I2C driver. This alternate - driver implements some rather complex workarounds for errata against - the STM32 F103 "Performance Line". This selection is an option - because: (1) It has not yet been fully verified and (2) It is not - certain that he scope of this workaround is needed only for the F103. - -config STM32_I2C_DUTY16_9 - bool "Frequency with Tlow/Thigh = 16/9" - default n - depends on STM32_I2C - -config STM32_I2C_DMA - bool "I2C DMA Support" - default n - depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED - ---help--- - This option enables the DMA for I2C transfers. - Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the - I2C dma streams, else the default priority level is set to medium. - -endmenu - -menu "I2C Slave Configuration" - depends on STM32_I2C_SLAVE - -config STM32_I2C_SLAVE_DEFAULT_TX - hex "Default TX byte to be sent when the TX buffer is empty" - default 0xFF - -config STM32_I2C_SLAVE_USEWQ - bool "Use work queue to delegate the isr completion status" - default n - ---help--- - With the current upperhalf I2C slave driver implementation, the user - should delegate the callback completion status using a work queue. - However, work queues introduce a delay, so in certain scenarios - it is better to use a custom driver without using a work queue. - -config STM32_I2C_SLAVE_RETRANSFER - bool "The frame is retransferred when stop is issued beforehand" - default n - ---help--- - If stop is issued before the whole frame is transferred, - the tx pointer is reset to 0. - -endmenu - -comment "USB Device Configuration" - -config STM32_USB_ITRMP - bool "Re-map USB interrupt" - default STM32_CAN1 - depends on STM32_USB && STM32_STM32F30XX - ---help--- - The legacy USB in the F1 series shared interrupt lines with USB - device and CAN1. In the F3 series, a hardware options was added to - either retain the legacy F1 behavior or to map the USB interrupts to - their own dedicated vectors. The option is available only for the - F3 family and selects the use of the dedicated USB interrupts. - -config STM32_QE - bool - default n - -if STM32_FOC - -config STM32_FOC_USE_ADC4 - bool - default n - select STM32_ADC4 - select STM32_ADC3_JEXTSEL - -config STM32_FOC_G4_ADCCHAN0_WORKAROUND - bool "FOC G4 ADC channel 0 unwanted conversion workaround" - default n - depends on STM32_STM32G4XXX - ---help--- - Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 - conversion when a regular conversion is interrupted by an injected conversion. - This FOC implementation uses injected conversion to sample phase currents - and allows user to use regular conversion as an auxiliary analog conversion. - In this case, there is a certain probability that regular conversion will be - interrupted by an injected conversion that will lead to an incorrect reading - of phase currents. - - This workaround inserts a dummy conversion at the beginning of the injected - sequence. For more details look at the chip errata documents. - -endif #STM32_FOC diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 3680c9a8ac3ba..5b6849a034ce1 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -1413,122 +1413,3 @@ config STM32_SYSTICK_CORECLK_DIV16 bool "Cortex-M0 core clock divided by 16" endchoice # SysTick clock source - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_VREFINT - bool - default n - -config STM32_HAVE_USART4 - bool - default n - -config STM32_HAVE_USART5 - bool - default n - -config STM32_HAVE_USART7 - bool - default n - -config STM32_HAVE_USART8 - bool - default n - -config STM32_HAVE_LPUART2 - bool - default n - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_CEC - bool - default n - -config STM32_HAVE_SDIO - bool - default n - -config STM32_HAVE_I2S2 - bool - default n - -config STM32_HAVE_UCPD1 - bool - default n - -config STM32_HAVE_UCPD2 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_USART_V1 - bool - default n - -config STM32_HAVE_IP_USART_V2 - bool - default n - -config STM32_HAVE_IP_EXTI_V1 - bool - default n - -config STM32_HAVE_IP_EXTI_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32_VREFINT - bool "Enable VREFINT" - default n - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - default n - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - default n - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - default n - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - default n - depends on STM32_HAVE_USART8 - select STM32_USART - -endmenu # STM32 Peripheral Support - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_CONTINUOUS - bool "Enable ADC1 Continuous Conversion Mode" - default n - depends on STM32_ADC1 - ---help--- - If enabled, the ADC will operate in continuous conversion mode. - Otherwise, it will perform single conversions. - Note: Continuous and discontinuous mode cannot be defined at - the same time - -endmenu # ADC Configuration diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index b8203336b2fde..c1d9712cd83dc 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -11,11 +11,8 @@ config STM32_F7_PERIPHERALS bool default ARCH_CHIP_STM32F7 select STM32_HAVE_ADC1 - select STM32_HAVE_ADC1_DMA select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA select STM32_HAVE_ADC3 - select STM32_HAVE_ADC3_DMA select STM32_HAVE_COMMON_FOC select STM32_HAVE_DAC1 select STM32_HAVE_DAC2 @@ -45,7 +42,6 @@ config STM32_F7_PERIPHERALS select STM32_HAVE_USART3 select STM32_HAVE_USART6 select STM32_HAVE_FLASH_ART_ACCELERATOR - select STM32_HAVE_SDMMC2_DMAPRIO select STM32_HAVE_IP_WDG_M3M4_V1 choice @@ -1196,22 +1192,6 @@ config STM32_STM32F779AX select STM32_HAVE_JPEG select STM32_HAVE_CRYP select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_USART1_RXDMA if STM32_DMA2 - select STM32_HAVE_USART1_TXDMA if STM32_DMA2 - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 - select STM32_HAVE_USART2_TXDMA if STM32_DMA1 - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 - select STM32_HAVE_USART3_TXDMA if STM32_DMA1 - select STM32_HAVE_UART4_RXDMA if STM32_DMA1 - select STM32_HAVE_UART4_TXDMA if STM32_DMA1 - select STM32_HAVE_UART5_RXDMA if STM32_DMA1 - select STM32_HAVE_UART5_TXDMA if STM32_DMA1 - select STM32_HAVE_USART6_RXDMA if STM32_DMA2 - select STM32_HAVE_USART6_TXDMA if STM32_DMA2 - select STM32_HAVE_UART7_RXDMA if STM32_DMA1 - select STM32_HAVE_UART7_TXDMA if STM32_DMA1 - select STM32_HAVE_UART8_RXDMA if STM32_DMA1 - select STM32_HAVE_UART8_TXDMA if STM32_DMA1 select STM32_HAVE_HASH select STM32_HAVE_DFSDM1 select STM32_HAVE_CAN2 diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index b7b5d76bc7ad0..002e693e1a9ec 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -63,14 +63,6 @@ config STM32_STM32H56XXX select STM32_HAVE_FDCAN1 select STM32_HAVE_FDCAN2 select STM32_HAVE_IP_CORDIC_M3M4_V1 - select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART4_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART5_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART6_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART7_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART8_RXDMA if STM32_DMA1 || STM32_DMA2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index fe6c6aa3cb935..caede91b0f612 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -272,7 +272,7 @@ static const struct adc_ops_s g_adcops = # define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ CONFIG_STM32_ADC1_DMA_BATCH) -# ifdef CONFIG_STM32_ADC_H5_ADC1_DMA_CFG +# if CONFIG_STM32_ADC1_DMA_CFG == 1 # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2) # else # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE) @@ -327,7 +327,7 @@ static struct stm32_dev_s g_adcpriv1 = .r_chanbuffer = g_adc1_chanbuffer, .r_dmabuffer = g_adc1_dmabuffer, .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, -# ifdef CONFIG_STM32_ADC_H5_ADC1_DMA_CFG +# if CONFIG_STM32_ADC1_DMA_CFG == 1 .circular = true, # else .circular = false, @@ -2642,4 +2642,3 @@ struct adc_dev_s *stm32_adc_initialize(int intf, } #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ - diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 5316a69a910d1..17a8fc57014c3 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -9,7 +9,8 @@ comment "STM32 H7 Configuration Options" config STM32_H7_PERIPHERALS bool - default y + default ARCH_CHIP_STM32H7 + select STM32_HAVE_DMA1 select STM32_HAVE_DMA2 select STM32_HAVE_I2C1 select STM32_HAVE_I2C2 @@ -408,22 +409,6 @@ config ARCH_CHIP_STM32H755XI select STM32_HAVE_FDCAN2 select STM32_HAVE_CRYP select STM32_HAVE_IP_CRYPTO_H7 - select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART1_TXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART2_TXDMA if STM32_DMA1 - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART3_TXDMA if STM32_DMA1 - select STM32_HAVE_UART4_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART4_TXDMA if STM32_DMA1 - select STM32_HAVE_UART5_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART5_TXDMA if STM32_DMA1 - select STM32_HAVE_USART6_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_USART6_TXDMA if STM32_DMA2 - select STM32_HAVE_UART7_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART7_TXDMA if STM32_DMA1 - select STM32_HAVE_UART8_RXDMA if STM32_DMA1 || STM32_DMA2 - select STM32_HAVE_UART8_TXDMA if STM32_DMA1 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 39f391f230f20..8c7e33356dac8 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -926,11 +926,6 @@ config STM32_STM32L4S9XX select STM32_HAVE_AES select STM32_HAVE_HASH select STM32_HAVE_IP_AES_M3M4_V1 - select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX # Pin/package configurations diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index bece5610c34cf..1aa316fce613b 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -52,11 +52,6 @@ config STM32_STM32L562XX select STM32_HAVE_USART3 select STM32_HAVE_UART4 select STM32_HAVE_UART5 - select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX # Pin/package configurations diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 0f90a5c3ef66c..ddd50dece4b7e 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -129,11 +129,6 @@ config STM32_STM32U585XX select STM32_HAVE_CORDIC select STM32_HAVE_IP_AES_M3M4_V1 select STM32_HAVE_IP_CORDIC_M3M4_V1 - select STM32_HAVE_USART1_RXDMA if STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_USART2_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_USART3_RXDMA if STM32_DMA1 || STM32_DMAMUX - select STM32_HAVE_UART4_RXDMA if STM32_DMA2 || STM32_DMAMUX - select STM32_HAVE_UART5_RXDMA if STM32_DMA2 || STM32_DMAMUX select STM32_HAVE_LPUART1 select STM32_HAVE_USART1 select STM32_HAVE_USART2 diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index f9cdaae492a86..107f025ac2dfa 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -22,7 +22,6 @@ config STM32_WB_PERIPHERALS select STM32_HAVE_SPI1 select STM32_HAVE_SYSCFG select STM32_HAVE_USART1 - select STM32_HAVE_USART1_RXDMA if STM32_DMA choice prompt "STM32 WB Chip Selection" diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig index 27f2e6708bbc3..748044ad5fcd6 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig @@ -52,9 +52,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y CONFIG_STM32_ADC1=y CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 CONFIG_STM32_ADC1_WDG1=y CONFIG_STM32_ADC1_WDG1_HIGHTHRESH=2048 -CONFIG_STM32_ADC_H5_ADC1_DMA_CFG=y CONFIG_STM32_DMA1=y CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig index 68f4df61d6500..e73fc9f8fa830 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -68,9 +68,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_DTCMEXCLUDE=y CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_HSI48=y CONFIG_STM32_PHYSR=31 CONFIG_STM32_PHYSR_100FD=0x0018 diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig index 3c0284fa3b793..11f85e483ede7 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -46,8 +46,8 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_SRAM4EXCLUDE=y CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig index 47a638c77ada6..715f1f0df18b0 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig @@ -74,8 +74,8 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y CONFIG_STM32_SPI3=y CONFIG_STM32_SRAM4EXCLUDE=y CONFIG_STM32_USART3=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index e5d2f3e188fa4..9be0478f7eafb 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -74,9 +74,9 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PHYSR=31 CONFIG_STM32_PHYSR_100FD=0x0018 CONFIG_STM32_PHYSR_100HD=0x0008 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index e8889b2c6e2a7..ac1dce20115d1 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -56,8 +56,8 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 6ad0662ee2446..8d9cdb06d9a01 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -55,8 +55,8 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index 10e1dee8be13a..ceb8ba55d3581 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -57,8 +57,8 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig index ce019ad2d4ff5..91975793f411d 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig @@ -31,7 +31,7 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USERLED=y From dd4c90e8330025325fabeff2a3dffd86e3dc618d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 20:50:38 +0200 Subject: [PATCH 25/52] !arch/stm32: move common sources to common/stm32 BREAKING CHANGE: Common STM32 source and private header files moved to arch/arm/src/common/stm32. Out-of-tree code that references family-local common source paths must update includes, build rules, and source paths to the new common STM32 location. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 504 ++++++ arch/arm/src/common/stm32/Make.defs | 549 +++++++ .../{ => common}/stm32/hardware/stm32_adc.h | 44 +- .../src/common/stm32/hardware/stm32_adc_v1.h | 640 ++++++++ .../common/stm32/hardware/stm32_adc_v1l1.h | 571 +++++++ .../src/common/stm32/hardware/stm32_adc_v2.h | 735 +++++++++ .../stm32/hardware/stm32_adc_v2_m0.h} | 8 +- .../common/stm32/hardware/stm32_adc_v2g4.h | 869 ++++++++++ .../arm/src/common/stm32/hardware/stm32_aes.h | 101 ++ .../arm/src/common/stm32/hardware/stm32_bkp.h | 177 ++ .../arm/src/common/stm32/hardware/stm32_can.h | 43 + .../stm32/hardware/stm32_can_bxcan.h} | 18 +- .../stm32/hardware/stm32_can_bxcan_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_comp.h | 45 + .../stm32/hardware/stm32_comp_m0.h} | 8 +- .../stm32/hardware/stm32_comp_v1v2.h} | 16 +- .../arm/src/common/stm32/hardware/stm32_crc.h | 82 + .../arm/src/common/stm32/hardware/stm32_crs.h | 103 ++ .../arm/src/common/stm32/hardware/stm32_dac.h | 45 + .../stm32/hardware/stm32_dac_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_dac_v1.h | 315 ++++ .../stm32/hardware/stm32_dac_v1v2.h} | 16 +- .../src/common/stm32/hardware/stm32_dbgmcu.h | 47 + .../stm32/hardware/stm32_dbgmcu_m0.h} | 8 +- .../stm32/hardware/stm32_dbgmcu_v1.h} | 28 +- .../stm32/hardware/stm32_dma.h} | 38 +- .../src/common/stm32/hardware/stm32_dma2d.h | 237 +++ .../stm32/hardware/stm32_dma_v1.h} | 25 +- .../stm32/hardware/stm32_dma_v1_7ch.h} | 8 +- .../stm32/hardware/stm32_dma_v1_8ch.h} | 32 +- .../src/common/stm32/hardware/stm32_dma_v2.h | 561 +++++++ .../src/common/stm32/hardware/stm32_dmamux.h | 40 + .../stm32/hardware/stm32_dmamux_16ch.h} | 8 +- .../stm32/hardware/stm32_dmamux_7ch.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_eth.h | 877 ++++++++++ .../stm32/hardware/stm32_exti.h} | 36 +- .../stm32/hardware/stm32_exti_v1v2.h} | 12 +- .../stm32/hardware/stm32_exti_v1v2_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_fdcan.h | 43 + .../stm32/hardware/stm32_fdcan_mcan.h} | 8 +- .../stm32/hardware/stm32_fdcan_mcan_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_flash.h | 43 + .../stm32/hardware/stm32_flash_m0.h} | 8 +- .../stm32/hardware/stm32_flash_v1v2.h} | 28 +- .../arm/src/common/stm32/hardware/stm32_fmc.h | 392 +++++ .../src/common/stm32/hardware/stm32_fsmc.h | 301 ++++ .../stm32/hardware/stm32_gpio.h} | 36 +- .../stm32/hardware/stm32_gpio_v2_m0.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_i2c.h | 51 + .../src/common/stm32/hardware/stm32_i2c_v1.h | 203 +++ .../src/common/stm32/hardware/stm32_i2c_v2.h | 241 +++ .../stm32/hardware/stm32_i2c_v2_m0.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_lcd.h | 209 +++ .../src/common/stm32/hardware/stm32_ltdc.h | 368 +++++ .../src/common/stm32/hardware/stm32_otghs.h | 1111 +++++++++++++ .../arm/src/common/stm32/hardware/stm32_pwr.h | 45 + .../stm32/hardware/stm32_pwr_v1.h} | 12 +- .../stm32/hardware/stm32_pwr_v1_m0_g0.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_rcc.h | 69 + .../stm32/hardware/stm32_rng.h} | 24 +- .../stm32/hardware/stm32_rng_m0.h} | 8 +- .../stm32/hardware/stm32_rng_v1.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_rtc.h | 83 + .../src/common/stm32/hardware/stm32_rtcc.h | 47 + .../stm32/hardware/stm32_rtcc_m0.h} | 8 +- .../stm32/hardware/stm32_rtcc_v1.h} | 8 +- .../src/common/stm32/hardware/stm32_sdio.h | 279 ++++ .../arm/src/common/stm32/hardware/stm32_spi.h | 54 + .../stm32/hardware/stm32_spi_v1v2_m0.h} | 16 +- .../stm32/hardware/stm32_spi_v2v3v4.h} | 14 +- .../src/common/stm32/hardware/stm32_syscfg.h | 43 + .../arm/src/common/stm32/hardware/stm32_tim.h | 55 + .../common/stm32/hardware/stm32_tim_v1v2.h | 1307 +++++++++++++++ .../src/common/stm32/hardware/stm32_tim_v3.h | 1440 +++++++++++++++++ .../stm32/hardware/stm32_tim_v3_m0.h} | 8 +- .../stm32/hardware/stm32_uart.h} | 30 +- .../src/common/stm32/hardware/stm32_uart_v1.h | 206 +++ .../src/common/stm32/hardware/stm32_uart_v2.h | 236 +++ .../src/common/stm32/hardware/stm32_uart_v3.h | 331 ++++ .../src/common/stm32/hardware/stm32_uart_v4.h | 390 +++++ .../src/common/stm32/hardware/stm32_usbdev.h | 43 + .../stm32/hardware/stm32_usbdev_m0.h} | 8 +- .../stm32/hardware/stm32_usbdev_v1.h} | 8 +- .../src/common/stm32/hardware/stm32_usbfs.h | 250 +++ .../arm/src/common/stm32/hardware/stm32_wdg.h | 43 + .../stm32/hardware/stm32_wdg_m0.h} | 8 +- .../stm32/hardware/stm32_wdg_v1v2.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_wdt.h | 129 ++ .../common/stm32/hardware/stm32fxxxxx_otgfs.h | 1115 +++++++++++++ .../common/stm32/hardware/stm32gxxxxx_dac.h | 525 ++++++ arch/arm/src/{ => common}/stm32/stm32_1wire.h | 10 +- .../stm32/stm32_1wire_m3m4_v1.c} | 3 +- .../stm32/stm32_adc.h} | 20 +- .../stm32/stm32_adc_m0_v1.c} | 2 +- .../stm32/stm32_adc_m0_v1.h} | 10 +- .../stm32/stm32_adc_m3m4_v1v2.c} | 10 +- .../stm32/stm32_adc_m3m4_v1v2.h} | 10 +- arch/arm/src/{ => common}/stm32/stm32_aes.h | 24 +- .../stm32/stm32_aes_m0_v1.c} | 4 +- .../stm32/stm32_aes_m3m4_v1.c} | 4 +- arch/arm/src/{ => common}/stm32/stm32_alarm.h | 8 +- .../stm32/stm32_allocateheap_m3m4_v1.c} | 4 +- .../stm32/stm32_bbsram.h} | 17 +- .../stm32/stm32_bbsram_m3m4_v1.c} | 4 +- .../stm32/stm32_bbsram_m3m4_v1.h} | 10 +- arch/arm/src/{ => common}/stm32/stm32_bkp.h | 8 +- arch/arm/src/{ => common}/stm32/stm32_can.h | 90 +- .../stm32/stm32_can_m3m4_v1.c} | 2 +- .../stm32/stm32_can_m3m4_v1_sock.c} | 2 +- .../src/{ => common}/stm32/stm32_capture.h | 85 +- .../stm32/stm32_capture_m3m4_v1.c} | 2 +- .../stm32/stm32_capture_m3m4_v1_lowerhalf.c} | 2 +- .../stm32/stm32_ccm.h} | 15 +- .../stm32/stm32_ccm_m3m4_v1.c} | 4 +- .../stm32/stm32_ccm_m3m4_v1.h} | 10 +- .../stm32/stm32_comp.h} | 158 +- .../stm32/stm32_comp_m3m4_v1.c} | 19 +- .../stm32/stm32_comp_m3m4_v2.c} | 19 +- .../stm32/stm32_cordic.h} | 16 +- .../stm32/stm32_cordic_m3m4_v1.c} | 4 +- .../stm32/stm32_cordic_m3m4_v1.h} | 8 +- .../stm32/stm32_crypto_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_dac.h | 39 + .../stm32/stm32_dac_m3m4_v1.c} | 19 +- .../stm32/stm32_dac_m3m4_v1.h} | 13 +- .../arm/src/{ => common}/stm32/stm32_dbgmcu.h | 14 +- arch/arm/src/common/stm32/stm32_dfumode.h | 38 + .../stm32/stm32_dfumode_m3m4_v1.c} | 8 +- .../stm32/stm32_dfumode_m3m4_v1.h} | 10 +- arch/arm/src/common/stm32/stm32_dma.h | 39 + arch/arm/src/common/stm32/stm32_dma2d.h | 38 + .../stm32/stm32_dma2d_m3m4_v1.c} | 6 +- .../stm32/stm32_dma2d_m3m4_v1.h} | 8 +- .../stm32/stm32_dma_channel_stream.h} | 8 +- .../stm32/stm32_dma_m0_v1_7ch.c} | 2 +- .../stm32/stm32_dma_m0_v1_7ch_dmamux.c} | 4 +- .../stm32/stm32_dma_m3m4_v1_8ch.c} | 6 +- .../stm32/stm32_dma_m3m4_v1_8ch_dmamux.c} | 4 +- .../stm32/stm32_dma_m3m4_v2_stream.c} | 2 +- .../stm32/stm32_dumpgpio_m3m4_v1.c} | 4 +- arch/arm/src/common/stm32/stm32_eth.h | 38 + .../stm32/stm32_eth_m3m4_v1.c} | 14 +- .../stm32/stm32_eth_m3m4_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_exti.h | 12 +- .../stm32/stm32_exti_alarm_m3m4_v1.c} | 2 +- .../stm32/stm32_exti_gpio_m0_v1.c} | 2 +- .../stm32/stm32_exti_gpio_m3m4_v1v2.c} | 2 +- arch/arm/src/common/stm32/stm32_exti_pwr.h | 38 + .../stm32/stm32_exti_pwr_m3m4_v1.c} | 6 +- .../stm32/stm32_exti_pwr_m3m4_v1.h} | 8 +- .../stm32/stm32_exti_wakeup_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_fdcan.h | 80 + .../stm32/stm32_fdcan_m0_v1.c} | 2 +- .../stm32/stm32_fdcan_m0_v1_sock.c} | 2 +- .../stm32/stm32_fdcan_m3m4_v1.c} | 2 +- .../stm32/stm32_fdcan_m3m4_v1_sock.c} | 2 +- .../stm32}/stm32_flash.h | 37 +- .../stm32/stm32_flash_m0_g0c0.c} | 2 +- .../stm32/stm32_flash_m3m4_f1f3.c} | 2 +- .../stm32/stm32_flash_m3m4_f2f4.c} | 6 +- .../stm32/stm32_flash_m3m4_g4.c} | 2 +- .../stm32/stm32_flash_m3m4_l1.c} | 2 +- arch/arm/src/common/stm32/stm32_fmc.h | 38 + .../stm32/stm32_fmc_m3m4_v1.c} | 2 +- .../stm32/stm32_fmc_m3m4_v1.h} | 12 +- arch/arm/src/common/stm32/stm32_foc.h | 38 + .../stm32/stm32_foc_m3m4_v1.c} | 51 +- .../stm32/stm32_foc_m3m4_v1.h} | 8 +- .../stm32/stm32_freerun.h} | 67 +- .../stm32/stm32_freerun_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_fsmc.h | 38 + .../stm32/stm32_fsmc_m3m4_v1.c} | 6 +- .../stm32/stm32_fsmc_m3m4_v1.h} | 12 +- arch/arm/src/common/stm32/stm32_gpio.h | 40 + .../stm32/stm32_gpio_m0_v1.c} | 4 +- .../stm32/stm32_gpio_m0_v1.h} | 10 +- .../stm32/stm32_gpio_m3m4_v1v2.c} | 2 +- .../stm32/stm32_gpio_m3m4_v1v2.h} | 8 +- .../src/{ => common}/stm32/stm32_hall3ph.c | 3 +- .../src/{ => common}/stm32/stm32_hall3ph.h | 12 +- arch/arm/src/common/stm32/stm32_hciuart.h | 52 + .../stm32/stm32_hciuart_m3m4_v1.c} | 13 +- arch/arm/src/common/stm32/stm32_hrtim.h | 38 + .../stm32/stm32_hrtim_m3m4_v1.c} | 6 +- .../stm32/stm32_hrtim_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_hsi48.h | 38 + .../stm32/stm32_hsi48_m0_v1.c} | 4 +- .../stm32/stm32_hsi48_m0_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_i2c.h | 27 +- .../stm32/stm32_i2c_m0_v1.c} | 2 +- .../stm32/stm32_i2c_m3m4_v1.c} | 10 +- .../stm32/stm32_i2c_m3m4_v1_alt.c} | 8 +- .../stm32/stm32_i2c_m3m4_v1_f40xxx.c} | 8 +- .../stm32/stm32_i2c_m3m4_v2.c} | 2 +- .../stm32/stm32_i2c_m3m4_v2_slave.c} | 2 +- arch/arm/src/{ => common}/stm32/stm32_i2s.h | 40 +- .../stm32/stm32_i2s_m3m4_v1.c} | 9 +- .../stm32/stm32_idle_m0_v1.c} | 2 +- .../stm32/stm32_idle_m3m4_v1.c} | 2 +- .../stm32/stm32_irq_m0_v1.c} | 2 +- .../stm32/stm32_irq_m3m4_v1.c} | 2 +- .../stm32/stm32_iwdg_m0_v1.c} | 160 +- .../stm32/stm32_iwdg_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_lowputc.h | 66 + .../stm32/stm32_lowputc_usart_m0_v3.c} | 2 +- .../stm32/stm32_lowputc_usart_m0_v4.c} | 2 +- .../stm32_lowputc_usart_m3m4_v1v2v3v4.c} | 2 +- .../stm32/stm32_lse_m0_v1.c} | 2 +- .../stm32/stm32_lse_m3m4_v1.c} | 2 +- .../stm32/stm32_lsi_m0_v1.c} | 8 +- .../stm32/stm32_lsi_m3m4_v1.c} | 10 +- arch/arm/src/common/stm32/stm32_ltdc.h | 38 + .../stm32/stm32_ltdc_m3m4_v1.c} | 6 +- .../stm32/stm32_ltdc_m3m4_v1.h} | 12 +- arch/arm/src/common/stm32/stm32_mpuinit.h | 65 + .../stm32/stm32_mpuinit_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_oneshot.h | 94 ++ .../stm32/stm32_oneshot_m3m4_v1.c} | 2 +- .../stm32/stm32_oneshot_m3m4_v1_lowerhalf.c} | 2 +- arch/arm/src/common/stm32/stm32_opamp.h | 38 + .../stm32/stm32_opamp_m3m4_v1.c} | 6 +- .../stm32/stm32_opamp_m3m4_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_otgfs.h | 8 +- .../stm32/stm32_otgfsdev_m3m4_v1.c} | 2 +- .../stm32/stm32_otgfshost_m3m4_v1.c} | 4 +- arch/arm/src/{ => common}/stm32/stm32_otghs.h | 8 +- .../stm32/stm32_otghsdev_m3m4_v1.c} | 2 +- .../stm32/stm32_otghshost_m3m4_v1.c} | 4 +- .../stm32_fdcan.h => common/stm32/stm32_pm.h} | 83 +- .../stm32/stm32_pminitialize_m3m4_v1.c} | 2 +- .../stm32/stm32_pmsleep_m3m4_v1.c} | 2 +- .../stm32/stm32_pmstandby_m3m4_v1.c} | 2 +- .../stm32/stm32_pmstop_m3m4_v1.c} | 2 +- .../stm32}/stm32_pulsecount.h | 8 +- .../stm32/stm32_pulsecount_m0_v1.c} | 2 +- .../stm32/stm32_pulsecount_m3m4_v1v2v3.c} | 2 +- .../stm32/stm32_pwm.h} | 23 +- .../stm32/stm32_pwm_m0_v1.c} | 2 +- .../stm32/stm32_pwm_m0_v1.h} | 8 +- .../stm32/stm32_pwm_m3m4_v1v2v3.c} | 2 +- .../stm32/stm32_pwm_m3m4_v1v2v3.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_pwr.h | 40 +- .../stm32/stm32_pwr_m0_g0.c} | 2 +- .../stm32/stm32_pwr_m0_v1.c} | 2 +- .../stm32/stm32_pwr_m3m4_v1.c} | 2 +- .../src/{ => common}/stm32/stm32_qencoder.h | 29 +- .../stm32/stm32_qencoder_m0_v1.c} | 2 +- .../stm32/stm32_qencoder_m3m4_v1v2v3.c} | 2 +- .../stm32_pwr.h => common/stm32/stm32_rcc.h} | 203 ++- .../stm32/stm32_rng_m0_v1.c} | 2 +- .../stm32/stm32_rng_m3m4_v1.c} | 14 +- arch/arm/src/{ => common}/stm32/stm32_rtc.h | 12 +- .../stm32/stm32_rtc_m3m4_v1_lowerhalf.c} | 2 +- .../stm32/stm32_rtcc_m3m4_f4.c} | 2 +- .../stm32/stm32_rtcc_m3m4_l1.c} | 2 +- .../stm32/stm32_rtcc_m3m4_v1.c} | 2 +- .../stm32/stm32_rtcounter_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_sdadc.h | 38 + .../stm32/stm32_sdadc_m3m4_v1.c} | 6 +- .../stm32/stm32_sdadc_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_sdio.h | 38 + .../stm32/stm32_sdio_m3m4_v1.c} | 14 +- .../stm32/stm32_sdio_m3m4_v1.h} | 13 +- .../stm32/stm32_serial_m0_v3.c} | 2 +- .../stm32/stm32_serial_m0_v4.c} | 2 +- .../stm32/stm32_serial_m3m4_v1v2v3v4.c} | 2 +- arch/arm/src/{ => common}/stm32/stm32_spi.h | 15 +- .../stm32/stm32_spi_m0_v1.c} | 2 +- .../stm32/stm32_spi_m3m4_v2v3v4.c} | 8 +- arch/arm/src/common/stm32/stm32_start.h | 64 + .../stm32/stm32_start_m0_v1.c} | 2 +- .../stm32/stm32_start_m3m4_v1.c} | 2 +- .../arm/src/{ => common}/stm32/stm32_syscfg.h | 8 +- .../stm32/stm32_tickless_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_tim.h | 42 + .../stm32/stm32_tim_m0_v1.c} | 2 +- .../stm32/stm32_tim_m0_v1.h} | 8 +- .../stm32/stm32_tim_m0_v1_lowerhalf.c} | 2 +- .../stm32/stm32_tim_m3m4_v1v2v3.c} | 2 +- .../stm32/stm32_tim_m3m4_v1v2v3.h} | 8 +- .../stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c} | 2 +- .../stm32/stm32_timerisr_armv6m.c} | 2 +- .../stm32/stm32_timerisr_armv7m.c} | 2 +- arch/arm/src/common/stm32/stm32_uart.h | 46 + .../stm32/stm32_uart_m0_v1.h} | 8 +- .../stm32/stm32_uart_m3m4_v1v2.h} | 26 +- .../{stm32f0l0g0 => common/stm32}/stm32_uid.h | 14 +- .../stm32/stm32_uid_m0_v1.c} | 2 +- .../stm32/stm32_uid_m3m4_v1v2.c} | 2 +- .../stm32}/stm32_usbdev.h | 18 +- .../stm32/stm32_usbdev_m0_v1.c} | 2 +- .../stm32/stm32_usbdev_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_usbfs.h | 38 + .../stm32/stm32_usbfs_m3m4_v1.c} | 6 +- .../stm32/stm32_usbfs_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_usbhost.h | 38 + .../stm32/stm32_usbhost_m3m4_v1.c} | 4 +- .../stm32/stm32_usbhost_m3m4_v1.h} | 8 +- .../stm32/stm32_userspace.h} | 58 +- .../stm32/stm32_userspace_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_waste.h | 45 + .../stm32/stm32_waste_m3m4_v1.c} | 2 +- .../{stm32f0l0g0 => common/stm32}/stm32_wdg.h | 8 +- .../stm32/stm32_wwdg_m0_v1.c} | 2 +- .../stm32/stm32_wwdg_m3m4_v1.c} | 177 +- arch/arm/src/stm32/CMakeLists.txt | 226 +-- arch/arm/src/stm32/Make.defs | 217 +-- arch/arm/src/stm32/hardware/stm32_adc_v1.h | 2 +- arch/arm/src/stm32/hardware/stm32_adc_v2.h | 2 +- arch/arm/src/stm32/hardware/stm32_dac_v1.h | 4 +- arch/arm/src/stm32/hardware/stm32_dma.h | 7 +- arch/arm/src/stm32/hardware/stm32_pinmap.h | 136 -- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 52 +- arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h | 4 +- arch/arm/src/stm32/stm32_comp.c | 60 - arch/arm/src/stm32/stm32_comp_v2.h | 99 -- arch/arm/src/stm32/stm32_flash.h | 114 -- arch/arm/src/stm32/stm32_freerun.h | 161 -- arch/arm/src/stm32/stm32_hciuart.h | 96 -- arch/arm/src/stm32/stm32_oneshot.h | 197 --- arch/arm/src/stm32/stm32_rtc.c | 61 - arch/arm/src/stm32/stm32_uid.h | 52 - arch/arm/src/stm32/stm32_usbdev.h | 92 -- arch/arm/src/stm32/stm32_wdg.h | 106 -- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 84 +- arch/arm/src/stm32f0l0g0/Make.defs | 79 +- .../stm32f0l0g0/hardware/stm32_memorymap.h | 49 - .../src/stm32f0l0g0/hardware/stm32_pinmap.h | 51 - .../arm/src/stm32f0l0g0/hardware/stm32_uart.h | 11 +- arch/arm/src/stm32f0l0g0/stm32_aes.h | 50 - arch/arm/src/stm32f0l0g0/stm32_dma.h | 327 ---- arch/arm/src/stm32f0l0g0/stm32_exti.h | 131 -- arch/arm/src/stm32f0l0g0/stm32_fdcan.h | 112 -- arch/arm/src/stm32f0l0g0/stm32_i2c.h | 91 -- arch/arm/src/stm32f0l0g0/stm32_qencoder.h | 116 -- arch/arm/src/stm32f0l0g0/stm32_spi.h | 171 -- 336 files changed, 19162 insertions(+), 4198 deletions(-) create mode 100644 arch/arm/src/common/stm32/CMakeLists.txt create mode 100644 arch/arm/src/common/stm32/Make.defs rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc.h (56%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_adc_v1.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_adc_v2.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_adc.h => common/stm32/hardware/stm32_adc_v2_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_aes.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_bkp.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_can.h rename arch/arm/src/{stm32/hardware/stm32_can.h => common/stm32/hardware/stm32_can_bxcan.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_can.h => common/stm32/hardware/stm32_can_bxcan_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_comp.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_comp.h => common/stm32/hardware/stm32_comp_m0.h} (97%) rename arch/arm/src/{stm32/hardware/stm32_comp.h => common/stm32/hardware/stm32_comp_v1v2.h} (79%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_crc.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_crs.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dac.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dac.h => common/stm32/hardware/stm32_dac_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dac_v1.h rename arch/arm/src/{stm32/hardware/stm32_dac.h => common/stm32/hardware/stm32_dac_v1v2.h} (79%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dbgmcu.h => common/stm32/hardware/stm32_dbgmcu_m0.h} (93%) rename arch/arm/src/{stm32/hardware/stm32_dbgmcu.h => common/stm32/hardware/stm32_dbgmcu_v1.h} (94%) rename arch/arm/src/{stm32/stm32_dma.c => common/stm32/hardware/stm32_dma.h} (62%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dma2d.h rename arch/arm/src/{stm32/hardware/stm32_i2c.h => common/stm32/hardware/stm32_dma_v1.h} (67%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dma_v1.h => common/stm32/hardware/stm32_dma_v1_7ch.h} (99%) rename arch/arm/src/{stm32/hardware/stm32_dma_v1.h => common/stm32/hardware/stm32_dma_v1_8ch.h} (97%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dma_v2.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dmamux.h rename arch/arm/src/{stm32/hardware/stm32_dmamux.h => common/stm32/hardware/stm32_dmamux_16ch.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dmamux.h => common/stm32/hardware/stm32_dmamux_7ch.h} (97%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_eth.h rename arch/arm/src/{stm32/stm32_flash.c => common/stm32/hardware/stm32_exti.h} (57%) rename arch/arm/src/{stm32/hardware/stm32_exti.h => common/stm32/hardware/stm32_exti_v1v2.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_exti.h => common/stm32/hardware/stm32_exti_v1v2_m0.h} (85%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_fdcan.h rename arch/arm/src/{stm32/hardware/stm32_fdcan.h => common/stm32/hardware/stm32_fdcan_mcan.h} (99%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_fdcan.h => common/stm32/hardware/stm32_fdcan_mcan_m0.h} (99%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_flash.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_flash.h => common/stm32/hardware/stm32_flash_m0.h} (86%) rename arch/arm/src/{stm32/hardware/stm32_flash.h => common/stm32/hardware/stm32_flash_v1v2.h} (97%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_fmc.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_fsmc.h rename arch/arm/src/{stm32/hardware/stm32_memorymap.h => common/stm32/hardware/stm32_gpio.h} (61%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_gpio.h => common/stm32/hardware/stm32_gpio_v2_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_i2c.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_i2c.h => common/stm32/hardware/stm32_i2c_v2_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_lcd.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_ltdc.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_otghs.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_pwr.h rename arch/arm/src/{stm32/hardware/stm32_pwr.h => common/stm32/hardware/stm32_pwr_v1.h} (95%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_pwr.h => common/stm32/hardware/stm32_pwr_v1_m0_g0.h} (85%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rcc.h rename arch/arm/src/{stm32/hardware/stm32_tim.h => common/stm32/hardware/stm32_rng.h} (66%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rng.h => common/stm32/hardware/stm32_rng_m0.h} (92%) rename arch/arm/src/{stm32/hardware/stm32_rng.h => common/stm32/hardware/stm32_rng_v1.h} (91%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rtc.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rtcc.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rtcc.h => common/stm32/hardware/stm32_rtcc_m0.h} (98%) rename arch/arm/src/{stm32/hardware/stm32_rtcc.h => common/stm32/hardware/stm32_rtcc_v1.h} (99%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_sdio.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_spi.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_spi.h => common/stm32/hardware/stm32_spi_v1v2_m0.h} (96%) rename arch/arm/src/{stm32/hardware/stm32_spi.h => common/stm32/hardware/stm32_spi_v2v3v4.h} (97%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_syscfg.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_tim.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_tim_v3.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_tim.h => common/stm32/hardware/stm32_tim_v3_m0.h} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_serial.c => common/stm32/hardware/stm32_uart.h} (63%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v1.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v2.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v3.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v4.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_usbdev.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_usbdev.h => common/stm32/hardware/stm32_usbdev_m0.h} (98%) rename arch/arm/src/{stm32/hardware/stm32_usbdev.h => common/stm32/hardware/stm32_usbdev_v1.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_usbfs.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_wdg.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_wdg.h => common/stm32/hardware/stm32_wdg_m0.h} (96%) rename arch/arm/src/{stm32/hardware/stm32_wdg.h => common/stm32/hardware/stm32_wdg_v1v2.h} (96%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_wdt.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h rename arch/arm/src/{ => common}/stm32/stm32_1wire.h (92%) rename arch/arm/src/{stm32/stm32_1wire.c => common/stm32/stm32_1wire_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lowputc.c => common/stm32/stm32_adc.h} (73%) rename arch/arm/src/{stm32f0l0g0/stm32_adc.c => common/stm32/stm32_adc_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_adc.h => common/stm32/stm32_adc_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_adc.c => common/stm32/stm32_adc_m3m4_v1v2.c} (99%) rename arch/arm/src/{stm32/stm32_adc.h => common/stm32/stm32_adc_m3m4_v1v2.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_aes.h (80%) rename arch/arm/src/{stm32/stm32_aes.c => common/stm32/stm32_aes_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_aes.c => common/stm32/stm32_aes_m3m4_v1.c} (98%) rename arch/arm/src/{ => common}/stm32/stm32_alarm.h (94%) rename arch/arm/src/{stm32/stm32_allocateheap.c => common/stm32/stm32_allocateheap_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_dma.c => common/stm32/stm32_bbsram.h} (78%) rename arch/arm/src/{stm32/stm32_bbsram.c => common/stm32/stm32_bbsram_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_bbsram.h => common/stm32/stm32_bbsram_m3m4_v1.h} (95%) rename arch/arm/src/{ => common}/stm32/stm32_bkp.h (90%) rename arch/arm/src/{ => common}/stm32/stm32_can.h (71%) rename arch/arm/src/{stm32/stm32_can.c => common/stm32/stm32_can_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_can_sock.c => common/stm32/stm32_can_m3m4_v1_sock.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_capture.h (81%) rename arch/arm/src/{stm32/stm32_capture.c => common/stm32/stm32_capture_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_capture_lowerhalf.c => common/stm32/stm32_capture_m3m4_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_flash.c => common/stm32/stm32_ccm.h} (76%) rename arch/arm/src/{stm32/stm32_ccm.c => common/stm32/stm32_ccm_m3m4_v1.c} (95%) rename arch/arm/src/{stm32/stm32_ccm.h => common/stm32/stm32_ccm_m3m4_v1.h} (93%) rename arch/arm/src/{stm32/stm32_comp_v1.h => common/stm32/stm32_comp.h} (51%) rename arch/arm/src/{stm32/stm32_comp_v1.c => common/stm32/stm32_comp_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_comp_v2.c => common/stm32/stm32_comp_m3m4_v2.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_serial.h => common/stm32/stm32_cordic.h} (75%) rename arch/arm/src/{stm32/stm32_cordic.c => common/stm32/stm32_cordic_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_cordic.h => common/stm32/stm32_cordic_m3m4_v1.h} (90%) rename arch/arm/src/{stm32/stm32_crypto.c => common/stm32/stm32_crypto_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_dac.h rename arch/arm/src/{stm32/stm32_dac.c => common/stm32/stm32_dac_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_dac.h => common/stm32/stm32_dac_m3m4_v1.h} (90%) rename arch/arm/src/{ => common}/stm32/stm32_dbgmcu.h (82%) create mode 100644 arch/arm/src/common/stm32/stm32_dfumode.h rename arch/arm/src/{stm32/stm32_dfumode.c => common/stm32/stm32_dfumode_m3m4_v1.c} (93%) rename arch/arm/src/{stm32/stm32_dfumode.h => common/stm32/stm32_dfumode_m3m4_v1.h} (87%) create mode 100644 arch/arm/src/common/stm32/stm32_dma.h create mode 100644 arch/arm/src/common/stm32/stm32_dma2d.h rename arch/arm/src/{stm32/stm32_dma2d.c => common/stm32/stm32_dma2d_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_dma2d.h => common/stm32/stm32_dma2d_m3m4_v1.h} (96%) rename arch/arm/src/{stm32/stm32_dma.h => common/stm32/stm32_dma_channel_stream.h} (97%) rename arch/arm/src/{stm32f0l0g0/stm32_dma_v1.c => common/stm32/stm32_dma_m0_v1_7ch.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_dma_v1mux.c => common/stm32/stm32_dma_m0_v1_7ch_dmamux.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v1.c => common/stm32/stm32_dma_m3m4_v1_8ch.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v1mux.c => common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v2.c => common/stm32/stm32_dma_m3m4_v2_stream.c} (99%) rename arch/arm/src/{stm32/stm32_dumpgpio.c => common/stm32/stm32_dumpgpio_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_eth.h rename arch/arm/src/{stm32/stm32_eth.c => common/stm32/stm32_eth_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_eth.h => common/stm32/stm32_eth_m3m4_v1.h} (94%) rename arch/arm/src/{ => common}/stm32/stm32_exti.h (94%) rename arch/arm/src/{stm32/stm32_exti_alarm.c => common/stm32/stm32_exti_alarm_m3m4_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_exti_gpio.c => common/stm32/stm32_exti_gpio_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_exti_gpio.c => common/stm32/stm32_exti_gpio_m3m4_v1v2.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_exti_pwr.h rename arch/arm/src/{stm32/stm32_exti_pwr.c => common/stm32/stm32_exti_pwr_m3m4_v1.c} (96%) rename arch/arm/src/{stm32/stm32_exti_pwr.h => common/stm32/stm32_exti_pwr_m3m4_v1.h} (90%) rename arch/arm/src/{stm32/stm32_exti_wakeup.c => common/stm32/stm32_exti_wakeup_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_fdcan.h rename arch/arm/src/{stm32f0l0g0/stm32_fdcan.c => common/stm32/stm32_fdcan_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_fdcan_sock.c => common/stm32/stm32_fdcan_m0_v1_sock.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan.c => common/stm32/stm32_fdcan_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan_sock.c => common/stm32/stm32_fdcan_m3m4_v1_sock.c} (99%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_flash.h (70%) rename arch/arm/src/{stm32f0l0g0/stm32g0c0_flash.c => common/stm32/stm32_flash_m0_g0c0.c} (99%) rename arch/arm/src/{stm32/stm32f10xxf30xx_flash.c => common/stm32/stm32_flash_m3m4_f1f3.c} (99%) rename arch/arm/src/{stm32/stm32f20xxf40xx_flash.c => common/stm32/stm32_flash_m3m4_f2f4.c} (97%) rename arch/arm/src/{stm32/stm32g4xxx_flash.c => common/stm32/stm32_flash_m3m4_g4.c} (99%) rename arch/arm/src/{stm32/stm32l15xx_flash.c => common/stm32/stm32_flash_m3m4_l1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_fmc.h rename arch/arm/src/{stm32/stm32_fmc.c => common/stm32/stm32_fmc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fmc.h => common/stm32/stm32_fmc_m3m4_v1.h} (93%) create mode 100644 arch/arm/src/common/stm32/stm32_foc.h rename arch/arm/src/{stm32/stm32_foc.c => common/stm32/stm32_foc_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_foc.h => common/stm32/stm32_foc_m3m4_v1.h} (96%) rename arch/arm/src/{stm32/stm32_waste.h => common/stm32/stm32_freerun.h} (54%) rename arch/arm/src/{stm32/stm32_freerun.c => common/stm32/stm32_freerun_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_fsmc.h rename arch/arm/src/{stm32/stm32_fsmc.c => common/stm32/stm32_fsmc_m3m4_v1.c} (93%) rename arch/arm/src/{stm32/stm32_fsmc.h => common/stm32/stm32_fsmc_m3m4_v1.h} (88%) create mode 100644 arch/arm/src/common/stm32/stm32_gpio.h rename arch/arm/src/{stm32f0l0g0/stm32_gpio.c => common/stm32/stm32_gpio_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_gpio.h => common/stm32/stm32_gpio_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_gpio.c => common/stm32/stm32_gpio_m3m4_v1v2.c} (99%) rename arch/arm/src/{stm32/stm32_gpio.h => common/stm32/stm32_gpio_m3m4_v1v2.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_hall3ph.c (98%) rename arch/arm/src/{ => common}/stm32/stm32_hall3ph.h (85%) create mode 100644 arch/arm/src/common/stm32/stm32_hciuart.h rename arch/arm/src/{stm32/stm32_hciuart.c => common/stm32/stm32_hciuart_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_hrtim.h rename arch/arm/src/{stm32/stm32_hrtim.c => common/stm32/stm32_hrtim_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_hrtim.h => common/stm32/stm32_hrtim_m3m4_v1.h} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_hsi48.h rename arch/arm/src/{stm32f0l0g0/stm32_hsi48.c => common/stm32/stm32_hsi48_m0_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_hsi48.h => common/stm32/stm32_hsi48_m0_v1.h} (94%) rename arch/arm/src/{ => common}/stm32/stm32_i2c.h (84%) rename arch/arm/src/{stm32f0l0g0/stm32_i2c.c => common/stm32/stm32_i2c_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_i2c.c => common/stm32/stm32_i2c_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_i2c_alt.c => common/stm32/stm32_i2c_m3m4_v1_alt.c} (99%) rename arch/arm/src/{stm32/stm32f40xxx_i2c.c => common/stm32/stm32_i2c_m3m4_v1_f40xxx.c} (99%) rename arch/arm/src/{stm32/stm32_i2c_v2.c => common/stm32/stm32_i2c_m3m4_v2.c} (99%) rename arch/arm/src/{stm32/stm32_i2cslave_v2.c => common/stm32/stm32_i2c_m3m4_v2_slave.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_i2s.h (78%) rename arch/arm/src/{stm32/stm32_i2s.c => common/stm32/stm32_i2s_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_idle.c => common/stm32/stm32_idle_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_idle.c => common/stm32/stm32_idle_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_irq.c => common/stm32/stm32_irq_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_irq.c => common/stm32/stm32_irq_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_iwdg.c => common/stm32/stm32_iwdg_m0_v1.c} (80%) rename arch/arm/src/{stm32/stm32_iwdg.c => common/stm32/stm32_iwdg_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_lowputc.h rename arch/arm/src/{stm32f0l0g0/stm32_lowputc_v1.c => common/stm32/stm32_lowputc_usart_m0_v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lowputc_v2.c => common/stm32/stm32_lowputc_usart_m0_v4.c} (99%) rename arch/arm/src/{stm32/stm32_lowputc.c => common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lse.c => common/stm32/stm32_lse_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_lse.c => common/stm32/stm32_lse_m3m4_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_lsi.c => common/stm32/stm32_lsi_m0_v1.c} (94%) rename arch/arm/src/{stm32/stm32_lsi.c => common/stm32/stm32_lsi_m3m4_v1.c} (92%) create mode 100644 arch/arm/src/common/stm32/stm32_ltdc.h rename arch/arm/src/{stm32/stm32_ltdc.c => common/stm32/stm32_ltdc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_ltdc.h => common/stm32/stm32_ltdc_m3m4_v1.h} (91%) create mode 100644 arch/arm/src/common/stm32/stm32_mpuinit.h rename arch/arm/src/{stm32/stm32_mpuinit.c => common/stm32/stm32_mpuinit_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_oneshot.h rename arch/arm/src/{stm32/stm32_oneshot.c => common/stm32/stm32_oneshot_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_oneshot_lowerhalf.c => common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_opamp.h rename arch/arm/src/{stm32/stm32_opamp.c => common/stm32/stm32_opamp_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_opamp.h => common/stm32/stm32_opamp_m3m4_v1.h} (96%) rename arch/arm/src/{ => common}/stm32/stm32_otgfs.h (95%) rename arch/arm/src/{stm32/stm32_otgfsdev.c => common/stm32/stm32_otgfsdev_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_otgfshost.c => common/stm32/stm32_otgfshost_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_otghs.h (95%) rename arch/arm/src/{stm32/stm32_otghsdev.c => common/stm32/stm32_otghsdev_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_otghshost.c => common/stm32/stm32_otghshost_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan.h => common/stm32/stm32_pm.h} (58%) rename arch/arm/src/{stm32/stm32_pminitialize.c => common/stm32/stm32_pminitialize_m3m4_v1.c} (97%) rename arch/arm/src/{stm32/stm32_pmsleep.c => common/stm32/stm32_pmsleep_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_pmstandby.c => common/stm32/stm32_pmstandby_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_pmstop.c => common/stm32/stm32_pmstop_m3m4_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_pulsecount.h (87%) rename arch/arm/src/{stm32f0l0g0/stm32_pulsecount.c => common/stm32/stm32_pulsecount_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_pulsecount.c => common/stm32/stm32_pulsecount_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32/stm32_pulsecount.h => common/stm32/stm32_pwm.h} (69%) rename arch/arm/src/{stm32f0l0g0/stm32_pwm.c => common/stm32/stm32_pwm_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwm.h => common/stm32/stm32_pwm_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_pwm.c => common/stm32/stm32_pwm_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32/stm32_pwm.h => common/stm32/stm32_pwm_m3m4_v1v2v3.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_pwr.h (94%) rename arch/arm/src/{stm32f0l0g0/stm32g0_pwr.c => common/stm32/stm32_pwr_m0_g0.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32f0l0_pwr.c => common/stm32/stm32_pwr_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_pwr.c => common/stm32/stm32_pwr_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_qencoder.h (84%) rename arch/arm/src/{stm32f0l0g0/stm32_qencoder.c => common/stm32/stm32_qencoder_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_qencoder.c => common/stm32/stm32_qencoder_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwr.h => common/stm32/stm32_rcc.h} (51%) rename arch/arm/src/{stm32/stm32_rng.c => common/stm32/stm32_rng_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_rng.c => common/stm32/stm32_rng_m3m4_v1.c} (96%) rename arch/arm/src/{ => common}/stm32/stm32_rtc.h (96%) rename arch/arm/src/{stm32/stm32_rtc_lowerhalf.c => common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32/stm32f40xxx_rtcc.c => common/stm32/stm32_rtcc_m3m4_f4.c} (99%) rename arch/arm/src/{stm32/stm32l15xxx_rtcc.c => common/stm32/stm32_rtcc_m3m4_l1.c} (99%) rename arch/arm/src/{stm32/stm32_rtcc.c => common/stm32/stm32_rtcc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_rtcounter.c => common/stm32/stm32_rtcounter_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_sdadc.h rename arch/arm/src/{stm32/stm32_sdadc.c => common/stm32/stm32_sdadc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_sdadc.h => common/stm32/stm32_sdadc_m3m4_v1.h} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_sdio.h rename arch/arm/src/{stm32/stm32_sdio.c => common/stm32/stm32_sdio_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_sdio.h => common/stm32/stm32_sdio_m3m4_v1.h} (93%) rename arch/arm/src/{stm32f0l0g0/stm32_serial_v1.c => common/stm32/stm32_serial_m0_v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_serial_v2.c => common/stm32/stm32_serial_m0_v4.c} (99%) rename arch/arm/src/{stm32/stm32_serial.c => common/stm32/stm32_serial_m3m4_v1v2v3v4.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_spi.h (94%) rename arch/arm/src/{stm32f0l0g0/stm32_spi.c => common/stm32/stm32_spi_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_spi.c => common/stm32/stm32_spi_m3m4_v2v3v4.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_start.h rename arch/arm/src/{stm32f0l0g0/stm32_start.c => common/stm32/stm32_start_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_start.c => common/stm32/stm32_start_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_syscfg.h (90%) rename arch/arm/src/{stm32/stm32_tickless.c => common/stm32/stm32_tickless_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_tim.h rename arch/arm/src/{stm32f0l0g0/stm32_tim.c => common/stm32/stm32_tim_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_tim.h => common/stm32/stm32_tim_m0_v1.h} (97%) rename arch/arm/src/{stm32f0l0g0/stm32_tim_lowerhalf.c => common/stm32/stm32_tim_m0_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32/stm32_tim.c => common/stm32/stm32_tim_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32/stm32_tim.h => common/stm32/stm32_tim_m3m4_v1v2v3.h} (96%) rename arch/arm/src/{stm32/stm32_tim_lowerhalf.c => common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_timerisr.c => common/stm32/stm32_timerisr_armv6m.c} (98%) rename arch/arm/src/{stm32/stm32_timerisr.c => common/stm32/stm32_timerisr_armv7m.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_uart.h rename arch/arm/src/{stm32f0l0g0/stm32_uart.h => common/stm32/stm32_uart_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_uart.h => common/stm32/stm32_uart_m3m4_v1v2.h} (96%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_uid.h (79%) rename arch/arm/src/{stm32f0l0g0/stm32_uid.c => common/stm32/stm32_uid_m0_v1.c} (97%) rename arch/arm/src/{stm32/stm32_uid.c => common/stm32/stm32_uid_m3m4_v1v2.c} (98%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_usbdev.h (85%) rename arch/arm/src/{stm32f0l0g0/stm32_usbdev.c => common/stm32/stm32_usbdev_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbdev.c => common/stm32/stm32_usbdev_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_usbfs.h rename arch/arm/src/{stm32/stm32_usbfs.c => common/stm32/stm32_usbfs_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbfs.h => common/stm32/stm32_usbfs_m3m4_v1.h} (92%) create mode 100644 arch/arm/src/common/stm32/stm32_usbhost.h rename arch/arm/src/{stm32/stm32_usbhost.c => common/stm32/stm32_usbhost_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbhost.h => common/stm32/stm32_usbhost_m3m4_v1.h} (98%) rename arch/arm/src/{stm32/stm32_comp.h => common/stm32/stm32_userspace.h} (66%) rename arch/arm/src/{stm32/stm32_userspace.c => common/stm32/stm32_userspace_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_waste.h rename arch/arm/src/{stm32/stm32_waste.c => common/stm32/stm32_waste_m3m4_v1.c} (97%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_wdg.h (94%) rename arch/arm/src/{stm32/stm32_wwdg.c => common/stm32/stm32_wwdg_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_wwdg.c => common/stm32/stm32_wwdg_m3m4_v1.c} (80%) delete mode 100644 arch/arm/src/stm32/hardware/stm32_pinmap.h delete mode 100644 arch/arm/src/stm32/stm32_comp.c delete mode 100644 arch/arm/src/stm32/stm32_comp_v2.h delete mode 100644 arch/arm/src/stm32/stm32_flash.h delete mode 100644 arch/arm/src/stm32/stm32_freerun.h delete mode 100644 arch/arm/src/stm32/stm32_hciuart.h delete mode 100644 arch/arm/src/stm32/stm32_oneshot.h delete mode 100644 arch/arm/src/stm32/stm32_rtc.c delete mode 100644 arch/arm/src/stm32/stm32_uid.h delete mode 100644 arch/arm/src/stm32/stm32_usbdev.h delete mode 100644 arch/arm/src/stm32/stm32_wdg.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_aes.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_dma.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_exti.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_fdcan.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_i2c.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_qencoder.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_spi.h diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt new file mode 100644 index 0000000000000..f7b24554c0f19 --- /dev/null +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -0,0 +1,504 @@ +# ############################################################################## +# arch/arm/src/common/stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_include_directories(arch BEFORE PUBLIC ${CMAKE_CURRENT_LIST_DIR}) + +if(CONFIG_BUILD_PROTECTED) + target_include_directories(arch_interface BEFORE + PUBLIC ${CMAKE_CURRENT_LIST_DIR}) +endif() + +set(SRCS) + +if(CONFIG_STM32_COMMON_LEGACY) + list( + APPEND + SRCS + stm32_allocateheap_m3m4_v1.c + stm32_start_m3m4_v1.c + stm32_lse_m3m4_v1.c + stm32_lsi_m3m4_v1.c + stm32_irq_m3m4_v1.c + stm32_waste_m3m4_v1.c + stm32_capture_m3m4_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) + list(APPEND SRCS stm32_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SPI_V1 + OR CONFIG_STM32_HAVE_IP_SPI_V2 + OR CONFIG_STM32_HAVE_IP_SPI_V3 + OR CONFIG_STM32_HAVE_IP_SPI_V4) + list(APPEND SRCS stm32_spi_m3m4_v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1) + list(APPEND SRCS stm32_i2s_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) + list(APPEND SRCS stm32_sdio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) + list(APPEND SRCS stm32_ccm_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) + list(APPEND SRCS stm32_uid_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) + list(APPEND SRCS stm32_dfumode_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m3m4_v1v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + + if(CONFIG_STM32_TICKLESS_TIMER) + list(APPEND SRCS stm32_tickless_m3m4_v1.c) + elseif(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + + if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace_m3m4_v1.c stm32_mpuinit_m3m4_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m3m4_v1.c) + endif() + + list(APPEND SRCS stm32_pmstop_m3m4_v1.c stm32_pmstandby_m3m4_v1.c + stm32_pmsleep_m3m4_v1.c) + + if(NOT CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pminitialize_m3m4_v1.c) + endif() + + if(CONFIG_STM32_USART) + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_serial_m3m4_v1v2v3v4.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) + endif() + + if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + if(CONFIG_STM32_I2C_ALT) + list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) + elseif(CONFIG_STM32_STM32F4XXX) + list(APPEND SRCS stm32_i2c_m3m4_v1_f40xxx.c) + else() + list(APPEND SRCS stm32_i2c_m3m4_v1.c) + endif() + elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + list(APPEND SRCS stm32_i2c_m3m4_v2.c) + if(CONFIG_STM32_I2C_SLAVE) + list(APPEND SRCS stm32_i2c_m3m4_v2_slave.c) + endif() + endif() + + if(CONFIG_USBDEV) + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) + list(APPEND SRCS stm32_usbdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_USBFS AND CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) + list(APPEND SRCS stm32_usbfs_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfsdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghsdev_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_USBHOST) + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG AND (CONFIG_USBHOST_TRACE + OR CONFIG_DEBUG_USB)) + list(APPEND SRCS stm32_usbhost_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_ETHMAC AND CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + list(APPEND SRCS stm32_eth_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWR AND CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + list(APPEND SRCS stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RTC) + if(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1) + list(APPEND SRCS stm32_rtcounter_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + list(APPEND SRCS stm32_rtcc_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) + list(APPEND SRCS stm32_rtcc_m3m4_f4.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + list(APPEND SRCS stm32_rtcc_m3m4_v1.c) + endif() + if(CONFIG_RTC_ALARM) + list(APPEND SRCS stm32_exti_alarm_m3m4_v1.c) + endif() + if(CONFIG_RTC_PERIODIC) + list(APPEND SRCS stm32_exti_wakeup_m3m4_v1.c) + endif() + if(CONFIG_RTC_DRIVER AND CONFIG_STM32_HAVE_IP_RTC_M3M4_V1) + list(APPEND SRCS stm32_rtc_m3m4_v1_lowerhalf.c) + endif() + endif() + + if(CONFIG_STM32_ADC + AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + list(APPEND SRCS stm32_adc_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_SDADC AND CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) + list(APPEND SRCS stm32_sdadc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DAC + AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + list(APPEND SRCS stm32_dac_m3m4_v1.c) + endif() + + if(CONFIG_STM32_COMP) + if(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + list(APPEND SRCS stm32_comp_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + list(APPEND SRCS stm32_comp_m3m4_v2.c) + endif() + endif() + + if(CONFIG_STM32_OPAMP AND CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) + list(APPEND SRCS stm32_opamp_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HRTIM AND CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) + list(APPEND SRCS stm32_hrtim_m3m4_v1.c) + endif() + + if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HCIUART) + list(APPEND SRCS stm32_hciuart_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) + list(APPEND SRCS stm32_rng_m3m4_v1.c) + endif() + + if(CONFIG_STM32_LTDC AND CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + list(APPEND SRCS stm32_ltdc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DMA2D AND CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1) + list(APPEND SRCS stm32_dma2d_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAP) + list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_m3m4_v1.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_can_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m3m4_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_iwdg_m3m4_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_wwdg_m3m4_v1.c) + endif() + + if(CONFIG_DEBUG_FEATURES + AND (CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) + list(APPEND SRCS stm32_dumpgpio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M3M4_V1) + list(APPEND SRCS stm32_aes_m3m4_v1.c) + endif() + + if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1) + list(APPEND SRCS stm32_crypto_m3m4_v1.c) + endif() + + if(CONFIG_STM32_BBSRAM AND CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) + list(APPEND SRCS stm32_bbsram_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FMC AND CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + list(APPEND SRCS stm32_fmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FSMC AND CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + list(APPEND SRCS stm32_fsmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_CORDIC AND CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) + list(APPEND SRCS stm32_cordic_m3m4_v1.c) + endif() +endif() + +if(CONFIG_ARCH_CORTEXM0) + list( + APPEND + SRCS + stm32_irq_m0_v1.c + stm32_start_m0_v1.c + stm32_lsi_m0_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) + list(APPEND SRCS stm32_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M0_V1) + list(APPEND SRCS stm32_uid_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V3) + list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) + elseif(CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) + endif() + + if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) + list(APPEND SRCS stm32_lse_m0_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m0_v1.c) + endif() + + if(NOT CONFIG_SCHED_TICKLESS) + if(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + endif() + + if(CONFIG_STM32_PWR) + if(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + list(APPEND SRCS stm32_pwr_m0_v1.c) + elseif(CONFIG_STM32_HAVE_IP_PWR_G0) + list(APPEND SRCS stm32_pwr_m0_g0.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_STM32_PROGMEM) + if(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0) + list(APPEND SRCS stm32_flash_m0_g0c0.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + endif() + + if(CONFIG_STM32_HAVE_HSI48) + list(APPEND SRCS stm32_hsi48_m0_v1.c) + endif() + + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + list(APPEND SRCS stm32_usbdev_m0_v1.c) + endif() + + if(CONFIG_STM32_I2C) + list(APPEND SRCS stm32_i2c_m0_v1.c) + endif() + + if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi_m0_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m0_v1.c) + endif() + + if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m0_v1.c) + endif() + + if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1) + list(APPEND SRCS stm32_adc_m0_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M0_V1) + list(APPEND SRCS stm32_aes_m0_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1) + list(APPEND SRCS stm32_rng_m0_v1.c) + endif() + + if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_iwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_wwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m0_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m0_v1_sock.c) + endif() + endif() + + if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder_m0_v1.c) + endif() +endif() + +if(CONFIG_SENSORS_HALL3PHASE) + list(APPEND SRCS stm32_hall3ph.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs new file mode 100644 index 0000000000000..1e51e18175506 --- /dev/null +++ b/arch/arm/src/common/stm32/Make.defs @@ -0,0 +1,549 @@ +############################################################################ +# arch/arm/src/common/stm32/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +STM32_COMMON_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +VPATH += common$(DELIM)stm32 +INCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) + +# IP-core driver selection notes (see arch/arm/src/common/stm32/Kconfig.have): +# - Some peripherals use a "register-set" symbol that picks the hardware header +# plus a "driver-variant" symbol that picks the .c file below (e.g. FLASH: +# STM32_HAVE_IP_FLASH_M3M4_V1 header + STM32_HAVE_IP_FLASH_M3M4_F2F4 driver). +# - This file is split into a legacy Cortex-M3/M4 block (the F1/F2/F3/F4/G4/L1 +# families, STM32_COMMON_LEGACY) and a Cortex-M0 block (F0/L0/G0/C0, +# ARCH_CORTEXM0). STM32_COMMON_LEGACY -- not a plain Cortex symbol -- gates +# the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include +# this file too but provide their own implementation. + +ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) + +CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c +CHIP_CSRCS += stm32_start_m3m4_v1.c +CHIP_CSRCS += stm32_lse_m3m4_v1.c +CHIP_CSRCS += stm32_lsi_m3m4_v1.c +CHIP_CSRCS += stm32_irq_m3m4_v1.c +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_lowputc_usart_m3m4_v1v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1),y) +CHIP_CSRCS += stm32_gpio_m3m4_v1v2.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m3m4_v1v2.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_SPI_V1) \ + $(CONFIG_STM32_HAVE_IP_SPI_V2) \ + $(CONFIG_STM32_HAVE_IP_SPI_V3) \ + $(CONFIG_STM32_HAVE_IP_SPI_V4)),) +CHIP_CSRCS += stm32_spi_m3m4_v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1),y) +CHIP_CSRCS += stm32_i2s_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) +CHIP_CSRCS += stm32_sdio_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c +endif +CHIP_CSRCS += stm32_waste_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) +CHIP_CSRCS += stm32_ccm_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M3M4_V1),y) +CHIP_CSRCS += stm32_uid_m3m4_v1v2.c +endif +CHIP_CSRCS += stm32_capture_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y) +CHIP_CSRCS += stm32_dfumode_m3m4_v1.c +endif + +ifdef CONFIG_STM32_TICKLESS_TIMER +CHIP_CSRCS += stm32_tickless_m3m4_v1.c +else +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace_m3m4_v1.c +CHIP_CSRCS += stm32_mpuinit_m3m4_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m3m4_v1.c +endif + +CHIP_CSRCS += stm32_pmstop_m3m4_v1.c +CHIP_CSRCS += stm32_pmstandby_m3m4_v1.c +CHIP_CSRCS += stm32_pmsleep_m3m4_v1.c + +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32_pminitialize_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_USART),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_serial_m3m4_v1v2v3v4.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot_m3m4_v1.c +CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) +ifeq ($(CONFIG_STM32_I2C_ALT),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_alt.c +else ifeq ($(CONFIG_STM32_STM32F4XXX),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_f40xxx.c +else +CHIP_CSRCS += stm32_i2c_m3m4_v1.c +endif +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2.c +ifeq ($(CONFIG_STM32_I2C_SLAVE),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2_slave.c +endif +endif + +ifeq ($(CONFIG_USBDEV),y) +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1),y) +CHIP_CSRCS += stm32_usbdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_USBFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1),y) +CHIP_CSRCS += stm32_usbfs_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfsdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghsdev_m3m4_v1.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG),y) +ifeq ($(CONFIG_USBHOST_TRACE),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +else +ifeq ($(CONFIG_DEBUG_USB),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +endif +endif +endif +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1),y) +CHIP_CSRCS += stm32_eth_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR)$(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1),yy) +CHIP_CSRCS += stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RTC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcounter_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4),y) +CHIP_CSRCS += stm32_rtcc_m3m4_f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_ALARM),y) +CHIP_CSRCS += stm32_exti_alarm_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_PERIODIC),y) +CHIP_CSRCS += stm32_exti_wakeup_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_DRIVER)$(CONFIG_STM32_HAVE_IP_RTC_M3M4_V1),yy) +CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_ADC),y) +CHIP_CSRCS += stm32_adc_m3m4_v1v2.c +endif +endif + +ifeq ($(CONFIG_STM32_SDADC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1),y) +CHIP_CSRCS += stm32_sdadc_m3m4_v1.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_DAC),y) +CHIP_CSRCS += stm32_dac_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_COMP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1),y) +CHIP_CSRCS += stm32_comp_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2),y) +CHIP_CSRCS += stm32_comp_m3m4_v2.c +endif +endif + +ifeq ($(CONFIG_STM32_OPAMP)$(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1),yy) +CHIP_CSRCS += stm32_opamp_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1),y) +CHIP_CSRCS += stm32_hrtim_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +CHIP_CSRCS += stm32_hciuart_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1),yy) +CHIP_CSRCS += stm32_rng_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1),y) +CHIP_CSRCS += stm32_ltdc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA2D),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1),y) +CHIP_CSRCS += stm32_dma2d_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAP),y) +CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_can_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CHIP_CSRCS += stm32_can_m3m4_v1_sock.c +endif +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_iwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_wwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_DEBUG_FEATURES),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)),) +CHIP_CSRCS += stm32_dumpgpio_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M3M4_V1),yy) +CHIP_CSRCS += stm32_aes_m3m4_v1.c +endif + +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1),yy) +CHIP_CSRCS += stm32_crypto_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1),y) +CHIP_CSRCS += stm32_bbsram_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fsmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CHIP_CSRCS += stm32_foc_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_CORDIC)$(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1),yy) +CHIP_CSRCS += stm32_cordic_m3m4_v1.c +endif + +endif + +ifeq ($(CONFIG_ARCH_CORTEXM0),y) + +CHIP_CSRCS += stm32_irq_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c +endif +CHIP_CSRCS += stm32_start_m0_v1.c +CHIP_CSRCS += stm32_lsi_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) +CHIP_CSRCS += stm32_gpio_m0_v1.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m0_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_serial_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_serial_m0_v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M0_V1),y) +CHIP_CSRCS += stm32_uid_m0_v1.c +endif + +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),) +CHIP_CSRCS += stm32_lse_m0_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m0_v1.c +endif + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR),y) +ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y) +CHIP_CSRCS += stm32_pwr_m0_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_PWR_G0),y) +CHIP_CSRCS += stm32_pwr_m0_g0.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_STM32_PROGMEM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0),y) +CHIP_CSRCS += stm32_flash_m0_g0c0.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +endif + +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) +CHIP_CSRCS += stm32_hsi48_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1),y) +CHIP_CSRCS += stm32_usbdev_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_I2C),y) +CHIP_CSRCS += stm32_i2c_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CHIP_CSRCS += stm32_spi_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m0_v1.c +endif + +ifeq ($(CONFIG_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy) +CHIP_CSRCS += stm32_adc_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy) +CHIP_CSRCS += stm32_aes_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) +CHIP_CSRCS += stm32_rng_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) +CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_iwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_wwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m0_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m0_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CHIP_CSRCS += stm32_qencoder_m0_v1.c +endif + +endif + +ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) +CHIP_CSRCS += stm32_hall3ph.c +endif diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc.h similarity index 56% rename from arch/arm/src/stm32/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc.h index 4bfee933c6e95..9ad1291ad40eb 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,51 +20,39 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H /**************************************************************************** * Included Files ****************************************************************************/ -#include +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "hardware/stm32_adc_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) -#include "chip.h" - -/* There are 2 main types of ADC IP cores among STM32 chips: - * 1. STM32 ADC IPv1: - * a) basic version for F1 and F37x - * b) extended version for F2, F4, F7, L1: - * 2. STM32 ADC IPv2: - * a) basic version for F0 and L0 - * b) extended version for F3 (without F37x), G4, H7, L4, L4+ - * - * We also distinguish these variants: - * 1. The modified STM32 ADC IPv1 core for the L1 family, which differs - * too much to keep it in the same file as ADC IPv1. - * 2. The modified STM32 ADC IPv2 core for the G4 family, which differs - * too much to keep it in the same file as ADC IPv2. - */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Only one STM32 ADC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # if defined(CONFIG_STM32_STM32L15XX) -# include "stm32_adc_v1l1.h" /* Special case for L1 */ +# include "stm32_adc_v1l1.h" # else # include "stm32_adc_v1.h" # endif -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32_adc_v2g4.h" /* Special case for G4 */ +# include "stm32_adc_v2g4.h" # else # include "stm32_adc_v2.h" # endif #else # error "STM32 ADC IP version not specified" #endif +#else +# error "Unsupported STM32 ADC" +#endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h new file mode 100644 index 0000000000000..ef09aabbac86d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h @@ -0,0 +1,640 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This is implementation for STM32 ADC IPv1 - F1, F2, F37x, F4, F7. + * NOTE: L1 use modified IPv1 (look at chip/stm32_adc_v1l1.h). + */ + +#define HAVE_IP_ADC_V1 +#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ +#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ +#undef HAVE_ADC_POWERDOWN /* No ADC power down */ + +/* F1 and F37x have basic version of ADC hardware + * - no common ADC registers + * - ADCs are not coupled in single ADC block (no common ADC base address) + * - no configurable resolution + * - no overrun + * - ... + */ + +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) +# define HAVE_BASIC_ADC +#else +# undef HAVE_BASIC_ADC +#endif + +/* VBAT channel support only if no basic ADC */ + +#ifndef HAVE_BASIC_ADC +# define HAVE_ADC_VBAT +#else +# undef HAVE_ADC_VBAT +#endif + +/* Base addresses ***********************************************************/ + +/* For the basic ADC IPv1, + * the ADCx_BASE definitions are defined in chip/stm32xxx_memorymap.h files + */ + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC1_OFFSET 0x0000 +# define STM32_ADC2_OFFSET 0x0100 +# define STM32_ADC3_OFFSET 0x0200 +# define STM32_ADC_CMN_OFFSET 0x0300 + +# define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC_BASE) /* ADC1 ADC */ +# define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC_BASE) /* ADC2 ADC */ +# define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC_BASE) /* ADC3 ADC */ + +# define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET + STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ +#endif + +/* Register Offsets *********************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ +# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ +#endif + +/* Register Addresses *******************************************************/ + +#if STM32_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) +#endif + +#ifndef HAVE_BASIC_ADC +# define STM32_ADC_CSR (STM32_ADCCMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC_CCR (STM32_ADCCMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC_CDR (STM32_ADCCMN_BASE + STM32_ADC_CDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#ifndef HAVE_BASIC_ADC +# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ +#endif + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) + +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) + +#ifdef HAVE_BASIC_ADC +# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */ +# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT) +# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */ +# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */ +# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */ +# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */ +# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */ +# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */ +# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */ +# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */ +#endif + +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles */ +# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles */ +# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ + +# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ +# define ADC_CR1_RESERVED (0xfb3f0000) +#endif + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#ifdef HAVE_BASIC_ADC +# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ +# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */ +#endif +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#ifndef HAVE_BASIC_ADC +# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#endif + +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + +#ifndef HAVE_BASIC_ADC + /* Bits 12-15: Reserved */ +# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ +# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ +# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ +# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ +# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ +# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ + +# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ +# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ +# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ +# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ +# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ + +# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ +# define ADC_CR2_RESERVED (0x8080f0fc) +#else /* HAVE_BASIC_ADC */ +# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */ +# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_CR2_JEXTSEL_T19CC1 (0 << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T19CC2 (1 << ADC_CR2_JEXTSEL_SHIFT) +# else +# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */ +# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */ +# endif +# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */ +# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ +# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ + +# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ +# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */ +# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT) +# if defined(CONFIG_STM32_STM32F37XX) +# define ADC_CR2_EXTSEL_T19TRGO (0 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T19CC3 (1 << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T19CC4 (2 << ADC_CR2_EXTSEL_SHIFT) +# else +# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */ +# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */ +# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */ +# endif +# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ +# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ + +# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ +# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */ +# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */ +# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */ +#endif + +/* ADC sample time register 1 */ + +#ifndef HAVE_BASIC_ADC +# define ADC_SMPR_3 0 /* 000: 3 cycles */ +# define ADC_SMPR_15 1 /* 001: 15 cycles */ +# define ADC_SMPR_28 2 /* 010: 28 cycles */ +# define ADC_SMPR_56 3 /* 011: 56 cycles */ +# define ADC_SMPR_84 4 /* 100: 84 cycles */ +# define ADC_SMPR_112 5 /* 101: 112 cycles */ +# define ADC_SMPR_144 6 /* 110: 144 cycles */ +# define ADC_SMPR_480 7 /* 111: 480 cycles */ +#else +# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ +# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ +# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ +# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ +# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ +# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ +# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ +# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ +#endif + +#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) +#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) +#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) +#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) +#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) +#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) +#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) +#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) +#ifndef HAVE_BASIC_ADC +# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) +#endif + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) +#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) +#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) +#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) +#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) +#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) +#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) +#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) +#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) +#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) +#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) +#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) +#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (13) +#define ADC_SQR1_LAST (16) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) +#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) +#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (7) +#define ADC_SQR2_LAST (12) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) +#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) +#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) +#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) +#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) +#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (1) +#define ADC_SQR3_LAST (6) +#define ADC_SQR3_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JSQ_SHIFT (5) /* Shift between JSQx bits */ +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) +#ifdef HAVE_BASIC_ADC +# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ +# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) +#endif + +/* Common status register */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + /* Bits 6-7: Reserved, must be kept at reset value. */ + +# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ +# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ +# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ +# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ +# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ +# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ + /* Bits 14-15: Reserved, must be kept at reset value. */ +# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ +# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ +# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ +# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ +# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ +# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ + /* Bits 22-31: Reserved, must be kept at reset value. */ +#endif + +/* Common control register */ + +#ifndef HAVE_BASIC_ADC +# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ +# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) +# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ + /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ +# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ + /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ +# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ +# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ +# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ +# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ +# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ +# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ + +/* Bits 5-7: Reserved, + * must be kept at reset value. + */ + +# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ + +/* Bit 12 Reserved, + * must be kept at reset value. + */ + +# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ + +# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ +# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) +# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ +# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ +# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ +# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ + +# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ +# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ +# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ + +/* Bits 18-21: Reserved, + * must be kept at reset value. + */ +# define ADC_CCR_VBATEN (1 << 22) /* Bit 22: VBAT enable */ +# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 24-31 Reserved, must be kept at reset value. */ +#endif + +/* Data register for dual and triple modes + * (32-bit data with no named fields) + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h new file mode 100644 index 0000000000000..919c9f5791932 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h @@ -0,0 +1,571 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This is implementation for STM32 ADC IPv1 modified for L1 */ + +#define HAVE_IP_ADC_V1 +#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ +#undef HAVE_BASIC_ADC /* No basic ADC */ +#undef HAVE_ADC_VBAT /* No VBAT channel */ + +/* Some families use HSI as clock-source for the ADC (L0, L1). + * NOTE: F0 use dedicated HSI14 clock which does not belong here. + */ + +#ifdef CONFIG_STM32_STM32L15XX +# define HAVE_ADC_CLOCK_HSI +#endif + +/* Power down functions for ADC (L1) */ + +#ifdef CONFIG_STM32_STM32L15XX +# define HAVE_ADC_POWERDOWN +#endif + +/* Base addresses ***********************************************************/ + +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0200 +#define STM32_ADC_CMN_OFFSET 0x0300 + +#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC_BASE) /* ADC1 ADC */ +#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC_BASE) /* ADC2 ADC */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC_BASE) /* ADC3 ADC */ + +#define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET + STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ + +/* Register Offsets *********************************************************/ + +#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ +#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ +#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ +#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ +#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ +#define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */ +#define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */ +#define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */ +#define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */ +#define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */ +#define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */ +#define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */ +#define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */ +#define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */ +#define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */ +#define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */ +#define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */ + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NADC > 0 +# define STM32_ADC1_SR (STM32_ADC1_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC1_CR1 (STM32_ADC1_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC1_CR2 (STM32_ADC1_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE + STM32_ADC_SMPR3_OFFSET) +# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC1_HTR (STM32_ADC1_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC1_LTR (STM32_ADC1_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_SQR5 (STM32_ADC1_BASE + STM32_ADC_SQR5_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE + STM32_ADC_SMPR0_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_SR (STM32_ADC2_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC2_CR1 (STM32_ADC2_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC2_CR2 (STM32_ADC2_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC2_HTR (STM32_ADC2_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC2_LTR (STM32_ADC2_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_SR (STM32_ADC3_BASE + STM32_ADC_SR_OFFSET) +# define STM32_ADC3_CR1 (STM32_ADC3_BASE + STM32_ADC_CR1_OFFSET) +# define STM32_ADC3_CR2 (STM32_ADC3_BASE + STM32_ADC_CR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE + STM32_ADC_JOFR1_OFFSET) +# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE + STM32_ADC_JOFR2_OFFSET) +# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE + STM32_ADC_JOFR3_OFFSET) +# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE + STM32_ADC_JOFR4_OFFSET) +# define STM32_ADC3_HTR (STM32_ADC3_BASE + STM32_ADC_HTR_OFFSET) +# define STM32_ADC3_LTR (STM32_ADC3_BASE + STM32_ADC_LTR_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) +#endif + +#define STM32_ADC_CSR (STM32_ADCCMN_BASE + STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE + STM32_ADC_CCR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* ADC status register */ + +#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ +#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ +#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ +#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ +#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ +#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ +#define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */ +#define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */ +#define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */ + +/* ADC control register 1 */ + +#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ +#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) + +#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ +#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ +#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ +#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ +#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ +#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) + +#define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */ +#define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must + * be written only when ADON=0 */ +#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ +#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) +# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 12 ADCCLK cycles */ +# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ +# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 7 ADCCLK cycles */ + +#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ +#define ADC_CR1_RESERVED (0xfb3f0000) + +/* ADC control register 2 */ + +#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ +#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ +#define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no + * conversion is on going. This bit is available in high and medium + + * density devices only. + */ + +#define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */ +#define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT) +#define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */ +#define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */ +#define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */ +#define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */ + +#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ +#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ +#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ +#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ + /* Bits 12-15: Reserved */ +#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ +#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) +# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ +# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ +# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ +# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ +# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ +# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ +# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ +# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ +# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ +# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ +# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ + +#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ +#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) +# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ + /* Bit 23: Reserved, must be kept at reset value. */ +#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ +#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) +# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ +# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ +# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ +# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ +# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ +# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ +# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ +# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ +# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ +# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ +# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ +# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ + +#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ +#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) +# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ + +#define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ +#define ADC_CR2_RESERVED (0x8080f0fc) + +/* ADC sample time register 1 */ + +#define ADC_SMPR_4 0 /* 000: 3 cycles */ +#define ADC_SMPR_9 1 /* 001: 9 cycles */ +#define ADC_SMPR_16 2 /* 010: 16 cycles */ +#define ADC_SMPR_24 3 /* 011: 24 cycles */ +#define ADC_SMPR_48 4 /* 100: 48 cycles */ +#define ADC_SMPR_96 5 /* 101: 96 cycles */ +#define ADC_SMPR_192 6 /* 110: 192 cycles */ +#define ADC_SMPR_384 7 /* 111: 384 cycles */ + +#define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */ +#define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT) +#define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */ +#define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT) +#define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */ +#define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT) +#define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */ +#define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT) +#define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */ +#define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT) +#define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */ +#define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT) +#define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */ +#define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT) +#define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */ +#define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT) +#define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */ +#define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT) +#define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */ +#define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT) + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) +#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) +#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) +#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) +#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) +#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) +#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) +#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) +#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) +#define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT) + +/* ADC sample time register 3 */ + +#define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ +#define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT) +#define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT) +#define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT) +#define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT) +#define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT) +#define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT) +#define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT) +#define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT) +#define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT) +#define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT) + +/* ADC sample time register 0 */ + +#define ADC_SMPR0_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */ +#define ADC_SMPR0_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT) +#define ADC_SMPR0_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */ +#define ADC_SMPR0_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT) + +/* ADC injected channel data offset register 1-4 */ + +#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ +#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) + +/* ADC watchdog high threshold register */ + +#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ +#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) + +/* ADC watchdog low threshold register */ + +#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ +#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ +#define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) +#define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */ +#define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT) +#define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */ +#define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT) +#define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */ +#define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT) +#define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_RESERVED (0xff000000) +#define ADC_SQR1_FIRST (25) +#define ADC_SQR1_LAST (28) +#define ADC_SQR1_SQ_OFFSET (0) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ +#define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) +#define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */ +#define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT) +#define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */ +#define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT) +#define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */ +#define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT) +#define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */ +#define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT ) +#define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ +#define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) +#define ADC_SQR2_RESERVED (0xc0000000) +#define ADC_SQR2_FIRST (19) +#define ADC_SQR2_LAST (24) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) +#define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ +#define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT) +#define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ +#define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT) +#define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */ +#define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT ) +#define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ +#define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) +#define ADC_SQR3_RESERVED (0xc0000000) +#define ADC_SQR3_FIRST (13) +#define ADC_SQR3_LAST (18) +#define ADC_SQR3_SQ_OFFSET (0) + +/* ADC regular sequence register 4 */ + +#define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ +#define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT) +#define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ +#define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT) +#define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ +#define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT) +#define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ +#define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT) +#define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ +#define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT ) +#define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ +#define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) +#define ADC_SQR4_RESERVED (0xc0000000) +#define ADC_SQR4_FIRST (7) +#define ADC_SQR4_LAST (12) +#define ADC_SQR4_SQ_OFFSET (0) + +/* ADC regular sequence register 5 */ + +#define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ +#define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT) +#define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ +#define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT) +#define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ +#define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT) +#define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ +#define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT) +#define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ +#define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT ) +#define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ +#define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) +#define ADC_SQR5_RESERVED (0xc0000000) +#define ADC_SQR5_FIRST (1) +#define ADC_SQR5_LAST (6) +#define ADC_SQR5_SQ_OFFSET (0) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (5) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +#define ADC_JSQR_JSQ_SHIFT (5) /* Shift between JSQx bits */ +#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ + +/* ADC injected data register 1-4 */ + +#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* Common status register */ + +#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ +#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ +#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ +#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ +#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ +#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ + /* Bits 6-7: Reserved, must be kept at reset value. */ +#define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */ + +/* Common control register */ + +/* Bits 15-0: Reserved, + * must be kept at reset value + */ + +#define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ +#define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) +# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */ +# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */ +# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */ + /* 11: Reserved */ + +/* Bits 22-18: Reserved, + * must be kept at reset value + */ +#define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ + /* Bits 31-24: Reserved, must be kept at reset value */ + +/* Data register for dual and triple modes + *(32-bit data with no named fields) + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h new file mode 100644 index 0000000000000..e8629afef8024 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h @@ -0,0 +1,735 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), + * H7, L0, L4, L4+ + */ + +#define HAVE_IP_ADC_V2 +#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ +#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ +#undef HAVE_ADC_POWERDOWN /* No ADC power down */ +#define HAVE_ADC_VBAT /* VBAT channel support */ + +/* F0 and L0 have basic version of ADC hardware (not present here for now): + * - channel selection register (CHSELR) + * - sampling time configuration common for all channels + * - one TR register + * - no SQR registers + * - ... + * + * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) + */ + +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC +# define HAVE_BASIC_ADC +# error TODO +#else +# undef HAVE_BASIC_ADC +#endif + +/* F30X and F33x don't have CFGR2 register */ + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) +# undef HAVE_ADC_CFGR2 +#else +# define HAVE_ADC_CFGR2 +#endif + +/* Base addresses ***********************************************************/ + +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0000 +#define STM32_ADC4_OFFSET 0x0100 +#define STM32_ADCCMN_OFFSET 0x0300 + +#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */ +#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */ +#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */ +#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */ +#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */ +#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */ + +/* Register Offsets *********************************************************/ + +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ +#ifdef HAVE_ADC_CFGR2 +# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#endif +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ + +/* Master and Slave ADC Common Registers */ + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ + +/* Register Addresses *******************************************************/ + +#if STM32_NADC > 0 +# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 3 +# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) +# ifdef HAVE_ADC_CFGR2 +# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) +# endif +# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) +#endif + +#if STM32_NADC > 0 +# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE + STM32_ADC_CDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* ADC interrupt and status register (ISR), and + * ADC interrupt enable register (IER) + */ + +#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ +#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ +#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ +#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ +#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ +#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ +#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ +#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ +#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ +#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ +#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ + +/* ADC control register */ + +#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ +#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ +#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ +#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */ +#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ +#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN_SHIFT (28) /* Bits 28-29: ADC voltage regulator enable */ +#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT) +# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) /* Intermediate state */ +# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator enabled */ +# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator disabled */ +#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ +#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ + +/* ADC configuration register 1 */ + +#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ +#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) +# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK cycles */ +# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK cycles */ +# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK cycles */ +# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK cycles */ +#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ +#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ +#define ADC_CFGR1_EXTSEL_MASK (15 << ADC_CFGR1_EXTSEL_SHIFT) +#if defined(CONFIG_STM32_STM32F33XX) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) + /* 0101: Reserved */ +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ +# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (7 << ADC_CFGR1_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */ +# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (8 << ADC_CFGR1_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */ +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) + /* 1100: Reserved */ +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) +#else +# error TODO EXTSEL +#endif +#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) +# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ +#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ +#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ +#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ +#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ +#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_MASK (7 << ADC_CFGR1_DISCNUM_SHIFT) +# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << \ + ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */ +#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ +#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */ +#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ +#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ +#define ADC_CFGR1_JAWD1EN (1 << 24) /* Bit 24: Analog watchdog enable 1 injected channels */ +#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */ +#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ +#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT) +# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT) + +/* TODO: ADC configuration register 2 */ + +/* ADC sample time register 1 */ + +#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ +#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */ +#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */ +#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */ +#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ +#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ +#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ +#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ + +#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ +#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) +#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ +#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT) +#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ +#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT) +#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ +#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT) +#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ +#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT) +#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ +#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT) +#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ +#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT) +#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ +#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT) +#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ +#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT) + +/* ADC sample time register 2 */ + +#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) +#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) +#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) +#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) +#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) +#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) +#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) +#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) +#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) + +/* ADC watchdog threshold register 1 */ + +#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ +#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT) +#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ +#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT) + +/* ADC watchdog threshold register 2 */ + +#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ +#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) +#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ +#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) + +/* ADC watchdog threshold register 3 */ + +#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ +#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) +#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ +#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) + +/* Offset between SQ bits */ + +#define ADC_SQ_OFFSET (6) + +/* ADC regular sequence register 1 */ + +#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */ +#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) +#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) +#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) +#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) +#define ADC_SQR1_RESERVED (0xe0820830) +#define ADC_SQR1_FIRST (1) +#define ADC_SQR1_LAST (4) +#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) + +/* ADC regular sequence register 2 */ + +#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) +#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) +#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_RESERVED (0xe0820820) +#define ADC_SQR2_FIRST (5) +#define ADC_SQR2_LAST (9) +#define ADC_SQR2_SQ_OFFSET (0) + +/* ADC regular sequence register 3 */ + +#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) +#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) +#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) +#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) +#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_RESERVED (0xe0820820) +#define ADC_SQR3_FIRST (10) +#define ADC_SQR3_LAST (14) +#define ADC_SQR3_SQ_OFFSET (0) + +/* ADC regular sequence register 4 */ + +#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) +#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) +#define ADC_SQR4_RESERVED (0xfffff820) +#define ADC_SQR4_FIRST (15) +#define ADC_SQR4_LAST (16) +#define ADC_SQR4_SQ_OFFSET (0) + +/* ADC regular data register */ + +#define ADC_DR_RDATA_SHIFT (0) +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* ADC injected sequence register */ + +#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ +#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ +#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ +#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) +#if defined(CONFIG_STM32_STM32F33XX) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) + /* 0101: Reserved */ +# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) /* 0110: EXTI line 15 */ + /* 0111: Reserved */ +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (9 << ADC_JSQR_JEXTSEL_SHIFT) /* 1001: HRTIM1 ADCTRG2 event */ +# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (10 << ADC_JSQR_JEXTSEL_SHIFT) /* 1010: HRTIM1 ADCTRG4 event */ +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +#elif defined(CONFIG_STM32_STM32F30XX) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +#else +# error TODO JEXTSEL +#endif +# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ +# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) +# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_JSQR_JEXTEN_BOTH (3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ_SHIFT (6) /* Shift between JSQx bits */ + +/* ADC offset register 1 and 2 */ + +#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ +#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) +# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) +#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ +#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) +# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) +#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ + +/* ADC injected data register 1 and 2 */ + +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC analog watchdog 2 configuration register */ + +#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) +# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ + +/* ADC analog watchdog 3 configuration register */ + +#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) +# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ + +/* ADC differential mode selection register 2 */ +#define ADC_DIFSEL_ + +#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ +#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) +# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ + +/* ADC calibration factors */ + +#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ +#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) +#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ +#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) + +/* Common status register */ + +#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ +#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ +#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ +#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ +#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ +#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ +#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ +#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ +#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ +#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ +#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ +#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ +#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ +#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ +#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ +#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ +#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ +#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ +#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ +#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ +#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ + +/* Common control register */ + +#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ +#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) +# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ +# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ +# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ +# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ +# define ADC_CCR_DUAL_INTINJ (3 << ADC_CCR_DUAL_SHIFT) /* Combined interl. mode + injected sim. */ +# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ +# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ +# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ +# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ +#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) +# define ADC_CCR_DELAY(n) (((n) - 1) << \ + ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ +#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) +# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ +# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ +# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ +#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ +#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) +# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ +# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ +# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ +# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ + +/* Common regular data register for dual mode */ + +#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ +#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) +#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ +#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h index f074647fe54dc..645174f463703 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -323,4 +323,4 @@ #define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */ #define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h new file mode 100644 index 0000000000000..314244086db37 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h @@ -0,0 +1,869 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_IP_ADC_V2 +#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ +#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ +#undef HAVE_ADC_POWERDOWN /* No ADC power down */ +#define HAVE_ADC_VBAT /* VBAT channel support */ +#undef HAVE_BASIC_ADC + +/* Base addresses ***********************************************************/ + +#define STM32_ADC1_OFFSET 0x0000 +#define STM32_ADC2_OFFSET 0x0100 +#define STM32_ADC3_OFFSET 0x0000 +#define STM32_ADC4_OFFSET 0x0100 +#define STM32_ADC5_OFFSET 0x0200 +#define STM32_ADCCMN_OFFSET 0x0300 + +#define STM32_ADC1_BASE (STM32_ADC12_BASE + STM32_ADC1_OFFSET) /* ADC1 Master ADC */ +#define STM32_ADC2_BASE (STM32_ADC12_BASE + STM32_ADC2_OFFSET) /* ADC2 Slave ADC */ +#define STM32_ADC12CMN_BASE (STM32_ADC12_BASE + STM32_ADCCMN_OFFSET) /* ADC1, ADC2 common */ +#define STM32_ADC3_BASE (STM32_ADC345_BASE + STM32_ADC3_OFFSET) /* ADC3 Master ADC */ +#define STM32_ADC4_BASE (STM32_ADC345_BASE + STM32_ADC4_OFFSET) /* ADC4 Slave ADC */ +#define STM32_ADC5_BASE (STM32_ADC345_BASE + STM32_ADC5_OFFSET) /* ADC4 Slave ADC */ +#define STM32_ADC345CMN_BASE (STM32_ADC345_BASE + STM32_ADCCMN_OFFSET) /* ADC3, ADC4 common */ + +/* Compatibility defines */ + +#define STM32_ADC34CMN_BASE STM32_ADC345CMN_BASE + +/* Register Offsets *********************************************************/ + +/* Registers for Each ADC */ + +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC Interrupt and Status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC Interrupt Enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC Control register */ +#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC Configuration register 1 */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC Configuration register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC Sample Time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC Sample Time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC Watchdog Threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC Watchdog Threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC Watchdog Threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC Regular Sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC Regular Sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC Regular Sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC Regular Sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC Regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC Injected Sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC Offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC Offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC Offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC Offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC Injected Data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC Injected Data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC Injected Data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC Injected Data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC Analog Watchdog 2 Configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC Analog Watchdog 3 Configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC Differential Mode Selection register */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC Calibration Factors register */ +#define STM32_ADC_GCOMP_OFFSET 0x00c0 /* ADC Gain compensation register */ + +/* Master and Slave ADC Common Registers */ + +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common Status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common Control register */ +#define STM32_ADC_CDR_OFFSET 0x000c /* Common Regular Data Register for Dual Mode */ + +/* Register Addresses *******************************************************/ + +/* Registers for Each ADC */ + +#if STM32_NADC > 0 +# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC1_GCOMP (STM32_ADC1_BASE + STM32_ADC_GCOMP_OFFSET) +#endif + +#if STM32_NADC > 1 +# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC2_GCOMP (STM32_ADC2_BASE + STM32_ADC_GCOMP_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC3_GCOMP (STM32_ADC3_BASE + STM32_ADC_GCOMP_OFFSET) +#endif + +#if STM32_NADC > 3 +# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC4_GCOMP (STM32_ADC4_BASE + STM32_ADC_GCOMP_OFFSET) +#endif + +#if STM32_NADC > 4 +# define STM32_ADC5_ISR (STM32_ADC5_BASE + STM32_ADC_ISR_OFFSET) +# define STM32_ADC5_IER (STM32_ADC5_BASE + STM32_ADC_IER_OFFSET) +# define STM32_ADC5_CR (STM32_ADC5_BASE + STM32_ADC_CR_OFFSET) +# define STM32_ADC5_CFGR1 (STM32_ADC5_BASE + STM32_ADC_CFGR1_OFFSET) +# define STM32_ADC5_CFGR2 (STM32_ADC5_BASE + STM32_ADC_CFGR2_OFFSET) +# define STM32_ADC5_SMPR1 (STM32_ADC5_BASE + STM32_ADC_SMPR1_OFFSET) +# define STM32_ADC5_SMPR2 (STM32_ADC5_BASE + STM32_ADC_SMPR2_OFFSET) +# define STM32_ADC5_TR1 (STM32_ADC5_BASE + STM32_ADC_TR1_OFFSET) +# define STM32_ADC5_TR2 (STM32_ADC5_BASE + STM32_ADC_TR2_OFFSET) +# define STM32_ADC5_TR3 (STM32_ADC5_BASE + STM32_ADC_TR3_OFFSET) +# define STM32_ADC5_SQR1 (STM32_ADC5_BASE + STM32_ADC_SQR1_OFFSET) +# define STM32_ADC5_SQR2 (STM32_ADC5_BASE + STM32_ADC_SQR2_OFFSET) +# define STM32_ADC5_SQR3 (STM32_ADC5_BASE + STM32_ADC_SQR3_OFFSET) +# define STM32_ADC5_SQR4 (STM32_ADC5_BASE + STM32_ADC_SQR4_OFFSET) +# define STM32_ADC5_DR (STM32_ADC5_BASE + STM32_ADC_DR_OFFSET) +# define STM32_ADC5_JSQR (STM32_ADC5_BASE + STM32_ADC_JSQR_OFFSET) +# define STM32_ADC5_OFR1 (STM32_ADC5_BASE + STM32_ADC_OFR1_OFFSET) +# define STM32_ADC5_OFR2 (STM32_ADC5_BASE + STM32_ADC_OFR2_OFFSET) +# define STM32_ADC5_OFR3 (STM32_ADC5_BASE + STM32_ADC_OFR3_OFFSET) +# define STM32_ADC5_OFR4 (STM32_ADC5_BASE + STM32_ADC_OFR4_OFFSET) +# define STM32_ADC5_JDR1 (STM32_ADC5_BASE + STM32_ADC_JDR1_OFFSET) +# define STM32_ADC5_JDR2 (STM32_ADC5_BASE + STM32_ADC_JDR2_OFFSET) +# define STM32_ADC5_JDR3 (STM32_ADC5_BASE + STM32_ADC_JDR3_OFFSET) +# define STM32_ADC5_JDR4 (STM32_ADC5_BASE + STM32_ADC_JDR4_OFFSET) +# define STM32_ADC5_AWD2CR (STM32_ADC5_BASE + STM32_ADC_AWD2CR_OFFSET) +# define STM32_ADC5_AWD3CR (STM32_ADC5_BASE + STM32_ADC_AWD3CR_OFFSET) +# define STM32_ADC5_DIFSEL (STM32_ADC5_BASE + STM32_ADC_DIFSEL_OFFSET) +# define STM32_ADC5_CALFACT (STM32_ADC5_BASE + STM32_ADC_CALFACT_OFFSET) +# define STM32_ADC5_GCOMP (STM32_ADC5_BASE + STM32_ADC_GCOMP_OFFSET) +#endif + +/* Master and Slave ADC Common Registers */ + +#if STM32_NADC > 0 +# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) +#endif + +#if STM32_NADC > 2 +# define STM32_ADC345_CSR (STM32_ADC345CMN_BASE + STM32_ADC_CSR_OFFSET) +# define STM32_ADC345_CCR (STM32_ADC345CMN_BASE + STM32_ADC_CCR_OFFSET) +# define STM32_ADC345_CDR (STM32_ADC345CMN_BASE + STM32_ADC_CDR_OFFSET) + +/* Compatibility defines */ + +# define STM32_ADC34_CSR STM32_ADC345_CSR +# define STM32_ADC34_CCR STM32_ADC345_CCR +# define STM32_ADC34_CDR STM32_ADC345_CDR +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* ADC Interrupt and Status Register (ISR), and + * ADC Interrupt Enable Register (IER) + */ + +#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ +#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ +#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ +#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ +#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ +#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ +#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ +#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ +#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ +#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ +#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ + +/* ADC Control Register (CR) */ + +#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ +#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ +#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ +#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */ +#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ +#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */ +#define ADC_CR_ADVREGEN (1 << 28) /* Bit 28: ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD (1 << 29) /* Bit 29: ADC deep power-down enable */ +#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ +#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ + +/* For compliance with the ADC driver we also define ADVREGEN like + * for previous chips. For new chips ST decided to better describe + * the mechanism behind ADVREGEN bits. + */ + +#define ADC_CR_ADVREGEN_SHIFT (28) +#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT) +# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) +# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) +# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) + +/* ADC configuration register 1 (CFGR1) */ + +#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ +#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ +#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ +#define ADC_CFGR1_RES_MASK (0x3 << ADC_CFGR1_RES_SHIFT) +# define ADC_CFGR1_RES_12BIT (0x0 << ADC_CFGR1_RES_SHIFT) /* 12-bit resolution */ +# define ADC_CFGR1_RES_10BIT (0x1 << ADC_CFGR1_RES_SHIFT) /* 10-bit resolution */ +# define ADC_CFGR1_RES_8BIT (0x2 << ADC_CFGR1_RES_SHIFT) /* 8-bit resolution */ +# define ADC_CFGR1_RES_6BIT (0x3 << ADC_CFGR1_RES_SHIFT) /* 6-bit resolution */ +#define ADC_CFGR1_EXTSEL_SHIFT (5) /* Bits 5-9: External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC2 (19 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T20CC3 (20 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC12_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ +# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_EXTI2 (5 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG2 (19 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG4 (20 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) +# define ADC34_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ +#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ +#define ADC_CFGR1_EXTEN_MASK (0x3 << ADC_CFGR1_EXTEN_SHIFT) +# define ADC_CFGR1_EXTEN_NONE (0x0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ +# define ADC_CFGR1_EXTEN_RISING (0x1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ +# define ADC_CFGR1_EXTEN_FALLING (0x2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ +# define ADC_CFGR1_EXTEN_BOTH (0x3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ +#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ +#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ +#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ +#define ADC_CFGR1_ALIGN (1 << 15) /* Bit 15: Data Alignment */ +#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT) +# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << ADC_CFGR1_DISCNUM_SHIFT) +# define ADC_CFGR1_DISCNUM_1 (0 << ADC_CFGR1_DISCNUM_SHIFT) /* 1 channel */ +# define ADC_CFGR1_DISCNUM_2 (1 << ADC_CFGR1_DISCNUM_SHIFT) /* 2 channels */ +# define ADC_CFGR1_DISCNUM_3 (2 << ADC_CFGR1_DISCNUM_SHIFT) /* 3 channels */ +# define ADC_CFGR1_DISCNUM_4 (3 << ADC_CFGR1_DISCNUM_SHIFT) /* 4 channels */ +# define ADC_CFGR1_DISCNUM_5 (4 << ADC_CFGR1_DISCNUM_SHIFT) /* 5 channels */ +# define ADC_CFGR1_DISCNUM_6 (5 << ADC_CFGR1_DISCNUM_SHIFT) /* 6 channels */ +# define ADC_CFGR1_DISCNUM_7 (6 << ADC_CFGR1_DISCNUM_SHIFT) /* 7 channels */ +# define ADC_CFGR1_DISCNUM_8 (7 << ADC_CFGR1_DISCNUM_SHIFT) /* 8 channels */ +#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ +#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */ +#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ +#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ +#define ADC_CFGR1_JAWD1EN (1 << 24) /* Bit 24: Analog watchdog enable 1 injected channels */ +#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic injected group conversion */ +#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ +#define ADC_CFGR1_AWD1CH_MASK (0x1f << ADC_CFGR1_AWD1CH_SHIFT) +# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT) +#define ADC_CFGR1_JQDIS (1 << 31) /* Bit 31: Injected queue disable */ + +/* ADC configuration register 2 (CFGR2) */ + +#define ADC_CFGR2_ROVSE (1 << 0) /* Bit 0: Regular oversampling enable */ +#define ADC_CFGR2_JOVSE (1 << 1) /* Bit 1: Injected oversampling enable */ +#define ADC_CFGR2_OVSR_SHIFT (2) /* Bits 2-4: Oversampling ratio */ +#define ADC_CFGR2_OVSR_MASK (0x7 << ADC_CFGR2_OVSR_SHIFT) +# define ADC_CFGR2_OVSR_2X (0x0 << ADC_CFGR2_OVSR_SHIFT) /* 000: 2x oversampling */ +# define ADC_CFGR2_OVSR_4X (0x1 << ADC_CFGR2_OVSR_SHIFT) /* 001: 4x oversampling */ +# define ADC_CFGR2_OVSR_8X (0x2 << ADC_CFGR2_OVSR_SHIFT) /* 010: 8x oversampling */ +# define ADC_CFGR2_OVSR_16X (0x3 << ADC_CFGR2_OVSR_SHIFT) /* 011: 16x oversampling */ +# define ADC_CFGR2_OVSR_32X (0x4 << ADC_CFGR2_OVSR_SHIFT) /* 100: 32x oversampling */ +# define ADC_CFGR2_OVSR_64X (0x5 << ADC_CFGR2_OVSR_SHIFT) /* 101: 64x oversampling */ +# define ADC_CFGR2_OVSR_128X (0x6 << ADC_CFGR2_OVSR_SHIFT) /* 110: 128x oversampling */ +# define ADC_CFGR2_OVSR_256X (0x7 << ADC_CFGR2_OVSR_SHIFT) /* 111: 256x oversampling */ +#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ +#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) +# define ADC_CFGR2_OVSS(n) ((n) << ADC_CFGR2_OVSS_SHIFT) +# define ADC_CFGR2_OVSS_NONE (0x0 << ADC_CFGR2_OVSS_SHIFT) /* 0000: No shift */ +# define ADC_CFGR2_OVSS_1_BIT (0x1 << ADC_CFGR2_OVSS_SHIFT) /* 0001: Shift 1 bits */ +# define ADC_CFGR2_OVSS_2_BIT (0x2 << ADC_CFGR2_OVSS_SHIFT) /* 0010: Shift 2 bits */ +# define ADC_CFGR2_OVSS_3_BIT (0x3 << ADC_CFGR2_OVSS_SHIFT) /* 0011: Shift 3 bits */ +# define ADC_CFGR2_OVSS_4_BIT (0x4 << ADC_CFGR2_OVSS_SHIFT) /* 0100: Shift 4 bits */ +# define ADC_CFGR2_OVSS_5_BIT (0x5 << ADC_CFGR2_OVSS_SHIFT) /* 0101: Shift 5 bits */ +# define ADC_CFGR2_OVSS_6_BIT (0x6 << ADC_CFGR2_OVSS_SHIFT) /* 0110: Shift 6 bits */ +# define ADC_CFGR2_OVSS_7_BIT (0x7 << ADC_CFGR2_OVSS_SHIFT) /* 0111: Shift 7 bits */ +# define ADC_CFGR2_OVSS_8_BIT (0x8 << ADC_CFGR2_OVSS_SHIFT) /* 1000: Shift 8 bits */ +#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered regular oversampling */ +#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular oversampling mode */ +#define ADC_CFGR2_GCOMP (1 << 16) /* Bit 16: Gain compensation mode */ +#define ADC_CFGR2_SWTRIG (1 << 25) /* Bit 25: Software trigger for sampling time control trigger mode */ +#define ADC_CFGR2_BULB (1 << 26) /* Bit 26: Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG (1 << 27) /* Bit 27: Sampling time control trigger mode */ + +/* ADC sample time values for use with SMPR1 and SMPR2 bitfields */ + +#define ADC_SMPR_2p5 0x0 /* 000: Sample for 2.5 cycles */ +#define ADC_SMPR_6p5 0x1 /* 001: Sample for 6.5 cycles */ +#define ADC_SMPR_12p5 0x2 /* 010: Sample for 12.5 cycles */ +#define ADC_SMPR_24p5 0x3 /* 011: Sample for 24.5 cycles */ +#define ADC_SMPR_47p5 0x4 /* 100: Sample for 47.5 cycles */ +#define ADC_SMPR_92p5 0x5 /* 101: Sample for 92.5 cycles */ +#define ADC_SMPR_247p5 0x6 /* 110: Sample for 247.5 cycles */ +#define ADC_SMPR_640p5 0x7 /* 111: Sample for 640.5 cycles */ + +/* ADC sample time register 1 (SMPR1) */ + +#define ADC_SMPR1_SMP0_SHIFT (0) /* Bits 0-2: Channel 0 Sample time selection */ +#define ADC_SMPR1_SMP0_MASK (0x7 << ADC_SMPR1_SMP1_SHIFT) +#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 3-5: Channel 1 Sample time selection */ +#define ADC_SMPR1_SMP1_MASK (0x7 << ADC_SMPR1_SMP1_SHIFT) +#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 6-8: Channel 2 Sample time selection */ +#define ADC_SMPR1_SMP2_MASK (0x7 << ADC_SMPR1_SMP2_SHIFT) +#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 9-11: Channel 3 Sample time selection */ +#define ADC_SMPR1_SMP3_MASK (0x7 << ADC_SMPR1_SMP3_SHIFT) +#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 12-14: Channel 4 Sample time selection */ +#define ADC_SMPR1_SMP4_MASK (0x7 << ADC_SMPR1_SMP4_SHIFT) +#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 15-17: Channel 5 Sample time selection */ +#define ADC_SMPR1_SMP5_MASK (0x7 << ADC_SMPR1_SMP5_SHIFT) +#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 18-20: Channel 6 Sample time selection */ +#define ADC_SMPR1_SMP6_MASK (0x7 << ADC_SMPR1_SMP6_SHIFT) +#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 21-23: Channel 7 Sample time selection */ +#define ADC_SMPR1_SMP7_MASK (0x7 << ADC_SMPR1_SMP7_SHIFT) +#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 24-26: Channel 8 Sample time selection */ +#define ADC_SMPR1_SMP8_MASK (0x7 << ADC_SMPR1_SMP8_SHIFT) +#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 27-29: Channel 9 Sample time selection */ +#define ADC_SMPR1_SMP9_MASK (0x7 << ADC_SMPR1_SMP9_SHIFT) +#define ADC_SMPR1_SMPPLUS (1 << 31) /* Bit 31: Addition of one clock cycle to the sampling time */ + +/* ADC sample time register 2 (SMPR2) */ + +#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ +#define ADC_SMPR2_SMP10_MASK (0x7 << ADC_SMPR2_SMP10_SHIFT) +#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ +#define ADC_SMPR2_SMP11_MASK (0x7 << ADC_SMPR2_SMP11_SHIFT) +#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ +#define ADC_SMPR2_SMP12_MASK (0x7 << ADC_SMPR2_SMP12_SHIFT) +#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ +#define ADC_SMPR2_SMP13_MASK (0x7 << ADC_SMPR2_SMP13_SHIFT) +#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ +#define ADC_SMPR2_SMP14_MASK (0x7 << ADC_SMPR2_SMP14_SHIFT) +#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ +#define ADC_SMPR2_SMP15_MASK (0x7 << ADC_SMPR2_SMP15_SHIFT) +#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ +#define ADC_SMPR2_SMP16_MASK (0x7 << ADC_SMPR2_SMP16_SHIFT) +#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ +#define ADC_SMPR2_SMP17_MASK (0x7 << ADC_SMPR2_SMP17_SHIFT) +#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ +#define ADC_SMPR2_SMP18_MASK (0x7 << ADC_SMPR2_SMP18_SHIFT) + +/* ADC watchdog threshold register 1 (TR1) */ + +#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ +#define ADC_TR1_LT_MASK (0xfff << ADC_TR1_LT_SHIFT) +#define ADC_TR1_AWDFILT_SHIFT (12) /* Bits 12-14: Analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_MASK (0x7 << ADC_TR1_AWDFILT_SHIFT) +# define ADC_TR1_AWDFILT(n) (((n) - 1) << ADC_TR1_AWDFILT_SHIFT) +# define ADC_TR1_AWDFILT_NONE (0x0 << ADC_TR1_AWDFILT_SHIFT) /* 000: No filtering */ +# define ADC_TR1_AWDFILT_2 (0x1 << ADC_TR1_AWDFILT_SHIFT) /* 001: Two consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_3 (0x2 << ADC_TR1_AWDFILT_SHIFT) /* 010: Three consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_4 (0x3 << ADC_TR1_AWDFILT_SHIFT) /* 011: Four consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_5 (0x4 << ADC_TR1_AWDFILT_SHIFT) /* 100: Five consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_6 (0x5 << ADC_TR1_AWDFILT_SHIFT) /* 101: Six consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_7 (0x6 << ADC_TR1_AWDFILT_SHIFT) /* 110: Seven consecutive detections generate an AWDx flag or interrupt */ +# define ADC_TR1_AWDFILT_8 (0x7 << ADC_TR1_AWDFILT_SHIFT) /* 111: Eight consecutive detections generate an AWDx flag or interrupt */ +#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ +#define ADC_TR1_HT_MASK (0xfff << ADC_TR1_HT_SHIFT) + +/* ADC watchdog threshold register 2 (TR2) */ + +#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ +#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) +#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ +#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) + +/* ADC watchdog threshold register 3 (TR3) */ + +#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ +#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) +#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ +#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) + +/* ADC regular sequence register 1 (SQR1) */ + +#define ADC_SQ_OFFSET (6) /* Offset between SQ bitfields in SQR1..SQR4 */ + +#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ +#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) +# define ADC_SQR1_L(n) (((n) - 1) << ADC_SQR1_L_SHIFT) +# define ADC_SQR1_L_1 (0x0 << ADC_SQR1_L_SHIFT) /* 1 conversion */ +# define ADC_SQR1_L_2 (0x1 << ADC_SQR1_L_SHIFT) /* 2 conversions */ +# define ADC_SQR1_L_3 (0x2 << ADC_SQR1_L_SHIFT) /* 3 conversions */ +# define ADC_SQR1_L_4 (0x3 << ADC_SQR1_L_SHIFT) /* 4 conversions */ +# define ADC_SQR1_L_5 (0x4 << ADC_SQR1_L_SHIFT) /* 5 conversion */ +# define ADC_SQR1_L_6 (0x5 << ADC_SQR1_L_SHIFT) /* 6 conversions */ +# define ADC_SQR1_L_7 (0x6 << ADC_SQR1_L_SHIFT) /* 7 conversions */ +# define ADC_SQR1_L_8 (0x7 << ADC_SQR1_L_SHIFT) /* 8 conversions */ +# define ADC_SQR1_L_9 (0x8 << ADC_SQR1_L_SHIFT) /* 9 conversion */ +# define ADC_SQR1_L_10 (0x9 << ADC_SQR1_L_SHIFT) /* 10 conversions */ +# define ADC_SQR1_L_11 (0xa << ADC_SQR1_L_SHIFT) /* 11 conversions */ +# define ADC_SQR1_L_12 (0xb << ADC_SQR1_L_SHIFT) /* 12 conversions */ +# define ADC_SQR1_L_13 (0xc << ADC_SQR1_L_SHIFT) /* 13 conversion */ +# define ADC_SQR1_L_14 (0xd << ADC_SQR1_L_SHIFT) /* 14 conversions */ +# define ADC_SQR1_L_15 (0xe << ADC_SQR1_L_SHIFT) /* 15 conversions */ +# define ADC_SQR1_L_16 (0xf << ADC_SQR1_L_SHIFT) /* 16 conversions */ +#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) +#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) +#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) +#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) +#define ADC_SQR1_RESERVED (0xe0820830) /* Mask of all reserved bits: 4, 5, 11, 17, 23, 29, 30, 31 */ +#define ADC_SQR1_FIRST (1) +#define ADC_SQR1_LAST (4) +#define ADC_SQR1_SQ_OFFSET (1 * ADC_SQ_OFFSET) /* Offset to first SQ bitfield in the register */ + +/* ADC regular sequence register 2 (SQR2) */ + +#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 0-4: 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) +#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) +#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) +#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) +#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) +#define ADC_SQR2_RESERVED (0xe0820820) /* Mask of all reserved bits: 5, 11, 17, 23, 29, 30, 31 */ +#define ADC_SQR2_FIRST (5) +#define ADC_SQR2_LAST (9) +#define ADC_SQR2_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ + +/* ADC regular sequence register 3 (SQR3) */ + +#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 0-4: 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) +#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) +#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) +#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) +#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) +#define ADC_SQR3_RESERVED (0xe0820820) /* Mask of all reserved bits: 5, 11, 17, 23, 29, 30, 31 */ +#define ADC_SQR3_FIRST (10) +#define ADC_SQR3_LAST (14) +#define ADC_SQR3_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ + +/* ADC regular sequence register 4 (SQR4) */ + +#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 0-4: 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) +#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) +#define ADC_SQR4_RESERVED (0xfffff820) /* Mask of all reserved bits: 5, 11-31 */ +#define ADC_SQR4_FIRST (15) +#define ADC_SQR4_LAST (16) +#define ADC_SQR4_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ + +/* ADC regular data register (DR) */ + +#define ADC_DR_RDATA_SHIFT (0) /* Bits 0-15: Regular data converted */ +#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) + +/* ADC injected sequence register (JSQR) */ + +#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected channel sequence length */ +#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL(n) (((n) - 1) << ADC_JSQR_JL_SHIFT) +# define ADC_JSQR_JL_1 (0x0 << ADC_JSQR_JL_SHIFT) /* 1 conversion */ +# define ADC_JSQR_JL_2 (0x1 << ADC_JSQR_JL_SHIFT) /* 2 conversions */ +# define ADC_JSQR_JL_3 (0x2 << ADC_JSQR_JL_SHIFT) /* 3 conversions */ +# define ADC_JSQR_JL_4 (0x3 << ADC_JSQR_JL_SHIFT) /* 4 conversions */ +#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-6: External trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_MASK (0x1f << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T20CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T16CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_RSVD1 (28 << ADC_JSQR_JEXTSEL_SHIFT) /* 11100: Reserved */ +# define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_RSVD2 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ +# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T20CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_HRT1TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC34_JSQR_JEXTSEL_RSVD1 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ +#define ADC_JSQR_JEXTEN_SHIFT (7) /* Bits 7-8: External trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_MASK (0x3 << ADC_JSQR_JEXTEN_SHIFT) +# define ADC_JSQR_JEXTEN_NONE (0x0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ +# define ADC_JSQR_JEXTEN_RISING (0x1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ +# define ADC_JSQR_JEXTEN_FALLING (0x2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ +# define ADC_JSQR_JEXTEN_BOTH (0x3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ +#define ADC_JSQR_JSQ1_SHIFT (9) /* Bits 9-13: 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) +# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ2_SHIFT (15) /* Bits 15-19: 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) +# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ3_SHIFT (21) /* Bits 21-25: 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) +# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ4_SHIFT (27) /* Bits 27-31: 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) +# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */ +#define ADC_JSQR_JSQ_SHIFT (6) /* Shift between JSQx bits */ + +/* ADC offset register 1 thru 4 (OFR1, OFR2, OFR3, OFR4) */ + +#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ +#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) +# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) +#define ADC_OFR_OFFSETPOS (1 << 24) /* Bit 24: Positive offset (0=negative, 1=positive) */ +#define ADC_OFR_SATEN (1 << 25) /* Bit 25: Saturation enable */ +#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ +#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) +# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) +#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ + +/* ADC injected data register 1 and 2 (JDR1, JDR2) */ + +#define ADC_JDR_JDATA_SHIFT (0) +#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) + +/* ADC analog watchdog 2 configuration register (AWD2CR) */ + +#define ADC_AWD2CR_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_CH_MASK (0x7ffff << ADC_AWD2CR_CH_SHIFT) +# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=0..18 */ + +/* ADC analog watchdog 3 configuration register (AWD3CR) */ + +#define ADC_AWD3CR_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_CH_MASK (0x7ffff << ADC_AWD3CR_CH_SHIFT) +# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=0..18 */ + +/* ADC differential mode selection register (DIFSEL) */ + +#define ADC_DIFSEL_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ +#define ADC_DIFSEL_CH_MASK (0x7ffff << ADC_DIFSEL_CH_SHIFT) +# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=0..18 */ + +/* ADC calibration factors register (CALFACT) */ + +#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ +#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) +#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration factors in differential mode */ +#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) + +/* ADC gain compensation register (GCOMP) */ + +#define ADC_GCOMP_SHIFT (0) /* Bits 0-13: Gain compensation coefficient */ +#define ADC_GCOMP_MASK (0x3fff << ADC_GCOMP_SHIFT) + +/* ADC12, ADC345 - Common status register (CSR) */ + +#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ +#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ +#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ +#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ +#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ +#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ +#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ +#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ +#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ +#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ +#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ +#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ +#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ +#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ +#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ +#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ +#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ +#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ +#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ +#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ +#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ + +/* ADC12, ADC345 - Common control register (CCR) */ + +#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ +#define ADC_CCR_DUAL_MASK (0x1f << ADC_CCR_DUAL_SHIFT) +# define ADC_CCR_DUAL_IND (0x0 << ADC_CCR_DUAL_SHIFT) /* 00000: Independent mode */ +# define ADC_CCR_DUAL_DUAL (0x1 << ADC_CCR_DUAL_SHIFT) /* 00001: Dual mode, master/slave ADCs together */ +# define ADC_CCR_DUAL_SIMINJ (0x1 << ADC_CCR_DUAL_SHIFT) /* 00001: Combined regular sim. + injected sim. */ +# define ADC_CCR_DUAL_SIMALT (0x2 << ADC_CCR_DUAL_SHIFT) /* 00010: Combined regular sim. + alternate trigger */ +# define ADC_CCR_DUAL_INTINJ (0x3 << ADC_CCR_DUAL_SHIFT) /* 00011: Combined interl. mode + injected sim. */ +# define ADC_CCR_DUAL_INJECTED (0x5 << ADC_CCR_DUAL_SHIFT) /* 00101: Injected simultaneous mode only */ +# define ADC_CCR_DUAL_SIM (0x6 << ADC_CCR_DUAL_SHIFT) /* 00110: Regular simultaneous mode only */ +# define ADC_CCR_DUAL_INTERLEAVE (0x7 << ADC_CCR_DUAL_SHIFT) /* 00111: Interleaved mode only */ +# define ADC_CCR_DUAL_ALT (0x9 << ADC_CCR_DUAL_SHIFT) /* 01001: Alternate trigger mode only */ +#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ +# define ADC_CCR_DELAY(n) (((n) - 1) << ADC_CCR_DELAY_SHIFT) +#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_MASK (0x3 << ADC_CCR_MDMA_SHIFT) +# define ADC_CCR_MDMA_DISABLED (0x0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ +# define ADC_CCR_MDMA_10_12 (0x2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ +# define ADC_CCR_MDMA_6_8 (0x3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ +#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ +#define ADC_CCR_CKMODE_MASK (0x3 << ADC_CCR_CKMODE_SHIFT) +# define ADC_CCR_CKMODE_ASYNCH (0x0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ +# define ADC_CCR_CKMODE_SYNCH_DIV1 (0x1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ +# define ADC_CCR_CKMODE_SYNCH_DIV2 (0x2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ +# define ADC_CCR_CKMODE_SYNCH_DIV4 (0x3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ +#define ADC_CCR_PRESC_SHIFT (18) /* Bits 18-21: ADC prescaler */ +#define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) +# define ADC_CCR_PRESC_1 (0x0 << ADC_CCR_PRESC_SHIFT) /* 0000: Input ADC clock not divided */ +# define ADC_CCR_PRESC_2 (0x1 << ADC_CCR_PRESC_SHIFT) /* 0001: Input ADC clock divided by 2 */ +# define ADC_CCR_PRESC_4 (0x2 << ADC_CCR_PRESC_SHIFT) /* 0010: Input ADC clock divided by 4 */ +# define ADC_CCR_PRESC_6 (0x3 << ADC_CCR_PRESC_SHIFT) /* 0011: Input ADC clock divided by 6 */ +# define ADC_CCR_PRESC_8 (0x4 << ADC_CCR_PRESC_SHIFT) /* 0100: Input ADC clock divided by 8 */ +# define ADC_CCR_PRESC_10 (0x5 << ADC_CCR_PRESC_SHIFT) /* 0101: Input ADC clock divided by 10 */ +# define ADC_CCR_PRESC_12 (0x6 << ADC_CCR_PRESC_SHIFT) /* 0110: Input ADC clock divided by 12 */ +# define ADC_CCR_PRESC_16 (0x7 << ADC_CCR_PRESC_SHIFT) /* 0111: Input ADC clock divided by 16 */ +# define ADC_CCR_PRESC_32 (0x8 << ADC_CCR_PRESC_SHIFT) /* 1000: Input ADC clock divided by 32 */ +# define ADC_CCR_PRESC_64 (0x9 << ADC_CCR_PRESC_SHIFT) /* 1001: Input ADC clock divided by 64 */ +# define ADC_CCR_PRESC_128 (0xa << ADC_CCR_PRESC_SHIFT) /* 1010: Input ADC clock divided by 128 */ +# define ADC_CCR_PRESC_256 (0xb << ADC_CCR_PRESC_SHIFT) /* 1011: Input ADC clock divided by 256 */ +#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ +#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ +#define ADC_CCR_VBATEN (1 << 24) /* Bit 24: VBAT enable */ + +/* Common regular data register for dual mode */ + +#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the Master ADC */ +#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) +#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */ +#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_aes.h b/arch/arm/src/common/stm32/hardware/stm32_aes.h new file mode 100644 index 0000000000000..2f1342a749235 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_aes.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_aes.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES register offsets *****************************************************/ + +#define STM32_AES_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_AES_SR_OFFSET 0x0004 /* Status Register */ +#define STM32_AES_DINR_OFFSET 0x0008 /* Data Input Register */ +#define STM32_AES_DOUTR_OFFSET 0x000C /* Data Output Register */ +#define STM32_AES_KEYR0_OFFSET 0x0010 /* AES Key Register 0 */ +#define STM32_AES_KEYR1_OFFSET 0x0014 /* AES Key Register 1 */ +#define STM32_AES_KEYR2_OFFSET 0x0018 /* AES Key Register 2 */ +#define STM32_AES_KEYR3_OFFSET 0x001C /* AES Key Register 3 */ +#define STM32_AES_IVR0_OFFSET 0x0020 /* AES Initialization Vector Register 0 */ +#define STM32_AES_IVR1_OFFSET 0x0024 /* AES Initialization Vector Register 1 */ +#define STM32_AES_IVR2_OFFSET 0x0028 /* AES Initialization Vector Register 2 */ +#define STM32_AES_IVR3_OFFSET 0x002C /* AES Initialization Vector Register 3 */ + +/* AES register addresses ***************************************************/ + +#define STM32_AES_CR (STM32_AES_BASE + STM32_AES_CR_OFFSET) +#define STM32_AES_SR (STM32_AES_BASE + STM32_AES_SR_OFFSET) +#define STM32_AES_DINR (STM32_AES_BASE + STM32_AES_DINR_OFFSET) +#define STM32_AES_DOUTR (STM32_AES_BASE + STM32_AES_DOUTR_OFFSET) +#define STM32_AES_KEYR0 (STM32_AES_BASE + STM32_AES_KEYR0_OFFSET) +#define STM32_AES_KEYR1 (STM32_AES_BASE + STM32_AES_KEYR1_OFFSET) +#define STM32_AES_KEYR2 (STM32_AES_BASE + STM32_AES_KEYR2_OFFSET) +#define STM32_AES_KEYR3 (STM32_AES_BASE + STM32_AES_KEYR3_OFFSET) +#define STM32_AES_IVR0 (STM32_AES_BASE + STM32_AES_IVR0_OFFSET) +#define STM32_AES_IVR1 (STM32_AES_BASE + STM32_AES_IVR1_OFFSET) +#define STM32_AES_IVR2 (STM32_AES_BASE + STM32_AES_IVR2_OFFSET) +#define STM32_AES_IVR3 (STM32_AES_BASE + STM32_AES_IVR3_OFFSET) + +/* AES register bit definitions *********************************************/ + +/* AES_CR register */ + +#define AES_CR_EN (1 << 0) /* AES Enable */ +#define AES_CR_DATATYPE (1 << 1) /* Data type selection */ +# define AES_CR_DATATYPE_LE (0x0 << 1) +# define AES_CR_DATATYPE_BE (0x2 << 1) + +#define AES_CR_MODE (1 << 3) /* AES Mode of operation */ +# define AES_CR_MODE_ENCRYPT (0x0 << 3) +# define AES_CR_MODE_KEYDERIV (0x1 << 3) +# define AES_CR_MODE_DECRYPT (0x2 << 3) +# define AES_CR_MODE_DECRYPT_KEYDERIV (0x3 << 3) + +#define AES_CR_CHMOD (1 << 5) /* AES Chaining Mode */ +# define AES_CR_CHMOD_ECB (0x0 << 5) +# define AES_CR_CHMOD_CBC (0x1 << 5) +# define AES_CR_CHMOD_CTR (0x2 << 5) + +#define AES_CR_CCFC (1 << 7) /* Computation Complete Flag Clear */ +#define AES_CR_ERRC (1 << 8) /* Error Clear */ +#define AES_CR_CCIE (1 << 9) /* Computation Complete Interrupt Enable */ +#define AES_CR_ERRIE (1 << 10) /* Error Interrupt Enable */ +#define AES_CR_DMAINEN (1 << 11) /* DMA Enable Input */ +#define AES_CR_DMAOUTEN (1 << 12) /* DMA Enable Output */ + +/* AES_SR register */ + +#define AES_SR_CCF (1 << 0) /* Computation Complete Flag */ +#define AES_SR_RDERR (1 << 1) /* Read Error Flag */ +#define AES_SR_WRERR (1 << 2) /* Write Error Flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_bkp.h b/arch/arm/src/common/stm32/hardware/stm32_bkp.h new file mode 100644 index 0000000000000..f37ffd14f1680 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_bkp.h @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_bkp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define CONFIG_STM32_NBKP_BYTES 84 +# define CONFIG_STM32_NBKP_REGS 42 +#else +# define CONFIG_STM32_NBKP_BYTES 20 +# define CONFIG_STM32_NBKP_REGS 10 +#endif + +/* Register Offsets *********************************************************/ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) +#else +# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) +#endif + +#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ +#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ +#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ +#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ +#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ +#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ +#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ +#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ +#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ +#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ + +#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ +#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ +#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ +# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ +# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ +# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ +# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ +# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ +# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ +# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ +# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ +# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ +# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ +# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ +# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ +# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ +# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ +# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ +# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ +# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ +# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ +# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ +# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ +# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ +# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ +# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ +# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ +# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ +# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ +# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ +# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ +# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ +# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ +# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ +#endif + +/* Register Addresses *******************************************************/ + +#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) +#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) +#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) + +#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) +#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) +#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) +#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) +#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) +#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) +#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) +#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) +#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) +#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) +#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) + +#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) +# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) +# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) +# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) +# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) +# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) +# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) +# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) +# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) +# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) +# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) +# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) +# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) +# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) +# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) +# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) +# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) +# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) +# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) +# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) +# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) +# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) +# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) +# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) +# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) +# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) +# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) +# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) +# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) +# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) +# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) +# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* RTC clock calibration register */ + +#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ +#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) +#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ +#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ + +/* Backup control register */ + +#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ +#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ + +/* Backup control/status register */ + +#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ +#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ +#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ +#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ + +/* Backup data register */ + +#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ +#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can.h new file mode 100644 index 0000000000000..6f8bdc2d273ae --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)) > 1 +# error Only one STM32 CAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) +# include "hardware/stm32_can_bxcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# include "hardware/stm32_can_bxcan.h" +#else +# error "Unsupported STM32 CAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h index f1c0fa67523b0..0de8ea6e5bef5 100644 --- a/arch/arm/src/stm32/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H /**************************************************************************** * Included Files @@ -437,14 +437,14 @@ /* CAN filter master register */ #define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */ # define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT) #endif /* CAN filter mode register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ # define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) #else @@ -454,7 +454,7 @@ /* CAN filter scale register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ # define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) #else @@ -464,7 +464,7 @@ /* CAN filter FIFO assignment register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ # define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) #else @@ -474,7 +474,7 @@ /* CAN filter activation register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ # define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) #else @@ -494,4 +494,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h index 774855c7f8fbe..378e5a03df55d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H /**************************************************************************** * Included Files @@ -453,4 +453,4 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp.h new file mode 100644 index 0000000000000..364b1f8a418a6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)) > 1 +# error Only one STM32 COMP IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) +# include "hardware/stm32_comp_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) +# include "hardware/stm32_comp_v1v2.h" +#else +# error "Unsupported STM32 COMP" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_m0.h index 5d96fe86f47b4..06672e2ff1dae 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ #define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ #define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h similarity index 79% rename from arch/arm/src/stm32/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h index 414f7e62739eb..94c93d429ba9a 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H /**************************************************************************** * Included Files @@ -39,15 +39,15 @@ /* If more than one COMP IP ensure that only one is selected */ -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # if defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_comp.h" +# include "hardware/stm32f33xxx_comp.h" # else # error "Device not supported." # endif -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_comp.h" +# include "hardware/stm32g4xxxx_comp.h" # else # error "Device not supported." # endif @@ -57,4 +57,4 @@ #endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_crc.h b/arch/arm/src/common/stm32/hardware/stm32_crc.h new file mode 100644 index 0000000000000..6b51ac8e12bdd --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_crc.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_crc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_CRC_DR_OFFSET 0x0000 /* Data register */ +#define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */ +#define STM32_CRC_CR_OFFSET 0x0008 /* Control register */ +#define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */ +#define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */ + +/* Register Addresses *******************************************************/ + +#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET) +#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET) +#define STM32_CRC_CR (STM32_CRC_BASE + STM32_CRC_CR_OFFSET) +#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET) +#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* CRC independent data register */ + +#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */ + +/* CRC control register */ + +#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */ +#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */ +#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT) +# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */ +# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */ +# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ +# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ + +#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits control the reversal of the bit order of the input data */ +#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) +# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ +# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ +# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */ +# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ + +#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_crs.h b/arch/arm/src/common/stm32/hardware/stm32_crs.h new file mode 100644 index 0000000000000..b544f9728c819 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_crs.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_crs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ + +/* Register Addresses *******************************************************/ + +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* CRS control register */ + +#define CRS_CR_SYNCOKIE (1 << 0) /* Bit 0: SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE (1 << 1) /* Bit 1: SYNC warning interrupt enable */ +#define CRS_CR_ERRIE (1 << 2) /* Bit 2: Synchronization or Trimming error interrupt enabled */ +#define CRS_CR_ESYNCIE (1 << 3) /* Bit 3: Expected SYNC interrupt enable */ +#define CRS_CR_CEN (1 << 5) /* Bit 5: Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN (1 << 6) /* Bit 6: Automatic trimming enabled */ +#define CRS_CR_SWSYNC (1 << 7) /* Bit 7: Generate software SYNC event */ +#define CRS_CR_TRIM_SHIFT 8 /* Bits 8-13: HSI48 oscillator smooth trimming */ +#define CRS_CR_TRIM_MASK (0x3f << CRS_CR_TRIM_SHIFT) + +/* CRS configuration register */ + +#define CRS_CFGR_RELOAD_SHIFT 0 /* Bits 0-15: Counter reload value */ +#define CRS_CFGR_RELOAD_MASK (0xffff << CRS_CFGR_RELOAD_SHIFT) +#define CRS_CFGR_FELIM_SHIFT 16 /* Bits 16-23: Frequency error limit */ +#define CRS_CFGR_FELIM_MASK (0xff << CRS_CFGR_FELIM_SHIFT) +#define CRS_CFGR_SYNCDIV_SHIFT 24 /* Bits 24-26: SYNC divider */ +#define CRS_CFGR_SYNCDIV_MASK (7 << CRS_CFGR_SYNCDIV_SHIFT) +# define CRS_CFGR_SYNCDIV_d1 (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */ +# define CRS_CFGR_SYNCDIV_d2 (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */ +# define CRS_CFGR_SYNCDIV_d4 (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */ +# define CRS_CFGR_SYNCDIV_d8 (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */ +# define CRS_CFGR_SYNCDIV_d16 (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */ +# define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */ +# define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */ +# define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */ + +#define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT) +# define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */ +# define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */ +# define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */ + +#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */ + +/* CRS interrupt and status register */ + +#define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ +#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */ +#define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ +#define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ +#define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ +#define CRS_ISR_TRIMOVF (1 << 10) /* Bit 10: Trimming overflow or underflow */ +#define CRS_ISR_FEDIR (1 << 15) /* Bit 15: Frequency error direction */ +#define CRS_ISR_FECAP_SHIFT 16 /* Bits 16-31: Frequency error capture */ +#define CRS_ISR_FECAP_MASK (0xffff << CRS_ISR_FECAP_SHIFT) + +/* CRS interrupt flag clear register */ + +#define CRS_ICR_SYNCOKC (1 << 0) /* Bit 0: SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC (1 << 1) /* Bit 1: SYNC warning clear flag */ +#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ +#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac.h new file mode 100644 index 0000000000000..dd8df7ed9b1bd --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) > 1 +# error Only one STM32 DAC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) +# include "hardware/stm32_dac_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "hardware/stm32_dac_v1v2.h" +#else +# error "Unsupported STM32 DAC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_m0.h index 7b5262432c060..f95f33e87c2f2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H /**************************************************************************** * Included Files @@ -208,4 +208,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h new file mode 100644 index 0000000000000..8e213a40b0588 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h @@ -0,0 +1,315 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* This is implementation for STM32 DAC IPv1 - F1, F2, F3, F4, F7, L1, L4 */ + +#define HAVE_IP_DAC_V1 +#undef HAVE_IP_DAC_V2 /* No DAC IPv2 */ + +/* Register Offsets *********************************************************/ + +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NDAC > 0 +/* DAC1 */ + +# define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) +# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) +# define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) +# define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) + +#endif + +#if STM32_NDAC > 2 +/* DAC2 */ + +# define STM32_DAC2_CR (STM32_DAC2_BASE + STM32_DAC_CR_OFFSET) +# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE + STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE + STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE + STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE + STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE + STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE + STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE + STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE + STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE + STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE + STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC2_DOR1 (STM32_DAC2_BASE + STM32_DAC_DOR1_OFFSET) +# define STM32_DAC2_DOR2 (STM32_DAC2_BASE + STM32_DAC_DOR2_OFFSET) +# define STM32_DAC2_SR (STM32_DAC2_BASE + STM32_DAC_SR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* DAC control register */ + +/* These definitions may be used for 16-bit values of either channel */ + +#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel enable */ +#define DAC_CR_BOFF (1 << 1) /* Bit 1: 1=DAC channel output buffer disable */ +#define DAC_CR_BOFF_EN (0 << 1) /* Bit 1: 0=DAC channel output buffer enable */ +#define DAC_CR_TEN (1 << 2) /* Bit 2: DAC channel trigger enable */ +#define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel trigger selection */ +#define DAC_CR_TSEL_MASK (7 << DAC_CR_TSEL_SHIFT) +# define DAC_CR_TSEL_TIM6 (0 << DAC_CR_TSEL_SHIFT) /* Timer 6 TRGO event */ +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL_TIM3 (1 << DAC_CR_TSEL_SHIFT) /* Timer 3 TRGO event */ +#else +# define DAC_CR_TSEL_TIM8 (1 << DAC_CR_TSEL_SHIFT) /* Timer 8 TRGO event */ +#endif +# define DAC_CR_TSEL_TIM7 (2 << DAC_CR_TSEL_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL_TIM15 (3 << DAC_CR_TSEL_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL_HRT1TRG1 (3 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG1 event */ +#else +# define DAC_CR_TSEL_TIM5 (3 << DAC_CR_TSEL_SHIFT) /* Timer 5 TRGO event */ +#endif +# define DAC_CR_TSEL_TIM2 (4 << DAC_CR_TSEL_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL_HRT1TRG2 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG2 event, or */ +# define DAC_CR_TSEL_HRT1TRG3 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG3 event */ +#else +# define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */ +#endif +# define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */ +# define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */ +#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */ +#define DAC_CR_WAVE_MASK (3 << DAC_CR_WAVE_SHIFT) +# define DAC_CR_WAVE_DISABLED (0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE_NOISE (1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE_TRIANGLE (2 << DAC_CR_WAVE_SHIFT) /* Triangle wave generation enabled */ +#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel mask/amplitude selector */ +#define DAC_CR_MAMP_MASK (15 << DAC_CR_MAMP_SHIFT) +# define DAC_CR_MAMP_AMP1 (0 << DAC_CR_MAMP_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ +# define DAC_CR_MAMP_AMP3 (1 << DAC_CR_MAMP_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ +# define DAC_CR_MAMP_AMP7 (2 << DAC_CR_MAMP_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ +# define DAC_CR_MAMP_AMP15 (3 << DAC_CR_MAMP_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ +# define DAC_CR_MAMP_AMP31 (4 << DAC_CR_MAMP_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ +# define DAC_CR_MAMP_AMP63 (5 << DAC_CR_MAMP_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ +# define DAC_CR_MAMP_AMP127 (6 << DAC_CR_MAMP_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ +# define DAC_CR_MAMP_AMP255 (7 << DAC_CR_MAMP_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ +# define DAC_CR_MAMP_AMP511 (8 << DAC_CR_MAMP_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ +# define DAC_CR_MAMP_AMP1023 (9 << DAC_CR_MAMP_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ +# define DAC_CR_MAMP_AMP2047 (10 << DAC_CR_MAMP_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ +# define DAC_CR_MAMP_AMP4095 (11 << DAC_CR_MAMP_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ +#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel DMA enable */ +#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel DMA Underrun Interrupt enable */ + +/* These definitions may be used with the full, 32-bit register */ + +#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ +#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ +#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ +#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ +#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) +# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ +#else +# define DAC_CR_TSEL1_TIM8 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 8 TRGO event */ +#endif +# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL1_HRT1TRG1 (3 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG1 event (DAC1 only) */ +#else +# define DAC_CR_TSEL1_TIM5 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 5 TRGO event */ +#endif +# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL1_HRT1TRG2 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG2 event (DAC1), or */ +# define DAC_CR_TSEL1_HRT1TRG3 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG3 event (DAC2) */ +#else +# define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */ +#endif +# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ +# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ +#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ +#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) +# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ +#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ +#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) +# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ +# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ +# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ +# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ +# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ +# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ +# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ +# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ +# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ +# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ +# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ +# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ +#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ +#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ + +#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ +#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ +#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ +#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ +#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) +# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ +#else +# define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ +#endif +# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_TIM15 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 15 TRGO event, or */ +# define DAC_CR_TSEL2_HRT1TRG1 (3 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG1 event */ +#else +# define DAC_CR_TSEL2_TIM5 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 5 TRGO event */ +#endif +# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ +#if defined(CONFIG_STM32_STM32F33XX) +# define DAC_CR_TSEL2_HRT1TRG2 (5 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG2 event */ +#else +# define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ +#endif +# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ +# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ +#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ +#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) +# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ +#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ +#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) +# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ +# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ +# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ +# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ +# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ +# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ +# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ +# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ +# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ +# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ +# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ +# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ +#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ +#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ + +/* DAC software trigger register */ + +#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ + +/* DAC channel 1/2 12-bit right-aligned data holding register */ + +#define DAC_DHR12R_MASK (0x0fff) + +/* DAC channel 1/2 12-bit left aligned data holding register */ + +#define DAC_DHR12L_MASK (0xfff0) + +/* DAC channel 1/2 8-bit right aligned data holding register */ + +#define DAC_DHR8R_MASK (0x00ff) + +/* Dual DAC 12-bit right-aligned data holding register */ + +#define DAC_DHR12RD_DACC_SHIFT(n) (((n)-1) << 4) +#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) + +#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) +#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) + +/* Dual DAC 12-bit left-aligned data holding register */ + +#define DAC_DHR12LD_DACC_SHIFT(n) ((((n)-1) << 4) + 4) +#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) + +#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) +#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) + +/* DUAL DAC 8-bit right aligned data holding register */ + +#define DAC_DHR8RD_DACC_SHIFT(n) (((n)-1) << 3) +#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) + +#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) +#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) + +/* DAC channel 1/2 data output register */ + +#define DAC_DOR_MASK (0x0fff) + +/* DAC status register */ + +#define DAC_SR_DMAUDR(n) (1 << ((((n)-1) << 4) + 13)) +#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h similarity index 79% rename from arch/arm/src/stm32/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h index b04b56b3d16ff..9c8587dd4af6b 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H /**************************************************************************** * Included Files @@ -36,14 +36,14 @@ * 2. STM32 DAC IPv2: G4 */ -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # error Only one STM32 DAC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # include "stm32_dac_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32gxxxxx_dac.h" /* Special case for G4 */ # else @@ -53,4 +53,4 @@ # error "STM32 DAC IP version not specified" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h new file mode 100644 index 0000000000000..23ef2b1fd8d91 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) > 1 +# error Only one STM32 DBGMCU IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) +# include "hardware/stm32_dbgmcu_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# include "hardware/stm32_dbgmcu_v1.h" +#else +# error "Unsupported STM32 DBGMCU" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h similarity index 93% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h index 0e5efadeaf7b3..d310e7c1ac7d8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H /**************************************************************************** * Included Files @@ -77,4 +77,4 @@ # define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */ #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h similarity index 94% rename from arch/arm/src/stm32/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h index d1b6946f8bdc3..12628ae6ed6df 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H /**************************************************************************** * Included Files @@ -39,11 +39,11 @@ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 # define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ # define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ # define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */ @@ -72,7 +72,7 @@ # define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ # define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 # define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ # define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ # define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ @@ -87,13 +87,13 @@ # define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ # define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ # define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 /* Debug MCU APB1 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ @@ -130,7 +130,7 @@ /* Debug MCU APB2 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ # define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ # define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ @@ -147,9 +147,9 @@ # define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ #endif -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 /* Debug MCU APB1 freeze 1 register */ @@ -180,7 +180,7 @@ # define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ # define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 */ /**************************************************************************** * Public Types @@ -194,4 +194,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/common/stm32/hardware/stm32_dma.h similarity index 62% rename from arch/arm/src/stm32/stm32_dma.c rename to arch/arm/src/common/stm32/hardware/stm32_dma.h index f5d1f1047a89b..ee43743cd57d4 100644 --- a/arch/arm/src/stm32/stm32_dma.c +++ b/arch/arm/src/common/stm32/hardware/stm32_dma.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma.c + * arch/arm/src/common/stm32/hardware/stm32_dma.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,6 +20,9 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H + /**************************************************************************** * Included Files ****************************************************************************/ @@ -28,26 +31,25 @@ #include "chip.h" -/* This file is only a thin shell that includes the correct DMA - * implementation for the selected STM32 IP core: +/* Include the correct DMA register definitions for + * selected STM32 DMA IP core: * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 * - STM32 DMA IP version 2 - F2, F4, F7, H7 - * - * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it - * adds the concept of "streams" that are used to associate DMA sources with - * DMA channels. */ -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" -# else -# include "stm32_dma_v1.c" -# endif -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# include "stm32_dma_v2.c" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# error Only one STM32 DMA IP version must be selected #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "stm32_dma_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) +# include "stm32_dma_v2.h" +#else +# error "STM32 DMA IP version not specified" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma2d.h b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h new file mode 100644 index 0000000000000..35abefb091516 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h @@ -0,0 +1,237 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/stm32_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_DMA2D_NCLUT 256 /* Number of entries in the CLUT */ + +/* DMA2D Register Offsets ***************************************************/ + +#define STM32_DMA2D_CR_OFFSET 0x0000 /* DMA2D Control Register */ +#define STM32_DMA2D_ISR_OFFSET 0x0004 /* DMA2D Interrupt Status Register */ +#define STM32_DMA2D_IFCR_OFFSET 0x0008 /* DMA2D Interrupt Flag Clear Register */ +#define STM32_DMA2D_FGMAR_OFFSET 0x000c /* DMA2D Foreground Memory Address Register */ +#define STM32_DMA2D_FGOR_OFFSET 0x0010 /* DMA2D Foreground Offset Register */ +#define STM32_DMA2D_BGMAR_OFFSET 0x0014 /* DMA2D Background Memory Address Register */ +#define STM32_DMA2D_BGOR_OFFSET 0x0018 /* DMA2D Background Offset Register */ +#define STM32_DMA2D_FGPFCCR_OFFSET 0x001c /* DMA2D Foreground PFC Control Register */ +#define STM32_DMA2D_FGCOLR_OFFSET 0x0020 /* DMA2D Foreground Color Register */ +#define STM32_DMA2D_BGPFCCR_OFFSET 0x0024 /* DMA2D Background PFC Control Register */ +#define STM32_DMA2D_BGCOLR_OFFSET 0x0028 /* DMA2D Background Color Register */ +#define STM32_DMA2D_FGCMAR_OFFSET 0x002c /* DMA2D Foreground CLUT Memory Address Register */ +#define STM32_DMA2D_BGCMAR_OFFSET 0x0030 /* DMA2D Background CLUT Memory Address Register */ +#define STM32_DMA2D_OPFCCR_OFFSET 0x0034 /* DMA2D Output PFC Control Register */ +#define STM32_DMA2D_OCOLR_OFFSET 0x0038 /* DMA2D Output Color Register */ +#define STM32_DMA2D_OMAR_OFFSET 0x003c /* DMA2D Output Memory Address Register */ +#define STM32_DMA2D_OOR_OFFSET 0x0040 /* DMA2D Output Offset Register */ +#define STM32_DMA2D_NLR_OFFSET 0x0044 /* DMA2D Number Of Line Register */ +#define STM32_DMA2D_LWR_OFFSET 0x0048 /* DMA2D Line Watermark Register */ +#define STM32_DMA2D_AMTCR_OFFSET 0x004c /* DMA2D AHB Master Time Configuration Register */ + +/* DMA2D Register Addresses *************************************************/ + +#define STM32_DMA2D_CR (STM32_DMA2D_BASE + STM32_DMA2D_CR_OFFSET) +#define STM32_DMA2D_ISR (STM32_DMA2D_BASE + STM32_DMA2D_ISR_OFFSET) +#define STM32_DMA2D_IFCR (STM32_DMA2D_BASE + STM32_DMA2D_IFCR_OFFSET) +#define STM32_DMA2D_FGMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGMAR_OFFSET) +#define STM32_DMA2D_FGOR (STM32_DMA2D_BASE + STM32_DMA2D_FGOR_OFFSET) +#define STM32_DMA2D_BGMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGMAR_OFFSET) +#define STM32_DMA2D_BGOR (STM32_DMA2D_BASE + STM32_DMA2D_BGOR_OFFSET) +#define STM32_DMA2D_FGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_FGPFCCR_OFFSET) +#define STM32_DMA2D_FGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_FGCOLR_OFFSET) +#define STM32_DMA2D_BGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_BGPFCCR_OFFSET) +#define STM32_DMA2D_BGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_BGCOLR_OFFSET) +#define STM32_DMA2D_FGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGCMAR_OFFSET) +#define STM32_DMA2D_BGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGCMAR_OFFSET) +#define STM32_DMA2D_OPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_OPFCCR_OFFSET) +#define STM32_DMA2D_OCOLR (STM32_DMA2D_BASE + STM32_DMA2D_OCOLR_OFFSET) +#define STM32_DMA2D_OMAR (STM32_DMA2D_BASE + STM32_DMA2D_OMAR_OFFSET) +#define STM32_DMA2D_OOR (STM32_DMA2D_BASE + STM32_DMA2D_OOR_OFFSET) +#define STM32_DMA2D_NLR (STM32_DMA2D_BASE + STM32_DMA2D_NLR_OFFSET) +#define STM32_DMA2D_LWR (STM32_DMA2D_BASE + STM32_DMA2D_LWR_OFFSET) + +/* DMA2D Register Bit Definitions *******************************************/ + +/* DMA2D Control Register */ + +#define DMA2D_CR_START (1 << 0) /* Start Bit */ +#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */ +#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */ +#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */ +#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */ +#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */ +#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */ +#define DMA2D_CR_CTCIE (1 << 12) /* CLUT Transfer Complete Interrupt Enable Bit */ +#define DMA2D_CR_CEIE (1 << 13) /* Configuration Error Interrupt Enable Bit */ +#define DMA2D_CR_MODE_SHIFT (16) /* Bits 16-17 DMA2D mode Bits */ +#define DMA2D_CR_MODE_MASK (3 << DMA2D_CR_MODE_SHIFT) +#define DMA2D_CR_MODE(n) ((uint32_t)(n) << DMA2D_CR_MODE_SHIFT) + +/* DMA2D Interrupt Status Register */ + +#define DMA2D_ISR_TEIF (1 << 0) /* Transfer error interrupt flag */ +#define DMA2D_ISR_TCIF (1 << 1) /* Transfer Complete Interrupt flag */ +#define DMA2D_ISR_TWIF (1 << 2) /* Transfer Watermark Interrupt flag */ +#define DMA2D_ISR_CAEIF (1 << 3) /* CLUT Access Error Interrupt flag */ +#define DMA2D_ISR_CTCIF (1 << 4) /* CLUT Transfer Complete Interrupt flag */ +#define DMA2D_ISR_CEIF (1 << 5) /* Configuration Error Interrupt flag */ + +/* DMA2D Interrupt Flag Clear Register */ + +#define DMA2D_IFCR_CTEIF (1 << 0) /* Clear Transfer Interrupt Flag */ +#define DMA2D_IFCR_CTCIF (1 << 1) /* Clear Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CTWIF (1 << 2) /* Clear Transfer Watermark Interrupt Flag */ +#define DMA2D_IFCR_CAECIF (1 << 3) /* Clear CLUT Access Error Interrupt Flag */ +#define DMA2D_IFCR_CCTCIF (1 << 4) /* Clear CLUT Transfer Complete Interrupt Flag */ +#define DMA2D_IFCR_CCEIF (1 << 5) /* Clear Configuration Error Interrupt Flag */ + +/* DMA2D Foreground Memory Access Register */ + +/* DMA2D Background Memory Access Register */ + +/* DMA2D Foreground/Background Offset Register */ + +#define DMA2D_XGOR_SHIFT (0) /* Bits 0-13 Line Offset */ +#define DMA2D_XGOR_MASK (0x3fff << DMA2D_XGOR_SHIFT) +#define DMA2D_XGOR(n) ((uint32_t)(n) << DMA2D_XGOR_SHIFT) + +/* DMA2D Foreground/Background PFC Control Register */ + +#define DMA2D_XGPFCCR_CM_SHIFT (0) /* Bits 0-3 Color Mode */ +#define DMA2D_XGPFCCR_CM_MASK (0xf << DMA2D_XGPFCCR_CM_SHIFT) +#define DMA2D_XGPFCCR_CM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CM_SHIFT) +#define DMA2D_XGPFCCR_CCM (1 << 4) /* CLUT Color Mode */ +#define DMA2D_XGPFCCR_START (1 << 5) /* Start */ +#define DMA2D_XGPFCCR_CS_SHIFT (8) /* Bits 8-15 CLUT Size */ +#define DMA2D_XGPFCCR_CS_MASK (0xff << DMA2D_XGPFCCR_CS_SHIFT) +#define DMA2D_XGPFCCR_CS(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CS_SHIFT) +#define DMA2D_XGPFCCR_AM_SHIFT (16) /* Bits 16-17 Alpha Mode */ +#define DMA2D_XGPFCCR_AM_MASK (3 << DMA2D_XGPFCCR_AM_SHIFT) +#define DMA2D_XGPFCCR_AM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_AM_SHIFT) +#define DMA2D_XGPFCCR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ +#define DMA2D_XGPFCCR_ALPHA_MASK (0xff << DMA2D_XGPFCCR_ALPHA_SHIFT) +#define DMA2D_XGPFCCR_ALPHA(n) ((uint32_t)(n) << DMA2D_XGPFCCR_ALPHA_SHIFT) + +/* DMA2D PFC alpha mode */ + +#define STM32_DMA2D_PFCCR_AM_NONE 0 +#define STM32_DMA2D_PFCCR_AM_CONST 1 +#define STM32_DMA2D_PFCCR_AM_PIXEL 2 + +/* DMA2D Foreground/Background Color Register */ + +#define DMA2D_XGCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ +#define DMA2D_XGCOLR_BLUE_MASK (0xff << DMA2D_XGCOLR_BLUE_SHIFT) +#define DMA2D_XGCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_XGCOLR_BLUE_SHIFT) +#define DMA2D_XGCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ +#define DMA2D_XGCOLR_GREEN_MASK (0xff << DMA2D_XGCOLR_GREEN_SHIFT) +#define DMA2D_XGCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_XGCOLR_GREEN_SHIFT) +#define DMA2D_XGCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ +#define DMA2D_XGCOLR_RED_MASK (0xff << DMA2D_XGCOLR_RED_SHIFT) +#define DMA2D_XGCOLR_RED(n) ((uint32_t)(n) << DMA2D_XGCOLR_RED_SHIFT) + +/* DMA2D Foreground CLUT Memory Address Register */ + +/* DMA2D Background CLUT Memory Address Register */ + +/* DMA2D Output PFC Control Register */ + +#define DMA2D_OPFCCR_CM_SHIFT (0) /* Bits 0-2 Color Mode */ +#define DMA2D_OPFCCR_CM_MASK (7 << DMA2D_OPFCCR_CM_SHIFT) +#define DMA2D_OPFCCR_CM(n) ((uint32_t)(n) << DMA2D_OPFCCR_CM_SHIFT) + +/* DMA2D PFC Pixel Format */ + +#define DMA2D_PF_ARGB8888 0 +#define DMA2D_PF_RGB888 1 +#define DMA2D_PF_RGB565 2 +#define DMA2D_PF_ARGB1555 3 +#define DMA2D_PF_ARGB14444 4 +#define DMA2D_PF_L8 5 +#define DMA2D_PF_AL44 6 +#define DMA2D_PF_AL88 7 +#define DMA2D_PF_L4 8 +#define DMA2D_PF_A8 9 +#define DMA2D_PF_A4 10 + +/* DMA2D Output Color Register */ + +#define DMA2D_OCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ +#define DMA2D_OCOLR_BLUE_MASK (0xff << DMA2D_OCOLR_BLUE_SHIFT) +#define DMA2D_OCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_OCOLR_BLUE_SHIFT) +#define DMA2D_OCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ +#define DMA2D_OCOLR_GREEN_MASK (0xff << DMA2D_OCOLR_GREEN_SHIFT) +#define DMA2D_OCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_OCOLR_GREEN_SHIFT) +#define DMA2D_OCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ +#define DMA2D_OCOLR_RED_MASK (0xff << DMA2D_OCOLR_RED_SHIFT) +#define DMA2D_OCOLR_RED(n) ((uint32_t)(n) << DMA2D_OCOLR_RED_SHIFT) +#define DMA2D_OCOLR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ +#define DMA2D_OCOLR_ALPHA_MASK (0xff << DMA2D_OCOLR_ALPHA_SHIFT) +#define DMA2D_OCOLR_ALPHA(n) ((uint32_t)(n) << DMA2D_OCOLR_ALPHA_SHIFT) + +/* DMA2D Output Memory Address Register */ + +/* DMA2D Output Offset Register */ + +#define DMA2D_OOR_LO_SHIFT (0) /* Bits 0-13 Line Offset */ +#define DMA2D_OOR_LO_MASK (0x3fff << DMA2D_OOR_LO_SHIFT) +#define DMA2D_OOR_LO(n) ((uint32_t)(n) << DMA2D_OOR_LO_SHIFT) + +/* DMA2D Number Of Line Register */ + +#define DMA2D_NLR_NL_SHIFT (0) /* Bits 0-15 Number Of Lines */ +#define DMA2D_NLR_NL_MASK (0xffff << DMA2D_NLR_NL_SHIFT) +#define DMA2D_NLR_NL(n) ((uint32_t)(n) << DMA2D_NLR_NL_SHIFT) +#define DMA2D_NLR_PL_SHIFT (16) /* Bits 16-29 Pixel per Lines */ +#define DMA2D_NLR_PL_MASK (0x3fff << DMA2D_NLR_PL_SHIFT) +#define DMA2D_NLR_PL(n) ((uint32_t)(n) << DMA2D_NLR_PL_SHIFT) + +/* DMA2D Line Watermark Register */ + +#define DMA2D_LWR_LW_SHIFT (0) /* Bits 0-15 Line Watermark */ +#define DMA2D_LWR_LW_MASK (0xffff << DMA2D_LWR_LW_SHIFT) +#define DMA2D_LWR_LW(n) ((uint32_t)(n) << DMA2D_LWR_LW_SHIFT) + +/* DMA2D AHB Master Timer Configuration Register */ + +#define DMA2D_AMTCR_EN (1 << 0) /* Enable */ +#define DMA2D_AMTCR_DT_SHIFT (0) /* Bits 8-15 Dead Time */ +#define DMA2D_AMTCR_DT_MASK (0xff << DMA2D_AMTCR_DT_SHIFT) +#define DMA2D_AMTCR_DT(n) ((uint32_t)(n) << DMA2D_AMTCR_DT_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h similarity index 67% rename from arch/arm/src/stm32/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1.h index 18c5f75cfa51f..1ddb8dcc46eef 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,24 +20,21 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H /**************************************************************************** * Included Files ****************************************************************************/ -/* There are 2 main types of I2C IP cores among STM32 chips: - * 1. STM32 I2C IPv1 - F1, F2, F4 and L1 - * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 - */ - -#if defined(CONFIG_STM32_HAVE_IP_I2C_V1) -# include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2) -# include "stm32_i2c_v2.h" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dma_v1_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dma_v1_8ch.h" #else -# error STM32 I2C IP version not specified +# error "Unsupported STM32 DMA v1" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h index cdae49a53ee25..6b3860db90359 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H /**************************************************************************** * Pre-processor Definitions @@ -545,4 +545,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h index 0f73d267096b8..4d4cb3ed4e6a2 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H /**************************************************************************** * Pre-processor Definitions @@ -139,7 +139,7 @@ #define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) #define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) #define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) #endif @@ -151,7 +151,7 @@ #define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) #define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) #define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) #endif @@ -163,7 +163,7 @@ #define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) #define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) #define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) #endif @@ -175,7 +175,7 @@ #define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) #define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) #define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) #endif @@ -188,7 +188,7 @@ #define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) #define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) #define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) # define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) # define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) @@ -200,7 +200,7 @@ #define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) #define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) #define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) # define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) # define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) @@ -212,7 +212,7 @@ #define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) #define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) #define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) # define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) # define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) @@ -224,7 +224,7 @@ #define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) #define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) #define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) # define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) # define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) @@ -286,7 +286,7 @@ #define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ #define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) || defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA_IFCR_ALLCHANNELS (0xffffffff) #else # define DMA_IFCR_ALLCHANNELS (0x0fffffff) @@ -350,14 +350,14 @@ #define STM32_DMA1_CHAN5 (4) #define STM32_DMA1_CHAN6 (5) #define STM32_DMA1_CHAN7 (6) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CHAN8 (7) # define STM32_DMA2_CHAN1 (8) # define STM32_DMA2_CHAN2 (9) # define STM32_DMA2_CHAN3 (10) # define STM32_DMA2_CHAN4 (11) # define STM32_DMA2_CHAN5 (12) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (13) # define STM32_DMA2_CHAN7 (14) # define STM32_DMA2_CHAN8 (15) @@ -368,7 +368,7 @@ # define STM32_DMA2_CHAN3 (9) # define STM32_DMA2_CHAN4 (10) # define STM32_DMA2_CHAN5 (11) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (12) # define STM32_DMA2_CHAN7 (13) # define STM32_DMA2_CHAN8 (14) @@ -770,4 +770,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h new file mode 100644 index 0000000000000..cff6393fb1296 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h @@ -0,0 +1,561 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dma_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is implementation for STM32 DMA IP version 2 - F2, F4, F7, H7 */ + +#define HAVE_IP_DMA_V2 1 +#undef HAVE_IP_DMA_V1 + +/* 2 DMA controllers */ + +#define DMA1 (0) +#define DMA2 (1) + +/* 8 DMA streams */ + +#define DMA_STREAM0 (0) +#define DMA_STREAM1 (1) +#define DMA_STREAM2 (2) +#define DMA_STREAM3 (3) +#define DMA_STREAM4 (4) +#define DMA_STREAM5 (5) +#define DMA_STREAM6 (6) +#define DMA_STREAM7 (7) + +/* 8 DMA channels */ + +#define DMA_CHAN0 (0) +#define DMA_CHAN1 (1) +#define DMA_CHAN2 (2) +#define DMA_CHAN3 (3) +#define DMA_CHAN4 (4) +#define DMA_CHAN5 (5) +#define DMA_CHAN6 (6) +#define DMA_CHAN7 (7) + +/* Register Offsets *********************************************************/ + +#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ +#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ +#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ +#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ + +#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) +#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ +#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ +#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ +#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ +#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ +#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ + +#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ +#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ +#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ +#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ +#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ +#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ +#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ +#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ + +#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ +#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ +#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ +#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ +#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ +#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ +#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ +#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ + +#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ +#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ +#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ +#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ +#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ +#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ +#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ +#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ + +#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ +#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ +#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ +#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ +#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ +#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ +#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ +#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ + +#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ +#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ +#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ +#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ +#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ +#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ +#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ +#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ + +#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ +#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ +#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ +#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ +#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ +#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ +#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ +#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ + +/* Register Addresses *******************************************************/ + +#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) + +#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) +#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) +#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) +#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) + +#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) +#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) +#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) +#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) +#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) +#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) +#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) +#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) + +#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) +#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) +#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) +#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) +#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) +#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) +#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) +#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) + +#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) +#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) +#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) +#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) +#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) +#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) +#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) +#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) + +#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) +#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) +#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) +#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) +#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) +#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) +#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) +#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) + +#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) +#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) +#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) +#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) +#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) +#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) +#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) +#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) + +#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) +#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) +#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) +#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) +#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) +#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) +#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) +#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) +#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define DMA_STREAM_MASK 0x3f +#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ +#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ +#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ +#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ +#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ + +/* DMA interrupt status register and interrupt flag clear register field + * definitions + */ + +#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ +#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) +#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ +#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) +#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ +#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) +#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ +#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) + +#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ +#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) +#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ +#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) +#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ +#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) +#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ +#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) + +/* DMA stream configuration register */ + +#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ +#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ +#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ +#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ +#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ +#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ +#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ +#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) +# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ +# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ +# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ + +#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ +#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ +#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ +#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ +#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) +# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ + +#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ +#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) +# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ +# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ +# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ + +#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ +#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ +#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) +# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ +# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ +# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ +# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ + +#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ +#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ +#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ +#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) +# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ + +#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ +#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) +# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ +# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ +# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ +# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ + +#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */ +#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT) +# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) + +#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) + +/* DMA stream number of data register */ + +#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ +#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) + +/* DMA stream n FIFO control register */ + +#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ +#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) +# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ +# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ +# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ +# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ + +#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ +#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ +#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) +# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ +# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ +# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ +# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ +# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ +# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ + + /* Bit 6: Reserved */ +#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ + /* Bits 8-31: Reserved */ + +/* DMA Stream mapping. + * Each DMA stream has a mapping to several possible sources/sinks of data. + * The requests from peripherals assigned to a stream are simply OR'ed + * together before entering the DMA block. This means that only one request + * on a given stream can be enabled at once. + * + * Alternative stream selections are provided with a numeric suffix like _1, + * _2, etc. The DMA driver, however, will use the pin selection without the + * numeric suffix. Additional definitions are required in the board.h file. + * For example, if SPI3_RX connects via DMA STREAM0, then following should + * be application-specific mapping should be used: + * + * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 + */ + +#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c)) +#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1) +#define STM32_DMA_STREAM(m) (((m) >> 3) & 7) +#define STM32_DMA_CHANNEL(m) ((m) & 7) + +#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) +#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) +#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) + +#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) +#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) +#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) +#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) +#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) +#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) +#define DMAMAP_I2S2_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN2) +#define DMAMAP_I2S3_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_I2S3_EXT_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) +#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) +#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) +#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) +#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) +#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) + +#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) +#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) +#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) +#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5) +# define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5) +#endif +#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5) +#endif +#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) +#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5) +#endif +#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) +#define DMAMAP_DAC1_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) +#define DMAMAP_DAC1_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) +#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) + +#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) +#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) +#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) +#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) +#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) + +#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) +#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) +#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1) +# define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1) +#endif +#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1) + +#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) +#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2) +# define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2) +#endif +#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) +#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) +#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2) + +#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) +#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) +#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) +#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4) +# define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4) +#endif +#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) +#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) +#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) +#define DMAMAP_SDIO_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) +#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) + +#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) +#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5) +# define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5) +#endif +#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) +#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) + +#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) +#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) +#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) +#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) +#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) +#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) +#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) + +#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) +#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) +#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) +#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7) +# define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7) +#endif +#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) +#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h new file mode 100644 index 0000000000000..1531e37123a7d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dmamux_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dmamux_16ch.h" +#else +# error "Unsupported STM32 DMAMUX" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h index 18fd66b1498f2..bc0cc2d68321e 100644 --- a/arch/arm/src/stm32/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H /**************************************************************************** * Included Files @@ -176,4 +176,4 @@ # error "Unsupported STM32 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h index ccab2c6f14ae9..b7c36335c0add 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H /**************************************************************************** * Included Files @@ -159,4 +159,4 @@ # error "Unsupported STM32 M0 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_eth.h b/arch/arm/src/common/stm32/hardware/stm32_eth.h new file mode 100644 index 0000000000000..1d02920541ce2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_eth.h @@ -0,0 +1,877 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +#if STM32_NETHERNET > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* MAC Registers */ + +#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */ +#define STM32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */ +#define STM32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */ +#define STM32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */ +#define STM32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */ +#define STM32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */ +#define STM32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */ +#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ +#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ +#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ +#endif +#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ +#define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */ +#define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */ +#define STM32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */ +#define STM32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */ +#define STM32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */ +#define STM32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */ +#define STM32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */ +#define STM32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */ +#define STM32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */ + +/* MMC Registers */ + +#define STM32_ETH_MMCCR_OFFSET 0x0100 /* Ethernet MMC control register */ +#define STM32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */ +#define STM32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */ +#define STM32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */ +#define STM32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */ +#define STM32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */ +#define STM32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */ +#define STM32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */ +#define STM32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */ +#define STM32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */ +#define STM32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */ + +/* IEEE 1588 time stamp registers */ + +#define STM32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */ +#define STM32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */ +#define STM32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */ +#define STM32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */ +#define STM32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */ +#define STM32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */ +#define STM32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */ +#define STM32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */ +#define STM32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */ +#define STM32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */ +#define STM32_ETH_PTPPPSCR_OFFSET 0x072c /* Ethernet PTP PPS control register */ + +/* DMA Registers */ + +#define STM32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */ +#define STM32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */ +#define STM32_ETH_DMARPDR_OFFSET 0x1008 /* Ethernet DMA receive poll demand register */ +#define STM32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */ +#define STM32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */ +#define STM32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */ +#define STM32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */ +#define STM32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */ +#define STM32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */ +#define STM32_ETH_DMARSWTR_OFFSET 0x1024 /* Ethernet DMA receive status watchdog timer register */ +#define STM32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */ +#define STM32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */ +#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */ +#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */ + +/* Register Base Addresses **************************************************/ + +/* MAC Registers */ + +#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET) +#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET) +#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET) +#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET) +#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET) +#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET) +#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET) +#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) +#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) +#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) +#endif +#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) +#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET) +#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET) +#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET) +#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET) +#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET) +#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET) +#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET) +#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET) +#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET) + +/* MMC Registers */ + +#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCCR_OFFSET) +#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET) +#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET) +#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET) +#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET) +#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET) +#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET) +#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET) +#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET) +#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET) +#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET) + +/* IEEE 1588 time stamp registers */ + +#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET) +#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET) +#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET) +#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET) +#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET) +#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET) +#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET) +#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET) +#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET) +#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET) +#define STM32_ETH_PTPPPSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPPPSCR_OFFSET) + +/* DMA Registers */ + +#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET) +#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET) +#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET) +#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET) +#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET) +#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET) +#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET) +#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET) +#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET) +#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET) +#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET) +#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET) +#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET) +#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* MAC Registers */ + +/* Ethernet MAC configuration register */ + +#define ETH_MACCR_RE (1 << 2) /* Bit 2: Receiver enable */ +#define ETH_MACCR_TE (1 << 3) /* Bit 3: Transmitter enable */ +#define ETH_MACCR_DC (1 << 4) /* Bit 4: Deferral check */ +#define ETH_MACCR_BL_SHIFT (5) /* Bits 5-6: Back-off limit */ +#define ETH_MACCR_BL_MASK (3 << ETH_MACCR_BL_SHIFT) +# define ETH_MACCR_BL_10 (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */ +# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */ +# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */ +# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */ + +#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */ +#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */ +#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */ +#define ETH_MACCR_DM (1 << 11) /* Bit 11: Duplex mode */ +#define ETH_MACCR_LM (1 << 12) /* Bit 12: Loopback mode */ +#define ETH_MACCR_ROD (1 << 13) /* Bit 13: Receive own disable */ +#define ETH_MACCR_FES (1 << 14) /* Bit 14: Fast Ethernet speed */ +#define ETH_MACCR_CSD (1 << 16) /* Bit 16: Carrier sense disable */ +#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */ +#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT) +# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ + +#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ +#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ +#endif + +/* Ethernet MAC frame filter register */ + +#define ETH_MACFFR_PM (1 << 0) /* Bit 0: Promiscuous mode */ +#define ETH_MACFFR_HU (1 << 1) /* Bit 1: Hash unicast */ +#define ETH_MACFFR_HM (1 << 2) /* Bit 2: Hash multicast */ +#define ETH_MACFFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */ +#define ETH_MACFFR_PAM (1 << 4) /* Bit 4: Pass all multicast */ +#define ETH_MACFFR_BFD (1 << 5) /* Bit 5: Broadcast frames disable */ +#define ETH_MACFFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ +#define ETH_MACFFR_PCF_MASK (3 << ETH_MACFFR_PCF_SHIFT) +# define ETH_MACFFR_PCF_NONE (0 << ETH_MACFFR_PCF_SHIFT) /* Prevents all control frames */ +# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */ +# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */ +# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */ + +#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */ +#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */ +#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */ +#define ETH_MACFFR_RA (1 << 31) /* Bit 31: Receive all */ + +/* Ethernet MAC hash table high/low registers (32-bit values) */ + +/* Ethernet MAC MII address register */ + +#define ETH_MACMIIAR_MB (1 << 0) /* Bit 0: MII busy */ +#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ +#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ +#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) +#if 0 /* Per the reference manual */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ +# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +#else /* Per the driver example */ +# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ +# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ +# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ +# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ +# define ETH_MACMIIAR_CR_150_180 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-180 MHz HCLK/102 */ +#endif +#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ +#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) +#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ +#define ETH_MACMIIAR_PA_MASK (31 << ETH_MACMIIAR_PA_SHIFT) + +/* Ethernet MAC MII data register */ + +#define ETH_MACMIIDR_MASK (0xffff) + +/* Ethernet MAC flow control register */ + +#define ETH_MACFCR_FCB_BPA (1 << 0) /* Bit 0: Flow control busy/back pressure activate */ +#define ETH_MACFCR_TFCE (1 << 1) /* Bit 1: Transmit flow control enable */ +#define ETH_MACFCR_RFCE (1 << 2) /* Bit 2: Receive flow control enable */ +#define ETH_MACFCR_UPFD (1 << 3) /* Bit 3: Unicast pause frame detect */ +#define ETH_MACFCR_PLT_SHIFT (4) /* Bits 4-5: Pause low threshold */ +#define ETH_MACFCR_PLT_MASK (3 << ETH_MACFCR_PLT_SHIFT) +# define ETH_MACFCR_PLT_M4 (0 << ETH_MACFCR_PLT_SHIFT) /* 00 Pause - 4 slot times */ +# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */ +# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */ +# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */ + +#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */ +#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */ +#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT) + +/* Ethernet MAC VLAN tag register */ + +#define ETH_MACVLANTR_VLANTI_SHIFT (0) /* Bits 0-15: VLAN tag identifier (for receive frames) */ +#define ETH_MACVLANTR_VLANTI_MASK (0xffff << ETH_MACVLANTR_VLANTI_SHIFT) +#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */ + +/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to + * remote remote wake-up filters. + */ + +/* Ethernet MAC PMT control and status register */ + +#define ETH_MACPMTCSR_PD (1 << 0) /* Bit 0: Power down */ +#define ETH_MACPMTCSR_MPE (1 << 1) /* Bit 1: Magic Packet enable */ +#define ETH_MACPMTCSR_WFE (1 << 2) /* Bit 2: Wakeup frame enable */ +#define ETH_MACPMTCSR_MPR (1 << 5) /* Bit 5: Magic packet received */ +#define ETH_MACPMTCSR_WFR (1 << 6) /* Bit 6: Wakeup frame received */ +#define ETH_MACPMTCSR_GU (1 << 9) /* Bit 9: Global unicast */ + +/* Ethernet MAC debug register */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + +#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ +#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ +#define ETH_MACDBGR_MSFRWCS_MASK (3 << ETH_MACDBGR_MSFRWCS_SHIFT) + +#define ETH_MACDBGR_RFWRA (1 << 4) /* Bit 4: Rx FIFO write controller active */ +#define ETH_MACDBGR_RFRCS_SHIFT (5) /* Bits 5-6: Rx FIFO read controller status */ +#define ETH_MACDBGR_RFRCS_MASK (3 << ETH_MACDBGR_RFRCS_SHIFT) +# define ETH_MACDBGR_RFRCS_IDLE (0 << ETH_MACDBGR_RFRCS_SHIFT) /* 00: IDLE state */ +# define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */ +# define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */ +# define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */ + +#define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */ +#define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT) +# define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */ +# define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */ +# define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */ +# define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */ + +#define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */ +#define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */ +#define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT) +# define ETH_MACDBGR_MTFCS_IDLE (0 << ETH_MACDBGR_MTFCS_SHIFT) /* 00: Idle */ +# define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */ +# define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */ +# define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */ + +#define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */ +#define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */ +#define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT) +# define ETH_MACDBGR_TFRS_IDLE (0 << ETH_MACDBGR_TFRS_SHIFT) /* 00: Idle state */ +# define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */ +# define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */ +# define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */ + +#define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */ +#define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ +#define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ + +#endif + +/* Ethernet MAC interrupt status register */ + +#define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */ +#define ETH_MACSR_MMCS (1 << 4) /* Bit 4: MMC status */ +#define ETH_MACSR_MMCRS (1 << 5) /* Bit 5: MMC receive status */ +#define ETH_MACSR_MMCTS (1 << 6) /* Bit 6: MMC transmit status */ +#define ETH_MACSR_TSTS (1 << 9) /* Bit 9: Time stamp trigger status */ + +/* Ethernet MAC interrupt mask register */ + +#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */ +#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */ +#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM) + +/* Ethernet MAC address 0 high register */ + +#define ETH_MACA0HR_MACA0H_SHIFT (0) /* Bits 0-15: MAC address0 high [47:32] */ +#define ETH_MACA0HR_MACA0H_MASK (0xffff << ETH_MACA0HR_MACA0H_SHIFT) +#define ETH_MACA0HR_MO (1 << 31) /* Bit 31:Always */ + +/* Ethernet MAC address 0 low register (MAC address0 low [31:0]) */ + +/* Ethernet MAC address 1 high register */ + +#define ETH_MACA1HR_MACA1H_SHIFT (0) /* Bits 0-15: MAC address1 high [47:32] */ +#define ETH_MACA1HR_MACA1H_MASK (0xffff << ETH_MACA1HR_MACA1H_SHIFT) +#define ETH_MACA1HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA1HR_MBC_MASK (0x3f << ETH_MACA1HR_MBC_SHIFT) +# define ETH_MACA1HR_MBC_40_47 (0x20 << ETH_MACA1HR_MBC_SHIFT) /* Bit 29: ETH_MACA1HR [8-15] */ +# define ETH_MACA1HR_MBC_32_39 (0x10 << ETH_MACA1HR_MBC_SHIFT) /* Bit 28: ETH_MACA1HR [0-7] */ +# define ETH_MACA1HR_MBC_24_31 (0x08 << ETH_MACA1HR_MBC_SHIFT) /* Bit 27: ETH_MACA1LR [24-31] */ +# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */ +# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */ +# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */ + +#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address1 low register (MAC address1 low [31:0]) */ + +/* Ethernet MAC address 2 high register */ + +#define ETH_MACA2HR_MACA2H_SHIFT (0) /* Bits 0-15: MAC address2 high [47:32] */ +#define ETH_MACA2HR_MACA2H_MASK (0xffff << ETH_MACA2HR_MACA2H_SHIFT) +#define ETH_MACA2HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA2HR_MBC_MASK (0x3f << ETH_MACA2HR_MBC_SHIFT) +# define ETH_MACA2HR_MBC_40_47 (0x20 << ETH_MACA2HR_MBC_SHIFT) /* Bit 29: ETH_MACA2HR [8-15] */ +# define ETH_MACA2HR_MBC_32_39 (0x10 << ETH_MACA2HR_MBC_SHIFT) /* Bit 28: ETH_MACA2HR [0-7] */ +# define ETH_MACA2HR_MBC_24_31 (0x08 << ETH_MACA2HR_MBC_SHIFT) /* Bit 27: ETH_MACA2LR [24-31] */ +# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */ +# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */ +# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */ + +#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address 2 low register (MAC address2 low [31:0]) */ + +/* Ethernet MAC address 3 high register */ + +#define ETH_MACA3HR_MACA3H_SHIFT (0) /* Bits 0-15: MAC address3 high [47:32] */ +#define ETH_MACA3HR_MACA3H_MASK (0xffff << ETH_MACA3HR_MACA3H_SHIFT) +#define ETH_MACA3HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ +#define ETH_MACA3HR_MBC_MASK (0x3f << ETH_MACA3HR_MBC_SHIFT) +# define ETH_MACA3HR_MBC_40_47 (0x20 << ETH_MACA3HR_MBC_SHIFT) /* Bit 29: ETH_MACA3HR [8-15] */ +# define ETH_MACA3HR_MBC_32_39 (0x10 << ETH_MACA3HR_MBC_SHIFT) /* Bit 28: ETH_MACA3HR [0-7] */ +# define ETH_MACA3HR_MBC_24_31 (0x08 << ETH_MACA3HR_MBC_SHIFT) /* Bit 27: ETH_MACA3LR [24-31] */ +# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */ +# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */ +# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */ + +#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */ +#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */ + +/* Ethernet MAC address 3 low register (MAC address3 low [31:0]) */ + +/* MMC Registers */ + +/* Ethernet MMC control register */ + +#define ETH_MMCCR_CR (1 << 0) /* Bit 0: Counter reset */ +#define ETH_MMCCR_CSR (1 << 1) /* Bit 1: Counter stop rollover */ +#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ +#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ +#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ +#endif + +/* Ethernet MMC receive interrupt and interrupt mask registers */ + +#define ETH_MMCRI_RFCE (1 << 5) /* Bit 5: Received frame CRC error */ +#define ETH_MMCRI_RFAE (1 << 6) /* Bit 6: Received frames alignment error */ +#define ETH_MMCRI_RGUF (1 << 17) /* Bit 17: Received good unicast frames */ + +/* Ethernet MMC transmit interrupt and interrupt mask register */ + +#define ETH_MMCTI_TGFSC (1 << 14) /* Bit 14: Transmitted good frames single collision */ +#define ETH_MMCTI_TGFMSC (1 << 15) /* Bit 15: Transmitted good frames more single collision */ +#define ETH_MMCTI_TGF (1 << 21) /* Bit 21: Transmitted good frames */ + +/* 32-bit counters: + * + * Ethernet MMC transmitted good frames counter register (single collision) + * Ethernet MMC transmitted good frames counter register (multiple-collision) + * Ethernet MMC transmitted good frames counter register + * Ethernet MMC received frames with CRC error counter register + * Ethernet MMC received frames with alignment error counter + * MMC received good unicast frames counter register + */ + +/* IEEE 1588 time stamp registers */ + +/* Ethernet PTP time stamp control register */ + +#define ETH_PTPTSCR_TSE (1 << 0) /* Bit 0: Time stamp enable */ +#define ETH_PTPTSCR_TSFCU (1 << 1) /* Bit 1: Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSSTI (1 << 2) /* Bit 2: Time stamp system time initialize */ +#define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */ +#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ +#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSPTPOEFE (1 << 11) /* Bit 11: Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE (1 << 12) /* Bit 12: Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSIPV4FE (1 << 13) /* Bit 13: Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSEME (1 << 14) /* Bit 14: Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSMRME (1 << 15) /* Bit 15: Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSCNT_SHIFT (16) /* Bits 16-17: Time stamp clock node type */ +#define ETH_PTPTSCR_TSCNT_MASK (3 << ETH_PTPTSCR_TSCNT_SHIFT) +# define ETH_PTPTSCR_TSCNT_ORDINARY (0 << ETH_PTPTSCR_TSCNT_SHIFT) /* 00: Ordinary clock */ +# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */ +# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ +# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ + +#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ +#endif + +/* Ethernet PTP subsecond increment register */ + +#define ETH_PTPSSIR_MASK (0xff) + +/* Ethernet PTP time stamp high register (32-bit) */ + +/* Ethernet PTP time stamp low register */ + +#define ETH_PTPTSLR_STPNS (1 << 31) /* Bit 31: System time positive or negative sign */ +#define ETH_PTPTSLR_MASK (0x7fffffff) /* Bits 0-30: System time subseconds */ + +/* Ethernet PTP time stamp high update register (32-bit) */ + +/* Ethernet PTP time stamp low update register */ + +#define ETH_PTPTSLU_TSUPNS (1 << 31) /* Bit 31: System time positive or negative sign */ +#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */ + +/* Ethernet PTP time stamp addend register (32-bit) */ + +/* Ethernet PTP target time high register (32-bit) */ + +/* Ethernet PTP target time low register (32-bit) */ + +/* Ethernet PTP time stamp status register */ + +#define ETH_PTPTSSR_TSSO (1 << 0) /* Bit 0: Time stamp second overflow */ +#define ETH_PTPTSSR_TSTTR (1 << 1) /* Bit 1: Time stamp target time reached */ + +/* Ethernet PTP PPS control register */ + +#define ETH_PTPPPSCR_PPSFREQ_SHIFT (0) /* Bits 0-3: PPS frequency selection */ +#define ETH_PTPPPSCR_PPSFREQ_MASK (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) +# define ETH_PTPPPSCR_PPSFREQ_1HZ (0 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1 Hz with pulse width of 125/100 ms for binary/digital rollover */ +# define ETH_PTPPPSCR_PPSFREQ_2HZ (1 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_4HZ (2 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_8HZ (3 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_16HZ (4 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_32HZ (5 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_64HZ (6 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 64 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_128HZ (7 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 128 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_256HZ (8 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 256 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_512HZ (9 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 512 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_1KHZ (10 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1024 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_2KHZ (11 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2048 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_4KHZ (12 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4096 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_8KHZ (13 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8192 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_16KHZ (14 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16384 Hz with 50% duty cycle */ +# define ETH_PTPPPSCR_PPSFREQ_32KHZ (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32768 Hz with 50% duty cycle */ + +/* DMA Registers */ + +/* Ethernet DMA bus mode register */ + +#define ETH_DMABMR_SR (1 << 0) /* Bit 0: Software reset */ +#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */ +#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */ +#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT) +# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT) +#define ETH_DMABMR_EDFE (1 << 7) /* Bit 7: Enhanced descriptor format enable */ +#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */ + +# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ +#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT) + +#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */ +#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT) +# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_RTPR_SHIFT) /* 00: 1:1 */ +# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_RTPR_SHIFT) /* 01: 2:1 */ +# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_RTPR_SHIFT) /* 10: 3:1 */ +# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_RTPR_SHIFT) /* 11: 4:1 */ + +#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */ +#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */ +#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT) +# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ + +#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ +#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ +#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ +#endif + +/* Ethernet DMA transmit poll demand register (32-bit) */ + +/* Ethernet DMA receive poll demand register (32-bit) */ + +/* Ethernet DMA receive descriptor list address register (32-bit address) */ + +/* Ethernet DMA transmit descriptor list address register (32-bit address) */ + +/* Interrupt bit definitions common between the DMA status register (DMASR) + * and the DMA interrupt enable register (DMAIER). + */ + +#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ +#define ETH_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */ +#define ETH_DMAINT_TBUI (1 << 2) /* Bit 2: Transmit buffer unavailable interrupt */ +#define ETH_DMAINT_TJTI (1 << 3) /* Bit 3: Transmit jabber timeout interrupt */ +#define ETH_DMAINT_ROI (1 << 4) /* Bit 4: Overflow interrupt */ +#define ETH_DMAINT_TUI (1 << 5) /* Bit 5: Underflow interrupt */ +#define ETH_DMAINT_RI (1 << 6) /* Bit 6: Receive interrupt */ +#define ETH_DMAINT_RBUI (1 << 7) /* Bit 7: Receive buffer unavailable interrupt */ +#define ETH_DMAINT_RPSI (1 << 8) /* Bit 8: Receive process stopped interrupt */ +#define ETH_DMAINT_RWTI (1 << 9) /* Bit 9: Receive watchdog timeout interrupt */ +#define ETH_DMAINT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */ +#define ETH_DMAINT_FBEI (1 << 13) /* Bit 13: Fatal bus error interrupt */ +#define ETH_DMAINT_ERI (1 << 14) /* Bit 14: Early receive interrupt */ +#define ETH_DMAINT_AIS (1 << 15) /* Bit 15: Abnormal interrupt summary */ +#define ETH_DMAINT_NIS (1 << 16) /* Bit 16: Normal interrupt summary */ + +/* Ethernet DMA status register (in addition to the interrupt bits above */ + +#define ETH_DMASR_RPS_SHIFT (17) /* Bits 17-19: Receive process state */ +#define ETH_DMASR_RPS_MASK (7 << ETH_DMASR_RPS_SHIFT) +# define ETH_DMASR_RPS_STOPPED (0 << ETH_DMASR_RPS_SHIFT) /* 000: Stopped: Reset or Stop Receive Command issued */ +# define ETH_DMASR_RPS_RXDESC (1 << ETH_DMASR_RPS_SHIFT) /* 001: Running: Fetching receive transfer descriptor */ +# define ETH_DMASR_RPS_WAITING (3 << ETH_DMASR_RPS_SHIFT) /* 011: Running: Waiting for receive packet */ +# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */ +# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */ +# define ETH_DMASR_RPS_TRANSFER (6 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */ + +#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */ +#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT) +# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */ +# define ETH_DMASR_TPS_TXDESC (1 << ETH_DMASR_TPS_SHIFT) /* 001: Running; Fetching transmit transfer descriptor */ +# define ETH_DMASR_TPS_WAITING (2 << ETH_DMASR_TPS_SHIFT) /* 010: Running; Waiting for status */ +# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */ +# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */ +# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */ + +#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */ +#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT) +#define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */ +#define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */ +#define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */ + +#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */ +#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */ +#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */ + +/* Ethernet DMA operation mode register */ + +#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */ +#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */ +#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */ +#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT) +# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT) +#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */ +#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */ +#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */ +#define ETH_DMAOMR_TTC_SHIFT (14) /* Bits 14-16: Transmit threshold control */ +#define ETH_DMAOMR_TTC_MASK (7 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_64 (0 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_128 (1 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_192 (2 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_256 (3 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_40 (4 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_32 (5 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_24 (6 << ETH_DMAOMR_TTC_SHIFT) +# define ETH_DMAOMR_TTC_16 (7 << ETH_DMAOMR_TTC_SHIFT) +#define ETH_DMAOMR_FTF (1 << 20) /* Bit 20: Flush transmit FIFO */ +#define ETH_DMAOMR_TSF (1 << 21) /* Bit 21: Transmit store and forward */ +#define ETH_DMAOMR_DFRF (1 << 24) /* Bit 24: Disable flushing of received frames */ +#define ETH_DMAOMR_RSF (1 << 25) /* Bit 25: Receive store and forward */ +#define ETH_DMAOMR_DTCEFD (1 << 26) /* Bit 26: Dropping of TCP/IP checksum error frames disable */ + +/* Ethernet DMA missed frame and buffer overflow counter register */ + +#define ETH_DMAMFBOC_MFC_SHIFT (0) /* Bits 0-15: Missed frames by the controller */ +#define ETH_DMAMFBOC_MFC_MASK (0xffff << ETH_DMAMFBOC_MFC_SHIFT) +#define ETH_DMAMFBOC_OMFC (1 << 16) /* Bit 16: Overflow bit for missed frame counter */ +#define ETH_DMAMFBOC_MFA_SHIFT (17) /* Bits 17-27: Missed frames by the application */ +#define ETH_DMAMFBOC_MFA_MASK (0x7ff << ETH_DMAMFBOC_MFA_SHIFT) +#define ETH_DMAMFBOC_OFOC (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */ + +/* Ethernet DMA receive status watchdog timer register */ + +#define ETH_DMARSWTR_MASK (0xff) + +/* Ethernet DMA current host transmit descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host receive descriptor register + * (32-bit address) + */ + +/* Ethernet DMA current host transmit buffer address register + * (32-bit address) + */ + +/* Ethernet DMA current host receive buffer address register + * (32-bit address) + */ + +/* DMA Descriptors **********************************************************/ + +/* TDES0: Transmit descriptor Word0 */ + +#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ +#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */ +#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */ +#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */ +#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT) +#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */ +#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */ +#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */ +#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */ +#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */ +#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */ +#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */ +#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */ +#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */ +#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */ +#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ +#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ +#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ +#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT) +# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */ +# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ +# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ +# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ + +#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ +#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ +#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ +#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */ +#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */ +#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */ +#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* TDES1: Transmit descriptor Word1 */ + +#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ +#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) +#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ +#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) + +/* TDES2: Transmit descriptor Word2 (32-bit address) */ + +/* TDES3: Transmit descriptor Word3 (32-bit address) */ + +/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ + +/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ + +/* RDES0: Receive descriptor Word0 */ + +#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ +#endif +#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ +#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ +#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ +#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */ +#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */ +#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */ +#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */ +#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */ +#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */ +#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */ +#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */ +#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */ +#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */ +#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */ +#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */ +#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */ +#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */ +#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT) +#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */ +#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */ + +/* RDES1: Receive descriptor Word1 */ + +#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ +#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) + /* Bit 13: Reserved */ +#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ +#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ +#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ +#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT) +#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ + +/* RDES2: Receive descriptor Word2 (32-bit address) */ + +/* RDES3: Receive descriptor Word3 (32-bit address) */ + +/* RDES4: Receive descriptor Word4 */ + +#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ +#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) +# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ +# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ +# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ + +#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ +#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ +#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ +#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */ +#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */ +#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ +#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT) +# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */ +# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */ +# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */ +# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */ +# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */ +# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Req (in peer-to-peer + * transparent clock) or Announce (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer + * transparent clock) or Management (in + * ordinary or boundary clock) */ +# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in + * peer-to-peer transparent clock) or + * Signaling (for ordinary or boundary + * clock) */ + +#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ +#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ + +/* RDES5: Receive descriptor Word5 - Reserved */ + +/* RDES6: Receive descriptor Word6 (32-bit time stamp) */ + +/* RDES7: Receive descriptor Word7 (32-bit time stamp) */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Ethernet TX DMA Descriptor */ + +struct eth_txdesc_s +{ + /* Normal DMA descriptor words */ + + volatile uint32_t tdes0; /* Status */ + volatile uint32_t tdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t tdes2; /* Buffer1 address pointer */ + volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t tdes4; /* Reserved */ + volatile uint32_t tdes5; /* Reserved */ + volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/* Ethernet RX DMA Descriptor */ + +struct eth_rxdesc_s +{ + volatile uint32_t rdes0; /* Status */ + volatile uint32_t rdes1; /* Control and buffer1/2 lengths */ + volatile uint32_t rdes2; /* Buffer1 address pointer */ + volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */ + + /* Enhanced DMA descriptor words with time stamp and PTP support */ + +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC + volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ + volatile uint32_t rdes5; /* Reserved */ + volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ + volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */ +#endif +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ASSEMBLY__ */ +#endif /* STM32_NETHERNET > 0 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/common/stm32/hardware/stm32_exti.h similarity index 57% rename from arch/arm/src/stm32/stm32_flash.c rename to arch/arm/src/common/stm32/hardware/stm32_exti.h index 0afd013d87243..8b22f1abf7045 100644 --- a/arch/arm/src/stm32/stm32_flash.c +++ b/arch/arm/src/common/stm32/hardware/stm32_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_flash.c + * arch/arm/src/common/stm32/hardware/stm32_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,30 +20,30 @@ * ****************************************************************************/ -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - */ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H /**************************************************************************** * Included Files ****************************************************************************/ -#include +/* The EXTI IP version (V1/V2) is independent of the CPU core. The M0 and + * M3/M4 ports currently keep separate register headers, so the file is + * chosen by the standard NuttX core symbol (CONFIG_ARCH_CORTEXM0) while the + * version is core-agnostic. + */ -/* Include the correct FLASH implementation for the selection STM32 part */ +#if (defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) > 1 +# error Only one STM32 EXTI IP version must be selected +#endif -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xx_flash.c" -#elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# include "stm32f10xxf30xx_flash.c" -#elif defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) -# include "stm32f20xxf40xx_flash.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxx_flash.c" +#if !(defined(CONFIG_STM32_HAVE_IP_EXTI_V1) || defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) +# error "Unsupported STM32 EXTI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_exti_v1v2_m0.h" #else -# warning "No FLASH support for the selected part" +# include "hardware/stm32_exti_v1v2.h" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h index 80d2d9c4bce55..66af0a47a616f 100644 --- a/arch/arm/src/stm32/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H /**************************************************************************** * Included Files @@ -55,7 +55,7 @@ # define STM32_EXTI1_MASK 0xffffffff # define STM32_NEXTI2 4 # define STM32_EXTI2_MASK 0x0000000f -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define STM32_NEXTI 23 # define STM32_EXTI_MASK 0x007fffff #endif @@ -132,7 +132,7 @@ # define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ # define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ # define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ # define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ # define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ @@ -228,4 +228,4 @@ # define STM32_EXTI_PR STM32_EXTI1_PR #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h index 82e7cff363d4b..3f147d2a17f60 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unrecognized STM32 M0 EXTI" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h new file mode 100644 index 0000000000000..6ce5e34f2aae7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)) > 1 +# error Only one STM32 FDCAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) +# include "hardware/stm32_fdcan_mcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# include "hardware/stm32_fdcan_mcan.h" +#else +# error "Unsupported STM32 FDCAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h index 11885bc6b57a3..be1f77a5d3a78 100644 --- a/arch/arm/src/stm32/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H /**************************************************************************** * Included Files @@ -585,4 +585,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h index fa93956fc691c..c8a0eba38e3f5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H /**************************************************************************** * Included Files @@ -579,4 +579,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash.h new file mode 100644 index 0000000000000..acfe2f89b921a --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)) > 1 +# error Only one STM32 flash IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) +# include "hardware/stm32_flash_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) +# include "hardware/stm32_flash_v1v2.h" +#else +# error "Unsupported STM32 flash" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h similarity index 86% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_m0.h index 57193fbe896e6..17f642f71e6b6 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 FLASH" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h index 2da31815084ed..3a3a5c796b12f 100644 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -45,7 +45,7 @@ #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # if defined(CONFIG_STM32_STM32L15XX) -# if defined(CONFIG_STM32_HIGHDENSITY) +# if defined(CONFIG_STM32L1_HIGHDENSITY) /* Different STM32L1xxx MCU version are now called by different 'categories' * instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. @@ -102,7 +102,7 @@ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ @@ -125,7 +125,7 @@ /* Define the Valid Configuration the F2 and F4 */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NPAGES 5 @@ -308,7 +308,7 @@ # define STM32_FLASH_AR_OFFSET 0x0014 # define STM32_FLASH_OBR_OFFSET 0x001c # define STM32_FLASH_WRPR_OFFSET 0x0020 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR_OFFSET 0x0014 # endif #endif @@ -372,7 +372,7 @@ # define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) # define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) # define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) # endif # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -447,7 +447,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ # define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ # define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ @@ -464,7 +464,7 @@ # define FLASH_SR_PGERR (1 << 2) /* Programming Error */ # define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ # define FLASH_SR_EOP (1 << 5) /* End of Operation */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ # define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ # define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ @@ -533,7 +533,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ # endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ # define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ @@ -610,7 +610,7 @@ /* Flash Option Control Register (OPTCR) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ # define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ # define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ @@ -786,8 +786,8 @@ int stm32_flash_lock(void); int stm32_flash_unlock(void); -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) int stm32_flash_writeprotect(size_t page, bool enabled); #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fmc.h b/arch/arm/src/common/stm32/hardware/stm32_fmc.h new file mode 100644 index 0000000000000..4b72c82856ed3 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fmc.h @@ -0,0 +1,392 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FMC_BCR_OFFSET(n) (8 * ((n) - 1)) +#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ + +#define STM32_FMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) +#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ + +#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) +#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ + +#define STM32_FMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) +#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) +#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) +#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ +#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ +#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ + +#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) +#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ +#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ +#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ + +#define STM32_FMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ + +#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) +#define STM32_FMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ +#define STM32_FMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ + +#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */ +#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 2 */ + +#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 1 */ +#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 2 */ + +#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ +#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ +#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ + +/* Register Addresses *******************************************************/ + +#define STM32_FMC_BCR(n) (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n)) +#define STM32_FMC_BCR1 (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET) +#define STM32_FMC_BCR2 (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET) +#define STM32_FMC_BCR3 (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET) +#define STM32_FMC_BCR4 (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET) + +#define STM32_FMC_BTR(n) (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n)) +#define STM32_FMC_BTR1 (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET) +#define STM32_FMC_BTR2 (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET) +#define STM32_FMC_BTR3 (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET) +#define STM32_FMC_BTR4 (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET) + +#define STM32_FMC_BWTR(n) (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n)) +#define STM32_FMC_BWTR1 (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET) +#define STM32_FMC_BWTR2 (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET) +#define STM32_FMC_BWTR3 (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET) +#define STM32_FMC_BWTR4 (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET) + +#define STM32_FMC_PCR(n) (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n)) +#define STM32_FMC_PCR2 (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET) +#define STM32_FMC_PCR3 (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET) +#define STM32_FMC_PCR4 (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET) + +#define STM32_FMC_SR(n) (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n)) +#define STM32_FMC_SR2 (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET) +#define STM32_FMC_SR3 (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET) +#define STM32_FMC_SR4 (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET) + +#define STM32_FMC_PMEM(n) (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n)) +#define STM32_FMC_PMEM2 (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET) +#define STM32_FMC_PMEM3 (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET) +#define STM32_FMC_PMEM4 (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET) + +#define STM32_FMC_PATT(n) (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n)) +#define STM32_FMC_PATT2 (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET) +#define STM32_FMC_PATT3 (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET) +#define STM32_FMC_PATT4 (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET) + +#define STM32_FMC_PIO4 (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET) + +#define STM32_FMC_ECCR(n) (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n)) +#define STM32_FMC_ECCR2 (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET) +#define STM32_FMC_ECCR3 (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET) + +#define STM32_FMC_SDCR1 (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET) +#define STM32_FMC_SDCR2 (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET) + +#define STM32_FMC_SDTR1 (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET) +#define STM32_FMC_SDTR2 (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET) + +#define STM32_FMC_SDCMR (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET) +#define STM32_FMC_SDRTR (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET) +#define STM32_FMC_SDSR (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) +# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) +#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) +# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) +#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ +#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ + +#define FMC_BCR_RSTVALUE 0x000003d2 + +#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) +# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) +# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) +# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ +#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) +# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) +# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) +# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) +# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) + +#define FMC_BTR_RSTVALUE 0xffffffff + +#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) +# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) +# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) +# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) +# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ +#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) +# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) +# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) + +#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ +#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ +#define FMC_PCR_PTYP (1 << 3) /* Memory type */ +#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ +#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) +# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) +#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ +#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ +#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) +# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ +#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) +# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ +#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) +# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ +# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ +# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ +# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ +# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ + +#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ +#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ +#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ +#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ +#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ +#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ +#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ + +#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ +#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT) +# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ +#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT) +# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ +#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT) +# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ +#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT) +# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ +#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT) +# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ +#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT) +# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ +#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT) +# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ +#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT) +# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ +#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT) +# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ +#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT) +# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ +#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT) +# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ +#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT) +# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FMC_SDCR_RESERVED (0x1ffff << 15) /* reserved bits */ + +#define FMC_SDCR_RPIPE_0 (0 << 13) /* read pipe */ +#define FMC_SDCR_RPIPE_1 (1 << 13) +#define FMC_SDCR_RPIPE_2 (2 << 13) +#define FMC_SDCR_READBURST (1 << 12) /* read burst */ +#define FMC_SDCR_SDCLK_DISABLE (0 << 10) /* sdram clock */ +#define FMC_SDCR_SDCLK_2X (2 << 10) +#define FMC_SDCR_SDCLK_3X (3 << 10) +#define FMC_SDCR_WP (1 << 9) /* write protect */ +#define FMC_SDCR_CAS_LATENCY_1 (1 << 7) /* cas latency */ +#define FMC_SDCR_CAS_LATENCY_2 (2 << 7) +#define FMC_SDCR_CAS_LATENCY_3 (3 << 7) +#define FMC_SDCR_NBANKS_2 (0 << 6) /* number of internal banks */ +#define FMC_SDCR_NBANKS_4 (1 << 6) +#define FMC_SDCR_WIDTH_8 (0 << 4) /* memory width */ +#define FMC_SDCR_WIDTH_16 (1 << 4) +#define FMC_SDCR_WIDTH_32 (2 << 4) +#define FMC_SDCR_ROWS_11 (0 << 2) /* number of rows */ +#define FMC_SDCR_ROWS_12 (1 << 2) +#define FMC_SDCR_ROWS_13 (2 << 2) +#define FMC_SDCR_COLS_8 (0 << 0) /* number of columns */ +#define FMC_SDCR_COLS_9 (1 << 0) +#define FMC_SDCR_COLS_10 (2 << 0) +#define FMC_SDCR_COLS_11 (3 << 0) + +#define FMC_SDTR_RESERVED (15 << 28) /* reserved bits */ +#define FMC_SDTR_TMRD(n) (((n & 15) - 1) << 0) +#define FMC_SDTR_TXSR(n) (((n & 15) - 1) << 4) +#define FMC_SDTR_TRAS(n) (((n & 15) - 1) << 8) +#define FMC_SDTR_TRC(n) (((n & 15) - 1) << 12) +#define FMC_SDTR_TWR(n) (((n & 15) - 1) << 16) +#define FMC_SDTR_TRP(n) (((n & 15) - 1) << 20) +#define FMC_SDTR_TRCD(n) (((n & 15) - 1) << 24) + +/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet. + * They should be standard, but it's probably a good idea to review + * the datasheet for your SDRAM device. + */ +#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */ +#define FMC_SDCMR_MDR_BURST_LENGTH_1 ((0 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_2 ((1 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_4 ((2 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_8 ((3 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_LENGTH_FULL ((7 << 0) << 9) +#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL ((0 << 3) << 9) +#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE ((1 << 3) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_1 ((1 << 4) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_2 ((2 << 4) << 9) +#define FMC_SDCMR_MDR_CAS_LATENCY_3 ((3 << 4) << 9) +#define FMC_SDCMR_MDR_MODE_NORMAL ((0 << 7) << 9) +#define FMC_SDCMR_MDR_WBL_BURST ((0 << 9) << 9) +#define FMC_SDCMR_MDR_WBL_SINGLE ((1 << 9) << 9) +#define FMC_SDCMR_NRFS(n) (((n & 15) - 1) << 5) +#define FMC_SDCMR_BANK_1 (1 << 4) +#define FMC_SDCMR_BANK_2 (1 << 3) +#define FMC_SDCMR_CMD_NORMAL (0 << 0) +#define FMC_SDCMR_CMD_CLK_ENABLE (1 << 0) +#define FMC_SDCMR_CMD_PALL (2 << 0) +#define FMC_SDCMR_CMD_AUTO_REFRESH (3 << 0) +#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0) +#define FMC_SDCMR_CMD_SELF_REFRESH (5 << 0) +#define FMC_SDCMR_CMD_POWER_DOWN (6 << 0) + +#define FMC_SDSR_RE (1 << 0) +#define FMC_SDSR_BUSY (1 << 5) +#define FMC_SDSR_MODES1_NORMAL (0 << 1) +#define FMC_SDSR_MODES1_SELF_REFRESH (1 << 1) +#define FMC_SDSR_MODES1_POWER_DOWN (2 << 1) +#define FMC_SDSR_MODES2_NORMAL (0 << 3) +#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) +#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fsmc.h b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h new file mode 100644 index 0000000000000..703dbb1ab7f94 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h @@ -0,0 +1,301 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_FSMC_BCR_OFFSET(n) (8 * ((n) - 1)) +#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ +#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ +#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ +#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ + +#define STM32_FSMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) +#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ +#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ +#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ +#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ + +#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) +#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ +#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ +#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ +#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ + +#define STM32_FSMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) +#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FSMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) +#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ +#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ +#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ + +#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) +#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ +#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ +#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ + +#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) +#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ +#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ +#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ + +#define STM32_FSMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ + +#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) +#define STM32_FSMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ +#define STM32_FSMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ + +/* Register Addresses *******************************************************/ + +#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n)) +#define STM32_FSMC_BCR1 (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET) +#define STM32_FSMC_BCR2 (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET) +#define STM32_FSMC_BCR3 (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET) +#define STM32_FSMC_BCR4 (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET) + +#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n)) +#define STM32_FSMC_BTR1 (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET) +#define STM32_FSMC_BTR2 (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET) +#define STM32_FSMC_BTR3 (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET) +#define STM32_FSMC_BTR4 (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET) + +#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n)) +#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET) +#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET) +#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET) +#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET) + +#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n)) +#define STM32_FSMC_PCR2 (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET) +#define STM32_FSMC_PCR3 (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET) +#define STM32_FSMC_PCR4 (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET) + +#define STM32_FSMC_SR(n) (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n)) +#define STM32_FSMC_SR2 (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET) +#define STM32_FSMC_SR3 (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET) +#define STM32_FSMC_SR4 (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET) + +#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n)) +#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET) +#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET) +#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET) + +#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n)) +#define STM32_FSMC_PATT2 (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET) +#define STM32_FSMC_PATT3 (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET) +#define STM32_FSMC_PATT4 (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET) + +#define STM32_FSMC_PIO4 (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET) + +#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n)) +#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET) +#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ +#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */ +#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT) +# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT) +#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ +#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT) +# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT) +# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT) +#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */ +#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ +#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ +#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ +#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ +#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ +#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ +#endif +#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ + +#define FSMC_BCR_RSTVALUE 0x000003d2 + +#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT) +# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT) +# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT) +# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT) +# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT) +# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */ +#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT) +# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT) +# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) + +#define FSMC_BTR_RSTVALUE 0xffffffff + +#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ +#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT) +# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT) +# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ + +#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ +#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT) +# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ +#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT) +# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ + +#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ +#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT) +# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ + +#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ +#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT) +# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) + +#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PTYP (1 << 3) /* Memory type */ +#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ +#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT) +# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT) +# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT) +#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ +#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ +#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT) +# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ +#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK) +# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ + +#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ +#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT) +# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */ +# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */ +# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ +# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ +# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ +# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ + +#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ +#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */ +#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ +#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ +#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */ + +#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ +#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT) +# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ +#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT) +# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ +#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT) +# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ +#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT) +# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ +#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT) +# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ +#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT) +# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ +#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT) +# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ +#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT) +# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#define FSMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ +#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT) +# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ + +#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ +#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT) +# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ + +#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ +#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT) +# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ + +#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ +#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) +# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_memorymap.h b/arch/arm/src/common/stm32/hardware/stm32_gpio.h similarity index 61% rename from arch/arm/src/stm32/hardware/stm32_memorymap.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio.h index 5fd8733f4f660..ea028b5b22335 100644 --- a/arch/arm/src/stm32/hardware/stm32_memorymap.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_memorymap.h + * arch/arm/src/common/stm32/hardware/stm32_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,34 +20,30 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_memorymap.h" +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "hardware/stm32_gpio_v2_m0.h" +#elif defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_memorymap.h" +# include "hardware/stm32f10xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_memorymap.h" +# include "hardware/stm32f20xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_memorymap.h" +# include "hardware/stm32f40xxx_gpio.h" #elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_memorymap.h" +# include "hardware/stm32g4xxxx_gpio.h" #else -# error "Unsupported STM32 memory map" +# error "Unsupported STM32 GPIO" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h index 11ecd42a32daf..94637dfc7a181 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h + * arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -344,4 +344,4 @@ #define GPIO_BRR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c.h new file mode 100644 index 0000000000000..879ec20a764f2 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1 +# error Only one STM32 I2C IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) +# include "hardware/stm32_i2c_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) +# include "stm32_i2c_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +# include "stm32_i2c_v2.h" +#else +# error STM32 I2C IP version not specified +#endif +#else +# error "Unsupported STM32 I2C" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h new file mode 100644 index 0000000000000..9f3bbda52a425 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h @@ -0,0 +1,203 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H + +/* This file provide definitions for the STM32 I2C IP core 1 + *(F1, F2, F4 and L1) + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */ +#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */ +#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */ +#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */ +#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */ +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) +# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */ +#endif + +/* Register Addresses *******************************************************/ + +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET) +# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET) +# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET) +# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET) +# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET) +# ifdef STM32_I2C_FLTR_OFFSET +# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET) +# endif +#endif + +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET) +# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET) +# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET) +# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET) +# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET) +# ifdef STM32_I2C_FLTR_OFFSET +# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET) +# endif +#endif + +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_DR (STM32_I2C3_BASE+STM32_I2C_DR_OFFSET) +# define STM32_I2C3_SR1 (STM32_I2C3_BASE+STM32_I2C_SR1_OFFSET) +# define STM32_I2C3_SR2 (STM32_I2C3_BASE+STM32_I2C_SR2_OFFSET) +# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET) +# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET) +# ifdef STM32_I2C_FLTR_OFFSET +# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET) +# endif +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ +#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */ +#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */ +#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */ +#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */ +#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */ +#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */ +#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */ +#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */ +#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */ +#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */ +#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */ + +/* Control register 2 */ + +#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */ +#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT) +#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */ +#define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */ +#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */ + +#define I2C_CR2_ALLINTS (I2C_CR2_ITERREN|I2C_CR2_ITEVFEN|I2C_CR2_ITBUFEN) + +/* Own address register 1 */ + +#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */ +#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */ +#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT) +#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/ +#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT) +#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */ +#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */ + +/* Own address register 2 */ + +#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */ +#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */ +#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT) + +/* Data register */ + +#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */ +#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT) + +/* Status register 1 */ + +#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */ +#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */ +#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */ + /* Bit 5: Reserved */ +#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */ +#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */ +#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */ +#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */ +#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */ +#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */ +#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */ + /* Bit 13: Reserved */ +#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */ + +#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|\ + I2C_SR1_PECERR|I2C_SR1_TIMEOUT|I2C_SR1_SMBALERT) + +/* Status register 2 */ + +#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */ +#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */ +#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */ +#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */ +#define I2C_SR2_PEC_SHIFT (8) /* Bits 15-8: Packet Error Checking Register */ +#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT) + +/* Clock control register */ + +#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT) +#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */ +#define I2C_CCR_FS (1 << 15) /* Bit 15: Fast Mode Selection */ + +/* TRISE Register */ + +#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */ +#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT) + +/* FLTR Register */ + +#ifdef STM32_I2C_FLTR_OFFSET +# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */ +# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */ +# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT) +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h new file mode 100644 index 0000000000000..5f3212b26c345 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H + +/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, + * G4, H7, L0 and L4). + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) +#endif + +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) +#endif + +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ +#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ +#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ +#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ +#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ +#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ +#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) +# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ +#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ +#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ +#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ +#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ +#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ +#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ +#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ +#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ +#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ +#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ + +/* Control register 2 */ + +#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ +#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) +#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ +#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) +#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ +#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ +#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ +#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ +#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ +#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ +#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ +#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) +#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ +#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ +#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ + +/* Own address register 1 */ + +#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ +#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) +#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) +#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ +#define I2C_OAR1_ONE (1 << 14) /* Bit 14: always keep on in software */ +#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ + +/* Own address register 2 */ + +#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ +#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) +#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) +# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ +# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ +# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ +# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ +# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ +# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ +# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ +# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ +#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ + +/* Timing register */ + +#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ +#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) +# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ + +#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ +#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) +# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ + +#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ +#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) +# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ + +#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ +#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) +# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ + +#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ +#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) +# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ + +/* Timeout register */ + +#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ +#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) +# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) +#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ +#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ +#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) +# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) +#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ + +/* Interrupt and Status register and interrupt clear register */ + +/* Common interrupt bits */ + +#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ +#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ +#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ +#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ +#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ +#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ +#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ +#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ +#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ + +/* Fields unique to the Interrupt and Status register */ + +#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ +#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ +#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ +#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ +#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ +#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ +#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ +#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) + +#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) + +#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ + | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) + +/* Packet error checking register */ + +#define I2C_PECR_MASK (0xff) + +/* Receive data register */ + +#define I2C_RXDR_MASK (0xff) + +/* Transmit data register */ + +#define I2C_TXDR_MASK (0xff) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h index aa10265f4a93b..2f8d29fd1f9a5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -224,4 +224,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_lcd.h b/arch/arm/src/common/stm32/hardware/stm32_lcd.h new file mode 100644 index 0000000000000..d23ab4d41e72b --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_lcd.h @@ -0,0 +1,209 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_lcd.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/* These definitions are valid only if the MCU supports a segment LCD */ + +#if STM32_NLCD > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_LCD_CR_OFFSET 0x0000 /* LCD control register */ +#define STM32_LCD_FCR_OFFSET 0x0004 /* LCD frame control register */ +#define STM32_LCD_SR_OFFSET 0x0008 /* LCD status register */ +#define STM32_LCD_CLR_OFFSET 0x000c /* LCD clear register */ + +#define STM32_LCD_RAM_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn */ +#define STM32_LCD_RAML_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn, S00-S31 */ +#define STM32_LCD_RAMH_OFFSET(n) (0x0018 + ((n) << 3)) /* LCD display memory, COMn, S32-S39 */ + +#define STM32_LCD_RAM0L_OFFSET 0x0014 /* LCD display memory, COM0, S00-S31 */ +#define STM32_LCD_RAM0H_OFFSET 0x0018 /* LCD display memory, COM0, S32-S39 */ +#define STM32_LCD_RAM1L_OFFSET 0x001c /* LCD display memory, COM1, S00-S31 */ +#define STM32_LCD_RAM1H_OFFSET 0x0020 /* LCD display memory, COM1, S32-S39 */ +#define STM32_LCD_RAM2L_OFFSET 0x0024 /* LCD display memory, COM2, S00-S31 */ +#define STM32_LCD_RAM2H_OFFSET 0x0028 /* LCD display memory, COM2, S32-S39 */ +#define STM32_LCD_RAM3L_OFFSET 0x002c /* LCD display memory, COM3, S00-S31 */ +#define STM32_LCD_RAM3H_OFFSET 0x0020 /* LCD display memory, COM3, S32-S39 */ +#define STM32_LCD_RAM4L_OFFSET 0x0034 /* LCD display memory, COM4, S00-S31 */ +#define STM32_LCD_RAM4H_OFFSET 0x0038 /* LCD display memory, COM4, S32-S39 */ +#define STM32_LCD_RAM5L_OFFSET 0x003c /* LCD display memory, COM5, S00-S31 */ +#define STM32_LCD_RAM5H_OFFSET 0x0040 /* LCD display memory, COM5, S32-S39 */ +#define STM32_LCD_RAM6L_OFFSET 0x0044 /* LCD display memory, COM6, S00-S31 */ +#define STM32_LCD_RAM6H_OFFSET 0x0048 /* LCD display memory, COM6, S32-S39 */ +#define STM32_LCD_RAM7L_OFFSET 0x004c /* LCD display memory, COM7, S00-S31 */ +#define STM32_LCD_RAM7H_OFFSET 0x0050 /* LCD display memory, COM7, S32-S39 */ + +/* Register Addresses *******************************************************/ + +#define STM32_LCD_CR (STM32_LCD_BASE+STM32_LCD_CR_OFFSET) +#define STM32_LCD_FCR (STM32_LCD_BASE+STM32_LCD_FCR_OFFSET) +#define STM32_LCD_SR (STM32_LCD_BASE+STM32_LCD_SR_OFFSET) +#define STM32_LCD_CLR (STM32_LCD_BASE+STM32_LCD_CLR_OFFSET) + +#define STM32_LCD_RAM(n) (STM32_LCD_BASE+STM32_LCD_RAM_OFFSET(n)) +#define STM32_LCD_RAML(n) (STM32_LCD_BASE+STM32_LCD_RAML_OFFSET(n)) +#define STM32_LCD_RAMH(n) (STM32_LCD_BASE+STM32_LCD_RAMH_OFFSET(n)) + +#define STM32_LCD_RAM0L (STM32_LCD_BASE+STM32_LCD_RAM0L_OFFSET) +#define STM32_LCD_RAM0H (STM32_LCD_BASE+STM32_LCD_RAM0H_OFFSET) +#define STM32_LCD_RAM1L (STM32_LCD_BASE+STM32_LCD_RAM1L_OFFSET) +#define STM32_LCD_RAM1H (STM32_LCD_BASE+STM32_LCD_RAM1H_OFFSET) +#define STM32_LCD_RAM2L (STM32_LCD_BASE+STM32_LCD_RAM2L_OFFSET) +#define STM32_LCD_RAM2H (STM32_LCD_BASE+STM32_LCD_RAM2H_OFFSET) +#define STM32_LCD_RAM3L (STM32_LCD_BASE+STM32_LCD_RAM3L_OFFSET) +#define STM32_LCD_RAM3H (STM32_LCD_BASE+STM32_LCD_RAM3H_OFFSET) +#define STM32_LCD_RAM4L (STM32_LCD_BASE+STM32_LCD_RAM4L_OFFSET) +#define STM32_LCD_RAM4H (STM32_LCD_BASE+STM32_LCD_RAM4H_OFFSET) +#define STM32_LCD_RAM5L (STM32_LCD_BASE+STM32_LCD_RAM5L_OFFSET) +#define STM32_LCD_RAM5H (STM32_LCD_BASE+STM32_LCD_RAM5H_OFFSET) +#define STM32_LCD_RAM6L (STM32_LCD_BASE+STM32_LCD_RAM6L_OFFSET) +#define STM32_LCD_RAM6H (STM32_LCD_BASE+STM32_LCD_RAM6H_OFFSET) +#define STM32_LCD_RAM7L (STM32_LCD_BASE+STM32_LCD_RAM7L_OFFSET) +#define STM32_LCD_RAM7H (STM32_LCD_BASE+STM32_LCD_RAM7H_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* LCD control register */ + +#define LCD_CR_LCDEN (1 << 0) /* Bit 0: LCD controller enable */ +#define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */ +#define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */ +#define LCD_CR_DUTY_MASK (7 << LCD_CR_DUTY_SHIFT) +# define LCD_CR_DUTY_STATIC (0 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ +# define LCD_CR_DUTY_1TO2 (1 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ +# define LCD_CR_DUTY_1TO3 (2 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ +# define LCD_CR_DUTY_1TO4 (3 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ +# define LCD_CR_DUTY_1TO8 (4 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ + +#define LCD_CR_BIAS_SHIFT (5) /* Bits 5-6: Bias selector */ +#define LCD_CR_BIAS_MASK (3 << LCD_CR_BIAS_SHIFT) +# define LCD_CR_BIAS_1TO4 (0 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */ +# define LCD_CR_BIAS_1TO2 (1 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */ +# define LCD_CR_BIAS_1TO3 (2 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */ + +#define LCD_CR_MUX_SEG (1 << 7) /* Bit 7: Mux segment enable */ + /* Bits 8-31 Reserved */ + +/* LCD frame control register */ + +#define LCD_FCR_HD (1 << 0) /* Bit 0: High drive enable */ +#define LCD_FCR_SOFIE (1 << 1) /* Bit 1: Start of frame interrupt enable */ + /* Bit 2 Reserved */ +#define LCD_FCR_UDDIE (1 << 3) /* Bit 3: Update display done interrupt enable */ +#define LCD_FCR_PON_SHIFT (4) /* Bits 4-6: Pulse ON duration */ +#define LCD_FCR_PON_MASK (7 << LCD_FCR_PON_SHIFT) +# define LCD_FCR_PON(n) ((n) << LCD_FCR_PON_SHIFT) /* n=0-7 */ + +#define LCD_FCR_DEAD_SHIFT (7) /* Bits 7-9: Dead time duration */ +#define LCD_FCR_DEAD_MASK (7 << LCD_FCR_DEAD_SHIFT) +# define LCD_FCR_DEAD_NONE (0 << LCD_FCR_DEAD_SHIFT) +# define LCD_FCR_DEAD(n) ((n) << LCD_FCR_DEAD_SHIFT) /* n=1..7 */ + +#define LCD_FCR_CC_SHIFT (10) /* Bits 10-12: Contrast control */ +#define LCD_FCR_CC_MASK (7 << LCD_FCR_CC_SHIFT) +# define LCD_FCR_CC_VLCD(n) ((n) << LCD_FCR_CC_SHIFT) /* VLCDn, n=0..7 */ + +#define LCD_FCR_BLINKF_SHIFT (13) /* Bits 13-15: Blink frequency selection */ +#define LCD_FCR_BLINKF_MASK (7 << LCD_FCR_BLINKF_SHIFT) +# define LCD_FCR_BLINKF_DIV8 (0 << LCD_FCR_BLINKF_SHIFT) /* 000: fLCD/8 */ +# define LCD_FCR_BLINKF_DIV16 (1 << LCD_FCR_BLINKF_SHIFT) /* 001: fLCD/16 */ +# define LCD_FCR_BLINKF_DIV32 (2 << LCD_FCR_BLINKF_SHIFT) /* 010: fLCD/32 */ +# define LCD_FCR_BLINKF_DIV64 (3 << LCD_FCR_BLINKF_SHIFT) /* 011: fLCD/64 */ +# define LCD_FCR_BLINKF_DIV128 (4 << LCD_FCR_BLINKF_SHIFT) /* 100: fLCD/128 */ +# define LCD_FCR_BLINKF_DIV256 (5 << LCD_FCR_BLINKF_SHIFT) /* 101: fLCD/256 */ +# define LCD_FCR_BLINKF_DIV512 (6 << LCD_FCR_BLINKF_SHIFT) /* 110: fLCD/512 */ +# define LCD_FCR_BLINKF_DIV1024 (7 << LCD_FCR_BLINKF_SHIFT) /* 111: fLCD/1024 */ + +#define LCD_FCR_BLINK_SHIFT (16) /* Bits 16-17: Blink mode selection */ +#define LCD_FCR_BLINK_MASK (3 << LCD_FCR_BLINK_SHIFT) +# define LCD_FCR_BLINK_DISABLE (0 << LCD_FCR_BLINK_SHIFT) /* 00: Blink disabled */ +# define LCD_FCR_BLINK_S0C0 (1 << LCD_FCR_BLINK_SHIFT) /* 01: Blink enabled on SEG[0], COM[0] (1 pixel) */ +# define LCD_FCR_BLINK_S0CALL (2 << LCD_FCR_BLINK_SHIFT) /* 10: Blink enabled on SEG[0], all COMs */ +# define LCD_FCR_BLINK_SALLCALL (3 << LCD_FCR_BLINK_SHIFT) /* 11: Blink enabled on all SEGs and all COMs */ + +#define LCD_FCR_DIV_SHIFT (18) /* Bits 18-21: DIV clock divider */ +#define LCD_FCR_DIV_MASK (15 << LCD_FCR_DIV_SHIFT) +# define LCD_FCR_DIV(n) (((n)-16) << LCD_FCR_DIV_SHIFT) /* n=16-31 */ + +#define LCD_FCR_PS_SHIFT (22) /* Bits 22-25: PS 16-bit prescaler */ +#define LCD_FCR_PS_MASK (15 << LCD_FCR_PS_SHIFT) +# define LCD_FCR_PS_DIV1 (0 << LCD_FCR_PS_SHIFT) /* 0000: ck_ps = LCDCLK */ +# define LCD_FCR_PS_DIV2 (1 << LCD_FCR_PS_SHIFT) /* 0001: ck_ps = LCDCLK/2 */ +# define LCD_FCR_PS_DIV4 (2 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4 */ +# define LCD_FCR_PS_DIV8 (3 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8 */ +# define LCD_FCR_PS_DIV16 (4 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16 */ +# define LCD_FCR_PS_DIV32 (5 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32 */ +# define LCD_FCR_PS_DIV64 (6 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/64 */ +# define LCD_FCR_PS_DIV128 (7 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/128 */ +# define LCD_FCR_PS_DIV256 (8 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/256 */ +# define LCD_FCR_PS_DIV512 (9 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/512 */ +# define LCD_FCR_PS_DIV1024 (10 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/1024 */ +# define LCD_FCR_PS_DIV2048 (11 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/2048 */ +# define LCD_FCR_PS_DIV4096 (12 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4096 */ +# define LCD_FCR_PS_DIV8192 (13 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8192 */ +# define LCD_FCR_PS_DIV16384 (14 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16384 */ +# define LCD_FCR_PS_DIV32768 (15 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32768 */ + + /* Bits 26-31 Reserved */ + +/* LCD status register */ + +#define LCD_SR_ENS (1 << 0) /* Bit 0: LCD enabled status */ +#define LCD_SR_SOF (1 << 1) /* Bit 1: Start of frame flag */ +#define LCD_SR_UDR (1 << 2) /* Bit 2: Update display request */ +#define LCD_SR_UDD (1 << 3) /* Bit 3: Update Display Done */ +#define LCD_SR_RDY (1 << 4) /* Bit 4: Ready flag */ +#define LCD_SR_FCRSF (1 << 5) /* Bit 5: LCD Frame Control Register Synchronization flag */ + /* Bits 6-31 Reserved */ + +/* LCD clear register */ + + /* Bit 0 Reserved */ +#define LCD_CLR_SOFC (1 << 1) /* Bit 1: Start of frame flag clear */ + /* Bit 2 Reserved */ +#define LCD_CLR_UDDC (1 << 2) /* Bit 3: Update display done clear */ + /* Bits 31:2-31 Reserved */ + +/* LCD display memory, COMn, S00-S31 */ + +#define LCD_RAML_S(n) (1 << (n)) + +/* LCD display memory, COMn, S32-S39 */ + +#define LCD_RAMH_S(n) (1 << ((n)-32)) + +#endif /* STM32_NLCD */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_ltdc.h b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h new file mode 100644 index 0000000000000..9d7be41f4390b --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h @@ -0,0 +1,368 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/stm32_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_LTDC_NCLUT 256 /* Number of entries in the CLUTs */ + +/* LCDC Register Offsets ****************************************************/ + +#define STM32_LTDC_SSCR_OFFSET 0x0008 /* LTDC Synchronization Size Config Register */ +#define STM32_LTDC_BPCR_OFFSET 0x000c /* LTDC Back Porch Configuration Register */ +#define STM32_LTDC_AWCR_OFFSET 0x0010 /* LTDC Active Width Configuration Register */ +#define STM32_LTDC_TWCR_OFFSET 0x0014 /* LTDC Total Width Configuration Register */ +#define STM32_LTDC_GCR_OFFSET 0x0018 /* LTDC Global Control Register */ + /* 0x0020 Reserved */ +#define STM32_LTDC_SRCR_OFFSET 0x0024 /* LTDC Shadow Reload Configuration Register */ + /* 0x0028 Reserved */ +#define STM32_LTDC_BCCR_OFFSET 0x002c /* LTDC Background Color Configuration Register */ + /* 0x0030 Reserved */ +#define STM32_LTDC_IER_OFFSET 0x0034 /* LTDC Interrupt Enable Register */ +#define STM32_LTDC_ISR_OFFSET 0x0038 /* LTDC Interrupt Status Register */ +#define STM32_LTDC_ICR_OFFSET 0x003c /* LTDC Interrupt Clear Register */ +#define STM32_LTDC_LIPCR_OFFSET 0x0040 /* LTDC Line Interrupt Position Config Register */ +#define STM32_LTDC_CPSR_OFFSET 0x0044 /* LTDC Current Position Status Register */ +#define STM32_LTDC_CDSR_OFFSET 0x0048 /* LTDC Current Display Status Register */ + /* 0x004c-0x0080 Reserved */ + +#define STM32_LTDC_L1CR_OFFSET 0x0084 /* LTDC Layer 1 Control Register */ +#define STM32_LTDC_L1WHPCR_OFFSET 0x0088 /* LTDC Layer 1 Window Horiz Pos Config Register */ +#define STM32_LTDC_L1WVPCR_OFFSET 0x008c /* LTDC Layer 1 Window Vert Pos Config Register */ +#define STM32_LTDC_L1CKCR_OFFSET 0x0090 /* LTDC Layer 1 Color Keying Config Register */ +#define STM32_LTDC_L1PFCR_OFFSET 0x0094 /* LTDC Layer 1 Pixel Format Configuration Register */ +#define STM32_LTDC_L1CACR_OFFSET 0x0098 /* LTDC Layer 1 Constant Alpha Config Register */ +#define STM32_LTDC_L1DCCR_OFFSET 0x009c /* LTDC Layer 1 Default Color Config Register */ +#define STM32_LTDC_L1BFCR_OFFSET 0x00a0 /* LTDC Layer 1 Blending Factors Config Register */ + /* 0x00A4-0x00A8 Reserved */ +#define STM32_LTDC_L1CFBAR_OFFSET 0x00ac /* LTDC Layer 1 Color Frame Buffer Address Register */ +#define STM32_LTDC_L1CFBLR_OFFSET 0x00b0 /* LTDC Layer 1 Color Frame Buffer Length Register */ +#define STM32_LTDC_L1CFBLNR_OFFSET 0x00b4 /* LTDC Layer 1 Color Frame Buffer Line Number Register */ + /* 0x00B8-0x00C0 Reserved */ +#define STM32_LTDC_L1CLUTWR_OFFSET 0x00c4 /* LTDC Layer 1 CLUT Write Register */ + /* 0x00C8-0x0100 Reserved */ +#define STM32_LTDC_L2CR_OFFSET 0x0104 /* LTDC Layer 2 Control Register */ +#define STM32_LTDC_L2WHPCR_OFFSET 0x0108 /* LTDC Layer 2 Window Horiz Pos Config Register */ +#define STM32_LTDC_L2WVPCR_OFFSET 0x010c /* LTDC Layer 2 Window Vert Pos Config Register */ +#define STM32_LTDC_L2CKCR_OFFSET 0x0110 /* LTDC Layer 2 Color Keying Config Register */ +#define STM32_LTDC_L2PFCR_OFFSET 0x0114 /* LTDC Layer 2 Pixel Format Configuration Register */ +#define STM32_LTDC_L2CACR_OFFSET 0x0118 /* LTDC Layer 2 Constant Alpha Config Register */ +#define STM32_LTDC_L2DCCR_OFFSET 0x011c /* LTDC Layer 2 Default Color Config Register */ +#define STM32_LTDC_L2BFCR_OFFSET 0x0120 /* LTDC Layer 2 Blending Factors Config Register */ + /* 0x0124-0x0128 Reserved */ +#define STM32_LTDC_L2CFBAR_OFFSET 0x012c /* LTDC Layer 2 Color Frame Buffer Address Register */ +#define STM32_LTDC_L2CFBLR_OFFSET 0x0130 /* LTDC Layer 2 Color Frame Buffer Length Register */ +#define STM32_LTDC_L2CFBLNR_OFFSET 0x0134 /* LTDC Layer 2 Color Frame Buffer Line Number Register */ + /* 0x0138-0x0130 Reserved */ +#define STM32_LTDC_L2CLUTWR_OFFSET 0x0144 /* LTDC Layer 2 CLUT Write Register */ + /* 0x0148-0x03ff Reserved */ + +/* LTDC Register Addresses **************************************************/ + +#define STM32_LTDC_SSCR (STM32_LTDC_BASE + STM32_LTDC_SSCR_OFFSET) +#define STM32_LTDC_BPCR (STM32_LTDC_BASE + STM32_LTDC_BPCR_OFFSET) +#define STM32_LTDC_AWCR (STM32_LTDC_BASE + STM32_LTDC_AWCR_OFFSET) +#define STM32_LTDC_TWCR (STM32_LTDC_BASE + STM32_LTDC_TWCR_OFFSET) +#define STM32_LTDC_GCR (STM32_LTDC_BASE + STM32_LTDC_GCR_OFFSET) +#define STM32_LTDC_SRCR (STM32_LTDC_BASE + STM32_LTDC_SRCR_OFFSET) +#define STM32_LTDC_BCCR (STM32_LTDC_BASE + STM32_LTDC_BCCR_OFFSET) +#define STM32_LTDC_IER (STM32_LTDC_BASE + STM32_LTDC_IER_OFFSET) +#define STM32_LTDC_ISR (STM32_LTDC_BASE + STM32_LTDC_ISR_OFFSET) +#define STM32_LTDC_ICR (STM32_LTDC_BASE + STM32_LTDC_ICR_OFFSET) +#define STM32_LTDC_LIPCR (STM32_LTDC_BASE + STM32_LTDC_LIPCR_OFFSET) +#define STM32_LTDC_CPSR (STM32_LTDC_BASE + STM32_LTDC_CPSR_OFFSET) +#define STM32_LTDC_CDSR (STM32_LTDC_BASE + STM32_LTDC_CDSR_OFFSET) + +#define STM32_LTDC_L1CR (STM32_LTDC_BASE + STM32_LTDC_L1CR_OFFSET) +#define STM32_LTDC_L1WHPCR (STM32_LTDC_BASE + STM32_LTDC_L1WHPCR_OFFSET) +#define STM32_LTDC_L1WVPCR (STM32_LTDC_BASE + STM32_LTDC_L1WVPCR_OFFSET) +#define STM32_LTDC_L1CKCR (STM32_LTDC_BASE + STM32_LTDC_L1CKCR_OFFSET) +#define STM32_LTDC_L1PFCR (STM32_LTDC_BASE + STM32_LTDC_L1PFCR_OFFSET) +#define STM32_LTDC_L1CACR (STM32_LTDC_BASE + STM32_LTDC_L1CACR_OFFSET) +#define STM32_LTDC_L1DCCR (STM32_LTDC_BASE + STM32_LTDC_L1DCCR_OFFSET) +#define STM32_LTDC_L1BFCR (STM32_LTDC_BASE + STM32_LTDC_L1BFCR_OFFSET) +#define STM32_LTDC_L1CFBAR (STM32_LTDC_BASE + STM32_LTDC_L1CFBAR_OFFSET) +#define STM32_LTDC_L1CFBLR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLR_OFFSET) +#define STM32_LTDC_L1CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLNR_OFFSET) +#define STM32_LTDC_L1CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L1CLUTWR_OFFSET) + +#define STM32_LTDC_L2CR (STM32_LTDC_BASE + STM32_LTDC_L2CR_OFFSET) +#define STM32_LTDC_L2WHPCR (STM32_LTDC_BASE + STM32_LTDC_L2WHPCR_OFFSET) +#define STM32_LTDC_L2WVPCR (STM32_LTDC_BASE + STM32_LTDC_L2WVPCR_OFFSET) +#define STM32_LTDC_L2CKCR (STM32_LTDC_BASE + STM32_LTDC_L2CKCR_OFFSET) +#define STM32_LTDC_L2PFCR (STM32_LTDC_BASE + STM32_LTDC_L2PFCR_OFFSET) +#define STM32_LTDC_L2CACR (STM32_LTDC_BASE + STM32_LTDC_L2CACR_OFFSET) +#define STM32_LTDC_L2DCCR (STM32_LTDC_BASE + STM32_LTDC_L2DCCR_OFFSET) +#define STM32_LTDC_L2BFCR (STM32_LTDC_BASE + STM32_LTDC_L2BFCR_OFFSET) +#define STM32_LTDC_L2CFBAR (STM32_LTDC_BASE + STM32_LTDC_L2CFBAR_OFFSET) +#define STM32_LTDC_L2CFBLR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLR_OFFSET) +#define STM32_LTDC_L2CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLNR_OFFSET) +#define STM32_LTDC_L2CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L2CLUTWR_OFFSET) + +/* LTDC Register Bit Definitions ********************************************/ + +/* LTDC Synchronization Size Configuration Register */ + +#define LTDC_SSCR_VSH_SHIFT (0) /* Bits 0-10: Vertical Sync Height (scan lines) */ +#define LTDC_SSCR_VSH_MASK (0x7ff << LTDC_SSCR_VSH_SHIFT) +# define LTDC_SSCR_VSH(n) ((uint32_t)(n) << LTDC_SSCR_VSH_SHIFT) +#define LTDC_SSCR_HSW_SHIFT (16) /* Bits 16-27: Horizontal Sync Width (pixel clocks) */ +#define LTDC_SSCR_HSW_MASK (0xfff << LTDC_SSCR_HSW_SHIFT) +# define LTDC_SSCR_HSW(n) ((uint32_t)(n) << LTDC_SSCR_HSW_SHIFT) + +/* LTDC Back Porch Configuration Register */ + +#define LTDC_BPCR_AVBP_SHIFT (0) /* Bits 0-10: Accumulated Vertical back porch (scan lines) */ +#define LTDC_BPCR_AVBP_MASK (0x7ff << LTDC_BPCR_AVBP_SHIFT) +# define LTDC_BPCR_AVBP(n) ((uint32_t)(n) << LTDC_BPCR_AVBP_SHIFT) +#define LTDC_BPCR_AHBP_SHIFT (16) /* Bits 16-27: Accumulated Horizontal back porch (pixel clocks) */ +#define LTDC_BPCR_AHBP_MASK (0xfff << LTDC_BPCR_AVBP_SHIFT) +# define LTDC_BPCR_AHBP(n) ((uint32_t)(n) << LTDC_BPCR_AHBP_SHIFT) + +/* LTDC Active Width Configuration Register */ + +#define LTDC_AWCR_AAH_SHIFT (0) /* Bits 0-10: Accumulated Active Height (scan lines) */ +#define LTDC_AWCR_AAH_MASK (0x7ff << LTDC_AWCR_AAH_SHIFT) +# define LTDC_AWCR_AAH(n) ((uint32_t)(n) << LTDC_AWCR_AAH_SHIFT) +#define LTDC_AWCR_AAW_SHIFT (16) /* Bits 16-27: Accumulated Active Width (pixel clocks) */ +#define LTDC_AWCR_AAW_MASK (0xfff << LTDC_AWCR_AAW_SHIFT) +# define LTDC_AWCR_AAW(n) ((uint32_t)(n) << LTDC_AWCR_AAW_SHIFT) + +/* LTDC Total Width Configuration Register */ + +#define LTDC_TWCR_TOTALH_SHIFT (0) /* Bits 0-10: Total Height (scan lines) */ +#define LTDC_TWCR_TOTALH_MASK (0x7ff << LTDC_TWCR_TOTALH_SHIFT) +# define LTDC_TWCR_TOTALH(n) ((uint32_t)(n) << LTDC_TWCR_TOTALH_SHIFT) +#define LTDC_TWCR_TOTALW_SHIFT (16) /* Bits 16-27: Total Width (pixel clocks) */ +#define LTDC_TWCR_TOTALW_MASK (0xfff << LTDC_TWCR_TOTALW_SHIFT) +# define LTDC_TWCR_TOTALW(n) ((uint32_t)(n) << LTDC_TWCR_TOTALW_SHIFT) + +/* LTDC Global Control Register */ + +#define LTDC_GCR_LTDCEN (1 << 0) /* Bit 0: LCD-TFT Controller Enable Bit */ +#define LTDC_GCR_DBW_SHIFT (4) /* Bits 4-6: Dither Blue Width */ +#define LTDC_GCR_DBW_MASK (0x7 << LTDC_GCR_DBW_SHIFT) +# define LTDC_GCR_DBW(n) ((uint32_t)(n) << LTDC_GCR_DBW_SHIFT) +#define LTDC_GCR_DGW_SHIFT (8) /* Bits 8-10: Dither Green Width */ +#define LTDC_GCR_DGW_MASK (0x7 << LTDC_GCR_DGW_SHIFT) +# define LTDC_GCR_DGW(n) ((uint32_t)(n) << LTDC_GCR_DGW_SHIFT) +#define LTDC_GCR_DRW_SHIFT (12) /* Bits 12-14: Dither Red Width */ +#define LTDC_GCR_DRW_MASK (0x7 << LTDC_GCR_DRW_SHIFT) +# define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT) +#define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */ +#define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */ +#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */ +#define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */ +#define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */ + +/* LTDC Shadow Reload Configuration Register */ + +#define LTDC_SRCR_IMR (1 << 0) /* Bit 0: Immediate Reload */ +#define LTDC_SRCR_VBR (1 << 1) /* Bit 1: Vertical Blanking Reload */ + +/* LTDC Background Color Configuration Register */ + +#define LTDC_BCCR_BCBLUE_SHIFT (0) /* Bits 0-7: Background Color Blue Value */ +#define LTDC_BCCR_BCBLUE_MASK (0xff << LTDC_BCCR_BCBLUE_SHIFT) +# define LTDC_BCCR_BCBLUE(n) ((uint32_t)(n) << LTDC_BCCR_BCBLUE_SHIFT) +#define LTDC_BCCR_BCGREEN_SHIFT (8) /* Bits 8-15: Background Color Green Value */ +#define LTDC_BCCR_BCGREEN_MASK (0xff << LTDC_BCCR_BCGREEN_SHIFT) +# define LTDC_BCCR_BCGREEN(n) ((uint32_t)(n) << LTDC_BCCR_BCGREEN_SHIFT) +#define LTDC_BCCR_BCRED_SHIFT (16) /* Bits 16-23: Background Color Red Value */ +#define LTDC_BCCR_BCRED_MASK (0xff << LTDC_BCCR_BCRED_SHIFT) +# define LTDC_BCCR_BCRED(n) ((uint32_t)(n) << LTDC_BCCR_BCRED_SHIFT) + +/* LTDC Interrupt Enable Register */ + +#define LTDC_IER_LIE (1 << 0) /* Bit 0: Line Interrupt Enable */ +#define LTDC_IER_FUIE (1 << 1) /* Bit 1: FIFO Underrun Interrupt Enable */ +#define LTDC_IER_TERRIE (1 << 2) /* Bit 2: Transfer Error Interrupt Enable */ +#define LTDC_IER_RRIE (1 << 3) /* Bit 3: Register Reload Interrupt Enable */ + +/* LTDC Interrupt Status Register */ + +#define LTDC_ISR_LIF (1 << 0) /* Bit 0: Line Interrupt Flag */ +#define LTDC_ISR_FUIF (1 << 1) /* Bit 1: FIFO Underrun Interrupt Flag */ +#define LTDC_IER_TERRIF (1 << 2) /* Bit 2: Transfer Error Interrupt Flag */ +#define LTDC_ISR_RRIF (1 << 3) /* Bit 3: Register Reload Interrupt Flag */ + +/* LTDC Interrupt Clear Register */ + +#define LTDC_ICR_CLIF (1 << 0) /* Bit 0: Clear Line Interrupt Flag */ +#define LTDC_ICR_CFUIF (1 << 1) /* Bit 1: Clear FIFO Underrun Interrupt Flag */ +#define LTDC_ICR_CTERRIF (1 << 2) /* Bit 2: Clear Transfer Error Interrupt Flag */ +#define LTDC_ICR_CRRIF (1 << 3) /* Bit 3: Clear Register Reload Interrupt Flag */ + +/* LTDC Line Interrupt Posittion Configuration Register */ + +#define LTDC_LIPCR_LIPOS_SHIFT (0) /* Bits 0-10: Line Interrupt Position */ +#define LTDC_LIPCR_LIPOS_MASK (0x7ff << LTDC_LIPCR_LIPOS_SHIFT) +# define LTDC_LIPCR_LIPOS(n) ((uint32_t)(n) << LTDC_LIPCR_LIPOS_SHIFT) + +/* LTDC Current Position Status Register */ + +#define LTDC_CPSR_CYPOS_SHIFT (0) /* Bits 0-15: Current Y Position */ +#define LTDC_CPSR_CYPOS_MASK (0xffff << LTDC_CPSR_CYPOS_SHIFT) +# define LTDC_CPSR_CYPOS(n) ((uint32_t)(n) << LTDC_CPSR_CYPOS_SHIFT) +#define LTDC_CPSR_CXPOS_SHIFT (16) /* Bits 15-31: Current X Position */ +#define LTDC_CPSR_CXPOS_MASK (0xffff << LTDC_CPSR_CXPOS_SHIFT) +# define LTDC_CPSR_CXPOS(n) ((uint32_t)(n) << LTDC_CPSR_CXPOS_SHIFT) + +/* LTDC Current Display Status Register */ + +#define LTDC_CDSR_VDES (1 << 0) /* Bit 0: Vertical Data Enable display Status */ +#define LTDC_CDSR_HDES (1 << 1) /* Bit 1: Horizontal Data Enable display Status */ +#define LTDC_CDSR_VSYNCS (1 << 2) /* Bit 2: Vertical Sync display Status */ +#define LTDC_CDSR_HSYNCS (1 << 3) /* Bit 3: Horizontal Sync display Status */ + +/* LTDC Layer x Control Register */ + +#define LTDC_LXCR_LEN (1 << 0) /* Bit 0: Layer Enable */ +#define LTDC_LXCR_COLKEN (1 << 1) /* Bit 1: Color Keying Enable */ +#define LTDC_LXCR_CLUTEN (1 << 4) /* Bit 4: Color Look-Up Table Enable */ + +/* LTDC Layer x Window Horizontal Position Configuration Register */ + +#define LTDC_LXWHPCR_WHSTPOS_SHIFT (0) /* Bits 0-11: Window Horizontal Start Position */ +#define LTDC_LXWHPCR_WHSTPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSTPOS_SHIFT) +# define LTDC_LXWHPCR_WHSTPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSTPOS_SHIFT) +#define LTDC_LXWHPCR_WHSPPOS_SHIFT (16) /* Bits 16-27: Window Horizontal Stop Position */ +#define LTDC_LXWHPCR_WHSPPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSPPOS_SHIFT) +# define LTDC_LXWHPCR_WHSPPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSPPOS_SHIFT) + +/* LTDC Layer x Window Vertical Position Configuration Register */ + +#define LTDC_LXWVPCR_WVSTPOS_SHIFT (0) /* Bits 0-10: Window Vertical Start Position */ +#define LTDC_LXWVPCR_WVSTPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSTPOS_SHIFT) +# define LTDC_LXWVPCR_WVSTPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSTPOS_SHIFT) +#define LTDC_LXWVPCR_WVSPPOS_SHIFT (16) /* Bits 16-26: Window Vertical Stop Position */ +#define LTDC_LXWVPCR_WVSPPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSPPOS_SHIFT) +# define LTDC_LXWVPCR_WVSPPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSPPOS_SHIFT) + +/* LTDC Layer x Color Keying Configuration Register */ + +#define LTDC_LXCKCR_CKBLUE_SHIFT (0) /* Bits 0-7: Color Key Blue Value */ +#define LTDC_LXCKCR_CKBLUE_MASK (0xff << LTDC_LXCKCR_CKBLUE_SHIFT) +# define LTDC_LXCKCR_CKBLUE(n) ((uint32_t)(n) << LTDC_LXCKCR_CKBLUE_SHIFT) +#define LTDC_LXCKCR_CKGREEN_SHIFT (8) /* Bits 8-15: Color Key Green Value */ +#define LTDC_LXCKCR_CKGREEN_MASK (0xff << LTDC_LXCKCR_CKGREEN_SHIFT) +# define LTDC_LXCKCR_CKGREEN(n) ((uint32_t)(n) << LTDC_LXCKCR_CKGREEN_SHIFT) +#define LTDC_LXCKCR_CKRED_SHIFT (16) /* Bits 16-23: Color Key Red Value */ +#define LTDC_LXCKCR_CKRED_MASK (0xff << LTDC_LXCKCR_CKRED_SHIFT) +# define LTDC_LXCKCR_CKRED(n) ((uint32_t)(n) << LTDC_LXCKCR_CKRED_SHIFT) + +/* LTDC Layer x Pixel Format Configuration Register */ + +#define LTDC_LXPFCR_PF_SHIFT (0) /* Bits 0-2: Pixel Format */ +#define LTDC_LXPFCR_PF_MASK (0x7 << LTDC_LXPFCR_PF_SHIFT) +# define LTDC_LXPFCR_PF(n) ((uint32_t)(n) << LTDC_LXPFCR_PF_SHIFT) + +#define LTDC_PF_ARGB8888 0 +#define LTDC_PF_RGB888 1 +#define LTDC_PF_RGB565 2 +#define LTDC_PF_ARGB1555 3 +#define LTDC_PF_ARGB4444 4 +#define LTDC_PF_L8 5 /* 8-bit Luninance (CLUT lookup) */ +#define LTDC_PF_AL44 6 /* 4-bit Alpha, 4-bit Luminance */ +#define LTDC_PF_AL88 7 /* 8-bit Alpha, 8-bit Luminance */ + +/* LTDC Layer x Constant Alpha Configuration Register */ + +#define LTDC_LXCACR_CONSTA_SHIFT (0) /* Bits 0-7: Constant Alpha */ +#define LTDC_LXCACR_CONSTA_MASK (0x7 << LTDC_LXCACR_CONSTA_SHIFT) +# define LTDC_LXCACR_CONSTA(n) ((uint32_t)(n) << LTDC_LXCACR_CONSTA_SHIFT) + +/* LTDC Layer x Default Color Configuration Register */ + +#define LTDC_LXDCCR_DCBLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ +#define LTDC_LXDCCR_DCBLUE_MASK (0xff << LTDC_LXDCCR_DCBLUE_SHIFT) +# define LTDC_LXDCCR_DCBLUE(n) ((uint32_t)(n) << LTDC_LXDCCR_DCBLUE_SHIFT) +#define LTDC_LXDCCR_DCGREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ +#define LTDC_LXDCCR_DCGREEN_MASK (0xff << LTDC_LXDCCR_DCGREEN_SHIFT) +# define LTDC_LXDCCR_DCGREEN(n) ((uint32_t)(n) << LTDC_LXDCCR_DCGREEN_SHIFT) +#define LTDC_LXDCCR_DCRED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ +#define LTDC_LXDCCR_DCRED_MASK (0xff << LTDC_LXDCCR_DCRED_SHIFT) +# define LTDC_LXDCCR_DCRED(n) ((uint32_t)(n) << LTDC_LXDCCR_DCRED_SHIFT) +#define LTDC_LXDCCR_DCALPHA_SHIFT (24) /* Bits 24-31: Default Color Alpha Value */ +#define LTDC_LXDCCR_DCALPHA_MASK (0xff << LTDC_LXDCCR_DCALPHA_SHIFT) +# define LTDC_LXDCCR_DCALPHA(n) ((uint32_t)(n) << LTDC_LXDCCR_DCALPHA_SHIFT) + +/* LTDC Layer x Blending Factors Configuration Register */ + +#define LTDC_LXBFCR_BF2_SHIFT (0) /* Bits 0-2: Blending Factor 2 */ +#define LTDC_LXBFCR_BF2_MASK (0x7 << LTDC_LXBFCR_BF2_SHIFT) +# define LTDC_LXBFCR_BF2(n) ((uint32_t)(n) << LTDC_LXBFCR_BF2_SHIFT) +#define LTDC_LXBFCR_BF1_SHIFT (8) /* Bits 8-10: Blending Factor 1 */ +#define LTDC_LXBFCR_BF1_MASK (0x7 << LTDC_LXBFCR_BF1_SHIFT) +# define LTDC_LXBFCR_BF1(n) ((uint32_t)(n) << LTDC_LXBFCR_BF1_SHIFT) + +#define LTDC_BF1_CONST_ALPHA 0x04 /* Constant Alpha */ +#define LTDC_BF1_PIXEL_ALPHA 0x06 /* Pixel Alpha x Constant Alpha */ +#define LTDC_BF2_CONST_ALPHA 0x05 /* Constant Alpha */ +#define LTDC_BF2_PIXEL_ALPHA 0x07 /* Pixel Alpha x Constant Alpha */ + +/* LTDC Layer x Color Frame Buffer Length Configuration Register */ + +#define LTDC_LXCFBLR_CFBLL_SHIFT (0) /* Bits 0-12: Color Frame Buffer Line Length */ +#define LTDC_LXCFBLR_CFBLL_MASK (0x1fff << LTDC_LXCFBLR_CFBLL_SHIFT) +# define LTDC_LXCFBLR_CFBLL(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBLL_SHIFT) +#define LTDC_LXCFBLR_CFBP_SHIFT (16) /* Bits 16-28: Color Frame Buffer Pitch */ +#define LTDC_LXCFBLR_CFBP_MASK (0x1fff << LTDC_LXCFBLR_CFBP_SHIFT) +# define LTDC_LXCFBLR_CFBP(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBP_SHIFT) + +/* LTDC Layer x Color Frame Buffer Line Number Register */ + +#define LTDC_LXCFBLNR_LN_SHIFT (0) /* Bits 0-10: Color Frame Buffer Line Number */ +#define LTDC_LXCFBLNR_LN_MASK (0x7ff << LTDC_LXCFBLNR_LN_SHIFT) +# define LTDC_LXCFBLNR_LN(n) ((uint32_t)(n) << LTDC_LXCFBLNR_LN_SHIFT) + +/* LTDC Layer x CLUT Write Register */ + +#define LTDC_LXCLUTWR_BLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ +#define LTDC_LXCLUTWR_BLUE_MASK (0xff << LTDC_LXCLUTWR_BLUE_SHIFT) +# define LTDC_LXCLUTWR_BLUE(n) ((uint32_t)(n) << LTDC_LXCLUTWR_BLUE_SHIFT) +#define LTDC_LXCLUTWR_GREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ +#define LTDC_LXCLUTWR_GREEN_MASK (0xff << LTDC_LXCLUTWR_GREEN_SHIFT) +# define LTDC_LXCLUTWR_GREEN(n) ((uint32_t)(n) << LTDC_LXCLUTWR_GREEN_SHIFT) +#define LTDC_LXCLUTWR_RED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ +#define LTDC_LXCLUTWR_RED_MASK (0xff << LTDC_LXCLUTWR_RED_SHIFT) +# define LTDC_LXCLUTWR_RED(n) ((uint32_t)(n) << LTDC_LXCLUTWR_RED_SHIFT) +#define LTDC_LXCLUTWR_CLUTADD_SHIFT (24) /* Bits 24-31: CLUT Address */ +#define LTDC_LXCLUTWR_CLUTADD_MASK (0xff << LTDC_LXCLUTWR_CLUTADD_SHIFT) +# define LTDC_LXCLUTWR_CLUTADD(n) ((uint32_t)(n) << LTDC_LXCLUTWR_CLUTADD_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_otghs.h b/arch/arm/src/common/stm32/hardware/stm32_otghs.h new file mode 100644 index 0000000000000..42e0fdab7c677 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_otghs.h @@ -0,0 +1,1111 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_otghs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General definitions */ + +#define OTGHS_EPTYPE_CTRL (0) /* Control */ +#define OTGHS_EPTYPE_ISOC (1) /* Isochronous */ +#define OTGHS_EPTYPE_BULK (2) /* Bulk */ +#define OTGHS_EPTYPE_INTR (3) /* Interrupt */ + +#define OTGHS_PID_DATA0 (0) +#define OTGHS_PID_DATA2 (1) +#define OTGHS_PID_DATA1 (2) +#define OTGHS_PID_MDATA (3) /* Non-control */ +#define OTGHS_PID_SETUP (3) /* Control */ + +/* Register Offsets *********************************************************/ + +/* Core global control and status registers */ + +#define STM32_OTGHS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGHS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGHS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGHS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGHS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGHS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGHS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGHS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGHS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGHS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGHS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGHS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGHS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGHS_GCCFG_OFFSET 0x0038 /* general core configuration register */ +#define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ +#define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ +#define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ + +/* Host-mode control and status registers */ + +#define STM32_OTGHS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGHS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGHS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGHS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGHS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGHS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGHS_HPRT_OFFSET 0x0440 /* Host port control and status register */ + +#define STM32_OTGHS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGHS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGHS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGHS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGHS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ + +#define STM32_OTGHS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGHS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ +#define STM32_OTGHS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ +#define STM32_OTGHS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ +#define STM32_OTGHS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ +#define STM32_OTGHS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ +#define STM32_OTGHS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ +#define STM32_OTGHS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ +#define STM32_OTGHS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ +#define STM32_OTGHS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ +#define STM32_OTGHS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ +#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ +#define STM32_OTGHS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ + +#define STM32_OTGHS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGHS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ +#define STM32_OTGHS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ +#define STM32_OTGHS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ +#define STM32_OTGHS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ +#define STM32_OTGHS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ +#define STM32_OTGHS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ +#define STM32_OTGHS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ +#define STM32_OTGHS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ +#define STM32_OTGHS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */ +#define STM32_OTGHS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */ +#define STM32_OTGHS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */ +#define STM32_OTGHS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */ + +#define STM32_OTGHS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGHS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */ +#define STM32_OTGHS_HCINTMSK11_OFFSET 0x068c /* Host channel-11 interrupt mask register */ + +#define STM32_OTGHS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGHS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ +#define STM32_OTGHS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ +#define STM32_OTGHS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ +#define STM32_OTGHS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ +#define STM32_OTGHS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ +#define STM32_OTGHS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ +#define STM32_OTGHS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ +#define STM32_OTGHS_HCTSIZ7_OFFSET 0x06f0 /* Host channel-7 interrupt register */ +#define STM32_OTGHS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */ +#define STM32_OTGHS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */ +#define STM32_OTGHS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */ +#define STM32_OTGHS_HCTSIZ11_OFFSET 0x05f0 /* Host channel-11 interrupt register */ + +/* Device-mode control and status registers */ + +#define STM32_OTGHS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGHS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGHS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGHS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGHS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGHS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGHS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGHS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ + +#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGHS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ + +#define STM32_OTGHS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGHS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ +#define STM32_OTGHS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ +#define STM32_OTGHS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ +#define STM32_OTGHS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ + +#define STM32_OTGHS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGHS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ +#define STM32_OTGHS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ +#define STM32_OTGHS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ +#define STM32_OTGHS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGHS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGHS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ +#define STM32_OTGHS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ + +#define STM32_OTGHS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGHS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ +#define STM32_OTGHS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ + +#define STM32_OTGHS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGHS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGHS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ + +#define STM32_OTGHS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGHS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ +#define STM32_OTGHS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ +#define STM32_OTGHS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ +#define STM32_OTGHS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ + +#define STM32_OTGHS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGHS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ +#define STM32_OTGHS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ +#define STM32_OTGHS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ +#define STM32_OTGHS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGHS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGHS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ +#define STM32_OTGHS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ + +/* Power and clock gating registers */ + +#define STM32_OTGHS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGHS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGHS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) + +#define STM32_OTGHS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ + +#define STM32_OTGHS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ +#define STM32_OTGHS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ + +/* Register Addresses *******************************************************/ + +#define STM32_OTGHS_GOTGCTL (STM32_OTGHS_BASE+STM32_OTGHS_GOTGCTL_OFFSET) +#define STM32_OTGHS_GOTGINT (STM32_OTGHS_BASE+STM32_OTGHS_GOTGINT_OFFSET) +#define STM32_OTGHS_GAHBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GAHBCFG_OFFSET) +#define STM32_OTGHS_GUSBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GUSBCFG_OFFSET) +#define STM32_OTGHS_GRSTCTL (STM32_OTGHS_BASE+STM32_OTGHS_GRSTCTL_OFFSET) +#define STM32_OTGHS_GINTSTS (STM32_OTGHS_BASE+STM32_OTGHS_GINTSTS_OFFSET) +#define STM32_OTGHS_GINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_GINTMSK_OFFSET) +#define STM32_OTGHS_GRXSTSR (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSR_OFFSET) +#define STM32_OTGHS_GRXSTSP (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSP_OFFSET) +#define STM32_OTGHS_GRXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_GRXFSIZ_OFFSET) +#define STM32_OTGHS_HNPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXFSIZ_OFFSET) +#define STM32_OTGHS_DIEPTXF0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF0_OFFSET) +#define STM32_OTGHS_HNPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXSTS_OFFSET) +#define STM32_OTGHS_GCCFG (STM32_OTGHS_BASE+STM32_OTGHS_GCCFG_OFFSET) +#define STM32_OTGHS_CID (STM32_OTGHS_BASE+STM32_OTGHS_CID_OFFSET) +#define STM32_OTGHS_HPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HPTXFSIZ_OFFSET) + +#define STM32_OTGHS_DIEPTXF(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF_OFFSET(n)) +#define STM32_OTGHS_DIEPTXF1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF1_OFFSET) +#define STM32_OTGHS_DIEPTXF2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF2_OFFSET) +#define STM32_OTGHS_DIEPTXF3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF3_OFFSET) + +/* Host-mode control and status registers */ + +#define STM32_OTGHS_HCFG (STM32_OTGHS_BASE+STM32_OTGHS_HCFG_OFFSET) +#define STM32_OTGHS_HFIR (STM32_OTGHS_BASE+STM32_OTGHS_HFIR_OFFSET) +#define STM32_OTGHS_HFNUM (STM32_OTGHS_BASE+STM32_OTGHS_HFNUM_OFFSET) +#define STM32_OTGHS_HPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HPTXSTS_OFFSET) +#define STM32_OTGHS_HAINT (STM32_OTGHS_BASE+STM32_OTGHS_HAINT_OFFSET) +#define STM32_OTGHS_HAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_HAINTMSK_OFFSET) +#define STM32_OTGHS_HPRT (STM32_OTGHS_BASE+STM32_OTGHS_HPRT_OFFSET) + +#define STM32_OTGHS_CHAN(n) (STM32_OTGHS_BASE+STM32_OTGHS_CHAN_OFFSET(n)) + +#define STM32_OTGHS_HCCHAR(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR_OFFSET(n)) +#define STM32_OTGHS_HCCHAR0 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR0_OFFSET) +#define STM32_OTGHS_HCCHAR1 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR1_OFFSET) +#define STM32_OTGHS_HCCHAR2 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR2_OFFSET) +#define STM32_OTGHS_HCCHAR3 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR3_OFFSET) +#define STM32_OTGHS_HCCHAR4 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR4_OFFSET) +#define STM32_OTGHS_HCCHAR5 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR5_OFFSET) +#define STM32_OTGHS_HCCHAR6 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR6_OFFSET) +#define STM32_OTGHS_HCCHAR7 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR7_OFFSET) +#define STM32_OTGHS_HCCHAR8 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR8_OFFSET) +#define STM32_OTGHS_HCCHAR9 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR9_OFFSET) +#define STM32_OTGHS_HCCHAR10 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR10_OFFSET) +#define STM32_OTGHS_HCCHAR11 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR11_OFFSET) + +#define STM32_OTGHS_HCINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINT_OFFSET(n)) +#define STM32_OTGHS_HCINT0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT0_OFFSET) +#define STM32_OTGHS_HCINT1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT1_OFFSET) +#define STM32_OTGHS_HCINT2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT2_OFFSET) +#define STM32_OTGHS_HCINT3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT3_OFFSET) +#define STM32_OTGHS_HCINT4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT4_OFFSET) +#define STM32_OTGHS_HCINT5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT5_OFFSET) +#define STM32_OTGHS_HCINT6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT6_OFFSET) +#define STM32_OTGHS_HCINT7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT7_OFFSET) +#define STM32_OTGHS_HCINT8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT8_OFFSET) +#define STM32_OTGHS_HCINT9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT9_OFFSET) +#define STM32_OTGHS_HCINT10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT10_OFFSET) +#define STM32_OTGHS_HCINT11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT11_OFFSET) + +#define STM32_OTGHS_HCINTMSK(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK_OFFSET(n)) +#define STM32_OTGHS_HCINTMSK0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK0_OFFSET) +#define STM32_OTGHS_HCINTMSK1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK1_OFFSET) +#define STM32_OTGHS_HCINTMSK2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK2_OFFSET) +#define STM32_OTGHS_HCINTMSK3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK3_OFFSET) +#define STM32_OTGHS_HCINTMSK4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK4_OFFSET) +#define STM32_OTGHS_HCINTMSK5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK5_OFFSET) +#define STM32_OTGHS_HCINTMSK6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK6_OFFSET) +#define STM32_OTGHS_HCINTMSK7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK7_OFFSET) +#define STM32_OTGHS_HCINTMSK8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK8_OFFSET) +#define STM32_OTGHS_HCINTMSK9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK9_OFFSET) +#define STM32_OTGHS_HCINTMSK10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK10_OFFSET) +#define STM32_OTGHS_HCINTMSK11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK11_OFFSET) + +#define STM32_OTGHS_HCTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ_OFFSET(n)) +#define STM32_OTGHS_HCTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ0_OFFSET) +#define STM32_OTGHS_HCTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ1_OFFSET) +#define STM32_OTGHS_HCTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ2_OFFSET) +#define STM32_OTGHS_HCTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ3_OFFSET) +#define STM32_OTGHS_HCTSIZ4 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ4_OFFSET) +#define STM32_OTGHS_HCTSIZ5 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ5_OFFSET) +#define STM32_OTGHS_HCTSIZ6 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ6_OFFSET) +#define STM32_OTGHS_HCTSIZ7 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ7_OFFSET) +#define STM32_OTGHS_HCTSIZ8 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ8_OFFSET) +#define STM32_OTGHS_HCTSIZ9 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ9_OFFSET) +#define STM32_OTGHS_HCTSIZ10 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ10_OFFSET) +#define STM32_OTGHS_HCTSIZ11 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ11_OFFSET) + +/* Device-mode control and status registers */ + +#define STM32_OTGHS_DCFG (STM32_OTGHS_BASE+STM32_OTGHS_DCFG_OFFSET) +#define STM32_OTGHS_DCTL (STM32_OTGHS_BASE+STM32_OTGHS_DCTL_OFFSET) +#define STM32_OTGHS_DSTS (STM32_OTGHS_BASE+STM32_OTGHS_DSTS_OFFSET) +#define STM32_OTGHS_DIEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPMSK_OFFSET) +#define STM32_OTGHS_DOEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DOEPMSK_OFFSET) +#define STM32_OTGHS_DAINT (STM32_OTGHS_BASE+STM32_OTGHS_DAINT_OFFSET) +#define STM32_OTGHS_DAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_DAINTMSK_OFFSET) +#define STM32_OTGHS_DVBUSDIS (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSDIS_OFFSET) +#define STM32_OTGHS_DVBUSPULSE (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSPULSE_OFFSET) +#define STM32_OTGHS_DIEPEMPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPEMPMSK_OFFSET) + +#define STM32_OTGHS_DIEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEP_OFFSET(n)) + +#define STM32_OTGHS_DIEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL_OFFSET(n)) +#define STM32_OTGHS_DIEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL0_OFFSET) +#define STM32_OTGHS_DIEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL1_OFFSET) +#define STM32_OTGHS_DIEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL2_OFFSET) +#define STM32_OTGHS_DIEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL3_OFFSET) + +#define STM32_OTGHS_DIEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT_OFFSET(n)) +#define STM32_OTGHS_DIEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT0_OFFSET) +#define STM32_OTGHS_DIEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT1_OFFSET) +#define STM32_OTGHS_DIEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT2_OFFSET) +#define STM32_OTGHS_DIEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT3_OFFSET) + +#define STM32_OTGHS_DIEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGHS_DIEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ0_OFFSET) +#define STM32_OTGHS_DIEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ1_OFFSET) +#define STM32_OTGHS_DIEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ2_OFFSET) +#define STM32_OTGHS_DIEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ3_OFFSET) + +#define STM32_OTGHS_DTXFSTS(n) (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS_OFFSET(n)) +#define STM32_OTGHS_DTXFSTS0 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS0_OFFSET) +#define STM32_OTGHS_DTXFSTS1 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS1_OFFSET) +#define STM32_OTGHS_DTXFSTS2 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS2_OFFSET) +#define STM32_OTGHS_DTXFSTS3 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS3_OFFSET) + +#define STM32_OTGHS_DOEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEP_OFFSET(n)) + +#define STM32_OTGHS_DOEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL_OFFSET(n)) +#define STM32_OTGHS_DOEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL0_OFFSET) +#define STM32_OTGHS_DOEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL1_OFFSET) +#define STM32_OTGHS_DOEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL2_OFFSET) +#define STM32_OTGHS_DOEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL3_OFFSET) + +#define STM32_OTGHS_DOEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT_OFFSET(n)) +#define STM32_OTGHS_DOEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT0_OFFSET) +#define STM32_OTGHS_DOEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT1_OFFSET) +#define STM32_OTGHS_DOEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT2_OFFSET) +#define STM32_OTGHS_DOEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT3_OFFSET) + +#define STM32_OTGHS_DOEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGHS_DOEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ0_OFFSET) +#define STM32_OTGHS_DOEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ1_OFFSET) +#define STM32_OTGHS_DOEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ2_OFFSET) +#define STM32_OTGHS_DOEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ3_OFFSET) + +/* Power and clock gating registers */ + +#define STM32_OTGHS_PCGCCTL (STM32_OTGHS_BASE+STM32_OTGHS_PCGCCTL_OFFSET) + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGHS_DFIFO_DEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGHS_DFIFO_HCH(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH_OFFSET(n)) + +#define STM32_OTGHS_DFIFO_DEP0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP0_OFFSET) +#define STM32_OTGHS_DFIFO_HCH0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH0_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP1_OFFSET) +#define STM32_OTGHS_DFIFO_HCH1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH1_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP2_OFFSET) +#define STM32_OTGHS_DFIFO_HCH2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH2_OFFSET) + +#define STM32_OTGHS_DFIFO_DEP3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP3_OFFSET) +#define STM32_OTGHS_DFIFO_HCH3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Core global control and status registers */ + +/* Control and status register */ + +#define OTGHS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ +#define OTGHS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ + /* Bits 2-72 Reserved, must be kept at reset value */ +#define OTGHS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ +#define OTGHS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ +#define OTGHS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ +#define OTGHS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ + /* Bits 12-15: Reserved, must be kept at reset value */ +#define OTGHS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ +#define OTGHS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ +#define OTGHS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ +#define OTGHS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* Interrupt register */ + +/* Bits 1:0 Reserved, + * must be kept at reset value + */ +#define OTGHS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ + /* Bits 3-7: Reserved, must be kept at reset value */ +#define OTGHS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ +#define OTGHS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ + /* Bits 16:10 Reserved, must be kept at reset value */ +#define OTGHS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ +#define OTGHS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ +#define OTGHS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ + /* Bits 2-31: Reserved, must be kept at reset value */ + +/* AHB configuration register */ + +#define OTGHS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ + /* Bits 1-6: Reserved, must be kept at reset value */ +#define OTGHS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ +#define OTGHS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* USB configuration register */ + +#define OTGHS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ +#define OTGHS_GUSBCFG_TOCAL_MASK (7 << OTGHS_GUSBCFG_TOCAL_SHIFT) + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ +#define OTGHS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ +#define OTGHS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ +#define OTGHS_GUSBCFG_TRDT_MASK (15 << OTGHS_GUSBCFG_TRDT_SHIFT) +# define OTGHS_GUSBCFG_TRDT(n) ((n) << OTGHS_GUSBCFG_TRDT_SHIFT) + /* Bits 14-28: Reserved, must be kept at reset value */ +#define OTGHS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ +#define OTGHS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ +#define OTGHS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* Reset register */ + +#define OTGHS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ +#define OTGHS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ +#define OTGHS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ + /* Bit 3 Reserved, must be kept at reset value */ +#define OTGHS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ +#define OTGHS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ +#define OTGHS_GRSTCTL_TXFNUM_SHIFT (10) /* Bits 6-10: TxFIFO number */ +#define OTGHS_GRSTCTL_TXFNUM_MASK (31 << OTGHS_GRSTCTL_TXFNUM_SHIFT) +# define OTGHS_GRSTCTL_TXFNUM_HNONPER (0 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ +# define OTGHS_GRSTCTL_TXFNUM_HPER (1 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ +# define OTGHS_GRSTCTL_TXFNUM_HALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ +# define OTGHS_GRSTCTL_TXFNUM_D(n) ((n) << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ +# define OTGHS_GRSTCTL_TXFNUM_DALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ + +/* Bits 11-31: Reserved, + * must be kept at reset value + */ +#define OTGHS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ + +/* Core interrupt and Interrupt mask registers */ + +#define OTGHS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ +# define OTGHS_GINTSTS_DEVMODE (0) +# define OTGHS_GINTSTS_HOSTMODE (OTGHS_GINTSTS_CMOD) +#define OTGHS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ +#define OTGHS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ +#define OTGHS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ +#define OTGHS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ +#define OTGHS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ +#define OTGHS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ +#define OTGHS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ + /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTGHS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ +#define OTGHS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ +#define OTGHS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ +#define OTGHS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ +#define OTGHS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ +#define OTGHS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ + /* Bits 16 Reserved, must be kept at reset value */ +#define OTGHS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ +#define OTGHS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ +#define OTGHS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ +#define OTGHS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ +#define OTGHS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer */ +#define OTGHS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ + /* Bits 22-23: Reserved, must be kept at reset value */ +#define OTGHS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ +#define OTGHS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ +#define OTGHS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ + /* Bit 27 Reserved, must be kept at reset value */ +#define OTGHS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ +#define OTGHS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ +#define OTGHS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ +#define OTGHS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ + +/* Receive status debug read/OTG status read and pop registers (host mode) */ + +#define OTGHS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ +#define OTGHS_GRXSTSH_CHNUM_MASK (15 << OTGHS_GRXSTSH_CHNUM_SHIFT) +#define OTGHS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGHS_GRXSTSH_BCNT_MASK (0x7ff << OTGHS_GRXSTSH_BCNT_SHIFT) +#define OTGHS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGHS_GRXSTSH_DPID_MASK (3 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA0 (0 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA2 (1 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_DATA1 (2 << OTGHS_GRXSTSH_DPID_SHIFT) +# define OTGHS_GRXSTSH_DPID_MDATA (3 << OTGHS_GRXSTSH_DPID_SHIFT) +#define OTGHS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGHS_GRXSTSH_PKTSTS_MASK (15 << OTGHS_GRXSTSH_PKTSTS_SHIFT) +# define OTGHS_GRXSTSH_PKTSTS_INRECVD (2 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ +# define OTGHS_GRXSTSH_PKTSTS_INDONE (3 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ +# define OTGHS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ +# define OTGHS_GRXSTSH_PKTSTS_HALTED (7 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ + +/* Bits 21-31: Reserved, + * must be kept at reset value + */ + +/* Receive status debug read/OTG status read and pop registers + * (device mode) + */ + +#define OTGHS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ +#define OTGHS_GRXSTSD_EPNUM_MASK (15 << OTGHS_GRXSTSD_EPNUM_SHIFT) +#define OTGHS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGHS_GRXSTSD_BCNT_MASK (0x7ff << OTGHS_GRXSTSD_BCNT_SHIFT) +#define OTGHS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGHS_GRXSTSD_DPID_MASK (3 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA0 (0 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA2 (1 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_DATA1 (2 << OTGHS_GRXSTSD_DPID_SHIFT) +# define OTGHS_GRXSTSD_DPID_MDATA (3 << OTGHS_GRXSTSD_DPID_SHIFT) +#define OTGHS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGHS_GRXSTSD_PKTSTS_MASK (15 << OTGHS_GRXSTSD_PKTSTS_SHIFT) +# define OTGHS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ +# define OTGHS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ +# define OTGHS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ +# define OTGHS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ +# define OTGHS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ + +#define OTGHS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ +#define OTGHS_GRXSTSD_FRMNUM_MASK (15 << OTGHS_GRXSTSD_FRMNUM_SHIFT) + /* Bits 25-31: Reserved, must be kept at reset value */ + +/* Receive FIFO size register */ + +#define OTGHS_GRXFSIZ_MASK (0xffff) + +/* Host non-periodic transmit FIFO size register */ + +#define OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ +#define OTGHS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT) +#define OTGHS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ +#define OTGHS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGHS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGHS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) + +/* Endpoint 0 Transmit FIFO size */ + +#define OTGHS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ +#define OTGHS_DIEPTXF0_TX0FD_MASK (0xffff << OTGHS_DIEPTXF0_TX0FD_SHIFT) +#define OTGHS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ +#define OTGHS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGHS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGHS_DIEPTXF0_TX0FSA_MIN (16 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGHS_DIEPTXF0_TX0FSA_MAX (256 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) + +/* Non-periodic transmit FIFO/queue status register */ + +#define OTGHS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ +#define OTGHS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) +# define OTGHS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) +#define OTGHS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ +#define OTGHS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) +# define OTGHS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) +#define OTGHS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ +#define OTGHS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGHS_HNPTXSTS_NPTXQTOP_SHIFT) +# define OTGHS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGHS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ +# define OTGHS_HNPTXSTS_TYPE_MASK (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) +# define OTGHS_HNPTXSTS_TYPE_INOUT (0 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGHS_HNPTXSTS_TYPE_ZLP (1 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ +# define OTGHS_HNPTXSTS_TYPE_HALT (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ + +# define OTGHS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGHS_HNPTXSTS_CHNUM_MASK (15 << OTGHS_HNPTXSTS_CHNUM_SHIFT) +# define OTGHS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGHS_HNPTXSTS_EPNUM_MASK (15 << OTGHS_HNPTXSTS_EPNUM_SHIFT) + /* Bit 31 Reserved, must be kept at reset value */ + +/* General core configuration register */ + +/* Bits 15:0 Reserved, + * must be kept at reset value + */ +#define OTGHS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ + /* Bit 17 Reserved, must be kept at reset value */ +#define OTGHS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing “A” device */ +#define OTGHS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing “B” device */ +#define OTGHS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ +#define OTGHS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ + /* Bits 31:22 Reserved, must be kept at reset value */ + +/* Core ID register (32-bit product ID) */ + +/* Host periodic transmit FIFO size register */ + +#define OTGHS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ +#define OTGHS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGHS_HPTXFSIZ_PTXSA_SHIFT) +#define OTGHS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ +#define OTGHS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGHS_HPTXFSIZ_PTXFD_SHIFT) + +/* Device IN endpoint transmit FIFOn size register */ + +#define OTGHS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ +#define OTGHS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGHS_DIEPTXF_INEPTXSA_SHIFT) +#define OTGHS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ +#define OTGHS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGHS_DIEPTXF_INEPTXFD_SHIFT) +# define OTGHS_DIEPTXF_INEPTXFD_MIN (16 << OTGHS_DIEPTXF_INEPTXFD_MASK) + +/* Host-mode control and status registers */ + +/* Host configuration register */ + +#define OTGHS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ +#define OTGHS_HCFG_FSLSPCS_MASK (3 << OTGHS_HCFG_FSLSPCS_SHIFT) +# define OTGHS_HCFG_FSLSPCS_FS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ +# define OTGHS_HCFG_FSLSPCS_LS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ +# define OTGHS_HCFG_FSLSPCS_LS6MHz (2 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ + +#define OTGHS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ + /* Bits 31:3 Reserved, must be kept at reset value */ + +/* Host frame interval register */ + +#define OTGHS_HFIR_MASK (0xffff) + +/* Host frame number/frame time remaining register */ + +#define OTGHS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ +#define OTGHS_HFNUM_FRNUM_MASK (0xffff << OTGHS_HFNUM_FRNUM_SHIFT) +#define OTGHS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ +#define OTGHS_HFNUM_FTREM_MASK (0xffff << OTGHS_HFNUM_FTREM_SHIFT) + +/* Host periodic transmit FIFO/queue status register */ + +#define OTGHS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ +#define OTGHS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) +# define OTGHS_HPTXSTS_PTXFSAVL_FULL (0 << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) +#define OTGHS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ +#define OTGHS_HPTXSTS_PTXQSAV_MASK (0xff << OTGHS_HPTXSTS_PTXQSAV_SHIFT) +# define OTGHS_HPTXSTS_PTXQSAV_FULL (0 << OTGHS_HPTXSTS_PTXQSAV_SHIFT) +#define OTGHS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ +#define OTGHS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGHS_HPTXSTS_PTXQTOP_SHIFT) +# define OTGHS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGHS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ +# define OTGHS_HPTXSTS_TYPE_MASK (3 << OTGHS_HPTXSTS_TYPE_SHIFT) +# define OTGHS_HPTXSTS_TYPE_INOUT (0 << OTGHS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGHS_HPTXSTS_TYPE_ZLP (1 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ +# define OTGHS_HPTXSTS_TYPE_HALT (3 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ + +# define OTGHS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGHS_HPTXSTS_EPNUM_MASK (15 << OTGHS_HPTXSTS_EPNUM_SHIFT) +# define OTGHS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGHS_HPTXSTS_CHNUM_MASK (15 << OTGHS_HPTXSTS_CHNUM_SHIFT) +# define OTGHS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ + +/* Host all channels interrupt and all channels interrupt mask registers */ + +#define OTGHS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ + +/* Host port control and status register */ + +#define OTGHS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ +#define OTGHS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ +#define OTGHS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ +#define OTGHS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ +#define OTGHS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ +#define OTGHS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ +#define OTGHS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ +#define OTGHS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ +#define OTGHS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ + /* Bit 9: Reserved, must be kept at reset value */ +#define OTGHS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ +#define OTGHS_HPRT_PLSTS_MASK (3 << OTGHS_HPRT_PLSTS_SHIFT) +# define OTGHS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ +# define OTGHS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ +#define OTGHS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ +#define OTGHS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ +#define OTGHS_HPRT_PTCTL_MASK (15 << OTGHS_HPRT_PTCTL_SHIFT) +# define OTGHS_HPRT_PTCTL_DISABLED (0 << OTGHS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ +# define OTGHS_HPRT_PTCTL_J (1 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_J mode */ +# define OTGHS_HPRT_PTCTL_L (2 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_K mode */ +# define OTGHS_HPRT_PTCTL_SE0_NAK (3 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGHS_HPRT_PTCTL_PACKET (4 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ +# define OTGHS_HPRT_PTCTL_FORCE (5 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGHS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ +#define OTGHS_HPRT_PSPD_MASK (3 << OTGHS_HPRT_PSPD_SHIFT) +# define OTGHS_HPRT_PSPD_FS (1 << OTGHS_HPRT_PSPD_SHIFT) /* Full speed */ +# define OTGHS_HPRT_PSPD_LS (2 << OTGHS_HPRT_PSPD_SHIFT) /* Low speed */ + +/* Bits 19-31: Reserved, + * must be kept at reset value + */ + +/* Host channel-n characteristics register */ + +#define OTGHS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_HCCHAR_MPSIZ_MASK (0x7ff << OTGHS_HCCHAR_MPSIZ_SHIFT) +#define OTGHS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ +#define OTGHS_HCCHAR_EPNUM_MASK (15 << OTGHS_HCCHAR_EPNUM_SHIFT) +#define OTGHS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ +# define OTGHS_HCCHAR_EPDIR_OUT (0) +# define OTGHS_HCCHAR_EPDIR_IN OTGHS_HCCHAR_EPDIR + /* Bit 16 Reserved, must be kept at reset value */ +#define OTGHS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ +#define OTGHS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_HCCHAR_EPTYP_MASK (3 << OTGHS_HCCHAR_EPTYP_SHIFT) +# define OTGHS_HCCHAR_EPTYP_CTRL (0 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Control */ +# define OTGHS_HCCHAR_EPTYP_ISOC (1 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_HCCHAR_EPTYP_BULK (2 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_HCCHAR_EPTYP_INTR (3 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ + +#define OTGHS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ +#define OTGHS_HCCHAR_MCNT_MASK (3 << OTGHS_HCCHAR_MCNT_SHIFT) +#define OTGHS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ +#define OTGHS_HCCHAR_DAD_MASK (0x7f << OTGHS_HCCHAR_DAD_SHIFT) +#define OTGHS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ +#define OTGHS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ +#define OTGHS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ + +/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ + +#define OTGHS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ +#define OTGHS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ +#define OTGHS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ +#define OTGHS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ +#define OTGHS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ +#define OTGHS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ +#define OTGHS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ +#define OTGHS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ +#define OTGHS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ + /* Bits 11-31 Reserved, must be kept at reset value */ + +/* Host channel-n interrupt register */ + +#define OTGHS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_HCTSIZ_XFRSIZ_SHIFT) +#define OTGHS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ +#define OTGHS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGHS_HCTSIZ_PKTCNT_SHIFT) +#define OTGHS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ +#define OTGHS_HCTSIZ_DPID_MASK (3 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA0 (0 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA2 (1 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_DATA1 (2 << OTGHS_HCTSIZ_DPID_SHIFT) +# define OTGHS_HCTSIZ_DPID_MDATA (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Non-control */ +# define OTGHS_HCTSIZ_PID_SETUP (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Control */ + +/* Bit 31 Reserved, + * must be kept at reset value + */ + +/* Device-mode control and status registers */ + +/* Device configuration register */ + +#define OTGHS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ +#define OTGHS_DCFG_DSPD_MASK (3 << OTGHS_DCFG_DSPD_SHIFT) +# define OTGHS_DCFG_DSPD_FS (3 << OTGHS_DCFG_DSPD_SHIFT) /* Full speed */ + +#define OTGHS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ + /* Bit 3: Reserved, must be kept at reset value */ +#define OTGHS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ +#define OTGHS_DCFG_DAD_MASK (0x7f << OTGHS_DCFG_DAD_SHIFT) +#define OTGHS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ +#define OTGHS_DCFG_PFIVL_MASK (3 << OTGHS_DCFG_PFIVL_SHIFT) +# define OTGHS_DCFG_PFIVL_80PCT (0 << OTGHS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ +# define OTGHS_DCFG_PFIVL_85PCT (1 << OTGHS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ +# define OTGHS_DCFG_PFIVL_90PCT (2 << OTGHS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ +# define OTGHS_DCFG_PFIVL_95PCT (3 << OTGHS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ + +/* Bits 13-31 Reserved, + * must be kept at reset value + */ + +/* Device control register */ + +#define OTGHS_TESTMODE_DISABLED (0) /* Test mode disabled */ +#define OTGHS_TESTMODE_J (1) /* Test_J mode */ +#define OTGHS_TESTMODE_K (2) /* Test_K mode */ +#define OTGHS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ +#define OTGHS_TESTMODE_PACKET (4) /* Test_Packet mode */ +#define OTGHS_TESTMODE_FORCE (5) /* Test_Force_Enable */ + +#define OTGHS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ +#define OTGHS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ +#define OTGHS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ +#define OTGHS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ +#define OTGHS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ +#define OTGHS_DCTL_TCTL_MASK (7 << OTGHS_DCTL_TCTL_SHIFT) +# define OTGHS_DCTL_TCTL_DISABLED (0 << OTGHS_DCTL_TCTL_SHIFT) /* Test mode disabled */ +# define OTGHS_DCTL_TCTL_J (1 << OTGHS_DCTL_TCTL_SHIFT) /* Test_J mode */ +# define OTGHS_DCTL_TCTL_K (2 << OTGHS_DCTL_TCTL_SHIFT) /* Test_K mode */ +# define OTGHS_DCTL_TCTL_SE0_NAK (3 << OTGHS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGHS_DCTL_TCTL_PACKET (4 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ +# define OTGHS_DCTL_TCTL_FORCE (5 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGHS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ +#define OTGHS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ +#define OTGHS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ +#define OTGHS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ +#define OTGHS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ + /* Bits 12-31: Reserved, must be kept at reset value */ + +/* Device status register */ + +#define OTGHS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ +#define OTGHS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ +#define OTGHS_DSTS_ENUMSPD_MASK (3 << OTGHS_DSTS_ENUMSPD_SHIFT) +# define OTGHS_DSTS_ENUMSPD_FS (3 << OTGHS_DSTS_ENUMSPD_MASK) /* Full speed */ + +/* Bits 4-7: Reserved, + * must be kept at reset value + */ +#define OTGHS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ +#define OTGHS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ +#define OTGHS_DSTS_SOFFN_MASK (0x3fff << OTGHS_DSTS_SOFFN_SHIFT) +#define OTGHS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ +#define OTGHS_DSTS_SOFFN_EVEN 0 +#define OTGHS_DSTS_SOFFN_ODD OTGHS_DSTS_SOFFN0 + /* Bits 22-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint common interrupt mask register */ + +#define OTGHS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGHS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ +#define OTGHS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ +#define OTGHS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ +#define OTGHS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint common interrupt mask register */ + +#define OTGHS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGHS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ +#define OTGHS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +/* Device all endpoints interrupt and All endpoints interrupt + * mask registers + */ + +#define OTGHS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTGHS_DAINT_IEP_MASK (0xffff << OTGHS_DAINT_IEP_SHIFT) +# define OTGHS_DAINT_IEP(n) (1 << (n)) +#define OTGHS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ +#define OTGHS_DAINT_OEP_MASK (0xffff << OTGHS_DAINT_OEP_SHIFT) +# define OTGHS_DAINT_OEP(n) (1 << ((n)+16)) + +/* Device VBUS discharge time register */ + +#define OTGHS_DVBUSDIS_MASK (0xffff) + +/* Device VBUS pulsing time register */ + +#define OTGHS_DVBUSPULSE_MASK (0xfff) + +/* Device IN endpoint FIFO empty interrupt mask register */ + +#define OTGHS_DIEPEMPMSK(n) (1 << (n)) + +/* Device control IN endpoint 0 control register */ + +#define OTGHS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGHS_DIEPCTL0_MPSIZ_MASK (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) +# define OTGHS_DIEPCTL0_MPSIZ_64 (0 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_32 (1 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_16 (2 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGHS_DIEPCTL0_MPSIZ_8 (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DIEPCTL0_EPTYP_MASK (3 << OTGHS_DIEPCTL0_EPTYP_SHIFT) +# define OTGHS_DIEPCTL0_EPTYP_CTRL (0 << OTGHS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGHS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGHS_DIEPCTL0_TXFNUM_MASK (15 << OTGHS_DIEPCTL0_TXFNUM_SHIFT) +#define OTGHS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device control IN endpoint n control register */ + +#define OTGHS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DIEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGHS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGHS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ +# define OTGHS_DIEPCTL_EVEN (0) +# define OTGHS_DIEPCTL_ODD OTGHS_DIEPCTL_EONUM +# define OTGHS_DIEPCTL_DATA0 (0) +# define OTGHS_DIEPCTL_DATA1 OTGHS_DIEPCTL_EONUM +#define OTGHS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DIEPCTL_EPTYP_MASK (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) +# define OTGHS_DIEPCTL_EPTYP_CTRL (0 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGHS_DIEPCTL_EPTYP_ISOC (1 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_DIEPCTL_EPTYP_BULK (2 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_DIEPCTL_EPTYP_INTR (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGHS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGHS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGHS_DIEPCTL_TXFNUM_MASK (15 << OTGHS_DIEPCTL_TXFNUM_SHIFT) +#define OTGHS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGHS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGHS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ +#define OTGHS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ +#define OTGHS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGHS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGHS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ +#define OTGHS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGHS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ +#define OTGHS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ + /* Bits 8-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint 0 transfer size register */ + +#define OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGHS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGHS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ +#define OTGHS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGHS_DIEPTSIZ0_PKTCNT_SHIFT) + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint n transfer size register */ + +#define OTGHS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT) +#define OTGHS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGHS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DIEPTSIZ_PKTCNT_SHIFT) +#define OTGHS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ +#define OTGHS_DIEPTSIZ_MCNT_MASK (3 << OTGHS_DIEPTSIZ_MCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint TxFIFO status register */ + +#define OTGHS_DTXFSTS_MASK (0xffff) + +/* Device OUT endpoint 0 control register */ + +#define OTGHS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGHS_DOEPCTL0_MPSIZ_MASK (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) +# define OTGHS_DOEPCTL0_MPSIZ_64 (0 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_32 (1 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_16 (2 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGHS_DOEPCTL0_MPSIZ_8 (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGHS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DOEPCTL0_EPTYP_MASK (3 << OTGHS_DOEPCTL0_EPTYP_SHIFT) +# define OTGHS_DOEPCTL0_EPTYP_CTRL (0 << OTGHS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +#define OTGHS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGHS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device OUT endpoint n control register */ + +#define OTGHS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGHS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DOEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGHS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ +# define OTGHS_DOEPCTL_DATA0 (0) +# define OTGHS_DOEPCTL_DATA1 OTGHS_DOEPCTL_DPID +#define OTGHS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ +# define OTGHS_DOEPCTL_EVEN (0) +# define OTGHS_DOEPCTL_ODD OTGHS_DOEPCTL_EONUM +#define OTGHS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGHS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGHS_DOEPCTL_EPTYP_MASK (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) +# define OTGHS_DOEPCTL_EPTYP_CTRL (0 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGHS_DOEPCTL_EPTYP_ISOC (1 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGHS_DOEPCTL_EPTYP_BULK (2 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGHS_DOEPCTL_EPTYP_INTR (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ + +#define OTGHS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGHS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGHS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGHS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGHS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGHS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ +#define OTGHS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ +#define OTGHS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ +#define OTGHS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGHS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGHS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGHS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGHS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ +#define OTGHS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGHS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-0 transfer size register */ + +#define OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGHS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGHS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ + /* Bits 20-28: Reserved, must be kept at reset value */ +#define OTGHS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGHS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-n transfer size register */ + +#define OTGHS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGHS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT) +#define OTGHS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGHS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DOEPTSIZ_PKTCNT_SHIFT) +#define OTGHS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGHS_DOEPTSIZ_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ_STUPCNT_SHIFT) +#define OTGHS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ +#define OTGHS_DOEPTSIZ_RXDPID_MASK (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGHS_DOEPTSIZ_RXDPID_MDATA (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Power and clock gating control register */ + +#define OTGHS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ +#define OTGHS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ + /* Bits 2-3: Reserved, must be kept at reset value */ +#define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr.h new file mode 100644 index 0000000000000..cbd743564b821 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1 +# error Only one STM32 PWR IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) +# include "hardware/stm32_pwr_v1_m0_g0.h" +#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# include "hardware/stm32_pwr_v1.h" +#else +# error "Unsupported STM32 PWR" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h similarity index 95% rename from arch/arm/src/stm32/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h index 18598c7716769..e2fc5e05621c2 100644 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H /**************************************************************************** * Included Files @@ -77,7 +77,7 @@ # endif #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ @@ -151,7 +151,7 @@ # define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ # define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ #endif @@ -162,4 +162,4 @@ # define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h index bdb173a17cbf1..66a345f6d8296 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 PWR" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..308cd4d9df954 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rcc.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F1) +# include "hardware/stm32f10xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F2) +# include "hardware/stm32f20xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F3) +# if defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || \ + defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +# else +# error "Unsupported STM32F3 RCC" +# endif +#elif defined(CONFIG_ARCH_CHIP_STM32F4) +# include "hardware/stm32f40xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G4) +# include "hardware/stm32g4xxxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L1) +# include "hardware/stm32l15xxx_rcc.h" +#else +# error "Unsupported STM32 RCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_rng.h similarity index 66% rename from arch/arm/src/stm32/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_rng.h index 7adb23e656706..5b81e5116b6b8 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_rng.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,20 +20,24 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H /**************************************************************************** * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) -# include "stm32_tim_v1v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) -# include "stm32_tim_v3.h" +#if (defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)) > 1 +# error Only one STM32 RNG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) +# include "hardware/stm32_rng_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) +# include "hardware/stm32_rng_v1.h" #else -# error "STM32 TIMER IP version not specified" +# error "Unsupported STM32 RNG" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h similarity index 92% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_m0.h index 7155e94758101..1fc3c863998d1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h similarity index 91% rename from arch/arm/src/stm32/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_v1.h index 645994e2f66eb..51a829ed5dc91 100644 --- a/arch/arm/src/stm32/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H /**************************************************************************** * Included Files @@ -61,4 +61,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtc.h b/arch/arm/src/common/stm32/hardware/stm32_rtc.h new file mode 100644 index 0000000000000..b80f73f118f07 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtc.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ +#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ +#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ +#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ +#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ +#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ +#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ +#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ +#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ +#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ + +/* Register Addresses *******************************************************/ + +#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) +#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) +#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) +#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) +#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) +#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) +#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) +#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) +#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) +#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* RTC control register High (16-bit) */ + +#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ +#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ +#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ + +/* RTC control register low (16-bit) */ + +#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ +#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ +#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ +#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ +#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ +#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ + +/* RTC prescaler load register high (16-bit) */ + +#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ +#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) + +/* RTC prescaler divider register high (16-bit) */ + +#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ +#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h new file mode 100644 index 0000000000000..7431435f80fa7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)) > 1 +# error Only one STM32 RTCC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) +# include "hardware/stm32_rtcc_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) +# include "hardware/stm32_rtcc_v1.h" +#else +# error "Unsupported STM32 RTCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h index 78145ffc5ca28..e90b32708968b 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H /**************************************************************************** * Pre-processor Definitions @@ -311,4 +311,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h index e939a1214ea38..278f432ecd89e 100644 --- a/arch/arm/src/stm32/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H /**************************************************************************** * Pre-processor Definitions @@ -405,4 +405,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_sdio.h b/arch/arm/src/common/stm32/hardware/stm32_sdio.h new file mode 100644 index 0000000000000..d9c18c5b7d554 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_sdio.h @@ -0,0 +1,279 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */ +#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */ +#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */ +#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */ +#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ +#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n)) +#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ +#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ +#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */ +#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ +#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ +#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */ +#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */ +#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ +#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */ +#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ +#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */ +#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ +#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ + +/* Register Addresses *******************************************************/ + +#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET) +#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET) +#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET) +#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET) +#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET) +#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n)) +#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET) +#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET) +#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET) +#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET) +#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET) +#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET) +#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET) +#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET) +#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET) +#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET) +#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET) +#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET) +#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET) + +/* Bit-band (BB) base addresses *********************************************/ + +#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE) + +#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5)) +#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5)) +#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5)) +#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5)) +#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5)) +#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5)) +#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5)) +#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5)) +#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5)) +#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5)) +#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5)) +#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5)) +#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5)) +#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5)) +#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5)) +#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5)) +#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5)) +#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5)) +#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5)) + +/* Register Bitfield Definitions ********************************************/ + +#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) +# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define SDIO_POWER_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) +#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) +# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ +# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ +# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ + +#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define SDIO_CLKCR_RESET (0) /* Reset value */ +#define SDIO_ARG_RESET (0) /* Reset value */ + +#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4)) +#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4)) +#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4)) +#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4)) +#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4)) + +#define SDIO_CMD_CMDINDEX_SHIFT (0) +#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) +#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) +# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ + +#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define SDIO_CMD_RESET (0) /* Reset value */ + +#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4)) +#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4)) +#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4)) +#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4)) +#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4)) +#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4)) +#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4)) + +#define SDIO_RESPCMD_SHIFT (0) +#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) + +#define SDIO_DTIMER_RESET (0) /* Reset value */ + +#define SDIO_DLEN_SHIFT (0) +#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) + +#define SDIO_DLEN_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define SDIO_DCTRL_RESET (0) /* Reset value */ + +#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4)) +#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4)) +#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4)) +#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4)) +#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4)) +#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4)) +#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4)) +#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4)) + +#define SDIO_DATACOUNT_SHIFT (0) +#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) + +#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ +#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define SDIO_ICR_RESET 0x00c007ff +#define SDIO_ICR_STATICFLAGS 0x000005ff + +#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define SDIO_MASK_RESET (0) + +#define SDIO_FIFOCNT_SHIFT (0) +#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi.h new file mode 100644 index 0000000000000..2d9836336efd0 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The SPI IP version (V1..V4) is independent of the CPU core. The register + * layout is the same, but the M0 and M3/M4 ports currently keep separate + * register headers, so the file is chosen by the standard NuttX core symbol + * (CONFIG_ARCH_CORTEXM0) while the version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_SPI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) > 1 +# error Only one STM32 SPI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_spi_v1v2_m0.h" +#else +# include "hardware/stm32_spi_v2v3v4.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h index fd63397093ee7..8d730e7b21fd7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H /**************************************************************************** * Included Files @@ -32,14 +32,12 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32_STM32F0) || \ - defined(CONFIG_STM32_STM32G0) || \ - defined(CONFIG_STM32_STM32C0) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32_STM32L0) +#elif defined(CONFIG_STM32_HAVE_IP_SPI_V1) # define HAVE_IP_SPI_V1 #else -# error Unsupported family +# error Unsupported STM32 F0/L0/G0/C0 SPI IP #endif /**************************************************************************** @@ -229,4 +227,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h index b52e278e38083..187df078bf53f 100644 --- a/arch/arm/src/stm32/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H /**************************************************************************** * Included Files @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32_HAVE_IP_SPI_V2) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V3) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V4) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -280,4 +280,4 @@ # define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_syscfg.h b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h new file mode 100644 index 0000000000000..7ed634e52b2b6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_syscfg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_syscfg.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_syscfg.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_syscfg.h" +#else +# error "Unsupported STM32 M0 SYSCFG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim.h new file mode 100644 index 0000000000000..4db3706e8899e --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_tim.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1 +# error Only one STM32 TIMER IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "hardware/stm32_tim_v3_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +# include "stm32_tim_v1v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_v3.h" +#else +# error "STM32 TIMER IP version not specified" +#endif +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h new file mode 100644 index 0000000000000..d519a4df68ed8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h @@ -0,0 +1,1307 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TIM version **************************************************************/ + +/* Chip has extended version of ADV Timers (F3/F7/H7/L4/L4+): + * - CCMR3, CCR5 and CCR6 registers + * - OC5 and OC6 + * - 32-bit CCMR register + * - UIFREMAP bit in CR1 register + * - TRGO2 configuration in CR2 register + * - OCCS bit and 4-bit SMS in SMCR register + * + * Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+): + * - UIFREMAP bit in CR1 register + * - 4-bit SMS in SMCR register + */ + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +# define HAVE_IP_TIMERS_V2 +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) +# define HAVE_IP_TIMERS_V1 +#else +# error +#endif + +/* TIM16 has OR register (F3/L4) */ + +#ifdef CONFIG_STM32_STM32F30XX +# define HAVE_TIM16_OR +#endif + +/* General Timers have CCxNP bits (not in F1) */ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ + defined(CONFIG_STM32_STM32F4XXX) +# define HAVE_GTIM_CCXNP +#endif + +/* Register Offsets *********************************************************/ + +/* Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ + +/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, + * and TIM14 + * For the STM32F10xx all timers are 16-bit. + * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit + * The STM32 F1 Value Line and the STM32 F3 have variant general purpose + * registers that are not yet fully covered in this header file. + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2-5 only) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ + +/* The Option register is available on in the + * + * STM32 F1 value line, F2 and F4: TIM2, TIM5, and TIM11 + * STM32 F3 (and possibly the F1 value line): TIM16 + */ + +#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */ + +/* Advanced Timers - TIM1, TIM8 and TIM20 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ + +/* Note that many of the above registers are 32-bits wide on the F3 */ + +#ifdef HAVE_IP_TIMERS_V2 +# define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +# define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ +# define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (32-bit) */ +#endif + +/* Register Addresses *******************************************************/ + +/* Advanced Timers - TIM1 and TIM8 */ + +#if STM32_NATIM > 0 +# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#ifdef HAVE_IP_TIMERS_V2 +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +# endif +#endif + +#if STM32_NATIM > 1 +# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +#ifdef HAVE_IP_TIMERS_V2 +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +# endif +#endif + +/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. + * For the STM32F10xx all timers are 16-bit. + * For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit + */ + +#if STM32_NGTIM > 0 +# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) +# endif +#endif + +#if STM32_NGTIM > 1 +# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 2 +# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 3 +# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) +# endif +#endif + +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) + +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCMR2 (STM32_TIM16_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) + +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCMR2 (STM32_TIM17_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) + +/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers + * support only a subset of the general timer registers are supported, and + * (2) TIM9 and TIM12 differ from the others. + */ + +#if STM32_NGTIMNDMA > 0 +# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32_NGTIMNDMA > 1 +# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32_NGTIMNDMA > 2 +# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) +#endif + +#if STM32_NGTIMNDMA > 3 +# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) +# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) +#endif + +#if STM32_NGTIMNDMA > 4 +# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +#if STM32_NGTIMNDMA > 5 +# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) +# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) +# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) +# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) +# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) +# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) +# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) +# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) +# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) +#endif + +/* Basic Timers - TIM6 and TIM7 */ + +#if STM32_NBTIM > 0 +# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +#if STM32_NBTIM > 1 +# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ +#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ +# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ +#endif + +/* Control register 2 */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ +# define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +# define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +# define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ +# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ +#endif + +/* Slave mode control register */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ +#endif +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ +#endif + +/* DMA/Interrupt enable register */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ + +/* Status register */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ +#endif +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ +# define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ +#endif + +/* Event generation register */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ +#endif + +/* Capture/compare mode register 1 -- Output compare mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ +#endif + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ + +/* Capture/compare mode register 1 -- Input capture mode */ + +/* Bits 1-0: + * (same as output compare mode) + */ + +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) + /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ +#endif + +/* Capture/compare mode register 2 - Input Capture Mode */ + +/* Bits 1-0: + * (same as output compare mode) + */ + +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + /* Bits 9:8 (same as output compare mode) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) + /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) + /* (See common (unshifted) bit field definitions above) */ + +/* Capture/compare mode register 3 -- Output compare mode */ + +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +# define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +# define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ +# define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +# define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +# define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +# define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +# define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ +# define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) + /* (See common (unshifted) bit field definitions below) */ +# define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +# define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +# define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ +#endif + +/* Capture/compare enable register */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity + * NOTE: Some ST documents show CC4NP bit but there is + * no CC4N output, so it does not make sense! + */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ +# define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ +# define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ +# define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ +#endif +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* 16-bit counter register */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ +#endif + +/* Repetition counter register */ + +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ +# define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) +# define ATIM_RCR_REP_MAX 32768 /* REVISIT */ +#else +# define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ +# define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT) +# define ATIM_RCR_REP_MAX 128 +#endif + +/* Capture/compare registers (CCR) */ + +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ +# define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ +# define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ +#endif + +#define ATIM_CCR_MASK (0xffff) + +/* Break and dead-time register */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ +#ifdef HAVE_IP_TIMERS_V2 +# define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +# define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +# define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +# define ATIM_BDTR_BK2F_MASK (15 << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +# define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +# define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ +#endif + +/* DMA control register */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Control register 1 (TIM2-5 and TIM9-14) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ +#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ +# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ +#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ +# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ +# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ +#ifdef HAVE_IP_TIMERS_V2 +# define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ +#endif + +/* Control register 2 (TIM2-5, TIM9-12, and TIM15-17 only) */ + +#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ +#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ +#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ +# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ +# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ +# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ +#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ +#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ +#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ + +/* Slave mode control register (TIM2-5 and TIM15 only) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ +#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ +# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ +#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ +# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ +# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ +# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ +# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ +#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ +#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ +#ifdef HAVE_IP_TIMERS_V2 +# define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ +#endif + +/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ +#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ +#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ + +/* Status register */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ +#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ +#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ + +/* Event generation register (TIM2-5 and TIM9-14) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ +#define GTIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ +#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ + +/* Capture/compare mode register 1 - Output compare mode + * (TIM2-5 and TIM9-14) + */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) + /* (See common CCMR Output Compare Mode definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#ifdef HAVE_IP_TIMERS_V2 +# define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +# define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ +#endif + +/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ + +#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ + +/* Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ + +/* Capture/compare mode register 1 - Input capture mode + * (TIM2-5 and TIM9-14) + */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) + /* (See common CCMR Capture/Compare Selection definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) + /* (See common CCMR Output Compare Mode definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ + +/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ + +/* Bits 1-0 + * (Same as Output Compare Mode) + */ +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + /* Bits 9-8: (Same as Output Compare Mode) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) + /* (See common CCMR Input Capture Prescaler definitions below) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) + /* (See common CCMR Input Capture Filter definitions below) */ + +/* Capture/compare enable register (TIM2-5 and TIM9-14) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ +#ifdef HAVE_GTIM_CCXNP +# define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ +#endif +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ +#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ +#ifdef HAVE_GTIM_CCXNP +# define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ +#endif +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ +#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ +#ifdef HAVE_GTIM_CCXNP +# define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ +#endif +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ +#ifdef HAVE_GTIM_CCXNP +# define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity + * NOTE: Some ST documents show CC4NP bit but there is + * no CC4N output, so it does not make sense! + */ +#endif +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* 16-bit counter register */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) +#ifdef HAVE_IP_TIMERS_V2 +# define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ +#endif + +/* DMA control register */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) + +/* Timer 2/5 option register */ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ +# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) +# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ +# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ +# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ +# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ + +# define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +# define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) +# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ +# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ +# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ +# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ + +# define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ +# define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) +# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ +# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ +#endif + +/* Timer 16 Option Register */ + +#ifdef HAVE_TIM16_OR +# define TIM16_OR_RMP_SHIFT (0) /* Bits 0-1: Timer 16 input 1 connection */ +# define TIM16_OR_RMP_MASK (3 << TIM16_OR_RMP_SHIFT) +# define TIM16_OR_RMP_GPRIO (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to GPIO */ +# define TIM16_OR_RMP_RTC (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to RTC_clock */ +# define TIM16_OR_RMP_HSEd32 (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to HSE/32 */ +# define TIM16_OR_RMP_MCO (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to MCO */ +#endif + +/* Control register 1 */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ + +/* Control register 2 */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* DMA/Interrupt enable register */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* Status register */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ + +/* Event generation register */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h new file mode 100644 index 0000000000000..d4bd858b59119 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h @@ -0,0 +1,1440 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_tim_v3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* BTIM: Basic Timers - TIM6 and TIM7 */ + +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (32-bit register, 16-bit counter) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit) */ + +/* GTIM: General Timers + * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 + * + * Caution! TIM2/5, TIM3/4, TIM15, and TIM16/17 are slightly different and + * have different registers, register sizes, and register bitfields! + * + * Some registers are marked with the following notes: + * + * Note 1: The register is 32-bit but its contents have different variants + * for TIM3/4 and TIM2/5, TIM15 + * Note 2: This register not available on TIM15 + * Note 3: This register not available on TIM16/17 + */ + +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit TIM2-5; 16-bit TIM15-17) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit TIM2-5, TIM15, See Note 3) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (32-bit TIM2-5; 16-bit TIM15) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (32-bit TIM2-5; 16-bit TIM15-17) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (32-bit, See Note 1) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit, See Note 1) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit, TIM15 only) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (32-bit, See Note 1) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (32-bit, See Notes 1, 3) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (32-bit, See Notes 1, 3) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (32-bit, See Notes 1, 3) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit, TIM15-17 only) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 (TIM16/17 only) */ +#define STM32_GTIM_DTR2_OFFSET 0x0054 /* Dead-time register 2 (32-bit, TIM15-17 only) */ +#define STM32_GTIM_ECR_OFFSET 0x0058 /* Encoder control register (32-bit, See Notes 2, 3) */ +#define STM32_GTIM_TISEL_OFFSET 0x005c /* Timer input selection register (32-bit) */ +#define STM32_GTIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ +#define STM32_GTIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ +#define STM32_GTIM_DCR_OFFSET 0x03dc /* DMA control register (16-bit, TIM2-5 only) */ +#define STM32_GTIM_DMAR_OFFSET 0x03e0 /* DMA address for burst mode (16-bit, TIM2-5 only) */ + +/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ + +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (32-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit register, 16-bit counter) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (32-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (32-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (32-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0048 /* Capture/compare register 5 (32-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x004c /* Capture/compare register 6 (32-bit) */ +#define STM32_ATIM_CCMR3_OFFSET 0x0050 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_DTR2_OFFSET 0x0054 /* Dead-time register 2 (32-bit) */ +#define STM32_ATIM_ECR_OFFSET 0x0058 /* Encoder control register (32-bit) */ +#define STM32_ATIM_TISEL_OFFSET 0x005c /* Timer input selection register (32-bit) */ +#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ +#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ +#define STM32_ATIM_DCR_OFFSET 0x03dc /* DMA control register (32-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x03e0 /* DMA address for full transfer (32-bit) */ + +/* Register Addresses *******************************************************/ + +/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ + +#if STM32_NATIM > 0 +# define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +# define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +# define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +# define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +# define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +# define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +# define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +# define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +# define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +# define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM1_DTR2 (STM32_TIM1_BASE + STM32_ATIM_DTR2_OFFSET) +# define STM32_TIM1_ECR (STM32_TIM1_BASE + STM32_ATIM_ECR_OFFSET) +# define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_ATIM_TISEL_OFFSET) +# define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_ATIM_AF1_OFFSET) +# define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_ATIM_AF2_OFFSET) +# define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +# define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#endif + +#if STM32_NATIM > 1 +# define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +# define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +# define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +# define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +# define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +# define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +# define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +# define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +# define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +# define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM8_DTR2 (STM32_TIM8_BASE + STM32_ATIM_DTR2_OFFSET) +# define STM32_TIM8_ECR (STM32_TIM8_BASE + STM32_ATIM_ECR_OFFSET) +# define STM32_TIM8_TISEL (STM32_TIM8_BASE + STM32_ATIM_TISEL_OFFSET) +# define STM32_TIM8_AF1 (STM32_TIM8_BASE + STM32_ATIM_AF1_OFFSET) +# define STM32_TIM8_AF2 (STM32_TIM8_BASE + STM32_ATIM_AF2_OFFSET) +# define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +# define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#endif + +#if STM32_NATIM > 2 +# define STM32_TIM20_CR1 (STM32_TIM20_BASE + STM32_ATIM_CR1_OFFSET) +# define STM32_TIM20_CR2 (STM32_TIM20_BASE + STM32_ATIM_CR2_OFFSET) +# define STM32_TIM20_SMCR (STM32_TIM20_BASE + STM32_ATIM_SMCR_OFFSET) +# define STM32_TIM20_DIER (STM32_TIM20_BASE + STM32_ATIM_DIER_OFFSET) +# define STM32_TIM20_SR (STM32_TIM20_BASE + STM32_ATIM_SR_OFFSET) +# define STM32_TIM20_EGR (STM32_TIM20_BASE + STM32_ATIM_EGR_OFFSET) +# define STM32_TIM20_CCMR1 (STM32_TIM20_BASE + STM32_ATIM_CCMR1_OFFSET) +# define STM32_TIM20_CCMR2 (STM32_TIM20_BASE + STM32_ATIM_CCMR2_OFFSET) +# define STM32_TIM20_CCER (STM32_TIM20_BASE + STM32_ATIM_CCER_OFFSET) +# define STM32_TIM20_CNT (STM32_TIM20_BASE + STM32_ATIM_CNT_OFFSET) +# define STM32_TIM20_PSC (STM32_TIM20_BASE + STM32_ATIM_PSC_OFFSET) +# define STM32_TIM20_ARR (STM32_TIM20_BASE + STM32_ATIM_ARR_OFFSET) +# define STM32_TIM20_RCR (STM32_TIM20_BASE + STM32_ATIM_RCR_OFFSET) +# define STM32_TIM20_CCR1 (STM32_TIM20_BASE + STM32_ATIM_CCR1_OFFSET) +# define STM32_TIM20_CCR2 (STM32_TIM20_BASE + STM32_ATIM_CCR2_OFFSET) +# define STM32_TIM20_CCR3 (STM32_TIM20_BASE + STM32_ATIM_CCR3_OFFSET) +# define STM32_TIM20_CCR4 (STM32_TIM20_BASE + STM32_ATIM_CCR4_OFFSET) +# define STM32_TIM20_BDTR (STM32_TIM20_BASE + STM32_ATIM_BDTR_OFFSET) +# define STM32_TIM20_CCR5 (STM32_TIM20_BASE + STM32_ATIM_CCR5_OFFSET) +# define STM32_TIM20_CCR6 (STM32_TIM20_BASE + STM32_ATIM_CCR6_OFFSET) +# define STM32_TIM20_CCMR3 (STM32_TIM20_BASE + STM32_ATIM_CCMR3_OFFSET) +# define STM32_TIM20_DTR2 (STM32_TIM20_BASE + STM32_ATIM_DTR2_OFFSET) +# define STM32_TIM20_ECR (STM32_TIM20_BASE + STM32_ATIM_ECR_OFFSET) +# define STM32_TIM20_TISEL (STM32_TIM20_BASE + STM32_ATIM_TISEL_OFFSET) +# define STM32_TIM20_AF1 (STM32_TIM20_BASE + STM32_ATIM_AF1_OFFSET) +# define STM32_TIM20_AF2 (STM32_TIM20_BASE + STM32_ATIM_AF2_OFFSET) +# define STM32_TIM20_DCR (STM32_TIM20_BASE + STM32_ATIM_DCR_OFFSET) +# define STM32_TIM20_DMAR (STM32_TIM20_BASE + STM32_ATIM_DMAR_OFFSET) +#endif + +/* GTIM: General Timers + * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 + */ + +#if STM32_NGTIM > 0 +# define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM2_ECR (STM32_TIM2_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM2_AF2 (STM32_TIM2_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 1 +# define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM3_ECR (STM32_TIM3_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM3_TISEL (STM32_TIM3_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM3_AF1 (STM32_TIM3_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM3_AF2 (STM32_TIM3_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 2 +# define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM4_ECR (STM32_TIM4_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM4_TISEL (STM32_TIM4_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM4_AF1 (STM32_TIM4_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM4_AF2 (STM32_TIM4_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 3 +# define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM5_ECR (STM32_TIM5_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM5_TISEL (STM32_TIM5_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM5_AF1 (STM32_TIM5_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM5_AF2 (STM32_TIM5_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 4 +# define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM15_CCMR2 (STM32_TIM15_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM15_CCR3 (STM32_TIM15_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM15_CCR4 (STM32_TIM15_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM15_ECR (STM32_TIM15_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM15_TISEL (STM32_TIM15_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM15_AF1 (STM32_TIM15_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM15_AF2 (STM32_TIM15_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 5 +# define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM16_SMCR (STM32_TIM16_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM16_CCMR2 (STM32_TIM16_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM16_CCR2 (STM32_TIM16_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM16_CCR3 (STM32_TIM16_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM16_CCR4 (STM32_TIM16_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM16_ECR (STM32_TIM16_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM16_AF2 (STM32_TIM16_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +#if STM32_NGTIM > 6 +# define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +# define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +# define STM32_TIM17_SMCR (STM32_TIM17_BASE + STM32_GTIM_SMCR_OFFSET) +# define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +# define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +# define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +# define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +# define STM32_TIM17_CCMR2 (STM32_TIM17_BASE + STM32_GTIM_CCMR2_OFFSET) +# define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +# define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +# define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +# define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +# define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +# define STM32_TIM17_CCR2 (STM32_TIM17_BASE + STM32_GTIM_CCR2_OFFSET) +# define STM32_TIM17_CCR3 (STM32_TIM17_BASE + STM32_GTIM_CCR3_OFFSET) +# define STM32_TIM17_CCR4 (STM32_TIM17_BASE + STM32_GTIM_CCR4_OFFSET) +# define STM32_TIM17_ECR (STM32_TIM17_BASE + STM32_GTIM_ECR_OFFSET) +# define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_GTIM_TISEL_OFFSET) +# define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_GTIM_AF1_OFFSET) +# define STM32_TIM17_AF2 (STM32_TIM17_BASE + STM32_GTIM_AF2_OFFSET) +# define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +# define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) +#endif + +/* BTIM: Basic Timers - TIM6 and TIM7 */ + +#if STM32_NBTIM > 0 +# define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +# define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +# define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +# define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +# define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +# define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +# define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +# define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) +#endif + +#if STM32_NBTIM > 1 +# define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +# define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +# define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +# define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +# define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +# define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +# define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +# define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) +#endif + +/* Register Bitfield Definitions - ATIM *************************************/ + +/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ + +/* ATIM Control register 1 (CR1) */ + +#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define ATIM_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ +#define ATIM_CR1_CMS_MASK (0x3 << ATIM_CR1_CMS_SHIFT) +# define ATIM_CR1_EDGE (0x0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define ATIM_CR1_CENTER1 (0x1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define ATIM_CR1_CENTER2 (0x2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define ATIM_CR1_CENTER3 (0x3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define ATIM_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ +#define ATIM_CR1_CKD_MASK (0x3 << ATIM_CR1_CKD_SHIFT) +# define ATIM_CR1_TCKINT (0x0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=1*tCK_INT */ +# define ATIM_CR1_2TCKINT (0x1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define ATIM_CR1_4TCKINT (0x2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ +#define ATIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering enable */ + +/* ATIM Control register 2 (CR2) */ + +#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ +#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ +#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define ATIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ +#define ATIM_CR2_MMS_MASK (0x200007 << ATIM_CR2_MMS_SHIFT) +# define ATIM_CR2_MMS_RESET (0x0 << ATIM_CR2_MMS_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRGO */ +# define ATIM_CR2_MMS_ENABLE (0x1 << ATIM_CR2_MMS_SHIFT) /* 0001: Enable - CNT_EN is TRGO */ +# define ATIM_CR2_MMS_UPDATE (0x2 << ATIM_CR2_MMS_SHIFT) /* 0010: Update event is TRGO */ +# define ATIM_CR2_MMS_COMPP (0x3 << ATIM_CR2_MMS_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS_OC1REF (0x4 << ATIM_CR2_MMS_SHIFT) /* 0100: Compare OC1REF is TRGO */ +# define ATIM_CR2_MMS_OC2REF (0x5 << ATIM_CR2_MMS_SHIFT) /* 0101: Compare OC2REF is TRGO */ +# define ATIM_CR2_MMS_OC3REF (0x6 << ATIM_CR2_MMS_SHIFT) /* 0110: Compare OC3REF is TRGO */ +# define ATIM_CR2_MMS_OC4REF (0x7 << ATIM_CR2_MMS_SHIFT) /* 0111: Compare OC4REF is TRGO */ +# define ATIM_CR2_MMS_ENCODER (0x200000 << ATIM_CR2_MMS_SHIFT) /* 1000: Encoder clock is TRGO */ +#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ +#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ +#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ +#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ +#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ +#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ +#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ +#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ +#define ATIM_CR2_OIS4N (1 << 15) /* Bit 15: Output Idle state 4 (OC4N output) */ +#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ +#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ +#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ +#define ATIM_CR2_MMS2_MASK (0xf << ATIM_CR2_MMS2_SHIFT) +# define ATIM_CR2_MMS2_RESET (0x0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ +# define ATIM_CR2_MMS2_ENABLE (0x1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ +# define ATIM_CR2_MMS2_UPDATE (0x2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0 */ +# define ATIM_CR2_MMS2_COMPP (0x3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define ATIM_CR2_MMS2_OC1REF (0x4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC2REF (0x5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC3REF (0x6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC4REF (0x7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC5REF (0x8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ +# define ATIM_CR2_MMS2_OC6REF (0x9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4 (0xa << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC6 (0xb << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ +# define ATIM_CR2_MMS2_CMPOC4R6R (0xc << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC4R6F (0xd << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ +# define ATIM_CR2_MMS2_CMPOC5R6R (0xe << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ +# define ATIM_CR2_MMS2_CMPOC5R6F (0xf << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ + +/* ATIM Slave mode control register (SMCR) */ + +#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define ATIM_SMCR_SMS_MASK (0x10007 << ATIM_SMCR_SMS_SHIFT) +# define ATIM_SMCR_DISAB (0x0 << ATIM_SMCR_SMS_SHIFT) /* 0000: Slave mode disabled */ +# define ATIM_SMCR_ENCMD1 (0x1 << ATIM_SMCR_SMS_SHIFT) /* 0001: Encoder mode 1 */ +# define ATIM_SMCR_ENCMD2 (0x2 << ATIM_SMCR_SMS_SHIFT) /* 0010: Encoder mode 2 */ +# define ATIM_SMCR_ENCMD3 (0x3 << ATIM_SMCR_SMS_SHIFT) /* 0011: Encoder mode 3 */ +# define ATIM_SMCR_RESET (0x4 << ATIM_SMCR_SMS_SHIFT) /* 0100: Reset Mode */ +# define ATIM_SMCR_GATED (0x5 << ATIM_SMCR_SMS_SHIFT) /* 0101: Gated Mode */ +# define ATIM_SMCR_TRIGGER (0x6 << ATIM_SMCR_SMS_SHIFT) /* 0110: Trigger Mode */ +# define ATIM_SMCR_EXTCLK1 (0x7 << ATIM_SMCR_SMS_SHIFT) /* 0111: External Clock Mode 1 */ +# define ATIM_SMCR_RESET_TRIGGER (0x10000 << ATIM_SMCR_SMS_SHIFT) /* 1000: Combined reset + trigger */ +# define ATIM_SMCR_GATED_RESET (0x10001 << ATIM_SMCR_SMS_SHIFT) /* 1001: Combined gated + reset */ +# define ATIM_SMCR_ENCMD4 (0x10002 << ATIM_SMCR_SMS_SHIFT) /* 1010: Encoder mode 4 */ +# define ATIM_SMCR_ENCMD5 (0x10003 << ATIM_SMCR_SMS_SHIFT) /* 1011: Encoder mode 5 */ +# define ATIM_SMCR_ENCMD6 (0x10004 << ATIM_SMCR_SMS_SHIFT) /* 1100: Encoder mode 6 */ +# define ATIM_SMCR_ENCMD7 (0x10005 << ATIM_SMCR_SMS_SHIFT) /* 1101: Encoder mode 7 */ +# define ATIM_SMCR_ENCMD8 (0x10006 << ATIM_SMCR_SMS_SHIFT) /* 1110: Encoder mode 8 */ +# define ATIM_SMCR_ENCMD9 (0x10007 << ATIM_SMCR_SMS_SHIFT) /* 1111: Encoder mode 9 */ +#define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ +#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define ATIM_SMCR_TS_MASK (0x30007 << ATIM_SMCR_TS_SHIFT) +# define ATIM_SMCR_ITR0 (0x0 << ATIM_SMCR_TS_SHIFT) /* 00 000: Internal trigger 0 (ITR0) */ +# define ATIM_SMCR_ITR1 (0x1 << ATIM_SMCR_TS_SHIFT) /* 00 001: Internal trigger 1 (ITR1) */ +# define ATIM_SMCR_ITR2 (0x2 << ATIM_SMCR_TS_SHIFT) /* 00 010: Internal trigger 2 (ITR2) */ +# define ATIM_SMCR_ITR3 (0x3 << ATIM_SMCR_TS_SHIFT) /* 00 011: Internal trigger 3 (ITR3) */ +# define ATIM_SMCR_TI1FED (0x4 << ATIM_SMCR_TS_SHIFT) /* 00 100: TI1 Edge Detector (TI1F_ED) */ +# define ATIM_SMCR_TI1FP1 (0x5 << ATIM_SMCR_TS_SHIFT) /* 00 101: Filtered Timer Input 1 (TI1FP1) */ +# define ATIM_SMCR_TI2FP2 (0x6 << ATIM_SMCR_TS_SHIFT) /* 00 110: Filtered Timer Input 2 (TI2FP2) */ +# define ATIM_SMCR_ETRF (0x7 << ATIM_SMCR_TS_SHIFT) /* 00 111: External Trigger Input (ETRF) */ +# define ATIM_SMCR_ITR4 (0x1000 << ATIM_SMCR_TS_SHIFT) /* 01 000: Internal Trigger 0 ITR4 */ +# define ATIM_SMCR_ITR5 (0x1001 << ATIM_SMCR_TS_SHIFT) /* 01 001: Internal Trigger 1 ITR5 */ +# define ATIM_SMCR_ITR6 (0x1002 << ATIM_SMCR_TS_SHIFT) /* 01 010: Internal Trigger 1 ITR6 */ +# define ATIM_SMCR_ITR7 (0x1003 << ATIM_SMCR_TS_SHIFT) /* 01 011: Internal Trigger 1 ITR7 */ +# define ATIM_SMCR_ITR8 (0x1004 << ATIM_SMCR_TS_SHIFT) /* 01 100: Internal Trigger 1 ITR8 */ +# define ATIM_SMCR_ITR9 (0x1005 << ATIM_SMCR_TS_SHIFT) /* 01 101: Internal Trigger 1 ITR9 */ +# define ATIM_SMCR_ITR10 (0x1006 << ATIM_SMCR_TS_SHIFT) /* 01 110: Internal Trigger 1 ITR10 */ +#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define ATIM_SMCR_ETF_MASK (0xf << ATIM_SMCR_ETF_SHIFT) +# define ATIM_SMCR_NOFILT (0x0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define ATIM_SMCR_FCKINT2 (0x1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_SMCR_FCKINT4 (0x2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_SMCR_FCKINT8 (0x3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_SMCR_FDTSd26 (0x4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_SMCR_FDTSd28 (0x5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_SMCR_FDTSd46 (0x6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_SMCR_FDTSd48 (0x7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_SMCR_FDTSd86 (0x8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_SMCR_FDTSd88 (0x9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_SMCR_FDTSd165 (0xa << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_SMCR_FDTSd166 (0xb << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_SMCR_FDTSd168 (0xc << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_SMCR_FDTSd325 (0xd << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_SMCR_FDTSd326 (0xe << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_SMCR_FDTSd328 (0xf << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define ATIM_SMCR_ETPS_MASK (0x3 << ATIM_SMCR_ETPS_SHIFT) +# define ATIM_SMCR_PSCOFF (0x0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define ATIM_SMCR_ETRPd2 (0x1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define ATIM_SMCR_ETRPd4 (0x2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define ATIM_SMCR_ETRPd8 (0x3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ +#define ATIM_SMCR_SMSPE (1 << 24) /* Bit 24: SMS preload enable */ +#define ATIM_SMCR_SMSPS (1 << 25) /* Bit 25: SMS preload source */ + +/* ATIM DMA/Interrupt enable register (DIER) */ + +#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ +#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ +#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ +#define ATIM_DIER_IDXIE (1 << 20) /* Bit 20: Index interrupt enable */ +#define ATIM_DIER_DIRIE (1 << 21) /* Bit 21: Direction change interrupt enable */ +#define ATIM_DIER_IERRIE (1 << 22) /* Bit 22: Index error interrupt enable */ +#define ATIM_DIER_TERRIE (1 << 23) /* Bit 23: Transition error interrupt enable */ + +/* ATIM Status register (SR) */ + +#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ +#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 Interrupt Flag */ +#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 Interrupt Flag */ +#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 Interrupt Flag */ +#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 Interrupt Flag */ +#define ATIM_SR_COMIF (1 << 5) /* Bit 5: Com Interrupt Flag */ +#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger Interrupt Flag */ +#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break Interrupt Flag */ +#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 Interrupt Flag */ +#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define ATIM_SR_SBIF (1 << 13) /* Bit 13: System Break Interrupt Flag */ +#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 Interrupt Flag */ +#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 Interrupt Flag */ +#define ATIM_SR_IDXF (1 << 20) /* Bit 20: Index Interrupt Flag */ +#define ATIM_SR_DIRF (1 << 21) /* Bit 21: Direction Change Interrupt Flag */ +#define ATIM_SR_IERRF (1 << 22) /* Bit 22: Index Error Interrupt Flag */ +#define ATIM_SR_TERRF (1 << 23) /* Bit 23: Transition Error Interrupt Flag */ + +/* ATIM Event generation register (EGR) */ + +#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ +#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ +#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ +#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ + +/* ATIM Capture/compare mode register 1 (CCMR1) - Output Compare Mode */ + +#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ +#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode */ +#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode */ +#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* ATIM Common CCMR (unshifted) Capture/Compare Selection + * bit-field definitions + */ + +#define ATIM_CCMR_CCS_CCOUT (0x0) /* 00: CCx channel output */ +#define ATIM_CCMR_CCS_CCIN1 (0x1) /* 01: CCx channel input, ICx is TIx */ +#define ATIM_CCMR_CCS_CCIN2 (0x2) /* 10: CCx channel input, ICx is TIy */ +#define ATIM_CCMR_CCS_CCINTRC (0x3) /* 11: CCx channel input, ICx is TRC */ + +/* ATIM Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define ATIM_CCMR_MODE_FRZN (0x0) /* 0000: Frozen */ +#define ATIM_CCMR_MODE_CHACT (0x1) /* 0001: Channel x active on match */ +#define ATIM_CCMR_MODE_CHINACT (0x2) /* 0010: Channel x inactive on match */ +#define ATIM_CCMR_MODE_OCREFTOG (0x3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ +#define ATIM_CCMR_MODE_OCREFLO (0x4) /* 0100: OCxREF forced low */ +#define ATIM_CCMR_MODE_OCREFHI (0x5) /* 0101: OCxREF forced high */ +#define ATIM_CCMR_MODE_PWM1 (0x6) /* 0110: PWM mode 1 */ +#define ATIM_CCMR_MODE_PWM2 (0x7) /* 0111: PWM mode 2 */ +#define ATIM_CCMR_MODE_OPM1 (0x8) /* 1000: Retriggerable OPM mode 1 */ +#define ATIM_CCMR_MODE_OPM2 (0x9) /* 1001: Retriggerable OPM mode 2 */ +#define ATIM_CCMR_MODE_COMBINED1 (0xc) /* 1100: Combined PWM mode 1 */ +#define ATIM_CCMR_MODE_COMBINED2 (0xd) /* 1101: Combined PWM mode 2 */ +#define ATIM_CCMR_MODE_ASYMMETRIC1 (0xe) /* 1110: Asymmetric PWM mode 1 */ +#define ATIM_CCMR_MODE_ASYMMETRIC2 (0xf) /* 1111: Asymmetric PWM mode 2 */ + +/* ATIM Capture/compare mode register 1 (CCMR1) - Input Capture Mode + * Bits 0-1 and Bits 8-9 are same as Output Compare Mode + */ + +#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ +#define ATIM_CCMR1_IC1PSC_MASK (0x3 << ATIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ +#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ +#define ATIM_CCMR1_IC2PSC_MASK (0x3 << ATIM_CCMR1_IC2PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ +#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define ATIM_CCMR_ICPSC_NOPSC (0x0) /* 00: no prescaler, capture each edge */ +#define ATIM_CCMR_ICPSC_EVENTS2 (0x1) /* 01: capture once every 2 events */ +#define ATIM_CCMR_ICPSC_EVENTS4 (0x2) /* 10: capture once every 4 events */ +#define ATIM_CCMR_ICPSC_EVENTS8 (0x3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define ATIM_CCMR_ICF_NOFILT (0x0) /* 0000: No filter, sampling at fDTS */ +#define ATIM_CCMR_ICF_FCKINT2 (0x1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define ATIM_CCMR_ICF_FCKINT4 (0x2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define ATIM_CCMR_ICF_FCKINT8 (0x3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define ATIM_CCMR_ICF_FDTSd26 (0x4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define ATIM_CCMR_ICF_FDTSd28 (0x5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define ATIM_CCMR_ICF_FDTSd46 (0x6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define ATIM_CCMR_ICF_FDTSd48 (0x7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define ATIM_CCMR_ICF_FDTSd86 (0x8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define ATIM_CCMR_ICF_FDTSd88 (0x9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define ATIM_CCMR_ICF_FDTSd165 (0xa) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define ATIM_CCMR_ICF_FDTSd166 (0xb) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define ATIM_CCMR_ICF_FDTSd168 (0xc) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define ATIM_CCMR_ICF_FDTSd325 (0xd) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define ATIM_CCMR_ICF_FDTSd326 (0xe) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define ATIM_CCMR_ICF_FDTSd328 (0xf) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* ATIM Capture/compare mode register 2 (CCMR2) - Output Compare Mode */ + +#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ +#define ATIM_CCMR2_CC3S_MASK (0x3 << ATIM_CCMR2_CC3S_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode */ +#define ATIM_CCMR2_OC3M_MASK (0x7 << ATIM_CCMR2_OC3M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ +#define ATIM_CCMR2_CC4S_MASK (0x3 << ATIM_CCMR2_CC4S_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode */ +#define ATIM_CCMR2_OC4M_MASK (0x7 << ATIM_CCMR2_OC4M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* ATIM Capture/compare mode register 2 (CCMR2) - Input Capture Mode + * Bits 0-1 and Bits 8-9 are same as Output Compare Mode + */ + +#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ +#define ATIM_CCMR2_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ +#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ +#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ +#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) /* (See common (unshifted) bit field definitions above) */ + +/* ATIM Capture/compare mode register 3 (CCMR3) */ + +#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ +#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ +#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 4-6: Output Compare 5 Mode */ +#define ATIM_CCMR3_OC5M_MASK (0x7 << ATIM_CCMR3_OC5M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ +#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ +#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ +#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 12-14: Output Compare 7 Mode */ +#define ATIM_CCMR3_OC6M_MASK (0x7 << ATIM_CCMR3_OC6M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ +#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ +#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ + +/* ATIM Capture/compare enable register (CCER) */ + +#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 Output Enable */ +#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 Output Polarity */ +#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary Output Enable */ +#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary Output Polarity */ +#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 Output Enable */ +#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 Output Polarity */ +#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary Output Enable */ +#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary Output Polarity */ +#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 Output Enable */ +#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 Output Polarity */ +#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary Output Enable */ +#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary Output Polarity */ +#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ +#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ +#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ +#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 Output Enable */ +#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 Output Polarity */ +#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 Output Enable */ +#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 Output Polarity */ +#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* ATIM Counter (CNT) */ + +#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ +#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) +#define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ + +/* ATIM Prescaler (PSC) */ + +#define ATIM_PSC_SHIFT (0) +#define ATIM_PSC_MASK (0xffff << ATIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ + +/* ATIM Auto-reload register (ARR) */ + +#define ATIM_ARR_SHIFT (0) +#define ATIM_ARR_MASK (0xffffffff << ATIM_ARR_SHIFT) /* Bits 0-31: Auto reload register */ + +/* ATIM Repetition counter register (RCR) */ + +#define ATIM_RCR_SHIFT (0) +#define ATIM_RCR_MASK (0xffff << ATIM_RCR_SHIFT) /* Bits 0-15: Repetition counter register */ + +/* ATIM Capture/compare register 1 (CCR1 - CCR6) */ + +#define ATIM_CCR_SHIFT (0) +#define ATIM_CCR_MASK (0xfffff << ATIM_CCR_SHIFT) /* Bits 0-19: Capture/compare 1 value */ +#define ATIM_CCR5_GC5C1 (1 << 29) /* CCR5 only, Bit 29: Group Channel 5 and Channel 1 */ +#define ATIM_CCR5_GC5C2 (1 << 30) /* CCR5 only, Bit 30: Group Channel 5 and Channel 2 */ +#define ATIM_CCR5_GC5C3 (1 << 31) /* CCR5 only, Bit 31: Group Channel 5 and Channel 3 */ + +/* ATIM Break and dead-time register (BDTR) */ + +#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 0-7: Dead-Time Generator set-up */ +#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) +#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 8-9: Lock Configuration */ +#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) +# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ +#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ + +#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT) +# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ +#define ATIM_BDTR_BK2F_MASK (15 << ATIM_BDTR_BK2F_SHIFT) +# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ +# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ +#define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ +#define ATIM_BDTR_BK_DSRM (1 << 26) /* Bit 26: Break disarm */ +#define ATIM_BDTR_BK2_DSRM (1 << 27) /* Bit 27: Break 2 disarm */ +#define ATIM_BDTR_BK_BID (1 << 28) /* Bit 28: Break bidirectional */ +#define ATIM_BDTR_BK2_BID (1 << 29) /* Bit 29: Break 2 bidirectional */ + +/* ATIM Dead-time register 2 (DTR2) */ + +#define ATIM_DTR2_DTGF_SHIFT (0) /* Dead time falling edge generator setup */ +#define ATIM_DTR2_DTGF_MASK (0xff << ATIM_DTR2_DTGF_SHIFT) +#define ATIM_DTR2_DTAE (1 << 16) /* Dead time asymmetric enable */ +#define ATIM_DTR2_DTPE (1 << 17) /* Dead time preload enable */ + +/* ATIM Encoder control register (ECR) */ + +#define ATIM_ECR_IE (1 << 0) /* Index enable (indicates if index resets counter): 0=no, 1=yes */ +#define ATIM_ECR_IDIR_SHIFT (1) /* Index direction */ +#define ATIM_ECR_IDIR_MASK (0x3 << ATIM_ECR_IDIR_SHIFT) +# define ATIM_ECR_IDIR_BOTH (0x0 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter in both directions */ +# define ATIM_ECR_IDIR_UP (0x1 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting up */ +# define ATIM_ECR_IDIR_DOWN (0x2 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting down */ +#define ATIM_ECR_FIDX (1 << 5) /* First index: 0=index always resets counter, 1=only first index resets counter */ +#define ATIM_ECR_IPOS_SHIFT (6) /* Index reset position */ +#define ATIM_ECR_IPOS_MASK (0x3 << ATIM_ECR_IPOS_SHIFT) +# define ATIM_ECR_IPOS_00 (0x0 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,0 */ +# define ATIM_ECR_IPOS_01 (0x1 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,1 */ +# define ATIM_ECR_IPOS_10 (0x2 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,0 */ +# define ATIM_ECR_IPOS_11 (0x3 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,1 */ +#define ATIM_ECR_PW_SHIFT (16) /* Pulse duration in units of t[PWG], see ATIM_ECR_PWPRSC_MASK */ +#define ATIM_ECR_PW_MASK (0xff << ATIM_ECR_PW_SHIFT) +#define ATIM_ECR_PWPRSC_SHIFT (24) /* Pulse width prescaler */ +#define ATIM_ECR_PWPRSC_MASK (0x7 << ATIM_ECR_PWPRSC_SHIFT) /* t[PWG] = (2^(PWPRSC[2:0])) * t[tim_ker_ck] */ + +/* ATIM Timer input selection register (TISEL) */ + +#define ATIM_TISEL_TI1SEL_SHIFT (0) +#define ATIM_TISEL_TI1SEL_MASK (0xf << TIM_TISEL_TI1SEL_SHIFT) + +#define ATIM_TISEL_TI2SEL_SHIFT (8) +#define ATIM_TISEL_TI2SEL_MASK (0xf << TIM_TISEL_TI2SEL_SHIFT) + +#define ATIM_TISEL_TI3SEL_SHIFT (16) +#define ATIM_TISEL_TI3SEL_MASK (0xf << TIM_TISEL_TI3SEL_SHIFT) + +#define ATIM_TISEL_TI4SEL_SHIFT (24) +#define ATIM_TISEL_TI4SEL_MASK (0xf << TIM_TISEL_TI4SEL_SHIFT) + +/* ATIM Alternate function option register 1 (AF1) */ + +#define ATIM_AF1_BKINE (1 << 0) /* BRK BKIN input enable */ +#define ATIM_AF1_BKCMP1E (1 << 1) /* BRK COMP1 enable */ +#define ATIM_AF1_BKCMP2E (1 << 2) /* BRK COMP2 enable */ +#define ATIM_AF1_BKCMP3E (1 << 3) /* BRK COMP3 enable */ +#define ATIM_AF1_BKCMP4E (1 << 4) /* BRK COMP4 enable */ +#define ATIM_AF1_BKCMP5E (1 << 5) /* BRK COMP5 enable */ +#define ATIM_AF1_BKCMP6E (1 << 6) /* BRK COMP6 enable */ +#define ATIM_AF1_BKCMP7E (1 << 7) /* BRK COMP7 enable */ +#define ATIM_AF1_BKINP (1 << 9) /* BRK BKIN input polarity */ +#define ATIM_AF1_BKCMP1P (1 << 10) /* BRK COMP1 input polarity */ +#define ATIM_AF1_BKCMP2P (1 << 11) /* BRK COMP2 input polarity */ +#define ATIM_AF1_BKCMP3P (1 << 12) /* BRK COMP3 input polarity */ +#define ATIM_AF1_BKCMP4P (1 << 13) /* BRK COMP4 input polarity */ +#define ATIM_AF1_ETRSEL_SHIFT (14) /* ETR source selection) */ +#define ATIM_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_Pos) + +/* ATIM Alternate function option register 2 (AF2) */ + +#define ATIM_AF2_BK2INE (1 << 0) /* BRK2 BKIN input enable */ +#define ATIM_AF2_BK2CMP1E (1 << 1) /* BRK2 COMP1 enable */ +#define ATIM_AF2_BK2CMP2E (1 << 2) /* BRK2 COMP2 enable */ +#define ATIM_AF2_BK2CMP3E (1 << 3) /* BRK2 COMP3 enable */ +#define ATIM_AF2_BK2CMP4E (1 << 4) /* BRK2 COMP4 enable */ +#define ATIM_AF2_BK2CMP5E (1 << 5) /* BRK2 COMP5 enable */ +#define ATIM_AF2_BK2CMP6E (1 << 6) /* BRK2 COMP6 enable */ +#define ATIM_AF2_BK2CMP7E (1 << 7) /* BRK2 COMP7 enable */ +#define ATIM_AF2_BK2INP (1 << 9) /* BRK2 BKIN input polarity */ +#define ATIM_AF2_BK2CMP1P (1 << 10) /* BRK2 COMP1 input polarity */ +#define ATIM_AF2_BK2CMP2P (1 << 11) /* BRK2 COMP2 input polarity */ +#define ATIM_AF2_BK2CMP3P (1 << 12) /* BRK2 COMP3 input polarity */ +#define ATIM_AF2_BK2CMP4P (1 << 13) /* BRK2 COMP4 input polarity */ +#define ATIM_AF2_OCRSEL_SHIFT (16) /* ocref_clr source selection */ +#define ATIM_AF2_OCRSEL_MASK (0x7 << TIM1_AF2_OCRSEL_Pos) + +/* ATIM DMA control register (DCR) */ + +#define ATIM_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ +#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) +#define ATIM_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ +#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) +# define ATIM_DCR_DBL(n) (((n) - 1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Register Bitfield Definitions - GTIM *************************************/ + +/* GTIM: General Timers + * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 + * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 + * + * Caution! TIM2/5, TIM3/4, TIM15, and TIM16/17 are slightly different and + * have different registers, register sizes, and register bitfields! + */ + +/* GTIM Control register 1 (CR1) */ + +#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ +#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ +#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ +#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ +#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ +#define GTIM_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ +#define GTIM_CR1_CMS_MASK (0x3 << GTIM_CR1_CMS_SHIFT) +# define GTIM_CR1_EDGE (0x0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ +# define GTIM_CR1_CENTER1 (0x1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ +# define GTIM_CR1_CENTER2 (0x2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ +# define GTIM_CR1_CENTER3 (0x3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ +#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ +#define GTIM_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ +#define GTIM_CR1_CKD_MASK (0x3 << GTIM_CR1_CKD_SHIFT) +# define GTIM_CR1_TCKINT (0x0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS=1*tCK_INT */ +# define GTIM_CR1_2TCKINT (0x1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ +# define GTIM_CR1_4TCKINT (0x2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ +#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ +#define GTIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering enable */ + +/* GTIM Control register 2 (CR2) */ + +#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ +#define GTIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ +#define GTIM_CR2_MMS_MASK (0x200007 << GTIM_CR2_MMS_SHIFT) +# define GTIM_CR2_MMS_RESET (0x0 << GTIM_CR2_MMS_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRGO */ +# define GTIM_CR2_MMS_ENABLE (0x1 << GTIM_CR2_MMS_SHIFT) /* 0001: Enable - CNT_EN is TRGO */ +# define GTIM_CR2_MMS_UPDATE (0x2 << GTIM_CR2_MMS_SHIFT) /* 0010: Update event is TRGO */ +# define GTIM_CR2_MMS_COMPP (0x3 << GTIM_CR2_MMS_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ +# define GTIM_CR2_MMS_OC1REF (0x4 << GTIM_CR2_MMS_SHIFT) /* 0100: Compare OC1REF is TRGO */ +# define GTIM_CR2_MMS_OC2REF (0x5 << GTIM_CR2_MMS_SHIFT) /* 0101: Compare OC2REF is TRGO */ +# define GTIM_CR2_MMS_OC3REF (0x6 << GTIM_CR2_MMS_SHIFT) /* 0110: Compare OC3REF is TRGO */ +# define GTIM_CR2_MMS_OC4REF (0x7 << GTIM_CR2_MMS_SHIFT) /* 0111: Compare OC4REF is TRGO */ +# define GTIM_CR2_MMS_ENCODER (0x200000 << GTIM_CR2_MMS_SHIFT) /* 1000: Encoder clock is TRGO */ +#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ + +/* GTIM Slave mode control register (SMCR) */ + +#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ +#define GTIM_SMCR_SMS_MASK (0x10007 << GTIM_SMCR_SMS_SHIFT) +# define GTIM_SMCR_DISAB (0x0 << GTIM_SMCR_SMS_SHIFT) /* 0000: Slave mode disabled */ +# define GTIM_SMCR_ENCMD1 (0x1 << GTIM_SMCR_SMS_SHIFT) /* 0001: Encoder mode 1 */ +# define GTIM_SMCR_ENCMD2 (0x2 << GTIM_SMCR_SMS_SHIFT) /* 0010: Encoder mode 2 */ +# define GTIM_SMCR_ENCMD3 (0x3 << GTIM_SMCR_SMS_SHIFT) /* 0011: Encoder mode 3 */ +# define GTIM_SMCR_RESET (0x4 << GTIM_SMCR_SMS_SHIFT) /* 0100: Reset Mode */ +# define GTIM_SMCR_GATED (0x5 << GTIM_SMCR_SMS_SHIFT) /* 0101: Gated Mode */ +# define GTIM_SMCR_TRIGGER (0x6 << GTIM_SMCR_SMS_SHIFT) /* 0110: Trigger Mode */ +# define GTIM_SMCR_EXTCLK1 (0x7 << GTIM_SMCR_SMS_SHIFT) /* 0111: External Clock Mode 1 */ +# define GTIM_SMCR_RESET_TRIGGER (0x10000 << GTIM_SMCR_SMS_SHIFT) /* 1000: Combined reset + trigger */ +# define GTIM_SMCR_GATED_RESET (0x10001 << GTIM_SMCR_SMS_SHIFT) /* 1001: Combined gated + reset */ +# define GTIM_SMCR_ENCMD4 (0x10002 << GTIM_SMCR_SMS_SHIFT) /* 1010: Encoder mode 4 */ +# define GTIM_SMCR_ENCMD5 (0x10003 << GTIM_SMCR_SMS_SHIFT) /* 1011: Encoder mode 5 */ +# define GTIM_SMCR_ENCMD6 (0x10004 << GTIM_SMCR_SMS_SHIFT) /* 1100: Encoder mode 6 */ +# define GTIM_SMCR_ENCMD7 (0x10005 << GTIM_SMCR_SMS_SHIFT) /* 1101: Encoder mode 7 */ +# define GTIM_SMCR_ENCMD8 (0x10006 << GTIM_SMCR_SMS_SHIFT) /* 1110: Encoder mode 8 */ +# define GTIM_SMCR_ENCMD9 (0x10007 << GTIM_SMCR_SMS_SHIFT) /* 1111: Encoder mode 9 */ +#define GTIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ +#define GTIM_SMCR_TS_MASK (0x30007 << GTIM_SMCR_TS_SHIFT) +# define GTIM_SMCR_ITR0 (0x0 << GTIM_SMCR_TS_SHIFT) /* 00 000: Internal trigger 0 (ITR0) */ +# define GTIM_SMCR_ITR1 (0x1 << GTIM_SMCR_TS_SHIFT) /* 00 001: Internal trigger 1 (ITR1) */ +# define GTIM_SMCR_ITR2 (0x2 << GTIM_SMCR_TS_SHIFT) /* 00 010: Internal trigger 2 (ITR2) */ +# define GTIM_SMCR_ITR3 (0x3 << GTIM_SMCR_TS_SHIFT) /* 00 011: Internal trigger 3 (ITR3) */ +# define GTIM_SMCR_TI1FED (0x4 << GTIM_SMCR_TS_SHIFT) /* 00 100: TI1 Edge Detector (TI1F_ED) */ +# define GTIM_SMCR_TI1FP1 (0x5 << GTIM_SMCR_TS_SHIFT) /* 00 101: Filtered Timer Input 1 (TI1FP1) */ +# define GTIM_SMCR_TI2FP2 (0x6 << GTIM_SMCR_TS_SHIFT) /* 00 110: Filtered Timer Input 2 (TI2FP2) */ +# define GTIM_SMCR_ETRF (0x7 << GTIM_SMCR_TS_SHIFT) /* 00 111: External Trigger Input (ETRF) */ +# define GTIM_SMCR_ITR4 (0x1000 << GTIM_SMCR_TS_SHIFT) /* 01 000: Internal Trigger 0 ITR4 */ +# define GTIM_SMCR_ITR5 (0x1001 << GTIM_SMCR_TS_SHIFT) /* 01 001: Internal Trigger 1 ITR5 */ +# define GTIM_SMCR_ITR6 (0x1002 << GTIM_SMCR_TS_SHIFT) /* 01 010: Internal Trigger 1 ITR6 */ +# define GTIM_SMCR_ITR7 (0x1003 << GTIM_SMCR_TS_SHIFT) /* 01 011: Internal Trigger 1 ITR7 */ +# define GTIM_SMCR_ITR8 (0x1004 << GTIM_SMCR_TS_SHIFT) /* 01 100: Internal Trigger 1 ITR8 */ +# define GTIM_SMCR_ITR9 (0x1005 << GTIM_SMCR_TS_SHIFT) /* 01 101: Internal Trigger 1 ITR9 */ +# define GTIM_SMCR_ITR10 (0x1006 << GTIM_SMCR_TS_SHIFT) /* 01 110: Internal Trigger 1 ITR10 */ +#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ +#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ +#define GTIM_SMCR_ETF_MASK (0xf << GTIM_SMCR_ETF_SHIFT) +# define GTIM_SMCR_NOFILT (0x0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ +# define GTIM_SMCR_FCKINT2 (0x1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_SMCR_FCKINT4 (0x2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_SMCR_FCKINT8 (0x3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_SMCR_FDTSd26 (0x4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_SMCR_FDTSd28 (0x5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_SMCR_FDTSd46 (0x6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_SMCR_FDTSd48 (0x7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_SMCR_FDTSd86 (0x8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_SMCR_FDTSd88 (0x9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_SMCR_FDTSd165 (0xa << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_SMCR_FDTSd166 (0xb << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_SMCR_FDTSd168 (0xc << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_SMCR_FDTSd325 (0xd << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_SMCR_FDTSd326 (0xe << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_SMCR_FDTSd328 (0xf << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ +#define GTIM_SMCR_ETPS_MASK (0x3 << GTIM_SMCR_ETPS_SHIFT) +# define GTIM_SMCR_PSCOFF (0x0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ +# define GTIM_SMCR_ETRPd2 (0x1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ +# define GTIM_SMCR_ETRPd4 (0x2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ +# define GTIM_SMCR_ETRPd8 (0x3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ +#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ +#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ +#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ +#define GTIM_SMCR_SMSPE (1 << 24) /* Bit 24: SMS preload enable */ +#define GTIM_SMCR_SMSPS (1 << 25) /* Bit 25: SMS preload source */ + +/* GTIM DMA/Interrupt enable register (DIER) */ + +#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ +#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ +#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ +#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ +#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ +#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ +#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ +#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ +#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ +#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ +#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ +#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ +#define GTIM_DIER_IDXIE (1 << 20) /* Bit 20: Index interrupt enable */ +#define GTIM_DIER_DIRIE (1 << 21) /* Bit 21: Direction change interrupt enable */ +#define GTIM_DIER_IERRIE (1 << 22) /* Bit 22: Index error interrupt enable */ +#define GTIM_DIER_TERRIE (1 << 23) /* Bit 23: Transition error interrupt enable */ + +/* GTIM Status register (SR) */ + +#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ +#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 Interrupt Flag */ +#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 Interrupt Flag */ +#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 Interrupt Flag */ +#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 Interrupt Flag */ +#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger Interrupt Flag */ +#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ +#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ +#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ +#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ +#define GTIM_SR_IDXF (1 << 20) /* Bit 20: Index Interrupt Flag */ +#define GTIM_SR_DIRF (1 << 21) /* Bit 21: Direction Change Interrupt Flag */ +#define GTIM_SR_IERRF (1 << 22) /* Bit 22: Index Error Interrupt Flag */ +#define GTIM_SR_TERRF (1 << 23) /* Bit 23: Transition Error Interrupt Flag */ + +/* GTIM Event generation register (EGR) */ + +#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ +#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ +#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ +#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ +#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ +#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ + +/* GTIM Capture/compare mode registers (CCMR1) - Output Compare Mode */ + +#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ +#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ +#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ +#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode */ +#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ +#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ +#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ +#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ +#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode */ +#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ +#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ +#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ + +/* GTIM Common CCMR (unshifted) Capture/Compare Selection + * bit-field definitions + */ + +#define GTIM_CCMR_CCS_CCOUT (0x0) /* 00: CCx channel output */ +#define GTIM_CCMR_CCS_CCIN1 (0x1) /* 01: CCx channel input, ICx is TIx */ +#define GTIM_CCMR_CCS_CCIN2 (0x2) /* 10: CCx channel input, ICx is TIy */ +#define GTIM_CCMR_CCS_CCINTRC (0x3) /* 11: CCx channel input, ICx is TRC */ + +/* GTIM Common CCMR (unshifted) Compare Mode bit field definitions */ + +#define GTIM_CCMR_MODE_FRZN (0x0) /* 0000: Frozen */ +#define GTIM_CCMR_MODE_CHACT (0x1) /* 0001: Channel x active on match */ +#define GTIM_CCMR_MODE_CHINACT (0x2) /* 0010: Channel x inactive on match */ +#define GTIM_CCMR_MODE_OCREFTOG (0x3) /* 0011: OCxREF toggle GTIM_CNT=GTIM_CCRx */ +#define GTIM_CCMR_MODE_OCREFLO (0x4) /* 0100: OCxREF forced low */ +#define GTIM_CCMR_MODE_OCREFHI (0x5) /* 0101: OCxREF forced high */ +#define GTIM_CCMR_MODE_PWM1 (0x6) /* 0110: PWM mode 1 */ +#define GTIM_CCMR_MODE_PWM2 (0x7) /* 0111: PWM mode 2 */ +#define GTIM_CCMR_MODE_OPM1 (0x8) /* 1000: Retriggerable OPM mode 1 */ +#define GTIM_CCMR_MODE_OPM2 (0x9) /* 1001: Retriggerable OPM mode 2 */ +#define GTIM_CCMR_MODE_COMBINED1 (0xc) /* 1100: Combined PWM mode 1 */ +#define GTIM_CCMR_MODE_COMBINED2 (0xd) /* 1101: Combined PWM mode 2 */ +#define GTIM_CCMR_MODE_ASYMMETRIC1 (0xe) /* 1110: Asymmetric PWM mode 1 */ +#define GTIM_CCMR_MODE_ASYMMETRIC2 (0xf) /* 1111: Asymmetric PWM mode 2 */ + +/* GTIM Capture/compare mode register 1 (CCMR1) - Input Capture Mode + * Bits 0-1 and Bits 8-9 are same as Output Compare Mode + */ + +#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ +#define GTIM_CCMR1_IC1PSC_MASK (0x3 << GTIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ +#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ +#define GTIM_CCMR1_IC2PSC_MASK (0x3 << GTIM_CCMR1_IC2PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ +#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ +#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) /* (See common (unshifted) bit field definitions below) */ + +/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ + +#define GTIM_CCMR_ICPSC_NOPSC (0x0) /* 00: no prescaler, capture each edge */ +#define GTIM_CCMR_ICPSC_EVENTS2 (0x1) /* 01: capture once every 2 events */ +#define GTIM_CCMR_ICPSC_EVENTS4 (0x2) /* 10: capture once every 4 events */ +#define GTIM_CCMR_ICPSC_EVENTS8 (0x3) /* 11: capture once every 8 events */ + +/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ + +#define GTIM_CCMR_ICF_NOFILT (0x0) /* 0000: No filter, sampling at fDTS */ +#define GTIM_CCMR_ICF_FCKINT2 (0x1) /* 0001: fSAMPLING=fCK_INT, N=2 */ +#define GTIM_CCMR_ICF_FCKINT4 (0x2) /* 0010: fSAMPLING=fCK_INT, N=4 */ +#define GTIM_CCMR_ICF_FCKINT8 (0x3) /* 0011: fSAMPLING=fCK_INT, N=8 */ +#define GTIM_CCMR_ICF_FDTSd26 (0x4) /* 0100: fSAMPLING=fDTS/2, N=6 */ +#define GTIM_CCMR_ICF_FDTSd28 (0x5) /* 0101: fSAMPLING=fDTS/2, N=8 */ +#define GTIM_CCMR_ICF_FDTSd46 (0x6) /* 0110: fSAMPLING=fDTS/4, N=6 */ +#define GTIM_CCMR_ICF_FDTSd48 (0x7) /* 0111: fSAMPLING=fDTS/4, N=8 */ +#define GTIM_CCMR_ICF_FDTSd86 (0x8) /* 1000: fSAMPLING=fDTS/8, N=6 */ +#define GTIM_CCMR_ICF_FDTSd88 (0x9) /* 1001: fSAMPLING=fDTS/8, N=8 */ +#define GTIM_CCMR_ICF_FDTSd165 (0xa) /* 1010: fSAMPLING=fDTS/16, N=5 */ +#define GTIM_CCMR_ICF_FDTSd166 (0xb) /* 1011: fSAMPLING=fDTS/16, N=6 */ +#define GTIM_CCMR_ICF_FDTSd168 (0xc) /* 1100: fSAMPLING=fDTS/16, N=8 */ +#define GTIM_CCMR_ICF_FDTSd325 (0xd) /* 1101: fSAMPLING=fDTS/32, N=5 */ +#define GTIM_CCMR_ICF_FDTSd326 (0xe) /* 1110: fSAMPLING=fDTS/32, N=6 */ +#define GTIM_CCMR_ICF_FDTSd328 (0xf) /* 1111: fSAMPLING=fDTS/32, N=8 */ + +/* GTIM Capture/compare mode register 2 (CCMR2) - Output Compare Mode */ + +#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ +#define GTIM_CCMR2_CC3S_MASK (0x3 << GTIM_CCMR2_CC3S_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ +#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ +#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode */ +#define GTIM_CCMR2_OC3M_MASK (0x7 << GTIM_CCMR2_OC3M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ +#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ +#define GTIM_CCMR2_CC4S_MASK (0x3 << GTIM_CCMR2_CC4S_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ +#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ +#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode */ +#define GTIM_CCMR2_OC4M_MASK (0x7 << GTIM_CCMR2_OC4M_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ +#define GTIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ +#define GTIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ + +/* GTIM Capture/compare mode register 2 (CCMR2) - Input Capture Mode + * Bits 0-1 and Bits 8-9 are same as Output Compare Mode + */ + +#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ +#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ +#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ +#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ +#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ +#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) /* (See common (unshifted) bit field definitions above) */ + +/* GTIM Capture/compare enable register (CCER) */ + +#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 Output Enable */ +#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 Output Polarity */ +#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary Output Polarity */ +#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 Output Enable */ +#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 Output Polarity */ +#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary Output Polarity */ +#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 Output Enable */ +#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 Output Polarity */ +#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary Output Polarity */ +#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ +#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ +#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ +#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ + +/* GTIM Counter (CNT) */ + +#define GTIM_CNT_SHIFT (0) /* Bits 0-15, 0-30, or 0-31: Timer counter value */ +#define GTIM_CNT_MASK16 (0xffff << GTIM_CNT_SHIFT) /* Bits 0-15 - 16-bit counter value */ +#define GTIM_CNT_MASK31 (0x7fffffff << GTIM_CNT_SHIFT) /* Bits 0-30 - 31-bit counter value, 32-bit counters only */ +#define GTIM_CNT_MASK32 (0xffffffff << GTIM_CNT_SHIFT) /* Bits 0-31 - 32-bit counter value, 32-bit counters only */ +#define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy, if not using this bit for counter */ + +/* GTIM Prescaler (PSC) */ + +#define GTIM_PSC_SHIFT (0) +#define GTIM_PSC_MASK (0xffff << GTIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ + +/* GTIM Auto-reload register (ARR) */ + +#define GTIM_ARR_SHIFT (0) +#define GTIM_ARR_MASK_20 (0xfffff << GTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register */ +#define GTIM_ARR_MASK_32 (0xffffffff << GTIM_ARR_SHIFT) /* Bits 0-31: Auto reload register, 32-bit counters only */ + +/* GTIM Repetition counter register (16-bit, TIM15 only) */ + +#define GTIM_RCR_SHIFT (0) +#define GTIM_RCR_MASK (0xff << GTIM_RCR_SHIFT) + +/* GTIM Capture/compare register 1 (CCR1 - CCR4) */ + +#define GTIM_CCR_SHIFT (0) +#define GTIM_CCR_MASK_20 (0xfffff << GTIM_CCR_SHIFT) /* Bits 0-19: Capture/compare 1 value */ +#define GTIM_CCR_MASK_32 (0xffffffff << GTIM_CCR_SHIFT) /* Bits 0-31: Capture/compare 1 value, 32-bit timers only */ + +/* GTIM Break and dead-time register (BDTR) - TIM15-TIM17 only */ + +#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 0-7: Dead-Time Generator set-up */ +#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) +#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 8-9: Lock Configuration */ +#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) +# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ +# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ +# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ +# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ +#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ +#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ +#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ +#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ +#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ +#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ + +#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ +#define GTIM_BDTR_BKF_MASK (15 << GTIM_BDTR_BKF_SHIFT) +# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ +# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ +# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ +# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ +# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ +# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ +# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ +# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ +# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ +# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ +# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ +# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ +# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ +# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ +# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ +# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ +#define GTIM_BDTR_BK_DSRM (1 << 26) /* Bit 26: Break disarm */ +#define GTIM_BDTR_BK_BID (1 << 28) /* Bit 28: Break bidirectional */ + +/* GTIM Option register 1 (OR1) - TIM16, TIM17 only */ + +#define GTIM_OR1_HSE32EN (1 << 0) /* Bit 1: HSE divide by 32 for tim_ti1_in3 */ + +/* GTIM Dead-time register 2 (DTR2) */ + +#define GTIM_DTR2_DTGF_SHIFT (0) /* Dead time falling edge generator setup */ +#define GTIM_DTR2_DTGF_MASK (0xff << GTIM_DTR2_DTGF_SHIFT) +#define GTIM_DTR2_DTAE (1 << 16) /* Dead time asymmetric enable */ +#define GTIM_DTR2_DTPE (1 << 17) /* Dead time preload enable */ + +/* GTIM Encoder control register (ECR) */ + +#define GTIM_ECR_IE (1 << 0) /* Index enable (indicates if index resets counter): 0=no, 1=yes */ +#define GTIM_ECR_IDIR_SHIFT (1) /* Index direction */ +#define GTIM_ECR_IDIR_MASK (0x3 << GTIM_ECR_IDIR_SHIFT) +# define GTIM_ECR_IDIR_BOTH (0x0 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter in both directions */ +# define GTIM_ECR_IDIR_UP (0x1 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting up */ +# define GTIM_ECR_IDIR_DOWN (0x2 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting down */ +#define GTIM_ECR_FIDX (1 << 5) /* First index: 0=index always resets counter, 1=only first index resets counter */ +#define GTIM_ECR_IPOS_SHIFT (6) /* Index reset position */ +#define GTIM_ECR_IPOS_MASK (0x3 << GTIM_ECR_IPOS_SHIFT) +# define GTIM_ECR_IPOS_00 (0x0 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,0 */ +# define GTIM_ECR_IPOS_01 (0x1 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,1 */ +# define GTIM_ECR_IPOS_10 (0x2 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,0 */ +# define GTIM_ECR_IPOS_11 (0x3 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,1 */ +#define GTIM_ECR_PW_SHIFT (16) /* Pulse duration in units of t[PWG], see GTIM_ECR_PWPRSC_MASK */ +#define GTIM_ECR_PW_MASK (0xff << GTIM_ECR_PW_SHIFT) +#define GTIM_ECR_PWPRSC_SHIFT (24) /* Pulse width prescaler */ +#define GTIM_ECR_PWPRSC_MASK (0x7 << GTIM_ECR_PWPRSC_SHIFT) /* t[PWG] = (2^(PWPRSC[2:0])) * t[tim_ker_ck] */ + +/* GTIM Timer input selection register (TISEL) */ + +#define GTIM_TISEL_TI1SEL_SHIFT (0) /* TIM2-TIM5, TIM15-TIM17 */ +#define GTIM_TISEL_TI1SEL_MASK (0xf << TIM_TISEL_TI1SEL_SHIFT) + +#define GTIM_TISEL_TI2SEL_SHIFT (8) /* TIM2-TIM5, TIM15 */ +#define GTIM_TISEL_TI2SEL_MASK (0xf << TIM_TISEL_TI2SEL_SHIFT) + +#define GTIM_TISEL_TI3SEL_SHIFT (16) /* TIM2-TIM5 */ +#define GTIM_TISEL_TI3SEL_MASK (0xf << TIM_TISEL_TI3SEL_SHIFT) + +#define GTIM_TISEL_TI4SEL_SHIFT (24) /* TIM2-TIM5 */ +#define GTIM_TISEL_TI4SEL_MASK (0xf << TIM_TISEL_TI4SEL_SHIFT) + +/* GTIM Alternate function option register 1 (AF1) */ + +#define GTIM_AF1_BKINE (1 << 0) /* BRK BKIN input enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP1E (1 << 1) /* BRK COMP1 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP2E (1 << 2) /* BRK COMP2 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP3E (1 << 3) /* BRK COMP3 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP4E (1 << 4) /* BRK COMP4 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP5E (1 << 5) /* BRK COMP5 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP6E (1 << 6) /* BRK COMP6 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP7E (1 << 7) /* BRK COMP7 enable TIM15-TIM17 only */ +#define GTIM_AF1_BKINP (1 << 9) /* BRK BKIN input polarity TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP1P (1 << 10) /* BRK COMP1 input polarity TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP2P (1 << 11) /* BRK COMP2 input polarity TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP3P (1 << 12) /* BRK COMP3 input polarity TIM15-TIM17 only */ +#define GTIM_AF1_BKCMP4P (1 << 13) /* BRK COMP4 input polarity TIM15-TIM17 only */ +#define GTIM_AF1_ETRSEL_SHIFT (14) /* ETR source selection) TIM2-TIM5 only */ +#define GTIM_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_Pos) + +/* GTIM Alternate function option register 2 (AF2) */ + +#define GTIM_AF2_OCRSEL_SHIFT (16) /* ocref_clr source selection */ +#define GTIM_AF2_OCRSEL_MASK (0x7 << TIM1_AF2_OCRSEL_Pos) + +/* GTIM DMA control register (DCR) */ + +#define GTIM_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ +#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) +#define GTIM_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ +#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) +# define GTIM_DCR_DBL(n) (((n) - 1) << GTIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ + +/* Register Bitfield Definitions - BTIM *************************************/ + +/* BTIM: Basic Timers - TIM6 and TIM7 */ + +/* BTIM Control register 1 (CR1) */ + +#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter Enable */ +#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ +#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ +#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ +#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ +#define BTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping: 1=copy UIF bit to bit 32 of CNT register */ +#define BTIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering Enable (can change only when CEN bit is 0) */ + +/* BTIM Control register 2 (CR2) */ + +#define BTIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ +#define BTIM_CR2_MMS_MASK (0x7 << BTIM_CR2_MMS_SHIFT) +# define BTIM_CR2_RESET (0x0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ +# define BTIM_CR2_ENAB (0x1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ +# define BTIM_CR2_UPDT (0x2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ + +/* BTIM DMA/Interrupt enable register (DIER) */ + +#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ +#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ + +/* BTIM Status register (SR) */ + +#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ + +/* BTIM Event generation register (EGR) */ + +#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ + +/* BTIM Counter (CNT) */ + +#define BTIM_CNT_SHIFT (0) /* Bits 0-15: 16-bit timer counter value */ +#define BTIM_CNT_MASK (0xffff << BTIM_CNT_SHIFT) +#define BTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy, if BTIM_CR1_UIFREMAP */ + +/* BTIM Prescaler (PSC) */ + +#define BTIM_PSC_SHIFT (0) +#define BTIM_PSC_MASK (0xffff << BTIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ + +/* BTIM Auto-reload register (ARR) */ + +#define BTIM_ARR_SHIFT (0) /* Bits 0-15 or 0-19: Auto reload register */ +#define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */ +#define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h index 7149293388a29..211e43f7d514e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H /**************************************************************************** * Included Files @@ -1148,4 +1148,4 @@ #define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/common/stm32/hardware/stm32_uart.h similarity index 63% rename from arch/arm/src/stm32f0l0g0/stm32_serial.c rename to arch/arm/src/common/stm32/hardware/stm32_uart.h index 5edb01036ef7e..471eb707aefbb 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/common/stm32/hardware/stm32_uart.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.c + * arch/arm/src/common/stm32/hardware/stm32_uart.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,6 +20,9 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H + /**************************************************************************** * Included Files ****************************************************************************/ @@ -27,20 +30,23 @@ #include #include "chip.h" -/* This file is only a thin shell that includes the correct serial - * implementation for the selected STM32 IP core: - * - STM32 UART IP version 1 - F0, L0 - * - STM32 UART IP version 2 - G0 - */ +#if (defined(CONFIG_STM32_HAVE_IP_USART_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V4)) > 1 +# error Only one STM32 USART IP version must be selected +#endif #if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_serial_v1.c" +# include "hardware/stm32_uart_v1.h" #elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_serial_v2.c" +# include "hardware/stm32_uart_v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V3) +# include "hardware/stm32_uart_v3.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "hardware/stm32_uart_v4.h" #else -# error "Unsupported STM32 M0 serial" +# error "Unsupported STM32 USART core" #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h new file mode 100644 index 0000000000000..3938a7f13fdf8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h new file mode 100644 index 0000000000000..02f3811c221a8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 5 +# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 6 +# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 7 +# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h new file mode 100644 index 0000000000000..be5e3970c9268 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h @@ -0,0 +1,331 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v3.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */ +#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */ +#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) + +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */ +#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) + +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | \ + USART_CR1_TCIE | USART_CR1_TXEIE | \ + USART_CR1_PEIE | USART_CR1_CMIE| \ + USART_CR1_RTOIE | USART_CR1_EOBIE) + +/* Control register 2 */ + +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ + +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */ + +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */ +#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */ +#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */ +#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */ + +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ + +#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ +#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) +#define USART_CR2_ADD8_SHIFT USART_CR2_ADD_SHIFT /* F1/F2/F4-compatible name */ +#define USART_CR2_ADD8_MASK USART_CR2_ADD_MASK + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */ +#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */ +#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */ +#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */ +#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 17-19: Smart card auto retry count */ +#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ +#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ +#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ + +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ +#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */ +#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) + +/* Request Register */ + +#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ +#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */ +#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ +#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ +#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ + +/* Interrupt and Status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */ +#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */ +#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */ +#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */ +#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ +#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ + +#define USART_ISR_ALLBITS (0x007fdfff) + +/* ICR */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ +#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ + +/* Receive Data register */ + +#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_RDR_MASK (0xff << USART_RDR_SHIFT) + +/* Transmit Data register */ + +#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_TDR_MASK (0xff << USART_TDR_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h new file mode 100644 index 0000000000000..8f8f0900c9334 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h @@ -0,0 +1,390 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v4.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART4_PRESC (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Control register 1 */ + +#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ +#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in low-power mode */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ +#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */ +#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ +#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ +#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ +#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) +# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT) +#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ +#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) +# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT) +#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ +#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length, bit 1 */ +#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */ +#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */ +#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */ + +#define USART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ + USART_CR1_TXFEIE | USART_CR1_RXFFIE) + +/* LPUART shares the USART CR1 layout but has no receiver-timeout or + * end-of-block interrupts. + */ + +#define LPUART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) + +/* Control register 2 */ + +#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ +#define USART_CR2_DISNSS (1 << 3) /* Bit 3: Ignore NSS pin input */ +#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-/4-bit Address Detection */ +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ +#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ +#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ +#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ +#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ +#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ +#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ +#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) +# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ +# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ +# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ +# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ + +#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ +#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ +#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) +# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT) +#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ +#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT) +# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT) +#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ +#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) +# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT) + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ +#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ +#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ +#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ +#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ +#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ +#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) +# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_ADDR (0 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_RXFNE (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup interrupt enable */ +#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ +#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) +# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) +# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */ +# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */ +# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */ +# define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */ +# define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */ +# define USART_CR3_RXFTCFG_FULL (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */ + +#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */ +#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */ +#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT) +# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT) +# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */ +# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */ +# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */ +# define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */ +# define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */ +# define USART_CR3_TXFTCFG_EMPY (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */ + +/* Baud Rate Register */ + +#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ +#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) +# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT) + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) +# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT) + +/* Receiver timeout register */ + +#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ +#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) +# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ +#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) +# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) + +/* Request register */ + +#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ +#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ +#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ +#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ +#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ + +/* Interrupt & status register */ + +#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ +#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ +#define USART_ISR_NE (1 << 2) /* Bit 2: Noise detected flag */ +#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ +#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ +#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ +#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ +#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ +#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ +#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ +#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ +#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ +#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */ +#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ +#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ +#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ +#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ +#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ +#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ +#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from low-power mode flag */ +#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ +#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ +#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO Empty */ +#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO Full */ +#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */ +#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold flag */ +#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold flag */ + +#define USART_ISR_ALLBITS (0x0fffffff) + +/* Interrupt flag clear register */ + +#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ +#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ +#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ +#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ +#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ +#define USART_ICR_TXFECF (1 << 5) /* Bit 5: TXFIFO empty clear flag */ +#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ +#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7: Transmission complete before Guard time clear flag */ +#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ +#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ +#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ +#define USART_ICR_UDRCF (1 << 13) /* Bit 13:SPI slave underrun clear flag */ +#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ +#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */ + +#define USART_ICR_ALLBITS (0x00123b7f) + +/* Receive data register */ + +#define USART_RDR_SHIFT (0) /* Bits 0-8: Receive data value */ +#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) + +/* Transmit data register */ + +#define USART_TDR_SHIFT (0) /* Bits 0-8: Transmit data value */ +#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) + +/* Prescaler register */ + +#define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ +#define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) +# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ +# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ +# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ +# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ +# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ +# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ +# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ +# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ +# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ +# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ +# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ +# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ + +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h new file mode 100644 index 0000000000000..ae78216c98a14 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)) > 1 +# error Only one STM32 USB device IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) +# include "hardware/stm32_usbdev_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) +# include "hardware/stm32_usbdev_v1.h" +#else +# error "Unsupported STM32 USB device" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h index 52f0df5aef25d..d40fb53b23aba 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H /**************************************************************************** * Included Files @@ -252,4 +252,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h index a2c0e40029465..2a7b97f4936f4 100644 --- a/arch/arm/src/stm32/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H /**************************************************************************** * Included Files @@ -224,4 +224,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbfs.h b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h new file mode 100644 index 0000000000000..cd0fc28018445 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h @@ -0,0 +1,250 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32_USBFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ + +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ + +/* Common Registers */ + +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ + +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Addresses *******************************************************/ + +/* Endpoint Registers */ + +#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) + +/* Common Registers */ + +#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET) + +/* Buffer Descriptor Table (Relatative to BTABLE address) */ + +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* USB endpoint register */ + +#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ +#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) +#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ +#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) +# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ +# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ +# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ +# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ +# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ +# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ + +#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ +#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ +#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ +#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ +#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) +# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ +# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ +# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ +# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ + +#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ +#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ +#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) +# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ +# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ +# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ +# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ +# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ +# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ + +#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ +#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ + +/* USB control register */ + +#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ +#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ +#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ +#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ +#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ +#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ +#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ +#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ + +#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ + USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) + +/* USB interrupt status register */ + +#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ +#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) +#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ +#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ +#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ +#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ +#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ +#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ +#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ +#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ + +#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ + USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) + +/* USB frame number register */ + +#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ +#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) +#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ +#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) +#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ +#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ +#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ + +/* USB device address */ + +#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ +#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) +#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ + +/* Buffer table address */ + +#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ +#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) + +/* Transmission buffer address */ + +#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ +#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ +#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) + +/* Transmission byte count */ + +#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ +#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) + +/* Reception buffer address */ + +#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ +#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ +#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) + +/* Reception byte count */ + +#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ +#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ +#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) +#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ +#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) + +/* LPM control and status register */ + +#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ +#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ +#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ +#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */ +#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT) + +/* Battery charging detector */ + +#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ +#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ +#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ +#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ +#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ +#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ +#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ +#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ +#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ + +#endif /* CONFIG_STM32_USBFS */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg.h new file mode 100644 index 0000000000000..2a24642f30780 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)) > 1 +# error Only one STM32 WDG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) +# include "hardware/stm32_wdg_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) +# include "hardware/stm32_wdg_v1v2.h" +#else +# error "Unsupported STM32 WDG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h index 824bf9c6a7dca..eb366fccc3706 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H /**************************************************************************** * Included Files @@ -138,4 +138,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h index 55ac57d3b64de..8febf5740cb0f 100644 --- a/arch/arm/src/stm32/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H /**************************************************************************** * Included Files @@ -147,4 +147,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdt.h b/arch/arm/src/common/stm32/hardware/stm32_wdt.h new file mode 100644 index 0000000000000..d99695aa858f0 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdt.h @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdt.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ + +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ + +/* Register Addresses *******************************************************/ + +#define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE + STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE + STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE + STM32_IWDG_WINR_OFFSET) + +#define STM32_WWDG_CR (STM32_WWDG_BASE + STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Key register (32-bit) */ + +#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ +#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) + +#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ +#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ +#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ +#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ + +/* Prescaler register (32-bit) */ + +#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ +#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) +# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ +# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ +# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ +# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ +# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ +# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ +# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ + +/* Reload register (32-bit) */ + +#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ +#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) + +#define IWDG_RLR_MAX (0xfff) + +/* Status register (32-bit) */ + +#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ +#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ +#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */ + +/* Window register (32-bit) */ + +#define IWDG_WINR_SHIFT (0) +#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) + +/* Control Register (32-bit) */ + +#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) +# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) +#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ + +/* Configuration register (32-bit) */ + +#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ +#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) +#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ +#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) +# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ +# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ +# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ +# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ + +#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ + +/* Status register (32-bit) */ + +#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h new file mode 100644 index 0000000000000..610531a01d818 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h @@ -0,0 +1,1115 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* General definitions */ + +#define OTGFS_EPTYPE_CTRL (0) /* Control */ +#define OTGFS_EPTYPE_ISOC (1) /* Isochronous */ +#define OTGFS_EPTYPE_BULK (2) /* Bulk */ +#define OTGFS_EPTYPE_INTR (3) /* Interrupt */ + +#define OTGFS_PID_DATA0 (0) +#define OTGFS_PID_DATA2 (1) +#define OTGFS_PID_DATA1 (2) +#define OTGFS_PID_MDATA (3) /* Non-control */ +#define OTGFS_PID_SETUP (3) /* Control */ + +/* Register Offsets *********************************************************/ + +/* Core global control and status registers */ + +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ +#define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ +#define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ + +/* Host-mode control and status registers */ + +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ + +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ + +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ +#define STM32_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ +#define STM32_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ +#define STM32_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ +#define STM32_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ +#define STM32_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ +#define STM32_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ +#define STM32_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ + +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ +#define STM32_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ +#define STM32_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ +#define STM32_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ +#define STM32_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ +#define STM32_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ +#define STM32_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ +#define STM32_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ + +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ +#define STM32_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ + +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ +#define STM32_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ +#define STM32_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ +#define STM32_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ +#define STM32_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ +#define STM32_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ +#define STM32_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ +#define STM32_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ + +/* Device-mode control and status registers */ + +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ + +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ + +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ +#define STM32_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ +#define STM32_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ +#define STM32_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ + +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ +#define STM32_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ +#define STM32_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ +#define STM32_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ +#define STM32_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ +#define STM32_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ +#define STM32_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ + +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ +#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ + +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ + +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ +#define STM32_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ +#define STM32_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ + +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ +#define STM32_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ +#define STM32_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ +#define STM32_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ + +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ +#define STM32_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ +#define STM32_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ +#define STM32_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ + +/* Power and clock gating registers */ + +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) + +#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ + +#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ + +#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ + +#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ +#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ + +/* Register Addresses *******************************************************/ + +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) + +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_DIEPTXF1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF1_OFFSET) +#define STM32_OTGFS_DIEPTXF2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF2_OFFSET) +#define STM32_OTGFS_DIEPTXF3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF3_OFFSET) + +/* Host-mode control and status registers */ + +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) + +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) + +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR0 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR0_OFFSET) +#define STM32_OTGFS_HCCHAR1 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR1_OFFSET) +#define STM32_OTGFS_HCCHAR2 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR2_OFFSET) +#define STM32_OTGFS_HCCHAR3 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR3_OFFSET) +#define STM32_OTGFS_HCCHAR4 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR4_OFFSET) +#define STM32_OTGFS_HCCHAR5 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR5_OFFSET) +#define STM32_OTGFS_HCCHAR6 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR6_OFFSET) +#define STM32_OTGFS_HCCHAR7 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR7_OFFSET) + +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT0_OFFSET) +#define STM32_OTGFS_HCINT1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT1_OFFSET) +#define STM32_OTGFS_HCINT2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT2_OFFSET) +#define STM32_OTGFS_HCINT3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT3_OFFSET) +#define STM32_OTGFS_HCINT4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT4_OFFSET) +#define STM32_OTGFS_HCINT5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT5_OFFSET) +#define STM32_OTGFS_HCINT6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT6_OFFSET) +#define STM32_OTGFS_HCINT7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT7_OFFSET) + +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK0_OFFSET) +#define STM32_OTGFS_HCINTMSK1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK1_OFFSET) +#define STM32_OTGFS_HCINTMSK2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK2_OFFSET) +#define STM32_OTGFS_HCINTMSK3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK3_OFFSET) +#define STM32_OTGFS_HCINTMSK4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK4_OFFSET) +#define STM32_OTGFS_HCINTMSK5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK5_OFFSET) +#define STM32_OTGFS_HCINTMSK6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK6_OFFSET) +#define STM32_OTGFS_HCINTMSK7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK7_OFFSET)_ + +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ0_OFFSET) +#define STM32_OTGFS_HCTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ1_OFFSET) +#define STM32_OTGFS_HCTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ2_OFFSET) +#define STM32_OTGFS_HCTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ3_OFFSET) +#define STM32_OTGFS_HCTSIZ4 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ4_OFFSET) +#define STM32_OTGFS_HCTSIZ5 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ5_OFFSET) +#define STM32_OTGFS_HCTSIZ6 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ6_OFFSET) +#define STM32_OTGFS_HCTSIZ7 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ7_OFFSET) + +/* Device-mode control and status registers */ + +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) + +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) + +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET) +#define STM32_OTGFS_DIEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL1_OFFSET) +#define STM32_OTGFS_DIEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL2_OFFSET) +#define STM32_OTGFS_DIEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL3_OFFSET) + +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT0_OFFSET) +#define STM32_OTGFS_DIEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT1_OFFSET) +#define STM32_OTGFS_DIEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT2_OFFSET) +#define STM32_OTGFS_DIEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT3_OFFSET) + +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ0_OFFSET) +#define STM32_OTGFS_DIEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ1_OFFSET) +#define STM32_OTGFS_DIEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ2_OFFSET) +#define STM32_OTGFS_DIEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ3_OFFSET) + +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS0 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS0_OFFSET) +#define STM32_OTGFS_DTXFSTS1 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS1_OFFSET) +#define STM32_OTGFS_DTXFSTS2 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS2_OFFSET) +#define STM32_OTGFS_DTXFSTS3 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS3_OFFSET) + +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) + +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL0_OFFSET) +#define STM32_OTGFS_DOEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL1_OFFSET) +#define STM32_OTGFS_DOEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL2_OFFSET) +#define STM32_OTGFS_DOEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL3_OFFSET) + +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT0_OFFSET) +#define STM32_OTGFS_DOEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT1_OFFSET) +#define STM32_OTGFS_DOEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT2_OFFSET) +#define STM32_OTGFS_DOEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT3_OFFSET) + +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ0_OFFSET) +#define STM32_OTGFS_DOEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ1_OFFSET) +#define STM32_OTGFS_DOEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ2_OFFSET) +#define STM32_OTGFS_DOEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ3_OFFSET) + +/* Power and clock gating registers */ + +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) + +#define STM32_OTGFS_DFIFO_DEP0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP0_OFFSET) +#define STM32_OTGFS_DFIFO_HCH0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH0_OFFSET) + +#define STM32_OTGFS_DFIFO_DEP1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP1_OFFSET) +#define STM32_OTGFS_DFIFO_HCH1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH1_OFFSET) + +#define STM32_OTGFS_DFIFO_DEP2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP2_OFFSET) +#define STM32_OTGFS_DFIFO_HCH2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH2_OFFSET) + +#define STM32_OTGFS_DFIFO_DEP3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP3_OFFSET) +#define STM32_OTGFS_DFIFO_HCH3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Core global control and status registers */ + +/* Control and status register */ + +#define OTGFS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ +#define OTGFS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */ +# define OTGFS_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */ +# define OTGFS_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */ +# define OTGFS_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */ +# define OTGFS_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */ +# define OTGFS_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */ +#endif +#define OTGFS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ +#define OTGFS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ +#define OTGFS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ +#define OTGFS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */ +#endif + /* Bits 13-15: Reserved, must be kept at reset value */ +#define OTGFS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ +#define OTGFS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ +#define OTGFS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ +#define OTGFS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */ +#endif +/* Bits 21-31: Reserved, + * must be kept at reset value + */ + +/* Interrupt register */ + +/* Bits 1:0 Reserved, + * must be kept at reset value + */ +#define OTGFS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ + /* Bits 3-7: Reserved, must be kept at reset value */ +#define OTGFS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ +#define OTGFS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ + /* Bits 16:10 Reserved, must be kept at reset value */ +#define OTGFS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ +#define OTGFS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ +#define OTGFS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */ +#endif + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* AHB configuration register */ + +#define OTGFS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ + /* Bits 1-6: Reserved, must be kept at reset value */ +#define OTGFS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ +#define OTGFS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* USB configuration register */ + +#define OTGFS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ +#define OTGFS_GUSBCFG_TOCAL_MASK (7 << OTGFS_GUSBCFG_TOCAL_SHIFT) + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTGFS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTGFS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ +#define OTGFS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ +#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ +#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT) +# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT) + /* Bits 14-28: Reserved, must be kept at reset value */ +#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ +#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ +#define OTGFS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ + /* Bits 20-31: Reserved, must be kept at reset value */ + +/* Reset register */ + +#define OTGFS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ +#define OTGFS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ +#define OTGFS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ + /* Bit 3 Reserved, must be kept at reset value */ +#define OTGFS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ +#define OTGFS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ +#define OTGFS_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ +#define OTGFS_GRSTCTL_TXFNUM_MASK (31 << OTGFS_GRSTCTL_TXFNUM_SHIFT) +# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ +# define OTGFS_GRSTCTL_TXFNUM_HPER (1 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ +# define OTGFS_GRSTCTL_TXFNUM_HALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ +# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ +# define OTGFS_GRSTCTL_TXFNUM_DALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ + +/* Bits 11-31: Reserved, + * must be kept at reset value + */ +#define OTGFS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ + +/* Core interrupt and Interrupt mask registers */ + +#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: ro Current mode of operation */ +# define OTGFS_GINTSTS_DEVMODE (0) +# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD) +#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: rc_w1 Mode mismatch interrupt */ +#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */ +#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: rc_w1 Start of frame */ +#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */ +#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */ +#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */ +#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ +#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: rc_w1 Early suspend */ +#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: rc_w1 USB suspend */ +#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: rc_w1 USB reset */ +#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: rc_w1 Enumeration done */ +#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: rc_w1 Isochronous OUT packet dropped interrupt */ +#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: rc_w1 End of periodic frame interrupt */ +#define OTGFS_GINT_RES16 (1 << 16) /* Bit 16 Reserved, must be kept at reset value */ +#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */ +#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */ +#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ +#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1 Incomplete isochronous IN transfer */ +#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer (device) */ +#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ +# define OTGFS_GINT_RSTDET (1 << 23) /* Bits 23: asserted when a reset is detected on the USB in partial */ +#else +# define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */ +#endif +#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */ +#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */ +#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +#define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27 LPM interrupt */ +#else +#define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */ +#endif +#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */ +#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */ +#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */ +#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: rc_w1 Resume/remote wakeup detected interrupt */ + +/* Receive status debug read/OTG status read and pop registers + * (host mode) + */ + +#define OTGFS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ +#define OTGFS_GRXSTSH_CHNUM_MASK (15 << OTGFS_GRXSTSH_CHNUM_SHIFT) +#define OTGFS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff << OTGFS_GRXSTSH_BCNT_SHIFT) +#define OTGFS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGFS_GRXSTSH_DPID_MASK (3 << OTGFS_GRXSTSH_DPID_SHIFT) +# define OTGFS_GRXSTSH_DPID_DATA0 (0 << OTGFS_GRXSTSH_DPID_SHIFT) +# define OTGFS_GRXSTSH_DPID_DATA2 (1 << OTGFS_GRXSTSH_DPID_SHIFT) +# define OTGFS_GRXSTSH_DPID_DATA1 (2 << OTGFS_GRXSTSH_DPID_SHIFT) +# define OTGFS_GRXSTSH_DPID_MDATA (3 << OTGFS_GRXSTSH_DPID_SHIFT) +#define OTGFS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGFS_GRXSTSH_PKTSTS_MASK (15 << OTGFS_GRXSTSH_PKTSTS_SHIFT) +# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ +# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ +# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ +# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ + +/* Bits 21-31: Reserved, + * must be kept at reset value + */ + +/* Receive status debug read/OTG status read and pop registers + * (device mode) + */ + +#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ +#define OTGFS_GRXSTSD_EPNUM_MASK (15 << OTGFS_GRXSTSD_EPNUM_SHIFT) +#define OTGFS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff << OTGFS_GRXSTSD_BCNT_SHIFT) +#define OTGFS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTGFS_GRXSTSD_DPID_MASK (3 << OTGFS_GRXSTSD_DPID_SHIFT) +# define OTGFS_GRXSTSD_DPID_DATA0 (0 << OTGFS_GRXSTSD_DPID_SHIFT) +# define OTGFS_GRXSTSD_DPID_DATA2 (1 << OTGFS_GRXSTSD_DPID_SHIFT) +# define OTGFS_GRXSTSD_DPID_DATA1 (2 << OTGFS_GRXSTSD_DPID_SHIFT) +# define OTGFS_GRXSTSD_DPID_MDATA (3 << OTGFS_GRXSTSD_DPID_SHIFT) +#define OTGFS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTGFS_GRXSTSD_PKTSTS_MASK (15 << OTGFS_GRXSTSD_PKTSTS_SHIFT) +# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ +# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ +# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ +# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ +# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ + +#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ +#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT) + /* Bits 25-31: Reserved, must be kept at reset value */ + +/* Receive FIFO size register */ + +#define OTGFS_GRXFSIZ_MASK (0xffff) + +/* Host non-periodic transmit FIFO size register */ + +#define OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ +#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT) +#define OTGFS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ +#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) + +/* Endpoint 0 Transmit FIFO size */ + +#define OTGFS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ +#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff << OTGFS_DIEPTXF0_TX0FD_SHIFT) +#define OTGFS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ +#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGFS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) +# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) + +/* Non-periodic transmit FIFO/queue status register */ + +#define OTGFS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ +#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) +# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) +#define OTGFS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ +#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) +# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) +#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ +#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGFS_HNPTXSTS_NPTXQTOP_SHIFT) +# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ +# define OTGFS_HNPTXSTS_TYPE_MASK (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) +# define OTGFS_HNPTXSTS_TYPE_INOUT (0 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGFS_HNPTXSTS_TYPE_ZLP (1 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ +# define OTGFS_HNPTXSTS_TYPE_HALT (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ + +# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGFS_HNPTXSTS_CHNUM_MASK (15 << OTGFS_HNPTXSTS_CHNUM_SHIFT) +# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT) + /* Bit 31 Reserved, must be kept at reset value */ + +/* General core configuration register */ + +/* Bits 0-15: Reserved, + * must be kept at reset value + */ +#define OTGFS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ + /* Bit 17 Reserved, must be kept at reset value */ +#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define OTGFS_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */ +#else +# define OTGFS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing A device */ +# define OTGFS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing B device */ +# define OTGFS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ +# define OTGFS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ +#endif + /* Bits 22-31: Reserved, must be kept at reset value */ + +/* Core ID register (32-bit product ID) */ + +/* Host periodic transmit FIFO size register */ + +#define OTGFS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ +#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGFS_HPTXFSIZ_PTXSA_SHIFT) +#define OTGFS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ +#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGFS_HPTXFSIZ_PTXFD_SHIFT) + +/* Device IN endpoint transmit FIFOn size register */ + +#define OTGFS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ +#define OTGFS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGFS_DIEPTXF_INEPTXSA_SHIFT) +#define OTGFS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ +#define OTGFS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGFS_DIEPTXF_INEPTXFD_SHIFT) +# define OTGFS_DIEPTXF_INEPTXFD_MIN (16 << OTGFS_DIEPTXF_INEPTXFD_MASK) + +/* Host-mode control and status registers */ + +/* Host configuration register */ + +#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ +#define OTGFS_HCFG_FSLSPCS_MASK (3 << OTGFS_HCFG_FSLSPCS_SHIFT) +# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ +# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ +# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ + +#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ + /* Bits 31:3 Reserved, must be kept at reset value */ + +/* Host frame interval register */ + +#define OTGFS_HFIR_MASK (0xffff) + +/* Host frame number/frame time remaining register */ + +#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ +#define OTGFS_HFNUM_FRNUM_MASK (0xffff << OTGFS_HFNUM_FRNUM_SHIFT) +#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ +#define OTGFS_HFNUM_FTREM_MASK (0xffff << OTGFS_HFNUM_FTREM_SHIFT) + +/* Host periodic transmit FIFO/queue status register */ + +#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ +#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) +# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) +#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ +#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff << OTGFS_HPTXSTS_PTXQSAV_SHIFT) +# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 << OTGFS_HPTXSTS_PTXQSAV_SHIFT) +#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ +#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGFS_HPTXSTS_PTXQTOP_SHIFT) +# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ +# define OTGFS_HPTXSTS_TYPE_MASK (3 << OTGFS_HPTXSTS_TYPE_SHIFT) +# define OTGFS_HPTXSTS_TYPE_INOUT (0 << OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTGFS_HPTXSTS_TYPE_ZLP (1 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ +# define OTGFS_HPTXSTS_TYPE_HALT (3 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ + +# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTGFS_HPTXSTS_EPNUM_MASK (15 << OTGFS_HPTXSTS_EPNUM_SHIFT) +# define OTGFS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTGFS_HPTXSTS_CHNUM_MASK (15 << OTGFS_HPTXSTS_CHNUM_SHIFT) +# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ + +/* Host all channels interrupt and all channels interrupt mask registers */ + +#define OTGFS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ + +/* Host port control and status register */ + +#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ +#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ +#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ +#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ +#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ +#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ +#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ +#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ +#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ + /* Bit 9: Reserved, must be kept at reset value */ +#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ +#define OTGFS_HPRT_PLSTS_MASK (3 << OTGFS_HPRT_PLSTS_SHIFT) +# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ +# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ +#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ +#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ +#define OTGFS_HPRT_PTCTL_MASK (15 << OTGFS_HPRT_PTCTL_SHIFT) +# define OTGFS_HPRT_PTCTL_DISABLED (0 << OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ +# define OTGFS_HPRT_PTCTL_J (1 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */ +# define OTGFS_HPRT_PTCTL_L (2 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */ +# define OTGFS_HPRT_PTCTL_SE0_NAK (3 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGFS_HPRT_PTCTL_PACKET (4 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ +# define OTGFS_HPRT_PTCTL_FORCE (5 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ +#define OTGFS_HPRT_PSPD_MASK (3 << OTGFS_HPRT_PSPD_SHIFT) +# define OTGFS_HPRT_PSPD_FS (1 << OTGFS_HPRT_PSPD_SHIFT) /* Full speed */ +# define OTGFS_HPRT_PSPD_LS (2 << OTGFS_HPRT_PSPD_SHIFT) /* Low speed */ + +/* Bits 19-31: Reserved, + * must be kept at reset value + */ + +/* Host channel-n characteristics register */ + +#define OTGFS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff << OTGFS_HCCHAR_MPSIZ_SHIFT) +#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ +#define OTGFS_HCCHAR_EPNUM_MASK (15 << OTGFS_HCCHAR_EPNUM_SHIFT) +#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ +# define OTGFS_HCCHAR_EPDIR_OUT (0) +# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR + +/* Bit 16 Reserved, + * must be kept at reset value + */ +#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ +#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGFS_HCCHAR_EPTYP_MASK (3 << OTGFS_HCCHAR_EPTYP_SHIFT) +# define OTGFS_HCCHAR_EPTYP_CTRL (0 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */ +# define OTGFS_HCCHAR_EPTYP_ISOC (1 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ +# define OTGFS_HCCHAR_EPTYP_BULK (2 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */ +# define OTGFS_HCCHAR_EPTYP_INTR (3 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ + +#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ +#define OTGFS_HCCHAR_MCNT_MASK (3 << OTGFS_HCCHAR_MCNT_SHIFT) +#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ +#define OTGFS_HCCHAR_DAD_MASK (0x7f << OTGFS_HCCHAR_DAD_SHIFT) +#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ +#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ +#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ + +/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ + +#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ +#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ +#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ +#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ +#define OTGFS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ +#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ +#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ +#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ +#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ + +/* Bits 11-31 Reserved, + * must be kept at reset value + */ + +/* Host channel-n interrupt register */ + +#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_HCTSIZ_XFRSIZ_SHIFT) +#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ +#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGFS_HCTSIZ_PKTCNT_SHIFT) +#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ +#define OTGFS_HCTSIZ_DPID_MASK (3 << OTGFS_HCTSIZ_DPID_SHIFT) +# define OTGFS_HCTSIZ_DPID_DATA0 (0 << OTGFS_HCTSIZ_DPID_SHIFT) +# define OTGFS_HCTSIZ_DPID_DATA2 (1 << OTGFS_HCTSIZ_DPID_SHIFT) +# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT) +# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Non-control */ +# define OTGFS_HCTSIZ_PID_SETUP (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Control */ + +/* Bit 31 Reserved, + * must be kept at reset value + */ + +/* Device-mode control and status registers */ + +/* Device configuration register */ + +#define OTGFS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ +#define OTGFS_DCFG_DSPD_MASK (3 << OTGFS_DCFG_DSPD_SHIFT) +# define OTGFS_DCFG_DSPD_FS (3 << OTGFS_DCFG_DSPD_SHIFT) /* Full speed */ + +#define OTGFS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ + /* Bit 3: Reserved, must be kept at reset value */ +#define OTGFS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ +#define OTGFS_DCFG_DAD_MASK (0x7f << OTGFS_DCFG_DAD_SHIFT) +#define OTGFS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ +#define OTGFS_DCFG_PFIVL_MASK (3 << OTGFS_DCFG_PFIVL_SHIFT) +# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ +# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ +# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ +# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ + +/* Bits 13-31 Reserved, + * must be kept at reset value + */ + +/* Device control register */ + +#define OTGFS_TESTMODE_DISABLED (0) /* Test mode disabled */ +#define OTGFS_TESTMODE_J (1) /* Test_J mode */ +#define OTGFS_TESTMODE_K (2) /* Test_K mode */ +#define OTGFS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ +#define OTGFS_TESTMODE_PACKET (4) /* Test_Packet mode */ +#define OTGFS_TESTMODE_FORCE (5) /* Test_Force_Enable */ + +#define OTGFS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ +#define OTGFS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ +#define OTGFS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ +#define OTGFS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ +#define OTGFS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ +#define OTGFS_DCTL_TCTL_MASK (7 << OTGFS_DCTL_TCTL_SHIFT) +# define OTGFS_DCTL_TCTL_DISABLED (0 << OTGFS_DCTL_TCTL_SHIFT) /* Test mode disabled */ +# define OTGFS_DCTL_TCTL_J (1 << OTGFS_DCTL_TCTL_SHIFT) /* Test_J mode */ +# define OTGFS_DCTL_TCTL_K (2 << OTGFS_DCTL_TCTL_SHIFT) /* Test_K mode */ +# define OTGFS_DCTL_TCTL_SE0_NAK (3 << OTGFS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTGFS_DCTL_TCTL_PACKET (4 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ +# define OTGFS_DCTL_TCTL_FORCE (5 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ + +#define OTGFS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ +#define OTGFS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ +#define OTGFS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ +#define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ +#define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ + /* Bits 12-31: Reserved, must be kept at reset value */ + +/* Device status register */ + +#define OTGFS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ +#define OTGFS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ +#define OTGFS_DSTS_ENUMSPD_MASK (3 << OTGFS_DSTS_ENUMSPD_SHIFT) +# define OTGFS_DSTS_ENUMSPD_FS (3 << OTGFS_DSTS_ENUMSPD_MASK) /* Full speed */ + +/* Bits 4-7: Reserved, + * must be kept at reset value + */ +#define OTGFS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ +#define OTGFS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ +#define OTGFS_DSTS_SOFFN_MASK (0x3fff << OTGFS_DSTS_SOFFN_SHIFT) +#define OTGFS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ +#define OTGFS_DSTS_SOFFN_EVEN 0 +#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 + /* Bits 22-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint common interrupt mask register */ + +#define OTGFS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGFS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGFS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ +#define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ +#define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ +#define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint common interrupt mask register */ + +#define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTGFS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGFS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ +#define OTGFS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +/* Device all endpoints interrupt and All endpoints interrupt mask + * registers + */ + +#define OTGFS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTGFS_DAINT_IEP_MASK (0xffff << OTGFS_DAINT_IEP_SHIFT) +# define OTGFS_DAINT_IEP(n) (1 << (n)) +#define OTGFS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ +#define OTGFS_DAINT_OEP_MASK (0xffff << OTGFS_DAINT_OEP_SHIFT) +# define OTGFS_DAINT_OEP(n) (1 << ((n)+16)) + +/* Device VBUS discharge time register */ + +#define OTGFS_DVBUSDIS_MASK (0xffff) + +/* Device VBUS pulsing time register */ + +#define OTGFS_DVBUSPULSE_MASK (0xfff) + +/* Device IN endpoint FIFO empty interrupt mask register */ + +#define OTGFS_DIEPEMPMSK(n) (1 << (n)) + +/* Device control IN endpoint 0 control register */ + +#define OTGFS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGFS_DIEPCTL0_MPSIZ_MASK (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) +# define OTGFS_DIEPCTL0_MPSIZ_64 (0 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGFS_DIEPCTL0_MPSIZ_32 (1 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGFS_DIEPCTL0_MPSIZ_16 (2 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGFS_DIEPCTL0_MPSIZ_8 (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGFS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGFS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGFS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGFS_DIEPCTL0_EPTYP_MASK (3 << OTGFS_DIEPCTL0_EPTYP_SHIFT) +# define OTGFS_DIEPCTL0_EPTYP_CTRL (0 << OTGFS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGFS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGFS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGFS_DIEPCTL0_TXFNUM_MASK (15 << OTGFS_DIEPCTL0_TXFNUM_SHIFT) +#define OTGFS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGFS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGFS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGFS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device control IN endpoint n control register */ + +#define OTGFS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGFS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DIEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGFS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGFS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ +# define OTGFS_DIEPCTL_EVEN (0) +# define OTGFS_DIEPCTL_ODD OTGFS_DIEPCTL_EONUM +# define OTGFS_DIEPCTL_DATA0 (0) +# define OTGFS_DIEPCTL_DATA1 OTGFS_DIEPCTL_EONUM +#define OTGFS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGFS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGFS_DIEPCTL_EPTYP_MASK (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) +# define OTGFS_DIEPCTL_EPTYP_CTRL (0 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGFS_DIEPCTL_EPTYP_ISOC (1 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGFS_DIEPCTL_EPTYP_BULK (2 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGFS_DIEPCTL_EPTYP_INTR (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ + +/* Bit 20: Reserved, + * must be kept at reset value + */ +#define OTGFS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTGFS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTGFS_DIEPCTL_TXFNUM_MASK (15 << OTGFS_DIEPCTL_TXFNUM_SHIFT) +#define OTGFS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGFS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGFS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGFS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ +#define OTGFS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ +#define OTGFS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGFS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGFS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGFS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGFS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ +#define OTGFS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGFS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ +#define OTGFS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ + /* Bits 8-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint 0 transfer size register */ + +#define OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGFS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGFS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ +#define OTGFS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGFS_DIEPTSIZ0_PKTCNT_SHIFT) + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* Device IN endpoint n transfer size register */ + +#define OTGFS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGFS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT) +#define OTGFS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGFS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DIEPTSIZ_PKTCNT_SHIFT) +#define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ +#define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint TxFIFO status register */ + +#define OTGFS_DTXFSTS_MASK (0xffff) + +/* Device OUT endpoint 0 control register */ + +#define OTGFS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTGFS_DOEPCTL0_MPSIZ_MASK (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) +# define OTGFS_DOEPCTL0_MPSIZ_64 (0 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTGFS_DOEPCTL0_MPSIZ_32 (1 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTGFS_DOEPCTL0_MPSIZ_16 (2 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTGFS_DOEPCTL0_MPSIZ_8 (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + +/* Bits 2-14: Reserved, + * must be kept at reset value + */ +#define OTGFS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTGFS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGFS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGFS_DOEPCTL0_EPTYP_MASK (3 << OTGFS_DOEPCTL0_EPTYP_SHIFT) +# define OTGFS_DOEPCTL0_EPTYP_CTRL (0 << OTGFS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + +#define OTGFS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGFS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGFS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGFS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTGFS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGFS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device OUT endpoint n control register */ + +#define OTGFS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTGFS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DOEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTGFS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTGFS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ +# define OTGFS_DOEPCTL_DATA0 (0) +# define OTGFS_DOEPCTL_DATA1 OTGFS_DOEPCTL_DPID +#define OTGFS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ +# define OTGFS_DOEPCTL_EVEN (0) +# define OTGFS_DOEPCTL_ODD OTGFS_DOEPCTL_EONUM +#define OTGFS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTGFS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTGFS_DOEPCTL_EPTYP_MASK (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) +# define OTGFS_DOEPCTL_EPTYP_CTRL (0 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Control */ +# define OTGFS_DOEPCTL_EPTYP_ISOC (1 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTGFS_DOEPCTL_EPTYP_BULK (2 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTGFS_DOEPCTL_EPTYP_INTR (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ + +#define OTGFS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTGFS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTGFS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTGFS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTGFS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTGFS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ +#define OTGFS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ +#define OTGFS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ +#define OTGFS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTGFS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTGFS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTGFS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTGFS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ +#define OTGFS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTGFS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ + /* Bits 7-31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-0 transfer size register */ + +#define OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTGFS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTGFS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ + /* Bits 20-28: Reserved, must be kept at reset value */ +#define OTGFS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGFS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Device OUT endpoint-n transfer size register */ + +#define OTGFS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTGFS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT) +#define OTGFS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTGFS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DOEPTSIZ_PKTCNT_SHIFT) +#define OTGFS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTGFS_DOEPTSIZ_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ_STUPCNT_SHIFT) +#define OTGFS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ +#define OTGFS_DOEPTSIZ_RXDPID_MASK (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGFS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGFS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGFS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) +# define OTGFS_DOEPTSIZ_RXDPID_MDATA (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ + +/* Power and clock gating control register */ + +#define OTGFS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ +#define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ + /* Bits 2-3: Reserved, must be kept at reset value */ +#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h new file mode 100644 index 0000000000000..d48838484d9b7 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h @@ -0,0 +1,525 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_IP_DAC_V2 +#undef HAVE_IP_DAC_V1 /* No DAC IPv1 */ + +/* Register Offsets *********************************************************/ + +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ +#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ +#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC channel 1 sample and hold time register */ +#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC channel 2 sample and hold time register */ +#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC sample and hold time register */ +#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC sample and hold refresh time register */ +#define STM32_DAC_STR1_OFFSET 0x0058 /* DAC channel 1 sawtooth register */ +#define STM32_DAC_STR2_OFFSET 0x005c /* DAC channel 2 sawtooth register */ +#define STM32_DAC_STMODR_OFFSET 0x0060 /* DAC sawtooth mode register */ + +/* Register Addresses *******************************************************/ + +#ifdef CONFIG_STM32_HAVE_DAC1 +/* DAC1 */ + +# define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) +# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) +# define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) +# define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) +# define STM32_DAC1_CCR (STM32_DAC1_BASE + STM32_DAC_CCR_OFFSET) +# define STM32_DAC1_MCR (STM32_DAC1_BASE + STM32_DAC_MCR_OFFSET) +# define STM32_DAC1_SHSR1 (STM32_DAC1_BASE + STM32_DAC_SHSR1_OFFSET) +# define STM32_DAC1_SHSR2 (STM32_DAC1_BASE + STM32_DAC_SHSR2_OFFSET) +# define STM32_DAC1_SHHR (STM32_DAC1_BASE + STM32_DAC_SHHR_OFFSET) +# define STM32_DAC1_SHRR (STM32_DAC1_BASE + STM32_DAC_SHRR_OFFSET) +# define STM32_DAC1_STR1 (STM32_DAC1_BASE + STM32_DAC_STR1_OFFSET) +# define STM32_DAC1_STR2 (STM32_DAC1_BASE + STM32_DAC_STR2_OFFSET) +# define STM32_DAC1_STMODR (STM32_DAC1_BASE + STM32_DAC_STMODR_OFFSET) + +#endif /* CONFIG_STM32_HAVE_DAC1 */ + +#ifdef CONFIG_STM32_HAVE_DAC2 +/* DAC2 */ + +# define STM32_DAC2_CR (STM32_DAC2_BASE + STM32_DAC_CR_OFFSET) +# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE + STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE + STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE + STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE + STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE + STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE + STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE + STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE + STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE + STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE + STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC2_DOR1 (STM32_DAC2_BASE + STM32_DAC_DOR1_OFFSET) +# define STM32_DAC2_DOR2 (STM32_DAC2_BASE + STM32_DAC_DOR2_OFFSET) +# define STM32_DAC2_SR (STM32_DAC2_BASE + STM32_DAC_SR_OFFSET) +# define STM32_DAC2_CCR (STM32_DAC2_BASE + STM32_DAC_CCR_OFFSET) +# define STM32_DAC2_MCR (STM32_DAC2_BASE + STM32_DAC_MCR_OFFSET) +# define STM32_DAC2_SHSR1 (STM32_DAC2_BASE + STM32_DAC_SHSR1_OFFSET) +# define STM32_DAC2_SHSR2 (STM32_DAC2_BASE + STM32_DAC_SHSR2_OFFSET) +# define STM32_DAC2_SHHR (STM32_DAC2_BASE + STM32_DAC_SHHR_OFFSET) +# define STM32_DAC2_SHRR (STM32_DAC2_BASE + STM32_DAC_SHRR_OFFSET) +# define STM32_DAC2_STR1 (STM32_DAC2_BASE + STM32_DAC_STR1_OFFSET) +# define STM32_DAC2_STR2 (STM32_DAC2_BASE + STM32_DAC_STR2_OFFSET) +# define STM32_DAC2_STMODR (STM32_DAC2_BASE + STM32_DAC_STMODR_OFFSET) + +#endif /* CONFIG_STM32_HAVE_DAC2 */ + +#ifdef CONFIG_STM32_HAVE_DAC3 +/* DAC3 */ + +# define STM32_DAC3_CR (STM32_DAC3_BASE + STM32_DAC_CR_OFFSET) +# define STM32_DAC3_SWTRIGR (STM32_DAC3_BASE + STM32_DAC_SWTRIGR_OFFSET) +# define STM32_DAC3_DHR12R1 (STM32_DAC3_BASE + STM32_DAC_DHR12R1_OFFSET) +# define STM32_DAC3_DHR12L1 (STM32_DAC3_BASE + STM32_DAC_DHR12L1_OFFSET) +# define STM32_DAC3_DHR8R1 (STM32_DAC3_BASE + STM32_DAC_DHR8R1_OFFSET) +# define STM32_DAC3_DHR12R2 (STM32_DAC3_BASE + STM32_DAC_DHR12R2_OFFSET) +# define STM32_DAC3_DHR12L2 (STM32_DAC3_BASE + STM32_DAC_DHR12L2_OFFSET) +# define STM32_DAC3_DHR8R2 (STM32_DAC3_BASE + STM32_DAC_DHR8R2_OFFSET) +# define STM32_DAC3_DHR12RD (STM32_DAC3_BASE + STM32_DAC_DHR12RD_OFFSET) +# define STM32_DAC3_DHR12LD (STM32_DAC3_BASE + STM32_DAC_DHR12LD_OFFSET) +# define STM32_DAC3_DHR8RD (STM32_DAC3_BASE + STM32_DAC_DHR8RD_OFFSET) +# define STM32_DAC3_DOR1 (STM32_DAC3_BASE + STM32_DAC_DOR1_OFFSET) +# define STM32_DAC3_DOR2 (STM32_DAC3_BASE + STM32_DAC_DOR2_OFFSET) +# define STM32_DAC3_SR (STM32_DAC3_BASE + STM32_DAC_SR_OFFSET) +# define STM32_DAC3_CCR (STM32_DAC3_BASE + STM32_DAC_CCR_OFFSET) +# define STM32_DAC3_MCR (STM32_DAC3_BASE + STM32_DAC_MCR_OFFSET) +# define STM32_DAC3_SHSR1 (STM32_DAC3_BASE + STM32_DAC_SHSR1_OFFSET) +# define STM32_DAC3_SHSR2 (STM32_DAC3_BASE + STM32_DAC_SHSR2_OFFSET) +# define STM32_DAC3_SHHR (STM32_DAC3_BASE + STM32_DAC_SHHR_OFFSET) +# define STM32_DAC3_SHRR (STM32_DAC3_BASE + STM32_DAC_SHRR_OFFSET) +# define STM32_DAC3_STR1 (STM32_DAC3_BASE + STM32_DAC_STR1_OFFSET) +# define STM32_DAC3_STR2 (STM32_DAC3_BASE + STM32_DAC_STR2_OFFSET) +# define STM32_DAC3_STMODR (STM32_DAC3_BASE + STM32_DAC_STMODR_OFFSET) + +#endif /* CONFIG_STM32_HAVE_DAC3 */ + +/* Register Bitfield Definitions ********************************************/ + +/* DAC control register (CR) */ + +/* These definitions may be used for 16-bit values of either channel: Leave + * as-is for use with DAC channel 1 or shift left by 16 for use with DAC + * channel 2. + */ + +#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel enable */ +#define DAC_CR_TEN (1 << 1) /* Bit 2: DAC channel trigger enable */ +#define DAC_CR_TSEL_SHIFT (2) /* Bits 2-5: DAC channel trigger selection */ +#define DAC_CR_TSEL_MASK (0xf << DAC_CR_TSEL_SHIFT) /* Possible values for TSEL follow: */ +# define DAC_CR_TSEL_SW (0x0 << DAC_CR_TSEL_SHIFT) /* SWTRIG1 */ +# define DAC_CR_TSEL_TIM8 (0x1 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg1 - TIM8_TRGO */ +# define DAC_CR_TSEL_TIM7 (0x2 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg2 - TIM7_TRGO */ +# define DAC_CR_TSEL_TIM15 (0x3 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg3 - TIM15_TRGO */ +# define DAC_CR_TSEL_TIM2 (0x4 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg4 - TIM2_TRGO */ +# define DAC_CR_TSEL_TIM4 (0x5 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg5 - TIM4_TRGO */ +# define DAC_CR_TSEL_EXTI9 (0x6 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg6 - EXTI9 */ +# define DAC_CR_TSEL_TIM6 (0x7 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg7 - TIM6_TRGO */ +# define DAC_CR_TSEL_TIM3 (0x8 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg8 - TIM3_TRGO */ +# define DAC_CR_TSEL_HRT1RTRG1 (0x9 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg9 - htrim_dac_reset_trg1 */ +# define DAC_CR_TSEL_HRT1RTRG2 (0xa << DAC_CR_TSEL_SHIFT) /* dac_chx_trg10 - htrim_dac_reset_trg2 */ +# define DAC_CR_TSEL_HRT1RTRG3 (0xb << DAC_CR_TSEL_SHIFT) /* dac_chx_trg11 - htrim_dac_reset_trg3 */ +# define DAC_CR_TSEL_HRT1RTRG4 (0xc << DAC_CR_TSEL_SHIFT) /* dac_chx_trg12 - htrim_dac_reset_trg4 */ +# define DAC_CR_TSEL_HRT1RTRG5 (0xd << DAC_CR_TSEL_SHIFT) /* dac_chx_trg13 - htrim_dac_reset_trg5 */ +# define DAC_CR_TSEL_HRT1RTRG6 (0xe << DAC_CR_TSEL_SHIFT) /* dac_chx_trg14 - htrim_dac_reset_trg6 */ +# define DAC_CR_TSEL_HRT1TRG1 (0xf << DAC_CR_TSEL_SHIFT) /* dac_chx_trg15 - htrim_dac_trg1 */ +#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation enable */ +#define DAC_CR_WAVE_MASK (0x3 << DAC_CR_WAVE_SHIFT) /* Possible values for WAVE follow: */ +# define DAC_CR_WAVE_DISABLED (0x0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE_NOISE (0x1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE_TRIANGLE (0x2 << DAC_CR_WAVE_SHIFT) /* Triangle wave generation enabled */ +# define DAC_CR_WAVE_SAWTOOTH (0x3 << DAC_CR_WAVE_SHIFT) /* Sawtooth wave generation enabled */ +#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel mask/amplitude selector */ +#define DAC_CR_MAMP_MASK (0xf << DAC_CR_MAMP_SHIFT) /* Possible values for MASK follow: */ +# define DAC_CR_MAMP_BIT0 (0x0 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ +# define DAC_CR_MAMP_BITS1_0 (0x1 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ +# define DAC_CR_MAMP_BITS2_0 (0x2 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ +# define DAC_CR_MAMP_BITS3_0 (0x3 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ +# define DAC_CR_MAMP_BITS4_0 (0x4 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ +# define DAC_CR_MAMP_BITS5_0 (0x5 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ +# define DAC_CR_MAMP_BITS6_0 (0x6 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ +# define DAC_CR_MAMP_BITS7_0 (0x7 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ +# define DAC_CR_MAMP_BITS8_0 (0x8 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ +# define DAC_CR_MAMP_BITS9_0 (0x9 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ +# define DAC_CR_MAMP_BITS10_0 (0xa << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ +# define DAC_CR_MAMP_BITS11_0 (0xb << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ +# define DAC_CR_MAMP_AMP1 (0x0 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ +# define DAC_CR_MAMP_AMP3 (0x1 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ +# define DAC_CR_MAMP_AMP7 (0x2 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ +# define DAC_CR_MAMP_AMP15 (0x3 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ +# define DAC_CR_MAMP_AMP31 (0x4 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ +# define DAC_CR_MAMP_AMP63 (0x5 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ +# define DAC_CR_MAMP_AMP127 (0x6 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ +# define DAC_CR_MAMP_AMP255 (0x7 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ +# define DAC_CR_MAMP_AMP511 (0x8 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ +# define DAC_CR_MAMP_AMP1023 (0x9 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ +# define DAC_CR_MAMP_AMP2047 (0xa << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ +# define DAC_CR_MAMP_AMP4095 (0xb << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ +#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel DMA enable */ +#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel DMA underrun interrupt enable */ +#define DAC_CR_CEN (1 << 14) /* Bit 14: DAC channel calibration enable */ + +/* These definitions may be used with the full, 32-bit register */ + +#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ +#define DAC_CR_TEN1 (1 << 1) /* Bit 2: DAC channel 1 trigger enable */ +#define DAC_CR_TSEL1_SHIFT (2) /* Bits 2-5: DAC channel 1 trigger selection */ +#define DAC_CR_TSEL1_MASK (0xf << DAC_CR_TSEL1_SHIFT) /* Possible values for TSEL1 follow: */ +# define DAC_CR_TSEL1_SW (0x0 << DAC_CR_TSEL1_SHIFT) /* SWTRIG1 */ +# define DAC_CR_TSEL1_TIM8 (0x1 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg1 - TIM8_TRGO */ +# define DAC_CR_TSEL1_TIM7 (0x2 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg2 - TIM7_TRGO */ +# define DAC_CR_TSEL1_TIM15 (0x3 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg3 - TIM15_TRGO */ +# define DAC_CR_TSEL1_TIM2 (0x4 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg4 - TIM2_TRGO */ +# define DAC_CR_TSEL1_TIM4 (0x5 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg5 - TIM4_TRGO */ +# define DAC_CR_TSEL1_EXTI9 (0x6 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg6 - EXTI9 */ +# define DAC_CR_TSEL1_TIM6 (0x7 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg7 - TIM6_TRGO */ +# define DAC_CR_TSEL1_TIM3 (0x8 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg8 - TIM3_TRGO */ +# define DAC_CR_TSEL1_HRT1RTRG1 (0x9 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg9 - htrim_dac_reset_trg1 */ +# define DAC_CR_TSEL1_HRT1RTRG2 (0xa << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg10 - htrim_dac_reset_trg2 */ +# define DAC_CR_TSEL1_HRT1RTRG3 (0xb << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg11 - htrim_dac_reset_trg3 */ +# define DAC_CR_TSEL1_HRT1RTRG4 (0xc << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg12 - htrim_dac_reset_trg4 */ +# define DAC_CR_TSEL1_HRT1RTRG5 (0xd << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg13 - htrim_dac_reset_trg5 */ +# define DAC_CR_TSEL1_HRT1RTRG6 (0xe << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg14 - htrim_dac_reset_trg6 */ +# define DAC_CR_TSEL1_HRT1TRG1 (0xf << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg15 - htrim_dac_trg1 */ +#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation enable */ +#define DAC_CR_WAVE1_MASK (0x3 << DAC_CR_WAVE1_SHIFT) /* Possible values for WAVE1 follow: */ +# define DAC_CR_WAVE1_DISABLED (0x0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE1_TRIANGLE (0x2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ +# define DAC_CR_WAVE1_SAWTOOTH (0x3 << DAC_CR_WAVE1_SHIFT) /* Sawtooth wave generation enabled */ +#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ +#define DAC_CR_MAMP1_MASK (0xf << DAC_CR_MAMP1_SHIFT) /* Possible values for MASK1 follow: */ +# define DAC_CR_MAMP1_BIT0 (0x0 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ +# define DAC_CR_MAMP1_BITS1_0 (0x1 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ +# define DAC_CR_MAMP1_BITS2_0 (0x2 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ +# define DAC_CR_MAMP1_BITS3_0 (0x3 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ +# define DAC_CR_MAMP1_BITS4_0 (0x4 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ +# define DAC_CR_MAMP1_BITS5_0 (0x5 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ +# define DAC_CR_MAMP1_BITS6_0 (0x6 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ +# define DAC_CR_MAMP1_BITS7_0 (0x7 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ +# define DAC_CR_MAMP1_BITS8_0 (0x8 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ +# define DAC_CR_MAMP1_BITS9_0 (0x9 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ +# define DAC_CR_MAMP1_BITS10_0 (0xa << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ +# define DAC_CR_MAMP1_BITS11_0 (0xb << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ +# define DAC_CR_MAMP1_AMP1 (0x0 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ +# define DAC_CR_MAMP1_AMP3 (0x1 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ +# define DAC_CR_MAMP1_AMP7 (0x2 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ +# define DAC_CR_MAMP1_AMP15 (0x3 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ +# define DAC_CR_MAMP1_AMP31 (0x4 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ +# define DAC_CR_MAMP1_AMP63 (0x5 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ +# define DAC_CR_MAMP1_AMP127 (0x6 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ +# define DAC_CR_MAMP1_AMP255 (0x7 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ +# define DAC_CR_MAMP1_AMP511 (0x8 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ +# define DAC_CR_MAMP1_AMP1023 (0x9 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ +# define DAC_CR_MAMP1_AMP2047 (0xa << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ +# define DAC_CR_MAMP1_AMP4095 (0xb << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ +#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ +#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun interrupt enable */ +#define DAC_CR_CEN1 (1 << 14) /* Bit 14: DAC channel 1 calibration enable */ + +#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ +#define DAC_CR_TEN2 (1 << 17) /* Bit 17: DAC channel 2 trigger enable */ +#define DAC_CR_TSEL2_SHIFT (18) /* Bits 18-21: DAC channel 2 trigger selection */ +#define DAC_CR_TSEL2_MASK (0xf << DAC_CR_TSEL2_SHIFT) /* Possible values for TSEL2 follow: */ +# define DAC_CR_TSEL2_SW (0x0 << DAC_CR_TSEL2_SHIFT) /* SWTRIG2 */ +# define DAC_CR_TSEL2_TIM8 (0x1 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg1 - TIM8_TRGO */ +# define DAC_CR_TSEL2_TIM7 (0x2 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg2 - TIM7_TRGO */ +# define DAC_CR_TSEL2_TIM15 (0x3 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg3 - TIM15_TRGO */ +# define DAC_CR_TSEL2_TIM2 (0x4 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg4 - TIM2_TRGO */ +# define DAC_CR_TSEL2_TIM4 (0x5 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg5 - TIM4_TRGO */ +# define DAC_CR_TSEL2_EXTI9 (0x6 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg6 - EXTI9 */ +# define DAC_CR_TSEL2_TIM6 (0x7 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg7 - TIM6_TRGO */ +# define DAC_CR_TSEL2_TIM3 (0x8 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg8 - TIM3_TRGO */ +# define DAC_CR_TSEL2_HRT1RTRG1 (0x9 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg9 - htrim_dac_reset_trg1 */ +# define DAC_CR_TSEL2_HRT1RTRG2 (0xa << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg10 - htrim_dac_reset_trg2 */ +# define DAC_CR_TSEL2_HRT1RTRG3 (0xb << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg11 - htrim_dac_reset_trg3 */ +# define DAC_CR_TSEL2_HRT1RTRG4 (0xc << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg12 - htrim_dac_reset_trg4 */ +# define DAC_CR_TSEL2_HRT1RTRG5 (0xd << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg13 - htrim_dac_reset_trg5 */ +# define DAC_CR_TSEL2_HRT1RTRG6 (0xe << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg14 - htrim_dac_reset_trg6 */ +# define DAC_CR_TSEL2_HRT1TRG1 (0xf << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg15 - htrim_dac_trg1 */ +#define DAC_CR_WAVE2_SHIFT (22) /* Bits 22-23: DAC channel 2 noise/triangle wave generation enable */ +#define DAC_CR_WAVE2_MASK (0x3 << DAC_CR_WAVE2_SHIFT) /* Possible values for WAVE2 follow: */ +# define DAC_CR_WAVE2_DISABLED (0x0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ +# define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ +# define DAC_CR_WAVE2_TRIANGLE (0x2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ +# define DAC_CR_WAVE2_SAWTOOTH (0x3 << DAC_CR_WAVE2_SHIFT) /* Sawtooth wave generation enabled */ +#define DAC_CR_MAMP2_SHIFT (24) /* Bits 24-27: DAC channel 2 mask/amplitude selector */ +#define DAC_CR_MAMP2_MASK (0xf << DAC_CR_MAMP2_SHIFT) /* Possible values for MASK2 follow: */ +# define DAC_CR_MAMP2_BIT0 (0x0 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ +# define DAC_CR_MAMP2_BITS1_0 (0x1 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ +# define DAC_CR_MAMP2_BITS2_0 (0x2 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ +# define DAC_CR_MAMP2_BITS3_0 (0x3 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ +# define DAC_CR_MAMP2_BITS4_0 (0x4 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ +# define DAC_CR_MAMP2_BITS5_0 (0x5 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ +# define DAC_CR_MAMP2_BITS6_0 (0x6 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ +# define DAC_CR_MAMP2_BITS7_0 (0x7 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ +# define DAC_CR_MAMP2_BITS8_0 (0x8 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ +# define DAC_CR_MAMP2_BITS9_0 (0x9 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ +# define DAC_CR_MAMP2_BITS10_0 (0xa << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ +# define DAC_CR_MAMP2_BITS11_0 (0xb << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ +# define DAC_CR_MAMP2_AMP1 (0x0 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ +# define DAC_CR_MAMP2_AMP3 (0x1 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ +# define DAC_CR_MAMP2_AMP7 (0x2 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ +# define DAC_CR_MAMP2_AMP15 (0x3 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ +# define DAC_CR_MAMP2_AMP31 (0x4 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ +# define DAC_CR_MAMP2_AMP63 (0x5 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ +# define DAC_CR_MAMP2_AMP127 (0x6 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ +# define DAC_CR_MAMP2_AMP255 (0x7 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ +# define DAC_CR_MAMP2_AMP511 (0x8 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ +# define DAC_CR_MAMP2_AMP1023 (0x9 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ +# define DAC_CR_MAMP2_AMP2047 (0xa << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ +# define DAC_CR_MAMP2_AMP4095 (0xb << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ +#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ +#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ +#define DAC_CR_CEN2 (1 << 30) /* Bit 30: DAC channel 2 calibration enable */ + +/* DAC software trigger register (SWTRGR) */ + +#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n) - 1)) /* Software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ + +#define DAC_SWTRIGR_SWTRIGB(n) (1 << ((n) - 1)) /* Software trigger B for sawtooth generation */ +#define DAC_SWTRIGR_SWTRIGB1 (1 << 0) /* Bit 16: DAC channel 1 software trigger B for sawtooth increment */ +#define DAC_SWTRIGR_SWTRIGB2 (1 << 1) /* Bit 17: DAC channel 2 software trigger B for sawtooth increment */ + +/* DAC channels 1/2 12-bit right-aligned data holding register + * (DHR12R1, DHR12R2) + */ + +#define DAC_DHR12R_MASK_SHIFT (0) /* DAC channel 1/2 right-aligned data */ +#define DAC_DHR12R_MASK (0xfff << DAC_DHR12R_MASK_SHIFT) +#define DAC_DHR12R_MASKB_SHIFT (16) /* DAC channel 1/2 right-aligned data B for Double Data Mode */ +#define DAC_DHR12R_MASKB (0xfff << DAC_DHR12R_MASKB_SHIFT) + +/* DAC channel 1/2 12-bit left aligned data holding register + * (DHR12L1, DHR12L2) + */ + +#define DAC_DHR12L_MASK_SHIFT (4) /* DAC channel 1/2 left-aligned data */ +#define DAC_DHR12L_MASK (0xfff << DAC_DHR12L_MASK_SHIFT) +#define DAC_DHR12L_MASKB_SHIFT (20) /* DAC channel 1/2 left-aligned data B for Double Data Mode */ +#define DAC_DHR12L_MASKB (0xfff << DAC_DHR12L_MASKB_SHIFT) + +/* DAC channel 1/2 8-bit right aligned data holding register + * (DHR8R1, DHR8R2) + */ + +#define DAC_DHR8R_MASK_SHIFT (0) /* DAC channel 1/2 right-aligned data */ +#define DAC_DHR8R_MASK (0xff << DAC_DHR8R_MASK_SHIFT) +#define DAC_DHR8R_MASKB_SHIFT (8) /* DAC channel 1/2 right-aligned data B for Double Data Mode */ +#define DAC_DHR8R_MASKB (0xff << DAC_DHR8R_MASKB_SHIFT) + +/* Dual DAC 12-bit right-aligned data holding register (DHR12RD) */ + +#define DAC_DHR12RD_DACC_SHIFT(n) (((n) - 1) << 4) +#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) + +#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) +#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ +#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) + +/* Dual DAC 12-bit left-aligned data holding register (DHR12LD) */ + +#define DAC_DHR12LD_DACC_SHIFT(n) ((((n) - 1) << 4) + 4) +#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) + +#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) +#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ +#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) + +/* DUAL DAC 8-bit right aligned data holding register (DHR8RD) */ + +#define DAC_DHR8RD_DACC_SHIFT(n) (((n) - 1) << 3) +#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) + +#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) +#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ +#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) + +/* DAC channel 1/2 data output register (DOR1, DOR2) */ + +#define DAC_DOR_MASK_SHIFT (0) /* DAC channel 1/2 data output */ +#define DAC_DOR_MASK (0xfff << DAC_DOR_MASK_SHIFT) +#define DAC_DOR_MASKB_SHIFT (16) /* DAC channel 1/2 data output B for Double Data Mode */ +#define DAC_DOR_MASKB (0xfff << DAC_DOR_MASKB_SHIFT) + +/* DAC status register (SR) */ + +#define DAC_SR_DACRDY(n) (1 << ((((n) - 1) << 4) + 11)) +#define DAC_SR_DAC1RDY (1 << 11) /* Bit 13: DAC channel 1 ready status bit */ +#define DAC_SR_DAC2RDY (1 << 27) /* Bit 27: DAC channel 2 ready status bit */ + +#define DAC_SR_DORSTAT(n) (1 << ((((n) - 1) << 4) + 12)) +#define DAC_SR_DORSTAT1 (1 << 12) /* Bit 13: DAC channel 1 output register status bit */ +#define DAC_SR_DORSTAT2 (1 << 28) /* Bit 29: DAC channel 2 output register status bit */ + +#define DAC_SR_DMAUDR(n) (1 << ((((n) - 1) << 4) + 13)) +#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ + +#define DAC_SR_CAL_FLAG(n) (1 << ((((n) - 1) << 4) + 14)) +#define DAC_SR_CAL_FLAG1 (1 << 14) /* Bit 13: DAC channel 1 calibration offset status */ +#define DAC_SR_CAL_FLAG2 (1 << 30) /* Bit 29: DAC channel 2 calibration offset status */ + +#define DAC_SR_BWST(n) (1 << ((((n) - 1) << 4) + 15)) +#define DAC_SR_BWST1 (1 << 15) /* Bit 13: DAC channel 1 busy writing sample time flag */ +#define DAC_SR_BWST2 (1 << 31) /* Bit 29: DAC channel 2 busy writing sample time flag */ + +/* DAC calibration control register (CCR) */ + +#define DAC_CCR_OTRIM_SHIFT(n) (((n) - 1) << 4) +#define DAC_CCR_OTRIM_MASK(n) (0x1f << DAC_CCR_OTRIM_SHIFT(n)) + +#define DAC_CCR_OTRIM1_SHIFT (0) /* DAC channel 1 offset trimming value */ +#define DAC_CCR_OTRIM1_MASK (0x1f << DAC_CCR_OTRIM1_SHIFT) +#define DAC_CCR_OTRIM2_SHIFT (16) /* DAC channel 2 offset trimming value */ +#define DAC_CCR_OTRIM2_MASK (0x1f << DAC_CCR_OTRIM2_SHIFT) + +/* DAC mode control register (MCR) */ + +#define DAC_MCR_MODE_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 mode */ +#define DAC_MCR_MODE_MASK(n) (0x7 << DAC_MCR_MODE_SHIFT(n)) +# define DAC_MCR_MODE_0(n) (0x0 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE_1(n) (0x1 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE_2(n) (0x2 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin with buffer disabled */ +# define DAC_MCR_MODE_3(n) (0x3 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE_4(n) (0x4 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE_5(n) (0x5 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE_6(n) (0x6 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE_7(n) (0x7 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ + +#define DAC_MCR_MODE1_SHIFT (0) /* DAC channel 1 mode */ +#define DAC_MCR_MODE1_MASK (0x7 << DAC_MCR_MODE1_SHIFT) +# define DAC_MCR_MODE1_0 (0x0 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE1_1 (0x1 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE1_2 (0x2 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin with buffer disabled */ +# define DAC_MCR_MODE1_3 (0x3 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE1_4 (0x4 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE1_5 (0x5 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE1_6 (0x6 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE1_7 (0x7 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ + +#define DAC_MCR_MODE2_SHIFT (16) /* DAC channel 2 mode */ +#define DAC_MCR_MODE2_MASK (0x7 << DAC_MCR_MODE2_SHIFT) +# define DAC_MCR_MODE2_0 (0x0 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE2_1 (0x1 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE2_2 (0x2 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin with buffer disabled */ +# define DAC_MCR_MODE2_3 (0x3 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE2_4 (0x4 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin with buffer enabled */ +# define DAC_MCR_MODE2_5 (0x5 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ +# define DAC_MCR_MODE2_6 (0x6 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ +# define DAC_MCR_MODE2_7 (0x7 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ + +#define DAC_MCR_DMADOUBLE(n) (1 << ((((n) - 1) << 4) + 8)) /* DAC Channel 1/2 DMA double data mode */ +#define DAC_MCR_DMADOUBLE1 (1 << 8) /* DAC Channel 1 DMA double data mode */ +#define DAC_MCR_DMADOUBLE2 (1 << 24) /* DAC Channel 2 DMA double data mode */ + +#define DAC_MCR_SINFORMAT(n) (1 << ((((n) - 1) << 4) + 9)) /* DAC Channel 1/2 enable signed format */ +#define DAC_MCR_SINFORMAT1 (1 << 9) /* DAC Channel 1 enable signed format */ +#define DAC_MCR_SINFORMAT2 (1 << 25) /* DAC Channel 2 enable signed format */ + +#define DAC_MCR_HFSEL_SHIFT (14) /* High-frequency interface mode selection */ +#define DAC_MCR_HFSEL_MASK (0x3 << DAC_MCR_HFSEL_SHIFT) +# define DAC_MCR_HFSEL_DISABLED (0x0 << DAC_MCR_HFSEL_SHIFT) /* High-frequency disabled */ +# define DAC_MCR_HFSEL_AHB_80MHz (0x1 << DAC_MCR_HFSEL_SHIFT) /* High-frequency for AHB > 80 MHz */ +# define DAC_MCR_HFSEL_AHB_160MHz (0x2 << DAC_MCR_HFSEL_SHIFT) /* High-frequency for AHB > 160 MHz */ +# define DAC_MCR_HFSEL_RESERVED (0x3 << DAC_MCR_HFSEL_SHIFT) /* Reserved */ + +/* DAC channel 1/2 sample and hold sample time register (SHSR1, SHSR2) */ + +#define DAC_SHSR_TSAMPLE_SHIFT (0) /* DAC channel 1/2 Sample phase time = (TSAMPLE + 1) * LSI/LSE clock period */ +#define DAC_SHSR_TSAMPLE_MASK (0x3ff << DAC_SHSR1_TSAMPLE1_SHIFT) + +/* DAC sample and hold time register (SHHR) */ + +#define DAC_SHHR_THOLD_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 Hold time = THOLD * LSI/LSE clock period */ +#define DAC_SHHR_THOLD_MASK(n) (0x3ff << DAC_SHHR_THOLD_SHIFT(n)) + +#define DAC_SHHR_THOLD1_SHIFT (0) /* DAC channel 1 Hold time */ +#define DAC_SHHR_THOLD1_MASK (0x3ff << DAC_SHHR_THOLD1_SHIFT) +#define DAC_SHHR_THOLD2_SHIFT (16) /* DAC channel 2 Hold time */ +#define DAC_SHHR_THOLD2_MASK (0x3ff << DAC_SHHR_THOLD2_SHIFT) + +/* DAC sample and hold refresh time register (SHRR) */ + +#define DAC_SHHR_TREFRESH_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 Refresh time = TREFRESH * LSI/LSE clock period */ +#define DAC_SHHR_TREFRESH_MASK(n) (0xff << DAC_SHHR_THOLD_SHIFT(n)) + +#define DAC_SHRR_TREFRESH1_SHIFT (0) /* DAC channel 1 Refresh time */ +#define DAC_SHRR_TREFRESH1_MASK (0xff << DAC_SHRR_TREFRESH1_SHIFT) +#define DAC_SHRR_TREFRESH2_SHIFT (16) /* DAC channel 2 Refresh time */ +#define DAC_SHRR_TREFRESH2_MASK (0xff << DAC_SHRR_TREFRESH2_SHIFT) + +/* DAC channel 1/2 sawtooth register register (STR1, STR2) */ + +#define DAC_STR_STRSTDATA_SHIFT (0) /* DAC channel 1 Sawtooth starting value */ +#define DAC_STR_STRSTDATA_MASK (0xfff << DAC_STR1_STRSTDATA1_SHIFT) +#define DAC_STR_STDIR (1 << 12) /* DAC channel 1 Sawtooth direction setting */ +#define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */ +#define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT) + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h similarity index 92% rename from arch/arm/src/stm32/stm32_1wire.h rename to arch/arm/src/common/stm32/stm32_1wire.h index dbd2ed588d7c1..79f9f6d47e46f 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.h + * arch/arm/src/common/stm32/stm32_1wire.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#include + #include "stm32_uart.h" /**************************************************************************** @@ -71,4 +73,4 @@ struct onewire_dev_s *stm32_1wireinitialize(int port); int stm32_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_1wire.c rename to arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c index e3c27f32354ed..595136c6c65d0 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.c + * arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -52,6 +52,7 @@ #include "arm_internal.h" #include "stm32_rcc.h" #include "stm32_1wire.h" +#include "stm32_rcc.h" #ifdef HAVE_1WIREDRIVER diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_adc.h similarity index 73% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_adc.h index 91bd0cfbeae41..fce412ef2ef38 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,21 +20,21 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_lowputc_v2.c" +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "stm32_adc_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# include "stm32_adc_m3m4_v1v2.h" #else -# error "Unsupported STM32 M0 serial" +# error "Unsupported STM32 ADC" #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.c index 6366eb0ed321d..cfa4e5c8cf1e4 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.h index 579d1ffc21c55..1cd50f60f7c5b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -165,7 +165,7 @@ /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 #else -# error +# error "Unrecognized STM32 M0 sub-family for ADC EXTSEL" #endif /* EXTSEL configuration *****************************************************/ @@ -445,4 +445,4 @@ const struct stm32_adc_ops_s #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_ADC1 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c index cd53b780eb463..b53e2b6a07166 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * @@ -308,7 +308,7 @@ /* ADC resolution. Not supported for basic STM32 ADC IPv1 */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define HAVE_ADC_RESOLUTION #else # undef HAVE_ADC_RESOLUTION @@ -316,7 +316,7 @@ /* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # undef HAVE_ADC_CMN_REGS #else # define HAVE_ADC_CMN_REGS @@ -333,7 +333,7 @@ /* ADC DMA configuration bit support */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define ADC_HAVE_DMACFG 1 #else # undef ADC_HAVE_DMACFG @@ -341,7 +341,7 @@ /* ADC scan mode support - only for ADCv1 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 # define ADC_HAVE_SCAN 1 # ifndef CONFIG_STM32_ADC1_SCAN # define CONFIG_STM32_ADC1_SCAN 0 diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h index 05c5bdf48013f..b6317b5e32d5c 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H /**************************************************************************** * Included Files @@ -134,7 +134,7 @@ # undef CONFIG_STM32_TIM4_ADC4 #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifndef CONFIG_STM32_TIM5 # undef CONFIG_STM32_TIM5_ADC # undef CONFIG_STM32_TIM5_ADC1 @@ -2342,4 +2342,4 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_aes.h b/arch/arm/src/common/stm32/stm32_aes.h similarity index 80% rename from arch/arm/src/stm32/stm32_aes.h rename to arch/arm/src/common/stm32/stm32_aes.h index f0de4f5972071..8e0a90c4424a5 100644 --- a/arch/arm/src/stm32/stm32_aes.h +++ b/arch/arm/src/common/stm32/stm32_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.h + * arch/arm/src/common/stm32/stm32_aes.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_AES_H -#define __ARCH_ARM_SRC_STM32_STM32_AES_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H /**************************************************************************** * Included Files @@ -33,14 +33,14 @@ #include "chip.h" -/* Only the STM32L162 devices have AES, but we don't bother with exact macros - * for simplicity. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# include "hardware/stm32l15xxx_aes.h" -#else -# error "Unknown chip for AES" +#if defined(CONFIG_STM32_HAVE_IP_AES_M0_V1) +# include "hardware/stm32_aes.h" +#elif defined(CONFIG_STM32_HAVE_IP_AES_M3M4_V1) +# ifdef CONFIG_STM32_STM32L15XX +# include "hardware/stm32l15xxx_aes.h" +# else +# error "Unknown chip for AES" +# endif #endif /**************************************************************************** @@ -55,4 +55,4 @@ * Inline Functions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H */ diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m0_v1.c index ae58ed82c1771..4348d1c4f0bb6 100644 --- a/arch/arm/src/stm32/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c index 746047df3d7be..96ff3b7cbf660 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -71,7 +71,7 @@ static int stm32aes_setup_cr(int mode, int encrypt); ****************************************************************************/ static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; -static bool g_stm32aes_initdone; +static bool g_stm32aes_initdone = false; /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32/stm32_alarm.h b/arch/arm/src/common/stm32/stm32_alarm.h similarity index 94% rename from arch/arm/src/stm32/stm32_alarm.h rename to arch/arm/src/common/stm32/stm32_alarm.h index 2660dfd8a059e..0d192e8e847c1 100644 --- a/arch/arm/src/stm32/stm32_alarm.h +++ b/arch/arm/src/common/stm32/stm32_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_alarm.h + * arch/arm/src/common/stm32/stm32_alarm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ALARM_H -#define __ARCH_ARM_SRC_STM32_STM32_ALARM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_RTC_ALARM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ALARM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_allocateheap.c rename to arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c index 69d5a18bb7b04..010ede1eeb338 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_allocateheap.c + * arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -342,7 +342,7 @@ * In addition, external FSMC SRAM may be available. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) /* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/common/stm32/stm32_bbsram.h similarity index 78% rename from arch/arm/src/stm32f0l0g0/stm32_dma.c rename to arch/arm/src/common/stm32/stm32_bbsram.h index 3e3b9af30ead7..8c8658f963fb5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ b/arch/arm/src/common/stm32/stm32_bbsram.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.c + * arch/arm/src/common/stm32/stm32_bbsram.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,20 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) +# include "stm32_bbsram_m3m4_v1.h" #else -# include "stm32_dma_v1.c" +# error "Unsupported STM32 stm32_bbsram" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_bbsram.c rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c index b595b37761100..14c132dc8ea45 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.c + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,7 @@ #include #include -#include "stm32_bbsram.h" +#include "stm32_bbsram_m3m4_v1.h" #include "chip.h" #include "stm32_pwr.h" #include "stm32_rtc.h" diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h similarity index 95% rename from arch/arm/src/stm32/stm32_bbsram.h rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h index bca2251088f56..3f8abefa83e4c 100644 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.h + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H -#define __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H /**************************************************************************** * The purpose of this driver is to add battery backup file to the file @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) # define STM32_BBSRAM_SIZE 4096 #else # error No backup SRAM on this STM32 @@ -149,4 +149,4 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/common/stm32/stm32_bkp.h similarity index 90% rename from arch/arm/src/stm32/stm32_bkp.h rename to arch/arm/src/common/stm32/stm32_bkp.h index 1d2c3cc858d73..ab84719310e1d 100644 --- a/arch/arm/src/stm32/stm32_bkp.h +++ b/arch/arm/src/common/stm32/stm32_bkp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bkp.h + * arch/arm/src/common/stm32/stm32_bkp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_STM32_BKP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/common/stm32/stm32_can.h similarity index 71% rename from arch/arm/src/stm32/stm32_can.h rename to arch/arm/src/common/stm32/stm32_can.h index e9f906a92e183..ef931423e57bc 100644 --- a/arch/arm/src/stm32/stm32_can.h +++ b/arch/arm/src/common/stm32/stm32_can.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.h + * arch/arm/src/common/stm32/stm32_can.h * * SPDX-License-Identifier: Apache-2.0 * @@ -23,16 +23,18 @@ #ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H #define __ARCH_ARM_SRC_STM32_STM32_CAN_H +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + /**************************************************************************** * Included Files ****************************************************************************/ -#include +# include -#include "chip.h" -#include "hardware/stm32_can.h" +# include "chip.h" +# include "hardware/stm32_can.h" -#include +# include /**************************************************************************** * Pre-processor Definitions @@ -42,23 +44,23 @@ /* Up to 2 CAN interfaces are supported */ -#if STM32_NCAN < 2 -# undef CONFIG_STM32_CAN2 -#endif +# if STM32_NCAN < 2 +# undef CONFIG_STM32_CAN2 +# endif -#if STM32_NCAN < 1 -# undef CONFIG_STM32_CAN1 -#endif +# if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 +# endif /* CAN BAUD */ -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) -# error "CONFIG_STM32_CAN1_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" +# endif -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) -# error "CONFIG_STM32_CAN2_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" +# endif /* User-defined TSEG1 and TSEG2 settings may be used. * @@ -67,46 +69,46 @@ * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32_CAN_TSEG1 -# define CONFIG_STM32_CAN_TSEG1 6 -#endif +# ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 +# endif -#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32_CAN_TSEG1 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" +# endif -#ifndef CONFIG_STM32_CAN_TSEG2 -# define CONFIG_STM32_CAN_TSEG2 7 -#endif +# ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 +# endif -#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32_CAN_TSEG2 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" +# endif /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_CAN_CHARDRIVER +# ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -124,9 +126,9 @@ extern "C" struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); -#endif +# endif -#ifdef CONFIG_STM32_CAN_SOCKET +# ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize @@ -143,12 +145,14 @@ struct can_dev_s *stm32_caninitialize(int port); ****************************************************************************/ int stm32_cansockinitialize(int port); -#endif +# endif -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } +# endif + +# endif /* __ASSEMBLY__ */ #endif -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_can.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1.c index d0e8373aa361c..90959870c4955 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_can_sock.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_can_sock.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c index 433ec29e15318..60561620cfa51 100644 --- a/arch/arm/src/stm32/stm32_can_sock.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can_sock.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/common/stm32/stm32_capture.h similarity index 81% rename from arch/arm/src/stm32/stm32_capture.h rename to arch/arm/src/common/stm32/stm32_capture.h index 33f2a3157a13f..ab80b5c4c1ff9 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/common/stm32/stm32_capture.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.h + * arch/arm/src/common/stm32/stm32_capture.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H -#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H /**************************************************************************** * Included Files @@ -29,6 +29,12 @@ #include +#include +#include + +#include +#include + #include "chip.h" #include #include "hardware/stm32_tim.h" @@ -64,48 +70,28 @@ extern "C" #define EXTERN extern #endif -/* Capture Device Structure */ - struct stm32_cap_dev_s { struct stm32_cap_ops_s *ops; }; -/* Capture input EDGE sources */ - typedef enum { - /* Mapped */ - STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK), STM32_CAP_MAPPED_TI1 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI2 = (GTIM_CCMR_CCS_CCIN2), STM32_CAP_MAPPED_TI3 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI4 = (GTIM_CCMR_CCS_CCIN2), - -/* TODO STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */ - - /* Event prescaler */ - STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK), STM32_CAP_INPSC_NO = (0 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_2EVENTS = (1 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_4EVENTS = (2 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_8EVENTS = (3 << GTIM_CCMR1_IC1PSC_SHIFT), - - /* Event prescaler */ - STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK), STM32_CAP_FILTER_NO = (0 << GTIM_CCMR1_IC1F_SHIFT), - - /* Internal clock with N time to confirm event */ - STM32_CAP_FILTER_INT_N2 = (1 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N4 = (2 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N8 = (3 << GTIM_CCMR1_IC1F_SHIFT), - - /* DTS clock div by D with N time to confirm event */ - STM32_CAP_FILTER_DTS_D2_N6 = (4 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D2_N8 = (5 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D4_N6 = (6 << GTIM_CCMR1_IC1F_SHIFT), @@ -118,9 +104,6 @@ typedef enum STM32_CAP_FILTER_DTS_D32_N5 = (13 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N6 = (14 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N8 = (15 << GTIM_CCMR1_IC1F_SHIFT), - - /* EDGE */ - STM32_CAP_EDGE_MASK = (3 << 8), STM32_CAP_EDGE_DISABLED = (0 << 8), STM32_CAP_EDGE_RISING = (1 << 8), @@ -128,12 +111,8 @@ typedef enum STM32_CAP_EDGE_BOTH = (3 << 8), } stm32_cap_ch_cfg_t; -/* Slave mode control configure */ - typedef enum { - /* Slave mode selection */ - STM32_CAP_SMS_MASK = (7 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_INT = (0 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_ENC1 = (1 << GTIM_SMCR_SMS_SHIFT), @@ -143,9 +122,6 @@ typedef enum STM32_CAP_SMS_GAT = (5 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_TRG = (6 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_EXT = (7 << GTIM_SMCR_SMS_SHIFT), - - /* Trigger selection */ - STM32_CAP_TS_MASK = (7 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR0 = (0 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR1 = (1 << GTIM_SMCR_TS_SHIFT), @@ -155,25 +131,16 @@ typedef enum STM32_CAP_TS_TI1FP1 = (5 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_TI2FP2 = (6 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ETRF = (7 << GTIM_SMCR_TS_SHIFT), - - /* Master/Slave mode setting */ - STM32_CAP_MSM_MASK = (1 << 7) } stm32_cap_smc_cfg_t; -/* Capture flags */ - typedef enum { - /* One of the following */ - STM32_CAP_FLAG_IRQ_COUNTER = (GTIM_SR_UIF), - STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF), STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF), - STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF), STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF), STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF), @@ -184,8 +151,6 @@ typedef enum #define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1)) #define STM32_CAP_CHANNEL_COUNTER 0 -/* Capture Operations */ - struct stm32_cap_ops_s { int (*setsmc)(struct stm32_cap_dev_s *dev, stm32_cap_smc_cfg_t cfg); @@ -202,38 +167,9 @@ struct stm32_cap_ops_s uint32_t (*rstcounter)(struct stm32_cap_dev_s *dev); }; -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - struct stm32_cap_dev_s *stm32_cap_init(int timer); - -/* Power-down timer, mark it as unused */ - int stm32_cap_deinit(struct stm32_cap_dev_s *dev); - -/**************************************************************************** - * Name: stm32_cap_initialize - * - * Description: - * Initialize one timer for use with the upper_level capture driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,5 8,...,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half capture driver returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_CAPTURE struct cap_lowerhalf_s *stm32_cap_initialize(int timer); -#endif #undef EXTERN #if defined(__cplusplus) @@ -241,4 +177,5 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H */ diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c index 966f41a0a439f..48fcfe57c7390 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture_lowerhalf.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c index 0246f5e28f983..ea4e0b174fbbd 100644 --- a/arch/arm/src/stm32/stm32_capture_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture_lowerhalf.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/common/stm32/stm32_ccm.h similarity index 76% rename from arch/arm/src/stm32f0l0g0/stm32_flash.c rename to arch/arm/src/common/stm32/stm32_ccm.h index 010d5059c0c76..432d3bf549269 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ b/arch/arm/src/common/stm32/stm32_ccm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.c + * arch/arm/src/common/stm32/stm32_ccm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) -# include "stm32g0c0_flash.c" +#if defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) +# include "stm32_ccm_m3m4_v1.h" #else -# error "Flash driver unsupported on selected chip." +# error "Unsupported STM32 stm32_ccm" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H */ diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c similarity index 95% rename from arch/arm/src/stm32/stm32_ccm.c rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c index 9c87b61d4aff6..fb4507e1d082c 100644 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.c + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ #include -#include "stm32_ccm.h" +#include "stm32_ccm_m3m4_v1.h" #ifdef HAVE_CCM_HEAP diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_ccm.h rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h index f5a38d3d41be6..705a58c08045e 100644 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.h + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CCM_H -#define __ARCH_ARM_SRC_STM32_STM32_CCM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32_STM32F30XX) # define CCM_START 0x10000000 # define CCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#elif defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) || \ defined(CONFIG_STM32_STM32F33XX) # define CCM_START 0x10000000 # define CCM_END 0x10010000 @@ -122,4 +122,4 @@ EXTERN struct mm_heap_s *g_ccm_heap; #endif /* __ASSEMBLY__ */ #endif /* HAVE_CCM_HEAP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CCM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.h b/arch/arm/src/common/stm32/stm32_comp.h similarity index 51% rename from arch/arm/src/stm32/stm32_comp_v1.h rename to arch/arm/src/common/stm32/stm32_comp.h index 5389e5ddca15b..8178f55e6d486 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.h +++ b/arch/arm/src/common/stm32/stm32_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.h + * arch/arm/src/common/stm32/stm32_comp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,41 +20,55 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H /**************************************************************************** * Included Files ****************************************************************************/ -#ifdef CONFIG_STM32_COMP +#include + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +#include "chip.h" + +#include "hardware/stm32_comp.h" /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) +# define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS +# define COMP_POL_DEFAULT COMP_POL_NONINVERT +# define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF +# define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL +# define COMP_LOCK_DEFAULT COMP_LOCK_RW -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT +# ifndef CONFIG_STM32_STM32F33XX +# define COMP_MODE_DEFAULT +# define COMP_HYST_DEFAULT +# define COMP_WINMODE_DEFAULT +# endif +# endif #endif /**************************************************************************** * Public Types ****************************************************************************/ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + /* Blanking source */ enum stm32_comp_blanking_e { COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_BLANKING_T1OC5, COMP_BLANKING_T3OC4, COMP_BLANKING_T2OC3, @@ -62,7 +76,7 @@ enum stm32_comp_blanking_e COMP_BLANKING_T15OC1, COMP_BLANKING_T2OC4, COMP_BLANKING_T15OC2, -#endif +# endif }; /* Output polarisation */ @@ -91,7 +105,7 @@ enum stm32_comp_inm_e enum stm32_comp_outsel_e { COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_OUTSEL_BRKACTH, COMP_OUTSEL_BRK2, COMP_OUTSEL_T1OCC, /* COMP2 only */ @@ -106,7 +120,7 @@ enum stm32_comp_outsel_e COMP_OUTSEL_T15OCC, /* COMP4 only */ COMP_OUTSEL_T16CAP1, /* COMP6 only */ COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif +# endif }; /* CSR register lock state */ @@ -117,9 +131,9 @@ enum stm32_comp_lock_e COMP_LOCK_RO }; -#ifndef CONFIG_STM32_STM32F33XX +# ifndef CONFIG_STM32_STM32F33XX -/* Hysteresis */ +/* Hysteresis */ enum stm32_comp_hyst_e { @@ -147,7 +161,109 @@ enum stm32_comp_winmode_e COMP_WINMODE_EN }; +# endif +# elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +# endif +#endif /* CONFIG_STM32_COMP */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} #endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_COMP_M3M4_V1 || CONFIG_STM32_HAVE_IP_COMP_M3M4_V2 */ -#endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v1.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c index 17e5ccefab23a..5af2ab5217701 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_comp_v2.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v2.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c index d6fbae9c202ad..8939e4a6ce93c 100644 --- a/arch/arm/src/stm32/stm32_comp_v2.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.h b/arch/arm/src/common/stm32/stm32_cordic.h similarity index 75% rename from arch/arm/src/stm32f0l0g0/stm32_serial.h rename to arch/arm/src/common/stm32/stm32_cordic.h index 725db01e52176..aa536a50f26a7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.h +++ b/arch/arm/src/common/stm32/stm32_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.h + * arch/arm/src/common/stm32/stm32_cordic.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H /**************************************************************************** * Included Files @@ -29,8 +29,10 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) +# include "stm32_cordic_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_cordic" +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_cordic.c b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_cordic.c rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c index a9ab089a7fbf4..e77afc841a1c4 100644 --- a/arch/arm/src/stm32/stm32_cordic.c +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.c + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -39,7 +39,7 @@ #include "hardware/stm32g4xxxx_cordic.h" -#include "stm32_cordic.h" +#include "stm32_cordic_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_cordic.h b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_cordic.h rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h index be6da8d85ef36..84328ab75c101 100644 --- a/arch/arm/src/stm32/stm32_cordic.h +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.h + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CORDIC_H -#define __ARCH_ARM_SRC_STM32_STM32_CORDIC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ struct cordic_lowerhalf_s *stm32_cordicinitialize(void); -#endif /* __ARCH_ARM_SRC_STM32_STM32_CORDIC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_crypto.c b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_crypto.c rename to arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c index cf4646e04ee6a..8a88cff4803ae 100644 --- a/arch/arm/src/stm32/stm32_crypto.c +++ b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_crypto.c + * arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac.h new file mode 100644 index 0000000000000..192a666ec9346 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "stm32_dac_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dac" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dac.c rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c index 873e3af543152..c9cb731658fb6 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.c + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32.h" -#include "stm32_dac.h" +#include "stm32_dac_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_dma.h" #include "stm32_syscfg.h" @@ -145,7 +145,7 @@ # undef CONFIG_STM32_DAC1CH2_DMA # undef CONFIG_STM32_DAC2CH1_DMA # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # ifndef CONFIG_STM32_DMA1 # warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" # undef CONFIG_STM32_DAC1CH1_DMA @@ -235,7 +235,7 @@ # if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) # define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # define HAVE_DMA 1 # define DAC_DMA 1 # if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) @@ -524,9 +524,12 @@ #warning "Missing Logic" -/* DMA stream/channel configuration */ +/* DMA stream/channel configuration. The register layout depends on the DMA + * IP version, not the DAC IP version: stream DMA (IPv2) uses the SCR + * register fields, while channel DMA (IPv1) uses the CCR register fields. + */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ DMA_SCR_PSIZE_16BITS | \ DMA_SCR_MINC | \ @@ -603,7 +606,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, /* Interrupt handler */ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg); #endif @@ -971,7 +974,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, * ****************************************************************************/ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg) { #warning "Missing logic" diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_dac.h rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h index b031fa463d8ee..9683dab6d8884 100644 --- a/arch/arm/src/stm32/stm32_dac.h +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.h + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H /**************************************************************************** * Included Files @@ -29,6 +29,9 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) + #include "chip.h" #include "hardware/stm32_dac.h" @@ -136,4 +139,6 @@ struct dac_dev_s *stm32_dacinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DAC_H */ +#endif /* CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 || CONFIG_STM32_HAVE_IP_DAC_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/common/stm32/stm32_dbgmcu.h similarity index 82% rename from arch/arm/src/stm32/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/stm32_dbgmcu.h index 1695141ff16b0..4b1b2f81ee37d 100644 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/stm32_dbgmcu.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dbgmcu.h + * arch/arm/src/common/stm32/stm32_dbgmcu.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -29,6 +29,10 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) + #include "chip.h" #include "hardware/stm32_dbgmcu.h" @@ -48,4 +52,6 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 || ... */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode.h new file mode 100644 index 0000000000000..593c06fad90ad --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +# include "stm32_dfumode_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dfumode" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H */ diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_dfumode.c rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c index 45b8b0e9cd4cd..40bb4b28ad07d 100644 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.c + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include -#include "stm32_dfumode.h" +#include "stm32_dfumode_m3m4_v1.h" /**************************************************************************** * Public Functions @@ -56,7 +56,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) { #ifdef CONFIG_DEBUG_WARN @@ -77,4 +77,4 @@ void stm32_dfumode(void) __builtin_unreachable(); /* Tell compiler we will not return */ } -#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1 */ diff --git a/arch/arm/src/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h similarity index 87% rename from arch/arm/src/stm32/stm32_dfumode.h rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h index 332ef05c0974b..5a3c639fc129c 100644 --- a/arch/arm/src/stm32/stm32_dfumode.h +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.h + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H -#define __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H /**************************************************************************** * Included Files @@ -44,8 +44,8 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) noreturn_function; #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma.h new file mode 100644 index 0000000000000..16124d4a4b73f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_channel_stream.h" +#else +# error "Unsupported STM32 DMA" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d.h new file mode 100644 index 0000000000000..548dd220034ea --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_dma2d_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dma2d" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma2d.c rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index 83b98668454d7..e129ee671cec7 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.c + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -48,8 +48,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ccm.h" -#include "stm32_dma2d.h" +#include "stm32_dma2d_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_dma2d.h rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h index f8627cfe1058e..5bc43e6da99f8 100644 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.h + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA2D_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H /**************************************************************************** * Included Files @@ -189,4 +189,4 @@ int stm32_dma2dinitialize(void); void stm32_dma2duninitialize(void); #endif /* CONFIG_FB_OVERLAY */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA2D_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h similarity index 97% rename from arch/arm/src/stm32/stm32_dma.h rename to arch/arm/src/common/stm32/stm32_dma_channel_stream.h index f7eb641ef8623..aec408a552764 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma.h + * arch/arm/src/common/stm32/stm32_dma_channel_stream.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H /**************************************************************************** * Included Files @@ -349,4 +349,4 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c index 3117fad02ec9a..06ae4eaf7ea15 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index e622ab417d501..6fb57a23624b0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c index ebd0f3d0af521..2d18d541a1a09 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c * * SPDX-License-Identifier: Apache-2.0 * @@ -55,14 +55,14 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define DMA1_NCHANNELS 8 #else # define DMA1_NCHANNELS 7 #endif #if STM32_NDMA > 1 -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA2_NCHANNELS 8 # else # define DMA2_NCHANNELS 5 diff --git a/arch/arm/src/stm32/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c index d518dcf801c0c..dd8892f0f6502 100644 --- a/arch/arm/src/stm32/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v2.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c index ed3784d53881c..0fadcf45a61b9 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v2.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dumpgpio.c rename to arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c index 1f21684650bad..429e3e70a16d4 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dumpgpio.c + * arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -191,7 +191,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) getreg32(base + STM32_GPIO_AFRL_OFFSET), getreg32(base + STM32_GPIO_BRR_OFFSET)); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) DEBUGASSERT(port < STM32_NGPIO_PORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", diff --git a/arch/arm/src/common/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth.h new file mode 100644 index 0000000000000..6e77273239630 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# include "stm32_eth_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_eth" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_eth.c rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c index 3f1fdf514a366..3fc669d3ff79d 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.c + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,9 +57,11 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_syscfg.h" -#include "stm32_eth.h" +#include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include @@ -113,7 +115,7 @@ #endif #ifdef CONFIG_STM32_MII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK) # warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif @@ -128,7 +130,7 @@ #endif #ifdef CONFIG_STM32_RMII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK) # warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif @@ -322,7 +324,7 @@ * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define MACCR_CLEAR_BITS \ (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ @@ -518,7 +520,7 @@ * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define DMABMR_CLEAR_MASK \ (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h similarity index 94% rename from arch/arm/src/stm32/stm32_eth.h rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h index 68515b800068b..e2cfbdefe70cd 100644 --- a/arch/arm/src/stm32/stm32_eth.h +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.h + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_STM32_ETH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H /**************************************************************************** * Included Files @@ -106,4 +106,4 @@ int stm32_phy_boardinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/common/stm32/stm32_exti.h similarity index 94% rename from arch/arm/src/stm32/stm32_exti.h rename to arch/arm/src/common/stm32/stm32_exti.h index ae9ac9dba4ccf..8e301cf999700 100644 --- a/arch/arm/src/stm32/stm32_exti.h +++ b/arch/arm/src/common/stm32/stm32_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti.h + * arch/arm/src/common/stm32/stm32_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H /**************************************************************************** * Included Files @@ -31,6 +31,9 @@ #include +#include +#include + #include "chip.h" #include "hardware/stm32_exti.h" @@ -127,4 +130,5 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_alarm.c rename to arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c index e908fbae17fc8..e7b7d07cf8117 100644 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_alarm.c + * arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c index 5e8beb51a12a6..00b9158085c57 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c index abe6146c0be82..db62fac13f669 100644 --- a/arch/arm/src/stm32/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr.h new file mode 100644 index 0000000000000..f99225e585032 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_exti_pwr_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_exti_pwr" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32/stm32_exti_pwr.c rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c index 97b0060ac8c9e..0b83b171c19ea 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.c +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.c + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,8 +37,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" #include "stm32_exti.h" -#include "stm32_exti_pwr.h" +#include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_exti_pwr.h rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h index 9eb22090c6004..41058ed24aab6 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.h +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.h + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef STM32_EXTI_PWR_H_ -#define STM32_EXTI_PWR_H_ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H /**************************************************************************** * Included Files @@ -55,4 +55,4 @@ int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -#endif /* STM32_EXTI_PWR_H_ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_wakeup.c rename to arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c index dce70638d43ee..f3baba30545f5 100644 --- a/arch/arm/src/stm32/stm32_exti_wakeup.c +++ b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_wakeup.c + * arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_fdcan.h new file mode 100644 index 0000000000000..8a2dc52c68a33 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_fdcan.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Port numbers for use with stm32_fdcan_initialize() */ + +#define FDCAN1 1 + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# define FDCAN2 2 +# define FDCAN3 3 +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER +struct can_dev_s *stm32_fdcaninitialize(int port); +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_fdcansockinitialize(int port); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index 02d2c0f773de3..c9695564c9379 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c index f17be5729df59..d118271cf97dd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c index 519b77626e933..4e23a563b1c91 100644 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c index b4f37e29c6588..55d16f4234960 100644 --- a/arch/arm/src/stm32/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.h b/arch/arm/src/common/stm32/stm32_flash.h similarity index 70% rename from arch/arm/src/stm32f0l0g0/stm32_flash.h rename to arch/arm/src/common/stm32/stm32_flash.h index 1c670fa862c7a..9050b255d6bc1 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.h +++ b/arch/arm/src/common/stm32/stm32_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.h + * arch/arm/src/common/stm32/stm32_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,48 +20,47 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include #include #include "chip.h" #include "hardware/stm32_flash.h" /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) void stm32_flash_getopt(uint32_t *opt); - int stm32_flash_optmodify(uint32_t clear, uint32_t set); - void stm32_flash_lock(void); - void stm32_flash_unlock(void); -#undef EXTERN -#if defined(__cplusplus) -} +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) + +int stm32_flash_lock(void); +int stm32_flash_unlock(void); +uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); +size_t stm32_eeprom_size(void); +size_t stm32_eeprom_getaddress(void); +ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); +ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); + #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c index 1acb1b4a597e5..ec3a06037fbd5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c + * arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxf30xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c index a35d47482ba5e..5bdb27b1ddc35 100644 --- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxf30xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c similarity index 97% rename from arch/arm/src/stm32/stm32f20xxf40xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c index f8125b7ceb9f8..afd7300dda0f3 100644 --- a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxf40xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,7 +47,7 @@ /* Only for the STM32F[2|4]0xx family. */ -#if defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # warning "Default Flash Configuration Used - See Override Flash Size Designator" @@ -449,4 +449,4 @@ uint8_t up_progmem_erasestate(void) return FLASH_ERASEDVALUE; } -#endif /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#endif /* defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) */ diff --git a/arch/arm/src/stm32/stm32g4xxx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c index c14dd875a9ab5..f2d722e4799d2 100644 --- a/arch/arm/src/stm32/stm32g4xxx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c index 4051a7eafda5d..ec1379498f4a7 100644 --- a/arch/arm/src/stm32/stm32l15xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc.h new file mode 100644 index 0000000000000..c113a7995414d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) +# include "stm32_fmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H */ diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fmc.c rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c index 4f0ac88e2a165..aa91d1824b297 100644 --- a/arch/arm/src/stm32/stm32_fmc.c +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.c + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_fmc.h rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h index 9644068d0ee66..a29da3062fe8a 100644 --- a/arch/arm/src/stm32/stm32_fmc.h +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.h + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H -#define __ARCH_ARM_STC_STM32_STM32_FMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fmc.h" @@ -133,4 +135,6 @@ void stm32_fmc_sdram_command(uint32_t cmd); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc.h new file mode 100644 index 0000000000000..4f1b673f5674c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_COMMON_FOC) +# include "stm32_foc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_foc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H */ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_foc.c rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c index edced961d9af3..a50572a8bc570 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.c + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,13 +38,15 @@ #include "arm_internal.h" #include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "stm32_adc.h" #include "stm32_dma.h" #include #include -#include "stm32_foc.h" +#include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "hardware/stm32_dbgmcu.h" @@ -106,14 +108,14 @@ /* This is not for ADC IPv2 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) && defined(HAVE_BASIC_ADC) # error Not supported ADC IP core #endif /* Multi instances support tested only on IP_ADC_V1 */ #if CONFIG_MOTOR_FOC_INST > 1 -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Not tested yet # endif #endif @@ -141,10 +143,9 @@ /* Debug register for PWM timers */ -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +#if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +#elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) #endif @@ -154,10 +155,9 @@ # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) # endif # if CONFIG_STM32_TIM1_MODE != 2 @@ -171,10 +171,9 @@ # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) # endif # if CONFIG_STM32_TIM8_MODE != 2 @@ -248,14 +247,14 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) # endif @@ -314,14 +313,14 @@ * TIMx TRGO = (ARR) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) # endif @@ -470,11 +469,11 @@ /* Generalize ADC interrupt flags */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # define FOC_ADC_ISR_FOC ADC_ISR_JEOS # define FOC_ADC_IER_FOC ADC_IER_JEOS # define FOC_ADC_ISR_OVR ADC_INT_OVR -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # define FOC_ADC_ISR_FOC ADC_ISR_JEOC # define FOC_ADC_IER_FOC ADC_IER_JEOC # define FOC_ADC_ISR_OVR ADC_SR_OVR @@ -515,7 +514,7 @@ /* Common for ADCv1 */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && !defined(HAVE_BASIC_ADC) # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn123) @@ -530,7 +529,7 @@ /* Common for ADCv1 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && defined(HAVE_BASIC_ADC) # undef FOC_ADC_HAVE_CMN # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (0) @@ -545,7 +544,7 @@ /* Common for ADCv2 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn12) @@ -895,7 +894,7 @@ static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, ****************************************************************************/ #ifdef FOC_ADC_HAVE_CMN -# ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 /* Common for ADC123 */ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = @@ -903,9 +902,9 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = .cntr = 0, .lock = NXMUTEX_INITIALIZER, }; -# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 */ -# ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2) /* Common for ADC12 */ @@ -924,7 +923,7 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ -# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 */ #endif /* FOC_ADC_HAVE_CMN */ /* STM32 specific FOC data */ diff --git a/arch/arm/src/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_foc.h rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h index bfc145dbda8a1..58cddf08b2b45 100644 --- a/arch/arm/src/stm32/stm32_foc.h +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.h + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FOC_H -#define __ARCH_ARM_SRC_STM32_STM32_FOC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H /**************************************************************************** * Included Files @@ -200,4 +200,4 @@ struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FOC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H */ diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_freerun.h similarity index 54% rename from arch/arm/src/stm32/stm32_waste.h rename to arch/arm/src/common/stm32/stm32_freerun.h index 39a9b88893e6f..155917f7ea3af 100644 --- a/arch/arm/src/stm32/stm32_waste.h +++ b/arch/arm/src/common/stm32/stm32_freerun.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.h + * arch/arm/src/common/stm32/stm32_freerun.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,16 +20,36 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H - -/* Waste CPU Time */ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H /**************************************************************************** - * Pre-processor Definitions + * Included Files ****************************************************************************/ -#ifndef __ASSEMBLY__ +#include + +#include +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_FREERUN + +struct stm32_freerun_s +{ + uint8_t chan; + uint8_t width; + struct stm32_tim_dev_s *tch; + uint32_t frequency; +#ifndef CONFIG_CLOCK_TIMEKEEPING + uint32_t overflow; +#endif +#ifdef CONFIG_CLOCK_TIMEKEEPING + uint64_t counter_mask; +#endif +}; #undef EXTERN #if defined(__cplusplus) @@ -40,27 +60,22 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution); +#ifndef CONFIG_CLOCK_TIMEKEEPING +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts); +#else +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + uint64_t *counter); +#endif +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ +#endif /* CONFIG_STM32_FREERUN */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_freerun.c rename to arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c index af5599a931452..e8122d5ef413c 100644 --- a/arch/arm/src/stm32/stm32_freerun.c +++ b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.c + * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc.h new file mode 100644 index 0000000000000..15951027c411a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# include "stm32_fsmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fsmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H */ diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_fsmc.c rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c index 5bfc967a9614f..c72cf09477f2b 100644 --- a/arch/arm/src/stm32/stm32_fsmc.c +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.c + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,7 @@ void stm32_fsmc_enable(void) modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_enable(void) { @@ -73,7 +73,7 @@ void stm32_fsmc_disable(void) modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_disable(void) { diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h similarity index 88% rename from arch/arm/src/stm32/stm32_fsmc.h rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h index df340763016cc..215ce47c016f7 100644 --- a/arch/arm/src/stm32/stm32_fsmc.h +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.h + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FSMC_H -#define __ARCH_ARM_SRC_STM32_STM32_FSMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fsmc.h" @@ -73,4 +75,6 @@ void stm32_fsmc_disable(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio.h new file mode 100644 index 0000000000000..f4910cabef1de --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "stm32_gpio_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) +# include "stm32_gpio_m3m4_v1v2.h" +#else +# error "Unsupported STM32 GPIO" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.c index 7917ca44a79c0..3313cba03cdd7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.h index 0d6e7c881acf3..43990a8514a6e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ #endif #include -#include +#include #include "chip.h" #include "hardware/stm32_gpio.h" @@ -364,4 +364,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c index 947d75bf042c4..14fe1654baad8 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h index 8fc0ef475ebca..17689d672d9b2 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H /**************************************************************************** * Included Files @@ -559,4 +559,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_hall3ph.c b/arch/arm/src/common/stm32/stm32_hall3ph.c similarity index 98% rename from arch/arm/src/stm32/stm32_hall3ph.c rename to arch/arm/src/common/stm32/stm32_hall3ph.c index 4eff99aee7627..d6f7d360f5ca4 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.c +++ b/arch/arm/src/common/stm32/stm32_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.c + * arch/arm/src/common/stm32/stm32_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,6 +37,7 @@ #include "chip.h" #include "arm_internal.h" +#include "stm32_gpio.h" #include "stm32_hall3ph.h" /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_hall3ph.h b/arch/arm/src/common/stm32/stm32_hall3ph.h similarity index 85% rename from arch/arm/src/stm32/stm32_hall3ph.h rename to arch/arm/src/common/stm32/stm32_hall3ph.h index 97a7bde16bf44..e8329f84b2956 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.h +++ b/arch/arm/src/common/stm32/stm32_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.h + * arch/arm/src/common/stm32/stm32_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H -#define __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H /**************************************************************************** * Included Files @@ -47,10 +47,6 @@ struct stm32_hall3ph_cfg_s * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: stm32_hall3ph_initialize - ****************************************************************************/ - /**************************************************************************** * Name: stm32_hall3ph_initialize * @@ -62,4 +58,4 @@ struct stm32_hall3ph_cfg_s int stm32_hall3ph_initialize(const char *devpath, struct stm32_hall3ph_cfg_s *cfg); -#endif /* __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H */ diff --git a/arch/arm/src/common/stm32/stm32_hciuart.h b/arch/arm/src/common/stm32/stm32_hciuart.h new file mode 100644 index 0000000000000..f1ae1f79c8173 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hciuart.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hciuart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +enum hciuart_devno_e +{ + HCIUART1 = 0, + HCIUART2 = 1, + HCIUART3 = 2, + HCIUART5 = 5, + HCIUART6 = 6, + HCIUART7 = 7 +}; + +const struct btuart_lowerhalf_s * +hciuart_instantiate(enum hciuart_devno_e uart); +void hciuart_initialize(void); + +#ifdef CONFIG_STM32_HCIUART_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hciuart.c rename to arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c index cca04ded7239b..5f77bdc28997d 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.c + * arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,9 +46,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_uart.h" +#include "stm32_hciuart.h" #include "stm32_dma.h" #include "stm32_rcc.h" -#include "stm32_hciuart.h" +#include "stm32_uart.h" #include @@ -66,7 +67,7 @@ #ifdef CONFIG_STM32_HCIUART_RXDMA -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) /* Verify that DMA has been enabled and the DMA channel has been defined. */ @@ -152,7 +153,7 @@ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ defined(CONFIG_STM32_STM32F37XX) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -164,7 +165,7 @@ # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif @@ -174,7 +175,7 @@ /* DMA control word */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SERIAL_DMA_CONTROL_WORD \ (DMA_SCR_DIR_P2M | \ DMA_SCR_CIRC | \ diff --git a/arch/arm/src/common/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim.h new file mode 100644 index 0000000000000..0be3fcfe2f701 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) +# include "stm32_hrtim_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_hrtim" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.c rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c index 86e0a074b2633..73791c4c21fc8 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.c + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32.h" #include "stm32_gpio.h" -#include "stm32_hrtim.h" +#include "stm32_hrtim_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_hrtim_m3m4_v1.h" #if defined(CONFIG_STM32_HRTIM1) diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.h rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h index 7934ca14bff22..026c6e2e7f310 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.h + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H -#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H /**************************************************************************** * Included Files @@ -1136,4 +1136,4 @@ int hrtim_register(const char *path, struct hrtim_dev_s *dev); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_HRTIM1 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48.h new file mode 100644 index 0000000000000..6116df0117e42 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HSI48_M0_V1) +# include "stm32_hsi48_m0_v1.h" +#else +# error "Unsupported STM32 stm32_hsi48" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.c rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c index 9902f196f26b0..ac6162fc82bed 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.c + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include "hardware/stm32_rcc.h" #include "hardware/stm32_crs.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.h rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h index 216fce2501e86..095c9e62cc67c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.h + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H /**************************************************************************** * Included Files @@ -93,4 +93,4 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/common/stm32/stm32_i2c.h similarity index 84% rename from arch/arm/src/stm32/stm32_i2c.h rename to arch/arm/src/common/stm32/stm32_i2c.h index 1ad4f2b7f1ae1..834372fd75c7c 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/common/stm32/stm32_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.h + * arch/arm/src/common/stm32/stm32_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H /**************************************************************************** * Included Files @@ -88,6 +88,7 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port); int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) /**************************************************************************** * Name: stm32_i2cbus_slaveinitialize * @@ -104,22 +105,6 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); ****************************************************************************/ struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port); +#endif -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m0_v1.c index b2f689f97981a..b8cbdebce4cf2 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c index da30fd1342d72..4cc9c4f829187 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -1281,7 +1281,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) * from the F1 in that BTF is not set after data is received (only RXNE). */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) || \ defined(CONFIG_STM32_STM32L15XX) if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0) #else @@ -1941,5 +1941,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_alt.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c index 115a5a8d1033e..3f4055fd0bf7f 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_alt.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. @@ -112,7 +112,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -172,7 +172,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2448,5 +2448,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c index 58b769fc5d96a..9ed73e228db8f 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2690,5 +2690,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c index 87d9a1700e0ba..8b0fd802c5e4a 100644 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2cslave_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2cslave_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c index bbf86c2e49d68..53ce3975f1673 100644 --- a/arch/arm/src/stm32/stm32_i2cslave_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2cslave_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/common/stm32/stm32_i2s.h similarity index 78% rename from arch/arm/src/stm32/stm32_i2s.h rename to arch/arm/src/common/stm32/stm32_i2s.h index 5ed34136591cf..376fa24efed81 100644 --- a/arch/arm/src/stm32/stm32_i2s.h +++ b/arch/arm/src/common/stm32/stm32_i2s.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.h + * arch/arm/src/common/stm32/stm32_i2s.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,32 +20,35 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2S_H -#define __ARCH_ARM_SRC_STM32_STM32_I2S_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include "chip.h" +#ifdef CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 -#ifndef __ASSEMBLY__ +# include + +# include "chip.h" + +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes @@ -67,10 +70,13 @@ extern "C" struct i2s_dev_s *stm32_i2sbus_initialize(int port); -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } -#endif +# endif + +# endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 */ -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2S_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H */ diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2s.c rename to arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c index af156dd8a7eac..49be32aa82630 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.c + * arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -72,6 +72,7 @@ #include "arm_internal.h" #include "stm32_dma.h" +#include "stm32_i2s.h" #include "stm32_spi.h" #include "stm32_rcc.h" @@ -144,7 +145,7 @@ # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -154,7 +155,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -176,7 +177,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m0_v1.c index 1b971a961caf6..a9d6ff68a084b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c index 22f559f276752..19f57a3117eac 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m0_v1.c index c46388c264139..fb71ce0917a1e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c index 57ed8ba1a4406..c79c0bddd8deb 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c index f282194202027..172534d89e831 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -43,6 +43,14 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -69,6 +77,14 @@ /* Configuration ************************************************************/ +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + /* REVISIT: It appears that you can only setup the prescaler and reload * registers once. After that, the SR register's PVU and RVU bits never go * to zero. So we defer setting up these registers until the watchdog @@ -116,17 +132,25 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +#endif + static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); /**************************************************************************** * Private Data @@ -153,6 +177,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 IWDG register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setprescaler * @@ -170,7 +278,7 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { /* Enable write access to IWDG_PR and IWDG_RLR registers */ - putreg32(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset be hardware. These bits * were set the last time that the PR register was written and may not @@ -181,20 +289,20 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) */ #ifndef CONFIG_STM32_IWDG_ONETIMESETUP - while ((getreg32(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); + while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); #endif /* Set the prescaler */ - putreg32((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - putreg32((uint16_t)priv->reload, STM32_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); } /**************************************************************************** @@ -244,7 +352,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_START, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -303,7 +411,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -561,33 +669,41 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_rcc_enablelsi(); -#ifdef STM32_RCC_CSR wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); -#else - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR1)); -#endif /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, IWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - /* When the microcontroller enters debug mode (core halted), + /* When the microcontroller enters debug mode (Cortex-M4F core halted), * the IWDG counter either continues to work normally or stops, depending * on DBG_IWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_IWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c index 8996a9e845e9b..026b0edf05370 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_lowputc.h b/arch/arm/src/common/stm32/stm32_lowputc.h new file mode 100644 index 0000000000000..0c2ddb9156d36 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_lowputc.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_lowputc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization of serial console. + * + ****************************************************************************/ + +void stm32_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c index 2f3e87315b390..03acef0e8d0f7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c index db8065517c3f1..154051ca63cc2 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c index ff9659c97107e..aa83d21a3b3e2 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m0_v1.c index 9fb81ae318eb0..0e5bc4fbc3db5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c index 7f4d215ddc1d7..25f33542e59c4 100644 --- a/arch/arm/src/stm32/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m0_v1.c index cfcc05e19027c..19aa04dd4f037 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,11 +33,11 @@ * Pre-processor Definitions ****************************************************************************/ -/* STM32C0 use the second CSR register for LSI */ +/* STM32C0 uses the second CSR register for LSI. */ #ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION # define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY #endif diff --git a/arch/arm/src/stm32/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c similarity index 92% rename from arch/arm/src/stm32/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c index 45d15c8fab1c1..97ae757a001b7 100644 --- a/arch/arm/src/stm32/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,6 +33,14 @@ * Pre-processor Definitions ****************************************************************************/ +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION +# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +#endif + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc.h new file mode 100644 index 0000000000000..d51c2b4ba3d38 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) +# include "stm32_ltdc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_ltdc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_ltdc.c rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c index 8e36b797a5e97..59bc7fc4484ee 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.c + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,8 +49,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ltdc.h" -#include "stm32_dma2d.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h similarity index 91% rename from arch/arm/src/stm32/stm32_ltdc.h rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h index 50e089869e09a..c0e4e3adb5fbb 100644 --- a/arch/arm/src/stm32/stm32_ltdc.h +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.h + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + #include #include @@ -99,4 +101,6 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); #ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_LTDC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H */ diff --git a/arch/arm/src/common/stm32/stm32_mpuinit.h b/arch/arm/src/common/stm32/stm32_mpuinit.h new file mode 100644 index 0000000000000..606d589ef28e4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_mpuinit.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_mpuinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mpuinitialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted MCU + * resources. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void stm32_mpuinitialize(void); +#else +# define stm32_mpuinitialize() +#endif + +/**************************************************************************** + * Name: stm32_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void stm32_mpu_uheap(uintptr_t start, size_t size); +#else +# define stm32_mpu_uheap(start,size) +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.c b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_mpuinit.c rename to arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c index 6cc545c825ea4..cc066077de60b 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.c +++ b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.c + * arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_oneshot.h b/arch/arm/src/common/stm32/stm32_oneshot.h new file mode 100644 index 0000000000000..7cb508f67d48f --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_ONESHOT + +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 +#endif + +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 +# warning Additional logic required to handle more than 8 timers +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 +#endif + +typedef void (*oneshot_handler_t)(void *arg); + +struct stm32_oneshot_s +{ + uint8_t chan; +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 + uint8_t cbndx; +#endif + volatile bool running; + struct stm32_tim_dev_s *tch; + volatile oneshot_handler_t handler; + volatile void *arg; + uint32_t frequency; + uint32_t period; +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution); +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_ONESHOT */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c index b80df41e76265..e8ba155e9daf7 100644 --- a/arch/arm/src/stm32/stm32_oneshot.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c index 8d5c5c79a2861..729adb4078c3e 100644 --- a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot_lowerhalf.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp.h new file mode 100644 index 0000000000000..f3c9827a95927 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) +# include "stm32_opamp_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_opamp" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_opamp.c b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_opamp.c rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c index 05f685eab55a4..7c90dae4b8b8d 100644 --- a/arch/arm/src/stm32/stm32_opamp.c +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.c + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32_gpio.h" -#include "stm32_opamp.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_opamp_m3m4_v1.h" /* OPAMP "upper half" support must be enabled */ diff --git a/arch/arm/src/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_opamp.h rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h index b85acb37bff16..d45a753223622 100644 --- a/arch/arm/src/stm32/stm32_opamp.h +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.h + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H -#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H /**************************************************************************** * Included Files @@ -216,4 +216,4 @@ struct opamp_dev_s *stm32_opampinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OPAMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/common/stm32/stm32_otgfs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otgfs.h rename to arch/arm/src/common/stm32/stm32_otgfs.h index 42287bc2120ea..b7cf5962ed05d 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/common/stm32/stm32_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfs.h + * arch/arm/src/common/stm32/stm32_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfsdev.c rename to arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c index 2f3c1416e7ee6..af02d027c98cd 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfsdev.c + * arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfshost.c rename to arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c index b8a44c901782f..1197648cd1b26 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfshost.c + * arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGFS) diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/common/stm32/stm32_otghs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otghs.h rename to arch/arm/src/common/stm32/stm32_otghs.h index 68016e3793fd8..c64843045937e 100644 --- a/arch/arm/src/stm32/stm32_otghs.h +++ b/arch/arm/src/common/stm32/stm32_otghs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghs.h + * arch/arm/src/common/stm32/stm32_otghs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGHS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGHS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghsdev.c rename to arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c index a4fae9cad4fea..4a0e61a213236 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghsdev.c + * arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghshost.c rename to arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c index 4acc263c4209f..45faa0a4963e8 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghshost.c + * arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGHS) diff --git a/arch/arm/src/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_pm.h similarity index 58% rename from arch/arm/src/stm32/stm32_fdcan.h rename to arch/arm/src/common/stm32/stm32_pm.h index f157213828d9b..f9bdebd9f6031 100644 --- a/arch/arm/src/stm32/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/stm32_pm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.h + * arch/arm/src/common/stm32/stm32_pm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H /**************************************************************************** * Included Files @@ -29,33 +29,25 @@ #include -#include "chip.h" -#include "hardware/stm32_fdcan.h" +#include -#include +#include "chip.h" +#include "arm_internal.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 -#define FDCAN2 2 -#define FDCAN3 3 - /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ - /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) +#ifndef __ASSEMBLY__ +#ifdef __cplusplus #define EXTERN extern "C" extern "C" { @@ -67,48 +59,69 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /**************************************************************************** - * Name: stm32_fdcaninitialize + * Name: stm32_pmstop * * Description: - * Initialize the selected FDCAN port + * Enter STOP mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). * * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal voltage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. * ****************************************************************************/ -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32_fdcansockinitialize + * Name: stm32_pmstandby * * Description: - * Initialize the selected FDCAN port as SocketCAN interface + * Enter STANDBY mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * None * * Returned Value: - * OK on success; Negated errno on failure. + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. * ****************************************************************************/ -int stm32_fdcansockinitialize(int port); -#endif +int stm32_pmstandby(void); + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep + * mode as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif - #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FDCAN_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_pminitialize.c b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_pminitialize.c rename to arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c index 2f9883b2123d0..6120feeb7c4f3 100644 --- a/arch/arm/src/stm32/stm32_pminitialize.c +++ b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pminitialize.c + * arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmsleep.c b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmsleep.c rename to arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c index 5f78cc8626884..24113447340a5 100644 --- a/arch/arm/src/stm32/stm32_pmsleep.c +++ b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmsleep.c + * arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstandby.c b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstandby.c rename to arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c index d8b9825aed5e1..71195ed4bc59b 100644 --- a/arch/arm/src/stm32/stm32_pmstandby.c +++ b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstandby.c + * arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstop.c b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstop.c rename to arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c index 9acf05990f9aa..82ce0a60bc0e8 100644 --- a/arch/arm/src/stm32/stm32_pmstop.c +++ b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstop.c + * arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h b/arch/arm/src/common/stm32/stm32_pulsecount.h similarity index 87% rename from arch/arm/src/stm32f0l0g0/stm32_pulsecount.h rename to arch/arm/src/common/stm32/stm32_pulsecount.h index 8c8aca535f1a7..ec76dfe48e4ec 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h +++ b/arch/arm/src/common/stm32/stm32_pulsecount.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.h + * arch/arm/src/common/stm32/stm32_pulsecount.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H /**************************************************************************** * Included Files @@ -36,4 +36,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c index e644f31003f22..e64d5be88fedf 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c index c8aea22c4e19e..d73a83d002294 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.h b/arch/arm/src/common/stm32/stm32_pwm.h similarity index 69% rename from arch/arm/src/stm32/stm32_pulsecount.h rename to arch/arm/src/common/stm32/stm32_pwm.h index 20ccf3608fed1..c2a9a90789744 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.h +++ b/arch/arm/src/common/stm32/stm32_pwm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.h + * arch/arm/src/common/stm32/stm32_pwm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,20 +20,23 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_pwm_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_pwm_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 PWM" +#endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.c index 0710973de1b91..cf7e6a3b23843 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.h index fc5beb4482cde..eafff64985fa6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H /* The STM32F0L0G0 does not have dedicated PWM hardware. Rather, pulsed * output control is a capability of the STM32F0L0G0 timers. The logic in @@ -560,4 +560,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* CONFIG_STM32_TIMx_PWM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c index 4b7d1378d8240..17fff3b6e3e7f 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h index f2f7191bcf077..032a0410d40d4 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H /* The STM32 does not have dedicated PWM hardware. Rather, pulsed output * control is a capability of the STM32 timers. The logic in this file @@ -1175,4 +1175,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_PWM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h similarity index 94% rename from arch/arm/src/stm32/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_pwr.h index 141f81a360910..f7d0ec2b90956 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H /**************************************************************************** * Included Files @@ -30,29 +30,17 @@ #include #include +#include #include "chip.h" #include "hardware/stm32_pwr.h" /**************************************************************************** - * Pre-processor Definitions + * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - /* Identify MCU-specific wakeup pin. * Different STM32 parts support differing numbers of wakeup pins. */ @@ -68,6 +56,15 @@ enum stm32_pwr_wupin_e * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /**************************************************************************** * Name: stm32_pwr_enablesdadc * @@ -112,7 +109,7 @@ void stm32_pwr_initbkp(bool writable); * * Description: * Enables access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM). + * (RTC registers, RTC backup data registers and backup SRAM). * * NOTE: * Reference counting is used in order to supported nested calls to this @@ -214,8 +211,9 @@ void stm32_pwr_enablebreg(bool region); * ****************************************************************************/ -#ifdef CONFIG_STM32_ENERGYLITE +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) void stm32_pwr_setvos(uint16_t vos); +#endif /**************************************************************************** * Name: stm32_pwr_setpvd @@ -234,6 +232,7 @@ void stm32_pwr_setvos(uint16_t vos); * ****************************************************************************/ +#ifdef CONFIG_STM32_ENERGYLITE void stm32_pwr_setpvd(uint16_t pls); /**************************************************************************** @@ -264,4 +263,5 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32g0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_g0.c index 0e8b03e12efdc..d1627f7fa5f8c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_g0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_v1.c index 6516b14f98cba..5ff40ed9e6665 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c index b55c301cd3622..0d2bed7a90f57 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.h b/arch/arm/src/common/stm32/stm32_qencoder.h similarity index 84% rename from arch/arm/src/stm32/stm32_qencoder.h rename to arch/arm/src/common/stm32/stm32_qencoder.h index a8c9ff66e002c..e82881b3032d1 100644 --- a/arch/arm/src/stm32/stm32_qencoder.h +++ b/arch/arm/src/common/stm32/stm32_qencoder.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.h + * arch/arm/src/common/stm32/stm32_qencoder.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32_STM32_QENCODER_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H /**************************************************************************** * Included Files @@ -34,13 +34,13 @@ #ifdef CONFIG_SENSORS_QENCODER /**************************************************************************** - * Included Files + * Pre-processor Definitions ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that timer - * "n" is intended to be used for as a quadrature encoder. + * then CONFIG_STM32_TIMn_QE indicates that timer "n" is intended to be used + * as a quadrature encoder. */ #ifndef CONFIG_STM32_TIM1 @@ -62,9 +62,7 @@ # undef CONFIG_STM32_TIM8_QE #endif -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder (at least - * for the STM32 F4) - */ +/* Basic and small general-purpose timers do not support encoder mode. */ #undef CONFIG_STM32_TIM6_QE #undef CONFIG_STM32_TIM7_QE @@ -74,9 +72,12 @@ #undef CONFIG_STM32_TIM12_QE #undef CONFIG_STM32_TIM13_QE #undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** @@ -84,12 +85,11 @@ * * Description: * Initialize a quadrature encoder interface. This function must be called - * from board-specific logic.. + * from board-specific logic. * * Input Parameters: * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} + * tim - The timer number to use. * * Returned Value: * Zero on success; A negated errno value is returned on failure. @@ -118,4 +118,5 @@ int stm32_qe_index_init(int tim, uint32_t gpio); #endif #endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_QENCODER_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c index 65cc99455469d..e88ff33418d2b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c index 1c0a9921b4ea5..f5c4bea0d22a0 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_rcc.h similarity index 51% rename from arch/arm/src/stm32f0l0g0/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_rcc.h index 1562b6073283e..c2c57a6a0b6b4 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H /**************************************************************************** * Included Files @@ -29,12 +29,10 @@ #include -#include - +#include "arm_internal.h" #include "chip.h" -#include "hardware/stm32_pwr.h" -#ifdef CONFIG_STM32_PWR +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -52,177 +50,178 @@ extern "C" #endif /**************************************************************************** - * Public Types + * Inline Functions ****************************************************************************/ -/* Identify MCU-specific wakeup pin. Different STM32 parts support differing - * numbers of wakeup pins. - */ +/**************************************************************************** + * Name: stm32_mco1config + * + * Description: + * Selects the clock source to output on MCO1 pin (PA8). PA8 should be + * configured in alternate function mode. + * + ****************************************************************************/ -enum stm32_pwr_wupin_e +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco1config(uint32_t source, uint32_t div) { - PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ - PWR_WUPIN_2, /* Wake-up pin 2 */ - PWR_WUPIN_3 /* Wake-up pin 3 */ -}; + uint32_t regval; -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /**************************************************************************** - * Name: stm32_pwr_initbkp + * Name: stm32_mcoconfig * * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. - * - * NOTE: This function should only be called by SoC Start up code. - * - * Input Parameters: - * writable - set the initial state of the enable and the - * bkp_writable_counter - * - * Returned Value: - * None + * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. + * PA8 should be configured in alternate function mode. * ****************************************************************************/ -void stm32_pwr_initbkp(bool writable); +#if defined(CONFIG_STM32_CONNECTIVITYLINE) +static inline void stm32_mcoconfig(uint32_t source) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO_MASK); + regval |= (source & RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /**************************************************************************** - * Name: stm32_pwr_enablebkp + * Name: stm32_mcodivconfig * * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None + * Selects the clock source to output and clock divider on MC pin (PA4) for + * stm32l1xxx. PA4 should be configured in alternate function mode. * ****************************************************************************/ -void stm32_pwr_enablebkp(bool writable); +#if defined(CONFIG_STM32_STM32L15XX) +static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCOSEL_MASK); + regval |= (source & RCC_CFGR_MCOSEL_MASK); + regval &= ~(RCC_CFGR_MCOPRE_MASK); + regval |= (divider & RCC_CFGR_MCOPRE_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /**************************************************************************** - * Name: stm32_pwr_enablewkup + * Name: stm32_mco2config * * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. + * Selects the clock source to output on MCO2 pin (PC9). PC9 should be + * configured in alternate function mode. * ****************************************************************************/ -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco2config(uint32_t source, uint32_t div) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ /**************************************************************************** - * Name: stm32_pwr_getsbf + * Name: stm32_clockconfig * * Description: - * Return the standby flag. + * Called to initialize the STM32F0XX. + * This does whatever setup is needed to put the MCU in a usable state. + * This includes the initialization of clocking using the settings + * in board.h. * ****************************************************************************/ -bool stm32_pwr_getsbf(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32_pwr_getwuf + * Name: stm32_board_clockconfig * * Description: - * Return the wakeup flag. + * Any STM32 board may replace the standard board clock configuration logic + * with its own custom clock configuration logic. * ****************************************************************************/ -bool stm32_pwr_getwuf(void); +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); +#endif /**************************************************************************** - * Name: stm32_pwr_setvos + * Name: stm32_clockenable * * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. + * Re-enable the clock and restore the clock settings after low-power + * modes. * ****************************************************************************/ -#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) -void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */ +#ifdef CONFIG_PM +void stm32_clockenable(void); +#endif /**************************************************************************** - * Name: stm32_pwr_setpvd + * Name: stm32_rcc_enablelse * * Description: - * Sets power voltage detector for EnergyLite devices. + * Enable the External Low-Speed (LSE) Oscillator. * * Input Parameters: - * pls - PVD level + * None * * Returned Value: * None * - * Assumptions: - * At present, this function is called only from initialization logic. - * ****************************************************************************/ -#if defined(CONFIG_STM32_ENERGYLITE) -void stm32_pwr_setpvd(uint16_t pls); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32_pwr_enablepvd + * Name: stm32_rcc_enablelsi * * Description: - * Enable the Programmable Voltage Detector + * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_pwr_enablepvd(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32_pwr_disablepvd + * Name: stm32_rcc_disablelsi * * Description: - * Disable the Programmable Voltage Detector + * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_pwr_disablepvd(void); - -#endif /* CONFIG_STM32_ENERGYLITE */ +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) } #endif - #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_PWR */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m0_v1.c index 9a4c46aaa0bef..837ed6ce85ee4 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32f0l0g0/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c index 2ccebb1060b5d..a40caf80bd529 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -158,7 +158,7 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) rngsr = getreg32(STM32_RNG_SR); if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ - || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ + || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ { /* This random value is not valid, we will try again. */ @@ -172,8 +172,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * RNGEN bit should not be used, but saved for comparison with the next * generated random number. Each subsequent generated random number has to * be compared with the previously generated number. The test fails if any - * two compared numbers are equal - * (continuous random number generator test). + * two compared numbers are equal (continuous random number generator + * test). */ if (g_rngdev.rd_first) @@ -223,8 +223,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * Name: stm32_rng_read ****************************************************************************/ -static ssize_t stm32_rng_read(struct file *filep, - char *buffer, size_t buflen) +static ssize_t stm32_rng_read(struct file *filep, char *buffer, + size_t buflen) { int ret; @@ -234,7 +234,7 @@ static ssize_t stm32_rng_read(struct file *filep, return ret; } - /* We've got the semaphore. */ + /* We've got the mutex. */ /* Reset the operation semaphore with 0 for blocking until the * buffer is filled from interrupts. diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/common/stm32/stm32_rtc.h similarity index 96% rename from arch/arm/src/stm32/stm32_rtc.h rename to arch/arm/src/common/stm32/stm32_rtc.h index 3df1ac02a7b3d..96c8e4f5b8bcb 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/common/stm32/stm32_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.h + * arch/arm/src/common/stm32/stm32_rtc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,11 +24,13 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H #include +#ifdef CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 + #include "chip.h" /* The STM32 F1 has a simple battery-backed counter for its RTC and has a @@ -222,4 +224,6 @@ struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtc_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c index 69c59d6f8879d..e8c1c75fc9d84 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc_lowerhalf.c + * arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c index 6917d43fd3472..9dff0b4bccab7 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c index 3a37110089d26..06d729c437bc9 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c index cd0e55db467f6..fac37d3b5638a 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcounter.c rename to arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c index a93fcb4f8904b..6f5259e449806 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcounter.c + * arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc.h new file mode 100644 index 0000000000000..f69f80d1d56de --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) +# include "stm32_sdadc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdadc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H */ diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdadc.c rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c index 783dd03c6cc28..23e5fc8a33f22 100644 --- a/arch/arm/src/stm32/stm32_sdadc.c +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.c + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015-2017 Gregory Nutt. All rights reserved. @@ -64,8 +64,10 @@ #include "chip.h" #include "stm32.h" #include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #include "stm32_pwr.h" -#include "stm32_sdadc.h" +#include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #ifdef CONFIG_STM32_SDADC diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_sdadc.h rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h index 75d474efa568d..6906d43f07c11 100644 --- a/arch/arm/src/stm32/stm32_sdadc.h +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.h + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Gregory Nutt. All rights reserved. @@ -37,8 +37,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H -#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H /**************************************************************************** * Included Files @@ -428,4 +428,4 @@ struct adc_dev_s *stm32_sdadcinitialize(int intf, #endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || * CONFIG_STM32_SDADC3 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio.h new file mode 100644 index 0000000000000..8dc71bb2709d6 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) +# include "stm32_sdio_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdio" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H */ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdio.c rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c index 5d6e5cfc44126..3387e111c4e0e 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.c + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,9 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_dma.h" -#include "stm32_sdio.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_dma.h" +#include "stm32_sdio_m3m4_v1.h" #ifdef CONFIG_STM32_SDIO @@ -107,7 +109,7 @@ # ifndef CONFIG_STM32_SDIO_DMAPRIO # if defined(CONFIG_STM32_STM32F10XX) # define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI # else # error "Unknown STM32 DMA" @@ -117,7 +119,7 @@ # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif @@ -199,7 +201,7 @@ /* STM32 F4 stream configuration register (SCR) settings. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ @@ -219,7 +221,7 @@ #if defined(CONFIG_STM32_STM32F10XX) # define SDIO_DMACHAN DMACHAN_SDIO -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_DMACHAN DMAMAP_SDIO #else # error "Unknown STM32 DMA" diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_sdio.h rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h index d74b3fe398949..8ffd42b7eecbd 100644 --- a/arch/arm/src/stm32/stm32_sdio.h +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.h + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,17 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_STM32_SDIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H /**************************************************************************** * Included Files ****************************************************************************/ #include + +#ifdef CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 + #include #include @@ -133,4 +136,6 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */ + +#endif /* CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v1.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v3.c index 444e48887214f..504e31b9c49e6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c + * arch/arm/src/common/stm32/stm32_serial_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v2.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v4.c index 0d9d208c67fba..feb3307bc6d84 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v2.c + * arch/arm/src/common/stm32/stm32_serial_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_serial.c rename to arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c index 09cbe58c2fc50..c5b3f861d109a 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_serial.c + * arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/common/stm32/stm32_spi.h similarity index 94% rename from arch/arm/src/stm32/stm32_spi.h rename to arch/arm/src/common/stm32/stm32_spi.h index 13a48fb92cea0..9e861bcc69025 100644 --- a/arch/arm/src/stm32/stm32_spi.h +++ b/arch/arm/src/common/stm32/stm32_spi.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.h + * arch/arm/src/common/stm32/stm32_spi.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H /**************************************************************************** * Included Files @@ -29,6 +29,13 @@ #include +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#endif + #include #include "chip.h" @@ -206,4 +213,4 @@ int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m0_v1.c index ae149747b0815..9b32cd490f5b0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c index 62b019ce07ed8..567f79a95fe27 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -103,7 +103,7 @@ # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -114,7 +114,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -135,7 +135,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/common/stm32/stm32_start.h b/arch/arm/src/common/stm32/stm32_start.h new file mode 100644 index 0000000000000..ad9bbda5e31f1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_start.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_start.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void); + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m0_v1.c index 9b1449d4fb716..b2585f49bc627 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m3m4_v1.c index e4abdb7d3e980..ad74f104e3c61 100644 --- a/arch/arm/src/stm32/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/common/stm32/stm32_syscfg.h similarity index 90% rename from arch/arm/src/stm32/stm32_syscfg.h rename to arch/arm/src/common/stm32/stm32_syscfg.h index 74d049711a61f..1e95d770342d8 100644 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_syscfg.h + * arch/arm/src/common/stm32/stm32_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_tickless.c rename to arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c index 3cd076bf1d742..1e49c2a3cb3d8 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tickless.c + * arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h new file mode 100644 index 0000000000000..77d884e06727a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_tim_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.c index 48a549aa41501..9401a884a27c0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.h index ba9d7c7fbc4b8..07c0ef1f7e592 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -230,4 +230,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c index dbb558fa81b68..356a3e9e6c782 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c index 71774e2898b47..65a9a062d05bd 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h similarity index 96% rename from arch/arm/src/stm32/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h index 6e01e6693d7ae..9bd99fb862f29 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H /**************************************************************************** * Included Files @@ -222,4 +222,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c index 14407bdc4f76f..25d5b63192639 100644 --- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv6m.c index 9a92038c40141..a3136b8657912 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv6m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c similarity index 99% rename from arch/arm/src/stm32/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv7m.c index c4fa9c76fb601..b7f8e713252f6 100644 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv7m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart.h new file mode 100644 index 0000000000000..29de62701fe9c --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ARMV6M) +# if defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m0_v1.h" +# else +# error "Unsupported STM32 UART core for M0" +# endif +#elif defined(CONFIG_STM32_HAVE_IP_USART_V1) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m3m4_v1v2.h" +#else +# error "Unsupported STM32 UART" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m0_v1.h index 9ebcefc8fc5a9..5844f46e08413 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H /**************************************************************************** * Included Files @@ -449,4 +449,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H */ diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h similarity index 96% rename from arch/arm/src/stm32/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h index 3723edd4c1e22..c4e20a1a781f1 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H -#define __ARCH_ARM_STC_STM32_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H /**************************************************************************** * Included Files @@ -31,23 +31,7 @@ #include #include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f30xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_uart.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_uart.h" -#else -# error "Unsupported STM32 UART" -#endif +#include "hardware/stm32_uart.h" /**************************************************************************** * Pre-processor Definitions @@ -665,4 +649,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.h b/arch/arm/src/common/stm32/stm32_uid.h similarity index 79% rename from arch/arm/src/stm32f0l0g0/stm32_uid.h rename to arch/arm/src/common/stm32/stm32_uid.h index 34661df85deb7..e925374353edd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.h +++ b/arch/arm/src/common/stm32/stm32_uid.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.h + * arch/arm/src/common/stm32/stm32_uid.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,19 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H /**************************************************************************** * Included Files ****************************************************************************/ +#include + #include /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_UID_M0_V1) void stm32_get_uniqueid(uint32_t *uid); +#elif defined(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) +void stm32_get_uniqueid(uint8_t uniqueid[12]); +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m0_v1.c index a57b048b8a79a..9f9be6610a7ab 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c index fa274e1d62ae3..9986db93d7c39 100644 --- a/arch/arm/src/stm32/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h b/arch/arm/src/common/stm32/stm32_usbdev.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.h rename to arch/arm/src/common/stm32/stm32_usbdev.h index afa99490451f9..1d1a989b0d082 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/stm32_usbdev.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.h + * arch/arm/src/common/stm32/stm32_usbdev.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -34,6 +34,16 @@ #include "chip.h" #include "hardware/stm32_usbdev.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#ifndef STM32_NENDPOINTS +# define STM32_NENDPOINTS (8) +#endif + /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ @@ -81,4 +91,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c index d98ef7274af32..59632743a295c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c index 09e7393131211..f84789892b163 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs.h new file mode 100644 index 0000000000000..443a87bacfe36 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) +# include "stm32_usbfs_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbfs" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H */ diff --git a/arch/arm/src/stm32/stm32_usbfs.c b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbfs.c rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c index cb6cf7f47459a..418dcf33211f8 100644 --- a/arch/arm/src/stm32/stm32_usbfs.c +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.c + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,8 +47,10 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #include "stm32_gpio.h" -#include "stm32_usbfs.h" +#include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #if defined(CONFIG_STM32_USBFS) diff --git a/arch/arm/src/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h similarity index 92% rename from arch/arm/src/stm32/stm32_usbfs.h rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h index b9c7ed0405b62..8a5b8adf76287 100644 --- a/arch/arm/src/stm32/stm32_usbfs.h +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.h + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_STM32_USBFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H /**************************************************************************** * Included Files @@ -76,4 +76,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost.h new file mode 100644 index 0000000000000..c659a23a25b7e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_usbhost_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbhost" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_usbhost.c b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbhost.c rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c index 1314be9c5e481..d6241c81881a8 100644 --- a/arch/arm/src/stm32/stm32_usbhost.c +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.c + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #ifdef HAVE_USBHOST_TRACE diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_usbhost.h rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h index b71a9e46a7c09..867260f81c8d1 100644 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.h + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBHOST_H -#define __ARCH_ARM_SRC_STM32_STM32_USBHOST_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H /**************************************************************************** * Included Files @@ -280,4 +280,4 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS && CONFIG_STM32_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBHOST_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/common/stm32/stm32_userspace.h similarity index 66% rename from arch/arm/src/stm32/stm32_comp.h rename to arch/arm/src/common/stm32/stm32_userspace.h index 5f3ae2c74e916..36da6f4a783ab 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/common/stm32/stm32_userspace.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp.h + * arch/arm/src/common/stm32/stm32_userspace.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -29,18 +29,8 @@ #include -#include "chip.h" - -#include "hardware/stm32_comp.h" - -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) -# include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) -# include "stm32_comp_v2.h" -#endif - /**************************************************************************** - * Pre-processor definitions + * Pre-processor Definitions ****************************************************************************/ /**************************************************************************** @@ -48,42 +38,26 @@ ****************************************************************************/ /**************************************************************************** - * Public Function Prototypes + * Public Data ****************************************************************************/ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ /**************************************************************************** - * Name: stm32_compinitialize + * Name: stm32_userspace * * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. * ****************************************************************************/ -struct comp_dev_s *stm32_compinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} +#ifdef CONFIG_BUILD_PROTECTED +void stm32_userspace(void); #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.c b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_userspace.c rename to arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c index 92897821b352e..31f567ecd0295 100644 --- a/arch/arm/src/stm32/stm32_userspace.c +++ b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.c + * arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_waste.h new file mode 100644 index 0000000000000..702c166346ab1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_waste.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_waste.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +void stm32_waste(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32/stm32_waste.c b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_waste.c rename to arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c index ce40916f4f9c8..b689d1d91b040 100644 --- a/arch/arm/src/stm32/stm32_waste.c +++ b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.c + * arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/common/stm32/stm32_wdg.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_wdg.h rename to arch/arm/src/common/stm32/stm32_wdg.h index 96ce766df5585..c70b669ad87d7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ b/arch/arm/src/common/stm32/stm32_wdg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wdg.h + * arch/arm/src/common/stm32/stm32_wdg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H /**************************************************************************** * Included Files @@ -101,4 +101,4 @@ void stm32_wwdginitialize(const char *devpath); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c index 26decaa9e5f33..9ec66a9fa9294 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c index f8717ce0f2c33..8d8ccdac2b02a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,6 +40,8 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -63,6 +65,16 @@ #define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) #define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -89,25 +101,33 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window); /* Interrupt handling *******************************************************/ -static int stm32_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -134,6 +154,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setwindow * @@ -145,16 +249,17 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window) +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window) { uint16_t regval; /* Set W[6:0] bits according to selected window value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_W_MASK; regval |= window << WWDG_CFR_W_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Remember the window setting */ @@ -182,7 +287,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) /* Check if the EWI interrupt is really pending */ - regval = getreg32(STM32_WWDG_SR); + regval = stm32_getreg(STM32_WWDG_SR); if ((regval & WWDG_SR_EWIF) != 0) { /* Is there a registered handler? */ @@ -202,7 +307,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) */ regval &= ~WWDG_SR_EWIF; - putreg32(regval, STM32_WWDG_SR); + stm32_putreg(regval, STM32_WWDG_SR); } return OK; @@ -235,7 +340,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) * except by a reset. */ - putreg32(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); + stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); priv->started = true; return OK; } @@ -300,7 +405,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) * a read-modify-write; writing a 0 to WDGA bit does nothing. */ - putreg32((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); + stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); return OK; } @@ -349,7 +454,7 @@ static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, /* Get the time remaining until the watchdog expires (in milliseconds) */ - reload = (getreg32(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; + reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; elapsed = priv->reload - reload; status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); @@ -479,10 +584,10 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, /* Set WDGTB[1:0] bits according to calculated value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_WDGTB_MASK; regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Reset the 7-bit window value to the maximum value.. essentially * disabling the lower limit of the watchdog reset time. @@ -536,13 +641,13 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Are we attaching or detaching the handler? */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); if (handler) { /* Attaching... Enable the EWI interrupt */ regval |= WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_enable_irq(STM32_IRQ_WWDG); } @@ -551,7 +656,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Detaching... Disable the EWI interrupt */ regval &= ~WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_disable_irq(STM32_IRQ_WWDG); } @@ -581,7 +686,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg) + unsigned long arg) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = -ENOTTY; @@ -663,7 +768,8 @@ void stm32_wwdginitialize(const char *devpath) * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, WWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_WWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -674,11 +780,22 @@ void stm32_wwdginitialize(const char *devpath) * on DBG_WWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_WWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt index a725dcc6f908b..f36e41d25df01 100644 --- a/arch/arm/src/stm32/CMakeLists.txt +++ b/arch/arm/src/stm32/CMakeLists.txt @@ -30,32 +30,8 @@ list( stm32_rcc.c stm32_lse.c stm32_lsi.c - stm32_gpio.c - stm32_exti_gpio.c - stm32_flash.c stm32_irq.c - stm32_lowputc.c - stm32_spi.c - stm32_i2s.c - stm32_sdio.c - stm32_tim.c - stm32_waste.c - stm32_ccm.c - stm32_uid.c - stm32_capture.c - stm32_dfumode.c) - -if(CONFIG_STM32_USART) - list(APPEND SRCS stm32_serial.c) -endif() - -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() + stm32_lowputc.c) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) @@ -63,64 +39,10 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() -if(CONFIG_STM32_HAVE_IP_I2C_V1) - if(CONFIG_STM32_I2C_ALT) - list(APPEND SRCS stm32_i2c_alt.c) - elseif(CONFIG_STM32_STM32F4XXX) - list(APPEND SRCS stm32f40xxx_i2c.c) - else() - list(APPEND SRCS stm32_i2c.c) - endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_V2) - list(APPEND SRCS stm32_i2c_v2.c) - if(CONFIG_STM32_I2C_SLAVE) - list(APPEND SRCS stm32_i2cslave_v2.c) - endif() -endif() - -if(CONFIG_USBDEV) - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() - if(CONFIG_STM32_USBFS) - list(APPEND SRCS stm32_usbfs.c) - endif() - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfsdev.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghsdev.c) - endif() -endif() - -if(CONFIG_STM32_USBHOST) - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfshost.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghshost.c) - endif() - if(CONFIG_USBHOST_TRACE) - list(APPEND SRCS stm32_usbhost.c) - else() - if(CONFIG_DEBUG_USB) - list(APPEND SRCS stm32_usbhost.c) - endif() - endif() -endif() - if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() @@ -131,149 +53,5 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT) list(APPEND SRCS stm32_pminitialize.c) endif() -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_eth.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) -endif() - -if(CONFIG_STM32_RTC) - list(APPEND SRCS stm32_rtc.c) - if(CONFIG_RTC_ALARM) - list(APPEND SRCS stm32_exti_alarm.c) - endif() - if(CONFIG_RTC_PERIODIC) - list(APPEND SRCS stm32_exti_wakeup.c) - endif() - if(CONFIG_RTC_DRIVER) - list(APPEND SRCS stm32_rtc_lowerhalf.c) - endif() -endif() - -if(CONFIG_STM32_SDADC) - list(APPEND SRCS stm32_sdadc.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire.c) -endif() - -if(CONFIG_STM32_HCIUART) - list(APPEND SRCS stm32_hciuart.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_ltdc.c) -endif() - -if(CONFIG_STM32_DMA2D) - list(APPEND SRCS stm32_dma2d.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_CAP) - list(APPEND SRCS stm32_capture_lowerhalf.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) - endif() -endif() - -if(CONFIG_SENSORS_HALL3PHASE) - list(APPEND SRCS stm32_hall3ph.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_can_sock.c) - endif() -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_DEBUG_FEATURES) - list(APPEND SRCS stm32_dumpgpio.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - list(APPEND SRCS stm32_crypto.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_fmc.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_fsmc.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 32c30a76ee74e..a7cf6decf4ba2 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -23,23 +23,7 @@ include armv7-m/Make.defs CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c -CHIP_CSRCS += stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_spi.c stm32_i2s.c stm32_sdio.c stm32_tim.c -CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c -CHIP_CSRCS += stm32_dfumode.c - -ifeq ($(CONFIG_STM32_USART),y) -CHIP_CSRCS += stm32_serial.c -endif - -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif +CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c ifdef CONFIG_STM32_TICKLESS_TIMER CHIP_CSRCS += stm32_tickless.c @@ -47,64 +31,10 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y) -ifeq ($(CONFIG_STM32_I2C_ALT),y) -CHIP_CSRCS += stm32_i2c_alt.c -else ifeq ($(CONFIG_STM32_STM32F4XXX),y) -CHIP_CSRCS += stm32f40xxx_i2c.c -else -CHIP_CSRCS += stm32_i2c.c -endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y) -CHIP_CSRCS += stm32_i2c_v2.c -ifeq ($(CONFIG_STM32_I2C_SLAVE),y) -CHIP_CSRCS += stm32_i2cslave_v2.c -endif -endif - -ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif -ifeq ($(CONFIG_STM32_USBFS),y) -CHIP_CSRCS += stm32_usbfs.c -endif -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfsdev.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghsdev.c -endif -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfshost.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghshost.c -endif -ifeq ($(CONFIG_USBHOST_TRACE),y) -CHIP_CSRCS += stm32_usbhost.c -else -ifeq ($(CONFIG_DEBUG_USB),y) -CHIP_CSRCS += stm32_usbhost.c -endif -endif -endif - ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif @@ -115,147 +45,4 @@ ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CHIP_CSRCS += stm32_pminitialize.c endif -ifeq ($(CONFIG_STM32_ETHMAC),y) -CHIP_CSRCS += stm32_eth.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c -endif - -ifeq ($(CONFIG_STM32_RTC),y) -CHIP_CSRCS += stm32_rtc.c -ifeq ($(CONFIG_RTC_ALARM),y) -CHIP_CSRCS += stm32_exti_alarm.c -endif -ifeq ($(CONFIG_RTC_PERIODIC),y) -CHIP_CSRCS += stm32_exti_wakeup.c -endif -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += stm32_rtc_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDADC),y) -CHIP_CSRCS += stm32_sdadc.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CHIP_CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CHIP_CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_OPAMP),y) -CHIP_CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CHIP_CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -CHIP_CSRCS += stm32_hciuart.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_LTDC),y) -CHIP_CSRCS += stm32_ltdc.c -endif - -ifeq ($(CONFIG_STM32_DMA2D),y) -CHIP_CSRCS += stm32_dma2d.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - -ifeq ($(CONFIG_STM32_CAP),y) -CHIP_CSRCS += stm32_capture_lowerhalf.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - ifeq ($(CONFIG_STM32_QE),y) - CHIP_CSRCS += stm32_qencoder.c - endif -endif - -ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) -CHIP_CSRCS += stm32_hall3ph.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CHIP_CSRCS += stm32_can_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_DEBUG_FEATURES),y) -CHIP_CSRCS += stm32_dumpgpio.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) -CHIP_CSRCS += stm32_crypto.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CHIP_CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CHIP_CSRCS += stm32_fmc.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CHIP_CSRCS += stm32_fsmc.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CHIP_CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_CORDIC),y) -CHIP_CSRCS += stm32_cordic.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h index 2d4432ca128ff..d1ba76649c384 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v1.h @@ -54,7 +54,7 @@ * - ... */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) # define HAVE_BASIC_ADC #else # undef HAVE_BASIC_ADC diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h index 09a83fa13bf4a..6e62bb59a7418 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h @@ -57,7 +57,7 @@ * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC # define HAVE_BASIC_ADC # error TODO #else diff --git a/arch/arm/src/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/stm32/hardware/stm32_dac_v1.h index 74742ac2781c6..669c27af662a2 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_dac_v1.h @@ -38,8 +38,8 @@ /* This is implementation for STM32 DAC IPv1 - F1, F2, F3, F4, F7, L1, L4 */ -#define HAVE_IP_DAC_V1 -#undef HAVE_IP_DAC_V2 /* No DAC IPv2 */ +#define HAVE_IP_DAC_M3M4_V1 +#undef HAVE_IP_DAC_M3M4_V2 /* No DAC IPv2 */ /* Register Offsets *********************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/stm32/hardware/stm32_dma.h index a34478f90294c..d1caacc4ea678 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ b/arch/arm/src/stm32/hardware/stm32_dma.h @@ -41,9 +41,12 @@ # error Only one STM32 DMA IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) # include "stm32_dma_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) # include "stm32_dma_v2.h" #else # error "STM32 DMA IP version not specified" diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h deleted file mode 100644 index 7e35c3b9b755c..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_pinmap.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* STM32L EnergyLite Line ***************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) - -/* STM32L15xx family */ - -# if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_pinmap.h" -# else -# error "Unsupported EnergyLite chip" -# endif - -/* STM32 F1 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F10XX) - -/* STM32F100 Value Line */ - -# if defined(CONFIG_STM32_VALUELINE) -# include "hardware/stm32f100_pinmap.h" - -/* STM32 F102 USB Access Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# include "hardware/stm32f102_pinmap.h" - -/* STM32 F103 Low / Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ - defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ - defined(CONFIG_ARCH_CHIP_STM32F103CB) -# include "hardware/stm32f103c_pinmap.h" - -/* STM32 F103 High Density Family */ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RG) -# include "hardware/stm32f103r_pinmap.h" - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# include "hardware/stm32f103v_pinmap.h" - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# include "hardware/stm32f103z_pinmap.h" - -/* STM32 F105/F107 Connectivity Line */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# include "hardware/stm32f105v_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# include "hardware/stm32f105r_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include "hardware/stm32f107v_pinmap.h" -# else -# error "Unsupported STM32F10XXX chip" -# endif - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_pinmap.h" - -/* STM32 F3 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_pinmap.h" - -/* STM32 F412 Family ********************************************************/ - -#elif defined(CONFIG_STM32_STM32F412) -# include "hardware/stm32f412xx_pinmap.h" - -/* STM32 F4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_pinmap.h" - -/* STM32 G4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_pinmap.h" - -#else -# error "No pinmap file for this STM32 chip" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index bc1408b48474a..bf1cfaf5f755c 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -42,10 +42,10 @@ * - 4-bit SMS in SMCR register */ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) -# define HAVE_IP_TIMERS_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) -# define HAVE_IP_TIMERS_V1 +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) +# define HAVE_IP_TIMERS_M3M4_V2 +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) +# define HAVE_IP_TIMERS_M3M4_V1 #else # error #endif @@ -138,7 +138,7 @@ /* Note that many of the above registers are 32-bits wide on the F3 */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ # define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ # define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (32-bit) */ @@ -169,7 +169,7 @@ # define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) # define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) # define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) # define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) @@ -197,7 +197,7 @@ # define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) # define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) # define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) # define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) # define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) @@ -485,7 +485,7 @@ # define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ # define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ # define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ #endif @@ -512,7 +512,7 @@ #define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ #define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ #define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ # define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ # define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ @@ -547,7 +547,7 @@ # define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ # define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ # define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ #endif #define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ @@ -587,7 +587,7 @@ # define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ #define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ #define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ #endif @@ -619,14 +619,14 @@ #define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ #define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ #define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ #endif #define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ #define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ #define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ #define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ # define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ #endif @@ -641,7 +641,7 @@ #define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ #define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ #define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ #endif @@ -665,7 +665,7 @@ #define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) /* (See common (unshifted) bit field definitions below) */ #define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ # define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ #endif @@ -758,7 +758,7 @@ #define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) /* (See common (unshifted) bit field definitions above) */ #define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ # define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ #endif @@ -785,7 +785,7 @@ /* Capture/compare mode register 3 -- Output compare mode */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ # define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ # define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ @@ -822,7 +822,7 @@ * NOTE: Some ST documents show CC4NP bit but there is * no CC4N output, so it does not make sense! */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ # define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ # define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ @@ -834,13 +834,13 @@ #define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ #define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ #endif /* Repetition counter register */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ # define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) # define ATIM_RCR_REP_MAX 32768 /* REVISIT */ @@ -852,7 +852,7 @@ /* Capture/compare registers (CCR) */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ # define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ # define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ @@ -876,7 +876,7 @@ #define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ #define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ #define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ # define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT) # define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ @@ -944,7 +944,7 @@ # define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ # define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ # define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ #endif @@ -1017,7 +1017,7 @@ # define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ #define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ #define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ #endif @@ -1087,7 +1087,7 @@ #define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) /* (See common CCMR Output Compare Mode definitions below) */ #define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ # define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ #endif @@ -1230,7 +1230,7 @@ #define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ #define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#ifdef HAVE_IP_TIMERS_V2 +#ifdef HAVE_IP_TIMERS_M3M4_V2 # define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ #endif diff --git a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h index 0b412885c978d..5a1a52ca69e48 100644 --- a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h +++ b/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h @@ -36,8 +36,8 @@ /* Configuration ************************************************************/ -#define HAVE_IP_DAC_V2 -#undef HAVE_IP_DAC_V1 /* No DAC IPv1 */ +#define HAVE_IP_DAC_M3M4_V2 +#undef HAVE_IP_DAC_M3M4_V1 /* No DAC IPv1 */ /* Register Offsets *********************************************************/ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c deleted file mode 100644 index 2f25d07a5a37d..0000000000000 --- a/arch/arm/src/stm32/stm32_comp.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_comp.h" -#include "stm32_gpio.h" - -/* This file is only a thin shell that includes the correct COMP - * implementation. At this moment STM32 COMP IP versions 1 and 2 are - * supported. - * - STM32 COMP IP version 1: SMT32F33XX - * - STM32 COMP IP version 2: SMT32G4XXX - */ - -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) -# include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) -# include "stm32_comp_v2.c" -#else -# error "STM32 COMP IP version not supported." -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h deleted file mode 100644 index 3b748b01a9eff..0000000000000 --- a/arch/arm/src/stm32/stm32_comp_v2.h +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Inverting input. See Table 196 in RM0440 */ - -enum stm32_comp_inm_e -{ - COMP_INM_1_4_VREF, - COMP_INM_1_2_VREF, - COMP_INM_3_4_VREF, - COMP_INM_VREF, - COMP_INM_DAC_1, - COMP_INM_DAC_2, - COMP_INM_PIN_1, - COMP_INM_PIN_2, -}; - -/* Non-inverting input. See Table 195 in RM0440 */ - -enum stm32_comp_inp_e -{ - COMP_INP_PIN_1, - COMP_INP_PIN_2, -}; - -/* Output polarity */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_10MV, - COMP_HYST_20MV, - COMP_HYST_30MV, - COMP_HYST_40MV, - COMP_HYST_50MV, - COMP_HYST_60MV, - COMP_HYST_70MV, -}; - -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, - COMP_BLANKING_TIMX_OCY_1, - COMP_BLANKING_TIMX_OCY_2, - COMP_BLANKING_TIMX_OCY_3, - COMP_BLANKING_TIMX_OCY_4, - COMP_BLANKING_TIMX_OCY_5, - COMP_BLANKING_TIMX_OCY_6, - COMP_BLANKING_TIMX_OCY_7, -}; - -#endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */ diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h deleted file mode 100644 index 6a67d7b2ce6a7..0000000000000 --- a/arch/arm/src/stm32/stm32_flash.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_flash.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int stm32_flash_lock(void); -int stm32_flash_unlock(void); - -/**************************************************************************** - * Name: stm32_flash_user_optbytes - * - * Description: - * Modify the contents of the user option bytes (USR OPT) on the flash. - * This does not set OBL_LAUNCH so new options take effect only after - * next power reset. - * - * Input Parameters: - * clrbits - Bits in the option bytes to be cleared - * setbits - Bits in the option bytes to be set - * - * Returned Value: - * Option bytes after operation is completed - * - ****************************************************************************/ - -uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); - -/**************************************************************************** - * Name: stm32_eeprom_size - * - * Description: - * Get EEPROM data memory size - * - * Returned Value: - * Length of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_size(void); - -/**************************************************************************** - * Name: stm32_eeprom_getaddress - * - * Description: - * Get EEPROM data memory address - * - * Returned Value: - * Address of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_getaddress(void); - -/**************************************************************************** - * Name: stm32_eeprom_write - * - * Description: - * Write buffer to EEPROM data memory address - * - * Returned Value: - * Number of written bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); - -/**************************************************************************** - * Name: stm32_eeprom_erase - * - * Description: - * Erase memory on EEPROM data memory address - * - * Returned Value: - * Number of erased bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h deleted file mode 100644 index 4dbaadeee3c5e..0000000000000 --- a/arch/arm/src/stm32/stm32_freerun.h +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32_STM32_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.h b/arch/arm/src/stm32/stm32_hciuart.h deleted file mode 100644 index ccbc7af5f4d8d..0000000000000 --- a/arch/arm/src/stm32/stm32_hciuart.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_HCIUART_H -#define __ARCH_ARM_SRC_STM32_STM32_HCIUART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum hciuart_devno_e -{ - HCIUART1 = 0, /* HCI UART on STM32 USART1 */ - HCIUART2 = 1, /* HCI UART on STM32 USART2 */ - HCIUART3 = 2, /* HCI UART on STM32 USART3 */ - /* UARTs 4-5 do not support RTS/CTS flow control */ - HCIUART5 = 5, /* HCI UART on STM32 USART6 */ - HCIUART6 = 6, /* HCI UART on STM32 UART7 */ - HCIUART7 = 7 /* HCI UART on STM32 UART8 */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_instantiate - * - * Description: - * Obtain an instance of the HCI UART interface for the specified HCI UART - * This assumes that hciuart_initialize was called previously. - * - * Input Parameters: - * uart - Identifies the HCI UART to be configured - * - * Returned Value: - * On success, a reference to the HCI UART lower driver for the associated - * U[S]ART - * - ****************************************************************************/ - -const struct btuart_lowerhalf_s * -hciuart_instantiate(enum hciuart_devno_e uart); - -/**************************************************************************** - * Name: hciuart_initialize - * - * Description: - * Performs the low-level, one-time USART initialization. This must be - * called before hciuart_instantiate. - * - ****************************************************************************/ - -void hciuart_initialize(void); - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h deleted file mode 100644 index 913321fa60ea2..0000000000000 --- a/arch/arm/src/stm32/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c deleted file mode 100644 index 7d191c9882517..0000000000000 --- a/arch/arm/src/stm32/stm32_rtc.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct RTC - * implementation for the selected STM32 family. The correct file cannot be - * selected by the make system because it needs the intelligence that only - * exists in chip.h that can associate an STM32 part number with an STM32 - * family. - */ - -/* The STM32 F1 has a simple battery-backed counter for its RTC and has a - * separate block for the BKP registers. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# include "stm32_rtcounter.c" - -/* The other families use a more traditional Realtime Clock/Calendar (RTCC) - * with broken-out data/time in BCD format. The backup registers are - * integrated into the RTCC in these families. - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) -# include "stm32_rtcc.c" -#elif defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rtcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rtcc.c" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_uid.h b/arch/arm/src/stm32/stm32_uid.h deleted file mode 100644 index d820fcee8c6e1..0000000000000 --- a/arch/arm/src/stm32/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_UID_H -#define __ARCH_ARM_SRC_STM32_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_UID_H */ diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h deleted file mode 100644 index 350bbb234d30b..0000000000000 --- a/arch/arm/src/stm32/stm32_usbdev.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbdev.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (8) - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable); - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h deleted file mode 100644 index 0ad2d4eb362c7..0000000000000 --- a/arch/arm/src/stm32/stm32_wdg.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_wdg.h" - -#ifdef CONFIG_WATCHDOG - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog time. The watchdog timer is initialized - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); -#endif - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initializeed - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG -void stm32_wwdginitialize(const char *devpath); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt index 44b85031e93e5..7eca474eaf9ac 100644 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ b/arch/arm/src/stm32f0l0g0/CMakeLists.txt @@ -26,23 +26,15 @@ list( APPEND SRCS stm32_start.c - stm32_gpio.c - stm32_exti_gpio.c stm32_irq.c stm32_lowputc.c - stm32_serial.c stm32_lsi.c - stm32_rcc.c - stm32_uid.c) + stm32_rcc.c) if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() @@ -59,77 +51,5 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c) endif() -if(CONFIG_STM32_PROGMEM) - list(APPEND SRCS stm32_flash.c) -endif() - -if(CONFIG_STM32_GPIOIRQ) - list(APPEND SRCS stm32_gpioint.c) -endif() - -if(CONFIG_ARCH_IRQPRIO) - list(APPEND SRCS stm32_irqprio.c) -endif() - -if(CONFIG_STM32_HAVE_HSI48) - list(APPEND SRCS stm32_hsi48.c) -endif() - -if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_STM32_I2C) - list(APPEND SRCS stm32_i2c.c) -endif() - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index 8ff7580bde293..9b02c48921085 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -22,17 +22,13 @@ include armv6-m/Make.defs -CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c -CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c +CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c +CHIP_CSRCS += stm32_rcc.c stm32_lsi.c ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -49,73 +45,4 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32_PROGMEM),y) -CHIP_CSRCS += stm32_flash.c -endif - -ifeq ($(CONFIG_STM32_GPIOIRQ),y) -CHIP_CSRCS += stm32_gpioint.c -endif - -ifeq ($(CONFIG_STM32_HAVE_HSI48),y) -CHIP_CSRCS += stm32_hsi48.c -endif - -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_STM32_I2C),y) -CHIP_CSRCS += stm32_i2c.c -endif - -ifeq ($(CONFIG_STM32_SPI),y) -CHIP_CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h deleted file mode 100644 index f6f07839c12f9..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32_STM32F05X) || \ - defined(CONFIG_STM32_STM32F07X) || \ - defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f05xf07xf09x_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_memorymap.h" -#else -# error "Unsupported STM32 M0 memory map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h deleted file mode 100644 index 3f1e617b3cb7a..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F05X) -# include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F07X) -# include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f09x_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_pinmap.h" -#else -# error "Unsupported STM32 M0 pin map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h index 1a03d8f4dcdbd..4c77ee8a1d1d7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h @@ -30,12 +30,17 @@ #include #include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_M0_V1) && \ + defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V1) # include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_M0_V1) && \ + defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V2) # include "hardware/stm32_uart_v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V2) +# error "Legacy STM32 USART must include a legacy family hardware header" #else -# error "Unsupported STM32 M0 USART" +# error "Unsupported STM32 F0/L0/G0/C0 USART" #endif #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h deleted file mode 100644 index f499aa8b95d41..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#include "hardware/stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h deleted file mode 100644 index ce5cb1a18af6e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ /dev/null @@ -1,327 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "hardware/stm32_dma_v1.h" - -#ifdef CONFIG_STM32_HAVE_DMAMUX -# include "hardware/stm32_dmamux.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions provide the bit encoding of the 'status' parameter - * passed to the DMA callback function (see dma_callback_t). - */ - -#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ -#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ -#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ - -#define DMA_STATUS_ERROR (DMA_STATUS_TEIF) -#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* DMA_HANDLE provides an opaque reference that can be used to represent a - * DMA channel (F1) or a DMA stream (F4). - */ - -typedef void *DMA_HANDLE; - -/* Description: - * This is the type of the callback that is used to inform the user of the - * completion of the DMA. - * - * Input Parameters: - * handle - Refers to the DMA channel or stream - * status - A bit encoded value that provides the completion status. See - * the DMASTATUS_* definitions above. - * arg - A user-provided value that was provided when stm32_dmastart() - * was called. - */ - -typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); - -#ifdef CONFIG_DEBUG_DMA_INFO -struct stm32_dmaregs_s -{ - uint32_t isr; - uint32_t ccr; - uint32_t cndtr; - uint32_t cpar; - uint32_t cmar; -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chan' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chan' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chan); - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will - * re-assign the DMA channel to that thread and wake it up. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to - * the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can - * be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address with the given configuration. This depends on the internal - * connections in the ARM bus matrix of the processor. Note that this - * only applies to memory addresses, it will return false for any - * peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); -#else -# define stm32_dmacapable(maddr, count, ccr) (true) -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); -#else -# define stm32_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); -#else -# define stm32_dmadump(handle,regs,msg) -#endif - -/* High performance, zero latency DMA interrupts need some additional - * interfaces. - * - * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. - * It should be unified somehow. - */ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -void stm32_dma_intack(unsigned int chndx, uint32_t isr); -#elif defined(HAVE_IP_DMA_V2) -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); -#endif - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -uint32_t stm32_dma_intget(unsigned int chndx); -#elif defined(HAVE_IP_DMA_V2) -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); -#endif - -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h deleted file mode 100644 index 33156f0dece9e..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_exti.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, - bool event, xcpt_t func, - void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h deleted file mode 100644 index 83893b284efe0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fdcan.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - -/**************************************************************************** - * Name: stm32_fdcansockinitialize - * - * Description: - * Initialize the selected FDCAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h deleted file mode 100644 index 9d1d09b17a94b..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h deleted file mode 100644 index c46fbdf913574..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is - * defined then the CONFIG_STM32_TIMn_QE must also be defined to - * indicate that timer "n" is intended to be used for as a quadrature - * encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif - -/* Only timers 1-4 can be used as a quadrature encoder (timers with - * encoder mode support). - * TIM6, TIM7, TIM14-17 are basic/general purpose timers without encoder - * capability. - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM14_QE -#undef CONFIG_STM32_TIM15_QE -#undef CONFIG_STM32_TIM16_QE -#undef CONFIG_STM32_TIM17_QE - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio); -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h deleted file mode 100644 index dd99c76575a22..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct spi_dev_s; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * bus number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus); - -/**************************************************************************** - * Name: stm32_spi1/2/...select and stm32_spi1/2/...status - * - * Description: - * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, - * and stm32_spi1/2/...cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_board_initialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32_spi1/2/...cmddata() functions in your - * board-specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 5. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/...register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD driver when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H */ From 57ef256607fbae315e0912a621ac657ef505f55d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 19:47:22 +0200 Subject: [PATCH 26/52] !arch/stm32: unify STM32_QUADSPI into STM32_QSPI BREAKING CHANGE: CONFIG_STM32_QUADSPI is removed. Board configurations that selected CONFIG_STM32_QUADSPI must now use CONFIG_STM32_QSPI. The QUADSPI/QSPI IP block was enabled by two different Kconfig symbols depending on the family: STM32_QUADSPI (F7/H7) and STM32_QSPI (L4/WB/G4). Both select the same peripheral. Unify them under the single STM32_QSPI symbol and remove STM32_QUADSPI. The arch sources, RCC enables, build files and board configurations are updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig.qspi | 22 ++++++++----------- arch/arm/src/stm32f7/CMakeLists.txt | 2 +- arch/arm/src/stm32f7/Make.defs | 2 +- arch/arm/src/stm32f7/stm32_qspi.c | 2 +- arch/arm/src/stm32f7/stm32_qspi.h | 2 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 2 +- arch/arm/src/stm32h7/CMakeLists.txt | 2 +- arch/arm/src/stm32h7/Make.defs | 2 +- arch/arm/src/stm32h7/stm32_qspi.c | 2 +- arch/arm/src/stm32h7/stm32_qspi.h | 2 +- boards/arm/stm32f7/stm32f746g-disco/Kconfig | 2 +- .../configs/f7corecomp/defconfig | 2 +- .../configs/i2s/defconfig | 2 +- .../configs/projectlab/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../stm32f777zit6-meadow/src/stm32_boot.c | 4 ++-- .../configs/littlefs/defconfig | 2 +- .../linum-stm32h753bi/configs/nxffs/defconfig | 2 +- 20 files changed, 29 insertions(+), 33 deletions(-) diff --git a/arch/arm/src/common/stm32/Kconfig.qspi b/arch/arm/src/common/stm32/Kconfig.qspi index 4150915fe4735..81e31aceca319 100644 --- a/arch/arm/src/common/stm32/Kconfig.qspi +++ b/arch/arm/src/common/stm32/Kconfig.qspi @@ -113,24 +113,20 @@ config STM32_QSPI_DMAPRIORITY_LOW endchoice -config STM32_QUADSPI - bool "QuadSPI" - depends on STM32_COMMON_F7_H7 - config STM32_QSPI_FLASH_SIZE int "Size of attached serial flash, bytes" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + depends on STM32_QSPI || STM32_QSPI1 default 16777216 range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 ---help--- The STM32F7 QSPI peripheral requires the size of the Flash be specified config STM32_QSPI_FIFO_THESHOLD int "Number of bytes before asserting FIFO threshold flag" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + depends on STM32_QSPI || STM32_QSPI1 default 4 - range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 16 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 ---help--- The STM32F7 QSPI peripheral requires that the FIFO threshold be specified @@ -138,10 +134,10 @@ config STM32_QSPI_FIFO_THESHOLD config STM32_QSPI_CSHT int "Number of cycles Chip Select must be inactive between transactions" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + depends on STM32_QSPI || STM32_QSPI1 default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 default 1 - range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 8 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 ---help--- The STM32F7 QSPI peripheral requires that it be specified the minimum number @@ -149,7 +145,7 @@ config STM32_QSPI_CSHT config STM32_QSPI_DMATHRESHOLD int "QSPI DMA threshold" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA default 4 ---help--- When QSPI DMA is enabled, small DMA transfers will still be performed @@ -158,7 +154,7 @@ config STM32_QSPI_DMATHRESHOLD config STM32_QSPI_DMADEBUG bool "QSPI DMA transfer debug" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + depends on (STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA ---help--- Enable special debug instrumentation to analyze QSPI DMA data transfers. This logic is as non-invasive as possible: It samples DMA @@ -167,7 +163,7 @@ config STM32_QSPI_DMADEBUG config STM32_QSPI_REGDEBUG bool "QSPI Register level debug" - depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + depends on STM32_COMMON_F7_H7 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO ---help--- Output detailed register-level QSPI device debug information. Requires also CONFIG_DEBUG_SPI_INFO. diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index c352c7cf3a1e2..76b478bf67fcb 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -132,7 +132,7 @@ if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32_QUADSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 1afb883a71723..7136cf42a7006 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -130,7 +130,7 @@ ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32_QUADSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 0bbc0f9659943..e43268126c707 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index edeeea7157aaf..c10cb95d8bbb7 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 0042ed990e3dc..5911b6a713921 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -309,7 +309,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 2a2346e41c230..4da3ddffceb5f 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -311,7 +311,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 83f5630e0b8dc..95eb7e6a59260 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -319,7 +319,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index a0664d6adae66..b226502c0931c 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -113,7 +113,7 @@ if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32_QUADSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 21944591be786..e8fb7d38e3a13 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -111,7 +111,7 @@ ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32_QUADSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index f5c615e433b90..9de983152154c 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 0db4496ae660c..5d7fc92ab8a5e 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index 8db1185d95b9a..15c51d8a03e1d 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32_QUADSPI + select STM32_QSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 9da945aff6e96..5be0771023dcc 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -66,8 +66,8 @@ CONFIG_START_DAY=14 CONFIG_STM32_DMA1=y CONFIG_STM32_DMA2=y CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y CONFIG_STM32_QSPI_POLLING=y -CONFIG_STM32_QUADSPI=y CONFIG_STM32_SDMMC2=y CONFIG_STM32_SDMMC_DMA=y CONFIG_STM32_USART1=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index d49ba47815bcf..62cd75915ad6a 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -94,8 +94,8 @@ CONFIG_STM32_I2S2=y CONFIG_STM32_I2S2_MCK=y CONFIG_STM32_I2S2_TX=y CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y CONFIG_STM32_QSPI_POLLING=y -CONFIG_STM32_QUADSPI=y CONFIG_STM32_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index dd681d42bb6cc..70331b5896eb2 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -67,7 +67,7 @@ CONFIG_SPI=y CONFIG_START_DAY=14 CONFIG_STM32_I2C1=y CONFIG_STM32_OTGFS=y -CONFIG_STM32_QUADSPI=y +CONFIG_STM32_QSPI=y CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 58b13ee72e00f..e06beff8f4caa 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -56,7 +56,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 CONFIG_STM32_OTGFS=y -CONFIG_STM32_QUADSPI=y +CONFIG_STM32_QSPI=y CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index 6e1fa08f1e1fb..bbf5cd536c139 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32_QUADSPI +#ifdef CONFIG_STM32_QSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index 7b2e63c57f640..ed872fc7b3ba9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -59,8 +59,8 @@ CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y CONFIG_STM32_QSPI_INTERRUPTS=y -CONFIG_STM32_QUADSPI=y CONFIG_STM32_RTC=y CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index f358b89c9249a..b15a5f909aa49 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -53,8 +53,8 @@ CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y CONFIG_STM32_QSPI_INTERRUPTS=y -CONFIG_STM32_QUADSPI=y CONFIG_STM32_RTC=y CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y From a3748006cebc07d63bd3ccb060502d4cf46f1cb6 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 12:12:39 +0200 Subject: [PATCH 27/52] !boards/arm/stm32: move common board sources BREAKING CHANGE: Move the existing STM32 board common sources to boards/arm/common/stm32 and fold in the common STM32F0/L0/G0/C0 board helpers so split STM32 board families can share one source tree. Keep board-common discovery on the existing ../common path by replacing the old family common directories with links to the shared tree instead of adding STM32-specific fallback logic to global Make or CMake files. Signed-off-by: raiden00pl --- .../drivers/character/input/keypad.rst | 2 +- .../drivers/character/input/mpr121.rst | 2 +- .../drivers/character/input/sbutton.rst | 2 +- .../common => common/stm32}/CMakeLists.txt | 2 +- .../{stm32/common => common/stm32}/Kconfig | 0 .../{stm32/common => common/stm32}/Makefile | 2 +- .../stm32}/include/board_hall3ph.h | 8 +- .../stm32}/include/board_pwm.h | 8 +- .../stm32}/include/board_qencoder.h | 8 +- .../stm32}/include/board_sbutton.h | 8 +- .../stm32}/include/stm32_amg88xx.h | 8 +- .../stm32}/include/stm32_apa102.h | 8 +- .../stm32}/include/stm32_apds9960.h | 8 +- .../stm32}/include/stm32_bh1750.h | 8 +- .../stm32}/include/stm32_bmp180.h | 8 +- .../stm32}/include/stm32_bmp280.h | 8 +- .../stm32}/include/stm32_dhtxx.h | 8 +- .../stm32}/include/stm32_drv8266.h | 8 +- .../stm32}/include/stm32_ds1307.h | 8 +- .../stm32}/include/stm32_hcsr04.h | 8 +- .../stm32}/include/stm32_ihm07m1.h | 8 +- .../stm32}/include/stm32_ihm08m1.h | 8 +- .../stm32}/include/stm32_ihm16m1.h | 8 +- .../stm32}/include/stm32_ina219.h | 8 +- .../stm32}/include/stm32_kmatrix_gpio.h | 8 +- .../stm32}/include/stm32_kmatrix_i2c.h | 8 +- .../stm32}/include/stm32_l3gd20.h | 8 +- .../stm32}/include/stm32_lcd_backpack.h | 8 +- .../stm32}/include/stm32_lis3dsh.h | 8 +- .../stm32}/include/stm32_lm75.h | 8 +- .../stm32}/include/stm32_max31855.h | 8 +- .../stm32}/include/stm32_max6675.h | 8 +- .../stm32}/include/stm32_max7219_matrix.h | 8 +- .../stm32}/include/stm32_mfrc522.h | 8 +- .../stm32}/include/stm32_mlx90614.h | 8 +- .../stm32}/include/stm32_mpl115a.h | 8 +- .../stm32}/include/stm32_mpr121.h | 8 +- .../stm32}/include/stm32_ms5611.h | 6 +- .../stm32}/include/stm32_mt6816.h | 8 +- .../stm32}/include/stm32_nrf24l01.h | 8 +- .../stm32}/include/stm32_nunchuck.h | 8 +- .../stm32}/include/stm32_ssd1306.h | 8 +- .../stm32}/include/stm32_tone.h | 8 +- .../stm32}/include/stm32_veml6070.h | 8 +- .../stm32}/include/stm32_ws2812.h | 8 +- .../stm32}/include/stm32_xen1210.h | 8 +- .../stm32}/include/stm32_zerocross.h | 8 +- .../stm32}/src/CMakeLists.txt | 8 +- .../common => common/stm32}/src/Make.defs | 19 ++- .../stm32}/src/board_hall3ph.c | 2 +- .../common => common/stm32}/src/board_pwm.c | 16 +- .../stm32}/src/board_qencoder.c | 4 +- .../stm32}/src/stm32_amg88xx.c | 2 +- .../stm32}/src/stm32_apa102.c | 2 +- .../stm32}/src/stm32_apds9960.c | 2 +- .../stm32}/src/stm32_bh1750.c | 2 +- .../stm32}/src/stm32_bmp180.c | 2 +- .../stm32}/src/stm32_bmp280.c | 2 +- .../common => common/stm32}/src/stm32_dhtxx.c | 2 +- .../stm32}/src/stm32_drv8825.c | 2 +- .../stm32}/src/stm32_ds1307.c | 2 +- .../stm32}/src/stm32_hcsr04.c | 2 +- .../stm32}/src/stm32_ihm07m1.c | 2 +- .../stm32}/src/stm32_ihm08m1.c | 2 +- .../stm32}/src/stm32_ihm16m1.c | 2 +- .../stm32}/src/stm32_ina219.c | 2 +- .../stm32}/src/stm32_kmatrix_gpio.c | 2 +- .../stm32}/src/stm32_kmatrix_i2c.c | 2 +- .../stm32}/src/stm32_l3gd20.c | 2 +- .../stm32}/src/stm32_lcd_backpack.c | 2 +- .../stm32}/src/stm32_lis3dsh.c | 2 +- .../common => common/stm32}/src/stm32_lm75.c | 2 +- .../stm32}/src/stm32_max31855.c | 2 +- .../stm32}/src/stm32_max6675.c | 2 +- .../stm32}/src/stm32_max7219_matrix.c | 2 +- .../stm32}/src/stm32_mfrc522.c | 2 +- .../stm32}/src/stm32_mlx90614.c | 2 +- .../stm32}/src/stm32_mpl115a.c | 2 +- .../stm32}/src/stm32_mpr121.c | 2 +- .../stm32}/src/stm32_ms5611.c | 2 +- .../stm32}/src/stm32_mt6816.c | 2 +- .../stm32}/src/stm32_nrf24l01.c | 2 +- .../stm32}/src/stm32_nunchuck.c | 2 +- .../stm32}/src/stm32_sbutton.c | 2 +- .../stm32}/src/stm32_ssd1306.c | 8 +- .../common => common/stm32}/src/stm32_tone.c | 2 +- .../stm32}/src/stm32_veml6070.c | 2 +- .../stm32}/src/stm32_ws2812.c | 2 +- .../stm32}/src/stm32_xen1210.c | 2 +- .../stm32}/src/stm32_zerocross.c | 2 +- boards/arm/stm32/common | 1 + boards/arm/stm32/common/src/stm32_qencoder.c | 68 -------- boards/arm/stm32/common/src/stm32_ssd1306.c | 160 ------------------ boards/arm/stm32f0l0g0/common | 1 + boards/arm/stm32f0l0g0/common/CMakeLists.txt | 24 --- boards/arm/stm32f0l0g0/common/Kconfig | 5 - boards/arm/stm32f0l0g0/common/Makefile | 35 ---- .../common/include/board_qencoder.h | 63 ------- .../common/include/stm32_ssd1306.h | 82 --------- .../arm/stm32f0l0g0/common/src/CMakeLists.txt | 38 ----- boards/arm/stm32f0l0g0/common/src/Make.defs | 41 ----- 101 files changed, 242 insertions(+), 743 deletions(-) rename boards/arm/{stm32/common => common/stm32}/CMakeLists.txt (96%) rename boards/arm/{stm32/common => common/stm32}/Kconfig (100%) rename boards/arm/{stm32/common => common/stm32}/Makefile (97%) rename boards/arm/{stm32/common => common/stm32}/include/board_hall3ph.h (91%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/include/board_pwm.h (85%) rename boards/arm/{stm32/common => common/stm32}/include/board_qencoder.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/board_sbutton.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_amg88xx.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_apa102.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_apds9960.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bh1750.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bmp180.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bmp280.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_dhtxx.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_drv8266.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ds1307.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_hcsr04.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm07m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm08m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm16m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ina219.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_kmatrix_gpio.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_kmatrix_i2c.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_l3gd20.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lcd_backpack.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lis3dsh.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lm75.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max31855.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max6675.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max7219_matrix.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mfrc522.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mlx90614.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mpl115a.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mpr121.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ms5611.h (94%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mt6816.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_nrf24l01.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_nunchuck.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ssd1306.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_tone.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_veml6070.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ws2812.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_xen1210.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_zerocross.h (91%) rename boards/arm/{stm32/common => common/stm32}/src/CMakeLists.txt (95%) rename boards/arm/{stm32/common => common/stm32}/src/Make.defs (87%) rename boards/arm/{stm32/common => common/stm32}/src/board_hall3ph.c (98%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/board_pwm.c (93%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/board_qencoder.c (96%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_amg88xx.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_apa102.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_apds9960.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bh1750.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bmp180.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bmp280.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_dhtxx.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_drv8825.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ds1307.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_hcsr04.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm07m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm08m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm16m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ina219.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_kmatrix_gpio.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_kmatrix_i2c.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_l3gd20.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lcd_backpack.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lis3dsh.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lm75.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max31855.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max6675.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max7219_matrix.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mfrc522.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mlx90614.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mpl115a.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mpr121.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ms5611.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mt6816.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_nrf24l01.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_nunchuck.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_sbutton.c (99%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/stm32_ssd1306.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_tone.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_veml6070.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ws2812.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_xen1210.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_zerocross.c (99%) create mode 120000 boards/arm/stm32/common delete mode 100644 boards/arm/stm32/common/src/stm32_qencoder.c delete mode 100644 boards/arm/stm32/common/src/stm32_ssd1306.c create mode 120000 boards/arm/stm32f0l0g0/common delete mode 100644 boards/arm/stm32f0l0g0/common/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/common/Kconfig delete mode 100644 boards/arm/stm32f0l0g0/common/Makefile delete mode 100644 boards/arm/stm32f0l0g0/common/include/board_qencoder.h delete mode 100644 boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h delete mode 100644 boards/arm/stm32f0l0g0/common/src/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/common/src/Make.defs diff --git a/Documentation/components/drivers/character/input/keypad.rst b/Documentation/components/drivers/character/input/keypad.rst index 93d357bc7ac29..58425f4fd5e32 100644 --- a/Documentation/components/drivers/character/input/keypad.rst +++ b/Documentation/components/drivers/character/input/keypad.rst @@ -62,7 +62,7 @@ kbd-codec layer. ``board_kmatrix_initialize("/dev/keypad0")``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_kmatrix_gpio.c``: +is in ``boards/arm/common/stm32/src/stm32_kmatrix_gpio.c``: - Rows: ``BOARD_KMATRIX_ROW0..3`` (outputs) - Columns: ``BOARD_KMATRIX_COL0..2`` (inputs with pull-up) diff --git a/Documentation/components/drivers/character/input/mpr121.rst b/Documentation/components/drivers/character/input/mpr121.rst index 9a24b3158fbf4..c8ccae104208a 100644 --- a/Documentation/components/drivers/character/input/mpr121.rst +++ b/Documentation/components/drivers/character/input/mpr121.rst @@ -53,7 +53,7 @@ kbd-codec layer. ``board_mpr121_initialize(0, 1)`` for ``/dev/keymap0`` and ``i2c1``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_mpr121.c``: +is in ``boards/arm/common/stm32/src/stm32_mpr121.c``: - Keymap: 4x3 keypad layout - Registration: ``board_mpr121_initialize()`` calls diff --git a/Documentation/components/drivers/character/input/sbutton.rst b/Documentation/components/drivers/character/input/sbutton.rst index 3281db7fd4a51..ca118f95e7430 100644 --- a/Documentation/components/drivers/character/input/sbutton.rst +++ b/Documentation/components/drivers/character/input/sbutton.rst @@ -23,7 +23,7 @@ It uses a kind of "polymorphism" in C to allow the driver to get access to the functions responsible to attach and enable the interrupt and to get the status of the pin. See ``include/nuttx/input/sbutton.h`` -and ``boards/arm/stm32/common/src/stm32_sbutton.c`` to understand +and ``boards/arm/common/stm32/src/stm32_sbutton.c`` to understand better how it works. But basically the board file (config data) creates a struct when the first field (variable) is the config struct used the but SButton driver (``drivers/input/sbutton.c``). diff --git a/boards/arm/stm32/common/CMakeLists.txt b/boards/arm/common/stm32/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/common/CMakeLists.txt rename to boards/arm/common/stm32/CMakeLists.txt index 48a2ca9e109b2..1c54914f408d5 100644 --- a/boards/arm/stm32/common/CMakeLists.txt +++ b/boards/arm/common/stm32/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/common/CMakeLists.txt +# boards/arm/common/stm32/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/common/Kconfig b/boards/arm/common/stm32/Kconfig similarity index 100% rename from boards/arm/stm32/common/Kconfig rename to boards/arm/common/stm32/Kconfig diff --git a/boards/arm/stm32/common/Makefile b/boards/arm/common/stm32/Makefile similarity index 97% rename from boards/arm/stm32/common/Makefile rename to boards/arm/common/stm32/Makefile index c6b78fa6a476c..3ce135c107029 100644 --- a/boards/arm/stm32/common/Makefile +++ b/boards/arm/common/stm32/Makefile @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32/common/Makefile +# boards/arm/common/stm32/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/common/include/board_hall3ph.h b/boards/arm/common/stm32/include/board_hall3ph.h similarity index 91% rename from boards/arm/stm32/common/include/board_hall3ph.h rename to boards/arm/common/stm32/include/board_hall3ph.h index 3cd1f2d819a18..21ab10f8220db 100644 --- a/boards/arm/stm32/common/include/board_hall3ph.h +++ b/boards/arm/common/stm32/include/board_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_hall3ph.h + * boards/arm/common/stm32/include/board_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H /**************************************************************************** * Included Files @@ -66,4 +66,4 @@ int board_hall3ph_initialize(int devno, int pha, int phb, int phc); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/board_pwm.h b/boards/arm/common/stm32/include/board_pwm.h similarity index 85% rename from boards/arm/stm32f0l0g0/common/include/board_pwm.h rename to boards/arm/common/stm32/include/board_pwm.h index b86407e0aa590..2e67391573319 100644 --- a/boards/arm/stm32f0l0g0/common/include/board_pwm.h +++ b/boards/arm/common/stm32/include/board_pwm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_pwm.h + * boards/arm/common/stm32/include/board_pwm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H /**************************************************************************** * Included Files @@ -37,4 +37,4 @@ int stm32_pwm_setup(void); #endif -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H */ diff --git a/boards/arm/stm32/common/include/board_qencoder.h b/boards/arm/common/stm32/include/board_qencoder.h similarity index 91% rename from boards/arm/stm32/common/include/board_qencoder.h rename to boards/arm/common/stm32/include/board_qencoder.h index 5d6dbe191786c..241f64d4ad089 100644 --- a/boards/arm/stm32/common/include/board_qencoder.h +++ b/boards/arm/common/stm32/include/board_qencoder.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_qencoder.h + * boards/arm/common/stm32/include/board_qencoder.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_qencoder_initialize(int devno, int timerno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32/common/include/board_sbutton.h b/boards/arm/common/stm32/include/board_sbutton.h similarity index 92% rename from boards/arm/stm32/common/include/board_sbutton.h rename to boards/arm/common/stm32/include/board_sbutton.h index 0dd67c113980a..f123d0b4f5789 100644 --- a/boards/arm/stm32/common/include/board_sbutton.h +++ b/boards/arm/common/stm32/include/board_sbutton.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_sbutton.h + * boards/arm/common/stm32/include/board_sbutton.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_sbutton_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H */ diff --git a/boards/arm/stm32/common/include/stm32_amg88xx.h b/boards/arm/common/stm32/include/stm32_amg88xx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_amg88xx.h rename to boards/arm/common/stm32/include/stm32_amg88xx.h index c8cb6fb724f64..e11cee5e7e8b9 100644 --- a/boards/arm/stm32/common/include/stm32_amg88xx.h +++ b/boards/arm/common/stm32/include/stm32_amg88xx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_amg88xx.h + * boards/arm/common/stm32/include/stm32_amg88xx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_amg88xx_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H */ diff --git a/boards/arm/stm32/common/include/stm32_apa102.h b/boards/arm/common/stm32/include/stm32_apa102.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apa102.h rename to boards/arm/common/stm32/include/stm32_apa102.h index 241fb474b0714..ad36c2e60682a 100644 --- a/boards/arm/stm32/common/include/stm32_apa102.h +++ b/boards/arm/common/stm32/include/stm32_apa102.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apa102.h + * boards/arm/common/stm32/include/stm32_apa102.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_apa102_initialize(int devno, int spino); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H */ diff --git a/boards/arm/stm32/common/include/stm32_apds9960.h b/boards/arm/common/stm32/include/stm32_apds9960.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apds9960.h rename to boards/arm/common/stm32/include/stm32_apds9960.h index c38b3a5bdf897..c2fe29bae609f 100644 --- a/boards/arm/stm32/common/include/stm32_apds9960.h +++ b/boards/arm/common/stm32/include/stm32_apds9960.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apds9960.h + * boards/arm/common/stm32/include/stm32_apds9960.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_apds9960_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H */ diff --git a/boards/arm/stm32/common/include/stm32_bh1750.h b/boards/arm/common/stm32/include/stm32_bh1750.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bh1750.h rename to boards/arm/common/stm32/include/stm32_bh1750.h index b9de5a874ddb9..96be9db21f1c8 100644 --- a/boards/arm/stm32/common/include/stm32_bh1750.h +++ b/boards/arm/common/stm32/include/stm32_bh1750.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bh1750.h + * boards/arm/common/stm32/include/stm32_bh1750.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bh1750_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp180.h b/boards/arm/common/stm32/include/stm32_bmp180.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp180.h rename to boards/arm/common/stm32/include/stm32_bmp180.h index 0e963442c9bb3..6b7865c6e9ba4 100644 --- a/boards/arm/stm32/common/include/stm32_bmp180.h +++ b/boards/arm/common/stm32/include/stm32_bmp180.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp180.h + * boards/arm/common/stm32/include/stm32_bmp180.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp180_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp280.h b/boards/arm/common/stm32/include/stm32_bmp280.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp280.h rename to boards/arm/common/stm32/include/stm32_bmp280.h index cf558b6791f90..22b375eaaa5de 100644 --- a/boards/arm/stm32/common/include/stm32_bmp280.h +++ b/boards/arm/common/stm32/include/stm32_bmp280.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp280.h + * boards/arm/common/stm32/include/stm32_bmp280.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp280_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H */ diff --git a/boards/arm/stm32/common/include/stm32_dhtxx.h b/boards/arm/common/stm32/include/stm32_dhtxx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_dhtxx.h rename to boards/arm/common/stm32/include/stm32_dhtxx.h index 7c1b5d6a9f41b..5b971aa41ae3b 100644 --- a/boards/arm/stm32/common/include/stm32_dhtxx.h +++ b/boards/arm/common/stm32/include/stm32_dhtxx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_dhtxx.h + * boards/arm/common/stm32/include/stm32_dhtxx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_dhtxx_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H */ diff --git a/boards/arm/stm32/common/include/stm32_drv8266.h b/boards/arm/common/stm32/include/stm32_drv8266.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_drv8266.h rename to boards/arm/common/stm32/include/stm32_drv8266.h index f0252073074af..ec0dc22b10c08 100644 --- a/boards/arm/stm32/common/include/stm32_drv8266.h +++ b/boards/arm/common/stm32/include/stm32_drv8266.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_drv8266.h + * boards/arm/common/stm32/include/stm32_drv8266.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_drv8825_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H */ diff --git a/boards/arm/stm32/common/include/stm32_ds1307.h b/boards/arm/common/stm32/include/stm32_ds1307.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ds1307.h rename to boards/arm/common/stm32/include/stm32_ds1307.h index 6baf58c63c4db..2e39c16ffba10 100644 --- a/boards/arm/stm32/common/include/stm32_ds1307.h +++ b/boards/arm/common/stm32/include/stm32_ds1307.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ds1307.h + * boards/arm/common/stm32/include/stm32_ds1307.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_ds1307_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H */ diff --git a/boards/arm/stm32/common/include/stm32_hcsr04.h b/boards/arm/common/stm32/include/stm32_hcsr04.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_hcsr04.h rename to boards/arm/common/stm32/include/stm32_hcsr04.h index d58e0e503564a..59ab41da73b89 100644 --- a/boards/arm/stm32/common/include/stm32_hcsr04.h +++ b/boards/arm/common/stm32/include/stm32_hcsr04.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_hcsr04.h + * boards/arm/common/stm32/include/stm32_hcsr04.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_hcsr04_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm07m1.h b/boards/arm/common/stm32/include/stm32_ihm07m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm07m1.h rename to boards/arm/common/stm32/include/stm32_ihm07m1.h index 6de00e3ec97e3..32c5601bc73c3 100644 --- a/boards/arm/stm32/common/include/stm32_ihm07m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm07m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm07m1.h + * boards/arm/common/stm32/include/stm32_ihm07m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm07m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm08m1.h b/boards/arm/common/stm32/include/stm32_ihm08m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm08m1.h rename to boards/arm/common/stm32/include/stm32_ihm08m1.h index 3f9738eadb3e1..eaee68a8875a4 100644 --- a/boards/arm/stm32/common/include/stm32_ihm08m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm08m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm08m1.h + * boards/arm/common/stm32/include/stm32_ihm08m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm08m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm16m1.h b/boards/arm/common/stm32/include/stm32_ihm16m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm16m1.h rename to boards/arm/common/stm32/include/stm32_ihm16m1.h index 442dc3bb3863f..76ff0c49b8e51 100644 --- a/boards/arm/stm32/common/include/stm32_ihm16m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm16m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm16m1.h + * boards/arm/common/stm32/include/stm32_ihm16m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm16m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ina219.h b/boards/arm/common/stm32/include/stm32_ina219.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ina219.h rename to boards/arm/common/stm32/include/stm32_ina219.h index 4fa91899c3d09..20b5a1e4656d8 100644 --- a/boards/arm/stm32/common/include/stm32_ina219.h +++ b/boards/arm/common/stm32/include/stm32_ina219.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ina219.h + * boards/arm/common/stm32/include/stm32_ina219.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_ina219_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_gpio.h rename to boards/arm/common/stm32/include/stm32_kmatrix_gpio.h index 6615fcc9b36fe..bfad9923c9a39 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_gpio.h + * boards/arm/common/stm32/include/stm32_kmatrix_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_i2c.h rename to boards/arm/common/stm32/include/stm32_kmatrix_i2c.h index 82669a943dbc4..51f6295e5ec2a 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_i2c.h + * boards/arm/common/stm32/include/stm32_kmatrix_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_i2c_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H */ diff --git a/boards/arm/stm32/common/include/stm32_l3gd20.h b/boards/arm/common/stm32/include/stm32_l3gd20.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_l3gd20.h rename to boards/arm/common/stm32/include/stm32_l3gd20.h index 8400e1193456d..edd5c6ca3b5e2 100644 --- a/boards/arm/stm32/common/include/stm32_l3gd20.h +++ b/boards/arm/common/stm32/include/stm32_l3gd20.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_l3gd20.h + * boards/arm/common/stm32/include/stm32_l3gd20.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_l3gd20_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H */ diff --git a/boards/arm/stm32/common/include/stm32_lcd_backpack.h b/boards/arm/common/stm32/include/stm32_lcd_backpack.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lcd_backpack.h rename to boards/arm/common/stm32/include/stm32_lcd_backpack.h index f0923df0c2a2a..731e0ed039f66 100644 --- a/boards/arm/stm32/common/include/stm32_lcd_backpack.h +++ b/boards/arm/common/stm32/include/stm32_lcd_backpack.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lcd_backpack.h + * boards/arm/common/stm32/include/stm32_lcd_backpack.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_lcd_backpack_init(int devno, int busno, int rows, int cols); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H */ diff --git a/boards/arm/stm32/common/include/stm32_lis3dsh.h b/boards/arm/common/stm32/include/stm32_lis3dsh.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lis3dsh.h rename to boards/arm/common/stm32/include/stm32_lis3dsh.h index 6c28d6e8b1c26..ea92bd41f5718 100644 --- a/boards/arm/stm32/common/include/stm32_lis3dsh.h +++ b/boards/arm/common/stm32/include/stm32_lis3dsh.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lis3dsh.h + * boards/arm/common/stm32/include/stm32_lis3dsh.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lis3dsh_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H */ diff --git a/boards/arm/stm32/common/include/stm32_lm75.h b/boards/arm/common/stm32/include/stm32_lm75.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lm75.h rename to boards/arm/common/stm32/include/stm32_lm75.h index 74e846e3a1391..339d91433d1f4 100644 --- a/boards/arm/stm32/common/include/stm32_lm75.h +++ b/boards/arm/common/stm32/include/stm32_lm75.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lm75.h + * boards/arm/common/stm32/include/stm32_lm75.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lm75_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H */ diff --git a/boards/arm/stm32/common/include/stm32_max31855.h b/boards/arm/common/stm32/include/stm32_max31855.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max31855.h rename to boards/arm/common/stm32/include/stm32_max31855.h index 36196eb6602be..243bd335ea9c1 100644 --- a/boards/arm/stm32/common/include/stm32_max31855.h +++ b/boards/arm/common/stm32/include/stm32_max31855.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max31855.h + * boards/arm/common/stm32/include/stm32_max31855.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_max31855_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H */ diff --git a/boards/arm/stm32/common/include/stm32_max6675.h b/boards/arm/common/stm32/include/stm32_max6675.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max6675.h rename to boards/arm/common/stm32/include/stm32_max6675.h index 01cdd85bc615c..6386116c9df62 100644 --- a/boards/arm/stm32/common/include/stm32_max6675.h +++ b/boards/arm/common/stm32/include/stm32_max6675.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max6675.h + * boards/arm/common/stm32/include/stm32_max6675.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_max6675_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H */ diff --git a/boards/arm/stm32/common/include/stm32_max7219_matrix.h b/boards/arm/common/stm32/include/stm32_max7219_matrix.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_max7219_matrix.h rename to boards/arm/common/stm32/include/stm32_max7219_matrix.h index a22addd854355..fea20cbaea3e2 100644 --- a/boards/arm/stm32/common/include/stm32_max7219_matrix.h +++ b/boards/arm/common/stm32/include/stm32_max7219_matrix.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max7219_matrix.h + * boards/arm/common/stm32/include/stm32_max7219_matrix.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_max7219_matrix_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H */ diff --git a/boards/arm/stm32/common/include/stm32_mfrc522.h b/boards/arm/common/stm32/include/stm32_mfrc522.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mfrc522.h rename to boards/arm/common/stm32/include/stm32_mfrc522.h index 6934ea3de6a6b..46a3956b264c0 100644 --- a/boards/arm/stm32/common/include/stm32_mfrc522.h +++ b/boards/arm/common/stm32/include/stm32_mfrc522.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mfrc522.h + * boards/arm/common/stm32/include/stm32_mfrc522.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int stm32_mfrc522initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H */ diff --git a/boards/arm/stm32/common/include/stm32_mlx90614.h b/boards/arm/common/stm32/include/stm32_mlx90614.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mlx90614.h rename to boards/arm/common/stm32/include/stm32_mlx90614.h index 3f6bd970d8f7a..5115ae35de705 100644 --- a/boards/arm/stm32/common/include/stm32_mlx90614.h +++ b/boards/arm/common/stm32/include/stm32_mlx90614.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mlx90614.h + * boards/arm/common/stm32/include/stm32_mlx90614.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mlx90614_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpl115a.h b/boards/arm/common/stm32/include/stm32_mpl115a.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpl115a.h rename to boards/arm/common/stm32/include/stm32_mpl115a.h index 88c3e3cc5a573..309d39481fda8 100644 --- a/boards/arm/stm32/common/include/stm32_mpl115a.h +++ b/boards/arm/common/stm32/include/stm32_mpl115a.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpl115a.h + * boards/arm/common/stm32/include/stm32_mpl115a.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpl115a_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpr121.h b/boards/arm/common/stm32/include/stm32_mpr121.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpr121.h rename to boards/arm/common/stm32/include/stm32_mpr121.h index 185f2aac544c2..a35b1c0247602 100644 --- a/boards/arm/stm32/common/include/stm32_mpr121.h +++ b/boards/arm/common/stm32/include/stm32_mpr121.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpr121.h + * boards/arm/common/stm32/include/stm32_mpr121.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpr121_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H */ diff --git a/boards/arm/stm32/common/include/stm32_ms5611.h b/boards/arm/common/stm32/include/stm32_ms5611.h similarity index 94% rename from boards/arm/stm32/common/include/stm32_ms5611.h rename to boards/arm/common/stm32/include/stm32_ms5611.h index f5a27d3394975..2e9c63e68b074 100644 --- a/boards/arm/stm32/common/include/stm32_ms5611.h +++ b/boards/arm/common/stm32/include/stm32_ms5611.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ms5611.h + * boards/arm/common/stm32/include/stm32_ms5611.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H /**************************************************************************** * Included Files diff --git a/boards/arm/stm32/common/include/stm32_mt6816.h b/boards/arm/common/stm32/include/stm32_mt6816.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_mt6816.h rename to boards/arm/common/stm32/include/stm32_mt6816.h index 2497d13aa9ad1..ff6447fded542 100644 --- a/boards/arm/stm32/common/include/stm32_mt6816.h +++ b/boards/arm/common/stm32/include/stm32_mt6816.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mt6816.h + * boards/arm/common/stm32/include/stm32_mt6816.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_mt6816_initialize(int devno, int spi_busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H */ diff --git a/boards/arm/stm32/common/include/stm32_nrf24l01.h b/boards/arm/common/stm32/include/stm32_nrf24l01.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_nrf24l01.h rename to boards/arm/common/stm32/include/stm32_nrf24l01.h index e5207c6d16d0f..8a676add6ba3d 100644 --- a/boards/arm/stm32/common/include/stm32_nrf24l01.h +++ b/boards/arm/common/stm32/include/stm32_nrf24l01.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nrf24l01.h + * boards/arm/common/stm32/include/stm32_nrf24l01.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_nrf24l01_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H */ diff --git a/boards/arm/stm32/common/include/stm32_nunchuck.h b/boards/arm/common/stm32/include/stm32_nunchuck.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_nunchuck.h rename to boards/arm/common/stm32/include/stm32_nunchuck.h index 138fab2feff3a..b08f8ee6b1776 100644 --- a/boards/arm/stm32/common/include/stm32_nunchuck.h +++ b/boards/arm/common/stm32/include/stm32_nunchuck.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nunchuck.h + * boards/arm/common/stm32/include/stm32_nunchuck.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_nunchuck_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H */ diff --git a/boards/arm/stm32/common/include/stm32_ssd1306.h b/boards/arm/common/stm32/include/stm32_ssd1306.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_ssd1306.h rename to boards/arm/common/stm32/include/stm32_ssd1306.h index d5e2d5279968b..a23b2d776ad28 100644 --- a/boards/arm/stm32/common/include/stm32_ssd1306.h +++ b/boards/arm/common/stm32/include/stm32_ssd1306.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ssd1306.h + * boards/arm/common/stm32/include/stm32_ssd1306.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ struct lcd_dev_s *board_ssd1306_getdev(void); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32/common/include/stm32_tone.h b/boards/arm/common/stm32/include/stm32_tone.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_tone.h rename to boards/arm/common/stm32/include/stm32_tone.h index 1834af76bab05..5306c10f30869 100644 --- a/boards/arm/stm32/common/include/stm32_tone.h +++ b/boards/arm/common/stm32/include/stm32_tone.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_tone.h + * boards/arm/common/stm32/include/stm32_tone.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H /**************************************************************************** * Included Files @@ -75,4 +75,4 @@ int board_tone_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H */ diff --git a/boards/arm/stm32/common/include/stm32_veml6070.h b/boards/arm/common/stm32/include/stm32_veml6070.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_veml6070.h rename to boards/arm/common/stm32/include/stm32_veml6070.h index 3b3a68999718f..ab73c1504ddf8 100644 --- a/boards/arm/stm32/common/include/stm32_veml6070.h +++ b/boards/arm/common/stm32/include/stm32_veml6070.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_veml6070.h + * boards/arm/common/stm32/include/stm32_veml6070.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_veml6070_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H */ diff --git a/boards/arm/stm32/common/include/stm32_ws2812.h b/boards/arm/common/stm32/include/stm32_ws2812.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ws2812.h rename to boards/arm/common/stm32/include/stm32_ws2812.h index ef6dfb8d8ab1a..76fa9b5724b6c 100644 --- a/boards/arm/stm32/common/include/stm32_ws2812.h +++ b/boards/arm/common/stm32/include/stm32_ws2812.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ws2812.h + * boards/arm/common/stm32/include/stm32_ws2812.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_ws2812_initialize(int devno, int spino, uint16_t nleds); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H */ diff --git a/boards/arm/stm32/common/include/stm32_xen1210.h b/boards/arm/common/stm32/include/stm32_xen1210.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_xen1210.h rename to boards/arm/common/stm32/include/stm32_xen1210.h index 19ed0c4246eab..a6b8e30955de7 100644 --- a/boards/arm/stm32/common/include/stm32_xen1210.h +++ b/boards/arm/common/stm32/include/stm32_xen1210.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_xen1210.h + * boards/arm/common/stm32/include/stm32_xen1210.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_xen1210_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H */ diff --git a/boards/arm/stm32/common/include/stm32_zerocross.h b/boards/arm/common/stm32/include/stm32_zerocross.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_zerocross.h rename to boards/arm/common/stm32/include/stm32_zerocross.h index ae07c6ddb5e76..2d92fd900be90 100644 --- a/boards/arm/stm32/common/include/stm32_zerocross.h +++ b/boards/arm/common/stm32/include/stm32_zerocross.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_zerocross.h + * boards/arm/common/stm32/include/stm32_zerocross.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_zerocross_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H */ diff --git a/boards/arm/stm32/common/src/CMakeLists.txt b/boards/arm/common/stm32/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/common/src/CMakeLists.txt rename to boards/arm/common/stm32/src/CMakeLists.txt index c7d9426af29e7..1f9b383736821 100644 --- a/boards/arm/stm32/common/src/CMakeLists.txt +++ b/boards/arm/common/stm32/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/common/src/CMakeLists.txt +# boards/arm/common/stm32/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -92,10 +92,14 @@ endif() if(CONFIG_SENSORS_QENCODER) if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) + list(APPEND SRCS board_qencoder.c) endif() endif() +if(CONFIG_PWM AND NOT EXISTS ${NUTTX_BOARD_DIR}/src/stm32_pwm.c) + list(APPEND SRCS board_pwm.c) +endif() + if(CONFIG_SENSORS_INA219) list(APPEND SRCS stm32_ina219.c) endif() diff --git a/boards/arm/stm32/common/src/Make.defs b/boards/arm/common/stm32/src/Make.defs similarity index 87% rename from boards/arm/stm32/common/src/Make.defs rename to boards/arm/common/stm32/src/Make.defs index 5b1f8556d767f..9470fe63aac34 100644 --- a/boards/arm/stm32/common/src/Make.defs +++ b/boards/arm/common/stm32/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32/common/src/Make.defs +# boards/arm/common/stm32/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,6 +22,8 @@ ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += stm32_bmp180.c endif @@ -100,7 +102,13 @@ endif ifeq ($(CONFIG_SENSORS_QENCODER),y) ifeq ($(CONFIG_STM32_QE),y) - CSRCS += stm32_qencoder.c + CSRCS += board_qencoder.c + endif +endif + +ifeq ($(CONFIG_PWM),y) + ifeq (,$(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)stm32_pwm.c)) + CSRCS += board_pwm.c endif endif @@ -184,8 +192,9 @@ ifeq ($(CONFIG_INPUT_KMATRIX_I2C),y) CSRCS += stm32_kmatrix_i2c.c endif -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src +DEPPATH += --dep-path $(STM32_BOARD_COMMON_DIR)$(DELIM)src +VPATH += :$(STM32_BOARD_COMMON_DIR)$(DELIM)src +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)src endif diff --git a/boards/arm/stm32/common/src/board_hall3ph.c b/boards/arm/common/stm32/src/board_hall3ph.c similarity index 98% rename from boards/arm/stm32/common/src/board_hall3ph.c rename to boards/arm/common/stm32/src/board_hall3ph.c index f96d5a953f3f1..3ce8efa7607cd 100644 --- a/boards/arm/stm32/common/src/board_hall3ph.c +++ b/boards/arm/common/stm32/src/board_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/board_hall3ph.c + * boards/arm/common/stm32/src/board_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/board_pwm.c b/boards/arm/common/stm32/src/board_pwm.c similarity index 93% rename from boards/arm/stm32f0l0g0/common/src/board_pwm.c rename to boards/arm/common/stm32/src/board_pwm.c index 793b0398537d8..fdc3ad58f4250 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_pwm.c +++ b/boards/arm/common/stm32/src/board_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_pwm.c + * boards/arm/common/stm32/src/board_pwm.c * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ int stm32_pwm_setup(void) if (!initialized) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM pwm = stm32_pwminitialize(1); if (pwm == NULL) { @@ -71,7 +71,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM pwm = stm32_pwminitialize(2); if (pwm == NULL) { @@ -87,7 +87,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM pwm = stm32_pwminitialize(3); if (pwm == NULL) { @@ -103,7 +103,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM pwm = stm32_pwminitialize(14); if (pwm == NULL) { @@ -119,7 +119,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM pwm = stm32_pwminitialize(15); if (pwm == NULL) { @@ -135,7 +135,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM pwm = stm32_pwminitialize(16); if (pwm == NULL) { @@ -151,7 +151,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM pwm = stm32_pwminitialize(17); if (pwm == NULL) { diff --git a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c b/boards/arm/common/stm32/src/board_qencoder.c similarity index 96% rename from boards/arm/stm32f0l0g0/common/src/board_qencoder.c rename to boards/arm/common/stm32/src/board_qencoder.c index 6f7e6260977a4..f67c7d857f44a 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c +++ b/boards/arm/common/stm32/src/board_qencoder.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_qencoder.c + * boards/arm/common/stm32/src/board_qencoder.c * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/common/src/stm32_amg88xx.c b/boards/arm/common/stm32/src/stm32_amg88xx.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_amg88xx.c rename to boards/arm/common/stm32/src/stm32_amg88xx.c index 4760fd947f17f..995a28e141253 100644 --- a/boards/arm/stm32/common/src/stm32_amg88xx.c +++ b/boards/arm/common/stm32/src/stm32_amg88xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_amg88xx.c + * boards/arm/common/stm32/src/stm32_amg88xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_apa102.c b/boards/arm/common/stm32/src/stm32_apa102.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_apa102.c rename to boards/arm/common/stm32/src/stm32_apa102.c index 5b19432385c66..5de33d0dc6bfc 100644 --- a/boards/arm/stm32/common/src/stm32_apa102.c +++ b/boards/arm/common/stm32/src/stm32_apa102.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_apa102.c + * boards/arm/common/stm32/src/stm32_apa102.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_apds9960.c b/boards/arm/common/stm32/src/stm32_apds9960.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_apds9960.c rename to boards/arm/common/stm32/src/stm32_apds9960.c index 902cac423d5ca..ff709d6949777 100644 --- a/boards/arm/stm32/common/src/stm32_apds9960.c +++ b/boards/arm/common/stm32/src/stm32_apds9960.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_apds9960.c + * boards/arm/common/stm32/src/stm32_apds9960.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bh1750.c b/boards/arm/common/stm32/src/stm32_bh1750.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bh1750.c rename to boards/arm/common/stm32/src/stm32_bh1750.c index 4a21eee85c3f6..d8f742f357b48 100644 --- a/boards/arm/stm32/common/src/stm32_bh1750.c +++ b/boards/arm/common/stm32/src/stm32_bh1750.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bh1750.c + * boards/arm/common/stm32/src/stm32_bh1750.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp180.c b/boards/arm/common/stm32/src/stm32_bmp180.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp180.c rename to boards/arm/common/stm32/src/stm32_bmp180.c index 35b6bf15a32c7..3301d4baf1bee 100644 --- a/boards/arm/stm32/common/src/stm32_bmp180.c +++ b/boards/arm/common/stm32/src/stm32_bmp180.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp180.c + * boards/arm/common/stm32/src/stm32_bmp180.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp280.c b/boards/arm/common/stm32/src/stm32_bmp280.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp280.c rename to boards/arm/common/stm32/src/stm32_bmp280.c index c42be6b3ec8cc..2d748ac1128de 100644 --- a/boards/arm/stm32/common/src/stm32_bmp280.c +++ b/boards/arm/common/stm32/src/stm32_bmp280.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp280.c + * boards/arm/common/stm32/src/stm32_bmp280.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_dhtxx.c b/boards/arm/common/stm32/src/stm32_dhtxx.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_dhtxx.c rename to boards/arm/common/stm32/src/stm32_dhtxx.c index 017f7de8f1456..24c82362750ec 100644 --- a/boards/arm/stm32/common/src/stm32_dhtxx.c +++ b/boards/arm/common/stm32/src/stm32_dhtxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_dhtxx.c + * boards/arm/common/stm32/src/stm32_dhtxx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_drv8825.c b/boards/arm/common/stm32/src/stm32_drv8825.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_drv8825.c rename to boards/arm/common/stm32/src/stm32_drv8825.c index e11b644d947df..60187a9eb9fe0 100644 --- a/boards/arm/stm32/common/src/stm32_drv8825.c +++ b/boards/arm/common/stm32/src/stm32_drv8825.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_drv8825.c + * boards/arm/common/stm32/src/stm32_drv8825.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ds1307.c b/boards/arm/common/stm32/src/stm32_ds1307.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ds1307.c rename to boards/arm/common/stm32/src/stm32_ds1307.c index 6d34e5255ca54..fb7cf4129b295 100644 --- a/boards/arm/stm32/common/src/stm32_ds1307.c +++ b/boards/arm/common/stm32/src/stm32_ds1307.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ds1307.c + * boards/arm/common/stm32/src/stm32_ds1307.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_hcsr04.c b/boards/arm/common/stm32/src/stm32_hcsr04.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_hcsr04.c rename to boards/arm/common/stm32/src/stm32_hcsr04.c index 7f8c235f0de6f..3f2d6ae229bbf 100644 --- a/boards/arm/stm32/common/src/stm32_hcsr04.c +++ b/boards/arm/common/stm32/src/stm32_hcsr04.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_hcsr04.c + * boards/arm/common/stm32/src/stm32_hcsr04.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm07m1.c b/boards/arm/common/stm32/src/stm32_ihm07m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm07m1.c rename to boards/arm/common/stm32/src/stm32_ihm07m1.c index 39e550affaa41..6fa02180e4183 100644 --- a/boards/arm/stm32/common/src/stm32_ihm07m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm07m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm07m1.c + * boards/arm/common/stm32/src/stm32_ihm07m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm08m1.c b/boards/arm/common/stm32/src/stm32_ihm08m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm08m1.c rename to boards/arm/common/stm32/src/stm32_ihm08m1.c index 97a12482b59a1..2c5b1b366a84b 100644 --- a/boards/arm/stm32/common/src/stm32_ihm08m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm08m1.c + * boards/arm/common/stm32/src/stm32_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm16m1.c b/boards/arm/common/stm32/src/stm32_ihm16m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm16m1.c rename to boards/arm/common/stm32/src/stm32_ihm16m1.c index d3d6ccb838e74..6bf525ca0b7f3 100644 --- a/boards/arm/stm32/common/src/stm32_ihm16m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm16m1.c + * boards/arm/common/stm32/src/stm32_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ina219.c b/boards/arm/common/stm32/src/stm32_ina219.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ina219.c rename to boards/arm/common/stm32/src/stm32_ina219.c index 98968b1adbc3a..20b1e565dadcc 100644 --- a/boards/arm/stm32/common/src/stm32_ina219.c +++ b/boards/arm/common/stm32/src/stm32_ina219.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ina219.c + * boards/arm/common/stm32/src/stm32_ina219.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2018 Erle Robotics (Juan Flores Muñoz). diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_gpio.c rename to boards/arm/common/stm32/src/stm32_kmatrix_gpio.c index d76d94fa0f3e2..7f5a68d0acd03 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_gpio.c + * boards/arm/common/stm32/src/stm32_kmatrix_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_i2c.c rename to boards/arm/common/stm32/src/stm32_kmatrix_i2c.c index 358c1d5584fe3..d4978eca0a56c 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_i2c.c + * boards/arm/common/stm32/src/stm32_kmatrix_i2c.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_l3gd20.c b/boards/arm/common/stm32/src/stm32_l3gd20.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_l3gd20.c rename to boards/arm/common/stm32/src/stm32_l3gd20.c index 5cbd5021d843c..145060bd52de8 100644 --- a/boards/arm/stm32/common/src/stm32_l3gd20.c +++ b/boards/arm/common/stm32/src/stm32_l3gd20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_l3gd20.c + * boards/arm/common/stm32/src/stm32_l3gd20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lcd_backpack.c b/boards/arm/common/stm32/src/stm32_lcd_backpack.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lcd_backpack.c rename to boards/arm/common/stm32/src/stm32_lcd_backpack.c index c288d2b4dd6e4..b65a3fcaaec19 100644 --- a/boards/arm/stm32/common/src/stm32_lcd_backpack.c +++ b/boards/arm/common/stm32/src/stm32_lcd_backpack.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lcd_backpack.c + * boards/arm/common/stm32/src/stm32_lcd_backpack.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lis3dsh.c b/boards/arm/common/stm32/src/stm32_lis3dsh.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lis3dsh.c rename to boards/arm/common/stm32/src/stm32_lis3dsh.c index 03d3fa84ad405..f1cfaa31ce388 100644 --- a/boards/arm/stm32/common/src/stm32_lis3dsh.c +++ b/boards/arm/common/stm32/src/stm32_lis3dsh.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lis3dsh.c + * boards/arm/common/stm32/src/stm32_lis3dsh.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lm75.c b/boards/arm/common/stm32/src/stm32_lm75.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lm75.c rename to boards/arm/common/stm32/src/stm32_lm75.c index ce7c9f796e65c..6f01942a00a78 100644 --- a/boards/arm/stm32/common/src/stm32_lm75.c +++ b/boards/arm/common/stm32/src/stm32_lm75.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lm75.c + * boards/arm/common/stm32/src/stm32_lm75.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max31855.c b/boards/arm/common/stm32/src/stm32_max31855.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max31855.c rename to boards/arm/common/stm32/src/stm32_max31855.c index b520888c5979f..ae21864b0951a 100644 --- a/boards/arm/stm32/common/src/stm32_max31855.c +++ b/boards/arm/common/stm32/src/stm32_max31855.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max31855.c + * boards/arm/common/stm32/src/stm32_max31855.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max6675.c b/boards/arm/common/stm32/src/stm32_max6675.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max6675.c rename to boards/arm/common/stm32/src/stm32_max6675.c index bd6b20d0e0f0f..4082eea356a9a 100644 --- a/boards/arm/stm32/common/src/stm32_max6675.c +++ b/boards/arm/common/stm32/src/stm32_max6675.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max6675.c + * boards/arm/common/stm32/src/stm32_max6675.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max7219_matrix.c b/boards/arm/common/stm32/src/stm32_max7219_matrix.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max7219_matrix.c rename to boards/arm/common/stm32/src/stm32_max7219_matrix.c index 4e5ac76473b5c..0ee46493a9c4c 100644 --- a/boards/arm/stm32/common/src/stm32_max7219_matrix.c +++ b/boards/arm/common/stm32/src/stm32_max7219_matrix.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max7219_matrix.c + * boards/arm/common/stm32/src/stm32_max7219_matrix.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mfrc522.c b/boards/arm/common/stm32/src/stm32_mfrc522.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mfrc522.c rename to boards/arm/common/stm32/src/stm32_mfrc522.c index fc0d5bdf40e0b..0da85237c697b 100644 --- a/boards/arm/stm32/common/src/stm32_mfrc522.c +++ b/boards/arm/common/stm32/src/stm32_mfrc522.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mfrc522.c + * boards/arm/common/stm32/src/stm32_mfrc522.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mlx90614.c b/boards/arm/common/stm32/src/stm32_mlx90614.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mlx90614.c rename to boards/arm/common/stm32/src/stm32_mlx90614.c index 3d6944c30fded..984422d914927 100644 --- a/boards/arm/stm32/common/src/stm32_mlx90614.c +++ b/boards/arm/common/stm32/src/stm32_mlx90614.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mlx90614.c + * boards/arm/common/stm32/src/stm32_mlx90614.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpl115a.c b/boards/arm/common/stm32/src/stm32_mpl115a.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mpl115a.c rename to boards/arm/common/stm32/src/stm32_mpl115a.c index ad467fd5d167e..f246d1716849c 100644 --- a/boards/arm/stm32/common/src/stm32_mpl115a.c +++ b/boards/arm/common/stm32/src/stm32_mpl115a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpl115a.c + * boards/arm/common/stm32/src/stm32_mpl115a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpr121.c b/boards/arm/common/stm32/src/stm32_mpr121.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_mpr121.c rename to boards/arm/common/stm32/src/stm32_mpr121.c index bd0d0d5ad5e02..29a5049dfadf6 100644 --- a/boards/arm/stm32/common/src/stm32_mpr121.c +++ b/boards/arm/common/stm32/src/stm32_mpr121.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpr121.c + * boards/arm/common/stm32/src/stm32_mpr121.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ms5611.c b/boards/arm/common/stm32/src/stm32_ms5611.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ms5611.c rename to boards/arm/common/stm32/src/stm32_ms5611.c index 9e230e86afb56..b38b0097608c9 100644 --- a/boards/arm/stm32/common/src/stm32_ms5611.c +++ b/boards/arm/common/stm32/src/stm32_ms5611.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ms5611.c + * boards/arm/common/stm32/src/stm32_ms5611.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mt6816.c b/boards/arm/common/stm32/src/stm32_mt6816.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mt6816.c rename to boards/arm/common/stm32/src/stm32_mt6816.c index 834e120385036..41757f28677d2 100644 --- a/boards/arm/stm32/common/src/stm32_mt6816.c +++ b/boards/arm/common/stm32/src/stm32_mt6816.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mt6816.c + * boards/arm/common/stm32/src/stm32_mt6816.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_nrf24l01.c b/boards/arm/common/stm32/src/stm32_nrf24l01.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_nrf24l01.c rename to boards/arm/common/stm32/src/stm32_nrf24l01.c index 62560e1244328..9b086e8c3b3eb 100644 --- a/boards/arm/stm32/common/src/stm32_nrf24l01.c +++ b/boards/arm/common/stm32/src/stm32_nrf24l01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_nrf24l01.c + * boards/arm/common/stm32/src/stm32_nrf24l01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_nunchuck.c b/boards/arm/common/stm32/src/stm32_nunchuck.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_nunchuck.c rename to boards/arm/common/stm32/src/stm32_nunchuck.c index e25d7fe770ab4..27b4ba76b7f6a 100644 --- a/boards/arm/stm32/common/src/stm32_nunchuck.c +++ b/boards/arm/common/stm32/src/stm32_nunchuck.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_nunchuck.c + * boards/arm/common/stm32/src/stm32_nunchuck.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_sbutton.c b/boards/arm/common/stm32/src/stm32_sbutton.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_sbutton.c rename to boards/arm/common/stm32/src/stm32_sbutton.c index 5f2e52a9ac8c0..0659794a375ae 100644 --- a/boards/arm/stm32/common/src/stm32_sbutton.c +++ b/boards/arm/common/stm32/src/stm32_sbutton.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_sbutton.c + * boards/arm/common/stm32/src/stm32_sbutton.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c b/boards/arm/common/stm32/src/stm32_ssd1306.c similarity index 98% rename from boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c rename to boards/arm/common/stm32/src/stm32_ssd1306.c index cf14f06f94338..1c73555da92e4 100644 --- a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c +++ b/boards/arm/common/stm32/src/stm32_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c + * boards/arm/common/stm32/src/stm32_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * @@ -90,6 +90,9 @@ int board_ssd1306_initialize(int busno) /* And turn the OLED on */ g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + + ssd1306_fill(g_lcddev, 0xff); + return OK; } } @@ -138,9 +141,6 @@ int board_ssd1306_initialize(int busno) /* And turn the OLED on */ g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - - ssd1306_fill(g_lcddev, 0xff); - return OK; } } diff --git a/boards/arm/stm32/common/src/stm32_tone.c b/boards/arm/common/stm32/src/stm32_tone.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_tone.c rename to boards/arm/common/stm32/src/stm32_tone.c index 58bbcd22242ad..178f8c1504c8a 100644 --- a/boards/arm/stm32/common/src/stm32_tone.c +++ b/boards/arm/common/stm32/src/stm32_tone.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_tone.c + * boards/arm/common/stm32/src/stm32_tone.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_veml6070.c b/boards/arm/common/stm32/src/stm32_veml6070.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_veml6070.c rename to boards/arm/common/stm32/src/stm32_veml6070.c index e5b38b9ac9b84..b5e918973f20c 100644 --- a/boards/arm/stm32/common/src/stm32_veml6070.c +++ b/boards/arm/common/stm32/src/stm32_veml6070.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_veml6070.c + * boards/arm/common/stm32/src/stm32_veml6070.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ws2812.c b/boards/arm/common/stm32/src/stm32_ws2812.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ws2812.c rename to boards/arm/common/stm32/src/stm32_ws2812.c index 640fb1e630879..d206941ed91ae 100644 --- a/boards/arm/stm32/common/src/stm32_ws2812.c +++ b/boards/arm/common/stm32/src/stm32_ws2812.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ws2812.c + * boards/arm/common/stm32/src/stm32_ws2812.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_xen1210.c b/boards/arm/common/stm32/src/stm32_xen1210.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_xen1210.c rename to boards/arm/common/stm32/src/stm32_xen1210.c index 1dcb2a2787ee6..4b4311933c7b9 100644 --- a/boards/arm/stm32/common/src/stm32_xen1210.c +++ b/boards/arm/common/stm32/src/stm32_xen1210.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_xen1210.c + * boards/arm/common/stm32/src/stm32_xen1210.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_zerocross.c b/boards/arm/common/stm32/src/stm32_zerocross.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_zerocross.c rename to boards/arm/common/stm32/src/stm32_zerocross.c index c0a8a3900f4e8..660719d6fb996 100644 --- a/boards/arm/stm32/common/src/stm32_zerocross.c +++ b/boards/arm/common/stm32/src/stm32_zerocross.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_zerocross.c + * boards/arm/common/stm32/src/stm32_zerocross.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common b/boards/arm/stm32/common new file mode 120000 index 0000000000000..f25cef98ae272 --- /dev/null +++ b/boards/arm/stm32/common @@ -0,0 +1 @@ +../common/stm32 \ No newline at end of file diff --git a/boards/arm/stm32/common/src/stm32_qencoder.c b/boards/arm/stm32/common/src/stm32_qencoder.c deleted file mode 100644 index c701ecc056409..0000000000000 --- a/boards/arm/stm32/common/src/stm32_qencoder.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno) -{ - int ret; - char devpath[12]; - - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", timerno); - snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno); - ret = stm32_qeinitialize(devpath, timerno); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - } - - return ret; -} diff --git a/boards/arm/stm32/common/src/stm32_ssd1306.c b/boards/arm/stm32/common/src/stm32_ssd1306.c deleted file mode 100644 index 093699e26b866..0000000000000 --- a/boards/arm/stm32/common/src/stm32_ssd1306.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. I2C version. - * - * Input Parameters: - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_I2C -int board_ssd1306_initialize(int busno) -{ - struct i2c_master_s *i2c; - const int devno = 0; - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - lcderr("ERROR: Failed to initialize I2C port %d\n", busno); - return -ENODEV; - } - - /* Bind the I2C port to the OLED */ - - g_lcddev = ssd1306_initialize(i2c, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind I2C port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound I2C port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. SPI version. - * - * Input Parameters: - * busno - The SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_SPI -int board_ssd1306_initialize(int busno) -{ - struct spi_dev_s *spi; - const int devno = 0; - - /* Initialize SPI */ - - spi = stm32_spibus_initialize(busno); - if (!spi) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", busno); - return -ENODEV; - } - - /* Bind the SPI port to the OLED */ - - g_lcddev = ssd1306_initialize(spi, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound SPI port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void) -{ - return g_lcddev; -} diff --git a/boards/arm/stm32f0l0g0/common b/boards/arm/stm32f0l0g0/common new file mode 120000 index 0000000000000..f25cef98ae272 --- /dev/null +++ b/boards/arm/stm32f0l0g0/common @@ -0,0 +1 @@ +../common/stm32 \ No newline at end of file diff --git a/boards/arm/stm32f0l0g0/common/CMakeLists.txt b/boards/arm/stm32f0l0g0/common/CMakeLists.txt deleted file mode 100644 index 4741419517f6b..0000000000000 --- a/boards/arm/stm32f0l0g0/common/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/common/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) -target_include_directories(board PRIVATE include) diff --git a/boards/arm/stm32f0l0g0/common/Kconfig b/boards/arm/stm32f0l0g0/common/Kconfig deleted file mode 100644 index 18c7905aed7cf..0000000000000 --- a/boards/arm/stm32f0l0g0/common/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - diff --git a/boards/arm/stm32f0l0g0/common/Makefile b/boards/arm/stm32f0l0g0/common/Makefile deleted file mode 100644 index 7318baae08c34..0000000000000 --- a/boards/arm/stm32f0l0g0/common/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -############################################################################# -# boards/arm/stm32f0l0g0/common/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -include board/Make.defs -include src/Make.defs - -DEPPATH += --dep-path board -DEPPATH += --dep-path src - -include $(TOPDIR)/boards/Board.mk - -ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src -BOARDDIR = $(ARCHSRCDIR)$(DELIM)board -CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h b/boards/arm/stm32f0l0g0/common/include/board_qencoder.h deleted file mode 100644 index b16fbb020d089..0000000000000 --- a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h b/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h deleted file mode 100644 index 3831d23592bf2..0000000000000 --- a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device - * - * Input Parameters: - * busno - The I2C or SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_ssd1306_initialize(int busno); - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt deleted file mode 100644 index 2b7dc2f3527bc..0000000000000 --- a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt +++ /dev/null @@ -1,38 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/common/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -if(CONFIG_ARCH_BOARD_COMMON) - - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_ssd1306.c) - endif() - - if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS board_qencoder.c) - endif() - - if(CONFIG_PWM) - list(APPEND SRCS board_pwm.c) - endif() - -endif() -target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f0l0g0/common/src/Make.defs b/boards/arm/stm32f0l0g0/common/src/Make.defs deleted file mode 100644 index 972383a629149..0000000000000 --- a/boards/arm/stm32f0l0g0/common/src/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################# -# boards/arm/stm32f0l0g0/common/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_ssd1306.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - CSRCS += board_qencoder.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += board_pwm.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif From 6ae6aee198c7cbede954f4fa1bcff80b22d7c588 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 09:34:14 +0200 Subject: [PATCH 28/52] boards/arm/stm32l4: build through common STM32 board infrastructure Add boards/arm/stm32l4/common so STM32L4 boards build through the shared STM32 board-common tree (boards/arm/common/stm32), like the other split STM32 families. Convert each STM32L4 board's src/Makefile to src/Make.defs so the per-board sources are pulled in by the common board Makefile. Signed-off-by: raiden00pl --- .../src/{Makefile => Make.defs} | 4 +- boards/arm/stm32l4/common/CMakeLists.txt | 23 +++++++++++ boards/arm/stm32l4/common/Kconfig | 6 +++ boards/arm/stm32l4/common/Makefile | 39 +++++++++++++++++++ .../nucleo-l432kc/src/{Makefile => Make.defs} | 4 +- .../nucleo-l452re/src/{Makefile => Make.defs} | 4 +- .../nucleo-l476rg/src/{Makefile => Make.defs} | 4 +- .../nucleo-l496zg/src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- .../stm32l476-mdk/src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- 12 files changed, 95 insertions(+), 9 deletions(-) rename boards/arm/stm32l4/b-l475e-iot01a/src/{Makefile => Make.defs} (89%) create mode 100644 boards/arm/stm32l4/common/CMakeLists.txt create mode 100644 boards/arm/stm32l4/common/Kconfig create mode 100644 boards/arm/stm32l4/common/Makefile rename boards/arm/stm32l4/nucleo-l432kc/src/{Makefile => Make.defs} (93%) rename boards/arm/stm32l4/nucleo-l452re/src/{Makefile => Make.defs} (90%) rename boards/arm/stm32l4/nucleo-l476rg/src/{Makefile => Make.defs} (94%) rename boards/arm/stm32l4/nucleo-l496zg/src/{Makefile => Make.defs} (92%) rename boards/arm/stm32l4/steval-stlcs01v1/src/{Makefile => Make.defs} (88%) rename boards/arm/stm32l4/stm32l476-mdk/src/{Makefile => Make.defs} (89%) rename boards/arm/stm32l4/stm32l476vg-disco/src/{Makefile => Make.defs} (92%) rename boards/arm/stm32l4/stm32l4r9ai-disco/src/{Makefile => Make.defs} (92%) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs similarity index 89% rename from boards/arm/stm32l4/b-l475e-iot01a/src/Makefile rename to boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs index 4b6dba43ad15b..f9a89b4acba9c 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs @@ -34,4 +34,6 @@ ifeq ($(CONFIG_SPIRIT_NETDEV),y) CSRCS += stm32_spirit.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/common/CMakeLists.txt b/boards/arm/stm32l4/common/CMakeLists.txt new file mode 100644 index 0000000000000..c675d8563e38e --- /dev/null +++ b/boards/arm/stm32l4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l4/common/Kconfig b/boards/arm/stm32l4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l4/common/Makefile b/boards/arm/stm32l4/common/Makefile new file mode 100644 index 0000000000000..af882fa76b3ec --- /dev/null +++ b/boards/arm/stm32l4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs similarity index 93% rename from boards/arm/stm32l4/nucleo-l432kc/src/Makefile rename to boards/arm/stm32l4/nucleo-l432kc/src/Make.defs index 6f1745c753a13..2cccd3b3d3c84 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs @@ -100,4 +100,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l452re/src/Makefile b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs similarity index 90% rename from boards/arm/stm32l4/nucleo-l452re/src/Makefile rename to boards/arm/stm32l4/nucleo-l452re/src/Make.defs index 4c04979e48a7b..95d5c9ae297db 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs @@ -42,4 +42,6 @@ ifeq ($(CONFIG_DAC),y) CSRCS += stm32_dac.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs similarity index 94% rename from boards/arm/stm32l4/nucleo-l476rg/src/Makefile rename to boards/arm/stm32l4/nucleo-l476rg/src/Make.defs index d51f9740937ce..5950a0e16c516 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs @@ -117,4 +117,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/nucleo-l496zg/src/Makefile rename to boards/arm/stm32l4/nucleo-l496zg/src/Make.defs index 4516af4433cb7..af3cc615e192c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs @@ -71,4 +71,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs similarity index 88% rename from boards/arm/stm32l4/steval-stlcs01v1/src/Makefile rename to boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs index 80a41f0fa3875..e67f020257ee0 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs @@ -32,4 +32,6 @@ ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs similarity index 89% rename from boards/arm/stm32l4/stm32l476-mdk/src/Makefile rename to boards/arm/stm32l4/stm32l476-mdk/src/Make.defs index 66a39c742290b..4c2a02f3f1bcf 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile +++ b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs @@ -36,4 +36,6 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/stm32l476vg-disco/src/Makefile rename to boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs index aa94c8d033ccd..a2a0313ee246f 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs @@ -64,4 +64,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile rename to boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs index 377448e664a8f..fb0302f1b5827 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs @@ -77,4 +77,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board From 914987119ce39aaeb1fc7ad47f5bca3e3c469818 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:43:32 +0200 Subject: [PATCH 29/52] !arch/stm32f0l0g0: split into stm32f0, stm32l0, stm32g0 and stm32c0 BREAKING CHANGE: The combined STM32F0/L0/G0/C0 architecture and board paths were split into stm32f0, stm32l0, stm32g0, and stm32c0 directories. Out-of-tree boards, include paths, source paths, and defconfigs must move from stm32f0l0g0 to the matching split family. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 559 +++---- LICENSE | 20 +- arch/arm/include/phy62xx/phy62xx_irq.h | 2 +- arch/arm/include/stm32c0/chip.h | 157 ++ .../stm32c0_irq.h => stm32c0/irq.h} | 68 +- arch/arm/include/stm32f0/chip.h | 238 +++ .../stm32f0_irq.h => stm32f0/irq.h} | 72 +- arch/arm/include/stm32f0l0g0/chip.h | 776 --------- arch/arm/include/stm32f0l0g0/irq.h | 114 -- arch/arm/include/stm32g0/chip.h | 166 ++ .../stm32g0_irq.h => stm32g0/irq.h} | 76 +- arch/arm/include/stm32l0/chip.h | 371 +++++ .../stm32l0_irq.h => stm32l0/irq.h} | 79 +- arch/arm/src/stm32c0/CMakeLists.txt | 32 + arch/arm/src/stm32c0/Kconfig | 283 ++++ .../src/{stm32f0l0g0 => stm32c0}/Make.defs | 21 +- arch/arm/src/{stm32f0l0g0 => stm32c0}/chip.h | 12 +- .../src/stm32c0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32c0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32c0_dmamux.h | 8 +- .../hardware/stm32c0_exti.h | 8 +- .../hardware/stm32c0_flash.h | 8 +- .../hardware/stm32c0_memorymap.h | 8 +- .../hardware/stm32c0_pinmap.h | 8 +- .../hardware/stm32c0_pwr.h | 8 +- .../hardware/stm32c0_rcc.h | 8 +- arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32.h | 8 +- .../src/{stm32f0l0g0 => stm32c0}/stm32_rcc.c | 16 +- .../{stm32f0l0g0 => stm32c0}/stm32c0_rcc.c | 2 +- arch/arm/src/stm32f0/CMakeLists.txt | 32 + arch/arm/src/stm32f0/Kconfig | 555 +++++++ arch/arm/src/stm32f0/Make.defs | 31 + .../stm32_syscfg.h => stm32f0/chip.h} | 33 +- .../src/stm32f0/hardware/stm32_memorymap.h | 26 + arch/arm/src/stm32f0/hardware/stm32_pinmap.h | 29 + .../hardware/stm32f03x_memorymap.h | 8 +- .../hardware/stm32f03x_pinmap.h | 8 +- .../hardware/stm32f05x_pinmap.h | 8 +- .../hardware/stm32f05xf07xf09x_memorymap.h | 8 +- .../hardware/stm32f07x_pinmap.h | 8 +- .../hardware/stm32f09x_pinmap.h | 8 +- .../hardware/stm32f0_exti.h | 8 +- .../hardware/stm32f0_flash.h | 8 +- .../hardware/stm32f0_pwr.h | 8 +- .../hardware/stm32f0_rcc.h | 8 +- .../hardware/stm32f0_syscfg.h | 8 +- .../stm32_pwr.c => stm32f0/stm32.h} | 34 +- arch/arm/src/stm32f0/stm32_rcc.c | 220 +++ .../{stm32f0l0g0 => stm32f0}/stm32f0_rcc.c | 2 +- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 55 - arch/arm/src/stm32f0l0g0/Kconfig | 1415 ----------------- arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h | 101 -- arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h | 82 - arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h | 103 -- .../arm/src/stm32f0l0g0/hardware/stm32_uart.h | 46 - .../src/stm32f0l0g0/hardware/stm32_uart_v1.h | 303 ---- .../src/stm32f0l0g0/hardware/stm32_uart_v2.h | 352 ---- arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h | 129 -- arch/arm/src/stm32f0l0g0/stm32_crypto.c | 162 -- arch/arm/src/stm32f0l0g0/stm32_lowputc.h | 66 - arch/arm/src/stm32f0l0g0/stm32_rcc.h | 90 -- arch/arm/src/stm32f0l0g0/stm32_start.h | 64 - arch/arm/src/stm32g0/CMakeLists.txt | 32 + arch/arm/src/stm32g0/Kconfig | 430 +++++ arch/arm/src/stm32g0/Make.defs | 31 + .../hardware/stm32_rcc.h => stm32g0/chip.h} | 35 +- .../src/stm32g0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32g0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32g0_dmamux.h | 8 +- .../hardware/stm32g0_exti.h | 8 +- .../hardware/stm32g0_flash.h | 8 +- .../hardware/stm32g0_memorymap.h | 8 +- .../hardware/stm32g0_pinmap.h | 8 +- .../hardware/stm32g0_pwr.h | 8 +- .../hardware/stm32g0_rcc.h | 8 +- .../hardware/stm32g0_syscfg.h | 8 +- arch/arm/src/stm32g0/stm32.h | 54 + arch/arm/src/stm32g0/stm32_rcc.c | 220 +++ .../{stm32f0l0g0 => stm32g0}/stm32g0_rcc.c | 2 +- arch/arm/src/stm32l0/CMakeLists.txt | 32 + arch/arm/src/stm32l0/Kconfig | 269 ++++ arch/arm/src/stm32l0/Make.defs | 31 + arch/arm/src/stm32l0/chip.h | 44 + .../src/stm32l0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32l0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32l0_exti.h | 8 +- .../hardware/stm32l0_flash.h | 8 +- .../hardware/stm32l0_memorymap.h | 8 +- .../hardware/stm32l0_pinmap.h | 8 +- .../hardware/stm32l0_pwr.h | 8 +- .../hardware/stm32l0_rcc.h | 8 +- .../hardware/stm32l0_syscfg.h | 8 +- arch/arm/src/stm32l0/stm32.h | 54 + arch/arm/src/stm32l0/stm32_rcc.c | 220 +++ .../{stm32f0l0g0 => stm32l0}/stm32l0_rcc.c | 2 +- boards/Kconfig | 7 +- boards/arm/stm32c0/common/CMakeLists.txt | 23 + boards/arm/stm32c0/common/Kconfig | 6 + boards/arm/stm32c0/common/Makefile | 39 + .../nucleo-c071rb}/CMakeLists.txt | 2 +- .../nucleo-c071rb/Kconfig | 0 .../nucleo-c071rb/configs/adcscope/defconfig | 3 +- .../nucleo-c071rb/configs/jumbo/defconfig | 3 +- .../nucleo-c071rb/configs/nsh/defconfig | 3 +- .../nucleo-c071rb/include/board.h | 2 +- .../nucleo-c071rb}/scripts/Make.defs | 2 +- .../nucleo-c071rb/scripts/flash.ld | 2 +- .../nucleo-c071rb/src/CMakeLists.txt | 2 +- .../nucleo-c071rb/src/Make.defs | 2 +- .../nucleo-c071rb/src/nucleo-c071rb.h | 2 +- .../nucleo-c071rb/src/stm32_adc.c | 2 +- .../nucleo-c071rb/src/stm32_autoleds.c | 2 +- .../nucleo-c071rb/src/stm32_boot.c | 2 +- .../nucleo-c071rb/src/stm32_bringup.c | 2 +- .../nucleo-c071rb/src/stm32_buttons.c | 2 +- .../nucleo-c071rb/src/stm32_userleds.c | 2 +- .../nucleo-c092rc}/CMakeLists.txt | 2 +- .../nucleo-c092rc/Kconfig | 0 .../nucleo-c092rc/configs/can/defconfig | 3 +- .../nucleo-c092rc/configs/cansock/defconfig | 3 +- .../nucleo-c092rc/configs/jumbo/defconfig | 3 +- .../nucleo-c092rc/configs/nsh/defconfig | 3 +- .../nucleo-c092rc/include/board.h | 2 +- .../nucleo-c092rc}/scripts/Make.defs | 2 +- .../nucleo-c092rc/scripts/flash.ld | 2 +- .../nucleo-c092rc/src/CMakeLists.txt | 2 +- .../nucleo-c092rc/src/Make.defs | 2 +- .../nucleo-c092rc/src/nucleo-c092rc.h | 2 +- .../nucleo-c092rc/src/stm32_adc.c | 2 +- .../nucleo-c092rc/src/stm32_autoleds.c | 2 +- .../nucleo-c092rc/src/stm32_boot.c | 2 +- .../nucleo-c092rc/src/stm32_bringup.c | 2 +- .../nucleo-c092rc/src/stm32_buttons.c | 2 +- .../nucleo-c092rc/src/stm32_can.c | 2 +- .../nucleo-c092rc/src/stm32_cansock.c | 2 +- .../nucleo-c092rc/src/stm32_userleds.c | 2 +- boards/arm/stm32f0/common/CMakeLists.txt | 23 + boards/arm/stm32f0/common/Kconfig | 6 + boards/arm/stm32f0/common/Makefile | 39 + .../nucleo-f072rb/CMakeLists.txt | 2 +- .../nucleo-f072rb/Kconfig | 0 .../nucleo-f072rb/configs/nsh/defconfig | 3 +- .../nucleo-f072rb/include/board.h | 2 +- .../nucleo-f072rb}/scripts/Make.defs | 2 +- .../nucleo-f072rb/scripts/flash.ld | 2 +- .../nucleo-f072rb/src/CMakeLists.txt | 2 +- .../nucleo-f072rb/src/Make.defs | 2 +- .../nucleo-f072rb/src/nucleo-f072rb.h | 2 +- .../nucleo-f072rb/src/stm32_autoleds.c | 2 +- .../nucleo-f072rb/src/stm32_boot.c | 2 +- .../nucleo-f072rb/src/stm32_bringup.c | 2 +- .../nucleo-f072rb/src/stm32_buttons.c | 2 +- .../nucleo-f072rb/src/stm32_userleds.c | 2 +- .../nucleo-f091rc/CMakeLists.txt | 2 +- .../nucleo-f091rc/Kconfig | 0 .../nucleo-f091rc/configs/nsh/defconfig | 3 +- .../nucleo-f091rc/configs/sx127x/defconfig | 3 +- .../nucleo-f091rc/include/board.h | 2 +- .../nucleo-f091rc/scripts/Make.defs | 2 +- .../nucleo-f091rc/scripts/flash.ld | 2 +- .../nucleo-f091rc/src/CMakeLists.txt | 2 +- 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.../stm32f051-discovery/src/stm32_userleds.c | 2 +- .../src/stm32f051-discovery.h | 2 +- .../stm32f072-discovery/CMakeLists.txt | 23 + .../stm32f072-discovery/Kconfig | 0 .../stm32f072-discovery/configs/nsh/defconfig | 3 +- .../stm32f072-discovery/include/board.h | 2 +- .../stm32f072-discovery/scripts/Make.defs | 41 + .../stm32f072-discovery/scripts/flash.ld | 2 +- .../stm32f072-discovery/src/CMakeLists.txt | 2 +- .../stm32f072-discovery/src/Make.defs | 2 +- .../stm32f072-discovery/src/stm32_autoleds.c | 2 +- .../stm32f072-discovery/src/stm32_boot.c | 2 +- .../stm32f072-discovery/src/stm32_bringup.c | 2 +- .../stm32f072-discovery/src/stm32_buttons.c | 2 +- .../stm32f072-discovery/src/stm32_userleds.c | 2 +- .../src/stm32f072-discovery.h | 2 +- .../b-l072z-lrwan1/scripts/Make.defs | 41 - boards/arm/stm32f0l0g0/common | 1 - .../stm32f0l0g0/nucleo-g070rb/CMakeLists.txt | 23 - .../stm32f0l0g0/nucleo-g071rb/CMakeLists.txt | 23 - .../stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt | 23 - .../stm32f0l0g0/nucleo-l073rz/CMakeLists.txt | 23 - .../stm32f051-discovery/CMakeLists.txt | 23 - .../stm32f051-discovery/scripts/Make.defs | 41 - .../stm32f072-discovery/CMakeLists.txt | 23 - .../stm32f072-discovery/scripts/Make.defs | 41 - .../stm32g071b-disco/CMakeLists.txt | 23 - .../stm32g071b-disco/scripts/Make.defs | 41 - .../stm32l0538-disco/CMakeLists.txt | 23 - boards/arm/stm32g0/common/CMakeLists.txt | 23 + boards/arm/stm32g0/common/Kconfig | 6 + boards/arm/stm32g0/common/Makefile | 39 + .../arm/stm32g0/nucleo-g070rb/CMakeLists.txt | 23 + .../nucleo-g070rb/Kconfig | 0 .../nucleo-g070rb/configs/nsh/defconfig | 3 +- .../nucleo-g070rb/include/board.h | 2 +- .../nucleo-g070rb/scripts/Make.defs | 2 +- .../nucleo-g070rb/scripts/ld.script | 2 +- .../nucleo-g070rb/src/CMakeLists.txt | 2 +- .../nucleo-g070rb/src/Make.defs | 2 +- .../nucleo-g070rb/src/nucleo-g070rb.h | 2 +- .../nucleo-g070rb/src/stm32_autoleds.c | 2 +- .../nucleo-g070rb/src/stm32_boot.c | 2 +- .../nucleo-g070rb/src/stm32_bringup.c | 2 +- .../nucleo-g070rb/src/stm32_buttons.c | 2 +- .../nucleo-g070rb/src/stm32_gpio.c | 2 +- .../nucleo-g070rb/src/stm32_pwm.c | 2 +- .../nucleo-g070rb/src/stm32_timer.c | 2 +- .../arm/stm32g0/nucleo-g071rb/CMakeLists.txt | 23 + .../nucleo-g071rb/Kconfig | 0 .../nucleo-g071rb/configs/nsh/defconfig | 3 +- .../nucleo-g071rb/include/board.h | 2 +- .../nucleo-g071rb/scripts/Make.defs | 2 +- .../nucleo-g071rb/scripts/ld.script | 2 +- .../nucleo-g071rb}/src/CMakeLists.txt | 2 +- .../nucleo-g071rb/src/Make.defs | 2 +- .../nucleo-g071rb/src/nucleo-g071rb.h | 2 +- .../nucleo-g071rb/src/stm32_autoleds.c | 2 +- .../nucleo-g071rb/src/stm32_boot.c | 2 +- .../nucleo-g071rb/src/stm32_bringup.c | 2 +- .../nucleo-g071rb/src/stm32_buttons.c | 2 +- .../arm/stm32g0/nucleo-g0b1re/CMakeLists.txt | 23 + .../nucleo-g0b1re/Kconfig | 0 .../nucleo-g0b1re/configs/adc/defconfig | 3 +- .../nucleo-g0b1re/configs/adc_dma/defconfig | 3 +- .../nucleo-g0b1re/configs/nsh/defconfig | 3 +- .../nucleo-g0b1re/include/board.h | 2 +- .../nucleo-g0b1re/scripts/Make.defs | 2 +- .../nucleo-g0b1re/scripts/ld.script | 2 +- .../nucleo-g0b1re}/src/CMakeLists.txt | 2 +- .../nucleo-g0b1re/src/Make.defs | 2 +- .../nucleo-g0b1re/src/nucleo-g0b1re.h | 2 +- .../nucleo-g0b1re/src/stm32_adc.c | 2 +- .../nucleo-g0b1re/src/stm32_autoleds.c | 2 +- .../nucleo-g0b1re/src/stm32_boot.c | 2 +- .../nucleo-g0b1re/src/stm32_bringup.c | 2 +- .../nucleo-g0b1re/src/stm32_buttons.c | 2 +- .../stm32g0/stm32g071b-disco/CMakeLists.txt | 23 + .../stm32g071b-disco/Kconfig | 0 .../stm32g071b-disco/configs/nsh/defconfig | 3 +- .../stm32g071b-disco/configs/oled/defconfig | 3 +- .../stm32g071b-disco/include/board.h | 2 +- .../stm32g071b-disco}/scripts/Make.defs | 2 +- .../stm32g071b-disco/scripts/ld.script | 2 +- .../stm32g071b-disco/src/CMakeLists.txt | 2 +- .../stm32g071b-disco/src/Make.defs | 2 +- .../stm32g071b-disco/src/stm32_boot.c | 2 +- .../stm32g071b-disco/src/stm32_bringup.c | 2 +- .../stm32g071b-disco/src/stm32_djoystick.c | 2 +- .../stm32g071b-disco/src/stm32_gpio.c | 2 +- .../stm32g071b-disco/src/stm32_ina226.c | 2 +- .../stm32g071b-disco/src/stm32_lcd_ssd1306.c | 2 +- .../stm32g071b-disco/src/stm32_spi.c | 2 +- .../stm32g071b-disco/src/stm32_userleds.c | 2 +- .../stm32g071b-disco/src/stm32g071b-disco.h | 2 +- .../arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt | 23 + .../b-l072z-lrwan1/Kconfig | 0 .../b-l072z-lrwan1/configs/adc/defconfig | 3 +- .../b-l072z-lrwan1/configs/nsh/defconfig | 3 +- .../configs/nxlines_oled/defconfig | 3 +- .../b-l072z-lrwan1/configs/sx127x/defconfig | 3 +- .../b-l072z-lrwan1/include/board.h | 2 +- .../stm32l0/b-l072z-lrwan1/scripts/Make.defs | 41 + .../b-l072z-lrwan1/scripts/ld.script | 2 +- .../b-l072z-lrwan1/src/CMakeLists.txt | 2 +- .../b-l072z-lrwan1/src/Make.defs | 2 +- .../b-l072z-lrwan1/src/b-l072z-lrwan1.h | 2 +- .../b-l072z-lrwan1/src/stm32_adc.c | 2 +- .../b-l072z-lrwan1/src/stm32_autoleds.c | 2 +- .../b-l072z-lrwan1/src/stm32_boot.c | 2 +- .../b-l072z-lrwan1/src/stm32_bringup.c | 2 +- .../b-l072z-lrwan1/src/stm32_lcd_ssd1306.c | 2 +- .../b-l072z-lrwan1/src/stm32_spi.c | 2 +- .../b-l072z-lrwan1/src/stm32_sx127x.c | 2 +- boards/arm/stm32l0/common/CMakeLists.txt | 23 + boards/arm/stm32l0/common/Kconfig | 6 + boards/arm/stm32l0/common/Makefile | 39 + .../arm/stm32l0/nucleo-l073rz/CMakeLists.txt | 23 + .../nucleo-l073rz/Kconfig | 0 .../nucleo-l073rz/configs/nsh/defconfig | 3 +- .../nucleo-l073rz/configs/sx127x/defconfig | 3 +- .../nucleo-l073rz/include/board.h | 2 +- .../stm32l0/nucleo-l073rz/scripts/Make.defs | 41 + .../nucleo-l073rz/scripts/ld.script | 2 +- .../nucleo-l073rz/src/CMakeLists.txt | 2 +- .../nucleo-l073rz/src/Make.defs | 2 +- .../nucleo-l073rz/src/nucleo-l073rz.h | 2 +- .../nucleo-l073rz/src/stm32_autoleds.c | 2 +- .../nucleo-l073rz/src/stm32_boot.c | 2 +- .../nucleo-l073rz/src/stm32_bringup.c | 2 +- .../nucleo-l073rz/src/stm32_buttons.c | 2 +- .../nucleo-l073rz/src/stm32_mfrc522.c | 2 +- .../nucleo-l073rz/src/stm32_nrf24l01.c | 2 +- .../nucleo-l073rz/src/stm32_spi.c | 2 +- .../nucleo-l073rz/src/stm32_sx127x.c | 2 +- .../stm32l0/stm32l0538-disco/CMakeLists.txt | 23 + .../stm32l0538-disco/Kconfig | 0 .../stm32l0538-disco/configs/nsh/defconfig | 3 +- .../stm32l0538-disco/include/board.h | 2 +- .../stm32l0538-disco/scripts/Make.defs | 2 +- .../stm32l0538-disco/scripts/ld.script | 2 +- .../stm32l0538-disco/src/CMakeLists.txt | 2 +- .../stm32l0538-disco/src/Make.defs | 2 +- .../stm32l0538-disco/src/stm32_autoleds.c | 2 +- .../stm32l0538-disco/src/stm32_boot.c | 2 +- .../stm32l0538-disco/src/stm32_bringup.c | 2 +- .../stm32l0538-disco/src/stm32_buttons.c | 2 +- .../stm32l0538-disco/src/stm32l0538-disco.h | 2 +- 330 files changed, 5081 insertions(+), 5113 deletions(-) create mode 100644 arch/arm/include/stm32c0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32c0_irq.h => stm32c0/irq.h} (78%) create mode 100644 arch/arm/include/stm32f0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32f0_irq.h => stm32f0/irq.h} (80%) delete mode 100644 arch/arm/include/stm32f0l0g0/chip.h delete mode 100644 arch/arm/include/stm32f0l0g0/irq.h create mode 100644 arch/arm/include/stm32g0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32g0_irq.h => stm32g0/irq.h} (85%) create mode 100644 arch/arm/include/stm32l0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32l0_irq.h => stm32l0/irq.h} (76%) create mode 100644 arch/arm/src/stm32c0/CMakeLists.txt create mode 100644 arch/arm/src/stm32c0/Kconfig rename arch/arm/src/{stm32f0l0g0 => stm32c0}/Make.defs (71%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/chip.h (85%) create mode 100644 arch/arm/src/stm32c0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32c0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_dmamux.h (89%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_exti.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_flash.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_pwr.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32.h (91%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32_rcc.c (94%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32c0_rcc.c (99%) create mode 100644 arch/arm/src/stm32f0/CMakeLists.txt create mode 100644 arch/arm/src/stm32f0/Kconfig create mode 100644 arch/arm/src/stm32f0/Make.defs rename arch/arm/src/{stm32f0l0g0/hardware/stm32_syscfg.h => stm32f0/chip.h} (69%) create mode 100644 arch/arm/src/stm32f0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f03x_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f03x_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f05x_pinmap.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f05xf07xf09x_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f07x_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f09x_pinmap.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_exti.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_flash.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_pwr.h (94%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_syscfg.h (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwr.c => stm32f0/stm32.h} (70%) create mode 100644 arch/arm/src/stm32f0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => stm32f0}/stm32f0_rcc.c (99%) delete mode 100644 arch/arm/src/stm32f0l0g0/CMakeLists.txt delete mode 100644 arch/arm/src/stm32f0l0g0/Kconfig delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_crypto.c delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_lowputc.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_rcc.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_start.h create mode 100644 arch/arm/src/stm32g0/CMakeLists.txt create mode 100644 arch/arm/src/stm32g0/Kconfig create mode 100644 arch/arm/src/stm32g0/Make.defs rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rcc.h => stm32g0/chip.h} (67%) create mode 100644 arch/arm/src/stm32g0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32g0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_dmamux.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_exti.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_flash.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_pwr.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_syscfg.h (98%) create mode 100644 arch/arm/src/stm32g0/stm32.h create mode 100644 arch/arm/src/stm32g0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => stm32g0}/stm32g0_rcc.c (99%) create mode 100644 arch/arm/src/stm32l0/CMakeLists.txt create mode 100644 arch/arm/src/stm32l0/Kconfig create mode 100644 arch/arm/src/stm32l0/Make.defs create mode 100644 arch/arm/src/stm32l0/chip.h create mode 100644 arch/arm/src/stm32l0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32l0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_exti.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_flash.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_pwr.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_syscfg.h (97%) create mode 100644 arch/arm/src/stm32l0/stm32.h create mode 100644 arch/arm/src/stm32l0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => 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stm32g0}/stm32g071b-disco/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_djoystick.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_gpio.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_ina226.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_lcd_ssd1306.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_userleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32g071b-disco.h (99%) create mode 100644 boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/adc/defconfig (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/nsh/defconfig (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/nxlines_oled/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/sx127x/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/include/board.h (99%) create mode 100644 boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/b-l072z-lrwan1.h (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_adc.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_sx127x.c (99%) create mode 100644 boards/arm/stm32l0/common/CMakeLists.txt create mode 100644 boards/arm/stm32l0/common/Kconfig create mode 100644 boards/arm/stm32l0/common/Makefile create mode 100644 boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/configs/nsh/defconfig (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/configs/sx127x/defconfig (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/include/board.h (99%) create mode 100644 boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/nucleo-l073rz.h (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_mfrc522.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_nrf24l01.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_sx127x.c (98%) create mode 100644 boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/configs/nsh/defconfig (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_boot.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_bringup.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32l0538-disco.h (98%) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index af9aa33347921..d6832ccd15103 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -905,9 +905,7 @@ arch/arm/include/mps/irq.h anjiahao@xiaomi.com alin.jerpelea@sony.com arch/arm/include/mx8mp/chip.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/irq.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/mx8mp_irq.h philippe.leduc@wandercraft.eu devel@sumpfralle.de alin.jerpelea@sony.com - arch/arm/include/nrf* raiden00@railab.me alin.jerpelea@sony.com - arch/arm/include/nuc1xx/chip.h alin.jerpelea@sony.com loketep@yahoo.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/nuc120_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com @@ -974,17 +972,17 @@ arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.gi arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32f0l0g0/chip.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com tbennett@2g-eng.com -arch/arm/include/stm32f0l0g0/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me gustavo.nihei@espressif.com -arch/arm/include/stm32f0l0g0/stm32c0_irq.h raiden00@railab.me -arch/arm/include/stm32f0l0g0/stm32f0_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com -arch/arm/include/stm32f0l0g0/stm32g0_irq.h dpo@certi.org.br 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com kwilson@2g-eng.com -arch/arm/include/stm32f0l0g0/stm32l0_irq.h alin.jerpelea@sony.com raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com +arch/arm/include/stm32c0/chip.h raiden00@railab.me +arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com +arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com titus@elbe-informatik.de arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32g0/chip.h raiden00@railab.me +arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +992,8 @@ arch/arm/include/stm32h7/stm32h7x3xx_irq.h simon@leitwert.ch David.Sidrane@NscDg arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32l0/chip.h raiden00@railab.me +arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br @@ -3431,7 +3431,6 @@ arch/arm/src/rp2040/rp2040_ws2812.h 58759586+curuvar@users.noreply.github.com xi arch/arm/src/rp2040/rp2040_ws2812.pio 58759586+curuvar@users.noreply.github.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de arch/arm/src/rp2040/rp2040_xosc.c y.512.nakamura@gmail.com ian@iandouglasscott.com xiaoxiang@xiaomi.com yinshengkai@xiaomi.com arch/arm/src/rp2040/rp2040_xosc.h y.512.nakamura@gmail.com alin.jerpelea@sony.com - arch/arm/src/rp23xx/* marco.casaroli@gmail.com alin.jerpelea@sony.com bijunda@dreame.tech arch/arm/src/rtl8720c/* jerry_tang@realsil.com.cn petro.karashchenko@gmail.com alin.jerpelea@sony.com arch/arm/src/s32k1xx/* jari.vanewijk@nxp.com peter.vanderperk@nxp.com David.Sidrane@NscDg.com alin.jerpelea@sony.com gustavo.nihei@espressif.com @@ -3440,7 +3439,6 @@ arch/arm/src/sama5/* alin.jerpelea@sony.com adam@adamfeuer.com 56726697+TimJTi@u arch/arm/src/samd2l2/* alin.jerpelea@sony.com arch/arm/src/samd5e5/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com leomar@falker.com.br arch/arm/src/samv7/* michallenc@seznam.cz petro.karashchenko@gmail.com pressste@fel.cvut.cz alin.jerpelea@sony.com xiaoxiang@xiaomi.com - arch/arm/src/stm32/Kconfig raiden00pl@gmail.com raiden00@railab.me danieloak@gmail.com arch/arm/src/stm32/chip.h raiden00pl@gmail.com alin.jerpelea@sony.com paul-a.patience@polymtl.ca arch/arm/src/stm32/hardware/stm32_adc.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com @@ -3746,142 +3744,38 @@ arch/arm/src/stm32/stm32l15xx_flash.c alin.jerpelea@sony.com abdelatif.guettouch arch/arm/src/stm32/stm32l15xxx_alarm.h juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32/stm32l15xxx_rcc.c 59230071+hartmannathan@users.noreply.github.com juha.niskanen@haltian.com alin.jerpelea@sony.com raiden00pl@gmail.com arch/arm/src/stm32/stm32l15xxx_rtcc.c juha.niskanen@haltian.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/Kconfig dpo@certi.org.br raiden00@railab.me kwilson@2g-eng.com tbennett@2g-eng.com -arch/arm/src/stm32f0l0g0/chip.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h tbennett@2g-eng.com alin.jerpelea@sony.com raiden00@railab.me kwilson@2g-eng.com -arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_can.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h raiden00@railab.me alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h alin.jerpelea@sony.com devel@sumpfralle.de -arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de -arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h alin.jerpelea@sony.com raiden00@railab.me hartman.nathan@gmail.com -arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h alin.jerpelea@sony.com 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arch/arm/src/stm32f7/chip.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com Lok Tep 1 file changed, 1 insertion(+) arch/arm/src/stm32f7/hardware/stm32_adc.h alin.jerpelea@sony.com @@ -4046,6 +3940,21 @@ arch/arm/src/stm32f7/stm32_waste.h ville.juven@unikie.com 101105604+simbit18@use arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c bob.feretich@rafresearch.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de ramtin@lambdaconcept.com arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c david_s5@nscdg.com jussi.kivilinna@haltian.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c david_s5@usa.net david_s5@nscdg.com titus@elbe-informatik.de jussi.kivilinna@haltian.com alin.jerpelea@sony.com +arch/arm/src/stm32g0/Kconfig raiden00@railab.me +arch/arm/src/stm32g0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com +arch/arm/src/stm32g0/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h kwilson@2g-eng.com raiden00pl@gmail.com raiden00@railab.me pettitkd@gmail.com alin.jerpelea@sony.com +arch/arm/src/stm32g0/hardware/stm32g0_exti.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g0/hardware/stm32g0_flash.h tbennett@2g-eng.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com petro.karashchenko@gmail.com kwilson@2g-eng.com +arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me David.Sidrane@NscDg.com gvr@certi.org.br +arch/arm/src/stm32g0/hardware/stm32g0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com kwilson@2g-eng.com tbennett@2g-eng.com +arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com +arch/arm/src/stm32g0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com +arch/arm/src/stm32g0/stm32g0_rcc.c raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me dpo@certi.org.br juha.niskanen@haltian.com arch/arm/src/stm32h5/Kconfig kwilson@2g-eng.com tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com raiden00@railab.me jlange@2g-eng.com arch/arm/src/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_adc.h tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com @@ -4276,6 +4185,20 @@ arch/arm/src/stm32h7/stm32h743xx_flash.c javiercasas@geotab.com petro.karashchen arch/arm/src/stm32h7/stm32h7b3xx_flash.c javiercasas@geotab.com petro.karashchenko@gmail.com alin.jerpelea@sony.com lipengfei28@xiaomi.com arch/arm/src/stm32h7/stm32h7x3xx_rcc.c simon@leitwert.ch raiden00pl@gmail.com david.sidrane@nscdg.com raiden00@railab.me anthony@vergeaero.com arch/arm/src/stm32h7/stm32h7x7xx_rcc.c lwazeh@gmail.com anthony@vergeaero.com raiden00@railab.me alin.jerpelea@sony.com jfbblue0922@gmail.com +arch/arm/src/stm32l0/Kconfig raiden00@railab.me +arch/arm/src/stm32l0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com +arch/arm/src/stm32l0/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_exti.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me david_s5@usa.net bob.feretich@rafresearch.com +arch/arm/src/stm32l0/hardware/stm32l0_flash.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com juha.niskanen@haltian.com +arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h David.Sidrane@NscDg.com raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32l0/hardware/stm32l0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com acassis@gmail.com +arch/arm/src/stm32l0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com +arch/arm/src/stm32l0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com +arch/arm/src/stm32l0/stm32l0_rcc.c raiden00pl@gmail.com raiden00@railab.me juha.niskanen@haltian.com matteo.golin@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/Kconfig dev@ziggurat29.com danieloak@gmail.com juha.niskanen@haltian.com sebastien@lorquet.fr arch/arm/src/stm32l4/chip.h sebastien@lorquet.fr alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/src/stm32l4/hardware/stm32l4_adc.h danieloak@gmail.com alin.jerpelea@sony.com anchao@xiaomi.com acassis@gmail.com @@ -4698,12 +4621,10 @@ arch/arm/src/stm32wl5/stm32wl5_userspace.c michal.lyszczek@bofc.pl alin.jerpelea arch/arm/src/stm32wl5/stm32wl5_userspace.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_waste.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_waste.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com - arch/arm/src/str71x/* alin.jerpelea@sony.com arch/arm/src/tiva/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com hartman.nathan@gmail.com arch/arm/src/tlsr82/* wangbowen6@xiaomi.com devel@sumpfralle.de alin.jerpelea@sony.com arch/arm/src/tms570/* xiaoxiang@xiaomi.com alin.jerpelea@sony.com - arch/arm/src/xmc4/Kconfig 101105604+simbit18@users.noreply.github.com adrien.desproges@gmail.com nicolas.lemble@gmail.com acassis@gmail.com arch/arm/src/xmc4/chip.h alin.jerpelea@sony.com raiden00pl@gmail.com arch/arm/src/xmc4/hardware/xmc4_ccu4.h thomas.narayana-swamy@wandercraft.eu nicolas.lemble@gmail.com alin.jerpelea@sony.com adrien.desproges@gmail.com @@ -10399,179 +10320,175 @@ boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c alin.jerpelea@sony.com x boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c alin.jerpelea@sony.com boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com thomas.narayana-swamy@wandercraft.eu raiden00@railab.me -boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig 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+boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/Kconfig raiden00@railab.me +boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32l0/stm32l0538-disco/include/board.h raiden00@railab.me devel@sumpfralle.de alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h raiden00@railab.me alin.jerpelea@sony.com boards/arm/stm32f7/common/Kconfig raiden00@railab.me acassis@gmail.com boards/arm/stm32f7/common/Makefile acassis@gmail.com alin.jerpelea@sony.com boards/arm/stm32f7/common/include/stm32_bh1750.h acassis@gmail.com alin.jerpelea@sony.com diff --git a/LICENSE b/LICENSE index f78dcd33b6ea2..a76c658ae4ebe 100644 --- a/LICENSE +++ b/LICENSE @@ -3386,9 +3386,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c ===================================================== Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4243,7 +4243,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h ===================================================== Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -4276,7 +4276,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_i2c.c +arch/arm/src/common/stm32/stm32_i2c_m0_v1.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4309,7 +4309,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.c +arch/arm/src/common/stm32/stm32_pwm_m0_v1.c ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4341,9 +4341,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.h -arch/arm/src/stm32f0l0g0/stm32_tim.c -arch/arm/src/stm32f0l0g0/stm32_tim.h +arch/arm/src/common/stm32/stm32_pwm_m0_v1.h +arch/arm/src/common/stm32/stm32_tim_m0_v1.c +arch/arm/src/common/stm32/stm32_tim_m0_v1.h ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4375,7 +4375,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c ================================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/include/phy62xx/phy62xx_irq.h b/arch/arm/include/phy62xx/phy62xx_irq.h index b8bf21ed912b9..c6d55217f6276 100644 --- a/arch/arm/include/phy62xx/phy62xx_irq.h +++ b/arch/arm/include/phy62xx/phy62xx_irq.h @@ -44,7 +44,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h + * found in nuttx/arch/arm/include/phy62xx/irq.h */ #define PHY62XX_IRQ_BB_IRQn (PHY62XX_IRQ_EXTINT + 4) /* 4: RCC and CRS */ diff --git a/arch/arm/include/stm32c0/chip.h b/arch/arm/include/stm32c0/chip.h new file mode 100644 index 0000000000000..64eb965d03f2d --- /dev/null +++ b/arch/arm/include/stm32c0/chip.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/include/stm32c0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32C0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32C0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32C051XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 1 /* One FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#else +# error "Unsupported STM32 Cortex M0 chip" +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32C0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h b/arch/arm/include/stm32c0/irq.h similarity index 78% rename from arch/arm/include/stm32f0l0g0/stm32c0_irq.h rename to arch/arm/include/stm32c0/irq.h index fe52e407a7dee..aba16028025fb 100644 --- a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h +++ b/arch/arm/include/stm32c0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32c0_irq.h + * arch/arm/include/stm32c0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32C0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32C0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: VDDIO2 monitor interrupt */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ @@ -87,31 +108,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32C0_IRQ_H */ diff --git a/arch/arm/include/stm32f0/chip.h b/arch/arm/include/stm32f0/chip.h new file mode 100644 index 0000000000000..c045084d62e0a --- /dev/null +++ b/arch/arm/include/stm32f0/chip.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/arm/include/stm32f0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) + +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 0 /* No I2S modules */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* One DAC channel */ +# define STM32_NCOMP 0 /* Two Analog Comparators */ +# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) + +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* Two USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 1 /* One DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072C8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072R8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072V8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) + +# ifdef CONFIG_ARCH_CHIP_STM32F091CB +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) + +# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 8 /* Eight USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# else +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# endif +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h b/arch/arm/include/stm32f0/irq.h similarity index 80% rename from arch/arm/include/stm32f0l0g0/stm32f0_irq.h rename to arch/arm/include/stm32f0/irq.h index 1d214b1569c1f..c142f9068bef7 100644 --- a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h +++ b/arch/arm/include/stm32f0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32f0_irq.h + * arch/arm/include/stm32f0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */ #define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ @@ -97,35 +118,8 @@ #define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */ #define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */ -#define STM32_IRQ_NEXTINTS (32) /* 32 external interrupts */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define STM32_IRQ_NEXTINTS (32) -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h deleted file mode 100644 index 11626cd2e83b3..0000000000000 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ /dev/null @@ -1,776 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) - -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 0 /* No I2S modules */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* One DAC channel */ -# define STM32_NCOMP 0 /* Two Analog Comparators */ -# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) - -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* Two USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 1 /* One DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072C8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072R8 -# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072V8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) - -# ifdef CONFIG_ARCH_CHIP_STM32F091CB -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) - -# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 8 /* Eight USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# else -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# endif -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) - -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, - * TIM14-17 */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 0 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 16-channels */ - -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071RB) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* Two LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ -# define STM32_NGTIM32 1 /* TIM2 */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ -# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ - /* Two LPUART */ -# define STM32_NCAN 1 /* One FDCAN controller */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 1 /* One USB full-speed controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 3 /* Three Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L073XX - With LCD - * STM32L072XX - No LCD - * STM32L071XX - Access line, no LCD - * - * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM - * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM - * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM - * - * STM32L0XXCX - 48-pins - * STM32L0XXRX - 64-pins - * STM32L0XXVX - 100-pins - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071K8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ - defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L072VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L073VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ -#elif defined(CONFIG_ARCH_CHIP_STM32C051XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 1 /* One FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#else -# error "Unsupported STM32 Cortex M0 chip" -#endif - -/* NVIC priority levels *****************************************************/ - -/* Each priority field holds a priority value, 0-31. The lower the value, - * the greater the priority of the corresponding interrupt. The processor - * implements only bits[7:6] of each field, bits[5:0] read as zero and - * ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/irq.h b/arch/arm/include/stm32f0l0g0/irq.h deleted file mode 100644 index 450d793e120de..0000000000000 --- a/arch/arm/include/stm32f0l0g0/irq.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* Common Processor Exceptions (vectors 0-15) */ - -#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ - /* Vectors 4-10: Reserved */ -#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ - /* Vector 12-13: Reserved */ -#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include MCU-specific external interrupt definitions */ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include -#else -# error Unrecognized STM32 Cortex M0 family -#endif - -#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */ diff --git a/arch/arm/include/stm32g0/chip.h b/arch/arm/include/stm32g0/chip.h new file mode 100644 index 0000000000000..4c92e149ced06 --- /dev/null +++ b/arch/arm/include/stm32g0/chip.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/include/stm32g0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) + +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, + * TIM14-17 */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 0 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 16-channels */ + +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071RB) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* Two LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ +# define STM32_NGTIM32 1 /* TIM2 */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ +# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ + /* Two LPUART */ +# define STM32_NCAN 1 /* One FDCAN controller */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 1 /* One USB full-speed controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 3 /* Three Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L073XX - With LCD + * STM32L072XX - No LCD + * STM32L071XX - Access line, no LCD + * + * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM + * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM + * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM + * + * STM32L0XXCX - 48-pins + * STM32L0XXRX - 64-pins + * STM32L0XXVX - 100-pins + */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32g0/irq.h similarity index 85% rename from arch/arm/include/stm32f0l0g0/stm32g0_irq.h rename to arch/arm/include/stm32g0/irq.h index ae5e5a29194dc..1edbcd2b85070 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32g0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32g0_irq.h + * arch/arm/include/stm32g0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32G0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ @@ -94,8 +115,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_COMP */ - #else # define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ #endif @@ -115,10 +134,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_DAC */ - -/* No STM32_IRQ_LPTIM1 */ - #else # define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ # define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */ @@ -128,8 +143,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_LPTIM2 */ - #else # define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */ #endif @@ -165,31 +178,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32G0_IRQ_H */ diff --git a/arch/arm/include/stm32l0/chip.h b/arch/arm/include/stm32l0/chip.h new file mode 100644 index 0000000000000..dcd8199454643 --- /dev/null +++ b/arch/arm/include/stm32l0/chip.h @@ -0,0 +1,371 @@ +/**************************************************************************** + * arch/arm/include/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32L071K8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ + defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L072VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L073VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h b/arch/arm/include/stm32l0/irq.h similarity index 76% rename from arch/arm/include/stm32f0l0g0/stm32l0_irq.h rename to arch/arm/include/stm32l0/irq.h index 166815ea7fa98..93fe2b0e049ee 100644 --- a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h +++ b/arch/arm/include/stm32l0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32l0_irq.h + * arch/arm/include/stm32l0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,34 +20,54 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions - * can be found in nuttx/arch/arm/include/stm32f0l0g0/irq.h +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */ @@ -92,31 +112,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L0_IRQ_H */ diff --git a/arch/arm/src/stm32c0/CMakeLists.txt b/arch/arm/src/stm32c0/CMakeLists.txt new file mode 100644 index 0000000000000..c795baf9c0418 --- /dev/null +++ b/arch/arm/src/stm32c0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32c0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32c0/Kconfig b/arch/arm/src/stm32c0/Kconfig new file mode 100644 index 0000000000000..9b90ec49a16be --- /dev/null +++ b/arch/arm/src/stm32c0/Kconfig @@ -0,0 +1,283 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 C0 configuration" + +if ARCH_CHIP_STM32C0 + +choice + prompt "ST STM32C0 Chip Selection" + default ARCH_CHIP_STM32C071RB + depends on ARCH_CHIP_STM32C0 + +config ARCH_CHIP_STM32C051D8 + bool "STM32C051D8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051F6 + bool "STM32C051F6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051F8 + bool "STM32C051F8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051G6 + bool "STM32C051G6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051G8 + bool "STM32C051G8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051K6 + bool "STM32C051K6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051K8 + bool "STM32C051K8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051C6 + bool "STM32C051C6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051C8 + bool "STM32C051C8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071F8 + bool "STM32C071F8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071FB + bool "STM32C071FB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071G8 + bool "STM32C071G8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071GB + bool "STM32C071GB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071K8 + bool "STM32C071K8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071KB + bool "STM32C071KB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071C8 + bool "STM32C071C8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071CB + bool "STM32C071CB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071R8 + bool "STM32C071R8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071RB + bool "STM32C071RB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FB + bool "STM32C091FB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FC + bool "STM32C091FC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091EC + bool "STM32C091EC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091GB + bool "STM32C091GB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091GC + bool "STM32C091GC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091KB + bool "STM32C091KB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091KC + bool "STM32C091KC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091CB + bool "STM32C091CB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091CC + bool "STM32C091CC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091RB + bool "STM32C091RB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091RC + bool "STM32C091RC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092FB + bool "STM32C092FB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092FC + bool "STM32C092FC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092EC + bool "STM32C092EC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092GB + bool "STM32C092GB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092GC + bool "STM32C092GC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092KB + bool "STM32C092KB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092KC + bool "STM32C092KC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092CB + bool "STM32C092CB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092CC + bool "STM32C092CC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092RB + bool "STM32C092RB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092RC + bool "STM32C092RC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +endchoice + +endif + +config STM32_STM32C0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select ARCH_HAVE_PROGMEM + +config ARCH_CHIP_STM32C051XX + bool + select STM32_STM32C0 + +config ARCH_CHIP_STM32C071XX + bool + select STM32_STM32C0 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32C091XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM15 + +config ARCH_CHIP_STM32C092XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_FDCAN1 diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32c0/Make.defs similarity index 71% rename from arch/arm/src/stm32f0l0g0/Make.defs rename to arch/arm/src/stm32c0/Make.defs index 9b02c48921085..f7f9d727e6765 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32c0/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32f0l0g0/Make.defs +# arch/arm/src/stm32c0/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,24 +22,7 @@ include armv6-m/Make.defs -CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_rcc.c stm32_lsi.c - -ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) -CHIP_CSRCS += stm32_lse.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32_timerisr.c -endif +CHIP_CSRCS = stm32_rcc.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c diff --git a/arch/arm/src/stm32f0l0g0/chip.h b/arch/arm/src/stm32c0/chip.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/chip.h rename to arch/arm/src/stm32c0/chip.h index b496c6b202067..e65e4fc23f633 100644 --- a/arch/arm/src/stm32f0l0g0/chip.h +++ b/arch/arm/src/stm32c0/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/chip.h + * arch/arm/src/stm32c0/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H +#ifndef __ARCH_ARM_SRC_STM32C0_CHIP_H +#define __ARCH_ARM_SRC_STM32C0_CHIP_H /**************************************************************************** * Included Files @@ -32,9 +32,7 @@ /* Include the chip capabilities file */ -#include - -#define ARMV6M_PERIPHERAL_INTERRUPTS 32 +#include /* Include the memory map file. * Other chip hardware files should then include this file for the proper @@ -43,4 +41,4 @@ #include "hardware/stm32_memorymap.h" -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_CHIP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..455026d894141 --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..4d31e5c8a3ed0 --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h similarity index 89% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h rename to arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h index 1d91dc308bca1..1e03567fdd5f7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h + * arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ #define DMAMAP_DMA1_REQGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) #define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h rename to arch/arm/src/stm32c0/hardware/stm32c0_exti.h index 800a7a4faff96..666034a22cd35 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h + * arch/arm/src/stm32c0/hardware/stm32c0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h rename to arch/arm/src/stm32c0/hardware/stm32c0_flash.h index dfcdb1e5e133f..0fb3d2d084424 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h + * arch/arm/src/stm32c0/hardware/stm32c0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H /**************************************************************************** * Included Files @@ -202,4 +202,4 @@ #define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force boot from user area */ /* Bits 20-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h index c847f7ca05088..212d3f4a95cc8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h + * arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -115,4 +115,4 @@ #define STM32_SYSMEM_UID 0x1fff7550 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h index 4e10209f8a623..5d8805236ed52 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h + * arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,8 +32,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H /**************************************************************************** * Included Files @@ -351,4 +351,4 @@ #define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4) #define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pwr.h index 7c16d410baf47..0b6db18987c6c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h + * arch/arm/src/stm32c0/hardware/stm32c0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H /**************************************************************************** * Included Files @@ -150,4 +150,4 @@ #define PWR_BKPR_MASK (0xffff) /* Bits 0-16: Backup bitfield */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h rename to arch/arm/src/stm32c0/hardware/stm32c0_rcc.h index 10119b6e62dad..9784111a9b184 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h + * arch/arm/src/stm32c0/hardware/stm32c0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -394,4 +394,4 @@ #define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32.h b/arch/arm/src/stm32c0/stm32.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/stm32.h rename to arch/arm/src/stm32c0/stm32.h index c43d655c8b9bf..7d1c5ae34764f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32.h +++ b/arch/arm/src/stm32c0/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32.h + * arch/arm/src/stm32c0/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H +#ifndef __ARCH_ARM_SRC_STM32C0_STM32_H +#define __ARCH_ARM_SRC_STM32C0_STM32_H /**************************************************************************** * Included Files @@ -51,4 +51,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_STM32_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32c0/stm32_rcc.c similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_rcc.c rename to arch/arm/src/stm32c0/stm32_rcc.c index b227f714756c2..4c847902807db 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c +++ b/arch/arm/src/stm32c0/stm32_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.c + * arch/arm/src/stm32c0/stm32_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "hardware/stm32_flash.h" #include "stm32_rcc.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions @@ -70,17 +70,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "stm32f0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "stm32l0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "stm32g0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "stm32c0_rcc.c" -#else -# error "Unsupported STM32F0/L0 RCC" -#endif +#include "stm32c0_rcc.c" /**************************************************************************** * Public Functions diff --git a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32c0_rcc.c rename to arch/arm/src/stm32c0/stm32c0_rcc.c index ec620d4953825..ffa41fc0c6dea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32c0_rcc.c + * arch/arm/src/stm32c0/stm32c0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0/CMakeLists.txt b/arch/arm/src/stm32f0/CMakeLists.txt new file mode 100644 index 0000000000000..1d1fbc82d053d --- /dev/null +++ b/arch/arm/src/stm32f0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32f0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig new file mode 100644 index 0000000000000..3d54d04029757 --- /dev/null +++ b/arch/arm/src/stm32f0/Kconfig @@ -0,0 +1,555 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F0 configuration" + +if ARCH_CHIP_STM32F0 + +choice + prompt "ST STM32F0 Chip Selection" + default ARCH_CHIP_STM32F051R8 + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C6 + bool "STM32F030C6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C8 + bool "STM32F030C8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030CC + bool "STM32F030CC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030F4 + bool "STM32F030F4" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030K6 + bool "STM32F030K6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030R8 + bool "STM32F030R8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030RC + bool "STM32F030RC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C4 + bool "STM32F031C4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C6 + bool "STM32F031C6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031E6 + bool "STM32F031E6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F4 + bool "STM32F031F4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F6 + bool "STM32F031F6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G4 + bool "STM32F031G4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G6 + bool "STM32F031G6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K4 + bool "STM32F031K4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K6 + bool "STM32F031K6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038C6 + bool "STM32F038C6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038E6 + bool "STM32F038E6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038F6 + bool "STM32F038F6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038G6 + bool "STM32F038G6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038K6 + bool "STM32F038K6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C4 + bool "STM32F042C4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C6 + bool "STM32F042C6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F4 + bool "STM32F042F4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F6 + bool "STM32F042F6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G4 + bool "STM32F042G4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G6 + bool "STM32F042G6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K4 + bool "STM32F042K4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K6 + bool "STM32F042K6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042T6 + bool "STM32F042T6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048C6 + bool "STM32F048C6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048G6 + bool "STM32F048G6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048T6 + bool "STM32F048T6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C4 + bool "STM32F051C4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C6 + bool "STM32F051C6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C8 + bool "STM32F051C8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K4 + bool "STM32F051K4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K6 + bool "STM32F051K6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K8 + bool "STM32F051K8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R4 + bool "STM32F051R4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R6 + bool "STM32F051R6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R8 + bool "STM32F051R8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051T8 + bool "STM32F051T8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058C8 + bool "STM32F058C8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058R8 + bool "STM32F058R8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058T8 + bool "STM32F058T8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070C6 + bool "STM32F070C6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070CB + bool "STM32F070CB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070F6 + bool "STM32F070F6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070RB + bool "STM32F070RB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071C8 + bool "STM32F071C8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071CB + bool "STM32F071CB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071RB + bool "STM32F071RB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071V8 + bool "STM32F071V8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071VB + bool "STM32F071VB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072C8 + bool "STM32F072C8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072CB + bool "STM32F072CB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072R8 + bool "STM32F072R8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072RB + bool "STM32F072RB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072V8 + bool "STM32F072V8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072VB + bool "STM32F072VB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078CB + bool "STM32F078CB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078RB + bool "STM32F078RB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078VB + bool "STM32F078VB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CB + bool "STM32F091CB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CC + bool "STM32F091CC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RB + bool "STM32F091RB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RC + bool "STM32F091RC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VB + bool "STM32F091VB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VC + bool "STM32F091VC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098CC + bool "STM32F098CC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098RC + bool "STM32F098RC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098VC + bool "STM32F098VC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +endchoice + +endif + +config STM32_STM32F0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_CAN_BXCAN_M0_V1 + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config STM32_STM32F03X + bool + default n + select STM32_STM32F0 + +config STM32_STM32F04X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + +config STM32_STM32F05X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_DMA2 + +config STM32_STM32F07X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32_STM32F09X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32F0_VALUELINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + +config STM32F0_ACCESSLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_LOWVOLTLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_USBLINE + bool + default n + select STM32_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + select STM32_HAVE_USBDEV diff --git a/arch/arm/src/stm32f0/Make.defs b/arch/arm/src/stm32f0/Make.defs new file mode 100644 index 0000000000000..54436033fa267 --- /dev/null +++ b/arch/arm/src/stm32f0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32f0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h b/arch/arm/src/stm32f0/chip.h similarity index 69% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h rename to arch/arm/src/stm32f0/chip.h index f8966bbbcb362..3e5f5a1103c59 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f0/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h + * arch/arm/src/stm32f0/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,24 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_H +#define __ARCH_ARM_SRC_STM32F0_CHIP_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_syscfg.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_syscfg.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_syscfg.h" -#else -# error "Unsupported STM32 M0 SYSCFG" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */ +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..b11687cda1f94 --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_memorymap.h" +#elif defined(CONFIG_STM32_STM32F05X) || defined(CONFIG_STM32_STM32F07X) || \ + defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f05xf07xf09x_memorymap.h" +#else +# error "Unsupported STM32F0 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..847044b52b358 --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h @@ -0,0 +1,29 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F05X) +# include "hardware/stm32f05x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F07X) +# include "hardware/stm32f07x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f09x_pinmap.h" +#else +# error "Unsupported STM32F0 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h index b88eb339fe7ca..c993ab035914f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -141,4 +141,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h index 1c9bbb9622c17..6a8d81bf82d35 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ #define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) #define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h index 81964a46b93cc..436a483058a33 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H /**************************************************************************** * Included Files @@ -119,4 +119,4 @@ #define GPIO_I2C2_SCL_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN10) #define GPIO_I2C2_SDA_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h index 384e67bdeeaba..b8fa02c00a129 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -145,4 +145,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h index 2210e67af117a..24255d24048c4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H /**************************************************************************** * Included Files @@ -385,4 +385,4 @@ #define GPIO_USB_NOE_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h index b2b2b44cd9b17..bfeb238a732a5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H /**************************************************************************** * Included Files @@ -414,4 +414,4 @@ #define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13) #define GPIO_USART8_CK_RST_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h rename to arch/arm/src/stm32f0/hardware/stm32f0_exti.h index ec2f58f8a186c..d006ddb3ff11f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h + * arch/arm/src/stm32f0/hardware/stm32f0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H /**************************************************************************** * Included Files @@ -114,4 +114,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h rename to arch/arm/src/stm32f0/hardware/stm32f0_flash.h index fde24890c4f05..46c87416a0afa 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h + * arch/arm/src/stm32f0/hardware/stm32f0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H /**************************************************************************** * Included Files @@ -94,4 +94,4 @@ #define FLASH_OBR_ /* To be provided */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h rename to arch/arm/src/stm32f0/hardware/stm32f0_pwr.h index 64a693f752288..9b981257bc55f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h + * arch/arm/src/stm32f0/hardware/stm32f0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H /**************************************************************************** * Included Files @@ -85,4 +85,4 @@ #define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ #define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0/hardware/stm32f0_rcc.h index 63c213b1531e5..3bd0a3dab1763 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0/hardware/stm32f0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h rename to arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h index 63f38bf07caed..f7822582a674a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h + * arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H /**************************************************************************** * Included Files @@ -378,4 +378,4 @@ #define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ #define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0/stm32.h similarity index 70% rename from arch/arm/src/stm32f0l0g0/stm32_pwr.c rename to arch/arm/src/stm32f0/stm32.h index 70c8df356ab39..fabdd48a6255b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ b/arch/arm/src/stm32f0/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.c + * arch/arm/src/stm32f0/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,23 +20,35 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_STM32F0_STM32_H +#define __ARCH_ARM_SRC_STM32F0_STM32_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" +#include +#include +#include -/* This file is only a thin shell that includes the proper PWR implementation - * according to the selected MCU family. - */ +#include "arm_internal.h" -#if defined(CONFIG_STM32_STM32G0) -# include "stm32g0_pwr.c" -#elif defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) -# include "stm32f0l0_pwr.c" -#endif +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" /**************************************************************************** - * Public Functions + * Pre-processor Definitions ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F0_STM32_H */ diff --git a/arch/arm/src/stm32f0/stm32_rcc.c b/arch/arm/src/stm32f0/stm32_rcc.c new file mode 100644 index 0000000000000..d343b49ad173e --- /dev/null +++ b/arch/arm/src/stm32f0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0/stm32f0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32f0_rcc.c rename to arch/arm/src/stm32f0/stm32f0_rcc.c index 018b81897df45..b5106208ca9e2 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0/stm32f0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0_rcc.c + * arch/arm/src/stm32f0/stm32f0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt deleted file mode 100644 index 7eca474eaf9ac..0000000000000 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32f0l0g0/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_start.c - stm32_irq.c - stm32_lowputc.c - stm32_lsi.c - stm32_rcc.c) - -if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) - list(APPEND SRCS stm32_lse.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(NOT CONFIG_SCHED_TICKLESS) - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig deleted file mode 100644 index 5b6849a034ce1..0000000000000 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ /dev/null @@ -1,1415 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32F0/L0/G0 Configuration Options" - -config STM32_F0L0G0_PERIPHERALS - bool - default y - depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 - select STM32_HAVE_COMP - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - -choice - prompt "ST STM32F0/L0/G0 Chip Selection" - default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 - default ARCH_CHIP_STM32L073RZ if ARCH_CHIP_STM32L0 - default ARCH_CHIP_STM32G071RB if ARCH_CHIP_STM32G0 - default ARCH_CHIP_STM32C071RB if ARCH_CHIP_STM32C0 - depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 - -config ARCH_CHIP_STM32F030C6 - bool "STM32F030C6" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030C8 - bool "STM32F030C8" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030CC - bool "STM32F030CC" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030F4 - bool "STM32F030F4" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030K6 - bool "STM32F030K6" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030R8 - bool "STM32F030R8" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030RC - bool "STM32F030RC" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C4 - bool "STM32F031C4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C6 - bool "STM32F031C6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031E6 - bool "STM32F031E6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F4 - bool "STM32F031F4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F6 - bool "STM32F031F6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G4 - bool "STM32F031G4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G6 - bool "STM32F031G6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K4 - bool "STM32F031K4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K6 - bool "STM32F031K6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038C6 - bool "STM32F038C6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038E6 - bool "STM32F038E6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038F6 - bool "STM32F038F6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038G6 - bool "STM32F038G6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038K6 - bool "STM32F038K6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C4 - bool "STM32F042C4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C6 - bool "STM32F042C6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F4 - bool "STM32F042F4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F6 - bool "STM32F042F6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G4 - bool "STM32F042G4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G6 - bool "STM32F042G6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K4 - bool "STM32F042K4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K6 - bool "STM32F042K6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042T6 - bool "STM32F042T6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048C6 - bool "STM32F048C6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048G6 - bool "STM32F048G6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048T6 - bool "STM32F048T6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C4 - bool "STM32F051C4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C6 - bool "STM32F051C6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C8 - bool "STM32F051C8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K4 - bool "STM32F051K4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K6 - bool "STM32F051K6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K8 - bool "STM32F051K8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R4 - bool "STM32F051R4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R6 - bool "STM32F051R6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R8 - bool "STM32F051R8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051T8 - bool "STM32F051T8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058C8 - bool "STM32F058C8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058R8 - bool "STM32F058R8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058T8 - bool "STM32F058T8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070C6 - bool "STM32F070C6" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070CB - bool "STM32F070CB" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070F6 - bool "STM32F070F6" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070RB - bool "STM32F070RB" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071C8 - bool "STM32F071C8" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071CB - bool "STM32F071CB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071RB - bool "STM32F071RB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071V8 - bool "STM32F071V8" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071VB - bool "STM32F071VB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072C8 - bool "STM32F072C8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072CB - bool "STM32F072CB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072R8 - bool "STM32F072R8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072RB - bool "STM32F072RB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072V8 - bool "STM32F072V8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072VB - bool "STM32F072VB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078CB - bool "STM32F078CB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078RB - bool "STM32F078RB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078VB - bool "STM32F078VB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CB - bool "STM32F091CB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CC - bool "STM32F091CC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RB - bool "STM32F091RB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RC - bool "STM32F091RC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VB - bool "STM32F091VB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VC - bool "STM32F091VC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098CC - bool "STM32F098CC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098RC - bool "STM32F098RC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098VC - bool "STM32F098VC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32G070CB - bool "STM32G070CB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070KB - bool "STM32G070KB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070RB - bool "STM32G070RB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071EB - bool "STM32G071EB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8 - bool "STM32G071G8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GB - bool "STM32G071GB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8XN - bool "STM32G071G8XN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GBXN - bool "STM32G071GBXN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8 - bool "STM32G071K8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KB - bool "STM32G071KB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8XN - bool "STM32G071K8XN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KBXN - bool "STM32G071KBXN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071C8 - bool "STM32G071C8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071CB - bool "STM32G071CB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071R8 - bool "STM32G071R8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071RB - bool "STM32G071RB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32L053C8 - bool "STM32L053C8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L053R8 - bool "STM32L053R8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071K8 - bool "STM32L071K8" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KB - bool "STM32L071KB" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KZ - bool "STM32L071KZ" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071C8 - bool "STM32L071C8" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CB - bool "STM32L071CB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CZ - bool "STM32L071CZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071V8 - bool "STM32L071V8" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VB - bool "STM32L071VB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VZ - bool "STM32L071VZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RB - bool "STM32L071RB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RZ - bool "STM32L071RZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072V8 - bool "STM32L072V8" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VB - bool "STM32L072VB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VZ - bool "STM32L072VZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KB - bool "STM32L072KB" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KZ - bool "STM32L072KZ" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CB - bool "STM32L072CB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CZ - bool "STM32L072CZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RB - bool "STM32L072RB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RZ - bool "STM32L072RZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073V8 - bool "STM32L073V8" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VB - bool "STM32L073VB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VZ - bool "STM32L073VZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CB - bool "STM32L073CB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CZ - bool "STM32L073CZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RB - bool "STM32L073RB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RZ - bool "STM32L073RZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32C051D8 - bool "STM32C051D8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051F6 - bool "STM32C051F6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051F8 - bool "STM32C051F8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051G6 - bool "STM32C051G6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051G8 - bool "STM32C051G8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051K6 - bool "STM32C051K6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051K8 - bool "STM32C051K8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051C6 - bool "STM32C051C6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051C8 - bool "STM32C051C8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071F8 - bool "STM32C071F8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071FB - bool "STM32C071FB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071G8 - bool "STM32C071G8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071GB - bool "STM32C071GB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071K8 - bool "STM32C071K8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071KB - bool "STM32C071KB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071C8 - bool "STM32C071C8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071CB - bool "STM32C071CB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071R8 - bool "STM32C071R8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071RB - bool "STM32C071RB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FB - bool "STM32C091FB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FC - bool "STM32C091FC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091EC - bool "STM32C091EC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091GB - bool "STM32C091GB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091GC - bool "STM32C091GC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091KB - bool "STM32C091KB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091KC - bool "STM32C091KC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091CB - bool "STM32C091CB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091CC - bool "STM32C091CC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091RB - bool "STM32C091RB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091RC - bool "STM32C091RC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092FB - bool "STM32C092FB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092FC - bool "STM32C092FC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092EC - bool "STM32C092EC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092GB - bool "STM32C092GB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092GC - bool "STM32C092GC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092KB - bool "STM32C092KB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092KC - bool "STM32C092KC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092CB - bool "STM32C092CB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092CC - bool "STM32C092CC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092RB - bool "STM32C092RB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092RC - bool "STM32C092RC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -endchoice # ST STM32F0/L0/G0/C0 Chip Selection - -# Flash configurations - -config STM32_FLASH_OVERRIDE - bool "Override Flash Designator" - default n - -config STM32_STM32F0 - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_EXTI_V1 - -config STM32_STM32G0 - bool - default n - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_I2C2 - select ARCH_HAVE_PROGMEM - -config STM32_STM32L0 - bool - default n - select STM32_ENERGYLITE - select STM32_HAVE_LCD - select STM32_HAVE_VREFINT - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_EXTI_V1 - -config STM32_STM32C0 - bool - default n - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_DMAMUX - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select ARCH_HAVE_PROGMEM - -config STM32_STM32F03X - bool - default n - select STM32_STM32F0 - -config STM32_STM32F04X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - -config STM32_STM32F05X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_DMA2 - -config STM32_STM32F07X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - select STM32_HAVE_DMA2 - -config STM32_STM32F09X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - select STM32_HAVE_DMA2 - -config STM32_STM32G030 - bool - default n - select STM32_STM32G0 - select STM32_STM32G03X - -config STM32_STM32G031 - bool - default n - select STM32_STM32G0 - select STM32_STM32G03X - select STM32_HAVE_LPUART1 - -config STM32_STM32G03X - bool - default n - -config STM32_STM32G041 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_LPUART1 - -config STM32_STM32G050 - bool - default n - select STM32_STM32G0 - select STM32_STM32G05X - -config STM32_STM32G051 - bool - default n - select STM32_STM32G0 - select STM32_STM32G05X - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM15 - select STM32_HAVE_LPUART1 - -config STM32_STM32G05X - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - -config STM32_STM32G061 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_LPUART1 - -config STM32_STM32G070 - bool - default n - select STM32_STM32G0 - select STM32_STM32G07X - -config STM32_STM32G071 - bool - default n - select STM32_STM32G0 - select STM32_STM32G07X - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_CEC - select STM32_HAVE_LPUART1 - -config STM32_STM32G07X - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - -config STM32_STM32G081 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_CEC - select STM32_HAVE_LPUART1 - -config STM32_STM32G0B0 - bool - default n - select STM32_STM32G0 - select STM32_STM32G0BX - -config STM32_STM32G0B1 - bool - default n - select STM32_STM32G0 - select STM32_STM32G0BX - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_CEC - -config STM32_STM32G0BX - bool - default n - select STM32_HAVE_DMA2 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_USART6 - select STM32_HAVE_LPUART1 - select STM32_HAVE_LPUART2 - select STM32_HAVE_CRS - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S2 - select STM32_HAVE_USBDEV - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_HSI48 - -config STM32_STM32G0C1 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_DMA2 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_USART6 - select STM32_HAVE_CRS - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S2 - select STM32_HAVE_LPUART2 - select STM32_HAVE_USBDEV - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_CEC - select STM32_HAVE_HSI48 - -config STM32_ACCESSLINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - -config STM32_LOWVOLTLINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - -config STM32_USBLINE - bool - default n - select STM32_HAVE_HSI48 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32L053XX - bool - select STM32_STM32L0 - -config ARCH_CHIP_STM32L071XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - -config ARCH_CHIP_STM32L072XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_I2C2 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32L073XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32C051XX - bool - select STM32_STM32C0 - -config ARCH_CHIP_STM32C071XX - bool - select STM32_STM32C0 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32C091XX - bool - select STM32_STM32C0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM15 - -config ARCH_CHIP_STM32C092XX - bool - select STM32_STM32C0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_FDCAN1 - -choice - prompt "SysTick clock source" - default STM32_SYSTICK_CORECLK - -config STM32_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config STM32_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice # SysTick clock source diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h deleted file mode 100644 index d49e402abbac0..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* AES register offsets *****************************************************/ - -#define STM32_AES_CR_OFFSET 0x0000 /* Control Register */ -#define STM32_AES_SR_OFFSET 0x0004 /* Status Register */ -#define STM32_AES_DINR_OFFSET 0x0008 /* Data Input Register */ -#define STM32_AES_DOUTR_OFFSET 0x000C /* Data Output Register */ -#define STM32_AES_KEYR0_OFFSET 0x0010 /* AES Key Register 0 */ -#define STM32_AES_KEYR1_OFFSET 0x0014 /* AES Key Register 1 */ -#define STM32_AES_KEYR2_OFFSET 0x0018 /* AES Key Register 2 */ -#define STM32_AES_KEYR3_OFFSET 0x001C /* AES Key Register 3 */ -#define STM32_AES_IVR0_OFFSET 0x0020 /* AES Initialization Vector Register 0 */ -#define STM32_AES_IVR1_OFFSET 0x0024 /* AES Initialization Vector Register 1 */ -#define STM32_AES_IVR2_OFFSET 0x0028 /* AES Initialization Vector Register 2 */ -#define STM32_AES_IVR3_OFFSET 0x002C /* AES Initialization Vector Register 3 */ - -/* AES register addresses ***************************************************/ - -#define STM32_AES_CR (STM32_AES_BASE + STM32_AES_CR_OFFSET) -#define STM32_AES_SR (STM32_AES_BASE + STM32_AES_SR_OFFSET) -#define STM32_AES_DINR (STM32_AES_BASE + STM32_AES_DINR_OFFSET) -#define STM32_AES_DOUTR (STM32_AES_BASE + STM32_AES_DOUTR_OFFSET) -#define STM32_AES_KEYR0 (STM32_AES_BASE + STM32_AES_KEYR0_OFFSET) -#define STM32_AES_KEYR1 (STM32_AES_BASE + STM32_AES_KEYR1_OFFSET) -#define STM32_AES_KEYR2 (STM32_AES_BASE + STM32_AES_KEYR2_OFFSET) -#define STM32_AES_KEYR3 (STM32_AES_BASE + STM32_AES_KEYR3_OFFSET) -#define STM32_AES_IVR0 (STM32_AES_BASE + STM32_AES_IVR0_OFFSET) -#define STM32_AES_IVR1 (STM32_AES_BASE + STM32_AES_IVR1_OFFSET) -#define STM32_AES_IVR2 (STM32_AES_BASE + STM32_AES_IVR2_OFFSET) -#define STM32_AES_IVR3 (STM32_AES_BASE + STM32_AES_IVR3_OFFSET) - -/* AES register bit definitions *********************************************/ - -/* AES_CR register */ - -#define AES_CR_EN (1 << 0) /* AES Enable */ -#define AES_CR_DATATYPE (1 << 1) /* Data type selection */ -# define AES_CR_DATATYPE_LE (0x0 << 1) -# define AES_CR_DATATYPE_BE (0x2 << 1) - -#define AES_CR_MODE (1 << 3) /* AES Mode of operation */ -# define AES_CR_MODE_ENCRYPT (0x0 << 3) -# define AES_CR_MODE_KEYDERIV (0x1 << 3) -# define AES_CR_MODE_DECRYPT (0x2 << 3) -# define AES_CR_MODE_DECRYPT_KEYDERIV (0x3 << 3) - -#define AES_CR_CHMOD (1 << 5) /* AES Chaining Mode */ -# define AES_CR_CHMOD_ECB (0x0 << 5) -# define AES_CR_CHMOD_CBC (0x1 << 5) -# define AES_CR_CHMOD_CTR (0x2 << 5) - -#define AES_CR_CCFC (1 << 7) /* Computation Complete Flag Clear */ -#define AES_CR_ERRC (1 << 8) /* Error Clear */ -#define AES_CR_CCIE (1 << 9) /* Computation Complete Interrupt Enable */ -#define AES_CR_ERRIE (1 << 10) /* Error Interrupt Enable */ -#define AES_CR_DMAINEN (1 << 11) /* DMA Enable Input */ -#define AES_CR_DMAOUTEN (1 << 12) /* DMA Enable Output */ - -/* AES_SR register */ - -#define AES_SR_CCF (1 << 0) /* Computation Complete Flag */ -#define AES_SR_RDERR (1 << 1) /* Read Error Flag */ -#define AES_SR_WRERR (1 << 2) /* Write Error Flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h deleted file mode 100644 index 8aa180ded0e30..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_CRC_DR_OFFSET 0x0000 /* Data register */ -#define STM32_CRC_IDR_OFFSET 0x0004 /* Independent Data register */ -#define STM32_CRC_CR_OFFSET 0x0008 /* Control register */ -#define STM32_CRC_INIT_OFFSET 0x0010 /* Initial CRC value register */ -#define STM32_CRC_POL_OFFSET 0x0014 /* CRC polynomial register */ - -/* Register Addresses *******************************************************/ - -#define STM32_CRC_DR (STM32_CRC_BASE + STM32_CRC_DR_OFFSET) -#define STM32_CRC_IDR (STM32_CRC_BASE + STM32_CRC_IDR_OFFSET) -#define STM32_CRC_CR (STM32_CRC_BASE + STM32_CRC_CR_OFFSET) -#define STM32_CRC_INIT (STM32_CRC_BASE + STM32_CRC_INIT_OFFSET) -#define STM32_CRC_POL (STM32_CRC_BASE + STM32_CRC_POL_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* CRC independent data register */ - -#define CRC_IDR_MASK 0xff /* These bits as a temporary location for one byte, not affected by RESET bit of CR */ - -/* CRC control register */ - -#define CRC_CR_RESET (1 << 0) /* This bit reset the CRC calculation unit and load CRC_DR with value of CRC_INIT */ -#define CRC_CR_POLYSIZE_SHIFT 3 /* Bits 3-4: Polynomial size (for STM32F07x and STM32F09x) */ -#define CRC_CR_POLYSIZE_MASK (3 << CRC_CR_POLYSIZE_SHIFT) -# define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) /* 00: 32 bit polynomial */ -# define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) /* 01: 16 bit polynomial */ -# define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ -# define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) /* 10: 8 bit polynomial */ - -#define CRC_CR_REVIN_SHIFT 5 /* Bits 5-6: These bits control the reversal of the bit order of the input data */ -#define CRC_CR_REVIN_MASK (3 << CRC_CR_REVIN_SHIFT) -# define CRC_CR_REVIN_NONE (0 << CRC_CR_REVIN_SHIFT) /* 00: bit order is not affected */ -# define CRC_CR_REVIN_BYTE (1 << CRC_CR_REVIN_SHIFT) /* 01: reversal done by byte */ -# define CRC_CR_REVIN_HWORD (2 << CRC_CR_REVIN_SHIFT) /* 10: reversal done by half-word */ -# define CRC_CR_REVIN_WORD (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */ - -#define CRC_CR_REVOUT (1 << 7) /* This bit controls the reversal of the bit order of the output data */ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h deleted file mode 100644 index 00e007a49cdd8..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ - -/* Register Addresses *******************************************************/ - -#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) -#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) -#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) -#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* CRS control register */ - -#define CRS_CR_SYNCOKIE (1 << 0) /* Bit 0: SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE (1 << 1) /* Bit 1: SYNC warning interrupt enable */ -#define CRS_CR_ERRIE (1 << 2) /* Bit 2: Synchronization or Trimming error interrupt enabled */ -#define CRS_CR_ESYNCIE (1 << 3) /* Bit 3: Expected SYNC interrupt enable */ -#define CRS_CR_CEN (1 << 5) /* Bit 5: Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN (1 << 6) /* Bit 6: Automatic trimming enabled */ -#define CRS_CR_SWSYNC (1 << 7) /* Bit 7: Generate software SYNC event */ -#define CRS_CR_TRIM_SHIFT 8 /* Bits 8-13: HSI48 oscillator smooth trimming */ -#define CRS_CR_TRIM_MASK (0x3f << CRS_CR_TRIM_SHIFT) - -/* CRS configuration register */ - -#define CRS_CFGR_RELOAD_SHIFT 0 /* Bits 0-15: Counter reload value */ -#define CRS_CFGR_RELOAD_MASK (0xffff << CRS_CFGR_RELOAD_SHIFT) -#define CRS_CFGR_FELIM_SHIFT 16 /* Bits 16-23: Frequency error limit */ -#define CRS_CFGR_FELIM_MASK (0xff << CRS_CFGR_FELIM_SHIFT) -#define CRS_CFGR_SYNCDIV_SHIFT 24 /* Bits 24-26: SYNC divider */ -#define CRS_CFGR_SYNCDIV_MASK (7 << CRS_CFGR_SYNCDIV_SHIFT) -# define CRS_CFGR_SYNCDIV_d1 (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */ -# define CRS_CFGR_SYNCDIV_d2 (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */ -# define CRS_CFGR_SYNCDIV_d4 (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */ -# define CRS_CFGR_SYNCDIV_d8 (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */ -# define CRS_CFGR_SYNCDIV_d16 (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */ -# define CRS_CFGR_SYNCDIV_d32 (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */ -# define CRS_CFGR_SYNCDIV_d64 (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */ -# define CRS_CFGR_SYNCDIV_d128 (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */ - -#define CRS_CFGR_SYNCSRC_SHIFT 28 /* Bits 28-29: SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_MASK (3 << CRS_CFGR_SYNCSRC_SHIFT) -# define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */ -# define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */ -# define CRS_CFGR_SYNCSRC_USBSOF (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */ - -#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */ - -/* CRS interrupt and status register */ - -#define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */ -#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */ -#define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */ -#define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */ -#define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */ -#define CRS_ISR_TRIMOVF (1 << 10) /* Bit 10: Trimming overflow or underflow */ -#define CRS_ISR_FEDIR (1 << 15) /* Bit 15: Frequency error direction */ -#define CRS_ISR_FECAP_SHIFT 16 /* Bits 16-31: Frequency error capture */ -#define CRS_ISR_FECAP_MASK (0xffff << CRS_ISR_FECAP_SHIFT) - -/* CRS interrupt flag clear register */ - -#define CRS_ICR_SYNCOKC (1 << 0) /* Bit 0: SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC (1 << 1) /* Bit 1: SYNC warning clear flag */ -#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ -#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h deleted file mode 100644 index 4c77ee8a1d1d7..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_HAVE_IP_USART_M0_V1) && \ - defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V1) -# include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_USART_M0_V1) && \ - defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V2) -# include "hardware/stm32_uart_v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_USART_M3M4_V2) -# error "Legacy STM32 USART must include a legacy family hardware header" -#else -# error "Unsupported STM32 F0/L0/G0/C0 USART" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h deleted file mode 100644 index 41bc90b3ae54f..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupot and status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_USART5_CR1 (STM32_USART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART5_CR2 (STM32_USART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART5_CR3 (STM32_USART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART5_BRR (STM32_USART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART5_GTPR (STM32_USART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART5_RTOR (STM32_USART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART5_RQR (STM32_USART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART5_ISR (STM32_USART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART5_ICR (STM32_USART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART5_RDR (STM32_USART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART5_TDR (STM32_USART5_BASE + STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode*/ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) - -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) - -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 12: word length */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE | USART_CR1_RXNEIE | \ - USART_CR1_TCIE | USART_CR1_TXEIE | \ - USART_CR1_PEIE | USART_CR1_CMIE| \ - USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ - -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */ - -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */ -#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */ -#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */ -#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ - -#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ -#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 17-19: Smart card auto retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */ -#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */ -#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send Break */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt and Status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 9: CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 10: Receiver timeout Flag */ -#define USART_ISR_EOBF (1 << 12) /* Bit 11: End of block Flag */ -#define USART_ISR_ABRE (1 << 13) /* Bit 12: Auto baud rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 14: Auto baud rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 15: Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 16: Character match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 17: Send break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 18: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 19: Wakeup from Stop mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ - -/* ICR */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -/* Receive Data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_RDR_MASK (0xff << USART_RDR_SHIFT) - -/* Transmit Data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_TDR_MASK (0xff << USART_TDR_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h deleted file mode 100644 index 82dbcfdcc2f70..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_USART4_CR1 (STM32_USART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART4_CR2 (STM32_USART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART4_CR3 (STM32_USART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART4_BRR (STM32_USART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_RTOR (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART4_RQR (STM32_USART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART4_GTPR (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART4_ISR (STM32_USART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART4_ICR (STM32_USART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART4_RDR (STM32_USART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART4_TDR (STM32_USART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART4_PRESC (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in low-power mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length, bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) ((uint32_t)(n) << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) ((uint32_t)(n) << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length, bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ -#define USART_CR2_DISNSS (1 << 3) /* Bit 3: Ignore NSS pin input */ -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-27: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4L_SHIFT) -# define USART_CR2_ADD4L(n) ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4H_SHIFT) -# define USART_CR2_ADD4H(n) ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) -# define USART_CR2_ADD8(n) ((uint32_t)(n) << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ -#define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */ -# define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */ -# define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */ -# define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */ -# define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */ -# define USART_CR3_RXFTCFG_FULL (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */ - -#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 29-31: TXFIFO threshold configuration */ -#define USART_CR3_TXFTCFG_MASK (7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG(n) ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */ -# define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */ -# define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */ -# define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */ -# define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */ -# define USART_CR3_TXFTCFG_EMPY (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -# define USART_BRR(n) ((uint32_t)(n) << USART_BRR_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) ((uint32_t)(n) << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) ((uint32_t)(n) << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) ((uint32_t)(n) << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NE (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from low-power mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23: TXFIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24: RXFIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25: Transmission complete before guard time flag */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26: RXFIFO threshold flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27: TXFIFO threshold flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5: TXFIFO empty clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7: Transmission complete before Guard time clear flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13:SPI slave underrun clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */ - -#define USART_ICR_ALLBITS (0x00123b7f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 0-8: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 0-8: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Prescaler register */ - -#define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ -#define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) -# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ -# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ -# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ -# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ -# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ -# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ -# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ -# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ -# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ -# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ -# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ -# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h deleted file mode 100644 index 54c6a345b3aa6..0000000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ - -#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ - -/* Register Addresses *******************************************************/ - -#define STM32_IWDG_KR (STM32_IWDG_BASE + STM32_IWDG_KR_OFFSET) -#define STM32_IWDG_PR (STM32_IWDG_BASE + STM32_IWDG_PR_OFFSET) -#define STM32_IWDG_RLR (STM32_IWDG_BASE + STM32_IWDG_RLR_OFFSET) -#define STM32_IWDG_SR (STM32_IWDG_BASE + STM32_IWDG_SR_OFFSET) -#define STM32_IWDG_WINR (STM32_IWDG_BASE + STM32_IWDG_WINR_OFFSET) - -#define STM32_WWDG_CR (STM32_WWDG_BASE + STM32_WWDG_CR_OFFSET) -#define STM32_WWDG_CFR (STM32_WWDG_BASE + STM32_WWDG_CFR_OFFSET) -#define STM32_WWDG_SR (STM32_WWDG_BASE + STM32_WWDG_SR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Key register (32-bit) */ - -#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */ -#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT) - -#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */ -#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */ -#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */ -#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */ - -/* Prescaler register (32-bit) */ - -#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */ -#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT) -# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */ -# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */ -# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */ -# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */ -# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */ -# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */ -# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */ - -/* Reload register (32-bit) */ - -#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */ -#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT) - -#define IWDG_RLR_MAX (0xfff) - -/* Status register (32-bit) */ - -#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */ -#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */ -#define IWDG_SR_WVU (1 << 2) /* Bit 2: Watchdog counter window value update */ - -/* Window register (32-bit) */ - -#define IWDG_WINR_SHIFT (0) -#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT) - -/* Control Register (32-bit) */ - -#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */ -#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT) -# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT) -#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */ - -/* Configuration register (32-bit) */ - -#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */ -#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT) -#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */ -#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT) -# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */ -# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */ -# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */ -# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */ - -#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */ - -/* Status register (32-bit) */ - -#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_crypto.c b/arch/arm/src/stm32f0l0g0/stm32_crypto.c deleted file mode 100644 index 64b4b99c4f813..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_crypto.c +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_crypto.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_stm32_sesnum = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: authcompute - * - * Description: - * Calculate the hash. - * - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_newsession - * - * Description: - * create new session for crypto. - * - ****************************************************************************/ - -static int stm32_newsession(uint32_t *sid, struct cryptoini *cri) -{ - if (sid == NULL || cri == NULL) - { - return -EINVAL; - } - - switch (cri->cri_alg) - { - case CRYPTO_AES_CBC: - *sid = g_stm32_sesnum++; - break; - case CRYPTO_AES_CTR: - if ((cri->cri_klen / 8 - 4) != 16) - { - /* stm32 aes-ctr key bits just support 128 */ - - return -EINVAL; - } - - *sid = g_stm32_sesnum++; - break; - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_freesession - * - * Description: - * free session. - * - ****************************************************************************/ - -static int stm32_freesession(uint64_t tid) -{ - return 0; -} - -/**************************************************************************** - * Name: stm32_process - * - * Description: - * process session to use hardware algorithm. - * - ****************************************************************************/ - -static int stm32_process(struct cryptop *crp) -{ - struct cryptodesc *crd; - uint8_t iv[AESCTR_BLOCKSIZE]; - - for (crd = crp->crp_desc; crd; crd = crd->crd_next) - { - switch (crd->crd_alg) - { - case CRYPTO_AES_CBC: - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - crd->crd_iv, crd->crd_key, 16, - AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); - case CRYPTO_AES_CTR: - - memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, - AESCTR_NONCESIZE); - memcpy(iv + AESCTR_NONCESIZE, crd->crd_iv, AESCTR_IVSIZE); - memset(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE , 0, 4); - - return aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, - iv, crd->crd_key, crd->crd_klen / 8 - 4, - AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); - default: - return -EINVAL; - } - } -} - -/**************************************************************************** - * Name: hwcr_init - * - * Description: - * register the hardware crypto driver. - * - ****************************************************************************/ - -void hwcr_init(void) -{ - int hwcr_id; - int algs[CRYPTO_ALGORITHM_MAX + 1]; - - hwcr_id = crypto_get_driverid(0); - DEBUGASSERT(hwcr_id >= 0); - - memset(algs, 0, sizeof(algs)); - - algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; - algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; - - crypto_register(hwcr_id, algs, stm32_newsession, - stm32_freesession, stm32_process); -} diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h deleted file mode 100644 index 8158c50f81339..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. Performs low level - * initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/stm32_rcc.h deleted file mode 100644 index 3a45a94a0cdc4..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "hardware/stm32_rcc.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to initialize the STM32F0XX. - * This does whatever setup is needed to put the MCU in a usable state. - * This includes the initialization of clocking using the settings - * in board.h. - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.h b/arch/arm/src/stm32f0l0g0/stm32_start.h deleted file mode 100644 index 34691d3ac8013..0000000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_start.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */ diff --git a/arch/arm/src/stm32g0/CMakeLists.txt b/arch/arm/src/stm32g0/CMakeLists.txt new file mode 100644 index 0000000000000..d2d126dda46d8 --- /dev/null +++ b/arch/arm/src/stm32g0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32g0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig new file mode 100644 index 0000000000000..bbee5cd55826b --- /dev/null +++ b/arch/arm/src/stm32g0/Kconfig @@ -0,0 +1,430 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G0 configuration" + +if ARCH_CHIP_STM32G0 + +choice + prompt "ST STM32G0 Chip Selection" + default ARCH_CHIP_STM32G071RB + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070CB + bool "STM32G070CB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070KB + bool "STM32G070KB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070RB + bool "STM32G070RB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071EB + bool "STM32G071EB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8 + bool "STM32G071G8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GB + bool "STM32G071GB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8XN + bool "STM32G071G8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GBXN + bool "STM32G071GBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8 + bool "STM32G071K8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KB + bool "STM32G071KB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8XN + bool "STM32G071K8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KBXN + bool "STM32G071KBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071C8 + bool "STM32G071C8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071CB + bool "STM32G071CB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071R8 + bool "STM32G071R8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071RB + bool "STM32G071RB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KB + bool "STM32G0B1KB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CB + bool "STM32G0B1CB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RB + bool "STM32G0B1RB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MB + bool "STM32G0B1MB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VB + bool "STM32G0B1VB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KC + bool "STM32G0B1KC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CC + bool "STM32G0B1CC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RC + bool "STM32G0B1RC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MC + bool "STM32G0B1MC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VC + bool "STM32G0B1VC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KE + bool "STM32G0B1KE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CE + bool "STM32G0B1CE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RE + bool "STM32G0B1RE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1NE + bool "STM32G0B1NE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1ME + bool "STM32G0B1ME" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VE + bool "STM32G0B1VE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +endchoice + +endif + +config STM32_STM32G0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C2 + select ARCH_HAVE_PROGMEM + +config STM32_STM32G030 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + +config STM32_STM32G031 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + select STM32_HAVE_LPUART1 + +config STM32_STM32G03X + bool + default n + +config STM32_STM32G041 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_LPUART1 + +config STM32_STM32G050 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + +config STM32_STM32G051 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G05X + bool + default n + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + +config STM32_STM32G061 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G070 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + +config STM32_STM32G071 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G07X + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + +config STM32_STM32G081 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G0B0 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + +config STM32_STM32G0B1 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + +config STM32_STM32G0BX + bool + default n + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_CRS + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_HSI48 + +config STM32_STM32G0C1 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_CRS + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_LPUART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + select STM32_HAVE_HSI48 diff --git a/arch/arm/src/stm32g0/Make.defs b/arch/arm/src/stm32g0/Make.defs new file mode 100644 index 0000000000000..75f1a3a88a880 --- /dev/null +++ b/arch/arm/src/stm32g0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32g0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h b/arch/arm/src/stm32g0/chip.h similarity index 67% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h rename to arch/arm/src/stm32g0/chip.h index 9242ac00ff6bd..1569d0603c762 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32g0/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h + * arch/arm/src/stm32g0/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,26 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_CHIP_H +#define __ARCH_ARM_SRC_STM32G0_CHIP_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_rcc.h" -#else -# error "Unsupported STM32 M0 RCC" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */ +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_CHIP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..cd95640e9a64b --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..56faffa2e66c7 --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h rename to arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h index 2f1161c7d3777..d8ac7f51795bb 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h + * arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H /**************************************************************************** * Included Files @@ -322,4 +322,4 @@ #define DMAMUX_SYNC_LPTIM2_OUT 21 #define DMAMUX_SYNC_TIM14_OC 22 -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h rename to arch/arm/src/stm32g0/hardware/stm32g0_exti.h index bfbd8802918f9..695a57836a50c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h + * arch/arm/src/stm32g0/hardware/stm32g0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h rename to arch/arm/src/stm32g0/hardware/stm32g0_flash.h index 5d5780116bf01..779011abd8313 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h + * arch/arm/src/stm32g0/hardware/stm32g0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H /**************************************************************************** * Included Files @@ -279,4 +279,4 @@ #define FLASH_SECR_SEC_SIZE2_MASK (0xff << FLASH_SECR_SEC_SIZE2_SHIFT) /* Bits 28-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h index 595e1886b4cfa..c5455b4df9729 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h + * arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -131,4 +131,4 @@ #define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h index efbb5415b7448..3cc3b5b08500e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h + * arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Gregory Nutt. All rights reserved. @@ -36,8 +36,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H /**************************************************************************** * Included Files @@ -283,4 +283,4 @@ /* TODO: CEC */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pwr.h index ae226f9fca6aa..2df357db170b9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h + * arch/arm/src/stm32g0/hardware/stm32g0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H /**************************************************************************** * Included Files @@ -175,4 +175,4 @@ #define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */ #define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32g0/hardware/stm32g0_rcc.h index 940cb9e6ba2ca..3c5f8ca45217e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32g0/hardware/stm32g0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -363,4 +363,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h rename to arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h index cb4f9bb9c39d5..7ca1ecbbce17d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h + * arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H /**************************************************************************** * Included Files @@ -300,4 +300,4 @@ #define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */ #define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h new file mode 100644 index 0000000000000..9e70f1bf95f02 --- /dev/null +++ b/arch/arm/src/stm32g0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_STM32_H +#define __ARCH_ARM_SRC_STM32G0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32G0_STM32_H */ diff --git a/arch/arm/src/stm32g0/stm32_rcc.c b/arch/arm/src/stm32g0/stm32_rcc.c new file mode 100644 index 0000000000000..f2f084012f86e --- /dev/null +++ b/arch/arm/src/stm32g0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32g0/stm32g0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32g0_rcc.c rename to arch/arm/src/stm32g0/stm32g0_rcc.c index 8933230be5f3e..b79a0224392b8 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32g0/stm32g0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c + * arch/arm/src/stm32g0/stm32g0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l0/CMakeLists.txt b/arch/arm/src/stm32l0/CMakeLists.txt new file mode 100644 index 0000000000000..0b2c640ff2d8f --- /dev/null +++ b/arch/arm/src/stm32l0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32l0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig new file mode 100644 index 0000000000000..e98b00f1cefd7 --- /dev/null +++ b/arch/arm/src/stm32l0/Kconfig @@ -0,0 +1,269 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L0 configuration" + +if ARCH_CHIP_STM32L0 + +choice + prompt "ST STM32L0 Chip Selection" + default ARCH_CHIP_STM32L073RZ + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053C8 + bool "STM32L053C8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053R8 + bool "STM32L053R8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071K8 + bool "STM32L071K8" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KB + bool "STM32L071KB" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KZ + bool "STM32L071KZ" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071C8 + bool "STM32L071C8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CB + bool "STM32L071CB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CZ + bool "STM32L071CZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071V8 + bool "STM32L071V8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VB + bool "STM32L071VB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VZ + bool "STM32L071VZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RB + bool "STM32L071RB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RZ + bool "STM32L071RZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072V8 + bool "STM32L072V8" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VB + bool "STM32L072VB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VZ + bool "STM32L072VZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KB + bool "STM32L072KB" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KZ + bool "STM32L072KZ" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CB + bool "STM32L072CB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CZ + bool "STM32L072CZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RB + bool "STM32L072RB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RZ + bool "STM32L072RZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073V8 + bool "STM32L073V8" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VB + bool "STM32L073VB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VZ + bool "STM32L073VZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CB + bool "STM32L073CB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CZ + bool "STM32L073CZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RB + bool "STM32L073RB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RZ + bool "STM32L073RZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +endchoice + +endif + +config STM32_STM32L0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_ENERGYLITE + select STM32_HAVE_LCD + select STM32_HAVE_VREFINT + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config ARCH_CHIP_STM32L053XX + bool + select STM32_STM32L0 + +config ARCH_CHIP_STM32L071XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + +config ARCH_CHIP_STM32L072XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_I2C2 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32L073XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_USBDEV + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" + default n diff --git a/arch/arm/src/stm32l0/Make.defs b/arch/arm/src/stm32l0/Make.defs new file mode 100644 index 0000000000000..41ee69999f4cf --- /dev/null +++ b/arch/arm/src/stm32l0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32l0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32l0/chip.h b/arch/arm/src/stm32l0/chip.h new file mode 100644 index 0000000000000..f5e1ecde93eae --- /dev/null +++ b/arch/arm/src/stm32l0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_CHIP_H +#define __ARCH_ARM_SRC_STM32L0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_CHIP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..44f335487ab12 --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..680c386947b24 --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h rename to arch/arm/src/stm32l0/hardware/stm32l0_exti.h index 4f246ccd8f734..dea6972eae5a4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h + * arch/arm/src/stm32l0/hardware/stm32l0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H /**************************************************************************** * Included Files @@ -116,4 +116,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h rename to arch/arm/src/stm32l0/hardware/stm32l0_flash.h index 489d8588f185b..2f22a50f7f8e0 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h + * arch/arm/src/stm32l0/hardware/stm32l0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H /**************************************************************************** * Included Files @@ -102,4 +102,4 @@ #define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ #define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h index 30da782402d28..dfdb2b3c4bcc3 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h + * arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -118,4 +118,4 @@ #define STM32_SYSMEM_UID 0x1ff80050 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h index a47d0df7245ac..9e18b9be9abe4 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h + * arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H /**************************************************************************** * Included Files @@ -326,4 +326,4 @@ /* TODO: LPUART */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pwr.h index b5c00fa05e000..9f98c41d29467 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h + * arch/arm/src/stm32l0/hardware/stm32l0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H /**************************************************************************** * Included Files @@ -91,4 +91,4 @@ #define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ #define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32l0/hardware/stm32l0_rcc.h index 42a19e5010088..1b924ce687016 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32l0/hardware/stm32l0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -538,4 +538,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h rename to arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h index 85d28dc0ce9c5..e3dd1bf71592b 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h + * arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H /**************************************************************************** * Included Files @@ -132,4 +132,4 @@ #define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */ #define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H */ diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h new file mode 100644 index 0000000000000..cdcdb2d4aa714 --- /dev/null +++ b/arch/arm/src/stm32l0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_STM32_H +#define __ARCH_ARM_SRC_STM32L0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32L0_STM32_H */ diff --git a/arch/arm/src/stm32l0/stm32_rcc.c b/arch/arm/src/stm32l0/stm32_rcc.c new file mode 100644 index 0000000000000..a41366fdfeb08 --- /dev/null +++ b/arch/arm/src/stm32l0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32l0/stm32l0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32l0_rcc.c rename to arch/arm/src/stm32l0/stm32l0_rcc.c index 6e7b9a92f9d4a..79359bb30bf61 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32l0/stm32l0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32l0_rcc.c + * arch/arm/src/stm32l0/stm32l0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/Kconfig b/boards/Kconfig index 2a6a401dd15a0..bf39f97fd5b93 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5206,14 +5206,11 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32 -source "boards/arm/stm32/common/Kconfig" -endif if ARCH_CHIP_STM32F7 source "boards/arm/stm32f7/common/Kconfig" endif -if ARCH_CHIP_STM32F0L0G0 -source "boards/arm/stm32f0l0g0/common/Kconfig" +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 +source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 source "boards/arm/rp2040/common/Kconfig" diff --git a/boards/arm/stm32c0/common/CMakeLists.txt b/boards/arm/stm32c0/common/CMakeLists.txt new file mode 100644 index 0000000000000..415c1f55334d5 --- /dev/null +++ b/boards/arm/stm32c0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32c0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32c0/common/Kconfig b/boards/arm/stm32c0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32c0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32c0/common/Makefile b/boards/arm/stm32c0/common/Makefile new file mode 100644 index 0000000000000..ef355b1592aef --- /dev/null +++ b/boards/arm/stm32c0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32c0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt index 1eaec21dd1a97..84bb8fe3c7be2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig b/boards/arm/stm32c0/nucleo-c071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig rename to boards/arm/stm32c0/nucleo-c071rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig index d7d1b1380ecca..c203fd3be4ddc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig @@ -13,7 +13,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig index 6f04583925bfe..6851bb112d3bb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig @@ -13,7 +13,8 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig index ede50792f32d5..5849d3ab45d5d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h b/boards/arm/stm32c0/nucleo-c071rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h rename to boards/arm/stm32c0/nucleo-c071rb/include/board.h index 5ca9fdd6cfa3c..500badf7dcb78 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h +++ b/boards/arm/stm32c0/nucleo-c071rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h + * boards/arm/stm32c0/nucleo-c071rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs rename to boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs index 58cbdee0271d3..50ef07255e8c7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs +# boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld rename to boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld index a522204b0c1de..d8da09abcd0e3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld + * boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt index 2d327d8c10698..0639871c1d3f9 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs rename to boards/arm/stm32c0/nucleo-c071rb/src/Make.defs index a89ade512165b..335741d9e20d7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs +++ b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs +# boards/arm/stm32c0/nucleo-c071rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h rename to boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h index 62e686e1c56a1..58b351b36a32f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h +++ b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h + * boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c index 25a62741c1c9b..8b0e2ebc7b168 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c index 86ed1091a04a8..aa077728f35e7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c index 67acc29262f07..8750e2643175f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c index 139d760fc25fc..d85f3e4d8d9db 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c index bc9ffb41367f3..82d2a8e704f96 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c index 2ee610d173f62..525b126499279 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt index 93b039d1da70c..a30b26ee4f4b6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig b/boards/arm/stm32c0/nucleo-c092rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig rename to boards/arm/stm32c0/nucleo-c092rc/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig index af46d19b5c7fe..1a2ebdb418500 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig index 9a9e901e2bd7e..57d858f02bd27 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig @@ -12,7 +12,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig index 8728028d0dc4e..bd38abc3918d6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig @@ -13,7 +13,8 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig index 49856182e0058..718871956d30c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h b/boards/arm/stm32c0/nucleo-c092rc/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h rename to boards/arm/stm32c0/nucleo-c092rc/include/board.h index f85f0b12044b3..0422106dda396 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h +++ b/boards/arm/stm32c0/nucleo-c092rc/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h + * boards/arm/stm32c0/nucleo-c092rc/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs rename to boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs index cb4dd0432323b..dad81a59c24fd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +# boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld rename to boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld index 675eb647b5b0b..83f188550d842 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld + * boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt index eacf44fab2591..0ab1b18faa21c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs rename to boards/arm/stm32c0/nucleo-c092rc/src/Make.defs index b6701ee29bf87..74c27aa25f718 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +++ b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +# boards/arm/stm32c0/nucleo-c092rc/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h rename to boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h index f7ab2300b193d..85f594562c755 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h +++ b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h + * boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c index 51a76e9d5912c..777e65c018e7d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c index 016eca350de0c..e43d5cf6749c6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c index 29e95219a8e08..d60d9f20b372a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c index eb5bb09a60f32..8f631a46a2c43 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c index 06501f3b4ff7c..c5659c8f6cc90 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c index b51e5ba4d4dcc..d2ba35278e02a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c index a1a4bcb89b2cf..8a24931b13dfe 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c index 77b08b2f3a8ba..5740dc20b9066 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/common/CMakeLists.txt b/boards/arm/stm32f0/common/CMakeLists.txt new file mode 100644 index 0000000000000..55e8f2f019110 --- /dev/null +++ b/boards/arm/stm32f0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f0/common/Kconfig b/boards/arm/stm32f0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f0/common/Makefile b/boards/arm/stm32f0/common/Makefile new file mode 100644 index 0000000000000..160e05f23b9ae --- /dev/null +++ b/boards/arm/stm32f0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt index 03f3ea5a66588..f4c468079f835 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig b/boards/arm/stm32f0/nucleo-f072rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig rename to boards/arm/stm32f0/nucleo-f072rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig rename to boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig index b5de6c951e8d5..4a266b9184f3a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig @@ -24,7 +24,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f072rb" CONFIG_ARCH_BOARD_NUCLEO_F072RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0/nucleo-f072rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h rename to boards/arm/stm32f0/nucleo-f072rb/include/board.h index c8098bc38de67..ecbb09cd8db12 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0/nucleo-f072rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h + * boards/arm/stm32f0/nucleo-f072rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs rename to boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs index 1e325f2a9bfac..8565d214ef4e7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs +# boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld rename to boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld index 5e638ee249884..ae6006b5cdbcb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld + * boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt index 16d4ed14c1224..26e316b2b248e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs rename to boards/arm/stm32f0/nucleo-f072rb/src/Make.defs index 27aae3fb3b131..8d74dbfdb4c3f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs +++ b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs +# boards/arm/stm32f0/nucleo-f072rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h rename to boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h index 36016f917cc98..d4bf7700d1023 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h +++ b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h + * boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c index 2738e92b21dca..dbd5f76182e73 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c index fb79ff4c3a4cf..e1c37566fda8b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c index dbb0d70b4b831..ccf38aeb624f8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c index 246f6a7a98e69..8bca5ed46ca84 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c index a64c333c331a4..9715fe31a22dc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt index a9ce71ece553b..7b9d3c1af756e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig b/boards/arm/stm32f0/nucleo-f091rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig rename to boards/arm/stm32f0/nucleo-f091rc/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig rename to boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig index 10d566c6b7dbf..1cd0f3abf3969 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig @@ -24,7 +24,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig rename to boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig index aac6d73808468..0298afca17958 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig @@ -10,7 +10,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0/nucleo-f091rc/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h rename to boards/arm/stm32f0/nucleo-f091rc/include/board.h index dd2355bc204e8..745d8a6644332 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0/nucleo-f091rc/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h + * boards/arm/stm32f0/nucleo-f091rc/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs rename to boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs index 0ee77f57b23f8..712d91084b71a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +# boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld rename to boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld index 4965225b11270..7d017d6432384 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld + * boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt index afd6342087a89..3ca74165ebc68 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs rename to boards/arm/stm32f0/nucleo-f091rc/src/Make.defs index 82b838efb8113..a79b2d81893fc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +++ b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +# boards/arm/stm32f0/nucleo-f091rc/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h rename to boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h index fadc808cd3833..e1f962c5270b5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h +++ b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h + * boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c index 6462ab5c8136b..c6905fbe01eb5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c index 57014d141dfc2..2d58bdb01f245 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c index 02697f3f88848..0a1f1e5eba1d5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c index 6bcff91cece11..060097e42e6a7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c index 0fc2cab2ae5f3..253eae21e0df0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c index 2c674d8aa6423..2f96bee994809 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c index cf8e3cccc45c2..92b0a4bcdd385 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt rename to boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt index be95ff78863a5..82f56ec121ee1 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt +# boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig b/boards/arm/stm32f0/stm32f051-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig rename to boards/arm/stm32f0/stm32f051-discovery/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig rename to boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig index 22a9310041d59..2e21e6e8d07ac 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig @@ -14,7 +14,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f051-discovery" CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F051R8=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0/stm32f051-discovery/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h rename to boards/arm/stm32f0/stm32f051-discovery/include/board.h index 0975e6956195d..64aa156add7cd 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f051-discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h + * boards/arm/stm32f0/stm32f051-discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs new file mode 100644 index 0000000000000..101580bd303eb --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld rename to boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld index bd4efbb45030b..7be00e78d9818 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld + * boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt rename to boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt index 091c56d51df1b..ea0e96675cc3a 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +# boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs rename to boards/arm/stm32f0/stm32f051-discovery/src/Make.defs index b991bc06e471b..df3653b25acbc 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +++ b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +# boards/arm/stm32f0/stm32f051-discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c index 1528e56afd61f..db37ca075aa6e 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c index bd53babb84aa0..94dafa4afee4f 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c index 5ad5089520cc3..c3adb7ee280bf 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c index 9fd07f705f527..fefd449f40a1c 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c index d0bda657d64fb..973ab746680aa 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h index 5c74903ff1f6b..46edd74b73963 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h + * boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt new file mode 100644 index 0000000000000..2e72ceab91ad9 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig b/boards/arm/stm32f0/stm32f072-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig rename to boards/arm/stm32f0/stm32f072-discovery/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig rename to boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig index 7fc5f309f92a9..8496c183dd9c7 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig @@ -14,7 +14,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f072-discovery" CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0/stm32f072-discovery/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h rename to boards/arm/stm32f0/stm32f072-discovery/include/board.h index 06932bb64ee68..52a339aee2a6f 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f072-discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h + * boards/arm/stm32f0/stm32f072-discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs new file mode 100644 index 0000000000000..9796d338da43e --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld rename to boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld index 5ae8a09a00d5f..fc42f97036ae7 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld + * boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt rename to boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt index ac55fa30c7416..4a75392b78b99 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +# boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs rename to boards/arm/stm32f0/stm32f072-discovery/src/Make.defs index b71427a76278a..e5b94f00634df 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +++ b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +# boards/arm/stm32f0/stm32f072-discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c index c6860f90f7a44..dc5246da6554a 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c index 623f491e91a00..5992d7a77ca33 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c index 4302171b88103..48c86e9507bc9 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c index 6c894a4a375b5..a4c7fa265fddd 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c index 555102839367f..30c6009348449 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h index db6fe74ca2982..482517929693b 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h + * boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs deleted file mode 100644 index cede66c2c8957..0000000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/common b/boards/arm/stm32f0l0g0/common deleted file mode 120000 index f25cef98ae272..0000000000000 --- a/boards/arm/stm32f0l0g0/common +++ /dev/null @@ -1 +0,0 @@ -../common/stm32 \ No newline at end of file diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt deleted file mode 100644 index 4427973ea2674..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt deleted file mode 100644 index b94721d67afc0..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt deleted file mode 100644 index f161ea4448aa7..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt deleted file mode 100644 index 79eec2b120d43..0000000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt deleted file mode 100644 index 3097fc40425d9..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs deleted file mode 100644 index 5d941d50d5a00..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt deleted file mode 100644 index 46b3a6cd11d6d..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs deleted file mode 100644 index 5d8a0c14523c9..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt deleted file mode 100644 index 9dcefda96ea37..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs deleted file mode 100644 index 8679bdc9fcdc3..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt deleted file mode 100644 index 367387d199b74..0000000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32g0/common/CMakeLists.txt b/boards/arm/stm32g0/common/CMakeLists.txt new file mode 100644 index 0000000000000..4a04cc45ad2f9 --- /dev/null +++ b/boards/arm/stm32g0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32g0/common/Kconfig b/boards/arm/stm32g0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32g0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g0/common/Makefile b/boards/arm/stm32g0/common/Makefile new file mode 100644 index 0000000000000..8919a4ba78378 --- /dev/null +++ b/boards/arm/stm32g0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32g0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt new file mode 100644 index 0000000000000..f505090d81c82 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig b/boards/arm/stm32g0/nucleo-g070rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig rename to boards/arm/stm32g0/nucleo-g070rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig index 9b43266c33578..f78e5a4b951d6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig @@ -10,7 +10,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g070rb" CONFIG_ARCH_BOARD_NUCLEO_G070RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G070RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h b/boards/arm/stm32g0/nucleo-g070rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h rename to boards/arm/stm32g0/nucleo-g070rb/include/board.h index 5e09c65d50a1e..2a65558b105d0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h +++ b/boards/arm/stm32g0/nucleo-g070rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h + * boards/arm/stm32g0/nucleo-g070rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs index df8a4c75ba114..2e92c773e09d4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script index 3eddc960eb999..96714a97dd6b7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script + * boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt index 08d07dd22c1c0..cea0f3cd6a324 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs rename to boards/arm/stm32g0/nucleo-g070rb/src/Make.defs index 3fcfafcf17fe3..e7b3454bb3201 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs +# boards/arm/stm32g0/nucleo-g070rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h rename to boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h index c48523c418437..7db19ce4ced36 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h +++ b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h + * boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c index b96b3795bd0d7..185304a690388 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c index 5fc389ad0669c..c5fbfbc30471b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c index 975cd5aeb1c7b..8ca8dd171b865 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c index 9bd12c84dfa97..4b711729ba839 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c index ecd0da7f94444..d414c7c3e0599 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c index b81ff3aa9b6a2..cfcbef9088a36 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c index 9442536d35ff2..886e6f72ca06e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt new file mode 100644 index 0000000000000..4d11fab0a1873 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig b/boards/arm/stm32g0/nucleo-g071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig rename to boards/arm/stm32g0/nucleo-g071rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig index 58d337a3690d7..fd83983a8e0b2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g071rb" CONFIG_ARCH_BOARD_NUCLEO_G071RB=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h b/boards/arm/stm32g0/nucleo-g071rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h rename to boards/arm/stm32g0/nucleo-g071rb/include/board.h index a6bba4ae7d9ea..bf18ab683b9a2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h +++ b/boards/arm/stm32g0/nucleo-g071rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h + * boards/arm/stm32g0/nucleo-g071rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs index e7c7c7f21aff5..dfc69a1d5bf71 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script index b545dc383e750..9ea7803e49ae5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script + * boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt index f6843c176e198..4a054473a96d2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs rename to boards/arm/stm32g0/nucleo-g071rb/src/Make.defs index 75e78e8bc721c..3fa2cd2f85f94 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs +# boards/arm/stm32g0/nucleo-g071rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h rename to boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h index 32e9d86e5fbe8..cda374f9f4393 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h +++ b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h + * boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c index e0c9af572f43e..38287bbc4a15a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c index 14706cd0ce53a..5f891341e72ee 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c index cea5f3eab4e73..d36512d8e58ba 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c index a8f4576836445..881950a0dbc6f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt new file mode 100644 index 0000000000000..7acee0b7feda7 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig b/boards/arm/stm32g0/nucleo-g0b1re/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig rename to boards/arm/stm32g0/nucleo-g0b1re/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig index 565ff0d9dd1dc..c72cc65d0a792 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig @@ -11,7 +11,8 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig index 539f7b5141c82..6b0f6cd7c324f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -12,7 +12,8 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig index 5eea859d573e5..05e08970e6c0d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h rename to boards/arm/stm32g0/nucleo-g0b1re/include/board.h index 03888c49925dd..6120aad294eda 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h +++ b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h + * boards/arm/stm32g0/nucleo-g0b1re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs index 4f7c125818c27..5090b0ed9603a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script index efe5f8f915ead..0010b5241542b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script + * boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt index b0e6eae77fbcc..cfb9418e3d3a9 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs rename to boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs index b3019b82f54fd..63f203ffda0e0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs +# boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h rename to boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h index 66318689a0f64..30f9bd80a2ccc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h + * boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c index b1f9be4fd7243..21ab51079be17 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c index 2ee5c55f2ade0..248a297f61745 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c index e882e5d161749..231a9256892b7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c index e9ca45a84d77d..d852c55b2a2fd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c index 688327750b6ff..8a389b06aef13 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt new file mode 100644 index 0000000000000..2b50926e86709 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig b/boards/arm/stm32g0/stm32g071b-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig rename to boards/arm/stm32g0/stm32g071b-disco/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig rename to boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig index 693e2684eb63e..0fc28153e81b9 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig @@ -10,7 +10,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig rename to boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig index 727e0620e56f2..37dc8896e4144 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig @@ -13,7 +13,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h b/boards/arm/stm32g0/stm32g071b-disco/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h rename to boards/arm/stm32g0/stm32g071b-disco/include/board.h index c3e14a3fe1d14..86274e4365e42 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h +++ b/boards/arm/stm32g0/stm32g071b-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h + * boards/arm/stm32g0/stm32g071b-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs rename to boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs index 0f50dc2d96b09..86966d95270e6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +# boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script rename to boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script index 83336a8c174c1..b39bb951fed56 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script + * boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt rename to boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt index 88d162b167978..2757b87d9fd47 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt +++ b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt +# boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs rename to boards/arm/stm32g0/stm32g071b-disco/src/Make.defs index 1f012b2515c36..0adb2e6de3efc 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs +++ b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs +# boards/arm/stm32g0/stm32g071b-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c index 9fd6f2becdcc3..9ceb6f99b0531 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c index c41a38d31a1f5..09ca37d7392ea 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c index bd9171ece4a96..0eae75d75e281 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c index 310ba0bc75c4e..edc72b34f92e2 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c index 1dce5040dd370..5655d41731c8a 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c index ee25ef5734fdf..db74b668500e7 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c index 07037ab3d6bb8..f75d17e3bd111 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c index d8845d205d5bf..c1341209dff81 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h index f8c27839f17e0..69585d3f7b1cb 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h + * boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt new file mode 100644 index 0000000000000..f474a7db2a1e0 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig b/boards/arm/stm32l0/b-l072z-lrwan1/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/Kconfig diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig index a9c565cda4266..016388d1db9a4 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig @@ -11,7 +11,8 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig index 6b40188837b4e..f8dc57d278479 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index d7167b38ab31a..b2c85a1eebb42 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -12,7 +12,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig index c200442001979..1f5723aba0a06 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h rename to boards/arm/stm32l0/b-l072z-lrwan1/include/board.h index 95e19a5a6c293..2029f595402a0 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h + * boards/arm/stm32l0/b-l072z-lrwan1/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs new file mode 100644 index 0000000000000..74fc513e986a0 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script rename to boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script index c95d535e86d18..1c6f4b40e82c3 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script + * boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt rename to boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt index 4770af26d5f88..3c1bf3c65f31a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +# boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs rename to boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs index 55c1d27f870da..0ef4cef9f33ed 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +# boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h rename to boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 81c81c06f1d51..dfbc614c32214 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h + * boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c index 36d2d48f60e71..593a484fd8397 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c index c71e5764e6e57..1b0b8cd55b38e 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c index ce025e3b964df..aad79dbb41f83 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c index 152c4cc463c30..c3935c1ff164f 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c index dcdae68aef25c..9644213f06626 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c index 7b42fb7e3ce13..368df13bf056d 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c index 32e9e6754068e..e6ffc4681397d 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/common/CMakeLists.txt b/boards/arm/stm32l0/common/CMakeLists.txt new file mode 100644 index 0000000000000..4ae413b13be07 --- /dev/null +++ b/boards/arm/stm32l0/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l0/common/Kconfig b/boards/arm/stm32l0/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l0/common/Makefile b/boards/arm/stm32l0/common/Makefile new file mode 100644 index 0000000000000..17c365d758c87 --- /dev/null +++ b/boards/arm/stm32l0/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt new file mode 100644 index 0000000000000..d660ec8525f44 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig b/boards/arm/stm32l0/nucleo-l073rz/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig rename to boards/arm/stm32l0/nucleo-l073rz/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig rename to boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig index c04c43cd46e47..d4ddb1d55dd86 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig rename to boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig index fc8331e8670e4..32220b19127c1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig @@ -10,7 +10,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32l0/nucleo-l073rz/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h rename to boards/arm/stm32l0/nucleo-l073rz/include/board.h index d24c64eaaf4d8..af284ca168eaf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32l0/nucleo-l073rz/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h + * boards/arm/stm32l0/nucleo-l073rz/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs new file mode 100644 index 0000000000000..596e9665da7c2 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script rename to boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script index e0da80b38d57a..2156f68042fc3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script + * boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt rename to boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt index ac95ed5c073dc..b70c2615c82b6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +++ b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +# boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs rename to boards/arm/stm32l0/nucleo-l073rz/src/Make.defs index ff5d2d230eb14..f29673903468f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +++ b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +# boards/arm/stm32l0/nucleo-l073rz/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h rename to boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h index 90410fded75cb..f72a20312f5fd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h + * boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c index 2f06c37702f38..ffe74f73f87a8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c index a08ebff39304d..8ee936849c333 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c index 35e5ae85e28b4..3a573ba1c8d59 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c index 6fee37bc6e0f0..5f59392762ab5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c index 2481cdfb428cf..4cbc3ee003cad 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c index b8bb669ff793c..4b3e1311e5823 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c index a9495e3544c7d..3daa75311914e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c index a57868721089b..1893e1797354d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt new file mode 100644 index 0000000000000..32e681f9f1be1 --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig b/boards/arm/stm32l0/stm32l0538-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig rename to boards/arm/stm32l0/stm32l0538-disco/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig similarity index 96% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig rename to boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig index f761d37e14ea2..7a823b72968f6 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig @@ -9,7 +9,8 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l0538-disco" CONFIG_ARCH_BOARD_STM32L0538_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L053C8=y CONFIG_ARCH_CHIP_STM32L053XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32l0/stm32l0538-disco/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h rename to boards/arm/stm32l0/stm32l0538-disco/include/board.h index 5cc344752dcbd..f1ba04878c682 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32l0/stm32l0538-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h + * boards/arm/stm32l0/stm32l0538-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs rename to boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs index 5417678c0ce39..5a209945f33c2 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs +# boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script rename to boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script index 3ab8df515ea8f..9eb309a0097b7 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script + * boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt rename to boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt index 2d3a59a01db8e..7819e8f72267f 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt +++ b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt +# boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs rename to boards/arm/stm32l0/stm32l0538-disco/src/Make.defs index 502d059a1057e..6d6fb20db57c7 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs +++ b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs +# boards/arm/stm32l0/stm32l0538-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c index b7564b913121f..9e28a2427ef07 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c index b760b793943a9..b3a0d820c4826 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c index c4907ef7ac8c3..1bc7e9a74e645 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c index f6cff70cb1942..73295823d915a 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h index 34b45f2a99444..38e14d22f82a8 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h + * boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h * * SPDX-License-Identifier: Apache-2.0 * From d5f1b2ca1f3454210d195c805d89bc98be7a34cc Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 30/52] !arch/stm32: split into stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, stm32g4 BREAKING CHANGE: The legacy STM32 architecture and board paths were split into stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, and stm32g4 directories. Out-of-tree boards must move from stm32 to the matching split family. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 3366 +++++++++-------- .../applications/examples/ft80x/index.rst | 2 +- .../applications/system/usbmsc/index.rst | 2 +- .../drivers/character/leds/userled.rst | 2 +- .../components/drivers/character/serial.rst | 2 +- .../components/drivers/special/lcd.rst | 6 +- .../components/drivers/special/sdio.rst | 2 +- .../components/drivers/special/usbdev.rst | 2 +- .../components/drivers/special/usbhost.rst | 2 +- Documentation/contributing/making-changes.rst | 2 +- .../guides/changing_systemclockconfig.rst | 4 +- Documentation/guides/etcromfs.rst | 2 +- Documentation/guides/ipv6.rst | 4 +- .../guides/nsh_network_link_management.rst | 2 +- Documentation/guides/ofloader.rst | 2 +- Documentation/guides/partially_linked_elf.rst | 2 +- .../guides/port_drivers_to_stm32f7.rst | 2 +- Documentation/guides/protected_build.rst | 22 +- .../guides/smaller_vector_tables.rst | 10 +- Documentation/guides/stm32ccm.rst | 2 +- Documentation/guides/usingkernelthreads.rst | 2 +- .../guides/zerolatencyinterrupts.rst | 4 +- Documentation/implementation/chip_h.rst | 10 +- .../implementation/file_descriptors.rst | 8 +- .../nuttx_initialization_sequence.rst | 26 +- .../arm/stm32f1/boards/fire-stm32v2/index.rst | 4 +- .../arm/stm32f1/boards/shenzhou/index.rst | 2 +- .../stm32f1/boards/stm3210e-eval/index.rst | 12 +- .../boards/stm32f103-minimum/index.rst | 4 +- .../stm32f1/boards/stm32vldiscovery/index.rst | 2 +- .../stm32f4/boards/clicker2-stm32/index.rst | 2 +- .../arm/stm32f4/boards/omnibusf4/index.rst | 2 +- .../stm32f4/boards/stm32f4discovery/index.rst | 14 +- Documentation/platforms/arm/stm32f4/index.rst | 2 +- .../stm32l4/boards/nucleo-l432kc/index.rst | 2 +- .../stm32l4/boards/nucleo-l476rg/index.rst | 2 +- Documentation/quickstart/organization.rst | 2 +- LICENSE | 44 +- arch/arm/Kconfig | 44 +- arch/arm/include/stm32/chip.h | 2756 -------------- arch/arm/include/stm32/irq.h | 121 - arch/arm/include/stm32/stm32f10xxx_irq.h | 298 -- arch/arm/include/stm32/stm32f20xxx_irq.h | 172 - arch/arm/include/stm32/stm32f40xxx_irq.h | 347 -- arch/arm/include/stm32/stm32g4xxxx_irq.h | 202 - arch/arm/include/stm32/stm32l15xxx_irq.h | 260 -- arch/arm/include/stm32f1/chip.h | 495 +++ arch/arm/include/stm32f1/irq.h | 286 ++ arch/arm/include/stm32f2/chip.h | 189 + arch/arm/include/stm32f2/irq.h | 168 + arch/arm/include/stm32f3/chip.h | 627 +++ arch/arm/include/stm32f3/irq.h | 84 + .../{stm32 => stm32f3}/stm32f30xxx_irq.h | 31 +- .../{stm32 => stm32f3}/stm32f33xxx_irq.h | 31 +- .../{stm32 => stm32f3}/stm32f37xxx_irq.h | 31 +- arch/arm/include/stm32f4/chip.h | 864 +++++ arch/arm/include/stm32f4/irq.h | 346 ++ arch/arm/include/stm32g4/chip.h | 350 ++ arch/arm/include/stm32g4/irq.h | 225 ++ arch/arm/include/stm32l1/chip.h | 491 +++ arch/arm/include/stm32l1/irq.h | 252 ++ .../src/common/stm32/stm32_dma2d_m3m4_v1.c | 2 +- .../common/stm32/stm32_dma_m0_v1_7ch_dmamux.c | 2 +- arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c | 2 +- arch/arm/src/stm32/CMakeLists.txt | 57 - arch/arm/src/stm32/Kconfig | 2101 ---------- arch/arm/src/stm32/Make.defs | 48 - arch/arm/src/stm32/chip.h | 59 - arch/arm/src/stm32/hardware/stm32_adc_v1.h | 640 ---- arch/arm/src/stm32/hardware/stm32_adc_v1l1.h | 571 --- arch/arm/src/stm32/hardware/stm32_adc_v2.h | 735 ---- arch/arm/src/stm32/hardware/stm32_adc_v2g4.h | 869 ----- arch/arm/src/stm32/hardware/stm32_bkp.h | 177 - arch/arm/src/stm32/hardware/stm32_dac_v1.h | 315 -- arch/arm/src/stm32/hardware/stm32_dma.h | 55 - arch/arm/src/stm32/hardware/stm32_dma2d.h | 237 -- arch/arm/src/stm32/hardware/stm32_dma_v2.h | 561 --- arch/arm/src/stm32/hardware/stm32_eth.h | 877 ----- arch/arm/src/stm32/hardware/stm32_fmc.h | 392 -- arch/arm/src/stm32/hardware/stm32_fsmc.h | 301 -- arch/arm/src/stm32/hardware/stm32_i2c_v1.h | 203 - arch/arm/src/stm32/hardware/stm32_i2c_v2.h | 241 -- arch/arm/src/stm32/hardware/stm32_lcd.h | 209 - arch/arm/src/stm32/hardware/stm32_ltdc.h | 368 -- arch/arm/src/stm32/hardware/stm32_otghs.h | 1111 ------ arch/arm/src/stm32/hardware/stm32_rtc.h | 83 - arch/arm/src/stm32/hardware/stm32_sdio.h | 279 -- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 1307 ------- arch/arm/src/stm32/hardware/stm32_tim_v3.h | 1440 ------- arch/arm/src/stm32/hardware/stm32_usbfs.h | 250 -- .../arm/src/stm32/hardware/stm32f10xxx_uart.h | 206 - .../arm/src/stm32/hardware/stm32f20xxx_uart.h | 218 -- .../arm/src/stm32/hardware/stm32f30xxx_uart.h | 341 -- .../arm/src/stm32/hardware/stm32f40xxx_uart.h | 236 -- .../src/stm32/hardware/stm32fxxxxx_otgfs.h | 1115 ------ .../arm/src/stm32/hardware/stm32g4xxxx_uart.h | 439 --- arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h | 525 --- .../arm/src/stm32/hardware/stm32l15xxx_uart.h | 208 - arch/arm/src/stm32/stm32.h | 69 - arch/arm/src/stm32/stm32_lowputc.h | 66 - arch/arm/src/stm32/stm32_mpuinit.h | 65 - arch/arm/src/stm32/stm32_pm.h | 127 - arch/arm/src/stm32/stm32_rcc.c | 252 -- arch/arm/src/stm32/stm32_rcc.h | 321 -- arch/arm/src/stm32/stm32_start.h | 49 - arch/arm/src/stm32/stm32_userspace.h | 63 - arch/arm/src/stm32f1/CMakeLists.txt | 28 + arch/arm/src/stm32f1/Kconfig | 482 +++ arch/arm/src/stm32f1/Kconfig.pinmap | 182 + arch/arm/src/stm32f1/Make.defs | 27 + arch/arm/src/stm32f1/chip.h | 59 + .../src/stm32f1/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32f1/hardware/stm32_pinmap.h | 46 + .../hardware/stm32f100_pinmap.h | 2 +- .../hardware/stm32f102_pinmap.h | 2 +- .../hardware/stm32f103c_pinmap.h | 2 +- .../hardware/stm32f103r_pinmap.h | 2 +- .../hardware/stm32f103v_pinmap.h | 2 +- .../hardware/stm32f103z_pinmap.h | 2 +- .../hardware/stm32f105r_pinmap.h | 2 +- .../hardware/stm32f105v_pinmap.h | 2 +- .../hardware/stm32f107v_pinmap.h | 2 +- .../hardware/stm32f10xxx_gpio.h | 2 +- .../hardware/stm32f10xxx_memorymap.h | 2 +- .../hardware/stm32f10xxx_rcc.h | 2 +- arch/arm/src/stm32f1/stm32.h | 69 + arch/arm/src/stm32f1/stm32_rcc.c | 234 ++ .../src/{stm32 => stm32f1}/stm32f10xxx_rcc.c | 2 +- arch/arm/src/stm32f2/CMakeLists.txt | 28 + arch/arm/src/stm32f2/Kconfig | 179 + arch/arm/src/stm32f2/Make.defs | 27 + arch/arm/src/stm32f2/chip.h | 59 + .../src/stm32f2/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32f2/hardware/stm32_pinmap.h | 17 + .../hardware/stm32f20xxx_gpio.h | 2 +- .../hardware/stm32f20xxx_memorymap.h | 2 +- .../hardware/stm32f20xxx_pinmap.h | 2 +- .../hardware/stm32f20xxx_rcc.h | 2 +- .../hardware/stm32f20xxx_syscfg.h | 2 +- arch/arm/src/stm32f2/stm32.h | 69 + arch/arm/src/stm32f2/stm32_rcc.c | 234 ++ .../src/{stm32 => stm32f2}/stm32f20xxx_rcc.c | 2 +- arch/arm/src/stm32f3/CMakeLists.txt | 28 + arch/arm/src/stm32f3/Kconfig | 614 +++ arch/arm/src/stm32f3/Make.defs | 27 + arch/arm/src/stm32f3/chip.h | 59 + .../src/stm32f3/hardware/stm32_memorymap.h | 27 + arch/arm/src/stm32f3/hardware/stm32_pinmap.h | 27 + .../hardware/stm32f30xxx_gpio.h | 2 +- .../hardware/stm32f30xxx_memorymap.h | 2 +- .../hardware/stm32f30xxx_pinmap.h | 2 +- .../hardware/stm32f30xxx_rcc.h | 2 +- .../hardware/stm32f30xxx_syscfg.h | 2 +- .../hardware/stm32f33xxx_comp.h | 2 +- .../hardware/stm32f33xxx_hrtim.h | 2 +- .../hardware/stm32f33xxx_memorymap.h | 2 +- .../hardware/stm32f33xxx_opamp.h | 2 +- .../hardware/stm32f33xxx_pinmap.h | 2 +- .../hardware/stm32f33xxx_rcc.h | 2 +- .../hardware/stm32f33xxx_syscfg.h | 2 +- .../hardware/stm32f37xxx_memorymap.h | 2 +- .../hardware/stm32f37xxx_pinmap.h | 2 +- .../hardware/stm32f37xxx_rcc.h | 2 +- .../hardware/stm32f37xxx_sdadc.h | 2 +- .../hardware/stm32f37xxx_syscfg.h | 2 +- arch/arm/src/stm32f3/stm32.h | 69 + arch/arm/src/stm32f3/stm32_rcc.c | 242 ++ .../src/{stm32 => stm32f3}/stm32f30xxx_rcc.c | 2 +- .../src/{stm32 => stm32f3}/stm32f33xxx_rcc.c | 2 +- .../src/{stm32 => stm32f3}/stm32f37xxx_rcc.c | 2 +- arch/arm/src/stm32f4/CMakeLists.txt | 28 + arch/arm/src/stm32f4/Kconfig | 619 +++ arch/arm/src/stm32f4/Make.defs | 27 + arch/arm/src/stm32f4/chip.h | 59 + .../src/stm32f4/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32f4/hardware/stm32_pinmap.h | 25 + .../hardware/stm32f40xxx_gpio.h | 2 +- .../hardware/stm32f40xxx_memorymap.h | 2 +- .../hardware/stm32f40xxx_pinmap.h | 2 +- .../hardware/stm32f40xxx_rcc.h | 2 +- .../hardware/stm32f40xxx_syscfg.h | 2 +- .../hardware/stm32f412xx_pinmap.h | 2 +- arch/arm/src/stm32f4/stm32.h | 69 + arch/arm/src/stm32f4/stm32_rcc.c | 234 ++ .../{stm32 => stm32f4}/stm32f40xxx_alarm.h | 2 +- .../src/{stm32 => stm32f4}/stm32f40xxx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32_can_sock.c | 2 +- arch/arm/src/stm32f7/stm32_foc.c | 3 +- arch/arm/src/stm32g4/CMakeLists.txt | 28 + arch/arm/src/stm32g4/Kconfig | 336 ++ arch/arm/src/stm32g4/Make.defs | 27 + arch/arm/src/stm32g4/chip.h | 59 + .../src/stm32g4/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32g4/hardware/stm32_pinmap.h | 17 + .../hardware/stm32g47xxx_hrtim.h | 2 +- .../hardware/stm32g4xxc_pinmap.h | 2 +- .../hardware/stm32g4xxk_pinmap.h | 2 +- .../hardware/stm32g4xxm_pinmap.h | 2 +- .../hardware/stm32g4xxp_pinmap.h | 2 +- .../hardware/stm32g4xxq_pinmap.h | 2 +- .../hardware/stm32g4xxr_pinmap.h | 2 +- .../hardware/stm32g4xxv_pinmap.h | 2 +- .../hardware/stm32g4xxxx_comp.h | 2 +- .../hardware/stm32g4xxxx_cordic.h | 2 +- .../hardware/stm32g4xxxx_dmamux.h | 2 +- .../hardware/stm32g4xxxx_gpio.h | 2 +- .../hardware/stm32g4xxxx_memorymap.h | 2 +- .../hardware/stm32g4xxxx_opamp.h | 2 +- .../hardware/stm32g4xxxx_pinmap.h | 2 +- .../hardware/stm32g4xxxx_pwr.h | 2 +- .../hardware/stm32g4xxxx_rcc.h | 2 +- .../hardware/stm32g4xxxx_syscfg.h | 2 +- .../hardware/stm32g4xxxx_vrefbuf.h | 2 +- arch/arm/src/stm32g4/stm32.h | 69 + arch/arm/src/stm32g4/stm32_rcc.c | 234 ++ .../src/{stm32 => stm32g4}/stm32g4xxxx_rcc.c | 2 +- arch/arm/src/stm32l1/CMakeLists.txt | 28 + arch/arm/src/stm32l1/Kconfig | 353 ++ arch/arm/src/stm32l1/Make.defs | 27 + arch/arm/src/stm32l1/chip.h | 59 + .../src/stm32l1/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32l1/hardware/stm32_pinmap.h | 17 + .../hardware/stm32l15xxx_aes.h | 2 +- .../hardware/stm32l15xxx_gpio.h | 2 +- .../hardware/stm32l15xxx_memorymap.h | 2 +- .../hardware/stm32l15xxx_pinmap.h | 2 +- .../hardware/stm32l15xxx_rcc.h | 2 +- .../hardware/stm32l15xxx_syscfg.h | 2 +- arch/arm/src/stm32l1/stm32.h | 69 + arch/arm/src/stm32l1/stm32_rcc.c | 234 ++ .../{stm32 => stm32l1}/stm32l15xxx_alarm.h | 2 +- .../src/{stm32 => stm32l1}/stm32l15xxx_rcc.c | 2 +- boards/Kconfig | 130 +- boards/arm/stm32/axoloti/CMakeLists.txt | 23 - .../arm/stm32/axoloti/configs/nsh/defconfig | 39 - boards/arm/stm32/axoloti/include/board.h | 263 -- boards/arm/stm32/axoloti/scripts/Make.defs | 41 - .../arm/stm32/axoloti/scripts/kernel-space.ld | 100 - boards/arm/stm32/axoloti/scripts/ld.script | 132 - boards/arm/stm32/axoloti/scripts/memory.ld | 88 - .../arm/stm32/axoloti/scripts/user-space.ld | 114 - boards/arm/stm32/axoloti/src/CMakeLists.txt | 53 - boards/arm/stm32/axoloti/src/Make.defs | 55 - boards/arm/stm32/axoloti/src/stm32_boot.c | 89 - boards/arm/stm32/axoloti/src/stm32_bringup.c | 176 - boards/arm/stm32/axoloti/src/stm32_buttons.c | 151 - boards/arm/stm32/axoloti/src/stm32_extmem.c | 310 -- boards/arm/stm32/axoloti/src/stm32_sdio.c | 156 - boards/arm/stm32/axoloti/src/stm32_usbhost.c | 265 -- boards/arm/stm32/axoloti/src/stm32_userleds.c | 93 - boards/arm/stm32/b-g431b-esc1/CMakeLists.txt | 23 - .../stm32/b-g431b-esc1/configs/can/defconfig | 53 - .../b-g431b-esc1/configs/cansock/defconfig | 61 - .../b-g431b-esc1/configs/foc_b16/defconfig | 87 - .../b-g431b-esc1/configs/foc_f32/defconfig | 88 - .../stm32/b-g431b-esc1/configs/nsh/defconfig | 48 - boards/arm/stm32/b-g431b-esc1/include/board.h | 380 -- .../arm/stm32/b-g431b-esc1/scripts/Make.defs | 51 - .../arm/stm32/b-g431b-esc1/scripts/ld.script | 139 - .../arm/stm32/b-g431b-esc1/src/CMakeLists.txt | 50 - boards/arm/stm32/b-g431b-esc1/src/Make.defs | 53 - .../stm32/b-g431b-esc1/src/stm32_autoleds.c | 80 - .../arm/stm32/b-g431b-esc1/src/stm32_boot.c | 95 - .../stm32/b-g431b-esc1/src/stm32_bringup.c | 185 - .../stm32/b-g431b-esc1/src/stm32_buttons.c | 113 - boards/arm/stm32/b-g431b-esc1/src/stm32_can.c | 105 - .../stm32/b-g431b-esc1/src/stm32_cansock.c | 84 - boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c | 766 ---- .../stm32/b-g431b-esc1/src/stm32_userleds.c | 77 - boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt | 23 - .../b-g474e-dpow1/configs/buckboost/defconfig | 89 - .../stm32/b-g474e-dpow1/configs/nsh/defconfig | 41 - .../b-g474e-dpow1/configs/ostest/defconfig | 43 - .../arm/stm32/b-g474e-dpow1/include/board.h | 256 -- .../arm/stm32/b-g474e-dpow1/scripts/Make.defs | 51 - .../arm/stm32/b-g474e-dpow1/scripts/ld.script | 139 - .../stm32/b-g474e-dpow1/scripts/ld.script.dfu | 142 - .../stm32/b-g474e-dpow1/src/CMakeLists.txt | 37 - boards/arm/stm32/b-g474e-dpow1/src/Make.defs | 40 - .../stm32/b-g474e-dpow1/src/stm32_autoleds.c | 111 - .../arm/stm32/b-g474e-dpow1/src/stm32_boot.c | 125 - .../arm/stm32/b-g474e-dpow1/src/stm32_smps.c | 1262 ------ .../stm32/b-g474e-dpow1/src/stm32_userleds.c | 124 - .../arm/stm32/clicker2-stm32/CMakeLists.txt | 23 - .../clicker2-stm32/configs/knsh/defconfig | 54 - .../configs/mrf24j40-6lowpan/defconfig | 108 - .../configs/mrf24j40-mac/defconfig | 60 - .../configs/mrf24j40-starhub/defconfig | 93 - .../configs/mrf24j40-starpoint/defconfig | 109 - .../clicker2-stm32/configs/nsh/defconfig | 49 - .../clicker2-stm32/configs/usbnsh/defconfig | 63 - .../configs/xbee-6lowpan/defconfig | 104 - .../arm/stm32/clicker2-stm32/include/board.h | 321 -- .../arm/stm32/clicker2-stm32/kernel/Makefile | 94 - .../clicker2-stm32/kernel/stm32_userspace.c | 113 - .../stm32/clicker2-stm32/scripts/Make.defs | 41 - .../arm/stm32/clicker2-stm32/scripts/flash.ld | 131 - .../clicker2-stm32/scripts/kernel-space.ld | 106 - .../stm32/clicker2-stm32/scripts/memory.ld | 87 - .../clicker2-stm32/scripts/user-space.ld | 108 - .../stm32/clicker2-stm32/src/CMakeLists.txt | 65 - boards/arm/stm32/clicker2-stm32/src/Make.defs | 67 - .../arm/stm32/clicker2-stm32/src/stm32_adc.c | 156 - .../stm32/clicker2-stm32/src/stm32_autoleds.c | 189 - .../arm/stm32/clicker2-stm32/src/stm32_boot.c | 139 - .../stm32/clicker2-stm32/src/stm32_bringup.c | 193 - .../stm32/clicker2-stm32/src/stm32_buttons.c | 123 - .../arm/stm32/clicker2-stm32/src/stm32_can.c | 100 - .../stm32/clicker2-stm32/src/stm32_mmcsd.c | 423 --- .../stm32/clicker2-stm32/src/stm32_mrf24j40.c | 328 -- .../arm/stm32/clicker2-stm32/src/stm32_spi.c | 268 -- .../arm/stm32/clicker2-stm32/src/stm32_usb.c | 96 - .../stm32/clicker2-stm32/src/stm32_userleds.c | 89 - boards/arm/stm32/cloudctrl/CMakeLists.txt | 23 - .../arm/stm32/cloudctrl/configs/nsh/defconfig | 78 - boards/arm/stm32/cloudctrl/include/board.h | 409 -- boards/arm/stm32/cloudctrl/scripts/Make.defs | 48 - boards/arm/stm32/cloudctrl/src/CMakeLists.txt | 67 - boards/arm/stm32/cloudctrl/src/Make.defs | 63 - boards/arm/stm32/cloudctrl/src/stm32_adc.c | 164 - .../arm/stm32/cloudctrl/src/stm32_autoleds.c | 376 -- boards/arm/stm32/cloudctrl/src/stm32_boot.c | 200 - .../arm/stm32/cloudctrl/src/stm32_buttons.c | 165 - boards/arm/stm32/cloudctrl/src/stm32_chipid.c | 79 - boards/arm/stm32/cloudctrl/src/stm32_relays.c | 274 -- boards/arm/stm32/cloudctrl/src/stm32_spi.c | 139 - boards/arm/stm32/cloudctrl/src/stm32_usb.c | 304 -- boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c | 71 - .../arm/stm32/cloudctrl/src/stm32_userleds.c | 96 - boards/arm/stm32/cloudctrl/src/stm32_w25.c | 144 - boards/arm/stm32/common | 1 - boards/arm/stm32/emw3162/CMakeLists.txt | 23 - .../arm/stm32/emw3162/configs/nsh/defconfig | 41 - .../arm/stm32/emw3162/configs/wlan/defconfig | 82 - boards/arm/stm32/emw3162/include/board.h | 218 -- boards/arm/stm32/emw3162/scripts/Make.defs | 41 - boards/arm/stm32/emw3162/scripts/ld.script | 130 - boards/arm/stm32/emw3162/src/CMakeLists.txt | 38 - boards/arm/stm32/emw3162/src/Make.defs | 40 - boards/arm/stm32/emw3162/src/stm32_autoleds.c | 101 - boards/arm/stm32/emw3162/src/stm32_boot.c | 80 - boards/arm/stm32/emw3162/src/stm32_bringup.c | 96 - boards/arm/stm32/emw3162/src/stm32_userleds.c | 74 - boards/arm/stm32/emw3162/src/stm32_wlan.c | 176 - .../arm/stm32/et-stm32-stamp/CMakeLists.txt | 23 - .../et-stm32-stamp/configs/nsh/defconfig | 35 - .../arm/stm32/et-stm32-stamp/include/board.h | 155 - .../stm32/et-stm32-stamp/scripts/Make.defs | 41 - .../stm32/et-stm32-stamp/scripts/ld.script | 123 - .../stm32/et-stm32-stamp/src/CMakeLists.txt | 27 - boards/arm/stm32/et-stm32-stamp/src/Make.defs | 29 - .../arm/stm32/et-stm32-stamp/src/stm32_boot.c | 83 - boards/arm/stm32/fire-stm32v2/CMakeLists.txt | 23 - .../stm32/fire-stm32v2/configs/nsh/defconfig | 88 - boards/arm/stm32/fire-stm32v2/include/board.h | 451 --- .../arm/stm32/fire-stm32v2/scripts/Make.defs | 48 - .../arm/stm32/fire-stm32v2/src/CMakeLists.txt | 59 - boards/arm/stm32/fire-stm32v2/src/Make.defs | 55 - .../stm32/fire-stm32v2/src/stm32_autoleds.c | 359 -- .../arm/stm32/fire-stm32v2/src/stm32_boot.c | 277 -- .../stm32/fire-stm32v2/src/stm32_buttons.c | 148 - .../stm32/fire-stm32v2/src/stm32_enc28j60.c | 222 -- .../arm/stm32/fire-stm32v2/src/stm32_mmcsd.c | 111 - .../stm32/fire-stm32v2/src/stm32_selectlcd.c | 182 - boards/arm/stm32/fire-stm32v2/src/stm32_spi.c | 181 - .../arm/stm32/fire-stm32v2/src/stm32_usbdev.c | 107 - .../arm/stm32/fire-stm32v2/src/stm32_usbmsc.c | 71 - .../stm32/fire-stm32v2/src/stm32_userleds.c | 104 - boards/arm/stm32/fire-stm32v2/src/stm32_w25.c | 144 - boards/arm/stm32/hymini-stm32v/CMakeLists.txt | 23 - .../stm32/hymini-stm32v/configs/nsh/defconfig | 47 - .../hymini-stm32v/configs/nsh2/defconfig | 90 - .../hymini-stm32v/configs/usbmsc/defconfig | 52 - .../hymini-stm32v/configs/usbnsh/defconfig | 48 - .../hymini-stm32v/configs/usbserial/defconfig | 36 - .../arm/stm32/hymini-stm32v/include/board.h | 242 -- .../arm/stm32/hymini-stm32v/scripts/Make.defs | 46 - .../arm/stm32/hymini-stm32v/scripts/ld.script | 122 - .../stm32/hymini-stm32v/src/CMakeLists.txt | 43 - boards/arm/stm32/hymini-stm32v/src/Make.defs | 45 - .../arm/stm32/hymini-stm32v/src/stm32_boot.c | 264 -- .../stm32/hymini-stm32v/src/stm32_buttons.c | 140 - .../arm/stm32/hymini-stm32v/src/stm32_leds.c | 224 -- .../arm/stm32/hymini-stm32v/src/stm32_spi.c | 148 - .../stm32/hymini-stm32v/src/stm32_ssd1289.c | 489 --- .../stm32/hymini-stm32v/src/stm32_usbdev.c | 105 - .../stm32/hymini-stm32v/src/stm32_usbmsc.c | 127 - boards/arm/stm32/maple/CMakeLists.txt | 23 - boards/arm/stm32/maple/configs/nsh/defconfig | 54 - boards/arm/stm32/maple/configs/nx/defconfig | 77 - .../arm/stm32/maple/configs/usbnsh/defconfig | 60 - boards/arm/stm32/maple/include/board.h | 190 - boards/arm/stm32/maple/scripts/Make.defs | 46 - boards/arm/stm32/maple/scripts/ld.script | 122 - boards/arm/stm32/maple/scripts/ld.script.dfu | 107 - boards/arm/stm32/maple/src/CMakeLists.txt | 43 - boards/arm/stm32/maple/src/Make.defs | 42 - boards/arm/stm32/maple/src/stm32_boot.c | 109 - boards/arm/stm32/maple/src/stm32_lcd.c | 198 - boards/arm/stm32/maple/src/stm32_leds.c | 120 - boards/arm/stm32/maple/src/stm32_spi.c | 138 - boards/arm/stm32/maple/src/stm32_usbdev.c | 103 - .../arm/stm32/mikroe-stm32f4/CMakeLists.txt | 23 - .../mikroe-stm32f4/configs/fulldemo/defconfig | 136 - .../mikroe-stm32f4/configs/kostest/defconfig | 83 - .../mikroe-stm32f4/configs/nsh/defconfig | 69 - .../stm32/mikroe-stm32f4/configs/nx/defconfig | 65 - .../mikroe-stm32f4/configs/nxlines/defconfig | 69 - .../mikroe-stm32f4/configs/nxtext/defconfig | 63 - .../mikroe-stm32f4/configs/usbnsh/defconfig | 74 - .../arm/stm32/mikroe-stm32f4/include/board.h | 251 -- .../arm/stm32/mikroe-stm32f4/kernel/Makefile | 94 - .../mikroe-stm32f4/kernel/stm32_userspace.c | 110 - .../stm32/mikroe-stm32f4/scripts/Make.defs | 41 - .../mikroe-stm32f4/scripts/kernel-space.ld | 100 - .../stm32/mikroe-stm32f4/scripts/ld.script | 126 - .../stm32/mikroe-stm32f4/scripts/memory.ld | 87 - .../mikroe-stm32f4/scripts/user-space.ld | 101 - .../stm32/mikroe-stm32f4/src/CMakeLists.txt | 67 - boards/arm/stm32/mikroe-stm32f4/src/Make.defs | 73 - .../arm/stm32/mikroe-stm32f4/src/stm32_boot.c | 467 --- .../stm32/mikroe-stm32f4/src/stm32_extmem.c | 141 - .../arm/stm32/mikroe-stm32f4/src/stm32_idle.c | 263 -- .../arm/stm32/mikroe-stm32f4/src/stm32_pm.c | 75 - .../arm/stm32/mikroe-stm32f4/src/stm32_pwm.c | 127 - .../arm/stm32/mikroe-stm32f4/src/stm32_spi.c | 246 -- .../mikroe-stm32f4/src/stm32_touchscreen.c | 1547 -------- .../arm/stm32/mikroe-stm32f4/src/stm32_usb.c | 304 -- boards/arm/stm32/nucleo-f103rb/CMakeLists.txt | 23 - .../stm32/nucleo-f103rb/configs/adc/defconfig | 53 - .../configs/ihm07m1_b16/defconfig | 85 - .../stm32/nucleo-f103rb/configs/nsh/defconfig | 42 - .../stm32/nucleo-f103rb/configs/pwm/defconfig | 49 - .../nucleo-f103rb/configs/qenco/defconfig | 55 - .../arm/stm32/nucleo-f103rb/include/board.h | 251 -- .../arm/stm32/nucleo-f103rb/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f103rb/scripts/ld.script | 127 - .../stm32/nucleo-f103rb/src/CMakeLists.txt | 51 - boards/arm/stm32/nucleo-f103rb/src/Make.defs | 53 - .../arm/stm32/nucleo-f103rb/src/stm32_adc.c | 242 -- .../stm32/nucleo-f103rb/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-f103rb/src/stm32_boot.c | 95 - .../stm32/nucleo-f103rb/src/stm32_bringup.c | 143 - .../stm32/nucleo-f103rb/src/stm32_buttons.c | 113 - .../nucleo-f103rb/src/stm32_foc_ihm07m1.c | 185 - .../arm/stm32/nucleo-f103rb/src/stm32_pwm.c | 110 - .../stm32/nucleo-f103rb/src/stm32_userleds.c | 77 - boards/arm/stm32/nucleo-f207zg/CMakeLists.txt | 23 - .../stm32/nucleo-f207zg/configs/adc/defconfig | 47 - .../stm32/nucleo-f207zg/configs/nsh/defconfig | 37 - .../stm32/nucleo-f207zg/configs/pwm/defconfig | 41 - .../arm/stm32/nucleo-f207zg/include/board.h | 209 - .../arm/stm32/nucleo-f207zg/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f207zg/scripts/ld.script | 124 - .../stm32/nucleo-f207zg/src/CMakeLists.txt | 49 - boards/arm/stm32/nucleo-f207zg/src/Make.defs | 51 - .../arm/stm32/nucleo-f207zg/src/stm32_adc.c | 243 -- .../stm32/nucleo-f207zg/src/stm32_autoleds.c | 171 - .../arm/stm32/nucleo-f207zg/src/stm32_boot.c | 87 - .../stm32/nucleo-f207zg/src/stm32_bringup.c | 92 - .../stm32/nucleo-f207zg/src/stm32_buttons.c | 107 - .../arm/stm32/nucleo-f207zg/src/stm32_pwm.c | 110 - .../arm/stm32/nucleo-f207zg/src/stm32_usb.c | 322 -- .../stm32/nucleo-f207zg/src/stm32_userleds.c | 127 - boards/arm/stm32/nucleo-f302r8/CMakeLists.txt | 23 - .../stm32/nucleo-f302r8/configs/can/defconfig | 54 - .../nucleo-f302r8/configs/cansock/defconfig | 67 - .../nucleo-f302r8/configs/highpri/defconfig | 58 - .../configs/ihm07m1_b16/defconfig | 87 - .../configs/ihm07m1_f32/defconfig | 86 - .../stm32/nucleo-f302r8/configs/nsh/defconfig | 85 - .../nucleo-f302r8/configs/qenco/defconfig | 111 - .../arm/stm32/nucleo-f302r8/include/board.h | 308 -- .../arm/stm32/nucleo-f302r8/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f302r8/scripts/ld.script | 127 - .../stm32/nucleo-f302r8/src/CMakeLists.txt | 62 - boards/arm/stm32/nucleo-f302r8/src/Make.defs | 64 - .../arm/stm32/nucleo-f302r8/src/stm32_adc.c | 112 - .../stm32/nucleo-f302r8/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-f302r8/src/stm32_boot.c | 95 - .../stm32/nucleo-f302r8/src/stm32_bringup.c | 188 - .../stm32/nucleo-f302r8/src/stm32_buttons.c | 113 - .../arm/stm32/nucleo-f302r8/src/stm32_can.c | 73 - .../stm32/nucleo-f302r8/src/stm32_cansock.c | 59 - .../nucleo-f302r8/src/stm32_foc_ihm07m1.c | 183 - .../stm32/nucleo-f302r8/src/stm32_highpri.c | 544 --- .../arm/stm32/nucleo-f302r8/src/stm32_pwm.c | 110 - .../stm32/nucleo-f302r8/src/stm32_userleds.c | 77 - boards/arm/stm32/nucleo-f303re/CMakeLists.txt | 23 - .../stm32/nucleo-f303re/configs/adc/defconfig | 47 - .../stm32/nucleo-f303re/configs/can/defconfig | 39 - .../nucleo-f303re/configs/hello/defconfig | 35 - .../stm32/nucleo-f303re/configs/nsh/defconfig | 35 - .../nucleo-f303re/configs/nxlines/defconfig | 47 - .../stm32/nucleo-f303re/configs/pwm/defconfig | 46 - .../nucleo-f303re/configs/serialrx/defconfig | 38 - .../arm/stm32/nucleo-f303re/include/board.h | 241 -- .../arm/stm32/nucleo-f303re/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f303re/scripts/ld.script | 121 - .../stm32/nucleo-f303re/src/CMakeLists.txt | 69 - boards/arm/stm32/nucleo-f303re/src/Make.defs | 71 - .../arm/stm32/nucleo-f303re/src/stm32_adc.c | 374 -- .../stm32/nucleo-f303re/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-f303re/src/stm32_boot.c | 171 - .../stm32/nucleo-f303re/src/stm32_buttons.c | 113 - .../arm/stm32/nucleo-f303re/src/stm32_can.c | 81 - .../arm/stm32/nucleo-f303re/src/stm32_pwm.c | 89 - .../arm/stm32/nucleo-f303re/src/stm32_spi.c | 195 - .../stm32/nucleo-f303re/src/stm32_ssd1351.c | 118 - .../arm/stm32/nucleo-f303re/src/stm32_timer.c | 67 - .../arm/stm32/nucleo-f303re/src/stm32_uid.c | 68 - .../stm32/nucleo-f303re/src/stm32_userleds.c | 77 - boards/arm/stm32/nucleo-f303ze/CMakeLists.txt | 23 - .../stm32/nucleo-f303ze/configs/adc/defconfig | 52 - .../stm32/nucleo-f303ze/configs/nsh/defconfig | 38 - .../configs/nxlines_oled/defconfig | 53 - .../arm/stm32/nucleo-f303ze/include/board.h | 207 - .../arm/stm32/nucleo-f303ze/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f303ze/scripts/ld.script | 121 - .../stm32/nucleo-f303ze/src/CMakeLists.txt | 45 - boards/arm/stm32/nucleo-f303ze/src/Make.defs | 47 - .../arm/stm32/nucleo-f303ze/src/stm32_adc.c | 243 -- .../stm32/nucleo-f303ze/src/stm32_autoleds.c | 171 - .../arm/stm32/nucleo-f303ze/src/stm32_boot.c | 81 - .../stm32/nucleo-f303ze/src/stm32_bringup.c | 71 - .../stm32/nucleo-f303ze/src/stm32_buttons.c | 107 - .../arm/stm32/nucleo-f303ze/src/stm32_lcd.c | 89 - .../stm32/nucleo-f303ze/src/stm32_userleds.c | 127 - boards/arm/stm32/nucleo-f334r8/CMakeLists.txt | 23 - .../stm32/nucleo-f334r8/configs/adc/defconfig | 95 - .../nucleo-f334r8/configs/highpri/defconfig | 62 - .../stm32/nucleo-f334r8/configs/nsh/defconfig | 86 - .../nucleo-f334r8/configs/spwm1/defconfig | 73 - .../nucleo-f334r8/configs/spwm2/defconfig | 64 - .../arm/stm32/nucleo-f334r8/include/board.h | 344 -- .../arm/stm32/nucleo-f334r8/scripts/Make.defs | 41 - .../arm/stm32/nucleo-f334r8/scripts/ld.script | 127 - .../stm32/nucleo-f334r8/src/CMakeLists.txt | 59 - boards/arm/stm32/nucleo-f334r8/src/Make.defs | 61 - .../arm/stm32/nucleo-f334r8/src/stm32_adc.c | 242 -- .../stm32/nucleo-f334r8/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-f334r8/src/stm32_boot.c | 162 - .../arm/stm32/nucleo-f334r8/src/stm32_comp.c | 122 - .../stm32/nucleo-f334r8/src/stm32_highpri.c | 586 --- .../arm/stm32/nucleo-f334r8/src/stm32_hrtim.c | 86 - .../arm/stm32/nucleo-f334r8/src/stm32_opamp.c | 86 - boards/arm/stm32/nucleo-f401re/CMakeLists.txt | 23 - .../stm32/nucleo-f401re/configs/fb/defconfig | 62 - .../stm32/nucleo-f401re/configs/nsh/defconfig | 48 - .../arm/stm32/nucleo-f401re/include/board.h | 380 -- .../arm/stm32/nucleo-f401re/scripts/Make.defs | 43 - .../arm/stm32/nucleo-f401re/scripts/flash.ld | 109 - .../stm32/nucleo-f401re/src/CMakeLists.txt | 54 - boards/arm/stm32/nucleo-f401re/src/Make.defs | 56 - .../arm/stm32/nucleo-f401re/src/stm32_adc.c | 142 - .../stm32/nucleo-f401re/src/stm32_ajoystick.c | 490 --- .../stm32/nucleo-f401re/src/stm32_autoleds.c | 83 - .../arm/stm32/nucleo-f401re/src/stm32_boot.c | 101 - .../stm32/nucleo-f401re/src/stm32_bringup.c | 212 -- .../stm32/nucleo-f401re/src/stm32_buttons.c | 117 - .../nucleo-f401re/src/stm32_lcd_ssd1306.c | 88 - .../stm32/nucleo-f401re/src/stm32_mcp2515.c | 241 -- .../arm/stm32/nucleo-f401re/src/stm32_spi.c | 246 -- .../stm32/nucleo-f401re/src/stm32_userleds.c | 218 -- boards/arm/stm32/nucleo-f410rb/CMakeLists.txt | 23 - .../stm32/nucleo-f410rb/configs/nsh/defconfig | 57 - .../arm/stm32/nucleo-f410rb/include/board.h | 303 -- .../arm/stm32/nucleo-f410rb/scripts/Make.defs | 41 - .../stm32/nucleo-f410rb/src/CMakeLists.txt | 41 - boards/arm/stm32/nucleo-f410rb/src/Make.defs | 43 - .../arm/stm32/nucleo-f410rb/src/stm32_adc.c | 142 - .../stm32/nucleo-f410rb/src/stm32_autoleds.c | 82 - .../arm/stm32/nucleo-f410rb/src/stm32_boot.c | 95 - .../stm32/nucleo-f410rb/src/stm32_bringup.c | 70 - .../stm32/nucleo-f410rb/src/stm32_buttons.c | 115 - .../stm32/nucleo-f410rb/src/stm32_userleds.c | 197 - boards/arm/stm32/nucleo-f411re/CMakeLists.txt | 23 - .../configs/mcp2515-extid/defconfig | 58 - .../stm32/nucleo-f411re/configs/nsh/defconfig | 49 - .../arm/stm32/nucleo-f411re/include/board.h | 377 -- .../arm/stm32/nucleo-f411re/scripts/Make.defs | 43 - .../arm/stm32/nucleo-f411re/scripts/flash.ld | 121 - .../stm32/nucleo-f411re/src/CMakeLists.txt | 54 - boards/arm/stm32/nucleo-f411re/src/Make.defs | 56 - .../arm/stm32/nucleo-f411re/src/stm32_adc.c | 142 - .../stm32/nucleo-f411re/src/stm32_ajoystick.c | 490 --- .../stm32/nucleo-f411re/src/stm32_autoleds.c | 83 - .../arm/stm32/nucleo-f411re/src/stm32_boot.c | 101 - .../stm32/nucleo-f411re/src/stm32_bringup.c | 212 -- .../stm32/nucleo-f411re/src/stm32_buttons.c | 117 - .../nucleo-f411re/src/stm32_lcd_ssd1306.c | 88 - .../stm32/nucleo-f411re/src/stm32_mcp2515.c | 241 -- .../arm/stm32/nucleo-f411re/src/stm32_spi.c | 246 -- .../stm32/nucleo-f411re/src/stm32_userleds.c | 218 -- boards/arm/stm32/nucleo-f412zg/CMakeLists.txt | 23 - .../nucleo-f412zg/configs/coremark/defconfig | 51 - .../stm32/nucleo-f412zg/configs/nsh/defconfig | 59 - .../nucleo-f412zg/configs/ostest/defconfig | 60 - .../arm/stm32/nucleo-f412zg/include/board.h | 228 -- .../arm/stm32/nucleo-f412zg/scripts/Make.defs | 42 - .../stm32/nucleo-f412zg/src/CMakeLists.txt | 35 - boards/arm/stm32/nucleo-f412zg/src/Make.defs | 38 - .../stm32/nucleo-f412zg/src/stm32_autoleds.c | 104 - .../arm/stm32/nucleo-f412zg/src/stm32_boot.c | 100 - .../stm32/nucleo-f412zg/src/stm32_bringup.c | 84 - .../arm/stm32/nucleo-f412zg/src/stm32_usb.c | 352 -- boards/arm/stm32/nucleo-f429zi/CMakeLists.txt | 23 - .../nucleo-f429zi/configs/netnsh/defconfig | 81 - .../stm32/nucleo-f429zi/configs/nsh/defconfig | 48 - .../nucleo-f429zi/configs/trace/defconfig | 89 - .../arm/stm32/nucleo-f429zi/include/board.h | 376 -- .../arm/stm32/nucleo-f429zi/scripts/Make.defs | 41 - .../nucleo-f429zi/scripts/kernel-space.ld | 100 - .../arm/stm32/nucleo-f429zi/scripts/ld.script | 133 - .../arm/stm32/nucleo-f429zi/scripts/memory.ld | 88 - .../stm32/nucleo-f429zi/scripts/user-space.ld | 114 - .../stm32/nucleo-f429zi/src/CMakeLists.txt | 73 - boards/arm/stm32/nucleo-f429zi/src/Make.defs | 75 - .../arm/stm32/nucleo-f429zi/src/stm32_adc.c | 169 - .../stm32/nucleo-f429zi/src/stm32_autoleds.c | 170 - .../arm/stm32/nucleo-f429zi/src/stm32_boot.c | 252 -- .../stm32/nucleo-f429zi/src/stm32_buttons.c | 110 - .../arm/stm32/nucleo-f429zi/src/stm32_gpio.c | 323 -- .../arm/stm32/nucleo-f429zi/src/stm32_pwm.c | 149 - .../arm/stm32/nucleo-f429zi/src/stm32_reset.c | 64 - .../arm/stm32/nucleo-f429zi/src/stm32_romfs.h | 63 - .../src/stm32_romfs_initialize.c | 141 - .../arm/stm32/nucleo-f429zi/src/stm32_sdio.c | 163 - .../arm/stm32/nucleo-f429zi/src/stm32_spi.c | 496 --- .../arm/stm32/nucleo-f429zi/src/stm32_usb.c | 322 -- .../stm32/nucleo-f429zi/src/stm32_userleds.c | 128 - boards/arm/stm32/nucleo-f446re/CMakeLists.txt | 23 - .../stm32/nucleo-f446re/configs/adc/defconfig | 56 - .../stm32/nucleo-f446re/configs/can/defconfig | 57 - .../nucleo-f446re/configs/cansock/defconfig | 71 - .../stm32/nucleo-f446re/configs/dac/defconfig | 55 - .../nucleo-f446re/configs/gpio/defconfig | 51 - .../configs/ihm08m1_b16/defconfig | 90 - .../configs/ihm08m1_f32/defconfig | 90 - .../nucleo-f446re/configs/jumbo/defconfig | 54 - .../stm32/nucleo-f446re/configs/lcd/defconfig | 58 - .../stm32/nucleo-f446re/configs/nsh/defconfig | 51 - .../stm32/nucleo-f446re/configs/pwm/defconfig | 55 - .../nucleo-f446re/configs/qenco/defconfig | 50 - .../configs/systemview/defconfig | 51 - .../arm/stm32/nucleo-f446re/include/board.h | 444 --- .../arm/stm32/nucleo-f446re/scripts/Make.defs | 42 - .../stm32/nucleo-f446re/src/CMakeLists.txt | 79 - boards/arm/stm32/nucleo-f446re/src/Make.defs | 81 - .../arm/stm32/nucleo-f446re/src/stm32_adc.c | 142 - .../stm32/nucleo-f446re/src/stm32_ajoystick.c | 491 --- .../stm32/nucleo-f446re/src/stm32_autoleds.c | 82 - .../arm/stm32/nucleo-f446re/src/stm32_boot.c | 103 - .../stm32/nucleo-f446re/src/stm32_bringup.c | 302 -- .../stm32/nucleo-f446re/src/stm32_buttons.c | 115 - .../arm/stm32/nucleo-f446re/src/stm32_can.c | 117 - .../stm32/nucleo-f446re/src/stm32_cansock.c | 85 - .../arm/stm32/nucleo-f446re/src/stm32_dac.c | 112 - .../arm/stm32/nucleo-f446re/src/stm32_gpio.c | 343 -- .../arm/stm32/nucleo-f446re/src/stm32_pwm.c | 134 - .../arm/stm32/nucleo-f446re/src/stm32_romfs.h | 63 - .../src/stm32_romfs_initialize.c | 141 - .../arm/stm32/nucleo-f446re/src/stm32_spi.c | 236 -- .../stm32/nucleo-f446re/src/stm32_userleds.c | 105 - boards/arm/stm32/nucleo-g431kb/CMakeLists.txt | 23 - .../nucleo-g431kb/configs/comp/defconfig | 48 - .../stm32/nucleo-g431kb/configs/nsh/defconfig | 47 - .../stm32/nucleo-g431kb/configs/pwm/defconfig | 40 - .../arm/stm32/nucleo-g431kb/include/board.h | 258 -- .../arm/stm32/nucleo-g431kb/scripts/Make.defs | 51 - .../arm/stm32/nucleo-g431kb/scripts/ld.script | 139 - .../stm32/nucleo-g431kb/src/CMakeLists.txt | 45 - boards/arm/stm32/nucleo-g431kb/src/Make.defs | 48 - .../stm32/nucleo-g431kb/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-g431kb/src/stm32_boot.c | 95 - .../stm32/nucleo-g431kb/src/stm32_bringup.c | 112 - .../arm/stm32/nucleo-g431kb/src/stm32_comp.c | 148 - .../arm/stm32/nucleo-g431kb/src/stm32_dac.c | 114 - .../arm/stm32/nucleo-g431kb/src/stm32_pwm.c | 86 - .../stm32/nucleo-g431kb/src/stm32_userleds.c | 77 - boards/arm/stm32/nucleo-g431rb/CMakeLists.txt | 23 - .../stm32/nucleo-g431rb/configs/adc/defconfig | 91 - .../stm32/nucleo-g431rb/configs/can/defconfig | 54 - .../nucleo-g431rb/configs/cansock/defconfig | 59 - .../nucleo-g431rb/configs/cordic/defconfig | 51 - .../configs/ihm16m1_b16/defconfig | 87 - .../configs/ihm16m1_f32/defconfig | 87 - .../stm32/nucleo-g431rb/configs/nsh/defconfig | 48 - .../stm32/nucleo-g431rb/configs/pwm/defconfig | 61 - .../nucleo-g431rb/configs/qenco/defconfig | 56 - .../arm/stm32/nucleo-g431rb/include/board.h | 399 -- .../arm/stm32/nucleo-g431rb/scripts/Make.defs | 51 - .../arm/stm32/nucleo-g431rb/scripts/ld.script | 139 - .../stm32/nucleo-g431rb/src/CMakeLists.txt | 64 - boards/arm/stm32/nucleo-g431rb/src/Make.defs | 67 - .../arm/stm32/nucleo-g431rb/src/stm32_adc.c | 240 -- .../stm32/nucleo-g431rb/src/stm32_autoleds.c | 80 - .../arm/stm32/nucleo-g431rb/src/stm32_boot.c | 95 - .../stm32/nucleo-g431rb/src/stm32_bringup.c | 185 - .../stm32/nucleo-g431rb/src/stm32_buttons.c | 113 - .../arm/stm32/nucleo-g431rb/src/stm32_can.c | 91 - .../stm32/nucleo-g431rb/src/stm32_cansock.c | 59 - .../arm/stm32/nucleo-g431rb/src/stm32_pwm.c | 86 - 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boards/arm/stm32/odrive36/src/stm32_bringup.c | 140 - boards/arm/stm32/odrive36/src/stm32_foc.c | 962 ----- boards/arm/stm32/odrive36/src/stm32_spi.c | 198 - boards/arm/stm32/odrive36/src/stm32_usb.c | 105 - .../stm32/olimex-stm32-e407/CMakeLists.txt | 23 - .../configs/bmp180/defconfig | 56 - .../olimex-stm32-e407/configs/dac/defconfig | 57 - .../configs/discover/defconfig | 70 - .../configs/ina219/defconfig | 57 - .../configs/mrf24j40-6lowpan/defconfig | 103 - .../configs/mrf24j40-mac/defconfig | 62 - .../configs/netnsh/defconfig | 75 - .../olimex-stm32-e407/configs/nsh/defconfig | 48 - .../configs/telnetd/defconfig | 78 - .../olimex-stm32-e407/configs/timer/defconfig | 53 - .../configs/usbnsh/defconfig | 54 - .../configs/webserver/defconfig | 72 - .../stm32/olimex-stm32-e407/include/board.h | 280 -- .../stm32/olimex-stm32-e407/scripts/Make.defs | 46 - .../olimex-stm32-e407/src/CMakeLists.txt | 77 - .../arm/stm32/olimex-stm32-e407/src/Make.defs | 75 - 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.../configs/kostest/Make.defs | 42 - .../configs/kostest/defconfig | 50 - .../configs/lcd1602/defconfig | 55 - .../stm32f4discovery/configs/lwl/defconfig | 46 - .../configs/max31855/defconfig | 53 - .../configs/max7219/defconfig | 91 - .../configs/mmcsdspi/defconfig | 70 - .../configs/modbus_slave/defconfig | 61 - .../stm32f4discovery/configs/module/defconfig | 51 - .../configs/mpr121_keypad/defconfig | 57 - .../stm32f4discovery/configs/mt6816/defconfig | 55 - .../stm32f4discovery/configs/netnsh/defconfig | 91 - .../stm32f4discovery/configs/nsh/defconfig | 49 - .../configs/nxlines/defconfig | 72 - .../configs/nxscope_cdcacm/defconfig | 61 - .../stm32f4discovery/configs/pm/defconfig | 55 - .../configs/posix_spawn/defconfig | 48 - .../configs/pseudoterm/defconfig | 53 - .../stm32f4discovery/configs/rgbled/defconfig | 62 - .../stm32f4discovery/configs/rndis/defconfig | 92 - .../configs/sbutton/defconfig | 55 - .../configs/sporadic/defconfig | 49 - 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.../stm32/stm32f4discovery/src/stm32_boot.c | 118 - .../stm32f4discovery/src/stm32_bringup.c | 703 ---- .../stm32f4discovery/src/stm32_buttons.c | 151 - .../stm32/stm32f4discovery/src/stm32_can.c | 102 - .../stm32f4discovery/src/stm32_composite.c | 349 -- .../stm32f4discovery/src/stm32_djoystick.c | 299 -- .../stm32f4discovery/src/stm32_enc28j60.c | 219 -- .../stm32/stm32f4discovery/src/stm32_extmem.c | 140 - .../stm32/stm32f4discovery/src/stm32_hx711.c | 104 - .../stm32/stm32f4discovery/src/stm32_idle.c | 260 -- .../stm32f4discovery/src/stm32_max7219.c | 114 - .../stm32/stm32f4discovery/src/stm32_mmcsd.c | 106 - .../stm32f4discovery/src/stm32_netinit.c | 41 - .../arm/stm32/stm32f4discovery/src/stm32_pm.c | 75 - .../stm32f4discovery/src/stm32_pmbuttons.c | 122 - .../stm32/stm32f4discovery/src/stm32_pwm.c | 125 - .../stm32/stm32f4discovery/src/stm32_reset.c | 64 - .../stm32/stm32f4discovery/src/stm32_rgbled.c | 173 - .../stm32/stm32f4discovery/src/stm32_romfs.h | 77 - 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.../viewtool-stm32f107/configs/nsh/defconfig | 40 - .../configs/tcpblaster/defconfig | 62 - .../stm32/viewtool-stm32f107/include/board.h | 166 - .../viewtool-stm32f107/scripts/Make.defs | 46 - .../stm32/viewtool-stm32f107/scripts/dfu.ld | 118 - .../stm32/viewtool-stm32f107/scripts/flash.ld | 118 - .../viewtool-stm32f107/src/CMakeLists.txt | 79 - .../stm32/viewtool-stm32f107/src/Make.defs | 77 - .../stm32/viewtool-stm32f107/src/stm32_boot.c | 99 - .../viewtool-stm32f107/src/stm32_bringup.c | 202 - .../viewtool-stm32f107/src/stm32_buttons.c | 153 - .../stm32/viewtool-stm32f107/src/stm32_can.c | 103 - .../viewtool-stm32f107/src/stm32_highpri.c | 277 -- .../stm32/viewtool-stm32f107/src/stm32_leds.c | 280 -- .../viewtool-stm32f107/src/stm32_mmcsd.c | 121 - .../stm32/viewtool-stm32f107/src/stm32_spi.c | 210 - .../viewtool-stm32f107/src/stm32_ssd1289.c | 568 --- .../viewtool-stm32f107/src/stm32_usbdev.c | 113 - .../viewtool-stm32f107/src/stm32_usbmsc.c | 73 - boards/arm/stm32f1/cloudctrl/CMakeLists.txt | 23 + .../arm/{stm32 => stm32f1}/cloudctrl/Kconfig | 0 .../stm32f1/cloudctrl/configs/nsh/defconfig | 79 + boards/arm/stm32f1/cloudctrl/include/board.h | 409 ++ .../arm/stm32f1/cloudctrl/scripts/Make.defs | 48 + .../cloudctrl/scripts/cloudctrl-dfu.ld | 2 +- .../cloudctrl/scripts/cloudctrl.ld | 2 +- .../arm/stm32f1/cloudctrl/src/CMakeLists.txt | 67 + boards/arm/stm32f1/cloudctrl/src/Make.defs | 63 + .../cloudctrl/src/cloudctrl.h | 2 +- boards/arm/stm32f1/cloudctrl/src/stm32_adc.c | 164 + .../stm32f1/cloudctrl/src/stm32_autoleds.c | 376 ++ boards/arm/stm32f1/cloudctrl/src/stm32_boot.c | 200 + .../arm/stm32f1/cloudctrl/src/stm32_buttons.c | 165 + .../arm/stm32f1/cloudctrl/src/stm32_chipid.c | 79 + .../cloudctrl/src/stm32_phyinit.c | 2 +- .../arm/stm32f1/cloudctrl/src/stm32_relays.c | 274 ++ boards/arm/stm32f1/cloudctrl/src/stm32_spi.c | 139 + boards/arm/stm32f1/cloudctrl/src/stm32_usb.c | 304 ++ .../arm/stm32f1/cloudctrl/src/stm32_usbmsc.c | 71 + .../stm32f1/cloudctrl/src/stm32_userleds.c | 96 + boards/arm/stm32f1/cloudctrl/src/stm32_w25.c | 144 + .../cloudctrl/tools/olimex-arm-usb-ocd.cfg | 0 .../cloudctrl/tools/oocd.sh | 0 .../cloudctrl/tools/stm32.cfg | 0 .../cloudctrl/tools/usb-driver.txt | 0 boards/arm/stm32f1/common/CMakeLists.txt | 23 + boards/arm/stm32f1/common/Kconfig | 6 + boards/arm/stm32f1/common/Makefile | 39 + .../arm/stm32f1/et-stm32-stamp/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/et-stm32-stamp/Kconfig | 0 .../et-stm32-stamp/configs/nsh/defconfig | 36 + .../stm32f1/et-stm32-stamp/include/board.h | 155 + .../stm32f1/et-stm32-stamp/scripts/Make.defs | 41 + .../stm32f1/et-stm32-stamp/scripts/ld.script | 123 + .../stm32f1/et-stm32-stamp/src/CMakeLists.txt | 27 + .../arm/stm32f1/et-stm32-stamp/src/Make.defs | 29 + .../et-stm32-stamp/src/et-stm32-stamp.h | 4 +- .../stm32f1/et-stm32-stamp/src/stm32_boot.c | 83 + .../arm/stm32f1/fire-stm32v2/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/fire-stm32v2/Kconfig | 0 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| 2 +- .../stm32f1/hymini-stm32v/src/stm32_usbdev.c | 105 + .../stm32f1/hymini-stm32v/src/stm32_usbmsc.c | 127 + boards/arm/stm32f1/maple/CMakeLists.txt | 23 + boards/arm/{stm32 => stm32f1}/maple/Kconfig | 0 .../arm/stm32f1/maple/configs/nsh/defconfig | 55 + boards/arm/stm32f1/maple/configs/nx/defconfig | 78 + .../stm32f1/maple/configs/usbnsh/defconfig | 61 + boards/arm/stm32f1/maple/include/board.h | 190 + boards/arm/stm32f1/maple/scripts/Make.defs | 46 + boards/arm/stm32f1/maple/scripts/ld.script | 122 + .../arm/stm32f1/maple/scripts/ld.script.dfu | 107 + boards/arm/stm32f1/maple/src/CMakeLists.txt | 43 + boards/arm/stm32f1/maple/src/Make.defs | 42 + .../arm/{stm32 => stm32f1}/maple/src/maple.h | 4 +- boards/arm/stm32f1/maple/src/stm32_boot.c | 109 + boards/arm/stm32f1/maple/src/stm32_lcd.c | 198 + boards/arm/stm32f1/maple/src/stm32_leds.c | 120 + boards/arm/stm32f1/maple/src/stm32_spi.c | 138 + boards/arm/stm32f1/maple/src/stm32_usbdev.c | 103 + .../arm/{stm32 => stm32f1}/maple/tools/dfu.sh | 0 .../arm/{stm32 => stm32f1}/maple/tools/env.sh | 0 .../arm/stm32f1/nucleo-f103rb/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/nucleo-f103rb/Kconfig | 0 .../nucleo-f103rb/configs/adc/defconfig | 54 + .../configs/ihm07m1_b16/defconfig | 86 + .../nucleo-f103rb/configs/nsh/defconfig | 43 + .../nucleo-f103rb/configs/pwm/defconfig | 50 + .../nucleo-f103rb/configs/qenco/defconfig | 56 + .../arm/stm32f1/nucleo-f103rb/include/board.h | 251 ++ .../stm32f1/nucleo-f103rb/scripts/Make.defs | 41 + .../stm32f1/nucleo-f103rb/scripts/ld.script | 127 + .../stm32f1/nucleo-f103rb/src/CMakeLists.txt | 51 + .../arm/stm32f1/nucleo-f103rb/src/Make.defs | 53 + .../nucleo-f103rb/src/nucleo-f103rb.h | 2 +- .../arm/stm32f1/nucleo-f103rb/src/stm32_adc.c | 242 ++ .../nucleo-f103rb/src/stm32_autoleds.c | 80 + .../stm32f1/nucleo-f103rb/src/stm32_boot.c | 95 + .../stm32f1/nucleo-f103rb/src/stm32_bringup.c | 143 + .../stm32f1/nucleo-f103rb/src/stm32_buttons.c | 113 + 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.../arm/stm32f1/shenzhou/src/stm32_relays.c | 274 ++ boards/arm/stm32f1/shenzhou/src/stm32_spi.c | 189 + .../arm/stm32f1/shenzhou/src/stm32_ssd1289.c | 597 +++ .../stm32f1/shenzhou/src/stm32_touchscreen.c | 276 ++ boards/arm/stm32f1/shenzhou/src/stm32_usb.c | 304 ++ .../arm/stm32f1/shenzhou/src/stm32_usbmsc.c | 72 + .../arm/stm32f1/shenzhou/src/stm32_userleds.c | 96 + boards/arm/stm32f1/shenzhou/src/stm32_w25.c | 145 + .../shenzhou/tools/olimex-arm-usb-ocd.cfg | 0 boards/arm/stm32f1/shenzhou/tools/oocd.sh | 90 + .../shenzhou/tools/stm32.cfg | 0 .../shenzhou/tools/usb-driver.txt | 0 .../arm/stm32f1/stm3210e-eval/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/stm3210e-eval/Kconfig | 0 .../stm3210e-eval/configs/composite/defconfig | 66 + .../stm3210e-eval/configs/nsh/defconfig | 53 + .../stm3210e-eval/configs/nsh2/defconfig | 110 + .../stm3210e-eval/configs/nx/defconfig | 72 + .../stm3210e-eval/configs/nxterm/defconfig | 68 + .../stm3210e-eval/configs/pm/defconfig | 95 + .../stm3210e-eval/configs/usbmsc/defconfig | 55 + .../stm3210e-eval/configs/usbserial/defconfig | 41 + .../arm/stm32f1/stm3210e-eval/include/board.h | 402 ++ .../stm32f1/stm3210e-eval/scripts/Make.defs | 46 + .../stm32f1/stm3210e-eval/scripts/ld.script | 122 + .../stm3210e-eval/scripts/ld.script.dfu | 118 + .../stm32f1/stm3210e-eval/src/CMakeLists.txt | 70 + .../arm/stm32f1/stm3210e-eval/src/Make.defs | 71 + .../stm3210e-eval/src/stm3210e-eval.h | 4 +- .../arm/stm32f1/stm3210e-eval/src/stm32_adc.c | 153 + .../stm32f1/stm3210e-eval/src/stm32_boot.c | 118 + .../stm32f1/stm3210e-eval/src/stm32_bringup.c | 317 ++ .../stm32f1/stm3210e-eval/src/stm32_buttons.c | 171 + .../arm/stm32f1/stm3210e-eval/src/stm32_can.c | 95 + .../stm3210e-eval/src/stm32_composite.c | 450 +++ .../stm3210e-eval/src/stm32_deselectlcd.c | 80 + .../stm3210e-eval/src/stm32_deselectnor.c | 2 +- .../stm3210e-eval/src/stm32_deselectsram.c | 80 + .../stm3210e-eval/src/stm32_djoystick.c | 299 ++ .../stm3210e-eval/src/stm32_extcontext.c | 2 +- .../stm32f1/stm3210e-eval/src/stm32_extmem.c | 137 + .../stm32f1/stm3210e-eval/src/stm32_idle.c | 437 +++ .../arm/stm32f1/stm3210e-eval/src/stm32_lcd.c | 1841 +++++++++ .../stm32f1/stm3210e-eval/src/stm32_leds.c | 372 ++ .../arm/stm32f1/stm3210e-eval/src/stm32_pm.c | 75 + .../stm3210e-eval/src/stm32_pmbuttons.c | 181 + .../stm3210e-eval/src/stm32_selectlcd.c | 134 + .../stm3210e-eval/src/stm32_selectnor.c | 2 +- .../stm3210e-eval/src/stm32_selectsram.c | 133 + .../arm/stm32f1/stm3210e-eval/src/stm32_spi.c | 146 + .../stm32f1/stm3210e-eval/src/stm32_usbdev.c | 102 + .../stm32f1/stm3210e-eval/src/stm32_usbmsc.c | 141 + .../tools/olimex-arm-usb-ocd.cfg | 0 .../arm/stm32f1/stm3210e-eval/tools/oocd.sh | 87 + .../stm3210e-eval/tools/stm32.cfg | 0 .../stm3210e-eval/tools/usb-driver.txt | 0 boards/arm/stm32f1/stm32_tiny/CMakeLists.txt | 23 + .../arm/{stm32 => stm32f1}/stm32_tiny/Kconfig | 0 .../stm32f1/stm32_tiny/configs/nsh/defconfig | 58 + .../stm32_tiny/configs/usbnsh/defconfig | 56 + boards/arm/stm32f1/stm32_tiny/include/board.h | 182 + .../arm/stm32f1/stm32_tiny/scripts/Make.defs | 41 + .../arm/stm32f1/stm32_tiny/scripts/ld.script | 122 + .../arm/stm32f1/stm32_tiny/src/CMakeLists.txt | 31 + boards/arm/stm32f1/stm32_tiny/src/Make.defs | 33 + .../arm/stm32f1/stm32_tiny/src/stm32_boot.c | 129 + .../arm/stm32f1/stm32_tiny/src/stm32_leds.c | 110 + boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c | 103 + boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c | 151 + .../stm32_tiny/src/stm32_tiny.h | 2 +- .../arm/stm32f1/stm32_tiny/src/stm32_usbdev.c | 106 + .../stm32f1/stm32butterfly2/CMakeLists.txt | 23 + .../stm32butterfly2/Kconfig | 0 .../stm32butterfly2/configs/nsh/defconfig | 72 + .../stm32butterfly2/configs/nshnet/defconfig | 91 + .../configs/nshusbdev/defconfig | 71 + .../configs/nshusbhost/defconfig | 72 + .../stm32f1/stm32butterfly2/include/board.h | 219 ++ .../stm32f1/stm32butterfly2/scripts/Make.defs | 46 + .../stm32f1/stm32butterfly2/scripts/dfu.ld | 118 + .../stm32f1/stm32butterfly2/scripts/flash.ld | 118 + .../stm32butterfly2/src/CMakeLists.txt | 55 + .../arm/stm32f1/stm32butterfly2/src/Make.defs | 57 + .../stm32f1/stm32butterfly2/src/stm32_adc.c | 78 + .../stm32f1/stm32butterfly2/src/stm32_boot.c | 100 + .../stm32butterfly2/src/stm32_butterfly2.h | 2 +- .../stm32butterfly2/src/stm32_buttons.c | 99 + .../stm32f1/stm32butterfly2/src/stm32_leds.c | 257 ++ .../stm32f1/stm32butterfly2/src/stm32_mmcsd.c | 203 + .../stm32f1/stm32butterfly2/src/stm32_spi.c | 98 + .../stm32f1/stm32butterfly2/src/stm32_usb.c | 51 + .../stm32butterfly2/src/stm32_usbdev.c | 65 + .../stm32butterfly2/src/stm32_usbhost.c | 187 + .../stm32f1/stm32f103-minimum/CMakeLists.txt | 23 + .../stm32f103-minimum/Kconfig | 0 .../stm32f103-minimum/configs/adb/defconfig | 79 + .../configs/apds9960/defconfig | 61 + .../configs/audio_tone/defconfig | 62 + .../configs/buttons/defconfig | 59 + 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++ .../stm32f103-minimum/src/stm32_usbdev.c | 93 + .../stm32f103-minimum/src/stm32_usbmsc.c | 71 + .../stm32f103-minimum/src/stm32_userleds.c | 102 + .../stm32f1/stm32f103-minimum/src/stm32_w25.c | 279 ++ .../stm32f103-minimum/src/stm32f103_minimum.h | 2 +- .../stm32f1/stm32vldiscovery/CMakeLists.txt | 23 + .../stm32vldiscovery/Kconfig | 0 .../stm32vldiscovery/configs/nsh/defconfig | 59 + .../stm32f1/stm32vldiscovery/include/board.h | 142 + .../stm32vldiscovery/scripts/Make.defs | 41 + .../scripts/stm32vldiscovery.ld | 2 +- .../stm32vldiscovery/src/CMakeLists.txt | 28 + .../stm32f1/stm32vldiscovery/src/Make.defs | 29 + .../stm32f1/stm32vldiscovery/src/stm32_boot.c | 82 + .../stm32vldiscovery/src/stm32_bringup.c | 96 + .../stm32vldiscovery/src/stm32_buttons.c | 111 + .../stm32f1/stm32vldiscovery/src/stm32_leds.c | 79 + .../stm32vldiscovery/src/stm32vldiscovery.h | 2 +- .../stm32f1/viewtool-stm32f107/CMakeLists.txt | 23 + .../viewtool-stm32f107/Kconfig | 0 .../configs/ft80x/defconfig | 44 + .../configs/highpri/defconfig | 39 + .../configs/netnsh/defconfig | 72 + .../viewtool-stm32f107/configs/nsh/defconfig | 41 + .../configs/tcpblaster/defconfig | 63 + .../include/board-stm32f103vct6.h | 2 +- .../include/board-stm32f107vct6.h | 2 +- .../viewtool-stm32f107/include/board.h | 166 + .../viewtool-stm32f107/scripts/Make.defs | 46 + .../stm32f1/viewtool-stm32f107/scripts/dfu.ld | 118 + .../viewtool-stm32f107/scripts/flash.ld | 118 + .../viewtool-stm32f107/src/CMakeLists.txt | 79 + .../stm32f1/viewtool-stm32f107/src/Make.defs | 77 + .../viewtool-stm32f107/src/stm32_ads7843e.c | 2 +- .../viewtool-stm32f107/src/stm32_boot.c | 99 + .../viewtool-stm32f107/src/stm32_bringup.c | 202 + .../viewtool-stm32f107/src/stm32_buttons.c | 153 + .../viewtool-stm32f107/src/stm32_can.c | 103 + .../viewtool-stm32f107/src/stm32_ft80x.c | 2 +- .../viewtool-stm32f107/src/stm32_highpri.c | 277 ++ .../viewtool-stm32f107/src/stm32_leds.c | 280 ++ .../viewtool-stm32f107/src/stm32_max3421e.c | 2 +- .../viewtool-stm32f107/src/stm32_mmcsd.c | 121 + .../viewtool-stm32f107/src/stm32_spi.c | 210 + .../viewtool-stm32f107/src/stm32_ssd1289.c | 568 +++ .../viewtool-stm32f107/src/stm32_usbdev.c | 113 + .../viewtool-stm32f107/src/stm32_usbmsc.c | 73 + .../src/viewtool_stm32f107.h | 2 +- boards/arm/stm32f2/common/CMakeLists.txt | 23 + boards/arm/stm32f2/common/Kconfig | 6 + boards/arm/stm32f2/common/Makefile | 39 + boards/arm/stm32f2/emw3162/CMakeLists.txt | 23 + boards/arm/{stm32 => stm32f2}/emw3162/Kconfig | 0 .../arm/stm32f2/emw3162/configs/nsh/defconfig | 42 + .../stm32f2/emw3162/configs/wlan/defconfig | 83 + boards/arm/stm32f2/emw3162/include/board.h | 218 ++ boards/arm/stm32f2/emw3162/scripts/Make.defs | 41 + boards/arm/stm32f2/emw3162/scripts/ld.script | 130 + boards/arm/stm32f2/emw3162/src/CMakeLists.txt | 38 + boards/arm/stm32f2/emw3162/src/Make.defs | 40 + .../{stm32 => stm32f2}/emw3162/src/emw3162.h | 4 +- .../arm/stm32f2/emw3162/src/stm32_autoleds.c | 101 + boards/arm/stm32f2/emw3162/src/stm32_boot.c | 80 + .../arm/stm32f2/emw3162/src/stm32_bringup.c | 96 + .../arm/stm32f2/emw3162/src/stm32_userleds.c | 74 + boards/arm/stm32f2/emw3162/src/stm32_wlan.c | 176 + .../emw3162/src/stm32_wlan_firmware.c | 0 .../arm/stm32f2/nucleo-f207zg/CMakeLists.txt | 23 + .../{stm32 => stm32f2}/nucleo-f207zg/Kconfig | 0 .../nucleo-f207zg/configs/adc/defconfig | 48 + .../nucleo-f207zg/configs/nsh/defconfig | 38 + .../nucleo-f207zg/configs/pwm/defconfig | 42 + .../arm/stm32f2/nucleo-f207zg/include/board.h | 209 + .../stm32f2/nucleo-f207zg/scripts/Make.defs | 41 + .../stm32f2/nucleo-f207zg/scripts/ld.script | 124 + .../stm32f2/nucleo-f207zg/src/CMakeLists.txt | 49 + .../arm/stm32f2/nucleo-f207zg/src/Make.defs | 51 + .../nucleo-f207zg/src/nucleo-f207zg.h | 2 +- .../arm/stm32f2/nucleo-f207zg/src/stm32_adc.c | 243 ++ .../nucleo-f207zg/src/stm32_autoleds.c | 171 + .../stm32f2/nucleo-f207zg/src/stm32_boot.c | 87 + .../stm32f2/nucleo-f207zg/src/stm32_bringup.c | 92 + .../stm32f2/nucleo-f207zg/src/stm32_buttons.c | 107 + .../arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c | 110 + .../arm/stm32f2/nucleo-f207zg/src/stm32_usb.c | 322 ++ .../nucleo-f207zg/src/stm32_userleds.c | 127 + .../stm32f2/olimex-stm32-p207/CMakeLists.txt | 23 + .../olimex-stm32-p207/Kconfig | 0 .../olimex-stm32-p207/configs/nsh/defconfig | 82 + .../stm32f2/olimex-stm32-p207/include/board.h | 241 ++ .../olimex-stm32-p207/scripts/Make.defs | 41 + .../olimex-stm32-p207/scripts/ld.script | 125 + .../olimex-stm32-p207/src/CMakeLists.txt | 49 + .../stm32f2/olimex-stm32-p207/src/Make.defs | 51 + .../olimex-stm32-p207/src/olimex-stm32-p207.h | 2 +- .../stm32f2/olimex-stm32-p207/src/stm32_adc.c | 156 + .../olimex-stm32-p207/src/stm32_autoleds.c | 160 + .../olimex-stm32-p207/src/stm32_boot.c | 205 + .../olimex-stm32-p207/src/stm32_buttons.c | 176 + .../stm32f2/olimex-stm32-p207/src/stm32_can.c | 100 + .../stm32f2/olimex-stm32-p207/src/stm32_usb.c | 313 ++ .../olimex-stm32-p207/src/stm32_userleds.c | 104 + boards/arm/stm32f2/photon/CMakeLists.txt | 23 + boards/arm/{stm32 => stm32f2}/photon/Kconfig | 0 .../arm/stm32f2/photon/configs/adb/defconfig | 71 + .../arm/stm32f2/photon/configs/nsh/defconfig | 47 + .../stm32f2/photon/configs/rgbled/defconfig | 69 + .../stm32f2/photon/configs/usbnsh/defconfig | 53 + .../photon/configs/wlan-perf/defconfig | 89 + .../arm/stm32f2/photon/configs/wlan/defconfig | 101 + boards/arm/stm32f2/photon/include/board.h | 311 ++ boards/arm/stm32f2/photon/scripts/Make.defs | 68 + .../photon/scripts/photon_dfu.ld | 2 +- .../photon/scripts/photon_jtag.ld | 2 +- boards/arm/stm32f2/photon/src/CMakeLists.txt | 68 + boards/arm/stm32f2/photon/src/Make.defs | 64 + .../photon/src/dfu_signature.c | 2 +- .../{stm32 => stm32f2}/photon/src/photon.h | 4 +- .../arm/stm32f2/photon/src/stm32_autoleds.c | 103 + boards/arm/stm32f2/photon/src/stm32_boot.c | 106 + boards/arm/stm32f2/photon/src/stm32_bringup.c | 167 + boards/arm/stm32f2/photon/src/stm32_buttons.c | 88 + .../arm/stm32f2/photon/src/stm32_composite.c | 166 + boards/arm/stm32f2/photon/src/stm32_rgbled.c | 169 + boards/arm/stm32f2/photon/src/stm32_spi.c | 186 + boards/arm/stm32f2/photon/src/stm32_usb.c | 68 + .../arm/stm32f2/photon/src/stm32_userleds.c | 74 + .../{stm32 => stm32f2}/photon/src/stm32_wdt.c | 2 +- boards/arm/stm32f2/photon/src/stm32_wlan.c | 157 + .../photon/src/stm32_wlan_firmware.c | 2 +- .../arm/stm32f2/stm3220g-eval/CMakeLists.txt | 23 + .../{stm32 => stm32f2}/stm3220g-eval/Kconfig | 0 .../stm3220g-eval/configs/dhcpd/defconfig | 61 + .../stm3220g-eval/configs/nettest/defconfig | 60 + .../stm3220g-eval/configs/nsh/defconfig | 75 + .../stm3220g-eval/configs/nsh2/defconfig | 89 + .../stm3220g-eval/configs/nxwm/defconfig | 126 + .../stm3220g-eval/configs/telnetd/defconfig | 62 + .../arm/stm32f2/stm3220g-eval/include/board.h | 552 +++ .../stm32f2/stm3220g-eval/scripts/Make.defs | 41 + .../stm32f2/stm3220g-eval/scripts/ld.script | 125 + .../stm32f2/stm3220g-eval/src/CMakeLists.txt | 69 + .../arm/stm32f2/stm3220g-eval/src/Make.defs | 63 + .../stm3220g-eval/src/stm3220g-eval.h | 2 +- .../arm/stm32f2/stm3220g-eval/src/stm32_adc.c | 157 + .../stm3220g-eval/src/stm32_autoleds.c | 232 ++ .../stm32f2/stm3220g-eval/src/stm32_boot.c | 368 ++ .../stm32f2/stm3220g-eval/src/stm32_buttons.c | 156 + .../arm/stm32f2/stm3220g-eval/src/stm32_can.c | 102 + .../stm3220g-eval/src/stm32_deselectlcd.c | 80 + .../stm3220g-eval/src/stm32_deselectsram.c | 80 + .../stm32f2/stm3220g-eval/src/stm32_extmem.c | 141 + .../arm/stm32f2/stm3220g-eval/src/stm32_lcd.c | 1186 ++++++ .../arm/stm32f2/stm3220g-eval/src/stm32_pwm.c | 105 + .../stm3220g-eval/src/stm32_selectlcd.c | 155 + .../stm3220g-eval/src/stm32_selectsram.c | 186 + .../arm/stm32f2/stm3220g-eval/src/stm32_spi.c | 130 + .../stm3220g-eval/src/stm32_stmpe811.c | 337 ++ .../arm/stm32f2/stm3220g-eval/src/stm32_usb.c | 304 ++ .../stm3220g-eval/src/stm32_userleds.c | 96 + .../tools/olimex-arm-usb-ocd.cfg | 0 .../arm/stm32f2/stm3220g-eval/tools/oocd.sh | 87 + .../stm3220g-eval/tools/stm32.cfg | 0 .../stm3220g-eval/tools/usb-driver.txt | 0 boards/arm/stm32f3/common/CMakeLists.txt | 23 + boards/arm/stm32f3/common/Kconfig | 6 + boards/arm/stm32f3/common/Makefile | 39 + .../arm/stm32f3/nucleo-f302r8/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f302r8/Kconfig | 0 .../nucleo-f302r8/configs/can/defconfig | 55 + .../nucleo-f302r8/configs/cansock/defconfig | 68 + .../nucleo-f302r8/configs/highpri/defconfig | 59 + .../configs/ihm07m1_b16/defconfig | 88 + .../configs/ihm07m1_f32/defconfig | 87 + .../nucleo-f302r8/configs/nsh/defconfig | 86 + .../nucleo-f302r8/configs/qenco/defconfig | 112 + .../arm/stm32f3/nucleo-f302r8/include/board.h | 308 ++ .../stm32f3/nucleo-f302r8/scripts/Make.defs | 41 + .../stm32f3/nucleo-f302r8/scripts/ld.script | 127 + .../stm32f3/nucleo-f302r8/src/CMakeLists.txt | 62 + .../arm/stm32f3/nucleo-f302r8/src/Make.defs | 64 + .../nucleo-f302r8/src/nucleo-f302r8.h | 2 +- .../arm/stm32f3/nucleo-f302r8/src/stm32_adc.c | 112 + .../nucleo-f302r8/src/stm32_autoleds.c | 80 + .../stm32f3/nucleo-f302r8/src/stm32_boot.c | 95 + .../stm32f3/nucleo-f302r8/src/stm32_bringup.c | 188 + .../stm32f3/nucleo-f302r8/src/stm32_buttons.c | 113 + .../arm/stm32f3/nucleo-f302r8/src/stm32_can.c | 73 + .../stm32f3/nucleo-f302r8/src/stm32_cansock.c | 59 + .../nucleo-f302r8/src/stm32_foc_ihm07m1.c | 183 + .../stm32f3/nucleo-f302r8/src/stm32_highpri.c | 544 +++ .../arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c | 110 + .../nucleo-f302r8/src/stm32_userleds.c | 77 + .../arm/stm32f3/nucleo-f303re/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f303re/Kconfig | 0 .../nucleo-f303re/configs/adc/defconfig | 48 + .../nucleo-f303re/configs/can/defconfig | 40 + .../nucleo-f303re/configs/hello/defconfig | 36 + .../nucleo-f303re/configs/nsh/defconfig | 36 + .../nucleo-f303re/configs/nxlines/defconfig | 48 + .../nucleo-f303re/configs/pwm/defconfig | 47 + .../nucleo-f303re/configs/serialrx/defconfig | 39 + .../arm/stm32f3/nucleo-f303re/include/board.h | 241 ++ .../stm32f3/nucleo-f303re/scripts/Make.defs | 41 + .../stm32f3/nucleo-f303re/scripts/ld.script | 121 + .../stm32f3/nucleo-f303re/src/CMakeLists.txt | 69 + .../arm/stm32f3/nucleo-f303re/src/Make.defs | 71 + .../nucleo-f303re/src/nucleo-f303re.h | 2 +- .../arm/stm32f3/nucleo-f303re/src/stm32_adc.c | 374 ++ .../nucleo-f303re/src/stm32_autoleds.c | 80 + .../stm32f3/nucleo-f303re/src/stm32_boot.c | 171 + .../stm32f3/nucleo-f303re/src/stm32_buttons.c | 113 + .../arm/stm32f3/nucleo-f303re/src/stm32_can.c | 81 + .../arm/stm32f3/nucleo-f303re/src/stm32_pwm.c | 89 + .../arm/stm32f3/nucleo-f303re/src/stm32_spi.c | 195 + .../stm32f3/nucleo-f303re/src/stm32_ssd1351.c | 118 + .../stm32f3/nucleo-f303re/src/stm32_timer.c | 67 + .../arm/stm32f3/nucleo-f303re/src/stm32_uid.c | 68 + .../nucleo-f303re/src/stm32_userleds.c | 77 + .../arm/stm32f3/nucleo-f303ze/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f303ze/Kconfig | 0 .../nucleo-f303ze/configs/adc/defconfig | 53 + .../nucleo-f303ze/configs/nsh/defconfig | 39 + .../configs/nxlines_oled/defconfig | 54 + .../arm/stm32f3/nucleo-f303ze/include/board.h | 207 + .../stm32f3/nucleo-f303ze/scripts/Make.defs | 41 + .../stm32f3/nucleo-f303ze/scripts/ld.script | 121 + .../stm32f3/nucleo-f303ze/src/CMakeLists.txt | 45 + .../arm/stm32f3/nucleo-f303ze/src/Make.defs | 47 + .../nucleo-f303ze/src/nucleo-f303ze.h | 2 +- .../arm/stm32f3/nucleo-f303ze/src/stm32_adc.c | 243 ++ .../nucleo-f303ze/src/stm32_autoleds.c | 171 + .../stm32f3/nucleo-f303ze/src/stm32_boot.c | 81 + .../stm32f3/nucleo-f303ze/src/stm32_bringup.c | 71 + .../stm32f3/nucleo-f303ze/src/stm32_buttons.c | 107 + .../arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c | 89 + .../nucleo-f303ze/src/stm32_userleds.c | 127 + .../arm/stm32f3/nucleo-f334r8/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f334r8/Kconfig | 0 .../nucleo-f334r8/configs/adc/defconfig | 96 + .../nucleo-f334r8/configs/highpri/defconfig | 63 + .../nucleo-f334r8/configs/nsh/defconfig | 87 + .../nucleo-f334r8/configs/spwm1/defconfig | 74 + .../nucleo-f334r8/configs/spwm2/defconfig | 65 + .../arm/stm32f3/nucleo-f334r8/include/board.h | 344 ++ .../stm32f3/nucleo-f334r8/scripts/Make.defs | 41 + .../stm32f3/nucleo-f334r8/scripts/ld.script | 127 + .../stm32f3/nucleo-f334r8/src/CMakeLists.txt | 59 + .../arm/stm32f3/nucleo-f334r8/src/Make.defs | 61 + .../nucleo-f334r8/src/nucleo-f334r8.h | 2 +- .../arm/stm32f3/nucleo-f334r8/src/stm32_adc.c | 242 ++ .../nucleo-f334r8/src/stm32_autoleds.c | 80 + .../stm32f3/nucleo-f334r8/src/stm32_boot.c | 162 + .../stm32f3/nucleo-f334r8/src/stm32_comp.c | 122 + .../stm32f3/nucleo-f334r8/src/stm32_highpri.c | 586 +++ .../stm32f3/nucleo-f334r8/src/stm32_hrtim.c | 86 + .../stm32f3/nucleo-f334r8/src/stm32_opamp.c | 86 + .../nucleo-f334r8/src/stm32_spwm.c | 2 +- .../stm32f3/stm32f334-disco/CMakeLists.txt | 23 + .../stm32f334-disco/Kconfig | 0 .../configs/buckboost/defconfig | 129 + .../stm32f334-disco/configs/nsh/defconfig | 89 + .../configs/powerled/defconfig | 99 + .../stm32f3/stm32f334-disco/include/board.h | 337 ++ .../stm32f3/stm32f334-disco/scripts/Make.defs | 41 + .../stm32f3/stm32f334-disco/scripts/ld.script | 127 + .../stm32f334-disco/src/CMakeLists.txt | 55 + .../arm/stm32f3/stm32f334-disco/src/Make.defs | 57 + .../stm32f3/stm32f334-disco/src/stm32_adc.c | 241 ++ .../stm32f334-disco/src/stm32_autoleds.c | 80 + .../stm32f3/stm32f334-disco/src/stm32_boot.c | 194 + .../stm32f3/stm32f334-disco/src/stm32_comp.c | 122 + .../stm32f3/stm32f334-disco/src/stm32_hrtim.c | 86 + .../stm32f3/stm32f334-disco/src/stm32_opamp.c | 86 + .../stm32f334-disco/src/stm32_powerled.c | 2 +- .../stm32f3/stm32f334-disco/src/stm32_smps.c | 1143 ++++++ .../stm32f334-disco/src/stm32f334-disco.h | 2 +- .../stm32f3/stm32f3discovery/CMakeLists.txt | 23 + .../stm32f3discovery/Kconfig | 0 .../stm32f3discovery/configs/nsh/defconfig | 53 + .../stm32f3discovery/configs/usbnsh/defconfig | 55 + .../stm32f3/stm32f3discovery/include/board.h | 275 ++ .../stm32f3discovery/scripts/Make.defs | 41 + .../stm32f3discovery/scripts/ld.script | 121 + .../stm32f3discovery/src/CMakeLists.txt | 45 + .../stm32f3/stm32f3discovery/src/Make.defs | 47 + .../stm32f3discovery/src/stm32_autoleds.c | 108 + .../stm32f3/stm32f3discovery/src/stm32_boot.c | 105 + .../stm32f3discovery/src/stm32_bringup.c | 141 + .../stm32f3discovery/src/stm32_buttons.c | 150 + .../stm32f3/stm32f3discovery/src/stm32_pwm.c | 127 + .../stm32f3/stm32f3discovery/src/stm32_spi.c | 182 + .../stm32f3/stm32f3discovery/src/stm32_usb.c | 116 + .../stm32f3discovery/src/stm32_userleds.c | 103 + .../stm32f3discovery/src/stm32f3discovery.h | 4 +- boards/arm/stm32f4/axoloti/CMakeLists.txt | 23 + boards/arm/{stm32 => stm32f4}/axoloti/Kconfig | 0 .../arm/stm32f4/axoloti/configs/nsh/defconfig | 40 + boards/arm/stm32f4/axoloti/include/board.h | 263 ++ boards/arm/stm32f4/axoloti/scripts/Make.defs | 41 + .../stm32f4/axoloti/scripts/kernel-space.ld | 100 + boards/arm/stm32f4/axoloti/scripts/ld.script | 132 + boards/arm/stm32f4/axoloti/scripts/memory.ld | 88 + .../arm/stm32f4/axoloti/scripts/user-space.ld | 114 + boards/arm/stm32f4/axoloti/src/CMakeLists.txt | 53 + boards/arm/stm32f4/axoloti/src/Make.defs | 55 + .../{stm32 => stm32f4}/axoloti/src/axoloti.h | 4 +- .../axoloti/src/stm32_adau1961.c | 2 +- boards/arm/stm32f4/axoloti/src/stm32_boot.c | 89 + .../arm/stm32f4/axoloti/src/stm32_bringup.c | 176 + .../arm/stm32f4/axoloti/src/stm32_buttons.c | 151 + boards/arm/stm32f4/axoloti/src/stm32_extmem.c | 310 ++ boards/arm/stm32f4/axoloti/src/stm32_sdio.c | 156 + .../arm/stm32f4/axoloti/src/stm32_usbhost.c | 265 ++ .../arm/stm32f4/axoloti/src/stm32_userleds.c | 93 + .../arm/stm32f4/clicker2-stm32/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/clicker2-stm32/Kconfig | 0 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.../clicker2-stm32/src/stm32_autoleds.c | 189 + .../clicker2-stm32/src/stm32_automount.c | 2 +- .../stm32f4/clicker2-stm32/src/stm32_boot.c | 139 + .../clicker2-stm32/src/stm32_bringup.c | 193 + .../clicker2-stm32/src/stm32_buttons.c | 123 + .../stm32f4/clicker2-stm32/src/stm32_can.c | 100 + .../stm32f4/clicker2-stm32/src/stm32_mmcsd.c | 423 +++ .../clicker2-stm32/src/stm32_mrf24j40.c | 328 ++ .../stm32f4/clicker2-stm32/src/stm32_spi.c | 268 ++ .../stm32f4/clicker2-stm32/src/stm32_usb.c | 96 + .../clicker2-stm32/src/stm32_userleds.c | 89 + .../clicker2-stm32/src/stm32_xbee.c | 2 +- boards/arm/stm32f4/common/CMakeLists.txt | 23 + boards/arm/stm32f4/common/Kconfig | 6 + boards/arm/stm32f4/common/Makefile | 39 + .../arm/stm32f4/mikroe-stm32f4/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/mikroe-stm32f4/Kconfig | 0 .../mikroe-stm32f4/configs/fulldemo/defconfig | 137 + .../mikroe-stm32f4/configs/kostest/defconfig | 84 + .../mikroe-stm32f4/configs/nsh/defconfig | 70 + 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.../stm32f4/mikroe-stm32f4/src/stm32_idle.c | 263 ++ .../mikroe-stm32f4/src/stm32_mio283qt2.c | 2 +- .../mikroe-stm32f4/src/stm32_mio283qt9a.c | 2 +- .../arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c | 75 + .../stm32f4/mikroe-stm32f4/src/stm32_pwm.c | 127 + .../stm32f4/mikroe-stm32f4/src/stm32_spi.c | 246 ++ .../mikroe-stm32f4/src/stm32_touchscreen.c | 1547 ++++++++ .../stm32f4/mikroe-stm32f4/src/stm32_usb.c | 304 ++ .../mikroe-stm32f4/src/stm32_vs1053.c | 2 +- .../arm/stm32f4/nucleo-f401re/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f401re/Kconfig | 0 .../nucleo-f401re/configs/fb/defconfig | 63 + .../nucleo-f401re/configs/nsh/defconfig | 49 + .../arm/stm32f4/nucleo-f401re/include/board.h | 380 ++ .../stm32f4/nucleo-f401re/scripts/Make.defs | 43 + .../stm32f4/nucleo-f401re/scripts/flash.ld | 109 + .../stm32f4/nucleo-f401re/src/CMakeLists.txt | 54 + .../arm/stm32f4/nucleo-f401re/src/Make.defs | 56 + .../nucleo-f401re/src/nucleo-f401re.h | 2 +- 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.../stm32f4/nucleo-f411re/src/stm32_bringup.c | 213 ++ .../stm32f4/nucleo-f411re/src/stm32_buttons.c | 117 + .../nucleo-f411re/src/stm32_lcd_ssd1306.c | 88 + .../stm32f4/nucleo-f411re/src/stm32_mcp2515.c | 241 ++ .../arm/stm32f4/nucleo-f411re/src/stm32_spi.c | 246 ++ .../nucleo-f411re/src/stm32_userleds.c | 218 ++ .../arm/stm32f4/nucleo-f412zg/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f412zg/Kconfig | 0 .../nucleo-f412zg/configs/coremark/defconfig | 52 + .../nucleo-f412zg/configs/nsh/defconfig | 60 + .../nucleo-f412zg/configs/ostest/defconfig | 61 + .../arm/stm32f4/nucleo-f412zg/include/board.h | 228 ++ .../stm32f4/nucleo-f412zg/scripts/Make.defs | 42 + .../nucleo-f412zg/scripts/f412zg.ld | 2 +- .../stm32f4/nucleo-f412zg/src/CMakeLists.txt | 35 + .../arm/stm32f4/nucleo-f412zg/src/Make.defs | 38 + .../nucleo-f412zg/src/nucleo-f412zg.h | 2 +- .../nucleo-f412zg/src/stm32_autoleds.c | 104 + .../stm32f4/nucleo-f412zg/src/stm32_boot.c | 100 + .../stm32f4/nucleo-f412zg/src/stm32_bringup.c | 84 + .../arm/stm32f4/nucleo-f412zg/src/stm32_usb.c | 352 ++ .../arm/stm32f4/nucleo-f429zi/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f429zi/Kconfig | 0 .../nucleo-f429zi/configs/netnsh/defconfig | 82 + .../nucleo-f429zi/configs/nsh/defconfig | 49 + .../nucleo-f429zi/configs/trace/defconfig | 90 + .../arm/stm32f4/nucleo-f429zi/include/board.h | 376 ++ .../stm32f4/nucleo-f429zi/scripts/Make.defs | 41 + .../nucleo-f429zi/scripts/kernel-space.ld | 100 + .../stm32f4/nucleo-f429zi/scripts/ld.script | 133 + .../stm32f4/nucleo-f429zi/scripts/memory.ld | 88 + .../nucleo-f429zi/scripts/user-space.ld | 114 + .../stm32f4/nucleo-f429zi/src/CMakeLists.txt | 73 + .../arm/stm32f4/nucleo-f429zi/src/Make.defs | 75 + .../nucleo-f429zi/src/nucleo-144.h | 2 +- .../arm/stm32f4/nucleo-f429zi/src/stm32_adc.c | 169 + .../nucleo-f429zi/src/stm32_autoleds.c | 170 + .../nucleo-f429zi/src/stm32_bbsram.c | 2 +- .../stm32f4/nucleo-f429zi/src/stm32_boot.c | 252 ++ .../stm32f4/nucleo-f429zi/src/stm32_buttons.c | 110 + .../nucleo-f429zi/src/stm32_dma_alloc.c | 2 +- .../stm32f4/nucleo-f429zi/src/stm32_gpio.c | 323 ++ .../arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c | 149 + .../stm32f4/nucleo-f429zi/src/stm32_reset.c | 64 + .../stm32f4/nucleo-f429zi/src/stm32_romfs.h | 63 + .../src/stm32_romfs_initialize.c | 141 + .../stm32f4/nucleo-f429zi/src/stm32_sdio.c | 163 + .../arm/stm32f4/nucleo-f429zi/src/stm32_spi.c | 496 +++ .../arm/stm32f4/nucleo-f429zi/src/stm32_usb.c | 322 ++ .../nucleo-f429zi/src/stm32_userleds.c | 128 + .../arm/stm32f4/nucleo-f446re/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f446re/Kconfig | 0 .../nucleo-f446re/configs/adc/defconfig | 57 + .../nucleo-f446re/configs/can/defconfig | 58 + .../nucleo-f446re/configs/cansock/defconfig | 72 + .../nucleo-f446re/configs/dac/defconfig | 56 + .../nucleo-f446re/configs/gpio/defconfig | 52 + .../configs/ihm08m1_b16/defconfig | 91 + .../configs/ihm08m1_f32/defconfig | 91 + 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.../arm/stm32f4/nucleo-f446re/src/stm32_dac.c | 112 + .../nucleo-f446re/src/stm32_foc_ihm08m1.c | 2 +- .../stm32f4/nucleo-f446re/src/stm32_gpio.c | 343 ++ .../nucleo-f446re/src/stm32_ili9225.c | 2 +- .../arm/stm32f4/nucleo-f446re/src/stm32_pwm.c | 134 + .../stm32f4/nucleo-f446re/src/stm32_romfs.h | 63 + .../src/stm32_romfs_initialize.c | 141 + .../arm/stm32f4/nucleo-f446re/src/stm32_spi.c | 236 ++ .../nucleo-f446re/src/stm32_userleds.c | 105 + boards/arm/stm32f4/odrive36/CMakeLists.txt | 23 + .../arm/{stm32 => stm32f4}/odrive36/Kconfig | 0 .../stm32f4/odrive36/configs/nsh/defconfig | 43 + .../stm32f4/odrive36/configs/usbnsh/defconfig | 55 + boards/arm/stm32f4/odrive36/include/board.h | 212 ++ boards/arm/stm32f4/odrive36/scripts/Make.defs | 42 + boards/arm/stm32f4/odrive36/scripts/ld.script | 125 + .../arm/stm32f4/odrive36/src/CMakeLists.txt | 39 + boards/arm/stm32f4/odrive36/src/Make.defs | 41 + .../{stm32 => stm32f4}/odrive36/src/odrive.h | 2 +- boards/arm/stm32f4/odrive36/src/stm32_boot.c | 107 + .../arm/stm32f4/odrive36/src/stm32_bringup.c | 140 + boards/arm/stm32f4/odrive36/src/stm32_foc.c | 962 +++++ boards/arm/stm32f4/odrive36/src/stm32_spi.c | 198 + boards/arm/stm32f4/odrive36/src/stm32_usb.c | 105 + .../stm32f4/olimex-stm32-e407/CMakeLists.txt | 23 + .../olimex-stm32-e407/Kconfig | 0 .../configs/bmp180/defconfig | 57 + .../olimex-stm32-e407/configs/dac/defconfig | 58 + .../configs/discover/defconfig | 71 + .../configs/ina219/defconfig | 58 + .../configs/mrf24j40-6lowpan/defconfig | 104 + .../configs/mrf24j40-mac/defconfig | 63 + .../configs/netnsh/defconfig | 76 + .../olimex-stm32-e407/configs/nsh/defconfig | 49 + .../configs/telnetd/defconfig | 79 + .../olimex-stm32-e407/configs/timer/defconfig | 54 + .../configs/usbnsh/defconfig | 55 + .../configs/webserver/defconfig | 73 + .../stm32f4/olimex-stm32-e407/include/board.h | 280 ++ .../olimex-stm32-e407/scripts/Make.defs | 46 + .../olimex-stm32-e407/scripts/f407ze.ld | 2 +- .../olimex-stm32-e407/scripts/f407zg.ld | 2 +- .../olimex-stm32-e407/src/CMakeLists.txt | 77 + .../stm32f4/olimex-stm32-e407/src/Make.defs | 75 + .../olimex-stm32-e407/src/olimex-stm32-e407.h | 4 +- .../stm32f4/olimex-stm32-e407/src/stm32_adc.c | 166 + .../olimex-stm32-e407/src/stm32_autoleds.c | 92 + .../olimex-stm32-e407/src/stm32_boot.c | 105 + .../olimex-stm32-e407/src/stm32_bringup.c | 283 ++ .../olimex-stm32-e407/src/stm32_buttons.c | 140 + .../stm32f4/olimex-stm32-e407/src/stm32_can.c | 100 + .../stm32f4/olimex-stm32-e407/src/stm32_dac.c | 110 + .../olimex-stm32-e407/src/stm32_mrf24j40.c | 279 ++ .../stm32f4/olimex-stm32-e407/src/stm32_spi.c | 303 ++ .../olimex-stm32-e407/src/stm32_timer.c | 63 + .../stm32f4/olimex-stm32-e407/src/stm32_usb.c | 329 ++ .../olimex-stm32-e407/src/stm32_userleds.c | 95 + .../stm32f4/olimex-stm32-h405/CMakeLists.txt | 23 + .../olimex-stm32-h405/Kconfig | 0 .../configs/usbnsh/defconfig | 68 + .../stm32f4/olimex-stm32-h405/include/board.h | 187 + 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tools/ci/testlist/arm-08.dat | 29 +- tools/ci/testlist/arm-09.dat | 16 +- tools/ci/testlist/arm-10.dat | 14 +- tools/ci/testlist/arm-11.dat | 16 +- tools/ci/testlist/arm-12.dat | 8 +- tools/ci/testlist/macos.dat | 2 +- tools/ci/testlist/msys2.dat | 4 +- tools/ci/testlist/windows.dat | 4 +- 2851 files changed, 167384 insertions(+), 178588 deletions(-) delete mode 100644 arch/arm/include/stm32/chip.h delete mode 100644 arch/arm/include/stm32/irq.h delete mode 100644 arch/arm/include/stm32/stm32f10xxx_irq.h delete mode 100644 arch/arm/include/stm32/stm32f20xxx_irq.h delete mode 100644 arch/arm/include/stm32/stm32f40xxx_irq.h delete mode 100644 arch/arm/include/stm32/stm32g4xxxx_irq.h delete mode 100644 arch/arm/include/stm32/stm32l15xxx_irq.h create mode 100644 arch/arm/include/stm32f1/chip.h create mode 100644 arch/arm/include/stm32f1/irq.h create mode 100644 arch/arm/include/stm32f2/chip.h create mode 100644 arch/arm/include/stm32f2/irq.h create mode 100644 arch/arm/include/stm32f3/chip.h create mode 100644 arch/arm/include/stm32f3/irq.h rename arch/arm/include/{stm32 => stm32f3}/stm32f30xxx_irq.h (93%) rename arch/arm/include/{stm32 => stm32f3}/stm32f33xxx_irq.h (92%) rename arch/arm/include/{stm32 => stm32f3}/stm32f37xxx_irq.h (92%) create mode 100644 arch/arm/include/stm32f4/chip.h create mode 100644 arch/arm/include/stm32f4/irq.h create mode 100644 arch/arm/include/stm32g4/chip.h create mode 100644 arch/arm/include/stm32g4/irq.h create mode 100644 arch/arm/include/stm32l1/chip.h create mode 100644 arch/arm/include/stm32l1/irq.h delete mode 100644 arch/arm/src/stm32/CMakeLists.txt delete mode 100644 arch/arm/src/stm32/Kconfig delete mode 100644 arch/arm/src/stm32/Make.defs delete mode 100644 arch/arm/src/stm32/chip.h delete mode 100644 arch/arm/src/stm32/hardware/stm32_adc_v1.h delete mode 100644 arch/arm/src/stm32/hardware/stm32_adc_v1l1.h delete mode 100644 arch/arm/src/stm32/hardware/stm32_adc_v2.h delete mode 100644 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delete mode 100644 arch/arm/src/stm32/stm32_start.h delete mode 100644 arch/arm/src/stm32/stm32_userspace.h create mode 100644 arch/arm/src/stm32f1/CMakeLists.txt create mode 100644 arch/arm/src/stm32f1/Kconfig create mode 100644 arch/arm/src/stm32f1/Kconfig.pinmap create mode 100644 arch/arm/src/stm32f1/Make.defs create mode 100644 arch/arm/src/stm32f1/chip.h create mode 100644 arch/arm/src/stm32f1/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f1/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f100_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f102_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103c_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103r_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103v_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103z_pinmap.h (99%) rename arch/arm/src/{stm32 => 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mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c create mode 100644 boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c create mode 100644 boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/Kconfig (100%) create mode 100644 boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig create mode 100644 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mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_reset.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_spi.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_timer.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_uid.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_usb.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c create mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c create mode 100644 boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/stm3240g-eval/Kconfig (100%) create mode 100644 boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig create mode 100644 boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig create mode 100644 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boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig create mode 100644 boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig create mode 100644 boards/arm/stm32g4/nucleo-g431rb/include/board.h create mode 100644 boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs create mode 100644 boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/.gitignore (100%) create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/Make.defs rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/nucleo-g431rb.h (99%) create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_cordic.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_foc_ihm16m1.c (98%) create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c create mode 100644 boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c create mode 100644 boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/Kconfig (100%) create mode 100644 boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig create mode 100644 boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig create mode 100644 boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig create mode 100644 boards/arm/stm32g4/nucleo-g474re/include/board.h create mode 100644 boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs create mode 100644 boards/arm/stm32g4/nucleo-g474re/scripts/ld.script create mode 100644 boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/.gitignore (100%) create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/Make.defs rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/nucleo-g474re.h (98%) create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c create mode 100644 boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c create mode 100644 boards/arm/stm32l1/common/CMakeLists.txt create mode 100644 boards/arm/stm32l1/common/Kconfig create mode 100644 boards/arm/stm32l1/common/Makefile create mode 100644 boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/Kconfig (100%) create mode 100644 boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig create mode 100644 boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig create mode 100644 boards/arm/stm32l1/nucleo-l152re/include/board.h create mode 100644 boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs create mode 100644 boards/arm/stm32l1/nucleo-l152re/scripts/ld.script create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/Make.defs rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/nucleo-l152re.h (98%) create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_ili93418b.c (99%) create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_spisd.c (98%) create mode 100644 boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/Kconfig (100%) create mode 100644 boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig create mode 100644 boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig create mode 100644 boards/arm/stm32l1/stm32ldiscovery/include/board.h create mode 100644 boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/scripts/stm32l152rb.ld (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/scripts/stm32l152rc.ld (98%) create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/Make.defs create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c create mode 100644 boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32ldiscovery.h (99%) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index d6832ccd15103..3528e51466d19 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -962,20 +962,21 @@ arch/arm/include/samv7/samv71_irq.h alin.jerpelea@sony.com petro.karashchenko@gm arch/arm/include/setjmp.h david.s.alessio@gmail.com alin.jerpelea@sony.com guowei15@xiaomi.com xiaoxiang@xiaomi.com huangqi3@xiaomi.com arch/arm/include/spinlock.h alin.jerpelea@sony.com anchao.archer@bytedance.com xiaoxiang@xiaomi.com hujun5@xiaomi.com arch/arm/include/stdarg.h alin.jerpelea@sony.com guoshichao@xiaomi.com -arch/arm/include/stm32/chip.h raiden00pl@gmail.com 59230071+hartmannathan@users.noreply.github.com paul-a.patience@polymtl.ca -arch/arm/include/stm32/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me -arch/arm/include/stm32/stm32f10xxx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net -arch/arm/include/stm32/stm32f20xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f30xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f33xxx_irq.h 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com -arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/include/stm32c0/chip.h raiden00@railab.me arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com +arch/arm/include/stm32f1/chip.h raiden00@railab.me +arch/arm/include/stm32f1/irq.h raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net peter.barada@gmail.com +arch/arm/include/stm32f2/chip.h raiden00@railab.me +arch/arm/include/stm32f2/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com +arch/arm/include/stm32f3/chip.h raiden00@railab.me +arch/arm/include/stm32f3/irq.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com mijung@gmx.net simon@leitwert.ch +arch/arm/include/stm32f3/stm32f30xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f3/stm32f33xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/include/stm32f3/stm32f37xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f4/chip.h raiden00@railab.me +arch/arm/include/stm32f4/irq.h david_s5@usa.net gwenj@trabucayre.com paul-a.patience@polymtl.ca alin.jerpelea@sony.com raiden00@railab.me arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com @@ -983,6 +984,8 @@ arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+ha arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32g0/chip.h raiden00@railab.me arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32g4/chip.h raiden00@railab.me +arch/arm/include/stm32g4/irq.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com devel@sumpfralle.de arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +997,8 @@ arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32l0/chip.h raiden00@railab.me arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/include/stm32l1/chip.h raiden00@railab.me +arch/arm/include/stm32l1/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br @@ -1550,6 +1555,342 @@ arch/arm/src/common/gnu/fork.S guoshichao@xiaomi.com yanghuatao@xiaomi.com liaoa arch/arm/src/common/hwcap.h liaoao@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/arm_fetchadd.S xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/fork.S guoshichao@xiaomi.com alin.jerpelea@sony.com +arch/arm/src/common/stm32/Kconfig raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.adc raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.ble raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.cache raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.can raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.comp raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dac raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dfsdm raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dma raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dts raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.eth raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.fdcan raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.flash raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.foc raiden00@railab.me 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59230071+hartmannathan@users.noreply.github.com -arch/arm/src/stm32/stm32l15xxx_rcc.c 59230071+hartmannathan@users.noreply.github.com juha.niskanen@haltian.com alin.jerpelea@sony.com raiden00pl@gmail.com -arch/arm/src/stm32/stm32l15xxx_rtcc.c juha.niskanen@haltian.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/src/stm32c0/Kconfig raiden00@railab.me arch/arm/src/stm32c0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com arch/arm/src/stm32c0/hardware/stm32_memorymap.h raiden00@railab.me @@ -3776,6 +3812,78 @@ arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h alin.jerpelea@sony.com 59230071+h arch/arm/src/stm32f0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com arch/arm/src/stm32f0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com 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arch/arm/src/stm32f7/Kconfig david_s5@nscdg.com raiden00@railab.me david_s5@usa.net titus@elbe-informatik.de arch/arm/src/stm32f7/chip.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com Lok Tep 1 file changed, 1 insertion(+) arch/arm/src/stm32f7/hardware/stm32_adc.h alin.jerpelea@sony.com @@ -3955,6 +4063,32 @@ arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h raiden00pl@gmail.com raiden00@rai arch/arm/src/stm32g0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com arch/arm/src/stm32g0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com arch/arm/src/stm32g0/stm32g0_rcc.c raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me dpo@certi.org.br juha.niskanen@haltian.com +arch/arm/src/stm32g4/Kconfig raiden00@railab.me +arch/arm/src/stm32g4/chip.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me 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devel@sumpfralle.de thomas.narayana-swamy@wandercraft.eu -boards/arm/stm32/stm32f401rc-rs485/Kconfig rcsim10@gmail.com -boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com acassis@gmail.com tiago.medicci@espressif.com -boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig acassis@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig rcsim10@gmail.com wangjianyu3@xiaomi.com -boards/arm/stm32/stm32f401rc-rs485/include/board.h rcsim10@gmail.com halysson1007@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script rcsim10@gmail.com maguotong66@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_appinit.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c rcsim10@gmail.com alin.jerpelea@sony.com petro.karashchenko@gmail.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c rcsim10@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c rcsim10@gmail.com acassis@gmail.com alin.jerpelea@sony.com -boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c rcsim10@gmail.com halysson1007@gmail.com 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gustavo.nihei@espressif.com augustofg96@gmail.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h alin.jerpelea@sony.com mnitsche@dc.uba.ar juha.niskanen@haltian.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/Kconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com liguiding1@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/include/board.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu +boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_appinit.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/Kconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com acassis@gmail.com f.panag@amco.gr +boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com acassis@gmail.com f.panag@amco.gr +boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de thomas.narayana-swamy@wandercraft.eu anthony@vergeaero.com +boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu hartman.nathan@gmail.com anthony@vergeaero.com +boards/arm/stm32f1/viewtool-stm32f107/include/board.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu +boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_appinit.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com mnitsche@dc.uba.ar raiden00@railab.me +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c alin.jerpelea@sony.com yamamoto@midokura.com buxiasen@xiaomi.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com anchao@xiaomi.com petro.karashchenko@gmail.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c alin.jerpelea@sony.com +boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com thomas.narayana-swamy@wandercraft.eu raiden00@railab.me boards/arm/stm32l0/b-l072z-lrwan1/Kconfig alin.jerpelea@sony.com boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com diff --git a/Documentation/applications/examples/ft80x/index.rst b/Documentation/applications/examples/ft80x/index.rst index 9020d67baf0a2..e093218737a09 100644 --- a/Documentation/applications/examples/ft80x/index.rst +++ b/Documentation/applications/examples/ft80x/index.rst @@ -4,4 +4,4 @@ This examples has ports of several FTDI demos for the FTDI/BridgeTek FT80x GUI chip. As an example configuration, see -``nuttx/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig``. +``nuttx/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig``. diff --git a/Documentation/applications/system/usbmsc/index.rst b/Documentation/applications/system/usbmsc/index.rst index 57da5b303581a..f387859f0ca77 100644 --- a/Documentation/applications/system/usbmsc/index.rst +++ b/Documentation/applications/system/usbmsc/index.rst @@ -13,7 +13,7 @@ This function will be called by the ``system/usbmsc`` indirectly via the ``board block device drivers. For examples of the implementation of ``board_usbmsc_initialize()`` see ``boards/arm/lpc214x/mcu123-lpc214x/src/up_usbmsc.c`` or -``boards/arm/stm32/stm3210e-eval/src/usbmsc.c``. +``boards/arm/stm32f1/stm3210e-eval/src/usbmsc.c``. Configuration options: diff --git a/Documentation/components/drivers/character/leds/userled.rst b/Documentation/components/drivers/character/leds/userled.rst index dd8ae215ccbea..feccbcb4c7dfa 100644 --- a/Documentation/components/drivers/character/leds/userled.rst +++ b/Documentation/components/drivers/character/leds/userled.rst @@ -59,7 +59,7 @@ Files supporting USERLED can be found in the following locations: Something important to note is that your board initialization code (normally named ``_bringup.c`` should call the function to register the driver. -For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: +For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: .. code-block:: C diff --git a/Documentation/components/drivers/character/serial.rst b/Documentation/components/drivers/character/serial.rst index 7af619f1270ea..6fb2e9cb3fc3f 100644 --- a/Documentation/components/drivers/character/serial.rst +++ b/Documentation/components/drivers/character/serial.rst @@ -39,7 +39,7 @@ Serial Device Drivers `character drivers <#chardrivers>`__ and are accessed as other character drivers. -- **Examples**: ``arch/arm/src/stm32/stm32_serial.c``, +- **Examples**: ``arch/arm/src/common/stm32/stm32_serial_m3m4_usart_v1v2v3v4.c``, ``arch/arm/src/lpc214x/lpc214x_serial.c``, ``arch/z16/src/z16f/z16f_serial.c``, etc. diff --git a/Documentation/components/drivers/special/lcd.rst b/Documentation/components/drivers/special/lcd.rst index 3e415e19694c9..5417a2a1bb96a 100644 --- a/Documentation/components/drivers/special/lcd.rst +++ b/Documentation/components/drivers/special/lcd.rst @@ -85,7 +85,7 @@ LCDs Generic LCD driver for LCDs based on the Solomon Systech SSD1289 LCD controller. Think of this as a template for an LCD driver that you will probably have to customize for any particular LCD - hardware. (See also boards/arm/stm32/hymini-stm32v/src/ssd1289.c below). + hardware. (See also boards/arm/stm32f1/hymini-stm32v/src/ssd1289.c below). - ``st7567.c`` @@ -120,7 +120,7 @@ OLEDs OLED Display Module, UUG-2864AMBAG01, Univision Technology Inc. Based on the SH1101A controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/lpc214x/zp214xpa - ``ug-9664hswag01.c`` @@ -140,7 +140,7 @@ OLEDs Densitron Technologies DD-12864WO-4A which is based on SSD1309 LCD controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/sam34/sam4l-xplained Segment LCDS (SLCDs) diff --git a/Documentation/components/drivers/special/sdio.rst b/Documentation/components/drivers/special/sdio.rst index 6822b82d38867..ba62f20495750 100644 --- a/Documentation/components/drivers/special/sdio.rst +++ b/Documentation/components/drivers/special/sdio.rst @@ -29,7 +29,7 @@ SDIO Device Drivers #. Provide that instance to the initialization method of the higher level device driver. -- **Examples**: ``arch/arm/src/stm32/stm32_sdio.c`` and +- **Examples**: ``arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c`` and ``drivers/mmcsd/mmcsd_sdio.c`` Implementing an SDIO lower-half diff --git a/Documentation/components/drivers/special/usbdev.rst b/Documentation/components/drivers/special/usbdev.rst index 589a60b7b7f0c..1b83d9a20d783 100644 --- a/Documentation/components/drivers/special/usbdev.rst +++ b/Documentation/components/drivers/special/usbdev.rst @@ -19,7 +19,7 @@ USB Device-Side Drivers ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c``, ``arch/arm/src/lpc214x/lpc214x_usbdev.c``, ``arch/arm/src/lpc313x/lpc313x_usbdev.c``, and - ``arch/arm/src/stm32/stm32_usbdev.c``. + ``arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c``. - ``struct usbdevclass_driver_s``. Each USB device class driver must implement an instance of diff --git a/Documentation/components/drivers/special/usbhost.rst b/Documentation/components/drivers/special/usbhost.rst index 63077758d102b..078677d5e2968 100644 --- a/Documentation/components/drivers/special/usbhost.rst +++ b/Documentation/components/drivers/special/usbhost.rst @@ -17,7 +17,7 @@ USB Host-Side Drivers **Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``, - ``arch/arm/src/stm32/stm32_otgfshost.c``, + ``arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c``, ``arch/arm/src/sama5/sam_ohci.c``, and ``arch/arm/src/sama5/sam_ehci.c``. diff --git a/Documentation/contributing/making-changes.rst b/Documentation/contributing/making-changes.rst index a60182210b486..7cbe6cb0add28 100644 --- a/Documentation/contributing/making-changes.rst +++ b/Documentation/contributing/making-changes.rst @@ -227,7 +227,7 @@ squash before submitting the Pull Request: .. code-block:: bash - arch/arm/stm32/: Add arch support for stm32 platform + arch/arm/stm32f4/: Add arch support for stm32f4 platform This patch adds initial support for stm32 platform. Please read the documentation included for more details how to wire the display. diff --git a/Documentation/guides/changing_systemclockconfig.rst b/Documentation/guides/changing_systemclockconfig.rst index 872415486ebe0..0b5039ee2ce7c 100644 --- a/Documentation/guides/changing_systemclockconfig.rst +++ b/Documentation/guides/changing_systemclockconfig.rst @@ -28,7 +28,7 @@ Custom Clock Configuration The ``configs/vsn/`` configuration does something like you say. It skips the initial clock configuration by defining ``CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y``. Then the normal clock -configuration logic in ``arch/arm/src/stm32/stm32_rcc.c`` is not executed. +configuration logic in ``arch/arm/src/stm32f4/stm32_rcc.c`` is not executed. Instead, the "custom" clock initialization at ``configs/vsn/src/sysclock.c`` is called: @@ -83,7 +83,7 @@ are hardcoded in the board.h header file. So you have two options: 2. **Variable Peripheral Clocking**. You can make the peripheral clocking variable. I had to do this for the SAMA5Dx family. Look at - ``boards/arm/stm32/sama5d4-ek/include/board_sdram.h`` for example. Notice + ``boards/arm/sama5/sama5d4-ek/include/board_sdram.h`` for example. Notice that the frequencies are not constants, but function calls: .. code-block:: c diff --git a/Documentation/guides/etcromfs.rst b/Documentation/guides/etcromfs.rst index 8bc92ef989e61..39ce17bddd2ea 100644 --- a/Documentation/guides/etcromfs.rst +++ b/Documentation/guides/etcromfs.rst @@ -86,7 +86,7 @@ behave as follows at Nuttx start-up time: ``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might provide useful examples: - - ``boards/arm/stm32/hymini-stm32v/nsh2`` + - ``boards/arm/stm32f1/hymini-stm32v/nsh2`` - ``boards/arm/dm320/ntosd-dm320/nsh`` - ``boards/sim/sim/sim/nsh`` - ``boards/sim/sim/sim/nsh2`` diff --git a/Documentation/guides/ipv6.rst b/Documentation/guides/ipv6.rst index d67c30c51899b..bf02bc57f8137 100644 --- a/Documentation/guides/ipv6.rst +++ b/Documentation/guides/ipv6.rst @@ -218,7 +218,7 @@ Board Configurations At present, there are three board configuration that are pre-configured to use IPv6: ``nuttx/boards/arm/tiva/dk-tm4c129x/configs/ipv6``, -``nuttx/boards/arm/stm32/stm32f4discovery/ipv6``, and +``nuttx/boards/arm/stm32f4/stm32f4discovery/ipv6``, and ``nuttx/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6``. These default configurations have only IPv6 enabled. But the `README` files at in those board directories describes how to enable `both` IPv4 and IPv6 simultaneously. @@ -345,4 +345,4 @@ the network utils (``netutils``). * Netutils: The network utilities in ``apps/netutils`` have been adapted to work with IPv6: DHCP, FTP, TFTP, Telnet, etc. Support for managing IPv6 address have been included in the ``netlib``, but nothing else has yet been - updated. \ No newline at end of file + updated. diff --git a/Documentation/guides/nsh_network_link_management.rst b/Documentation/guides/nsh_network_link_management.rst index 3100f7ba7d810..05cc4f9d41946 100644 --- a/Documentation/guides/nsh_network_link_management.rst +++ b/Documentation/guides/nsh_network_link_management.rst @@ -45,7 +45,7 @@ must be satisfied: are implemented for Atmel SAM4/4, SAMA5 families, and for the STMicro STM32. See ``nuttx/arch/arm/src/sam34/sam_emac.c``, ``nuttx/arch/arm/src/sam34/sam_emaca.c``, ``sam_emacb.c``, and ``sam_gmac.c``, - and ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + and ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. - ``CONFIG_ARCH_PHY_INTERRUPT`` This is not a user-selectable option. Rather, it is set when selecting a board that supports PHY interrupts. In most architectures, the PHY interrupt is not diff --git a/Documentation/guides/ofloader.rst b/Documentation/guides/ofloader.rst index 743fb9d1328b5..4dfe2375dc989 100644 --- a/Documentation/guides/ofloader.rst +++ b/Documentation/guides/ofloader.rst @@ -52,7 +52,7 @@ Precautions 1.If you need to implement the ofloader on a different board, you will need to read the `wiki ` and refer to the implementation of "ofloader.ld" linker script located -in the "boards/arm/stm32/stm32f429i-disco/scripts" directory. +in the "boards/arm/stm32f4/stm32f429i-disco/scripts" directory. This linker script defines how the different sections of the NuttX image are placed in memory. You should configure the corresponding sections to be located in RAM, where the J-Link can write the image correctly. diff --git a/Documentation/guides/partially_linked_elf.rst b/Documentation/guides/partially_linked_elf.rst index 0fe721e69edc0..b2b6ee8f307d3 100644 --- a/Documentation/guides/partially_linked_elf.rst +++ b/Documentation/guides/partially_linked_elf.rst @@ -40,7 +40,7 @@ compatible with the example provided here: In this example, let's illustrate this using an STM32F4-Discovery configuration. We will assume that you have modified the - ``boards/arm/stm32/stm32fdiscovery/src/stm32_bringup.c`` file, adding the + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` file, adding the following: .. code-block:: c diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index e7c04a2f3e3bd..876d184242fc3 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -191,7 +191,7 @@ An Example There is a good example in the STM32 Ethernet driver. The STM32 F7 Ethernet driver (``arch/arm/src/stm32f7/stm32_ethernet.c``) derives directly from the STM32 F4 Ethernet driver -(``arch/arm/src/stm32/stm32_eth.c``). These two Ethernet MAC peripherals +(``arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``). These two Ethernet MAC peripherals are nearly identical. Only changes that are a direct consequence of the STM32 F7 D-Cache were required to make the driver work on the STM32 F7. Those changes are summarized below. diff --git a/Documentation/guides/protected_build.rst b/Documentation/guides/protected_build.rst index e2a60713a3ae8..a49702df5c7ee 100644 --- a/Documentation/guides/protected_build.rst +++ b/Documentation/guides/protected_build.rst @@ -177,10 +177,10 @@ Files and Directories Here is a summary of directories and files used by the STM32F4Discovery protected build: -* ``boards/arm/stm32/stm32f4discovery/configs/kostest``. This is the kernel +* ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. This is the kernel mode OS test configuration. The two standard configuration files can be found in this directory: (1) ``defconfig`` and (2) ``Make.defs``. -* ``boards/arm/stm32/stm32f4discovery/kernel``. This is the first past +* ``boards/arm/stm32f4/stm32f4discovery/kernel``. This is the first past build directory. The Makefile in this directory is invoked to produce the pass1 object (``nuttx_user.elf`` in this case). The second pass object is created by ``arch/arm/src/Makefile``. Also @@ -188,7 +188,7 @@ protected build: contains a header that includes information need by the kernel blob in order to interface with the user-code. That header is defined in by this file. -* ``boards/arm/stm32/stm32f4discovery/scripts``. Linker scripts for +* ``boards/arm/stm32f4/stm32f4discovery/scripts``. Linker scripts for the kernel mode build are found in this directory. This includes (1) ``memory.ld`` which hold the common memory map, (2) ``user-space.ld`` that is used for linking the pass1 user-mode blob, and (3) @@ -314,11 +314,11 @@ Comparing the "Flat" Build Configuration with the Protected Build Configuration =============================================================================== Compare, for example the configuration -``boards/arm/stm32/stm32f4discovery/configs/ostest`` and the -configuration ``boards/arm/stm32/stm32f4discovery/configs/kostest``. +``boards/arm/stm32f4/stm32f4discovery/configs/ostest`` and the +configuration ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. These two configurations are identical except that one builds a "flat" version of OS test and the other builds a kernel version -of the OS test. See the file ``boards/arm/stm32/stm32f4discovery/README.txt`` +of the OS test. See the file ``boards/arm/stm32f4/stm32f4discovery/README.txt`` for more details about those configurations. The configurations can be compared using the ``cmpconfig`` tool: @@ -328,7 +328,7 @@ The configurations can be compared using the ``cmpconfig`` tool: cd tools make -f Makefile.host cmpconfig cd .. - tools/cmpconfig boards/arm/stm32/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig + tools/cmpconfig boards/arm/stm32f4/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig Here is a summary of the meaning of all of the important differences in the configurations. This should be enough information for you to convert any @@ -337,7 +337,7 @@ configuration from a "flat" to a protected build: * ``CONFIG_BUILD_2PASS=y``. This enables the two pass build. * ``CONFIG_BUILD_PROTECTED=y``. This option enables the "two pass" protected build. -* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel"``. +* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel"``. This tells the build system the (relative) location of the pass1 build directory. * ``CONFIG_PASS1_OBJECT=""``. In some "two pass" build configurations, the build system need to know the name of the first pass object. @@ -382,7 +382,7 @@ configuration from a "flat" to a protected build: These includes such things as initializing device drivers. These same initialization steps must be performed in kernel mode for the protected build and ``CONFIG_BOARD_LATE_INITIALIZE``. - See ``boards/arm/stm32/stm32f4discovery/src/up_boot.c`` for an + See ``boards/arm/stm32f4/stm32f4discovery/src/up_boot.c`` for an example of such board initialization code. Architecture-Specific Options: @@ -409,8 +409,8 @@ Size Expansion The protected build will, or course, result in a FLASH image that is larger than that of the corresponding "flat" build. How much larger? I don't have the numbers in hand, but you can build -``boards/arm/stm32/stm32f4discovery/configs/nsh`` and -``boards/arm/stm32/stm32f4discovery/configs/kostest`` and compare +``boards/arm/stm32f4/stm32f4discovery/configs/nsh`` and +``boards/arm/stm32f4/stm32f4discovery/configs/kostest`` and compare the resulting binaries for yourself using the ``size`` command. Increases in size are expected because: diff --git a/Documentation/guides/smaller_vector_tables.rst b/Documentation/guides/smaller_vector_tables.rst index 2cc629fa2a5c8..ed44b0432d201 100644 --- a/Documentation/guides/smaller_vector_tables.rst +++ b/Documentation/guides/smaller_vector_tables.rst @@ -202,7 +202,7 @@ Most ARMv7-M architectures support two mechanism for handling interrupts: ``CONFIG_ARMV7M_CMNVECTOR=y`` that can be found in ``arch/arm/src/armv7-m/``, and * MCU-specific interrupt handling logic. For the - STM32, this logic can be found at ``arch/arm/src/stm32/gnu/stm32_vectors.S``. + STM32, this logic can be found at ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``. The `common` vector logic is slightly more efficient, the MCU-specific logic is slightly more flexible. @@ -229,7 +229,7 @@ This technical approach requires changes to three files: define ``only`` the small set of 20 ``mapped`` IRQ numbers in the range from 0 through 19. It would also set ``NR_IRQS`` to the value 20. -* A new header file at ``arch/arm/src/stm32/hardware``, say +* A new header file at ``arch/arm/src/stm32f4/hardware``, say ``xyz_vector.h``. It would be similar to the other vector definitions files in that directory: It will consist of a sequence of 100 ``VECTOR`` and ``UNUSED`` macros. It will @@ -248,7 +248,7 @@ This has all been replaced with the common vector handling at Vector Definitions ================== -In ``arch/arm/src/stm32/gnu/stm32_vector.S``, notice that the +In ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``, notice that the ``xyz_vector.h`` file will be included twice. Before each inclusion, the macros ``VECTOR`` and ``UNUSED`` are defined. @@ -290,7 +290,7 @@ file like this: ... Where the value of ``STM32_IRQ_USART1`` was defined to -be 12 in the ``arch/arm/include/stm32/xyz_irq.h`` header +be 12 in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file. When ``xyz_vector.h`` is included by ``stm32_vectors.S`` with the above definitions for ``VECTOR`` and ``UNUSED``, the following would result: @@ -349,7 +349,7 @@ second time the ``xzy_vector.h`` is included by ``stm32_vectors.S``: In the above USART1 example, a single handler would be generated that will provide the IRQ number 12. Remember that 12 is the expansion of the macro ``STM32_IRQ_USART1`` -that is provided in the ``arch/arm/include/stm32/xyz_irq.h`` +that is provided in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file: .. code-block:: asm diff --git a/Documentation/guides/stm32ccm.rst b/Documentation/guides/stm32ccm.rst index 4ec8ba5acb398..1414813180506 100644 --- a/Documentation/guides/stm32ccm.rst +++ b/Documentation/guides/stm32ccm.rst @@ -34,7 +34,7 @@ This memory allocator is automatically enabled when the following options are se * ``CONFIG_MM_MULTIHEAP`` Support for multiple heaps is enabled. Under those conditions, the CCM memory allocator is enabled and the allocator -interfaces prototyped in the ``arch/arm/src/stm32/stm32_ccm.h`` are available. +interfaces prototyped in the ``arch/arm/src/common/stm32/stm32_ccm.h`` are available. NOTE: These interfaces are, technically, not prototyped since they are really provided via C pre-processor macros. diff --git a/Documentation/guides/usingkernelthreads.rst b/Documentation/guides/usingkernelthreads.rst index 5818842037a20..434dacd62a04a 100644 --- a/Documentation/guides/usingkernelthreads.rst +++ b/Documentation/guides/usingkernelthreads.rst @@ -52,7 +52,7 @@ In order to build the task into the OS as a kernel thread, you simply have to: (1) place the kernel thread code in your board source code directory, and (2) start it with ``kthread_create()`` in your board bring-up logic. There a few examples of this in the NuttX source tree. Here is one: -`https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c `_ +`https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c `_ So that is another trick that you can use to architecture optimal solutions: Create parts of your applications as kernel threads: They need to reside in diff --git a/Documentation/guides/zerolatencyinterrupts.rst b/Documentation/guides/zerolatencyinterrupts.rst index 7acd9352656fc..2a5f14e70c2ed 100644 --- a/Documentation/guides/zerolatencyinterrupts.rst +++ b/Documentation/guides/zerolatencyinterrupts.rst @@ -302,8 +302,8 @@ You can find an example that tests the high priority, nested interrupts in the N * :doc:`/platforms/arm/stm32f1/boards/viewtool-stm32f107/index` Description of the configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/highpri`` Test configuration +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/highpri`` Test configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri`` Test +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri`` Test driver. diff --git a/Documentation/implementation/chip_h.rst b/Documentation/implementation/chip_h.rst index a2b7158412689..2a9d9641986be 100644 --- a/Documentation/implementation/chip_h.rst +++ b/Documentation/implementation/chip_h.rst @@ -12,16 +12,16 @@ If you wonder about the purpose of the two ``chip.h`` files in each arm chip. .. code:: sh $ find arch/arm -name chip.h | grep stm32 - arch/arm/include/stm32/chip.h - arch/arm/src/stm32/chip.h + arch/arm/include/stm32f4/chip.h + arch/arm/src/stm32f4/chip.h -The reason behind ``arch/arm/src/stm32/chip.h`` file was a bad idea +The reason behind ``arch/arm/src/stm32f4/chip.h`` file was a bad idea that happened a long time ago. Right now, I believe that its only required when ``CONFIG_ARMV7M_CMNVECTOR`` -is selected in the configuration. In that case, ``arch/arm/src/stm32/chip.h`` +is selected in the configuration. In that case, ``arch/arm/src/stm32f4/chip.h`` is included by ``arch/arm/src/armv7-m/up_vectors.c`` in order provide -the number of interrupt vectors. In stm32, ``arch/arm/src/stm32/chip.h`` +the number of interrupt vectors. In stm32, ``arch/arm/src/stm32f4/chip.h`` provides the number of vectors indirectly by including the correct, chip-specific vectors.h file. This function is a little more obvious in ``arch/arm/srch/lpc43xx/chip.h``. diff --git a/Documentation/implementation/file_descriptors.rst b/Documentation/implementation/file_descriptors.rst index dfad984a347c8..a54ffae2f04ee 100644 --- a/Documentation/implementation/file_descriptors.rst +++ b/Documentation/implementation/file_descriptors.rst @@ -135,7 +135,7 @@ Detached File Helpers Once the file structure has been detached from its file descriptor, you can no longer use the standard VFS functions ``read()``, ``write()``, ``ioctl()``, etc. Fortunately, there are a parallel set of interfaces -that can be used with detached files. These are decribed in detail +that can be used with detached files. These are described in detail in ``include/nuttx/fs/fs.h`` and only listed here below: .. code-block:: c @@ -153,8 +153,8 @@ in ``include/nuttx/fs/fs.h`` and only listed here below: int file_vfcntl(FAR struct file *filep, int cmd, va_list ap); -The SYLOG Device: A Case Study -============================== +The SYSLOG Device: A Case Study +=============================== This technique is used for the SYSLOG device. Originally, NuttX used file descriptor ``1`` for SYSLOG output by default. For most task groups, @@ -179,7 +179,7 @@ Other Examples There are some other examples in analog joystick lower half drivers that use the ADC character driver to read joystick positions:: - boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c: + boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c: ret = file_detach(fd, &g_adcfile); boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c: diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index d88f092dd4599..315010cc0894a 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -35,7 +35,7 @@ to any supported architecture. Here is the map of initialization function calls:: - __start()-arch/arm/src/stm32/stm32_start.c + __start()-arch/arm/src/common/stm32/stm32_start_m3m4_v1.c | +--*Set stack limit +--stm32_clockconfig() @@ -45,7 +45,7 @@ Here is the map of initialization function calls:: +--showprogress('A') +-- +-- - +--stm32_boardinitialize()-boards/arm/stm32/stm32f4discovery/src/stm32_boot.c + +--stm32_boardinitialize()-boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c | | | +--stm32_spidev_initialize()-stm32_spi.c:ONLY CHIP SELECTS | +--stm32_usbinitialize()- @@ -196,7 +196,7 @@ There are few important things to note about this file. ``.section .vectors, ax``. This pseudo operation will place all of the vectors into a special section call ``.vectors``. On of the STM32 F4 linker scripts is located at -``nuttx/boards/arm/stm32/stm32f4discovery/scripts/ld.script``. +``nuttx/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script``. In that file, you can see that section ``.vectors`` is forced to lie at the very beginning of FLASH memory. The STM32 F4 can be configured to boot in different ways via strapping. @@ -229,7 +229,7 @@ nuttx/arch/arm/src/stm32_start.c ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The reset vector ``__start`` lies in the file -``nuttx/arch/arm/src/stm32/stm32_start.c`` and does the real, +``nuttx/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c`` and does the real, low-level architecture-specific initialization. This initialization includes: 1. ``stm32_clockconfig()`` - Initialize the PLLs and peripheral clocking @@ -262,7 +262,7 @@ low-level architecture-specific initialization. This initialization includes: 7. ``stm32_boardinitialize()`` - Board-specific logic is initialized by calling this function. For the case of the STM32F4Discovery board, this logic can be found at - ``nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c`` and does + ``nuttx/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c`` and does the following operations: a. ``stm32_spidev_initialize()`` - Initialize SPI chip selects @@ -351,19 +351,19 @@ file and in that case those operations are not performed: ``nx_start()``. However, if the board supports multiple, discontiguous memory regions, any addition memory regions can be added to the heap by this function. For the STM32 F4, ``up_addregion()`` is implemented - in ``nuttx/arch/arm/src/stm32/stm32_allocateheap.c``. + in ``nuttx/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c``. * ``arm_pminitialize()`` - If ``CONFIG_PM`` is defined, the function must initialize the power management subsystem. This MCU-specific function - must be called very early in the intialization sequence before any other + must be called very early in the initialization sequence before any other device drivers are initialized (since they may attempt to register with the power management subsystem). There is no implementation of ``up_pminitialize()`` for any STM32 platform. * ``arm_dmainitialize()`` - Initialize the DMA subsystem. For the STM32 F4, this DMA initialization can be found in - ``nuttx/arch/arm/src/stm32/stm32_dma.c`` (which includes - ``nuttx/arch/arm/src/stm32f4xxx_dma.c``). + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c`` (which includes + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c``). * ``devnull_register()`` - Registers the standard ``/dev/null``. @@ -381,11 +381,11 @@ file and in that case those operations are not performed: (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_usart_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, - this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + this function is in ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. * ``arm_usbinitialize()`` - Initialize USB (host or device). For the STM32 F4, this function is in - ``nuttx/arch/arm/src/stm32/stm32_otgfsdev.c``. + ``nuttx/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c``. * ``arm_l2ccinitialize()`` - Initialize the L2 cache if present and selected. @@ -448,7 +448,7 @@ This function performed the following specific operations: for a variety of purposes like misc garbage clean-up. * ``nx_create_initthread()`` - Once the operating system has been initialized, - this funcions either directly calls ``nx_start_application()`` or creates + this functions either directly calls ``nx_start_application()`` or creates a thread for running it * ``nx_start_application()`` - If set in the NuttX configuration, @@ -640,7 +640,7 @@ The resulting ROMFS file system can be found in * ``board_app_initialize()`` - For the STM32F4Discovery, this architecture specific initialization can be found at - ``boards/arm/stm32/stm32f4discovery/src/stm32_appinit.c``. + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_appinit.c``. This it does things like: 1. Initialize SPI devices. diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index 19ce66c3fb07f..9c15d336c5d1c 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -228,13 +228,13 @@ OpenOCD ======= I have also used OpenOCD with the M3 Wildfire. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD + boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh $PWD - Load NuttX:: diff --git a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst index d544bea76b21c..14f2d03a4cd87 100644 --- a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst @@ -517,7 +517,7 @@ NOTES: ADC_IN8 (PB0) CON5 CN14 Pin2 ADC_IN9 (PB1) CON5 CN14 Pin1 - The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The + The signal selection is hard-coded in boards/arm/stm32f1/shenzhou/src/up_adc.c: The potentiometer input (only) is selected. These selections will enable sampling the potentiometer input at 100Hz using diff --git a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst index fb218ff3c3b13..3e499fbfe9b2c 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst @@ -87,13 +87,13 @@ OpenOCD ======= I have also used OpenOCD with the STM3210E-EVAL. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD + boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh $PWD - Load NuttX:: @@ -171,7 +171,7 @@ More complex temperature sensor operations are also available. See the IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the descriptions of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the arch/board/board.h file (sames as -boards/arm/stm32/stm3210e-eval/include/board.h). +boards/arm/stm32f1/stm3210e-eval/include/board.h). NSH Command Line Application ---------------------------- @@ -812,7 +812,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -824,8 +824,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 4. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst index 68819f0f60316..e818cabd22119 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst @@ -186,7 +186,7 @@ instead of 64KiB as documented in the datasheet and reported by its internal register. In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace:: +new size. Open the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script and replace:: flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K @@ -358,7 +358,7 @@ enable/disable these options using "make menuconfig" :: Memory Management ---> [*] Small memory model - Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB + Also change the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script file to use 128KB of Flash instead 64KB (since this board has a hidden 64KB flash) : MEMORY diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst index 8e76e5abc8c3a..81c6d7b82893a 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst @@ -12,7 +12,7 @@ LEDs It is assumed that STMicro STM32F100RB generic board board has one LED on PA0. You should configure the port and pin number in -boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in include/board.h and src/up_leds.c. The LED is used to encode OS-related events as follows:: diff --git a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst index 40be36a057637..b2584194578dd 100644 --- a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst @@ -79,7 +79,7 @@ Using JTAG The Clicker2 comes with the mikroBootloader installed. That bootloader has not been used and is possibly incompatible with the Clicker2-STM32 -linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must +linker script at boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld. Often code must be built to execute at an offset in to FLASH when a bootloader is used. Certainly that is the case for the ST-Micro DFU bootloader but I am not aware of the requirements for use with the mikroBootloader. diff --git a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst index 7021a333f0edc..e81cd71ba97bc 100644 --- a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst @@ -79,6 +79,6 @@ package as flexible as, say, an STM32F4 Discovery board. Build Instructions ================== -The boards/arm/stm32/omnibusf4/nsh/defconfig file creates a basic setup, and +The boards/arm/stm32f4/omnibusf4/nsh/defconfig file creates a basic setup, and includes drivers for all supported onboard chips. The console and command prompt are sent to USART3. diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst index 65a7eaf78317a..ea78006fcfde1 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst @@ -517,7 +517,7 @@ MAPPING TO STM32 F4:: 4 Also the reset pin for the CS43L22 audio Codec. NOTE: The configuration to test this LCD configuration is available at -boards/arm/stm32/stm32f4discovery/nxlines. As of this writing, I have not seen the +boards/arm/stm32f4/stm32f4discovery/nxlines. As of this writing, I have not seen the LCD working so I probably have some things wrong. I might need to use a bit-banging interface. Below is the pin configuration @@ -613,7 +613,7 @@ that I am using:: Darcy Gong recently added support for the UG-2864HSWEG01 OLED which is also an option with this configuration. I have little technical information about -the UG-2864HSWEG01 interface (see boards/arm/stm32/stm32f4discovery/src/up_ug2864hsweg01.c). +the UG-2864HSWEG01 interface (see boards/arm/stm32f4/stm32f4discovery/src/up_ug2864hsweg01.c). NiceRF LoRa (2AD66-LoRa V2) =========================== @@ -639,7 +639,7 @@ connect the CS to PA4, connect RST to PE1 and finally connect INT to PE4. The next step is to enable the ENC28J60 in the menuconfig ("make menuconfig") and the necessary Network configuration, you can use the -boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig as reference. +boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig as reference. HCI UART ======== @@ -1202,7 +1202,7 @@ NOTES: The HCI UART selection can be changed by re-configuring and assigning the different U[S]ART to the HCI. The U[S]ART pin selections can be changed by modifying the disambiguation definitions in -boards/arm/stm32/stm32f4discovery/include/board.h +boards/arm/stm32f4/stm32f4discovery/include/board.h I have been testing with the DVK_BT960_SA board via J10 as follows:: @@ -2021,7 +2021,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -2033,8 +2033,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 3. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f4/index.rst b/Documentation/platforms/arm/stm32f4/index.rst index 3684b7dd5a012..474dae92be608 100644 --- a/Documentation/platforms/arm/stm32f4/index.rst +++ b/Documentation/platforms/arm/stm32f4/index.rst @@ -389,7 +389,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst index 578ca414e579b..0c691673f2abe 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst @@ -106,7 +106,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst index 17cb93b0dcc15..914494906fa04 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst @@ -107,7 +107,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index 006444feb8e43..af0cb591ebed9 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -68,7 +68,7 @@ specified by several settings in the NuttX configuration file. sub-directories and are discussed in a paragraph `below <#boards-subdirectory-structure>`__. - The directory ``boards/arm/stm32/stm32f4disovery/``, as an + The directory ``boards/arm/stm32f4/stm32f4discovery/``, as an example, holds board-specific logic for the STM32F4 Discovery board and is selected via the ``CONFIG_ARCH_BOARD="stm32f4discovery"`` configuration setting. diff --git a/LICENSE b/LICENSE index a76c658ae4ebe..a22fd18f55966 100644 --- a/LICENSE +++ b/LICENSE @@ -2918,7 +2918,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/photon/src/stm32_wlan_firmware.c +boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h ================================================ @@ -3249,8 +3249,8 @@ ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. boards/arm/rp2040/common/src/rp2040_ina219.c -boards/arm/stm32/common/src/stm32_ina219.c -boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +boards/arm/common/stm32/src/stm32_ina219.c +boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c =============================================== Copyright (C) 2018,2019 Erle Robotics (Juan Flores Muñoz). All rights reserved. @@ -3282,9 +3282,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f303re/src/stm32_uid.c -boards/arm/stm32/omnibusf4/src/stm32_uid.c -boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c +boards/arm/stm32f4/omnibusf4/src/stm32_uid.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c boards/arm/stm32h7/nucleo-h743zi/src/stm32_uid.c boards/arm/stm32h7/stm32h747i-disco/src/stm32_uid.c =============================================== @@ -3317,8 +3317,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c -boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c +boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c ================================================= Copyright (C) 2017 Gregory Nutt. All rights reserved. Copyright (C) 2017 Brian Webb. All rights reserved. @@ -3350,10 +3350,10 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/omnibusf4/src/stm32_romfs.h -boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c -boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h -boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c boards/arm/stm32f7/common/include/stm32_romfs.h boards/arm/stm32f7/common/src/stm32_romfs_initialize.c ============================================================= @@ -3975,7 +3975,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f100_pinmap.h +arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h ================================================= Copyright (C) 2009 Gregory Nutt. All rights reserved. @@ -4009,7 +4009,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h ==================================================== Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. @@ -4042,7 +4042,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_alt.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c =================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4076,7 +4076,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_v2.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4110,8 +4110,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_sdadc.c -arch/arm/src/stm32/stm32_sdadc.h +arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c +arch/arm/src/common/stm32/stm32_sdadc.h =================================== Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. @@ -4144,7 +4144,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tickless.c +arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c ====================================== Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. @@ -4177,7 +4177,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c =========================================== Copyright (C) 2015 Wail Khemir. All rights reserved. @@ -4210,8 +4210,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_uid.c -arch/arm/src/stm32/stm32_uid.h +arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c +arch/arm/src/common/stm32/stm32_uid.h =================================== Copyright (C) 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 603dab1a96506..e45eed4a24eee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1317,8 +1317,16 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default "stm32f1" if ARCH_CHIP_STM32F1 + default "stm32f2" if ARCH_CHIP_STM32F2 + default "stm32f3" if ARCH_CHIP_STM32F3 + default "stm32f4" if ARCH_CHIP_STM32F4 + default "stm32g4" if ARCH_CHIP_STM32G4 + default "stm32l1" if ARCH_CHIP_STM32L1 + default "stm32f0" if ARCH_CHIP_STM32F0 + default "stm32l0" if ARCH_CHIP_STM32L0 + default "stm32g0" if ARCH_CHIP_STM32G0 + default "stm32c0" if ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -1819,11 +1827,35 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 -source "arch/arm/src/stm32/Kconfig" +if ARCH_CHIP_STM32F1 +source "arch/arm/src/stm32f1/Kconfig" endif -if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 -source "arch/arm/src/stm32f0l0g0/Kconfig" +if ARCH_CHIP_STM32F2 +source "arch/arm/src/stm32f2/Kconfig" +endif +if ARCH_CHIP_STM32F3 +source "arch/arm/src/stm32f3/Kconfig" +endif +if ARCH_CHIP_STM32F4 +source "arch/arm/src/stm32f4/Kconfig" +endif +if ARCH_CHIP_STM32G4 +source "arch/arm/src/stm32g4/Kconfig" +endif +if ARCH_CHIP_STM32L1 +source "arch/arm/src/stm32l1/Kconfig" +endif +if ARCH_CHIP_STM32F0 +source "arch/arm/src/stm32f0/Kconfig" +endif +if ARCH_CHIP_STM32L0 +source "arch/arm/src/stm32l0/Kconfig" +endif +if ARCH_CHIP_STM32G0 +source "arch/arm/src/stm32g0/Kconfig" +endif +if ARCH_CHIP_STM32C0 +source "arch/arm/src/stm32c0/Kconfig" endif if ARCH_CHIP_STM32F7 source "arch/arm/src/stm32f7/Kconfig" diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h deleted file mode 100644 index 1c62bcc3c4b57..0000000000000 --- a/arch/arm/include/stm32/chip.h +++ /dev/null @@ -1,2756 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Check the STM32 family configuration. - * It must be done in arch/arm/src/stm32/Kconfig ! - */ - -#ifdef CONFIG_STM32_STM32F10XX -# define __HAVE_F1 1 -#else -# define __HAVE_F1 0 -#endif -#ifdef CONFIG_STM32_STM32F20XX -# define __HAVE_F2 1 -#else -# define __HAVE_F2 0 -#endif -#ifdef CONFIG_STM32_STM32F30XX -# define __HAVE_F30 1 -#else -# define __HAVE_F30 0 -#endif -#ifdef CONFIG_STM32_STM32F33XX -# define __HAVE_F33 1 -#else -# define __HAVE_F33 0 -#endif -#ifdef CONFIG_STM32_STM32F37XX -# define __HAVE_F37 1 -#else -# define __HAVE_F37 0 -#endif -#ifdef CONFIG_STM32_STM32F4XXX -# define __HAVE_F4 1 -#else -# define __HAVE_F4 0 -#endif -#ifdef CONFIG_STM32_STM32G4XXX -# define __HAVE_G4 1 -#else -# define __HAVE_G4 0 -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define __HAVE_L1 1 -#else -# define __HAVE_L1 0 -#endif - -#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \ - __HAVE_G4 + __HAVE_L1) != 1) -# error "Only one STM32 family must be selected !" -#endif - -#ifdef CONFIG_STM32_LOWDENSITY -# define __HAVE_LD 1 -#else -# define __HAVE_LD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMDENSITY -# define __HAVE_MD 1 -#else -# define __HAVE_MD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMPLUSDENSITY -# define __HAVE_MPD 1 -#else -# define __HAVE_MPD 0 -#endif -#ifdef CONFIG_STM32_HIGHDENSITY -# define __HAVE_HD 1 -#else -# define __HAVE_HD 0 -#endif - -#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1 -# error "Up to one density configuration must be selected" -#endif - -/* Get customizations for each supported chip and provide alternate function - * pin-mapping - * - * NOTE: Each GPIO pin may serve either for general purpose I/O or for a - * special alternate function (such as USART, CAN, USB, SDIO, etc.). That - * particular pin-mapping will depend on the package and STM32 family. If - * you are incorporating a new STM32 chip into NuttX, you will need to add - * the pin-mapping to a header file and to include that header file below. - * The chip-specific pin-mapping is defined in the chip datasheet. - */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L151XX -- No LCD - * STM32L152XX -- With LCD - * - * STM32L15XCX -- 48-pins - * STM32L15XRX -- 64-pins - * STM32L15XVX -- 100-pins - * STM32L15XZX -- 144-pins - * - * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM - * - * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) - * - * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) - * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) - */ - -#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC , 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 21-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 109 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-G,H */ -# define STM32_NADC 1 /* ADC1, 40-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 12-channels */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-G,H */ - -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 Value Line ****************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ - || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 High-density value Line ***************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100RE) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Low Density Family ********************************************/ - -/* STM32F103C4 & STM32F103C6 */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 2 /* General timers TIM2,3 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timer */ -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Medium Density Performance Line *******************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 26 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 High Density Family *******************************************/ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-D */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* General timers TIM2-5 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 3 /* ADC1-3 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 112 /* GPIOA-G */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F105/F107 Connectivity Line ****************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2*/ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 82 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 140 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -/* STM23 F3 Family **********************************************************/ - -/* Part Numbering: STM32Fssscfxxx - * - * Where - * sss = 302/303, 334 or 372/373 - * c = C (48pins) R (68 pins) V (100 pins) - * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) - * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) - * xxx = Package, temperature range, options (ignored here) - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 24 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (2) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 115 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 2 /* (2) USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ -# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 - * (2) 32-bit general timers with DMA: TIM2 and TIM5 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ -# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -/* STM23 F4 Family **********************************************************/ - -/* STM32F01xB/C Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 - * STM32F401RB LQFP64 128Kb Yes 16 - * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 - * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 - * STM32F401RC LQFP64 256Kb Yes 16 - * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F01xD/E Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 - * STM32F401RD LQFP64 384Kb Yes 16 - * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 - * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 - * STM32F401RE LQFP64 512Kb Yes 16 - * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-4 */ -# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 81 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ -# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 113 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 168 /* GPIOA-K */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ - defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NGPIO 114 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) -# define STM32_NGPIO 131 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NGPIO 161 /* GPIOA-K */ -# endif -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# endif -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431K) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 26 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 66 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431V) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-C, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 67 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-D, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 107 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474V) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#else -# error "Unsupported STM32 chip" -#endif - -/* Peripheral IP versions ***************************************************/ - -/* Peripheral IP versions are invariant and should be decided here, not in - * Kconfig. - * - * REVISIT: Currently only SPI IP version is handled here, with others being - * handled in Kconfig. Those others need to be gradually refactored - * and resolved here. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F20XX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32F30XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F33XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F4XXX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_HAVE_IP_SPI_V4 - -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_HAVE_IP_SPI_V1 - -#else -# error "Did not resolve peripheral IP versions!" -#endif - -/* NVIC priority levels *****************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ - -#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h deleted file mode 100644 index 6e55b57a3fcf5..0000000000000 --- a/arch/arm/include/stm32/irq.h +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - */ - -/* Processor Exceptions (vectors 0-15) */ - -#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ -#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16). - * These definitions are chip-specific - */ - -#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -# include -#elif defined(CONFIG_STM32_STM32F10XX) -# include -#elif defined(CONFIG_STM32_STM32F20XX) -# include -#elif defined(CONFIG_STM32_STM32F30XX) -# include -#elif defined(CONFIG_STM32_STM32F33XX) -# include -#elif defined(CONFIG_STM32_STM32F37XX) -# include -#elif defined(CONFIG_STM32_STM32F4XXX) -# include -#elif defined(CONFIG_STM32_STM32G4XXX) -# include -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h deleted file mode 100644 index 52d1b038f7826..0000000000000 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ /dev/null @@ -1,298 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f10xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -/* Value line devices */ - -#if defined(CONFIG_STM32_VALUELINE) -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */ -# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */ -# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */ -# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */ -# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */ -# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ -# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ -# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ -# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */ -# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */ -# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ -# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ -# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ - -# define STM32_IRQ_NEXTINTS (61) - -/* Connectivity Line Devices */ - -#elif defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ -# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */ -# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */ -# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */ -# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */ -# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */ -# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */ -# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */ -# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */ -# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ -# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */ -# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */ -# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */ -# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */ -# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */ -# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ -# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ - -# define STM32_IRQ_NEXTINTS (68) - -/* Medium and High Density Devices */ - -#else -# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ -# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ -# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ -# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ -# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/ -# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/ -# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ -# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ -# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ -# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ -# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/ -# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */ -# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */ -# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */ -# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */ -# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ -# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */ -# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ -# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ -# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */ - -# define STM32_IRQ_NEXTINTS (60) - -/* Convenience definitions for interrupts with multiple functions */ - -# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX -# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX -# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0 -# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0 -#endif - -# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f20xxx_irq.h b/arch/arm/include/stm32/stm32f20xxx_irq.h deleted file mode 100644 index fddc984135928..0000000000000 --- a/arch/arm/include/stm32/stm32f20xxx_irq.h +++ /dev/null @@ -1,172 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f20xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */ -#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */ -#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */ -#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */ -#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */ -#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */ -#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */ -#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ -#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */ -#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */ -#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */ -#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */ -#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 49) /* 49: SDIO global interrupt */ -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */ -#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */ -#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */ -#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */ -#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */ -#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */ -#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */ -#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */ -#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */ -#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */ -#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */ -#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */ -#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */ -#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */ -#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */ -#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ -#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */ -#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ -#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */ -#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */ -#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */ -#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ -#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ - -#define STM32_IRQ_NEXTINTS (81) -#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32/stm32f40xxx_irq.h deleted file mode 100644 index 268bcc2323bf1..0000000000000 --- a/arch/arm/include/stm32/stm32f40xxx_irq.h +++ /dev/null @@ -1,347 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32f40xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can - * be found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ -#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ -#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ -#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ -#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ -#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ -#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ -#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED19 (STM32_IRQ_FIRST+19) /* 19: Reserved */ -# define STM32_IRQ_RESERVED20 (STM32_IRQ_FIRST+20) /* 20: Reserved */ -# define STM32_IRQ_RESERVED21 (STM32_IRQ_FIRST+21) /* 21: Reserved */ -# define STM32_IRQ_RESERVED22 (STM32_IRQ_FIRST+22) /* 22: Reserved */ -#else -# define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ -# define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ -# define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ -# define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ -#endif - -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ -#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ -#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED28 (STM32_IRQ_FIRST+28) /* 28: Reserved */ -# define STM32_IRQ_RESERVED29 (STM32_IRQ_FIRST+29) /* 29: Reserved */ -# define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */ -#else -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ -#endif - -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED39 (STM32_IRQ_FIRST+39) /* 39: Reserved */ -#else -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ -#endif - -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */ -# define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */ -# define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */ -# define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */ -# define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */ -#else -# define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ -# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ -# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ -# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ -# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ -# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ -# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ -# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ -#endif - -#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */ -# define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 48: Reserved */ -#else -# define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ -# define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */ -#endif - -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */ -# define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */ -# define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */ -#else -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ -# define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ -#endif - -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ -#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED55 (STM32_IRQ_FIRST+55) /* 55: Reserved */ -#else -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ -#endif - -#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ -#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ -#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ -#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ -#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */ -# define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */ -#else -# define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ -# define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */ -# define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST+64) /* 63: Reserved */ -# define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST+65) /* 63: Reserved */ -# define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 63: Reserved */ -# define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 63: Reserved */ -#else -# define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ -# define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ -# define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ -# define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ -# define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ -#endif - -#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ -#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ -#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ -#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */ -# define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */ -# define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */ -# define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */ -# define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */ -# define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */ -# define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */ -#else -# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ -# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ -# define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ -# define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ -# define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ -# define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ -# define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ -# define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ -#else -# if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ -# else -# define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ -# endif -# define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ -# define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ -#endif - -#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */ -# define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */ -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED82 (STM32_IRQ_FIRST+82) /* 82: Reserved */ -# define STM32_IRQ_RESERVED83 (STM32_IRQ_FIRST+83) /* 83: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED84 (STM32_IRQ_FIRST+84) /* 84: Reserved */ -#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ -# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ -#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ -# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */ -#elif defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_RESERVED85 (STM32_IRQ_FIRST+85) /* 85: Reserved */ -# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED87 (STM32_IRQ_FIRST+87) /* 87: Reserved */ -#elif defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */ -# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */ -# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */ -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED88 (STM32_IRQ_FIRST+88) /* 88: Reserved */ -# define STM32_IRQ_RESERVED89 (STM32_IRQ_FIRST+89) /* 89: Reserved */ -# define STM32_IRQ_RESERVED90 (STM32_IRQ_FIRST+90) /* 90: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED91 (STM32_IRQ_FIRST+91) /* 91: Reserved */ -# define STM32_IRQ_RESERVED92 (STM32_IRQ_FIRST+92) /* 92: Reserved */ -#elif defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */ -# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */ -#elif defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+91) /* 92: QuadSPI Global interrupt */ -# define STM32_IRQ_DSI (STM32_IRQ_FIRST+92) /* 91: DSI Global interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F446) -# define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */ -# define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */ -# define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */ -# define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */ -#endif - -#if defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_RESERVED93 (STM32_IRQ_FIRST+93) /* 93: Reserved */ -# define STM32_IRQ_RESERVED94 (STM32_IRQ_FIRST+94) /* 94: Reserved */ -# define STM32_IRQ_RESERVED95 (STM32_IRQ_FIRST+95) /* 95: Reserved */ -# define STM32_IRQ_RESERVED96 (STM32_IRQ_FIRST+96) /* 96: Reserved */ -# define STM32_IRQ_RESERVED97 (STM32_IRQ_FIRST+97) /* 97: Reserved */ -#endif - -#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ - defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) -# define STM32_IRQ_NEXTINTS (82) -#elif defined(CONFIG_STM32_STM32F410) -# define STM32_IRQ_NEXTINTS (98) -#elif defined(CONFIG_STM32_STM32F427) -# define STM32_IRQ_NEXTINTS (87) -#elif defined(CONFIG_STM32_STM32F429) -# define STM32_IRQ_NEXTINTS (91) -#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) -# define STM32_IRQ_NEXTINTS (97) -#elif defined(CONFIG_STM32_STM32F469) -# define STM32_IRQ_NEXTINTS (93) -#endif - -# define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32g4xxxx_irq.h b/arch/arm/include/stm32/stm32g4xxxx_irq.h deleted file mode 100644 index 1d0418be96a18..0000000000000 --- a/arch/arm/include/stm32/stm32g4xxxx_irq.h +++ /dev/null @@ -1,202 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32g4xxxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence - * map directly to bits in the NVIC. This does, however, waste several words - * of memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15) are common to all STM32 parts and are - * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here. - * - * Other interrupts (vectors >= 16) are defined below. - */ - -#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */ -#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp interrupt (shared with STM32_IRQ_TAMPER) */ -#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt, or */ -#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ - -#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 shared global interrupt */ -#define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High priority interrupt */ - -#define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low priority interrupt */ -#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 21) /* 21: FDCAN1 interrupt 0 */ -#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST + 22) /* 22: FDCAN1 interrupt 1 */ -#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt (shared with STM32_IRQ_TIM1BRK) */ -#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break, Transition error, Index error (shared with STM32_IRQ_TIM15) */ -#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt (shared with STM32_IRQ_TIM1UP) */ -#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt (shared with STM32_IRQ_TIM16) */ -#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt (shared with STM32_IRQ_TIM1TRGCOM) */ -#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger, Commutation, Direction Change, and Index interrupt (shared with STM32_IRQ_TIM17) */ -#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - -#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ - -#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */ -#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break, Transition error, Index error */ -#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */ -#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */ -#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 49) /* 49: LPTIM1 interrupt */ - -#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt (shared with STM32_IRQ_DAC1, STM32_IRQ_DAC3) */ -#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC3) */ -#define STM32_IRQ_DAC3 (STM32_IRQ_FIRST + 54) /* 54: DAC3 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC1) */ -#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt (shared with STM32_IRQ_DAC2, STM32_IRQ_DAC4) */ -#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST + 55) /* 55: DAC2 underrun error interrupt (shared with STM32_IRQ_TIM7) */ -#define STM32_IRQ_DAC4 (STM32_IRQ_FIRST + 55) /* 55: DAC4 underrun error interrupt (shared with STM32_IRQ_TIM7) */ -#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 1 global interrupt */ -#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 2 global interrupt */ -#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 3 global interrupt */ -#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 4 global interrupt */ - -#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 5 global interrupt */ -#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 61) /* 61: ADC4 global interrupt */ -#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST + 62) /* 62: ADC5 global interrupt */ -#define STM32_IRQ_UCPD (STM32_IRQ_FIRST + 63) /* 63: UCPD global interrupt */ -#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST + 64) /* 64: COMP1, COMP2, and COMP3 interrupts */ -#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST + 65) /* 65: COMP4, COMP5, and COMP6 interrupts */ -#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST + 66) /* 66: COMPP7 interrupt */ -#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST + 67) /* 67: HRTIM1 master timer interrupt */ -#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST + 68) /* 68: HRTIM1 timer A interrupt */ -#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST + 69) /* 69: HRTIM1 timer B interrupt */ - -#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST + 70) /* 70: HRTIM1 timer C interrupt */ -#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST + 71) /* 71: HRTIM1 timer D interrupt */ -#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST + 72) /* 72: HRTIM1 timer E interrupt */ -#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST + 73) /* 73: HRTIM1 fault interrupt */ -#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST + 74) /* 74: HRTIM1 timer E interrupt */ -#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS (Clock Recovery System) global interrupt */ -#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 76) /* 76: SAI4 global interrupt */ -#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST + 77) /* 77: TIM20 Break, Transition error, Index error interrupt */ -#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST + 78) /* 78: TIM20 Update interrupt */ -#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST + 79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */ - -#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST + 80) /* 80: TIM20 Capture Compare interrupt */ -#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 82) /* 82: I2C4 event interrupt */ -#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 83) /* 83: I2C4 error interrupt */ -#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */ -#define STM32_IRQ_AES (STM32_IRQ_FIRST + 85) /* 85: AES global interrupt */ -#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 86) /* 86: FDCAN2 interrupt 0 */ -#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST + 87) /* 87: FDCAN2 interrupt 1 */ -#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 88) /* 88: FDCAN3 interrupt 0 */ -#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 89) /* 89: FDCAN3 interrupt 1 */ - -#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 90) /* 90: RNG global interrupt */ -#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 91) /* 91: LPUART global interrupt */ -#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 92) /* 92: I2C3 event interrupt */ -#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 93) /* 93: I2C3 error interrupt */ -#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ -#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 95) /* 95: QuadSPI global interrupt */ -#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 96) /* 96: DMA1 channel 8 global interrupt */ -#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 97) /* 97: DMA2 channel 6 global interrupt */ -#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 98) /* 98: DMA2 channel 7 global interrupt */ -#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */ - -#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */ -#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */ - -#define STM32_IRQ_NEXTINTS (102) -#define NR_IRQS (STM32_IRQ_FIRST + 102) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32/stm32l15xxx_irq.h deleted file mode 100644 index 432d4b013c83d..0000000000000 --- a/arch/arm/include/stm32/stm32l15xxx_irq.h +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/stm32l15xxx_irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) for low and medium density devices - */ - -#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ - -# define STM32_IRQ_NEXTINTS (45) - -/* External interrupts (vectors >= 16) medium+ density devices */ - -#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ -# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ -# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 45) /* 45: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 46) /* 46: SPI3 global interrupt */ -# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 47) /* 47: DMA2 channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 48) /* 48: DMA2 channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 49) /* 49: DMA2 channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 5 global interrupt */ -# define STM32_IRQ_AES (STM32_IRQ_FIRST + 52) /* 52: AES global interrupt */ -# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 53) /* 53: Comparator Channel Acquisition Interrupt */ - -# define STM32_IRQ_NEXTINTS (54) - -/* External interrupts (vectors >= 16) high density devices */ - -#elif defined(CONFIG_STM32_HIGHDENSITY) -# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ -# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ -# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ -# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ -# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ -# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ -# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ -# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ -# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ -# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ -# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ -# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ -# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ -# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ -# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ -# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ -# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ -# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ -# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ -# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ -# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ -# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ -# define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 45) /* 45: SDIO Global interrupt */ -# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 46) /* 46: TIM5 global interrupt */ -# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 47) /* 47: SPI3 global interrupt */ -# define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 48) /* 48: UART4 global interrupt */ -# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 49) /* 49: UART5 global interrupt */ -# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 1 global interrupt */ -# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 2 global interrupt */ -# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 52) /* 52: DMA2 channel 3 global interrupt */ -# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 53) /* 53: DMA2 channel 4 global interrupt */ -# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 5 global interrupt */ -# define STM32_IRQ_AES (STM32_IRQ_FIRST + 55) /* 55: AES global interrupt */ -# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 56) /* 56: Comparator Channel Acquisition Interrupt */ - -# define STM32_IRQ_NEXTINTS (57) -#else -# error "Unknown STM32L density" -#endif - -# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */ diff --git a/arch/arm/include/stm32f1/chip.h b/arch/arm/include/stm32f1/chip.h new file mode 100644 index 0000000000000..a216966d478ef --- /dev/null +++ b/arch/arm/include/stm32f1/chip.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/arm/include/stm32f1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ + || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 High-density value Line ***************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100RE) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Low Density Family ********************************************/ + +/* STM32F103C4 & STM32F103C6 */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 2 /* General timers TIM2,3 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timer */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Medium Density Performance Line *******************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 26 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 High Density Family *******************************************/ + +/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-D */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* General timers TIM2-5 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 3 /* ADC1-3 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 112 /* GPIOA-G */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F105/F107 Connectivity Line ****************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2*/ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F2 Family **********************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F1_CHIP_H */ diff --git a/arch/arm/include/stm32f1/irq.h b/arch/arm/include/stm32f1/irq.h new file mode 100644 index 0000000000000..50020cb6d587d --- /dev/null +++ b/arch/arm/include/stm32f1/irq.h @@ -0,0 +1,286 @@ +/**************************************************************************** + * arch/arm/include/stm32f1/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_VALUELINE) +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */ +# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */ +# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */ +# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */ +# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */ +# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ +# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ +# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ +# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */ +# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */ +# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ +# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */ +# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ + +# define STM32_IRQ_NEXTINTS (61) + +#elif defined(CONFIG_STM32_CONNECTIVITYLINE) +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ +# define STM32_IRQ_CAN1TX (35) /* 19: CAN1 TX interrupts */ +# define STM32_IRQ_CAN1RX0 (36) /* 20: CAN1 RX0 interrupts */ +# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_OTGFSWKUP (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +# define STM32_IRQ_RESERVED0 (59) /* 43: Reserved 0 */ +# define STM32_IRQ_RESERVED1 (60) /* 44: Reserved 1 */ +# define STM32_IRQ_RESERVED2 (61) /* 45: Reserved 2 */ +# define STM32_IRQ_RESERVED3 (62) /* 46: Reserved 3 */ +# define STM32_IRQ_RESERVED4 (63) /* 47: Reserved 4 */ +# define STM32_IRQ_RESERVED5 (64) /* 48: Reserved 5 */ +# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (75) /* 59: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */ +# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */ +# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */ +# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */ +# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */ +# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */ +# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */ + +# define STM32_IRQ_NEXTINTS (68) + +#else +# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */ +# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */ +# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (23) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (24) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (25) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (26) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (27) /* 11: DMA1 Channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (28) /* 12: DMA1 Channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (29) /* 13: DMA1 Channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (30) /* 14: DMA1 Channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ +# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */ +# define STM32_IRQ_USBHPCANTX (35) /* 19: USB High Priority or CAN TX interrupts*/ +# define STM32_IRQ_USBLPCANRX0 (36) /* 20: USB Low Priority or CAN RX0 interrupts*/ +# define STM32_IRQ_CAN1RX1 (37) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (38) /* 22: CAN1 SCE interrupt */ +# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ +# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */ +# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */ +# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (46) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (47) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (48) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (49) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (50) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (51) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (52) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (53) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (57) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (58) /* 42: USB wakeup from suspend through EXTI line interrupt*/ +# define STM32_IRQ_TIM8BRK (59) /* 43: TIM8 Break interrupt */ +# define STM32_IRQ_TIM8UP (60) /* 44: TIM8 Update interrupt */ +# define STM32_IRQ_TIM8TRGCOM (61) /* 45: TIM8 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM8CC (62) /* 46: TIM8 Capture Compare interrupt */ +# define STM32_IRQ_ADC3 (63) /* 47: ADC3 global interrupt */ +# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ +# define STM32_IRQ_SDIO (65) /* 49: SDIO global interrupt */ +# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (68) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (69) /* 53: UART5 global interrupt */ +# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */ + +# define STM32_IRQ_NEXTINTS (60) + +# define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX +# define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX +# define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0 +# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0 +#endif + +# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F1_IRQ_H */ diff --git a/arch/arm/include/stm32f2/chip.h b/arch/arm/include/stm32f2/chip.h new file mode 100644 index 0000000000000..6252fc7ad06ed --- /dev/null +++ b/arch/arm/include/stm32f2/chip.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/arm/include/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F2_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 82 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 140 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +/* STM23 F3 Family **********************************************************/ + +/* Part Numbering: STM32Fssscfxxx + * + * Where + * sss = 302/303, 334 or 372/373 + * c = C (48pins) R (68 pins) V (100 pins) + * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) + * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) + * xxx = Package, temperature range, options (ignored here) + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F2_CHIP_H */ diff --git a/arch/arm/include/stm32f2/irq.h b/arch/arm/include/stm32f2/irq.h new file mode 100644 index 0000000000000..b91d6952fa90c --- /dev/null +++ b/arch/arm/include/stm32f2/irq.h @@ -0,0 +1,168 @@ +/**************************************************************************** + * arch/arm/include/stm32f2/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F2_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F2_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 49) /* 49: SDIO global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */ +#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */ +#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */ +#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */ + +#define STM32_IRQ_NEXTINTS (81) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F2_IRQ_H */ diff --git a/arch/arm/include/stm32f3/chip.h b/arch/arm/include/stm32f3/chip.h new file mode 100644 index 0000000000000..f97f301c8f070 --- /dev/null +++ b/arch/arm/include/stm32f3/chip.h @@ -0,0 +1,627 @@ +/**************************************************************************** + * arch/arm/include/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F3_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 24 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (2) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 115 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 2 /* (2) USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ +# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 + * (2) 32-bit general timers with DMA: TIM2 and TIM5 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ +# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +/* STM23 F4 Family **********************************************************/ + +/* STM32F01xB/C Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 + * STM32F401RB LQFP64 128Kb Yes 16 + * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 + * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 + * STM32F401RC LQFP64 256Kb Yes 16 + * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define STM32_HAVE_IP_SPI_V3 + +#elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_HAVE_IP_SPI_V1 + +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_HAVE_IP_SPI_V3 + +#else +# error "Did not resolve peripheral IP versions!" +#endif + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F3_CHIP_H */ diff --git a/arch/arm/include/stm32f3/irq.h b/arch/arm/include/stm32f3/irq.h new file mode 100644 index 0000000000000..91c056320ef9b --- /dev/null +++ b/arch/arm/include/stm32f3/irq.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm/include/stm32f3/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F3_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F3_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F30XX) +# include +#elif defined(CONFIG_STM32_STM32F33XX) +# include +#elif defined(CONFIG_STM32_STM32F37XX) +# include +#else +# error "Unsupported STM32F3 chip" +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32F3_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f30xxx_irq.h b/arch/arm/include/stm32f3/stm32f30xxx_irq.h similarity index 93% rename from arch/arm/include/stm32/stm32f30xxx_irq.h rename to arch/arm/include/stm32f3/stm32f30xxx_irq.h index 32c5dc0d55767..b5a5612cfa2ae 100644 --- a/arch/arm/include/stm32/stm32f30xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f30xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f30xxx_irq.h + * arch/arm/include/stm32f3/stm32f30xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -153,31 +153,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f33xxx_irq.h b/arch/arm/include/stm32f3/stm32f33xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f33xxx_irq.h rename to arch/arm/include/stm32f3/stm32f33xxx_irq.h index bb6e9f84cc9cb..4dde150c30d89 100644 --- a/arch/arm/include/stm32/stm32f33xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f33xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f33xxx_irq.h + * arch/arm/include/stm32f3/stm32f33xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -143,31 +143,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32f3/stm32f37xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f37xxx_irq.h rename to arch/arm/include/stm32f3/stm32f37xxx_irq.h index cf052a8493a5a..445fa0c657bf4 100644 --- a/arch/arm/include/stm32/stm32f37xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f37xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f37xxx_irq.h + * arch/arm/include/stm32f3/stm32f37xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -138,31 +138,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32f4/chip.h b/arch/arm/include/stm32f4/chip.h new file mode 100644 index 0000000000000..796e1590ab464 --- /dev/null +++ b/arch/arm/include/stm32f4/chip.h @@ -0,0 +1,864 @@ +/**************************************************************************** + * arch/arm/include/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F01xD/E Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 + * STM32F401RD LQFP64 384Kb Yes 16 + * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 + * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 + * STM32F401RE LQFP64 512Kb Yes 16 + * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-4 */ +# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 81 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ +# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 113 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 168 /* GPIOA-K */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ + defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NGPIO 114 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) +# define STM32_NGPIO 131 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NGPIO 161 /* GPIOA-K */ +# endif +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# endif +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F4_CHIP_H */ diff --git a/arch/arm/include/stm32f4/irq.h b/arch/arm/include/stm32f4/irq.h new file mode 100644 index 0000000000000..eb9eb5e34385a --- /dev/null +++ b/arch/arm/include/stm32f4/irq.h @@ -0,0 +1,346 @@ +/**************************************************************************** + * arch/arm/include/stm32f4/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32F4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F4_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */ +#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */ +#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */ +#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */ +#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */ +#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */ +#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED19 (STM32_IRQ_FIRST+19) /* 19: Reserved */ +# define STM32_IRQ_RESERVED20 (STM32_IRQ_FIRST+20) /* 20: Reserved */ +# define STM32_IRQ_RESERVED21 (STM32_IRQ_FIRST+21) /* 21: Reserved */ +# define STM32_IRQ_RESERVED22 (STM32_IRQ_FIRST+22) /* 22: Reserved */ +#else +# define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */ +# define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */ +# define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */ +# define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */ +#endif + +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED28 (STM32_IRQ_FIRST+28) /* 28: Reserved */ +# define STM32_IRQ_RESERVED29 (STM32_IRQ_FIRST+29) /* 29: Reserved */ +# define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */ +#else +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */ +#endif + +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED39 (STM32_IRQ_FIRST+39) /* 39: Reserved */ +#else +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */ +#endif + +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */ +# define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */ +# define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */ +# define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */ +# define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */ +#else +# define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */ +# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */ +# define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */ +# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */ +# define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */ +# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */ +# define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */ +# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */ +#endif + +#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */ +# define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 48: Reserved */ +#else +# define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */ +# define STM32_IRQ_SDIO (STM32_IRQ_FIRST+49) /* 49: SDIO global interrupt */ +#endif + +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */ +# define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */ +# define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */ +#else +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */ +# define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */ +#endif + +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED55 (STM32_IRQ_FIRST+55) /* 55: Reserved */ +#else +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */ +#endif + +#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */ +#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */ +#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */ +#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */ +#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */ + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */ +# define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */ +#else +# define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */ +# define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */ +# define STM32_IRQ_RESERVED64 (STM32_IRQ_FIRST+64) /* 63: Reserved */ +# define STM32_IRQ_RESERVED65 (STM32_IRQ_FIRST+65) /* 63: Reserved */ +# define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 63: Reserved */ +# define STM32_IRQ_RESERVED67 (STM32_IRQ_FIRST+67) /* 63: Reserved */ +#else +# define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */ +# define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */ +# define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */ +# define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */ +# define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */ +#endif + +#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */ +#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */ +#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */ +#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */ + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED72 (STM32_IRQ_FIRST+72) /* 72: Reserved */ +# define STM32_IRQ_RESERVED73 (STM32_IRQ_FIRST+73) /* 73: Reserved */ +# define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */ +# define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */ +# define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */ +# define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */ +# define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */ +#else +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */ +# define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */ +# define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */ +# define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */ +# define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */ +# define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ +# define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */ +#else +# if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */ +# else +# define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */ +# endif +# define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +# define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */ +#endif + +#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */ + +#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 interrupt */ +# define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 interrupt */ +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED82 (STM32_IRQ_FIRST+82) /* 82: Reserved */ +# define STM32_IRQ_RESERVED83 (STM32_IRQ_FIRST+83) /* 83: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED84 (STM32_IRQ_FIRST+84) /* 84: Reserved */ +#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ +# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ +#elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ + defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 interrupt */ +# define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 interrupt */ +#elif defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_RESERVED85 (STM32_IRQ_FIRST+85) /* 85: Reserved */ +# define STM32_IRQ_RESERVED86 (STM32_IRQ_FIRST+86) /* 86: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED87 (STM32_IRQ_FIRST+87) /* 87: Reserved */ +#elif defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F446) || \ + defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F429) || defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LTDCINT interrupt */ +# define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LTDCERRINT interrupt */ +# define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D interrupt */ +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED88 (STM32_IRQ_FIRST+88) /* 88: Reserved */ +# define STM32_IRQ_RESERVED89 (STM32_IRQ_FIRST+89) /* 89: Reserved */ +# define STM32_IRQ_RESERVED90 (STM32_IRQ_FIRST+90) /* 90: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED91 (STM32_IRQ_FIRST+91) /* 91: Reserved */ +# define STM32_IRQ_RESERVED92 (STM32_IRQ_FIRST+92) /* 92: Reserved */ +#elif defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 Global interrupt */ +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI Global interrupt */ +#elif defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+91) /* 92: QuadSPI Global interrupt */ +# define STM32_IRQ_DSI (STM32_IRQ_FIRST+92) /* 91: DSI Global interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F446) +# define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+93) /* 93: HDMI-CEC Global interrupt */ +# define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+94) /* 94: SPDIF-Rx Global interrupt */ +# define STM32_IRQ_FMPI2C1 (STM32_IRQ_FIRST+95) /* 95: FMPI2C1 event interrupt */ +# define STM32_IRQ_FMPI2C1ERR (STM32_IRQ_FIRST+96) /* 96: FMPI2C1 Error event interrupt */ +#endif + +#if defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_RESERVED93 (STM32_IRQ_FIRST+93) /* 93: Reserved */ +# define STM32_IRQ_RESERVED94 (STM32_IRQ_FIRST+94) /* 94: Reserved */ +# define STM32_IRQ_RESERVED95 (STM32_IRQ_FIRST+95) /* 95: Reserved */ +# define STM32_IRQ_RESERVED96 (STM32_IRQ_FIRST+96) /* 96: Reserved */ +# define STM32_IRQ_RESERVED97 (STM32_IRQ_FIRST+97) /* 97: Reserved */ +#endif + +#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \ + defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) +# define STM32_IRQ_NEXTINTS (82) +#elif defined(CONFIG_STM32_STM32F410) +# define STM32_IRQ_NEXTINTS (98) +#elif defined(CONFIG_STM32_STM32F427) +# define STM32_IRQ_NEXTINTS (87) +#elif defined(CONFIG_STM32_STM32F429) +# define STM32_IRQ_NEXTINTS (91) +#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) +# define STM32_IRQ_NEXTINTS (97) +#elif defined(CONFIG_STM32_STM32F469) +# define STM32_IRQ_NEXTINTS (93) +#endif + +# define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32F4_IRQ_H */ diff --git a/arch/arm/include/stm32g4/chip.h b/arch/arm/include/stm32g4/chip.h new file mode 100644 index 0000000000000..f552caac654f4 --- /dev/null +++ b/arch/arm/include/stm32g4/chip.h @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/arm/include/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined (CONFIG_ARCH_CHIP_STM32G431K) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 26 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 66 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431V) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-C, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 67 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-D, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 107 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474V) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V4 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G4_CHIP_H */ diff --git a/arch/arm/include/stm32g4/irq.h b/arch/arm/include/stm32g4/irq.h new file mode 100644 index 0000000000000..ef6c1fd7fa635 --- /dev/null +++ b/arch/arm/include/stm32g4/irq.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/arm/include/stm32g4/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32G4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G4_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp interrupt (shared with STM32_IRQ_TAMPER) */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt, or */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ + +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 shared global interrupt */ +#define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High priority interrupt */ + +#define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low priority interrupt */ +#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_FIRST + 21) /* 21: FDCAN1 interrupt 0 */ +#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_FIRST + 22) /* 22: FDCAN1 interrupt 1 */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt (shared with STM32_IRQ_TIM1BRK) */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break, Transition error, Index error (shared with STM32_IRQ_TIM15) */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt (shared with STM32_IRQ_TIM1UP) */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt (shared with STM32_IRQ_TIM16) */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt (shared with STM32_IRQ_TIM1TRGCOM) */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger, Commutation, Direction Change, and Index interrupt (shared with STM32_IRQ_TIM17) */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ + +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: 42: USB wakeup from suspend through EXTI line interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break, Transition error, Index error */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger, Commutation, Direction Change, and Index interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 49) /* 49: LPTIM1 interrupt */ + +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt (shared with STM32_IRQ_DAC1, STM32_IRQ_DAC3) */ +#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC3) */ +#define STM32_IRQ_DAC3 (STM32_IRQ_FIRST + 54) /* 54: DAC3 underrun error interrupt (shared with STM32_IRQ_TIM6, STM32_IRQ_DAC1) */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt (shared with STM32_IRQ_DAC2, STM32_IRQ_DAC4) */ +#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST + 55) /* 55: DAC2 underrun error interrupt (shared with STM32_IRQ_TIM7) */ +#define STM32_IRQ_DAC4 (STM32_IRQ_FIRST + 55) /* 55: DAC4 underrun error interrupt (shared with STM32_IRQ_TIM7) */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 4 global interrupt */ + +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 5 global interrupt */ +#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 61) /* 61: ADC4 global interrupt */ +#define STM32_IRQ_ADC5 (STM32_IRQ_FIRST + 62) /* 62: ADC5 global interrupt */ +#define STM32_IRQ_UCPD (STM32_IRQ_FIRST + 63) /* 63: UCPD global interrupt */ +#define STM32_IRQ_COMP123 (STM32_IRQ_FIRST + 64) /* 64: COMP1, COMP2, and COMP3 interrupts */ +#define STM32_IRQ_COMP456 (STM32_IRQ_FIRST + 65) /* 65: COMP4, COMP5, and COMP6 interrupts */ +#define STM32_IRQ_COMP7 (STM32_IRQ_FIRST + 66) /* 66: COMPP7 interrupt */ +#define STM32_IRQ_HRTIM1MST (STM32_IRQ_FIRST + 67) /* 67: HRTIM1 master timer interrupt */ +#define STM32_IRQ_HRTIM1TIMA (STM32_IRQ_FIRST + 68) /* 68: HRTIM1 timer A interrupt */ +#define STM32_IRQ_HRTIM1TIMB (STM32_IRQ_FIRST + 69) /* 69: HRTIM1 timer B interrupt */ + +#define STM32_IRQ_HRTIM1TIMC (STM32_IRQ_FIRST + 70) /* 70: HRTIM1 timer C interrupt */ +#define STM32_IRQ_HRTIM1TIMD (STM32_IRQ_FIRST + 71) /* 71: HRTIM1 timer D interrupt */ +#define STM32_IRQ_HRTIM1TIME (STM32_IRQ_FIRST + 72) /* 72: HRTIM1 timer E interrupt */ +#define STM32_IRQ_HRTIM1FLT (STM32_IRQ_FIRST + 73) /* 73: HRTIM1 fault interrupt */ +#define STM32_IRQ_HRTIM1TIMF (STM32_IRQ_FIRST + 74) /* 74: HRTIM1 timer E interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 75) /* 75: CRS (Clock Recovery System) global interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 76) /* 76: SAI4 global interrupt */ +#define STM32_IRQ_TIM20BRK (STM32_IRQ_FIRST + 77) /* 77: TIM20 Break, Transition error, Index error interrupt */ +#define STM32_IRQ_TIM20UP (STM32_IRQ_FIRST + 78) /* 78: TIM20 Update interrupt */ +#define STM32_IRQ_TIM20TRGCOM (STM32_IRQ_FIRST + 79) /* 79: TIM20 Trigger, Commutation, Direction Change, and Index interrupt */ + +#define STM32_IRQ_TIM20CC (STM32_IRQ_FIRST + 80) /* 80: TIM20 Capture Compare interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 82) /* 82: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 83) /* 83: I2C4 error interrupt */ +#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 85) /* 85: AES global interrupt */ +#define STM32_IRQ_FDCAN2_0 (STM32_IRQ_FIRST + 86) /* 86: FDCAN2 interrupt 0 */ +#define STM32_IRQ_FDCAN2_1 (STM32_IRQ_FIRST + 87) /* 87: FDCAN2 interrupt 1 */ +#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 88) /* 88: FDCAN3 interrupt 0 */ +#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 89) /* 89: FDCAN3 interrupt 1 */ + +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 90) /* 90: RNG global interrupt */ +#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 91) /* 91: LPUART global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 92) /* 92: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 93) /* 93: I2C3 error interrupt */ +#define STM32_IRQ_DMAMUXOV (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 95) /* 95: QuadSPI global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 96) /* 96: DMA1 channel 8 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 97) /* 97: DMA2 channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 98) /* 98: DMA2 channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 99) /* 99: DMA2 channel 8 global interrupt */ + +#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */ +#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */ + +#define STM32_IRQ_NEXTINTS (102) +#define NR_IRQS (STM32_IRQ_FIRST + 102) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_STM32G4_IRQ_H */ diff --git a/arch/arm/include/stm32l1/chip.h b/arch/arm/include/stm32l1/chip.h new file mode 100644 index 0000000000000..a8b532d3673eb --- /dev/null +++ b/arch/arm/include/stm32l1/chip.h @@ -0,0 +1,491 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L151XX -- No LCD + * STM32L152XX -- With LCD + * + * STM32L15XCX -- 48-pins + * STM32L15XRX -- 64-pins + * STM32L15XVX -- 100-pins + * STM32L15XZX -- 144-pins + * + * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM + * + * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) + * + * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) + * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) + */ + +#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC , 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 21-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 109 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-G,H */ +# define STM32_NADC 1 /* ADC1, 40-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 12-channels */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-G,H */ + +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 Value Line ****************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */ diff --git a/arch/arm/include/stm32l1/irq.h b/arch/arm/include/stm32l1/irq.h new file mode 100644 index 0000000000000..cba5263dd4224 --- /dev/null +++ b/arch/arm/include/stm32l1/irq.h @@ -0,0 +1,252 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L1_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32L1_LOWDENSITY) || defined(CONFIG_STM32L1_MEDIUMDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ + +# define STM32_IRQ_NEXTINTS (45) + +#elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ +# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ +# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 45) /* 45: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 46) /* 46: SPI3 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 47) /* 47: DMA2 channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 48) /* 48: DMA2 channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 49) /* 49: DMA2 channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 5 global interrupt */ +# define STM32_IRQ_AES (STM32_IRQ_FIRST + 52) /* 52: AES global interrupt */ +# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 53) /* 53: Comparator Channel Acquisition Interrupt */ + +# define STM32_IRQ_NEXTINTS (54) + +#elif defined(CONFIG_STM32L1_HIGHDENSITY) +# define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +# define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +# define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ +# define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI line interrupt */ +# define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC Wakeup through EXTI line interrupt */ +# define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +# define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +# define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +# define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +# define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +# define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +# define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +# define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 global interrupt */ +# define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 global interrupt */ +# define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 global interrupt */ +# define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 global interrupt */ +# define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 global interrupt */ +# define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 global interrupt */ +# define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 global interrupt */ +# define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +# define STM32_IRQ_USBHP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority interrupts */ +# define STM32_IRQ_USBLP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority interrupt */ +# define STM32_IRQ_DAC (STM32_IRQ_FIRST + 21) /* 21: DAC interrupt */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: Comparator wakeup through EXTI interrupt, or */ +# define STM32_IRQ_CA (STM32_IRQ_FIRST + 22) /* 22: Channel acquisition interrupt */ +# define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +# define STM32_IRQ_LDC (STM32_IRQ_FIRST + 24) /* 24: LCD global interrupt */ +# define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 25) /* 25: TIM9 global interrupt */ +# define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 26) /* 26: TIM10 global interrupt */ +# define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 27) /* 27: TIM11 global interrupt */ +# define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +# define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +# define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +# define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +# define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +# define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +# define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +# define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +# define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +# define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +# define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +# define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +# define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +# define STM32_IRQ_USBWKUP (STM32_IRQ_FIRST + 42) /* 42: USB wakeup from suspend through EXTI line interrupt */ +# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */ +# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */ +# define STM32_IRQ_SDIO (STM32_IRQ_FIRST + 45) /* 45: SDIO Global interrupt */ +# define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 46) /* 46: TIM5 global interrupt */ +# define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 47) /* 47: SPI3 global interrupt */ +# define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 48) /* 48: UART4 global interrupt */ +# define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 49) /* 49: UART5 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 50) /* 50: DMA2 channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 51) /* 51: DMA2 channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 52) /* 52: DMA2 channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 53) /* 53: DMA2 channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 5 global interrupt */ +# define STM32_IRQ_AES (STM32_IRQ_FIRST + 55) /* 55: AES global interrupt */ +# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 56) /* 56: Comparator Channel Acquisition Interrupt */ + +# define STM32_IRQ_NEXTINTS (57) +#else +# error "Unknown STM32L density" +#endif + +# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_IRQ_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index e129ee671cec7..f1c195a43cd0c 100644 --- a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1093,7 +1093,7 @@ int stm32_dma2dinitialize(void) stm32_dma2duninitialize(); /* Enable dma2d is done in rcc_enableahb1, see - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32_rcc.c */ #ifdef CONFIG_STM32_FB_CMAP diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index 6fb57a23624b0..756c7031663f7 100644 --- a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -20,7 +20,7 @@ * ****************************************************************************/ -/* Ported from arch/arm/src/stm32/stm32_dma_v1mux.c */ +/* Ported from arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c */ /**************************************************************************** * Included Files diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index c9695564c9379..8c72dd6b209ac 100644 --- a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -47,7 +47,7 @@ #include "stm32_gpio.h" #include "stm32_rcc.h" -/* Ported from arch/arm/src/stm32/stm32_fdcan.c */ +/* Ported from arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt deleted file mode 100644 index f36e41d25df01..0000000000000 --- a/arch/arm/src/stm32/CMakeLists.txt +++ /dev/null @@ -1,57 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_allocateheap.c - stm32_start.c - stm32_rcc.c - stm32_lse.c - stm32_lsi.c - stm32_irq.c - stm32_lowputc.c) - -if(CONFIG_STM32_TICKLESS_TIMER) - list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -list(APPEND SRCS stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c) - -if(NOT CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pminitialize.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig deleted file mode 100644 index f8c9957e95433..0000000000000 --- a/arch/arm/src/stm32/Kconfig +++ /dev/null @@ -1,2101 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32 Configuration Options" - -config STM32_COMMON_PERIPHERALS - bool - default y - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - select STM32_HAVE_DMA2D if STM32_STM32F429 - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_I2C1 - select STM32_HAVE_LCD if STM32_STM32L15XX - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX - select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX - select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - -choice - prompt "STM32 Chip Selection" - default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - -config ARCH_CHIP_STM32L151C6 - bool "STM32L151C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151C8 - bool "STM32L151C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151CB - bool "STM32L151CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R6 - bool "STM32L151R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R8 - bool "STM32L151R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151RB - bool "STM32L151RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V6 - bool "STM32L151V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V8 - bool "STM32L151V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151VB - bool "STM32L151VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L152C6 - bool "STM32L152C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152C8 - bool "STM32L152C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152CB - bool "STM32L152CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152R6 - bool "STM32L152R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152R8 - bool "STM32L152R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152RB - bool "STM32L152RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152V6 - bool "STM32L152V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152V8 - bool "STM32L152V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152VB - bool "STM32L152VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152CC - bool "STM32L152CC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152RC - bool "STM32L152RC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152VC - bool "STM32L152VC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L151RE - bool "STM32L151RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152RE - bool "STM32L152RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151VE - bool "STM32L151VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152VE - bool "STM32L152VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151QE - bool "STM32L151QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152QE - bool "STM32L152QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151ZE - bool "STM32L151ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152ZE - bool "STM32L152ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L162ZD - bool "STM32L162ZD" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L162VE - bool "STM32L162VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32F100C8 - bool "STM32F100C8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100CB - bool "STM32F100CB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100R8 - bool "STM32F100R8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RB - bool "STM32F100RB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RC - bool "STM32F100RC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RD - bool "STM32F100RD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RE - bool "STM32F100RE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100V8 - bool "STM32F100V8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VB - bool "STM32F100VB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VC - bool "STM32F100VC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VD - bool "STM32F100VD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VE - bool "STM32F100VE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F102CB - bool "STM32F102CB" - select STM32_STM32F10XX - select STM32_USBACCESSLINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103T8 - bool "STM32F103T8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103TB - bool "STM32F103TB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103C4 - bool "STM32F103C4" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_LOWDENSITY - -config ARCH_CHIP_STM32F103C8 - bool "STM32F103C8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103CB - bool "STM32F103CB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103R8 - bool "STM32F103R8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RB - bool "STM32F103RB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RC - bool "STM32F103RC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RD - bool "STM32F103RD" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RE - bool "STM32F103RE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RG - bool "STM32F103RG" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103V8 - bool "STM32F103V8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VB - bool "STM32F103VB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VC - bool "STM32F103VC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VE - bool "STM32F103VE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103ZE - bool "STM32F103ZE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105VB - bool "STM32F105VBT7" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105RB - bool "STM32F105RB" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F107VC - bool "STM32F107VC" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F205RG - bool "STM32F205RG" - select STM32_STM32F20XX - select STM32_STM32F205 - -config ARCH_CHIP_STM32F207VC - bool "STM32F207VC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VE - bool "STM32F207VE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VF - bool "STM32F207VF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VG - bool "STM32F207VG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IC - bool "STM32F207IC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IE - bool "STM32F207IE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IF - bool "STM32F207IF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IG - bool "STM32F207IG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZC - bool "STM32F207ZC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZE - bool "STM32F207ZE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZF - bool "STM32F207ZF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZG - bool "STM32F207ZG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F302K6 - bool "STM32F302K6" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302K8 - bool "STM32F302K8" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302C6 - bool "STM32F302C6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302C8 - bool "STM32F302C8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R6 - bool "STM32F302R6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R8 - bool "STM32F302R8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302CB - bool "STM32F302CB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302CC - bool "STM32F302CC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302RB - bool "STM32F302RB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302RC - bool "STM32F302RC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VB - bool "STM32F302VB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VC - bool "STM32F302VC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F303K6 - bool "STM32F303K6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303K8 - bool "STM32F303K8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303C6 - bool "STM32F303C6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303C8 - bool "STM32F303C8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303CB - bool "STM32F303CB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303CC - bool "STM32F303CC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RB - bool "STM32F303RB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RC - bool "STM32F303RC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RD - bool "STM32F303RD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RE - bool "STM32F303RE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VB - bool "STM32F303VB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VC - bool "STM32F303VC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VD - bool "STM32F303VD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303VE - bool "STM32F303VE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZD - bool "STM32F303ZD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZE - bool "STM32F303ZE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F334K4 - bool "STM32F334K4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K6 - bool "STM32F334K6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K8 - bool "STM32F334K8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C4 - bool "STM32F334C4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C6 - bool "STM32F334C6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C8 - bool "STM32F334C8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R4 - bool "STM32F334R4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R6 - bool "STM32F334R6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R8 - bool "STM32F334R8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F372C8 - bool "STM32F372C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372R8 - bool "STM32F372R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372V8 - bool "STM32F372V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CB - bool "STM32F372CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RB - bool "STM32F372RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VB - bool "STM32F372VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CC - bool "STM32F372CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RC - bool "STM32F372RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VC - bool "STM32F372VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373C8 - bool "STM32F373C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373R8 - bool "STM32F373R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373V8 - bool "STM32F373V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CB - bool "STM32F373CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RB - bool "STM32F373RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VB - bool "STM32F373VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CC - bool "STM32F373CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RC - bool "STM32F373RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VC - bool "STM32F373VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F401CB - bool "STM32F401CB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RB - bool "STM32F401RB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VB - bool "STM32F401VB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CC - bool "STM32F401CC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RC - bool "STM32F401RC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VC - bool "STM32F401VC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CD - bool "STM32F401CD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RD - bool "STM32F401RD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VD - bool "STM32F401VD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401CE - bool "STM32F401CE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RE - bool "STM32F401RE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VE - bool "STM32F401VE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F410RB - bool "STM32F410RB" - select STM32_STM32F4XXX - select STM32_STM32F410 - -config ARCH_CHIP_STM32F411CE - bool "STM32F411CE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411RE - bool "STM32F411RE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411VE - bool "STM32F411VE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F412CE - bool "STM32F412CE" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F412ZG - bool "STM32F412ZG" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F405RG - bool "STM32F405RG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405VG - bool "STM32F405VG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405ZG - bool "STM32F405ZG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F407VE - bool "STM32F407VE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407VG - bool "STM32F407VG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZE - bool "STM32F407ZE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZG - bool "STM32F407ZG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IE - bool "STM32F407IE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IG - bool "STM32F407IG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F427V - bool "STM32F427V" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427Z - bool "STM32F427Z" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427I - bool "STM32F427I" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F429V - bool "STM32F429V" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429Z - bool "STM32F429Z" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429I - bool "STM32F429I" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429B - bool "STM32F429B" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429N - bool "STM32F429N" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F446M - bool "STM32F446M" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446R - bool "STM32F446R" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446V - bool "STM32F446V" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446Z - bool "STM32F446Z" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F469A - bool "STM32F469A" - select STM32_STM32F4XXX - select STM32_STM32F469 - -config ARCH_CHIP_STM32F469I - bool "STM32F469I" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469B - bool "STM32F469B" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469N - bool "STM32F469N" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32G431K - bool "STM32G431K" - select STM32_STM32G43XX - select STM32_STM32G4XXK - select STM32_STM32G431K - -config ARCH_CHIP_STM32G431C - bool "STM32G431C" - select STM32_STM32G43XX - select STM32_STM32G4XXC - select STM32_STM32G431C - -config ARCH_CHIP_STM32G431R - bool "STM32G431R" - select STM32_STM32G43XX - select STM32_STM32G4XXR - select STM32_STM32G431R - -config ARCH_CHIP_STM32G431M - bool "STM32G431M" - select STM32_STM32G43XX - select STM32_STM32G4XXM - select STM32_STM32G431M - -config ARCH_CHIP_STM32G431V - bool "STM32G431V" - select STM32_STM32G43XX - select STM32_STM32G4XXV - select STM32_STM32G431V - -config ARCH_CHIP_STM32G474C - bool "STM32G474C" - select STM32_STM32G47XX - select STM32_STM32G4XXC - select STM32_STM32G474C - -config ARCH_CHIP_STM32G474M - bool "STM32G474M" - select STM32_STM32G47XX - select STM32_STM32G4XXM - select STM32_STM32G474M - -config ARCH_CHIP_STM32G474R - bool "STM32G474R" - select STM32_STM32G47XX - select STM32_STM32G4XXR - select STM32_STM32G474R - select STM32_HAVE_USBFS - -config ARCH_CHIP_STM32G474Q - bool "STM32G474Q" - select STM32_STM32G47XX - select STM32_STM32G4XXQ - select STM32_STM32G474Q - -config ARCH_CHIP_STM32G474V - bool "STM32G474V" - select STM32_STM32G47XX - select STM32_STM32G4XXV - select STM32_STM32G474V - -endchoice - -config STM32_FLASH_CONFIG_DEFAULT - bool - -config STM32_FLASH_CONFIG_Z - bool - -config STM32_STM32L15XX - bool - default n - select ARCH_CORTEXM3 - select STM32_ENERGYLITE - select STM32_HAVE_USBDEV - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 - -config STM32_STM32F10XX - bool - default n - select ARCH_CORTEXM3 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_RTC_COUNTER - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_V1 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 - -config STM32_CONNECTIVITYLINE - bool - default n - select STM32_HAVE_OTGFS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - -config STM32_PERFORMANCELINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - -config STM32_USBACCESSLINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_SPI2 - -config STM32_MEDIUMPLUSDENSITY - bool - default n - -config STM32_HIGHDENSITY - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_MEDIUMDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_LOWDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 if !STM32_VALUELINE - -config STM32_STM32F20XX - bool - default n - select ARCH_CORTEXM3 - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_OTGFS - select STM32_HAVE_OTGHS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 - -config STM32_STM32F205 - bool - default n - -config STM32_STM32F207 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_ETHMAC - -config STM32_STM32F30XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F302 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_USBDEV - -config STM32_STM32F303 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_CCM - select STM32_HAVE_TIM7 - -config STM32_STM32F33XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_HRTIM1 - select STM32_HAVE_HRTIM1_PLLCLK - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP6 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_ADC2_DMA - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F37XX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_USBDEV - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - -config STM32_STM32F4XXX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 - -config STM32_STM32F401xBC - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401xDE - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401 - bool - default n - select ARCH_CORTEXM4 - select STM32_STM32F4XXX - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F410 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI5 - select STM32_HAVE_DAC1 - -config STM32_STM32F411 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F412 - bool - default n - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_USART3 - select STM32_HAVE_USART2 - select STM32_HAVE_USART6 - select STM32_HAVE_I2C1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI1 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_OTGFS - select STM32_HAVE_I2SPLL - -config STM32_STM32F405 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_OTGFS - -config STM32_STM32F407 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_OTGFS - -# This is really 427/437, but we treat the two the same. - -config STM32_STM32F427 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SPI6 - select STM32_HAVE_I2SPLL - -# This is really 429/439, but we treat the two the same. - -config STM32_STM32F429 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F446 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - -# This is really 469/479, but we treat the two the same. - -config STM32_STM32F469 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - -config STM32_STM32G4XXX - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_V3 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V2 - select STM32_HAVE_IP_DAC_V2 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - select STM32_HAVE_IP_TIMERS_V3 - -config STM32_STM32G4_CAT2 - bool - default n - -config STM32_STM32G4_CAT3 - bool - default n - -config STM32_STM32G4_CAT4 - bool - default n - -config STM32_STM32G4XXK - bool - default n - -config STM32_STM32G4XXC - bool - default n - -config STM32_STM32G4XXR - bool - default n - -config STM32_STM32G4XXM - bool - default n - -config STM32_STM32G4XXV - bool - default n - -config STM32_STM32G4XXP - bool - default n - -config STM32_STM32G4XXQ - bool - default n - -config STM32_STM32G43XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT2 - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC3 - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G431K - bool - default n - -config STM32_STM32G431C - bool - default n - select STM32_HAVE_USART3 - -config STM32_STM32G431R - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431M - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431V - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G47XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT3 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_ADC5 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP5 - select STM32_HAVE_COMP6 - select STM32_HAVE_COMP7 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_DAC3 - select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1_CHAN8 - select STM32_HAVE_DMA2_CHAN678 - select STM32_HAVE_FSMC - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_HRTIM1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_I2C4 - select STM32_HAVE_I2S3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_OPAMP4 - select STM32_HAVE_OPAMP5 - select STM32_HAVE_OPAMP6 - select STM32_HAVE_QSPI - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM20 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G474C - bool - default n - select STM32_HAVE_FDCAN3 - -config STM32_STM32G474M - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474R - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474Q - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474V - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs deleted file mode 100644 index a7cf6decf4ba2..0000000000000 --- a/arch/arm/src/stm32/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# arch/arm/src/stm32/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include armv7-m/Make.defs - -CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c - -ifdef CONFIG_STM32_TICKLESS_TIMER -CHIP_CSRCS += stm32_tickless.c -else -CHIP_CSRCS += stm32_timerisr.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -CHIP_CSRCS += stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c - -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += stm32_pminitialize.c -endif - -include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h deleted file mode 100644 index 295751fca513a..0000000000000 --- a/arch/arm/src/stm32/chip.h +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_CHIP_H -#define __ARCH_ARM_SRC_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Include the chip capabilities file */ - -#include - -/* Include the chip interrupt definition file */ - -#include - -/* Include the chip memory map */ - -#include "hardware/stm32_memorymap.h" - -/* Include the chip pinmap */ - -#include "hardware/stm32_pinmap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Provide the required number of peripheral interrupt vector - * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes - * from the chip-specific * IRQ header file included by arch/stm32/irq.h. - */ - -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS - -#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h deleted file mode 100644 index d1ba76649c384..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ /dev/null @@ -1,640 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This is implementation for STM32 ADC IPv1 - F1, F2, F37x, F4, F7. - * NOTE: L1 use modified IPv1 (look at chip/stm32_adc_v1l1.h). - */ - -#define HAVE_IP_ADC_V1 -#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ -#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ -#undef HAVE_ADC_POWERDOWN /* No ADC power down */ - -/* F1 and F37x have basic version of ADC hardware - * - no common ADC registers - * - ADCs are not coupled in single ADC block (no common ADC base address) - * - no configurable resolution - * - no overrun - * - ... - */ - -#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) -# define HAVE_BASIC_ADC -#else -# undef HAVE_BASIC_ADC -#endif - -/* VBAT channel support only if no basic ADC */ - -#ifndef HAVE_BASIC_ADC -# define HAVE_ADC_VBAT -#else -# undef HAVE_ADC_VBAT -#endif - -/* Base addresses ***********************************************************/ - -/* For the basic ADC IPv1, - * the ADCx_BASE definitions are defined in chip/stm32xxx_memorymap.h files - */ - -#ifndef HAVE_BASIC_ADC -# define STM32_ADC1_OFFSET 0x0000 -# define STM32_ADC2_OFFSET 0x0100 -# define STM32_ADC3_OFFSET 0x0200 -# define STM32_ADC_CMN_OFFSET 0x0300 - -# define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC_BASE) /* ADC1 ADC */ -# define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC_BASE) /* ADC2 ADC */ -# define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC_BASE) /* ADC3 ADC */ - -# define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET + STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ -#endif - -/* Register Offsets *********************************************************/ - -#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ -#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ -#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ -#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ -#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ -#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */ -#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */ -#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */ -#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */ -#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */ -#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */ -#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */ -#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */ -#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */ -#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */ -#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */ - -#ifndef HAVE_BASIC_ADC -# define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -# define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ -# define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */ -#endif - -/* Register Addresses *******************************************************/ - -#if STM32_NADC > 0 -# define STM32_ADC1_SR (STM32_ADC1_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC1_CR1 (STM32_ADC1_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC1_CR2 (STM32_ADC1_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC1_HTR (STM32_ADC1_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC1_LTR (STM32_ADC1_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -#endif - -#if STM32_NADC > 1 -# define STM32_ADC2_SR (STM32_ADC2_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC2_CR1 (STM32_ADC2_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC2_CR2 (STM32_ADC2_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC2_HTR (STM32_ADC2_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC2_LTR (STM32_ADC2_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC3_SR (STM32_ADC3_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC3_CR1 (STM32_ADC3_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC3_CR2 (STM32_ADC3_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC3_HTR (STM32_ADC3_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC3_LTR (STM32_ADC3_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) -#endif - -#ifndef HAVE_BASIC_ADC -# define STM32_ADC_CSR (STM32_ADCCMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC_CCR (STM32_ADCCMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC_CDR (STM32_ADCCMN_BASE + STM32_ADC_CDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* ADC status register */ - -#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ -#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ -#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ -#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ -#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ -#ifndef HAVE_BASIC_ADC -# define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ -#endif - -/* ADC control register 1 */ - -#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ -#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) - -#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ -#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ -#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ -#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ -#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ -#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) - -#ifdef HAVE_BASIC_ADC -# define ADC_CR1_DUALMOD_SHIFT (16) /* Bits 19-16: Dual mode selection */ -# define ADC_CR1_DUALMOD_MASK (0x0f << ADC_CR1_DUALMOD_SHIFT) -# define ADC_CR1_IND (0 << ADC_CR1_DUALMOD_SHIFT) /* 0000: Independent mode */ -# define ADC_CR1_RSIS (1 << ADC_CR1_DUALMOD_SHIFT) /* 0001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CR1_RSAT (2 << ADC_CR1_DUALMOD_SHIFT) /* 0010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CR1_ISFI (3 << ADC_CR1_DUALMOD_SHIFT) /* 0011: Combined injected simultaneous + fast interleaved mode */ -# define ADC_CR1_ISFL (4 << ADC_CR1_DUALMOD_SHIFT) /* 0100: Combined injected simultaneous + slow Interleaved mode */ -# define ADC_CR1_IS (5 << ADC_CR1_DUALMOD_SHIFT) /* 0101: Injected simultaneous mode only */ -# define ADC_CR1_RS (6 << ADC_CR1_DUALMOD_SHIFT) /* 0110: Regular simultaneous mode only */ -# define ADC_CR1_FI (7 << ADC_CR1_DUALMOD_SHIFT) /* 0111: Fast interleaved mode only */ -# define ADC_CR1_SI (8 << ADC_CR1_DUALMOD_SHIFT) /* 1000: Slow interleaved mode only */ -# define ADC_CR1_AT (9 << ADC_CR1_DUALMOD_SHIFT) /* 1001: Alternate trigger mode only */ -#endif - -#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ - -#ifndef HAVE_BASIC_ADC -# define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ -# define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) -# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles */ -# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles */ -# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ -# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ - -# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ -# define ADC_CR1_RESERVED (0xfb3f0000) -#endif - -/* ADC control register 2 */ - -#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ -#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ -#ifdef HAVE_BASIC_ADC -# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */ -# define ADC_CR2_RSTCAL (1 << 3) /* Bit 3: Reset Calibration */ -#endif -#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ -#ifndef HAVE_BASIC_ADC -# define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ -# define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ -#endif - -#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ - -#ifndef HAVE_BASIC_ADC - /* Bits 12-15: Reserved */ -# define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ -# define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T1CC4 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 CC4 event */ -# define ADC_CR2_JEXTSEL_T1TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 TRGO event */ -# define ADC_CR2_JEXTSEL_T3CC2 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC2 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_T5CC4 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 5 CC4 event */ -# define ADC_CR2_JEXTSEL_T5TRGO (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 5 TRGO event */ -# define ADC_CR2_JEXTSEL_T8CC2 (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 8 CC2 event */ -# define ADC_CR2_JEXTSEL_T8CC3 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 8 CC3 event */ -# define ADC_CR2_JEXTSEL_T8CC4 (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 8 CC4 event */ -# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ - -# define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ -# define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) -# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -# define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ - /* Bit 23: Reserved, must be kept at reset value. */ -# define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ -# define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */ -# define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */ -# define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 2 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 2 CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_T5CC1 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 5 CC1 event */ -# define ADC_CR2_EXTSEL_T5CC2 (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 5 CC2 event */ -# define ADC_CR2_EXTSEL_T5CC3 (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 5 CC3 event */ -# define ADC_CR2_EXTSEL_T8CC1 (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 8 CC1 event */ -# define ADC_CR2_EXTSEL_T8TRGO (0x0E << ADC_CR2_EXTSEL_SHIFT) /* 1110: Timer 8 TRGO event */ -# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ - -# define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ -# define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) -# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ -# define ADC_CR2_RESERVED (0x8080f0fc) -#else /* HAVE_BASIC_ADC */ -# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */ -# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT) -# if defined(CONFIG_STM32_STM32F37XX) -# define ADC_CR2_JEXTSEL_T19CC1 (0 << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T19CC2 (1 << ADC_CR2_JEXTSEL_SHIFT) -# else -# define ADC_CR2_JEXTSEL_T1TRGO (0 << ADC_CR2_JEXTSEL_SHIFT) /* 000: Timer 1 TRGO event */ -# define ADC_CR2_JEXTSEL_T1CC4 (1 << ADC_CR2_JEXTSEL_SHIFT) /* 001: Timer 1 CC4 event */ -# endif -# define ADC_CR2_JEXTSEL_T2TRGO (2 << ADC_CR2_JEXTSEL_SHIFT) /* 010: Timer 2 TRGO event */ -# define ADC_CR2_JEXTSEL_T2CC1 (3 << ADC_CR2_JEXTSEL_SHIFT) /* 011: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (4 << ADC_CR2_JEXTSEL_SHIFT) /* 100: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (5 << ADC_CR2_JEXTSEL_SHIFT) /* 101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (6 << ADC_CR2_JEXTSEL_SHIFT) /* 110: EXTI line 15 */ -# define ADC_CR2_JEXTSEL_JSWSTART (7 << ADC_CR2_JEXTSEL_SHIFT) /* 111: JSWSTART */ - -# define ADC_CR2_JEXTTRIG (1 << 15) /* Bit 15: External Trigger Conversion mode for injected channels */ -# define ADC_CR2_EXTSEL_SHIFT (17) /* Bits 19-17: External Event Select for regular group */ -# define ADC_CR2_EXTSEL_MASK (7 << ADC_CR2_EXTSEL_SHIFT) -# if defined(CONFIG_STM32_STM32F37XX) -# define ADC_CR2_EXTSEL_T19TRGO (0 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T19CC3 (1 << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T19CC4 (2 << ADC_CR2_EXTSEL_SHIFT) -# else -# define ADC_CR2_EXTSEL_T1CC1 (0 << ADC_CR2_EXTSEL_SHIFT) /* 000: Timer 1 CC1 event */ -# define ADC_CR2_EXTSEL_T1CC2 (1 << ADC_CR2_EXTSEL_SHIFT) /* 001: Timer 1 CC2 event */ -# define ADC_CR2_EXTSEL_T1CC3 (2 << ADC_CR2_EXTSEL_SHIFT) /* 010: Timer 1 CC3 event */ -# endif -# define ADC_CR2_EXTSEL_T2CC2 (3 << ADC_CR2_EXTSEL_SHIFT) /* 011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T3TRGO (4 << ADC_CR2_EXTSEL_SHIFT) /* 100: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (5 << ADC_CR2_EXTSEL_SHIFT) /* 101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_EXTI11 (6 << ADC_CR2_EXTSEL_SHIFT) /* 110: EXTI line 11 */ -# define ADC_CR2_EXTSEL_SWSTART (7 << ADC_CR2_EXTSEL_SHIFT) /* 111: SWSTART */ - -# define ADC_CR2_EXTTRIG (1 << 20) /* Bit 20: External Trigger Conversion mode for regular channels */ -# define ADC_CR2_JSWSTART (1 << 21) /* Bit 21: Start Conversion of injected channels */ -# define ADC_CR2_SWSTART (1 << 22) /* Bit 22: Start Conversion of regular channels */ -# define ADC_CR2_TSVREFE (1 << 23) /* Bit 23: Temperature Sensor and VREFINT Enable */ -#endif - -/* ADC sample time register 1 */ - -#ifndef HAVE_BASIC_ADC -# define ADC_SMPR_3 0 /* 000: 3 cycles */ -# define ADC_SMPR_15 1 /* 001: 15 cycles */ -# define ADC_SMPR_28 2 /* 010: 28 cycles */ -# define ADC_SMPR_56 3 /* 011: 56 cycles */ -# define ADC_SMPR_84 4 /* 100: 84 cycles */ -# define ADC_SMPR_112 5 /* 101: 112 cycles */ -# define ADC_SMPR_144 6 /* 110: 144 cycles */ -# define ADC_SMPR_480 7 /* 111: 480 cycles */ -#else -# define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -# define ADC_SMPR_7p5 1 /* 001: 7.5 cycles */ -# define ADC_SMPR_13p5 2 /* 010: 13.5 cycles */ -# define ADC_SMPR_28p5 3 /* 011: 28.5 cycles */ -# define ADC_SMPR_41p5 4 /* 100: 41.5 cycles */ -# define ADC_SMPR_55p5 5 /* 101: 55.5 cycles */ -# define ADC_SMPR_71p5 6 /* 110: 71.5 cycles */ -# define ADC_SMPR_239p5 7 /* 111: 239.5 cycles */ -#endif - -#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT) -#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT) -#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT) -#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT) -#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT) -#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT) -#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT) -#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT) -#ifndef HAVE_BASIC_ADC -# define ADC_SMPR1_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -# define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP18_SHIFT) -#endif - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT) -#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT) -#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT) -#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT) -#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT) -#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT) -#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT) -#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT) -#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT) -#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT) - -/* ADC injected channel data offset register 1-4 */ - -#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ -#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) - -/* ADC watchdog high threshold register */ - -#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ -#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) - -/* ADC watchdog low threshold register */ - -#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ -#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT) -#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ -#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT) -#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ -#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT) -#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ -#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT) -#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_RESERVED (0xff000000) -#define ADC_SQR1_FIRST (13) -#define ADC_SQR1_LAST (16) -#define ADC_SQR1_SQ_OFFSET (0) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ -#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT) -#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ -#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT ) -#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ -#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT) -#define ADC_SQR2_RESERVED (0xc0000000) -#define ADC_SQR2_FIRST (7) -#define ADC_SQR2_LAST (12) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ -#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT) -#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ -#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT) -#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ -#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT) -#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ -#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT) -#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ -#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT ) -#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ -#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT) -#define ADC_SQR3_RESERVED (0xc0000000) -#define ADC_SQR3_FIRST (1) -#define ADC_SQR3_LAST (6) -#define ADC_SQR3_SQ_OFFSET (0) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (5) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -#define ADC_JSQR_JSQ_SHIFT (5) /* Shift between JSQx bits */ -#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ - -/* ADC injected data register 1-4 */ - -#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) -#ifdef HAVE_BASIC_ADC -# define ADC_DR_ADC2DATA_SHIFT (16) /* Bits 31-16: ADC2 data */ -# define ADC_DR_ADC2DATA_MASK (0xffff << ADC_DR_ADC2DATA_SHIFT) -#endif - -/* Common status register */ - -#ifndef HAVE_BASIC_ADC -# define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ -# define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ -# define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ -# define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ -# define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ -# define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ - /* Bits 6-7: Reserved, must be kept at reset value. */ - -# define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */ -# define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */ -# define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */ -# define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */ -# define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */ -# define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */ - /* Bits 14-15: Reserved, must be kept at reset value. */ -# define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */ -# define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */ -# define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */ -# define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */ -# define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */ -# define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */ - /* Bits 22-31: Reserved, must be kept at reset value. */ -#endif - -/* Common control register */ - -#ifndef HAVE_BASIC_ADC -# define ADC_CCR_MULTI_SHIFT (0) /* Bits 0-4: Multi ADC mode selection */ -# define ADC_CCR_MULTI_MASK (31 << ADC_CCR_MULTI_SHIFT) -# define ADC_CCR_MULTI_NONE (0 << ADC_CCR_MULTI_SHIFT) /* 00000: Independent mode */ - /* 00001 to 01001: Dual mode (ADC1 and ADC2), ADC3 independent */ -# define ADC_CCR_MULTI_RSISM2 (1 << ADC_CCR_MULTI_SHIFT) /* 00001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM2 (2 << ADC_CCR_MULTI_SHIFT) /* 00010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM2 (5 << ADC_CCR_MULTI_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM2 (6 << ADC_CCR_MULTI_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM2 (7 << ADC_CCR_MULTI_SHIFT) /* 00111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM2 (9 << ADC_CCR_MULTI_SHIFT) /* 01001: Alternate trigger mode only */ - /* 10001 to 11001: Triple mode (ADC1, 2 and 3) */ -# define ADC_CCR_MULTI_RSISM3 (17 << ADC_CCR_MULTI_SHIFT) /* 10001: Combined regular simultaneous + injected simultaneous mode */ -# define ADC_CCR_MULTI_RSATM3 (18 << ADC_CCR_MULTI_SHIFT) /* 10010: Combined regular simultaneous + alternate trigger mode */ -# define ADC_CCR_MULTI_ISM3 (21 << ADC_CCR_MULTI_SHIFT) /* 10101: Injected simultaneous mode only */ -# define ADC_CCR_MULTI_RSM3 (22 << ADC_CCR_MULTI_SHIFT) /* 10110: Regular simultaneous mode only */ -# define ADC_CCR_MULTI_IM3 (23 << ADC_CCR_MULTI_SHIFT) /* 10111: interleaved mode only */ -# define ADC_CCR_MULTI_ATM3 (25 << ADC_CCR_MULTI_SHIFT) /* 11001: Alternate trigger mode only */ - -/* Bits 5-7: Reserved, - * must be kept at reset value. - */ - -# define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -# define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n)-5) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, n=5-20 */ - -/* Bit 12 Reserved, - * must be kept at reset value. - */ - -# define ADC_CCR_DDS (1 << 13) /* Bit 13: DMA disable selection (for multi-ADC mode) */ - -# define ADC_CCR_DMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for multi ADC mode */ -# define ADC_CCR_DMA_MASK (3 << ADC_CCR_DMA_SHIFT) -# define ADC_CCR_DMA_DISABLED (0 << ADC_CCR_DMA_SHIFT) /* 00: DMA mode disabled */ -# define ADC_CCR_DMA_MODE1 (1 << ADC_CCR_DMA_SHIFT) /* 01: DMA mode 1 enabled */ -# define ADC_CCR_DMA_MODE2 (2 << ADC_CCR_DMA_SHIFT) /* 10: DMA mode 2 enabled */ -# define ADC_CCR_DMA_MODE3 (3 << ADC_CCR_DMA_SHIFT) /* 11: DMA mode 3 enabled */ - -# define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ -# define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) -# define ADC_CCR_ADCPRE_DIV2 (0 << ADC_CCR_ADCPRE_SHIFT) /* 00: PCLK2 divided by 2 */ -# define ADC_CCR_ADCPRE_DIV4 (1 << ADC_CCR_ADCPRE_SHIFT) /* 01: PCLK2 divided by 4 */ -# define ADC_CCR_ADCPRE_DIV6 (2 << ADC_CCR_ADCPRE_SHIFT) /* 10: PCLK2 divided by 6 */ -# define ADC_CCR_ADCPRE_DIV8 (3 << ADC_CCR_ADCPRE_SHIFT) /* 11: PCLK2 divided by 8 */ - -/* Bits 18-21: Reserved, - * must be kept at reset value. - */ -# define ADC_CCR_VBATEN (1 << 22) /* Bit 22: VBAT enable */ -# define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ - /* Bits 24-31 Reserved, must be kept at reset value. */ -#endif - -/* Data register for dual and triple modes - * (32-bit data with no named fields) - */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h deleted file mode 100644 index 68b5beacd860d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h +++ /dev/null @@ -1,571 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1l1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This is implementation for STM32 ADC IPv1 modified for L1 */ - -#define HAVE_IP_ADC_V1 -#undef HAVE_IP_ADC_V2 /* No ADC IPv2 */ -#undef HAVE_BASIC_ADC /* No basic ADC */ -#undef HAVE_ADC_VBAT /* No VBAT channel */ - -/* Some families use HSI as clock-source for the ADC (L0, L1). - * NOTE: F0 use dedicated HSI14 clock which does not belong here. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# define HAVE_ADC_CLOCK_HSI -#endif - -/* Power down functions for ADC (L1) */ - -#ifdef CONFIG_STM32_STM32L15XX -# define HAVE_ADC_POWERDOWN -#endif - -/* Base addresses ***********************************************************/ - -#define STM32_ADC1_OFFSET 0x0000 -#define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC3_OFFSET 0x0200 -#define STM32_ADC_CMN_OFFSET 0x0300 - -#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC_BASE) /* ADC1 ADC */ -#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC_BASE) /* ADC2 ADC */ -#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC_BASE) /* ADC3 ADC */ - -#define STM32_ADCCMN_BASE (STM32_ADC_CMN_OFFSET + STM32_ADC_BASE) /* ADC1, ADC2, ADC3 common */ - -/* Register Offsets *********************************************************/ - -#define STM32_ADC_SR_OFFSET 0x0000 /* ADC status register (32-bit) */ -#define STM32_ADC_CR1_OFFSET 0x0004 /* ADC control register 1 (32-bit) */ -#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */ -#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */ -#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */ -#define STM32_ADC_SMPR3_OFFSET 0x0014 /* ADC sample time register 3 (32-bit) */ -#define STM32_ADC_JOFR1_OFFSET 0x0018 /* ADC injected channel data offset register 1 (32-bit) */ -#define STM32_ADC_JOFR2_OFFSET 0x001c /* ADC injected channel data offset register 2 (32-bit) */ -#define STM32_ADC_JOFR3_OFFSET 0x0020 /* ADC injected channel data offset register 3 (32-bit) */ -#define STM32_ADC_JOFR4_OFFSET 0x0024 /* ADC injected channel data offset register 4 (32-bit) */ -#define STM32_ADC_HTR_OFFSET 0x0028 /* ADC watchdog high threshold register (32-bit) */ -#define STM32_ADC_LTR_OFFSET 0x002c /* ADC watchdog low threshold register (32-bit) */ -#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 (32-bit) */ -#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 (32-bit) */ -#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 (32-bit) */ -#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 (32-bit) */ -#define STM32_ADC_SQR5_OFFSET 0x0040 /* ADC regular sequence register 5 (32-bit) */ -#define STM32_ADC_JSQR_OFFSET 0x0044 /* ADC injected sequence register (32-bit) */ -#define STM32_ADC_JDR1_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR2_OFFSET 0x004c /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR3_OFFSET 0x0050 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_JDR4_OFFSET 0x0054 /* ADC injected data register 1 (32-bit) */ -#define STM32_ADC_DR_OFFSET 0x0058 /* ADC regular data register (32-bit) */ -#define STM32_ADC_SMPR0_OFFSET 0X005c /* ADC sample time register 3 (32-bit) */ - -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NADC > 0 -# define STM32_ADC1_SR (STM32_ADC1_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC1_CR1 (STM32_ADC1_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC1_CR2 (STM32_ADC1_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_SMPR3 (STM32_ADC1_BASE + STM32_ADC_SMPR3_OFFSET) -# define STM32_ADC1_JOFR1 (STM32_ADC1_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC1_JOFR2 (STM32_ADC1_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC1_JOFR3 (STM32_ADC1_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC1_JOFR4 (STM32_ADC1_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC1_HTR (STM32_ADC1_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC1_LTR (STM32_ADC1_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC1_SQR5 (STM32_ADC1_BASE + STM32_ADC_SQR5_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC1_SMPR0 (STM32_ADC1_BASE + STM32_ADC_SMPR0_OFFSET) -#endif - -#if STM32_NADC > 1 -# define STM32_ADC2_SR (STM32_ADC2_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC2_CR1 (STM32_ADC2_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC2_CR2 (STM32_ADC2_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_JOFR1 (STM32_ADC2_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC2_JOFR2 (STM32_ADC2_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC2_JOFR3 (STM32_ADC2_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC2_JOFR4 (STM32_ADC2_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC2_HTR (STM32_ADC2_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC2_LTR (STM32_ADC2_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC3_SR (STM32_ADC3_BASE + STM32_ADC_SR_OFFSET) -# define STM32_ADC3_CR1 (STM32_ADC3_BASE + STM32_ADC_CR1_OFFSET) -# define STM32_ADC3_CR2 (STM32_ADC3_BASE + STM32_ADC_CR2_OFFSET) -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_JOFR1 (STM32_ADC3_BASE + STM32_ADC_JOFR1_OFFSET) -# define STM32_ADC3_JOFR2 (STM32_ADC3_BASE + STM32_ADC_JOFR2_OFFSET) -# define STM32_ADC3_JOFR3 (STM32_ADC3_BASE + STM32_ADC_JOFR3_OFFSET) -# define STM32_ADC3_JOFR4 (STM32_ADC3_BASE + STM32_ADC_JOFR4_OFFSET) -# define STM32_ADC3_HTR (STM32_ADC3_BASE + STM32_ADC_HTR_OFFSET) -# define STM32_ADC3_LTR (STM32_ADC3_BASE + STM32_ADC_LTR_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) -#endif - -#define STM32_ADC_CSR (STM32_ADCCMN_BASE + STM32_ADC_CSR_OFFSET) -#define STM32_ADC_CCR (STM32_ADCCMN_BASE + STM32_ADC_CCR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* ADC status register */ - -#define ADC_SR_AWD (1 << 0) /* Bit 0 : Analog watchdog flag */ -#define ADC_SR_EOC (1 << 1) /* Bit 1 : End of conversion */ -#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */ -#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */ -#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */ -#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */ -#define ADC_SR_ADONS (1 << 6) /* Bit 6 : ADC ON status. Set and cleared by HW */ -#define ADC_SR_RCNR (1 << 8) /* Bit 8 : Regular channel not ready. Set and cleared by HW */ -#define ADC_SR_JCNR (1 << 9) /* Bit 9 : Injected channel not ready. Set and cleared by HW */ - -/* ADC control register 1 */ - -#define ADC_CR1_AWDCH_SHIFT (0) /* Bits 4-0: Analog watchdog channel select bits */ -#define ADC_CR1_AWDCH_MASK (0x1f << ADC_CR1_AWDCH_SHIFT) - -#define ADC_CR1_EOCIE (1 << 5) /* Bit 5: Interrupt enable for EOC */ -#define ADC_CR1_AWDIE (1 << 6) /* Bit 6: Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE (1 << 7) /* Bit 7: Interrupt enable for injected channels */ -#define ADC_CR1_SCAN (1 << 8) /* Bit 8: Scan mode */ -#define ADC_CR1_AWDSGL (1 << 9) /* Bit 9: Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO (1 << 10) /* Bit 10: Automatic Injected Group conversion */ -#define ADC_CR1_DISCEN (1 << 11) /* Bit 11: Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN (1 << 12) /* Bit 12: Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM_SHIFT (13) /* Bits 15-13: Discontinuous mode channel count */ -#define ADC_CR1_DISCNUM_MASK (0x07 << ADC_CR1_DISCNUM_SHIFT) - -#define ADC_CR1_PDD (1 << 16) /* Bit 16 : Power down during the delay phase. This bit must be written only when ADON=0 */ -#define ADC_CR1_PDI (1 << 17) /* Bit 17 : Power down during the idle phase. This bit must - * be written only when ADON=0 */ -#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */ -#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT) -# define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 12 ADCCLK cycles */ -# define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles */ -# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles */ -# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 7 ADCCLK cycles */ - -#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */ -#define ADC_CR1_RESERVED (0xfb3f0000) - -/* ADC control register 2 */ - -#define ADC_CR2_ADON (1 << 0) /* Bit 0: A/D Converter ON / OFF */ -#define ADC_CR2_CONT (1 << 1) /* Bit 1: Continuous Conversion */ -#define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no - * conversion is on going. This bit is available in high and medium + - * density devices only. - */ - -#define ADC_CR2_DELS_SHIFT (4) /* Bits 2-0: Delay selection */ -#define ADC_CR2_DELS_MASK (0x07 << ADC_CR2_DELS_SHIFT) -#define ADC_CR2_DELS_NODEL (0x0 << ADC_CR2_DELS_SHIFT) /* No delay */ -#define ADC_CR2_DELS_TILLRD (0x01 << ADC_CR2_DELS_SHIFT) /* Until the converted data have been read */ -#define ADC_CR2_DELS_APB7 (0x02 << ADC_CR2_DELS_SHIFT) /* 7 APB clock cycles after the end of conversion */ -#define ADC_CR2_DELS_APB15 (0x03 << ADC_CR2_DELS_SHIFT) /* 15 APB clock cycles after the end of conversion */ -#define ADC_CR2_DELS_APB31 (0x04 << ADC_CR2_DELS_SHIFT) /* 31 APB clock cycles after the end of conversion */ -#define ADC_CR2_DELS_APB63 (0x05 << ADC_CR2_DELS_SHIFT) /* 63 APB clock cycles after the end of conversion */ -#define ADC_CR2_DELS_APB127 (0x06 << ADC_CR2_DELS_SHIFT) /* 127 APB clock cycles after the end of conversion */ -#define ADC_CR2_DELS_APB255 (0x07 << ADC_CR2_DELS_SHIFT) /* 255 APB clock cycles after the end of conversion */ - -#define ADC_CR2_DMA (1 << 8) /* Bit 8: Direct Memory access mode */ -#define ADC_CR2_DDS (1 << 9) /* Bit 9: DMA disable selection (for single ADC mode) */ -#define ADC_CR2_EOCS (1 << 10) /* Bit 10: End of conversion selection */ -#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */ - /* Bits 12-15: Reserved */ -#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */ -#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT) -# define ADC_CR2_JEXTSEL_T9CC1 (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 9 CC1 event */ -# define ADC_CR2_JEXTSEL_T9TRGO (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ -# define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event*/ -# define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */ -# define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */ -# define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */ -# define ADC_CR2_JEXTSEL_T4CC1 (0x06 << ADC_CR2_JEXTSEL_SHIFT) /* 0110: Timer 4 CC1 event */ -# define ADC_CR2_JEXTSEL_T4CC2 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 4 CC2 event */ -# define ADC_CR2_JEXTSEL_T4CC3 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 4 CC3 event */ -# define ADC_CR2_JEXTSEL_T10CC1 (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 10 CC1 event */ -# define ADC_CR2_JEXTSEL_T7TRGO (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 7 TRGO event */ -# define ADC_CR2_JEXTSEL_EXTI15 (0x0F << ADC_CR2_JEXTSEL_SHIFT) /* 1111: EXTI line 15 */ - -#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */ -#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT) -# define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */ - /* Bit 23: Reserved, must be kept at reset value. */ -#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */ -#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT) -# define ADC_CR2_EXTSEL_T9CC2 (0x00 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 9 CC2 event */ -# define ADC_CR2_EXTSEL_T9TRGO (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 9 TRGO event */ -# define ADC_CR2_EXTSEL_T2CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 2 CC3 event */ -# define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */ -# define ADC_CR2_EXTSEL_T3TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ -# define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ -# define ADC_CR2_EXTSEL_T2TRGO (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 2 TRGO event */ -# define ADC_CR2_EXTSEL_T3CC1 (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 3 CC1 event */ -# define ADC_CR2_EXTSEL_T3CC3 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 3 CC3 event */ -# define ADC_CR2_EXTSEL_T4TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 4 TRGO event */ -# define ADC_CR2_EXTSEL_T6TRGO (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 6 TRGO event */ -# define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */ - -#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */ -#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT) -# define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ - -#define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */ -#define ADC_CR2_RESERVED (0x8080f0fc) - -/* ADC sample time register 1 */ - -#define ADC_SMPR_4 0 /* 000: 3 cycles */ -#define ADC_SMPR_9 1 /* 001: 9 cycles */ -#define ADC_SMPR_16 2 /* 010: 16 cycles */ -#define ADC_SMPR_24 3 /* 011: 24 cycles */ -#define ADC_SMPR_48 4 /* 100: 48 cycles */ -#define ADC_SMPR_96 5 /* 101: 96 cycles */ -#define ADC_SMPR_192 6 /* 110: 192 cycles */ -#define ADC_SMPR_384 7 /* 111: 384 cycles */ - -#define ADC_SMPR1_SMP20_SHIFT (0) /* Bits 0-2: Channel 20 Sample time selection */ -#define ADC_SMPR1_SMP20_MASK (7 << ADC_SMPR1_SMP20_SHIFT) -#define ADC_SMPR1_SMP21_SHIFT (3) /* Bits 3-5: Channel 21 Sample time selection */ -#define ADC_SMPR1_SMP21_MASK (7 << ADC_SMPR1_SMP21_SHIFT) -#define ADC_SMPR1_SMP22_SHIFT (6) /* Bits 6-8: Channel 22 Sample time selection */ -#define ADC_SMPR1_SMP22_MASK (7 << ADC_SMPR1_SMP22_SHIFT) -#define ADC_SMPR1_SMP23_SHIFT (9) /* Bits 9-11: Channel 23 Sample time selection */ -#define ADC_SMPR1_SMP23_MASK (7 << ADC_SMPR1_SMP23_SHIFT) -#define ADC_SMPR1_SMP24_SHIFT (12) /* Bits 12-14: Channel 24 Sample time selection */ -#define ADC_SMPR1_SMP24_MASK (7 << ADC_SMPR1_SMP24_SHIFT) -#define ADC_SMPR1_SMP25_SHIFT (15) /* Bits 15-17: Channel 25 Sample time selection */ -#define ADC_SMPR1_SMP25_MASK (7 << ADC_SMPR1_SMP25_SHIFT) -#define ADC_SMPR1_SMP26_SHIFT (18) /* Bits 18-20: Channel 26 Sample time selection */ -#define ADC_SMPR1_SMP26_MASK (7 << ADC_SMPR1_SMP26_SHIFT) -#define ADC_SMPR1_SMP27_SHIFT (21) /* Bits 21-23: Channel 27 Sample time selection */ -#define ADC_SMPR1_SMP27_MASK (7 << ADC_SMPR1_SMP27_SHIFT) -#define ADC_SMPR1_SMP28_SHIFT (24) /* Bits 24-26: Channel 28 Sample time selection */ -#define ADC_SMPR1_SMP28_MASK (7 << ADC_SMPR1_SMP28_SHIFT) -#define ADC_SMPR1_SMP29_SHIFT (27) /* Bits 27-29: Channel 29 Sample time selection */ -#define ADC_SMPR1_SMP29_MASK (7 << ADC_SMPR1_SMP29_SHIFT) - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) -#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) -#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) -#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) -#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) -#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) -#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) -#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) -#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) -#define ADC_SMPR2_SMP19_SHIFT (27) /* Bits 27-29: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP19_MASK (7 << ADC_SMPR2_SMP19_SHIFT) - -/* ADC sample time register 3 */ - -#define ADC_SMPR3_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */ -#define ADC_SMPR3_SMP0_MASK (7 << ADC_SMPR3_SMP0_SHIFT) -#define ADC_SMPR3_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR3_SMP1_MASK (7 << ADC_SMPR3_SMP1_SHIFT) -#define ADC_SMPR3_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR3_SMP2_MASK (7 << ADC_SMPR3_SMP2_SHIFT) -#define ADC_SMPR3_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR3_SMP3_MASK (7 << ADC_SMPR3_SMP3_SHIFT) -#define ADC_SMPR3_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR3_SMP4_MASK (7 << ADC_SMPR3_SMP4_SHIFT) -#define ADC_SMPR3_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR3_SMP5_MASK (7 << ADC_SMPR3_SMP5_SHIFT) -#define ADC_SMPR3_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR3_SMP6_MASK (7 << ADC_SMPR3_SMP6_SHIFT) -#define ADC_SMPR3_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR3_SMP7_MASK (7 << ADC_SMPR3_SMP7_SHIFT) -#define ADC_SMPR3_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR3_SMP8_MASK (7 << ADC_SMPR3_SMP8_SHIFT) -#define ADC_SMPR3_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR3_SMP9_MASK (7 << ADC_SMPR3_SMP9_SHIFT) - -/* ADC sample time register 0 */ - -#define ADC_SMPR0_SMP30_SHIFT (0) /* Bits 2-0: Channel 30 Sample time selection */ -#define ADC_SMPR0_SMP30_MASK (7 << ADC_SMPR3_SMP30_SHIFT) -#define ADC_SMPR0_SMP31_SHIFT (3) /* Bits 5-3: Channel 31 Sample time selection */ -#define ADC_SMPR0_SMP31_MASK (7 << ADC_SMPR3_SMP31_SHIFT) - -/* ADC injected channel data offset register 1-4 */ - -#define ADC_JOFR_SHIFT (0) /* Bits 11-0: Data offset for injected channel x */ -#define ADC_JOFR_MASK (0x0fff << ADC_JOFR_SHIFT) - -/* ADC watchdog high threshold register */ - -#define ADC_HTR_SHIFT (0) /* Bits 11-0: Analog watchdog high threshold */ -#define ADC_HTR_MASK (0x0fff << ADC_HTR_SHIFT) - -/* ADC watchdog low threshold register */ - -#define ADC_LTR_SHIFT (0) /* Bits 11-0: Analog watchdog low threshold */ -#define ADC_LTR_MASK (0x0fff << ADC_LTR_SHIFT) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_SQ25_SHIFT (0) /* Bits 4-0: 25th conversion in regular sequence */ -#define ADC_SQR1_SQ25_MASK (0x1f << ADC_SQR1_SQ25_SHIFT) -#define ADC_SQR1_SQ26_SHIFT (5) /* Bits 9-5: 26th conversion in regular sequence */ -#define ADC_SQR1_SQ26_MASK (0x1f << ADC_SQR1_SQ26_SHIFT) -#define ADC_SQR1_SQ27_SHIFT (10) /* Bits 14-10: 27th conversion in regular sequence */ -#define ADC_SQR1_SQ27_MASK (0x1f << ADC_SQR1_SQ27_SHIFT) -#define ADC_SQR1_SQ28_SHIFT (15) /* Bits 19-15: 28th conversion in regular sequence */ -#define ADC_SQR1_SQ28_MASK (0x1f << ADC_SQR1_SQ28_SHIFT) -#define ADC_SQR1_L_SHIFT (20) /* Bits 24-20: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x1f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_RESERVED (0xff000000) -#define ADC_SQR1_FIRST (25) -#define ADC_SQR1_LAST (28) -#define ADC_SQR1_SQ_OFFSET (0) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ19_SHIFT (0) /* Bits 4-0: 19th conversion in regular sequence */ -#define ADC_SQR2_SQ19_MASK (0x1f << ADC_SQR2_SQ19_SHIFT) -#define ADC_SQR2_SQ20_SHIFT (5) /* Bits 9-5: 20th conversion in regular sequence */ -#define ADC_SQR2_SQ20_MASK (0x1f << ADC_SQR2_SQ20_SHIFT) -#define ADC_SQR2_SQ21_SHIFT (10) /* Bits 14-10: 21th conversion in regular sequence */ -#define ADC_SQR2_SQ21_MASK (0x1f << ADC_SQR2_SQ21_SHIFT) -#define ADC_SQR2_SQ22_SHIFT (15) /* Bits 19-15: 22th conversion in regular sequence */ -#define ADC_SQR2_SQ22_MASK (0x1f << ADC_SQR2_SQ22_SHIFT) -#define ADC_SQR2_SQ23_SHIFT (20) /* Bits 24-20: 23th conversion in regular sequence */ -#define ADC_SQR2_SQ23_MASK (0x1f << ADC_SQR2_SQ23_SHIFT ) -#define ADC_SQR2_SQ24_SHIFT (25) /* Bits 29-25: 24th conversion in regular sequence */ -#define ADC_SQR2_SQ24_MASK (0x1f << ADC_SQR2_SQ24_SHIFT) -#define ADC_SQR2_RESERVED (0xc0000000) -#define ADC_SQR2_FIRST (19) -#define ADC_SQR2_LAST (24) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -#define ADC_SQR3_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -#define ADC_SQR3_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */ -#define ADC_SQR3_SQ15_MASK (0x1f << ADC_SQR3_SQ15_SHIFT) -#define ADC_SQR3_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */ -#define ADC_SQR3_SQ16_MASK (0x1f << ADC_SQR3_SQ16_SHIFT) -#define ADC_SQR3_SQ17_SHIFT (20) /* Bits 24-20: 17th conversion in regular sequence */ -#define ADC_SQR3_SQ17_MASK (0x1f << ADC_SQR3_SQ17_SHIFT ) -#define ADC_SQR3_SQ18_SHIFT (25) /* Bits 29-25: 18th conversion in regular sequence */ -#define ADC_SQR3_SQ18_MASK (0x1f << ADC_SQR3_SQ18_SHIFT) -#define ADC_SQR3_RESERVED (0xc0000000) -#define ADC_SQR3_FIRST (13) -#define ADC_SQR3_LAST (18) -#define ADC_SQR3_SQ_OFFSET (0) - -/* ADC regular sequence register 4 */ - -#define ADC_SQR4_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */ -#define ADC_SQR4_SQ7_MASK (0x1f << ADC_SQR4_SQ7_SHIFT) -#define ADC_SQR4_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */ -#define ADC_SQR4_SQ8_MASK (0x1f << ADC_SQR4_SQ8_SHIFT) -#define ADC_SQR4_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */ -#define ADC_SQR4_SQ9_MASK (0x1f << ADC_SQR4_SQ9_SHIFT) -#define ADC_SQR4_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */ -#define ADC_SQR4_SQ10_MASK (0x1f << ADC_SQR4_SQ10_SHIFT) -#define ADC_SQR4_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */ -#define ADC_SQR4_SQ11_MASK (0x1f << ADC_SQR4_SQ11_SHIFT ) -#define ADC_SQR4_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */ -#define ADC_SQR4_SQ12_MASK (0x1f << ADC_SQR4_SQ12_SHIFT) -#define ADC_SQR4_RESERVED (0xc0000000) -#define ADC_SQR4_FIRST (7) -#define ADC_SQR4_LAST (12) -#define ADC_SQR4_SQ_OFFSET (0) - -/* ADC regular sequence register 5 */ - -#define ADC_SQR5_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */ -#define ADC_SQR5_SQ1_MASK (0x1f << ADC_SQR5_SQ1_SHIFT) -#define ADC_SQR5_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */ -#define ADC_SQR5_SQ2_MASK (0x1f << ADC_SQR5_SQ2_SHIFT) -#define ADC_SQR5_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */ -#define ADC_SQR5_SQ3_MASK (0x1f << ADC_SQR5_SQ3_SHIFT) -#define ADC_SQR5_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */ -#define ADC_SQR5_SQ4_MASK (0x1f << ADC_SQR5_SQ4_SHIFT) -#define ADC_SQR5_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */ -#define ADC_SQR5_SQ5_MASK (0x1f << ADC_SQR5_SQ5_SHIFT ) -#define ADC_SQR5_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */ -#define ADC_SQR5_SQ6_MASK (0x1f << ADC_SQR5_SQ6_SHIFT) -#define ADC_SQR5_RESERVED (0xc0000000) -#define ADC_SQR5_FIRST (1) -#define ADC_SQR5_LAST (6) -#define ADC_SQR5_SQ_OFFSET (0) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (5) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JSQ1_SHIFT (0) /* Bits 4-0: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -#define ADC_JSQR_JSQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -#define ADC_JSQR_JSQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -#define ADC_JSQR_JSQ4_SHIFT (15) /* Bits 19-15: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -#define ADC_JSQR_JSQ_SHIFT (5) /* Shift between JSQx bits */ -#define ADC_JSQR_JL_SHIFT (20) /* Bits 21-20: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ - -/* ADC injected data register 1-4 */ - -#define ADC_JDR_JDATA_SHIFT (0) /* Bits 15-0: Injected data */ -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) /* Bits 15-0 Regular data */ -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* Common status register */ - -#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */ -#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */ -#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */ -#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */ -#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */ -#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */ - /* Bits 6-7: Reserved, must be kept at reset value. */ -#define ADC_CSR_ADONS1 (1 << 6) /* Bit 6: ADON Status of ADC1. This bit is a copy of the ADONS bit in the ADC_SR register. */ - -/* Common control register */ - -/* Bits 15-0: Reserved, - * must be kept at reset value - */ - -#define ADC_CCR_ADCPRE_SHIFT (16) /* Bits 16-17: ADC prescaler */ -#define ADC_CCR_ADCPRE_MASK (3 << ADC_CCR_ADCPRE_SHIFT) -# define ADC_CCR_ADCPRE_DIV1 (0 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 1 */ -# define ADC_CCR_ADCPRE_DIV2 (1 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 2 */ -# define ADC_CCR_ADCPRE_DIV4 (2 << ADC_CCR_ADCPRE_SHIFT) /* HSI divided by 4 */ - /* 11: Reserved */ - -/* Bits 22-18: Reserved, - * must be kept at reset value - */ -#define ADC_CCR_TSVREFE (1 << 23) /* Bit 23: Temperature sensor and VREFINT enable */ - /* Bits 31-24: Reserved, must be kept at reset value */ - -/* Data register for dual and triple modes - *(32-bit data with no named fields) - */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h deleted file mode 100644 index 6e62bb59a7418..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ /dev/null @@ -1,735 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), - * H7, L0, L4, L4+ - */ - -#define HAVE_IP_ADC_V2 -#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ -#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ -#undef HAVE_ADC_POWERDOWN /* No ADC power down */ -#define HAVE_ADC_VBAT /* VBAT channel support */ - -/* F0 and L0 have basic version of ADC hardware (not present here for now): - * - channel selection register (CHSELR) - * - sampling time configuration common for all channels - * - one TR register - * - no SQR registers - * - ... - * - * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) - */ - -#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC -# define HAVE_BASIC_ADC -# error TODO -#else -# undef HAVE_BASIC_ADC -#endif - -/* F30X and F33x don't have CFGR2 register */ - -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) -# undef HAVE_ADC_CFGR2 -#else -# define HAVE_ADC_CFGR2 -#endif - -/* Base addresses ***********************************************************/ - -#define STM32_ADC1_OFFSET 0x0000 -#define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC3_OFFSET 0x0000 -#define STM32_ADC4_OFFSET 0x0100 -#define STM32_ADCCMN_OFFSET 0x0300 - -#define STM32_ADC1_BASE (STM32_ADC1_OFFSET + STM32_ADC12_BASE) /* ADC1 Master ADC */ -#define STM32_ADC2_BASE (STM32_ADC2_OFFSET + STM32_ADC12_BASE) /* ADC2 Slave ADC */ -#define STM32_ADC3_BASE (STM32_ADC3_OFFSET + STM32_ADC34_BASE) /* ADC3 Master ADC */ -#define STM32_ADC4_BASE (STM32_ADC4_OFFSET + STM32_ADC34_BASE) /* ADC4 Slave ADC */ -#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */ -#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */ - -/* Register Offsets *********************************************************/ - -#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC configuration register 1 */ -#ifdef HAVE_ADC_CFGR2 -# define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#endif -#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC data offset register 4 */ -#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */ -#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ - -/* Master and Slave ADC Common Registers */ - -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ - -/* Register Addresses *******************************************************/ - -#if STM32_NADC > 0 -# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) -# ifdef HAVE_ADC_CFGR2 -# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) -# endif -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) -#endif - -#if STM32_NADC > 1 -# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) -# ifdef HAVE_ADC_CFGR2 -# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) -# endif -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) -# ifdef HAVE_ADC_CFGR2 -# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) -# endif -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) -#endif - -#if STM32_NADC > 3 -# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) -# ifdef HAVE_ADC_CFGR2 -# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) -# endif -# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) -#endif - -#if STM32_NADC > 0 -# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC34_CSR (STM32_ADC34CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC34_CCR (STM32_ADC34CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE + STM32_ADC_CDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* ADC interrupt and status register (ISR), and - * ADC interrupt enable register (IER) - */ - -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ -#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ -#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ -#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ -#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ -#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ - -/* ADC control register */ - -#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ -#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ -#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ -#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */ -#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ -#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */ -#define ADC_CR_ADVREGEN_SHIFT (28) /* Bits 28-29: ADC voltage regulator enable */ -#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT) -# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) /* Intermediate state */ -# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator enabled */ -# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) /* ADC Voltage regulator disabled */ -#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ -#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ - -/* ADC configuration register 1 */ - -#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR1_RES_MASK (3 << ADC_CFGR1_RES_SHIFT) -# define ADC_CFGR1_RES_12BIT (0 << ADC_CFGR1_RES_SHIFT) /* 15 ADCCLK cycles */ -# define ADC_CFGR1_RES_10BIT (1 << ADC_CFGR1_RES_SHIFT) /* 13 ADCCLK cycles */ -# define ADC_CFGR1_RES_8BIT (2 << ADC_CFGR1_RES_SHIFT) /* 11 ADCCLK cycles */ -# define ADC_CFGR1_RES_6BIT (3 << ADC_CFGR1_RES_SHIFT) /* 9 ADCCLK cycles */ -#define ADC_CFGR1_ALIGN (1 << 5) /* Bit 5: Data Alignment */ -#define ADC_CFGR1_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */ -#define ADC_CFGR1_EXTSEL_MASK (15 << ADC_CFGR1_EXTSEL_SHIFT) -#if defined(CONFIG_STM32_STM32F33XX) -# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) - /* 0101: Reserved */ -# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (7 << ADC_CFGR1_EXTSEL_SHIFT) /* 0111: HRTIM1 ADCTRG1 event */ -# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (8 << ADC_CFGR1_EXTSEL_SHIFT) /* 1000: HRTIM1 ADCTRG3 event */ -# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) - /* 1100: Reserved */ -# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) -#elif defined(CONFIG_STM32_STM32F30XX) -# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T8TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20TRGO (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T3TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T7TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) -#else -# error TODO EXTSEL -#endif -#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR1_EXTEN_MASK (3 << ADC_CFGR1_EXTEN_SHIFT) -# define ADC_CFGR1_EXTEN_NONE (0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ -#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ -#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */ -#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ -#define ADC_CFGR1_DISCNUM_MASK (7 << ADC_CFGR1_DISCNUM_SHIFT) -# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << \ - ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */ -#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ -#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */ -#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ -#define ADC_CFGR1_JAWD1EN (1 << 24) /* Bit 24: Analog watchdog enable 1 injected channels */ -#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic Injected Group conversion */ -#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR1_AWD1CH_MASK (31 << ADC_CFGR1_AWD1CH_SHIFT) -# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT) - -/* TODO: ADC configuration register 2 */ - -/* ADC sample time register 1 */ - -#define ADC_SMPR_1p5 0 /* 000: 1.5 cycles */ -#define ADC_SMPR_2p5 1 /* 001: 2.5 cycles */ -#define ADC_SMPR_4p5 2 /* 010: 4.5 cycles */ -#define ADC_SMPR_7p5 3 /* 011: 7.5 cycles */ -#define ADC_SMPR_19p5 4 /* 100: 19.5 cycles */ -#define ADC_SMPR_61p5 5 /* 101: 61.5 cycles */ -#define ADC_SMPR_181p5 6 /* 110: 181.5 cycles */ -#define ADC_SMPR_601p5 7 /* 111: 601.5 cycles */ - -#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */ -#define ADC_SMPR1_SMP1_MASK (7 << ADC_SMPR1_SMP1_SHIFT) -#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */ -#define ADC_SMPR1_SMP2_MASK (7 << ADC_SMPR1_SMP2_SHIFT) -#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */ -#define ADC_SMPR1_SMP3_MASK (7 << ADC_SMPR1_SMP3_SHIFT) -#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */ -#define ADC_SMPR1_SMP4_MASK (7 << ADC_SMPR1_SMP4_SHIFT) -#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */ -#define ADC_SMPR1_SMP5_MASK (7 << ADC_SMPR1_SMP5_SHIFT) -#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */ -#define ADC_SMPR1_SMP6_MASK (7 << ADC_SMPR1_SMP6_SHIFT) -#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */ -#define ADC_SMPR1_SMP7_MASK (7 << ADC_SMPR1_SMP7_SHIFT) -#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */ -#define ADC_SMPR1_SMP8_MASK (7 << ADC_SMPR1_SMP8_SHIFT) -#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */ -#define ADC_SMPR1_SMP9_MASK (7 << ADC_SMPR1_SMP9_SHIFT) - -/* ADC sample time register 2 */ - -#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR2_SMP10_MASK (7 << ADC_SMPR2_SMP10_SHIFT) -#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR2_SMP11_MASK (7 << ADC_SMPR2_SMP11_SHIFT) -#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR2_SMP12_MASK (7 << ADC_SMPR2_SMP12_SHIFT) -#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR2_SMP13_MASK (7 << ADC_SMPR2_SMP13_SHIFT) -#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR2_SMP14_MASK (7 << ADC_SMPR2_SMP14_SHIFT) -#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR2_SMP15_MASK (7 << ADC_SMPR2_SMP15_SHIFT) -#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR2_SMP16_MASK (7 << ADC_SMPR2_SMP16_SHIFT) -#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR2_SMP17_MASK (7 << ADC_SMPR2_SMP17_SHIFT) -#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP18_MASK (7 << ADC_SMPR2_SMP18_SHIFT) - -/* ADC watchdog threshold register 1 */ - -#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ -#define ADC_TR1_LT_MASK (0x0fff << ADC_TR1_LT_SHIFT) -#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ -#define ADC_TR1_HT_MASK (0x0fff << ADC_TR1_HT_SHIFT) - -/* ADC watchdog threshold register 2 */ - -#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ -#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) -#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ -#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) - -/* ADC watchdog threshold register 3 */ - -#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ -#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) -#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ -#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) - -/* Offset between SQ bits */ - -#define ADC_SQ_OFFSET (6) - -/* ADC regular sequence register 1 */ - -#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 13th conversion in regular sequence */ -#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) -#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) -#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) -#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) -#define ADC_SQR1_RESERVED (0xe0820830) -#define ADC_SQR1_FIRST (1) -#define ADC_SQR1_LAST (4) -#define ADC_SQR1_SQ_OFFSET (1*ADC_SQ_OFFSET) - -/* ADC regular sequence register 2 */ - -#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 4-0: 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) -#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) -#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_RESERVED (0xe0820820) -#define ADC_SQR2_FIRST (5) -#define ADC_SQR2_LAST (9) -#define ADC_SQR2_SQ_OFFSET (0) - -/* ADC regular sequence register 3 */ - -#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 4-0: 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) -#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) -#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) -#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -#define ADC_SQR3_RESERVED (0xe0820820) -#define ADC_SQR3_FIRST (10) -#define ADC_SQR3_LAST (14) -#define ADC_SQR3_SQ_OFFSET (0) - -/* ADC regular sequence register 4 */ - -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 4-0: 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) -#define ADC_SQR4_RESERVED (0xfffff820) -#define ADC_SQR4_FIRST (15) -#define ADC_SQR4_LAST (16) -#define ADC_SQR4_SQ_OFFSET (0) - -/* ADC regular data register */ - -#define ADC_DR_RDATA_SHIFT (0) -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* ADC injected sequence register */ - -#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */ -#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */ -#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */ -#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT) -#if defined(CONFIG_STM32_STM32F33XX) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) - /* 0101: Reserved */ -# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) /* 0110: EXTI line 15 */ - /* 0111: Reserved */ -# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (9 << ADC_JSQR_JEXTSEL_SHIFT) /* 1001: HRTIM1 ADCTRG2 event */ -# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (10 << ADC_JSQR_JEXTSEL_SHIFT) /* 1010: HRTIM1 ADCTRG4 event */ -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -#elif defined(CONFIG_STM32_STM32F30XX) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC3 (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4TRGO (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T2TRGO (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T7TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -#else -# error TODO JEXTSEL -#endif -# define ADC_JSQR_JEXTEN_SHIFT (6) /* Bits 6-7: External trigger selection for injected greoup */ -# define ADC_JSQR_JEXTEN_MASK (3 << ADC_JSQR_JEXTEN_SHIFT) -# define ADC_JSQR_JEXTEN_NONE (0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_JSQR_JEXTEN_RISING (1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_JSQR_JEXTEN_FALLING (2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_JSQR_JEXTEN_BOTH (3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ -#define ADC_JSQR_JSQ1_SHIFT (8) /* Bits 8-12: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ4_SHIFT (26) /* Bits 26-30: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ_SHIFT (6) /* Shift between JSQx bits */ - -/* ADC offset register 1 and 2 */ - -#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ -#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) -# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) -#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ -#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) -# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) -#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ - -/* ADC injected data register 1 and 2 */ - -#define ADC_JDR_JDATA_SHIFT (0) -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC analog watchdog 2 configuration register */ - -#define ADC_AWD2CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x3ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC analog watchdog 3 configuration register */ - -#define ADC_AWD3CR_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x3ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC differential mode selection register 2 */ -#define ADC_DIFSEL_ - -#define ADC_DIFSEL_CH_SHIFT (1) /* Bits 1-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x3ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=1..18 */ - -/* ADC calibration factors */ - -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration Factors indifferential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) - -/* Common status register */ - -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ - -/* Common control register */ - -#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ -#define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) -# define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ -# define ADC_CCR_DUAL_DUAL (1 << ADC_CCR_DUAL_SHIFT) /* Dual mode, master/slave ADCs together */ -# define ADC_CCR_DUAL_SIMINJ (1 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + injected sim. */ -# define ADC_CCR_DUAL_SIMALT (2 << ADC_CCR_DUAL_SHIFT) /* Combined regular sim. + alternate trigger */ -# define ADC_CCR_DUAL_INTINJ (3 << ADC_CCR_DUAL_SHIFT) /* Combined interl. mode + injected sim. */ -# define ADC_CCR_DUAL_INJECTED (5 << ADC_CCR_DUAL_SHIFT) /* Injected simultaneous mode only */ -# define ADC_CCR_DUAL_SIM (6 << ADC_CCR_DUAL_SHIFT) /* Regular simultaneous mode only */ -# define ADC_CCR_DUAL_INTERLEAVE (7 << ADC_CCR_DUAL_SHIFT) /* Interleaved mode only */ -# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */ -#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT) -# define ADC_CCR_DELAY(n) (((n) - 1) << \ - ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ -#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT) -# define ADC_CCR_MDMA_DISABLED (0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ -# define ADC_CCR_MDMA_10_12 (2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ -# define ADC_CCR_MDMA_6_8 (3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ -#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ -#define ADC_CCR_CKMODE_MASK (15 << ADC_CCR_CKMODE_SHIFT) -# define ADC_CCR_CKMODE_ASYNCH (0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ -# define ADC_CCR_CKMODE_SYNCH_DIV1 (1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ -# define ADC_CCR_CKMODE_SYNCH_DIV2 (2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ -# define ADC_CCR_CKMODE_SYNCH_DIV4 (3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 22: VBAT enable */ - -/* Common regular data register for dual mode */ - -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h deleted file mode 100644 index 211bff7fe43f5..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h +++ /dev/null @@ -1,869 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2g4.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_IP_ADC_V2 -#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */ -#undef HAVE_ADC_CLOCK_HSI /* No ADC clock from HSI */ -#undef HAVE_ADC_POWERDOWN /* No ADC power down */ -#define HAVE_ADC_VBAT /* VBAT channel support */ -#undef HAVE_BASIC_ADC - -/* Base addresses ***********************************************************/ - -#define STM32_ADC1_OFFSET 0x0000 -#define STM32_ADC2_OFFSET 0x0100 -#define STM32_ADC3_OFFSET 0x0000 -#define STM32_ADC4_OFFSET 0x0100 -#define STM32_ADC5_OFFSET 0x0200 -#define STM32_ADCCMN_OFFSET 0x0300 - -#define STM32_ADC1_BASE (STM32_ADC12_BASE + STM32_ADC1_OFFSET) /* ADC1 Master ADC */ -#define STM32_ADC2_BASE (STM32_ADC12_BASE + STM32_ADC2_OFFSET) /* ADC2 Slave ADC */ -#define STM32_ADC12CMN_BASE (STM32_ADC12_BASE + STM32_ADCCMN_OFFSET) /* ADC1, ADC2 common */ -#define STM32_ADC3_BASE (STM32_ADC345_BASE + STM32_ADC3_OFFSET) /* ADC3 Master ADC */ -#define STM32_ADC4_BASE (STM32_ADC345_BASE + STM32_ADC4_OFFSET) /* ADC4 Slave ADC */ -#define STM32_ADC5_BASE (STM32_ADC345_BASE + STM32_ADC5_OFFSET) /* ADC4 Slave ADC */ -#define STM32_ADC345CMN_BASE (STM32_ADC345_BASE + STM32_ADCCMN_OFFSET) /* ADC3, ADC4 common */ - -/* Compatibility defines */ - -#define STM32_ADC34CMN_BASE STM32_ADC345CMN_BASE - -/* Register Offsets *********************************************************/ - -/* Registers for Each ADC */ - -#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC Interrupt and Status register */ -#define STM32_ADC_IER_OFFSET 0x0004 /* ADC Interrupt Enable register */ -#define STM32_ADC_CR_OFFSET 0x0008 /* ADC Control register */ -#define STM32_ADC_CFGR1_OFFSET 0x000c /* ADC Configuration register 1 */ -#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC Configuration register 2 */ -#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC Sample Time register 1 */ -#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC Sample Time register 2 */ -#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC Watchdog Threshold register 1 */ -#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC Watchdog Threshold register 2 */ -#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC Watchdog Threshold register 3 */ -#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC Regular Sequence register 1 */ -#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC Regular Sequence register 2 */ -#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC Regular Sequence register 3 */ -#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC Regular Sequence register 4 */ -#define STM32_ADC_DR_OFFSET 0x0040 /* ADC Regular data register */ -#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC Injected Sequence register */ -#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC Offset register 1 */ -#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC Offset register 2 */ -#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC Offset register 3 */ -#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC Offset register 4 */ -#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC Injected Data register 1 */ -#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC Injected Data register 2 */ -#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC Injected Data register 3 */ -#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC Injected Data register 4 */ -#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC Analog Watchdog 2 Configuration register */ -#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC Analog Watchdog 3 Configuration register */ -#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC Differential Mode Selection register */ -#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC Calibration Factors register */ -#define STM32_ADC_GCOMP_OFFSET 0x00c0 /* ADC Gain compensation register */ - -/* Master and Slave ADC Common Registers */ - -#define STM32_ADC_CSR_OFFSET 0x0000 /* Common Status register */ -#define STM32_ADC_CCR_OFFSET 0x0008 /* Common Control register */ -#define STM32_ADC_CDR_OFFSET 0x000c /* Common Regular Data Register for Dual Mode */ - -/* Register Addresses *******************************************************/ - -/* Registers for Each ADC */ - -#if STM32_NADC > 0 -# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC1_IER (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC1_CR (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC1_CFGR1 (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET) -# define STM32_ADC1_CFGR2 (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET) -# define STM32_ADC1_SMPR1 (STM32_ADC1_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC1_SMPR2 (STM32_ADC1_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC1_TR1 (STM32_ADC1_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC1_TR2 (STM32_ADC1_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC1_TR3 (STM32_ADC1_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC1_SQR1 (STM32_ADC1_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC1_SQR2 (STM32_ADC1_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC1_SQR3 (STM32_ADC1_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC1_SQR4 (STM32_ADC1_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC1_DR (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC1_JSQR (STM32_ADC1_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC1_OFR1 (STM32_ADC1_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC1_OFR2 (STM32_ADC1_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC1_OFR3 (STM32_ADC1_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC1_OFR4 (STM32_ADC1_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC1_JDR1 (STM32_ADC1_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC1_JDR2 (STM32_ADC1_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC1_JDR3 (STM32_ADC1_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC1_JDR4 (STM32_ADC1_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC1_AWD2CR (STM32_ADC1_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC1_AWD3CR (STM32_ADC1_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC1_DIFSEL (STM32_ADC1_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC1_CALFACT (STM32_ADC1_BASE + STM32_ADC_CALFACT_OFFSET) -# define STM32_ADC1_GCOMP (STM32_ADC1_BASE + STM32_ADC_GCOMP_OFFSET) -#endif - -#if STM32_NADC > 1 -# define STM32_ADC2_ISR (STM32_ADC2_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC2_IER (STM32_ADC2_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC2_CR (STM32_ADC2_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC2_CFGR1 (STM32_ADC2_BASE + STM32_ADC_CFGR1_OFFSET) -# define STM32_ADC2_CFGR2 (STM32_ADC2_BASE + STM32_ADC_CFGR2_OFFSET) -# define STM32_ADC2_SMPR1 (STM32_ADC2_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC2_SMPR2 (STM32_ADC2_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC2_TR1 (STM32_ADC2_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC2_TR2 (STM32_ADC2_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC2_TR3 (STM32_ADC2_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC2_SQR1 (STM32_ADC2_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC2_SQR2 (STM32_ADC2_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC2_SQR3 (STM32_ADC2_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC2_SQR4 (STM32_ADC2_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC2_DR (STM32_ADC2_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC2_JSQR (STM32_ADC2_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC2_OFR1 (STM32_ADC2_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC2_OFR2 (STM32_ADC2_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC2_OFR3 (STM32_ADC2_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC2_OFR4 (STM32_ADC2_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC2_JDR1 (STM32_ADC2_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC2_JDR2 (STM32_ADC2_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC2_JDR3 (STM32_ADC2_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC2_JDR4 (STM32_ADC2_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC2_AWD2CR (STM32_ADC2_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC2_AWD3CR (STM32_ADC2_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC2_DIFSEL (STM32_ADC2_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC2_CALFACT (STM32_ADC2_BASE + STM32_ADC_CALFACT_OFFSET) -# define STM32_ADC2_GCOMP (STM32_ADC2_BASE + STM32_ADC_GCOMP_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC3_ISR (STM32_ADC3_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC3_IER (STM32_ADC3_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC3_CR (STM32_ADC3_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC3_CFGR1 (STM32_ADC3_BASE + STM32_ADC_CFGR1_OFFSET) -# define STM32_ADC3_CFGR2 (STM32_ADC3_BASE + STM32_ADC_CFGR2_OFFSET) -# define STM32_ADC3_SMPR1 (STM32_ADC3_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC3_SMPR2 (STM32_ADC3_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC3_TR1 (STM32_ADC3_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC3_TR2 (STM32_ADC3_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC3_TR3 (STM32_ADC3_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC3_SQR1 (STM32_ADC3_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC3_SQR2 (STM32_ADC3_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC3_SQR3 (STM32_ADC3_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC3_SQR4 (STM32_ADC3_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC3_DR (STM32_ADC3_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC3_JSQR (STM32_ADC3_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC3_OFR1 (STM32_ADC3_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC3_OFR2 (STM32_ADC3_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC3_OFR3 (STM32_ADC3_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC3_OFR4 (STM32_ADC3_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC3_JDR1 (STM32_ADC3_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC3_JDR2 (STM32_ADC3_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC3_JDR3 (STM32_ADC3_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC3_JDR4 (STM32_ADC3_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC3_AWD2CR (STM32_ADC3_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC3_AWD3CR (STM32_ADC3_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC3_DIFSEL (STM32_ADC3_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC3_CALFACT (STM32_ADC3_BASE + STM32_ADC_CALFACT_OFFSET) -# define STM32_ADC3_GCOMP (STM32_ADC3_BASE + STM32_ADC_GCOMP_OFFSET) -#endif - -#if STM32_NADC > 3 -# define STM32_ADC4_ISR (STM32_ADC4_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC4_IER (STM32_ADC4_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC4_CR (STM32_ADC4_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC4_CFGR1 (STM32_ADC4_BASE + STM32_ADC_CFGR1_OFFSET) -# define STM32_ADC4_CFGR2 (STM32_ADC4_BASE + STM32_ADC_CFGR2_OFFSET) -# define STM32_ADC4_SMPR1 (STM32_ADC4_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC4_SMPR2 (STM32_ADC4_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC4_TR1 (STM32_ADC4_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC4_TR2 (STM32_ADC4_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC4_TR3 (STM32_ADC4_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC4_SQR1 (STM32_ADC4_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC4_SQR2 (STM32_ADC4_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC4_SQR3 (STM32_ADC4_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC4_SQR4 (STM32_ADC4_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC4_DR (STM32_ADC4_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC4_JSQR (STM32_ADC4_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC4_OFR1 (STM32_ADC4_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC4_OFR2 (STM32_ADC4_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC4_OFR3 (STM32_ADC4_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC4_OFR4 (STM32_ADC4_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC4_JDR1 (STM32_ADC4_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC4_JDR2 (STM32_ADC4_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC4_JDR3 (STM32_ADC4_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC4_JDR4 (STM32_ADC4_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC4_AWD2CR (STM32_ADC4_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC4_AWD3CR (STM32_ADC4_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC4_DIFSEL (STM32_ADC4_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC4_CALFACT (STM32_ADC4_BASE + STM32_ADC_CALFACT_OFFSET) -# define STM32_ADC4_GCOMP (STM32_ADC4_BASE + STM32_ADC_GCOMP_OFFSET) -#endif - -#if STM32_NADC > 4 -# define STM32_ADC5_ISR (STM32_ADC5_BASE + STM32_ADC_ISR_OFFSET) -# define STM32_ADC5_IER (STM32_ADC5_BASE + STM32_ADC_IER_OFFSET) -# define STM32_ADC5_CR (STM32_ADC5_BASE + STM32_ADC_CR_OFFSET) -# define STM32_ADC5_CFGR1 (STM32_ADC5_BASE + STM32_ADC_CFGR1_OFFSET) -# define STM32_ADC5_CFGR2 (STM32_ADC5_BASE + STM32_ADC_CFGR2_OFFSET) -# define STM32_ADC5_SMPR1 (STM32_ADC5_BASE + STM32_ADC_SMPR1_OFFSET) -# define STM32_ADC5_SMPR2 (STM32_ADC5_BASE + STM32_ADC_SMPR2_OFFSET) -# define STM32_ADC5_TR1 (STM32_ADC5_BASE + STM32_ADC_TR1_OFFSET) -# define STM32_ADC5_TR2 (STM32_ADC5_BASE + STM32_ADC_TR2_OFFSET) -# define STM32_ADC5_TR3 (STM32_ADC5_BASE + STM32_ADC_TR3_OFFSET) -# define STM32_ADC5_SQR1 (STM32_ADC5_BASE + STM32_ADC_SQR1_OFFSET) -# define STM32_ADC5_SQR2 (STM32_ADC5_BASE + STM32_ADC_SQR2_OFFSET) -# define STM32_ADC5_SQR3 (STM32_ADC5_BASE + STM32_ADC_SQR3_OFFSET) -# define STM32_ADC5_SQR4 (STM32_ADC5_BASE + STM32_ADC_SQR4_OFFSET) -# define STM32_ADC5_DR (STM32_ADC5_BASE + STM32_ADC_DR_OFFSET) -# define STM32_ADC5_JSQR (STM32_ADC5_BASE + STM32_ADC_JSQR_OFFSET) -# define STM32_ADC5_OFR1 (STM32_ADC5_BASE + STM32_ADC_OFR1_OFFSET) -# define STM32_ADC5_OFR2 (STM32_ADC5_BASE + STM32_ADC_OFR2_OFFSET) -# define STM32_ADC5_OFR3 (STM32_ADC5_BASE + STM32_ADC_OFR3_OFFSET) -# define STM32_ADC5_OFR4 (STM32_ADC5_BASE + STM32_ADC_OFR4_OFFSET) -# define STM32_ADC5_JDR1 (STM32_ADC5_BASE + STM32_ADC_JDR1_OFFSET) -# define STM32_ADC5_JDR2 (STM32_ADC5_BASE + STM32_ADC_JDR2_OFFSET) -# define STM32_ADC5_JDR3 (STM32_ADC5_BASE + STM32_ADC_JDR3_OFFSET) -# define STM32_ADC5_JDR4 (STM32_ADC5_BASE + STM32_ADC_JDR4_OFFSET) -# define STM32_ADC5_AWD2CR (STM32_ADC5_BASE + STM32_ADC_AWD2CR_OFFSET) -# define STM32_ADC5_AWD3CR (STM32_ADC5_BASE + STM32_ADC_AWD3CR_OFFSET) -# define STM32_ADC5_DIFSEL (STM32_ADC5_BASE + STM32_ADC_DIFSEL_OFFSET) -# define STM32_ADC5_CALFACT (STM32_ADC5_BASE + STM32_ADC_CALFACT_OFFSET) -# define STM32_ADC5_GCOMP (STM32_ADC5_BASE + STM32_ADC_GCOMP_OFFSET) -#endif - -/* Master and Slave ADC Common Registers */ - -#if STM32_NADC > 0 -# define STM32_ADC12_CSR (STM32_ADC12CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC12_CCR (STM32_ADC12CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC12_CDR (STM32_ADC12CMN_BASE + STM32_ADC_CDR_OFFSET) -#endif - -#if STM32_NADC > 2 -# define STM32_ADC345_CSR (STM32_ADC345CMN_BASE + STM32_ADC_CSR_OFFSET) -# define STM32_ADC345_CCR (STM32_ADC345CMN_BASE + STM32_ADC_CCR_OFFSET) -# define STM32_ADC345_CDR (STM32_ADC345CMN_BASE + STM32_ADC_CDR_OFFSET) - -/* Compatibility defines */ - -# define STM32_ADC34_CSR STM32_ADC345_CSR -# define STM32_ADC34_CCR STM32_ADC345_CCR -# define STM32_ADC34_CDR STM32_ADC345_CDR -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* ADC Interrupt and Status Register (ISR), and - * ADC Interrupt Enable Register (IER) - */ - -#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */ -#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */ -#define ADC_INT_EOC (1 << 2) /* Bit 2: End of conversion */ -#define ADC_INT_EOS (1 << 3) /* Bit 3: End of regular sequence flag */ -#define ADC_INT_OVR (1 << 4) /* Bit 4: Overrun */ -#define ADC_INT_JEOC (1 << 5) /* Bit 5: Injected channel end of conversion */ -#define ADC_INT_JEOS (1 << 6) /* Bit 6: Injected channel end of sequence flag */ -#define ADC_INT_AWD1 (1 << 7) /* Bit 7: Analog watchdog 1 flag */ -#define ADC_INT_AWD2 (1 << 8) /* Bit 8: Analog watchdog 2 flag */ -#define ADC_INT_AWD3 (1 << 9) /* Bit 9: Analog watchdog 3 flag */ -#define ADC_INT_JQOVF (1 << 10) /* Bit 10: Injected context queue overflow */ - -/* ADC Control Register (CR) */ - -#define ADC_CR_ADEN (1 << 0) /* Bit 0: ADC enable control */ -#define ADC_CR_ADDIS (1 << 1) /* Bit 1: ADC disable command */ -#define ADC_CR_ADSTART (1 << 2) /* Bit 2: ADC start of regular conversion */ -#define ADC_CR_JADSTART (1 << 3) /* Bit 3: ADC start of injected conversion */ -#define ADC_CR_ADSTP (1 << 4) /* Bit 4: ADC stop of regular conversion command */ -#define ADC_CR_JADSTP (1 << 5) /* Bit 5: ADC stop of injected conversion command */ -#define ADC_CR_ADVREGEN (1 << 28) /* Bit 28: ADC voltage regulator enable */ -#define ADC_CR_DEEPPWD (1 << 29) /* Bit 29: ADC deep power-down enable */ -#define ADC_CR_ADCALDIF (1 << 30) /* Bit 30: Differential mode for calibration */ -#define ADC_CR_ADCAL (1 << 31) /* Bit 31: ADC calibration */ - -/* For compliance with the ADC driver we also define ADVREGEN like - * for previous chips. For new chips ST decided to better describe - * the mechanism behind ADVREGEN bits. - */ - -#define ADC_CR_ADVREGEN_SHIFT (28) -#define ADC_CR_ADVREGEN_MASK (3 << ADC_CR_ADVREGEN_SHIFT) -# define ADC_CR_ADVREGEN_INTER (0 << ADC_CR_ADVREGEN_SHIFT) -# define ADC_CR_ADVREGEN_ENABLED (1 << ADC_CR_ADVREGEN_SHIFT) -# define ADC_CR_ADVREGEN_DISABLED (2 << ADC_CR_ADVREGEN_SHIFT) - -/* ADC configuration register 1 (CFGR1) */ - -#define ADC_CFGR1_DMAEN (1 << 0) /* Bit 0: Direct memory access enable */ -#define ADC_CFGR1_DMACFG (1 << 1) /* Bit 1: Direct memory access configuration */ -#define ADC_CFGR1_RES_SHIFT (3) /* Bits 3-4: Data resolution */ -#define ADC_CFGR1_RES_MASK (0x3 << ADC_CFGR1_RES_SHIFT) -# define ADC_CFGR1_RES_12BIT (0x0 << ADC_CFGR1_RES_SHIFT) /* 12-bit resolution */ -# define ADC_CFGR1_RES_10BIT (0x1 << ADC_CFGR1_RES_SHIFT) /* 10-bit resolution */ -# define ADC_CFGR1_RES_8BIT (0x2 << ADC_CFGR1_RES_SHIFT) /* 8-bit resolution */ -# define ADC_CFGR1_RES_6BIT (0x3 << ADC_CFGR1_RES_SHIFT) /* 6-bit resolution */ -#define ADC_CFGR1_EXTSEL_SHIFT (5) /* Bits 5-9: External trigger selection for regular group */ -#define ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC2 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2CC2 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T4CC4 (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_EXTI11 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T3CC4 (15 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T20CC2 (19 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T20CC3 (20 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC12_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ -# define ADC34_CFGR1_EXTSEL_T3CC1 (0 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2CC3 (1 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T1CC3 (2 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T8CC1 (3 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T3TRGO (4 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_EXTI2 (5 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T4CC1 (6 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T8TRGO (7 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T8TRGO2 (8 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T1TRGO (9 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T1TRGO2 (10 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2TRGO (11 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T4TRGO (12 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T6TRGO (13 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T15TRGO (14 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T2CC1 (15 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20TRGO (16 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20TRGO2 (17 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T20CC1 (18 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG2 (19 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG4 (20 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG1 (21 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG3 (22 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG5 (23 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG6 (24 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG7 (25 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG8 (26 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG9 (27 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_HRT1TRG10 (28 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_LPTIMOUT (29 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_T7TRGO (30 << ADC_CFGR1_EXTSEL_SHIFT) -# define ADC34_CFGR1_EXTSEL_RSVD1 (31 << ADC_CFGR1_EXTSEL_SHIFT) /* 11111: Reserved */ -#define ADC_CFGR1_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ -#define ADC_CFGR1_EXTEN_MASK (0x3 << ADC_CFGR1_EXTEN_SHIFT) -# define ADC_CFGR1_EXTEN_NONE (0x0 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection disabled */ -# define ADC_CFGR1_EXTEN_RISING (0x1 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the rising edge */ -# define ADC_CFGR1_EXTEN_FALLING (0x2 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on the falling edge */ -# define ADC_CFGR1_EXTEN_BOTH (0x3 << ADC_CFGR1_EXTEN_SHIFT) /* Trigger detection on both edges */ -#define ADC_CFGR1_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */ -#define ADC_CFGR1_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */ -#define ADC_CFGR1_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */ -#define ADC_CFGR1_ALIGN (1 << 15) /* Bit 15: Data Alignment */ -#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode for regular channels */ -#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */ -#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT) -# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << ADC_CFGR1_DISCNUM_SHIFT) -# define ADC_CFGR1_DISCNUM_1 (0 << ADC_CFGR1_DISCNUM_SHIFT) /* 1 channel */ -# define ADC_CFGR1_DISCNUM_2 (1 << ADC_CFGR1_DISCNUM_SHIFT) /* 2 channels */ -# define ADC_CFGR1_DISCNUM_3 (2 << ADC_CFGR1_DISCNUM_SHIFT) /* 3 channels */ -# define ADC_CFGR1_DISCNUM_4 (3 << ADC_CFGR1_DISCNUM_SHIFT) /* 4 channels */ -# define ADC_CFGR1_DISCNUM_5 (4 << ADC_CFGR1_DISCNUM_SHIFT) /* 5 channels */ -# define ADC_CFGR1_DISCNUM_6 (5 << ADC_CFGR1_DISCNUM_SHIFT) /* 6 channels */ -# define ADC_CFGR1_DISCNUM_7 (6 << ADC_CFGR1_DISCNUM_SHIFT) /* 7 channels */ -# define ADC_CFGR1_DISCNUM_8 (7 << ADC_CFGR1_DISCNUM_SHIFT) /* 8 channels */ -#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */ -#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */ -#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */ -#define ADC_CFGR1_AWD1EN (1 << 23) /* Bit 23: Analog watchdog enable 1 regular channels */ -#define ADC_CFGR1_JAWD1EN (1 << 24) /* Bit 24: Analog watchdog enable 1 injected channels */ -#define ADC_CFGR1_JAUTO (1 << 25) /* Bit 25: Automatic injected group conversion */ -#define ADC_CFGR1_AWD1CH_SHIFT (26) /* Bits 26-30: Analog watchdog 1 channel select bits */ -#define ADC_CFGR1_AWD1CH_MASK (0x1f << ADC_CFGR1_AWD1CH_SHIFT) -# define ADC_CFGR1_AWD1CH_DISABLED (0 << ADC_CFGR1_AWD1CH_SHIFT) -#define ADC_CFGR1_JQDIS (1 << 31) /* Bit 31: Injected queue disable */ - -/* ADC configuration register 2 (CFGR2) */ - -#define ADC_CFGR2_ROVSE (1 << 0) /* Bit 0: Regular oversampling enable */ -#define ADC_CFGR2_JOVSE (1 << 1) /* Bit 1: Injected oversampling enable */ -#define ADC_CFGR2_OVSR_SHIFT (2) /* Bits 2-4: Oversampling ratio */ -#define ADC_CFGR2_OVSR_MASK (0x7 << ADC_CFGR2_OVSR_SHIFT) -# define ADC_CFGR2_OVSR_2X (0x0 << ADC_CFGR2_OVSR_SHIFT) /* 000: 2x oversampling */ -# define ADC_CFGR2_OVSR_4X (0x1 << ADC_CFGR2_OVSR_SHIFT) /* 001: 4x oversampling */ -# define ADC_CFGR2_OVSR_8X (0x2 << ADC_CFGR2_OVSR_SHIFT) /* 010: 8x oversampling */ -# define ADC_CFGR2_OVSR_16X (0x3 << ADC_CFGR2_OVSR_SHIFT) /* 011: 16x oversampling */ -# define ADC_CFGR2_OVSR_32X (0x4 << ADC_CFGR2_OVSR_SHIFT) /* 100: 32x oversampling */ -# define ADC_CFGR2_OVSR_64X (0x5 << ADC_CFGR2_OVSR_SHIFT) /* 101: 64x oversampling */ -# define ADC_CFGR2_OVSR_128X (0x6 << ADC_CFGR2_OVSR_SHIFT) /* 110: 128x oversampling */ -# define ADC_CFGR2_OVSR_256X (0x7 << ADC_CFGR2_OVSR_SHIFT) /* 111: 256x oversampling */ -#define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ -#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) -# define ADC_CFGR2_OVSS(n) ((n) << ADC_CFGR2_OVSS_SHIFT) -# define ADC_CFGR2_OVSS_NONE (0x0 << ADC_CFGR2_OVSS_SHIFT) /* 0000: No shift */ -# define ADC_CFGR2_OVSS_1_BIT (0x1 << ADC_CFGR2_OVSS_SHIFT) /* 0001: Shift 1 bits */ -# define ADC_CFGR2_OVSS_2_BIT (0x2 << ADC_CFGR2_OVSS_SHIFT) /* 0010: Shift 2 bits */ -# define ADC_CFGR2_OVSS_3_BIT (0x3 << ADC_CFGR2_OVSS_SHIFT) /* 0011: Shift 3 bits */ -# define ADC_CFGR2_OVSS_4_BIT (0x4 << ADC_CFGR2_OVSS_SHIFT) /* 0100: Shift 4 bits */ -# define ADC_CFGR2_OVSS_5_BIT (0x5 << ADC_CFGR2_OVSS_SHIFT) /* 0101: Shift 5 bits */ -# define ADC_CFGR2_OVSS_6_BIT (0x6 << ADC_CFGR2_OVSS_SHIFT) /* 0110: Shift 6 bits */ -# define ADC_CFGR2_OVSS_7_BIT (0x7 << ADC_CFGR2_OVSS_SHIFT) /* 0111: Shift 7 bits */ -# define ADC_CFGR2_OVSS_8_BIT (0x8 << ADC_CFGR2_OVSS_SHIFT) /* 1000: Shift 8 bits */ -#define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered regular oversampling */ -#define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular oversampling mode */ -#define ADC_CFGR2_GCOMP (1 << 16) /* Bit 16: Gain compensation mode */ -#define ADC_CFGR2_SWTRIG (1 << 25) /* Bit 25: Software trigger for sampling time control trigger mode */ -#define ADC_CFGR2_BULB (1 << 26) /* Bit 26: Bulb sampling mode */ -#define ADC_CFGR2_SMPTRIG (1 << 27) /* Bit 27: Sampling time control trigger mode */ - -/* ADC sample time values for use with SMPR1 and SMPR2 bitfields */ - -#define ADC_SMPR_2p5 0x0 /* 000: Sample for 2.5 cycles */ -#define ADC_SMPR_6p5 0x1 /* 001: Sample for 6.5 cycles */ -#define ADC_SMPR_12p5 0x2 /* 010: Sample for 12.5 cycles */ -#define ADC_SMPR_24p5 0x3 /* 011: Sample for 24.5 cycles */ -#define ADC_SMPR_47p5 0x4 /* 100: Sample for 47.5 cycles */ -#define ADC_SMPR_92p5 0x5 /* 101: Sample for 92.5 cycles */ -#define ADC_SMPR_247p5 0x6 /* 110: Sample for 247.5 cycles */ -#define ADC_SMPR_640p5 0x7 /* 111: Sample for 640.5 cycles */ - -/* ADC sample time register 1 (SMPR1) */ - -#define ADC_SMPR1_SMP0_SHIFT (0) /* Bits 0-2: Channel 0 Sample time selection */ -#define ADC_SMPR1_SMP0_MASK (0x7 << ADC_SMPR1_SMP1_SHIFT) -#define ADC_SMPR1_SMP1_SHIFT (3) /* Bits 3-5: Channel 1 Sample time selection */ -#define ADC_SMPR1_SMP1_MASK (0x7 << ADC_SMPR1_SMP1_SHIFT) -#define ADC_SMPR1_SMP2_SHIFT (6) /* Bits 6-8: Channel 2 Sample time selection */ -#define ADC_SMPR1_SMP2_MASK (0x7 << ADC_SMPR1_SMP2_SHIFT) -#define ADC_SMPR1_SMP3_SHIFT (9) /* Bits 9-11: Channel 3 Sample time selection */ -#define ADC_SMPR1_SMP3_MASK (0x7 << ADC_SMPR1_SMP3_SHIFT) -#define ADC_SMPR1_SMP4_SHIFT (12) /* Bits 12-14: Channel 4 Sample time selection */ -#define ADC_SMPR1_SMP4_MASK (0x7 << ADC_SMPR1_SMP4_SHIFT) -#define ADC_SMPR1_SMP5_SHIFT (15) /* Bits 15-17: Channel 5 Sample time selection */ -#define ADC_SMPR1_SMP5_MASK (0x7 << ADC_SMPR1_SMP5_SHIFT) -#define ADC_SMPR1_SMP6_SHIFT (18) /* Bits 18-20: Channel 6 Sample time selection */ -#define ADC_SMPR1_SMP6_MASK (0x7 << ADC_SMPR1_SMP6_SHIFT) -#define ADC_SMPR1_SMP7_SHIFT (21) /* Bits 21-23: Channel 7 Sample time selection */ -#define ADC_SMPR1_SMP7_MASK (0x7 << ADC_SMPR1_SMP7_SHIFT) -#define ADC_SMPR1_SMP8_SHIFT (24) /* Bits 24-26: Channel 8 Sample time selection */ -#define ADC_SMPR1_SMP8_MASK (0x7 << ADC_SMPR1_SMP8_SHIFT) -#define ADC_SMPR1_SMP9_SHIFT (27) /* Bits 27-29: Channel 9 Sample time selection */ -#define ADC_SMPR1_SMP9_MASK (0x7 << ADC_SMPR1_SMP9_SHIFT) -#define ADC_SMPR1_SMPPLUS (1 << 31) /* Bit 31: Addition of one clock cycle to the sampling time */ - -/* ADC sample time register 2 (SMPR2) */ - -#define ADC_SMPR2_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */ -#define ADC_SMPR2_SMP10_MASK (0x7 << ADC_SMPR2_SMP10_SHIFT) -#define ADC_SMPR2_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */ -#define ADC_SMPR2_SMP11_MASK (0x7 << ADC_SMPR2_SMP11_SHIFT) -#define ADC_SMPR2_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */ -#define ADC_SMPR2_SMP12_MASK (0x7 << ADC_SMPR2_SMP12_SHIFT) -#define ADC_SMPR2_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */ -#define ADC_SMPR2_SMP13_MASK (0x7 << ADC_SMPR2_SMP13_SHIFT) -#define ADC_SMPR2_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */ -#define ADC_SMPR2_SMP14_MASK (0x7 << ADC_SMPR2_SMP14_SHIFT) -#define ADC_SMPR2_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */ -#define ADC_SMPR2_SMP15_MASK (0x7 << ADC_SMPR2_SMP15_SHIFT) -#define ADC_SMPR2_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */ -#define ADC_SMPR2_SMP16_MASK (0x7 << ADC_SMPR2_SMP16_SHIFT) -#define ADC_SMPR2_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */ -#define ADC_SMPR2_SMP17_MASK (0x7 << ADC_SMPR2_SMP17_SHIFT) -#define ADC_SMPR2_SMP18_SHIFT (24) /* Bits 24-26: Channel 18 Sample time selection */ -#define ADC_SMPR2_SMP18_MASK (0x7 << ADC_SMPR2_SMP18_SHIFT) - -/* ADC watchdog threshold register 1 (TR1) */ - -#define ADC_TR1_LT_SHIFT (0) /* Bits 0-11: Analog watchdog 1 lower threshold */ -#define ADC_TR1_LT_MASK (0xfff << ADC_TR1_LT_SHIFT) -#define ADC_TR1_AWDFILT_SHIFT (12) /* Bits 12-14: Analog watchdog filtering parameter */ -#define ADC_TR1_AWDFILT_MASK (0x7 << ADC_TR1_AWDFILT_SHIFT) -# define ADC_TR1_AWDFILT(n) (((n) - 1) << ADC_TR1_AWDFILT_SHIFT) -# define ADC_TR1_AWDFILT_NONE (0x0 << ADC_TR1_AWDFILT_SHIFT) /* 000: No filtering */ -# define ADC_TR1_AWDFILT_2 (0x1 << ADC_TR1_AWDFILT_SHIFT) /* 001: Two consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_3 (0x2 << ADC_TR1_AWDFILT_SHIFT) /* 010: Three consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_4 (0x3 << ADC_TR1_AWDFILT_SHIFT) /* 011: Four consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_5 (0x4 << ADC_TR1_AWDFILT_SHIFT) /* 100: Five consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_6 (0x5 << ADC_TR1_AWDFILT_SHIFT) /* 101: Six consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_7 (0x6 << ADC_TR1_AWDFILT_SHIFT) /* 110: Seven consecutive detections generate an AWDx flag or interrupt */ -# define ADC_TR1_AWDFILT_8 (0x7 << ADC_TR1_AWDFILT_SHIFT) /* 111: Eight consecutive detections generate an AWDx flag or interrupt */ -#define ADC_TR1_HT_SHIFT (16) /* Bits 16-27: Analog watchdog 1 higher threshold */ -#define ADC_TR1_HT_MASK (0xfff << ADC_TR1_HT_SHIFT) - -/* ADC watchdog threshold register 2 (TR2) */ - -#define ADC_TR2_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 2 lower threshold */ -#define ADC_TR2_LT_MASK (0xff << ADC_TR2_LT_SHIFT) -#define ADC_TR2_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 2 higher threshold */ -#define ADC_TR2_HT_MASK (0xff << ADC_TR2_HT_SHIFT) - -/* ADC watchdog threshold register 3 (TR3) */ - -#define ADC_TR3_LT_SHIFT (0) /* Bits 0-7: Analog watchdog 3 lower threshold */ -#define ADC_TR3_LT_MASK (0xff << ADC_TR3_LT_SHIFT) -#define ADC_TR3_HT_SHIFT (16) /* Bits 16-23: Analog watchdog 3 higher threshold */ -#define ADC_TR3_HT_MASK (0xff << ADC_TR3_HT_SHIFT) - -/* ADC regular sequence register 1 (SQR1) */ - -#define ADC_SQ_OFFSET (6) /* Offset between SQ bitfields in SQR1..SQR4 */ - -#define ADC_SQR1_L_SHIFT (0) /* Bits 0-3: Regular channel sequence length */ -#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT) -# define ADC_SQR1_L(n) (((n) - 1) << ADC_SQR1_L_SHIFT) -# define ADC_SQR1_L_1 (0x0 << ADC_SQR1_L_SHIFT) /* 1 conversion */ -# define ADC_SQR1_L_2 (0x1 << ADC_SQR1_L_SHIFT) /* 2 conversions */ -# define ADC_SQR1_L_3 (0x2 << ADC_SQR1_L_SHIFT) /* 3 conversions */ -# define ADC_SQR1_L_4 (0x3 << ADC_SQR1_L_SHIFT) /* 4 conversions */ -# define ADC_SQR1_L_5 (0x4 << ADC_SQR1_L_SHIFT) /* 5 conversion */ -# define ADC_SQR1_L_6 (0x5 << ADC_SQR1_L_SHIFT) /* 6 conversions */ -# define ADC_SQR1_L_7 (0x6 << ADC_SQR1_L_SHIFT) /* 7 conversions */ -# define ADC_SQR1_L_8 (0x7 << ADC_SQR1_L_SHIFT) /* 8 conversions */ -# define ADC_SQR1_L_9 (0x8 << ADC_SQR1_L_SHIFT) /* 9 conversion */ -# define ADC_SQR1_L_10 (0x9 << ADC_SQR1_L_SHIFT) /* 10 conversions */ -# define ADC_SQR1_L_11 (0xa << ADC_SQR1_L_SHIFT) /* 11 conversions */ -# define ADC_SQR1_L_12 (0xb << ADC_SQR1_L_SHIFT) /* 12 conversions */ -# define ADC_SQR1_L_13 (0xc << ADC_SQR1_L_SHIFT) /* 13 conversion */ -# define ADC_SQR1_L_14 (0xd << ADC_SQR1_L_SHIFT) /* 14 conversions */ -# define ADC_SQR1_L_15 (0xe << ADC_SQR1_L_SHIFT) /* 15 conversions */ -# define ADC_SQR1_L_16 (0xf << ADC_SQR1_L_SHIFT) /* 16 conversions */ -#define ADC_SQR1_SQ1_SHIFT (6) /* Bits 6-10: 1st conversion in regular sequence */ -#define ADC_SQR1_SQ1_MASK (0x1f << ADC_SQR1_SQ1_SHIFT) -#define ADC_SQR1_SQ2_SHIFT (12) /* Bits 12-16: 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_MASK (0x1f << ADC_SQR1_SQ2_SHIFT) -#define ADC_SQR1_SQ3_SHIFT (18) /* Bits 18-22: 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_MASK (0x1f << ADC_SQR1_SQ3_SHIFT) -#define ADC_SQR1_SQ4_SHIFT (24) /* Bits 24-28: 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_MASK (0x1f << ADC_SQR1_SQ4_SHIFT) -#define ADC_SQR1_RESERVED (0xe0820830) /* Mask of all reserved bits: 4, 5, 11, 17, 23, 29, 30, 31 */ -#define ADC_SQR1_FIRST (1) -#define ADC_SQR1_LAST (4) -#define ADC_SQR1_SQ_OFFSET (1 * ADC_SQ_OFFSET) /* Offset to first SQ bitfield in the register */ - -/* ADC regular sequence register 2 (SQR2) */ - -#define ADC_SQR2_SQ5_SHIFT (0) /* Bits 0-4: 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_MASK (0x1f << ADC_SQR2_SQ5_SHIFT) -#define ADC_SQR2_SQ6_SHIFT (6) /* Bits 6-10: 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_MASK (0x1f << ADC_SQR2_SQ6_SHIFT) -#define ADC_SQR2_SQ7_SHIFT (12) /* Bits 12-16: 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT) -#define ADC_SQR2_SQ8_SHIFT (18) /* Bits 18-22: 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT) -#define ADC_SQR2_SQ9_SHIFT (24) /* Bits 24-28: 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT) -#define ADC_SQR2_RESERVED (0xe0820820) /* Mask of all reserved bits: 5, 11, 17, 23, 29, 30, 31 */ -#define ADC_SQR2_FIRST (5) -#define ADC_SQR2_LAST (9) -#define ADC_SQR2_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ - -/* ADC regular sequence register 3 (SQR3) */ - -#define ADC_SQR3_SQ10_SHIFT (0) /* Bits 0-4: 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_MASK (0x1f << ADC_SQR3_SQ10_SHIFT) -#define ADC_SQR3_SQ11_SHIFT (6) /* Bits 6-10: 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_MASK (0x1f << ADC_SQR3_SQ11_SHIFT) -#define ADC_SQR3_SQ12_SHIFT (12) /* Bits 12-16: 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_MASK (0x1f << ADC_SQR3_SQ12_SHIFT) -#define ADC_SQR3_SQ13_SHIFT (18) /* Bits 18-22: 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_MASK (0x1f << ADC_SQR3_SQ13_SHIFT) -#define ADC_SQR3_SQ14_SHIFT (24) /* Bits 24-28: 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_MASK (0x1f << ADC_SQR3_SQ14_SHIFT) -#define ADC_SQR3_RESERVED (0xe0820820) /* Mask of all reserved bits: 5, 11, 17, 23, 29, 30, 31 */ -#define ADC_SQR3_FIRST (10) -#define ADC_SQR3_LAST (14) -#define ADC_SQR3_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ - -/* ADC regular sequence register 4 (SQR4) */ - -#define ADC_SQR4_SQ15_SHIFT (0) /* Bits 0-4: 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_MASK (0x1f << ADC_SQR4_SQ15_SHIFT) -#define ADC_SQR4_SQ16_SHIFT (6) /* Bits 6-10: 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_MASK (0x1f << ADC_SQR4_SQ16_SHIFT) -#define ADC_SQR4_RESERVED (0xfffff820) /* Mask of all reserved bits: 5, 11-31 */ -#define ADC_SQR4_FIRST (15) -#define ADC_SQR4_LAST (16) -#define ADC_SQR4_SQ_OFFSET (0) /* Offset to first SQ bitfield in the register */ - -/* ADC regular data register (DR) */ - -#define ADC_DR_RDATA_SHIFT (0) /* Bits 0-15: Regular data converted */ -#define ADC_DR_RDATA_MASK (0xffff << ADC_DR_RDATA_SHIFT) - -/* ADC injected sequence register (JSQR) */ - -#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected channel sequence length */ -#define ADC_JSQR_JL_MASK (0x3 << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL(n) (((n) - 1) << ADC_JSQR_JL_SHIFT) -# define ADC_JSQR_JL_1 (0x0 << ADC_JSQR_JL_SHIFT) /* 1 conversion */ -# define ADC_JSQR_JL_2 (0x1 << ADC_JSQR_JL_SHIFT) /* 2 conversions */ -# define ADC_JSQR_JL_3 (0x2 << ADC_JSQR_JL_SHIFT) /* 3 conversions */ -# define ADC_JSQR_JL_4 (0x3 << ADC_JSQR_JL_SHIFT) /* 4 conversions */ -#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-6: External trigger selection for injected group */ -#define ADC_JSQR_JEXTSEL_MASK (0x1f << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T2CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T3CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T20CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T16CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_RSVD1 (28 << ADC_JSQR_JEXTSEL_SHIFT) /* 11100: Reserved */ -# define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC12_JSQR_JEXTSEL_RSVD2 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ -# define ADC34_JSQR_JEXTSEL_T1TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T2TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T4CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T8TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T1CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T6TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T15TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T20CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_HRT1TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_T7TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT) -# define ADC34_JSQR_JEXTSEL_RSVD1 (31 << ADC_JSQR_JEXTSEL_SHIFT) /* 11111: Reserved */ -#define ADC_JSQR_JEXTEN_SHIFT (7) /* Bits 7-8: External trigger enable and polarity selection for injected channels */ -#define ADC_JSQR_JEXTEN_MASK (0x3 << ADC_JSQR_JEXTEN_SHIFT) -# define ADC_JSQR_JEXTEN_NONE (0x0 << ADC_JSQR_JEXTEN_SHIFT) /* 00: Trigger detection disabled */ -# define ADC_JSQR_JEXTEN_RISING (0x1 << ADC_JSQR_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */ -# define ADC_JSQR_JEXTEN_FALLING (0x2 << ADC_JSQR_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */ -# define ADC_JSQR_JEXTEN_BOTH (0x3 << ADC_JSQR_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */ -#define ADC_JSQR_JSQ1_SHIFT (9) /* Bits 9-13: 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT) -# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ2_SHIFT (15) /* Bits 15-19: 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT) -# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ3_SHIFT (21) /* Bits 21-25: 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT) -# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ4_SHIFT (27) /* Bits 27-31: 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_MASK (0x1f << ADC_JSQR_JSQ4_SHIFT) -# define ADC_JSQR_JSQ4(ch) ((ch) << ADC_JSQR_JSQ4_SHIFT) /* Channel number 1..18 */ -#define ADC_JSQR_JSQ_SHIFT (6) /* Shift between JSQx bits */ - -/* ADC offset register 1 thru 4 (OFR1, OFR2, OFR3, OFR4) */ - -#define ADC_OFR_OFFSETY_SHIFT (0) /* Bits 0-11: Data offset y for channel OFFSETY_CH */ -#define ADC_OFR_OFFSETY_MASK (0x0fff << ADC_OFR_OFFSETY_SHIFT) -# define ADC_OFR_OFFSETY(offset) ((offset) << ADC_OFR_OFFSETY_SHIFT) -#define ADC_OFR_OFFSETPOS (1 << 24) /* Bit 24: Positive offset (0=negative, 1=positive) */ -#define ADC_OFR_SATEN (1 << 25) /* Bit 25: Saturation enable */ -#define ADC_OFR_OFFSETY_CH_SHIFT (26) /* Bits 26-30: Channel selection for data offset y */ -#define ADC_OFR_OFFSETY_CH_MASK (31 << ADC_OFR_OFFSETY_CH_SHIFT) -# define ADC_OFR_OFFSETY_CH(ch) ((ch) << ADC_OFR_OFFSETY_CH_SHIFT) -#define ADC_OFR_OFFSETY_EN (1 << 31) /* Bit 31: Offset y enable */ - -/* ADC injected data register 1 and 2 (JDR1, JDR2) */ - -#define ADC_JDR_JDATA_SHIFT (0) -#define ADC_JDR_JDATA_MASK (0xffff << ADC_JDR_JDATA_SHIFT) - -/* ADC analog watchdog 2 configuration register (AWD2CR) */ - -#define ADC_AWD2CR_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_CH_MASK (0x7ffff << ADC_AWD2CR_CH_SHIFT) -# define ADC_AWD2CR_CH(n) (1 << (n)) /* Channel n=0..18 */ - -/* ADC analog watchdog 3 configuration register (AWD3CR) */ - -#define ADC_AWD3CR_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_CH_MASK (0x7ffff << ADC_AWD3CR_CH_SHIFT) -# define ADC_AWD3CR_CH(n) (1 << (n)) /* Channel n=0..18 */ - -/* ADC differential mode selection register (DIFSEL) */ - -#define ADC_DIFSEL_CH_SHIFT (0) /* Bits 0-18: Analog watchdog 2 channel selection */ -#define ADC_DIFSEL_CH_MASK (0x7ffff << ADC_DIFSEL_CH_SHIFT) -# define ADC_DIFSEL_CH(n) (1 << (n)) /* Channel n=0..18 */ - -/* ADC calibration factors register (CALFACT) */ - -#define ADC_CALFACT_S_SHIFT (0) /* Bits 0-6: Calibration factors in single-ended mode */ -#define ADC_CALFACT_S_MASK (0x7f << ADC_CALFACT_S_SHIFT) -#define ADC_CALFACT_D_SHIFT (16) /* Bits 16-22: Calibration factors in differential mode */ -#define ADC_CALFACT_D_MASK (0x7f << ADC_CALFACT_D_SHIFT) - -/* ADC gain compensation register (GCOMP) */ - -#define ADC_GCOMP_SHIFT (0) /* Bits 0-13: Gain compensation coefficient */ -#define ADC_GCOMP_MASK (0x3fff << ADC_GCOMP_SHIFT) - -/* ADC12, ADC345 - Common status register (CSR) */ - -#define ADC_CSR_ADRDY_MST (1 << 0) /* Bit 0: Master ADC ready */ -#define ADC_CSR_EOSMP_MST (1 << 1) /* Bit 1: End of Sampling phase flag (master ADC) */ -#define ADC_CSR_EOC_MST (1 << 2) /* Bit 2: End of regular conversion (master ADC) */ -#define ADC_CSR_EOS_MST (1 << 3) /* Bit 3: End of regular sequence flag (master ADC) */ -#define ADC_CSR_OVR_MST (1 << 4) /* Bit 4: Overrun flag (master ADC) */ -#define ADC_CSR_JEOC_MST (1 << 5) /* Bit 5: End of injected conversion flag (master ADC) */ -#define ADC_CSR_JEOS_MST (1 << 6) /* Bit 6: End of injected sequence flag (master ADC) */ -#define ADC_CSR_AWD1_MST (1 << 7) /* Bit 7: Analog watchdog 1 flag (master ADC) */ -#define ADC_CSR_AWD2_MST (1 << 8) /* Bit 8: Analog watchdog 2 flag (master ADC) */ -#define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ -#define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ -#define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ -#define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ -#define ADC_CSR_EOS_SLV (1 << 19) /* Bit 19: End of regular sequence flag (slave ADC) */ -#define ADC_CSR_OVR_SLV (1 << 20) /* Bit 20: Overrun flag (slave ADC) */ -#define ADC_CSR_JEOC_SLV (1 << 21) /* Bit 21: End of injected conversion flag (slave ADC) */ -#define ADC_CSR_JEOS_SLV (1 << 22) /* Bit 22: End of injected sequence flag (slave ADC) */ -#define ADC_CSR_AWD1_SLV (1 << 23) /* Bit 23: Analog watchdog 1 flag (slave ADC) */ -#define ADC_CSR_AWD2_SLV (1 << 24) /* Bit 24: Analog watchdog 2 flag (slave ADC) */ -#define ADC_CSR_AWD3_SLV (1 << 25) /* Bit 25: Analog watchdog 3 flag (slave ADC) */ -#define ADC_CSR_JQOVF_SLV (1 << 26) /* Bit 26: Injected Context Queue Overflow flag (slave ADC) */ - -/* ADC12, ADC345 - Common control register (CCR) */ - -#define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ -#define ADC_CCR_DUAL_MASK (0x1f << ADC_CCR_DUAL_SHIFT) -# define ADC_CCR_DUAL_IND (0x0 << ADC_CCR_DUAL_SHIFT) /* 00000: Independent mode */ -# define ADC_CCR_DUAL_DUAL (0x1 << ADC_CCR_DUAL_SHIFT) /* 00001: Dual mode, master/slave ADCs together */ -# define ADC_CCR_DUAL_SIMINJ (0x1 << ADC_CCR_DUAL_SHIFT) /* 00001: Combined regular sim. + injected sim. */ -# define ADC_CCR_DUAL_SIMALT (0x2 << ADC_CCR_DUAL_SHIFT) /* 00010: Combined regular sim. + alternate trigger */ -# define ADC_CCR_DUAL_INTINJ (0x3 << ADC_CCR_DUAL_SHIFT) /* 00011: Combined interl. mode + injected sim. */ -# define ADC_CCR_DUAL_INJECTED (0x5 << ADC_CCR_DUAL_SHIFT) /* 00101: Injected simultaneous mode only */ -# define ADC_CCR_DUAL_SIM (0x6 << ADC_CCR_DUAL_SHIFT) /* 00110: Regular simultaneous mode only */ -# define ADC_CCR_DUAL_INTERLEAVE (0x7 << ADC_CCR_DUAL_SHIFT) /* 00111: Interleaved mode only */ -# define ADC_CCR_DUAL_ALT (0x9 << ADC_CCR_DUAL_SHIFT) /* 01001: Alternate trigger mode only */ -#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */ -#define ADC_CCR_DELAY_MASK (0xf << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */ -# define ADC_CCR_DELAY(n) (((n) - 1) << ADC_CCR_DELAY_SHIFT) -#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */ -#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */ -#define ADC_CCR_MDMA_MASK (0x3 << ADC_CCR_MDMA_SHIFT) -# define ADC_CCR_MDMA_DISABLED (0x0 << ADC_CCR_MDMA_SHIFT) /* MDMA mode disabled */ -# define ADC_CCR_MDMA_10_12 (0x2 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (12 / 10-bit) */ -# define ADC_CCR_MDMA_6_8 (0x3 << ADC_CCR_MDMA_SHIFT) /* MDMA mode enabled (8 / 6-bit) */ -#define ADC_CCR_CKMODE_SHIFT (16) /* Bits 16-17: ADC clock mode */ -#define ADC_CCR_CKMODE_MASK (0x3 << ADC_CCR_CKMODE_SHIFT) -# define ADC_CCR_CKMODE_ASYNCH (0x0 << ADC_CCR_CKMODE_SHIFT) /* Asynchronous clock mode */ -# define ADC_CCR_CKMODE_SYNCH_DIV1 (0x1 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 1 */ -# define ADC_CCR_CKMODE_SYNCH_DIV2 (0x2 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 2 */ -# define ADC_CCR_CKMODE_SYNCH_DIV4 (0x3 << ADC_CCR_CKMODE_SHIFT) /* Synchronous clock mode divided by 4 */ -#define ADC_CCR_PRESC_SHIFT (18) /* Bits 18-21: ADC prescaler */ -#define ADC_CCR_PRESC_MASK (0xf << ADC_CCR_PRESC_SHIFT) -# define ADC_CCR_PRESC_1 (0x0 << ADC_CCR_PRESC_SHIFT) /* 0000: Input ADC clock not divided */ -# define ADC_CCR_PRESC_2 (0x1 << ADC_CCR_PRESC_SHIFT) /* 0001: Input ADC clock divided by 2 */ -# define ADC_CCR_PRESC_4 (0x2 << ADC_CCR_PRESC_SHIFT) /* 0010: Input ADC clock divided by 4 */ -# define ADC_CCR_PRESC_6 (0x3 << ADC_CCR_PRESC_SHIFT) /* 0011: Input ADC clock divided by 6 */ -# define ADC_CCR_PRESC_8 (0x4 << ADC_CCR_PRESC_SHIFT) /* 0100: Input ADC clock divided by 8 */ -# define ADC_CCR_PRESC_10 (0x5 << ADC_CCR_PRESC_SHIFT) /* 0101: Input ADC clock divided by 10 */ -# define ADC_CCR_PRESC_12 (0x6 << ADC_CCR_PRESC_SHIFT) /* 0110: Input ADC clock divided by 12 */ -# define ADC_CCR_PRESC_16 (0x7 << ADC_CCR_PRESC_SHIFT) /* 0111: Input ADC clock divided by 16 */ -# define ADC_CCR_PRESC_32 (0x8 << ADC_CCR_PRESC_SHIFT) /* 1000: Input ADC clock divided by 32 */ -# define ADC_CCR_PRESC_64 (0x9 << ADC_CCR_PRESC_SHIFT) /* 1001: Input ADC clock divided by 64 */ -# define ADC_CCR_PRESC_128 (0xa << ADC_CCR_PRESC_SHIFT) /* 1010: Input ADC clock divided by 128 */ -# define ADC_CCR_PRESC_256 (0xb << ADC_CCR_PRESC_SHIFT) /* 1011: Input ADC clock divided by 256 */ -#define ADC_CCR_VREFEN (1 << 22) /* Bit 22: VREFINT enable */ -#define ADC_CCR_TSEN (1 << 23) /* Bit 23: Temperature sensor enable */ -#define ADC_CCR_VBATEN (1 << 24) /* Bit 24: VBAT enable */ - -/* Common regular data register for dual mode */ - -#define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the Master ADC */ -#define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) -#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */ -#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_bkp.h b/arch/arm/src/stm32/hardware/stm32_bkp.h deleted file mode 100644 index a06ed4085dc81..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_bkp.h +++ /dev/null @@ -1,177 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_bkp.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define CONFIG_STM32_NBKP_BYTES 84 -# define CONFIG_STM32_NBKP_REGS 42 -#else -# define CONFIG_STM32_NBKP_BYTES 20 -# define CONFIG_STM32_NBKP_REGS 10 -#endif - -/* Register Offsets *********************************************************/ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR_OFFSET(n) ((n) > 10 ? 0x0040+4*((n)-10) : 0x0004+4*(n)) -#else -# define STM32_BKP_DR_OFFSET(n) (0x0004+4*(n)) -#endif - -#define STM32_BKP_DR1_OFFSET 0x0004 /* Backup data register 1 */ -#define STM32_BKP_DR2_OFFSET 0x0008 /* Backup data register 2 */ -#define STM32_BKP_DR3_OFFSET 0x000c /* Backup data register 3 */ -#define STM32_BKP_DR4_OFFSET 0x0010 /* Backup data register 4 */ -#define STM32_BKP_DR5_OFFSET 0x0014 /* Backup data register 5 */ -#define STM32_BKP_DR6_OFFSET 0x0018 /* Backup data register 6 */ -#define STM32_BKP_DR7_OFFSET 0x001c /* Backup data register 7 */ -#define STM32_BKP_DR8_OFFSET 0x0020 /* Backup data register 8 */ -#define STM32_BKP_DR9_OFFSET 0x0024 /* Backup data register 9 */ -#define STM32_BKP_DR10_OFFSET 0x0028 /* Backup data register 10 */ - -#define STM32_BKP_RTCCR_OFFSET 0x002c /* RTC clock calibration register */ -#define STM32_BKP_CR_OFFSET 0x0030 /* Backup control register */ -#define STM32_BKP_CSR_OFFSET 0x0034 /* Backup control/status register */ - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11_OFFSET 0x0040 /* Backup data register 11 */ -# define STM32_BKP_DR12_OFFSET 0x0044 /* Backup data register 12 */ -# define STM32_BKP_DR13_OFFSET 0x0048 /* Backup data register 13 */ -# define STM32_BKP_DR14_OFFSET 0x004c /* Backup data register 14 */ -# define STM32_BKP_DR15_OFFSET 0x0050 /* Backup data register 15 */ -# define STM32_BKP_DR16_OFFSET 0x0054 /* Backup data register 16 */ -# define STM32_BKP_DR17_OFFSET 0x0058 /* Backup data register 17 */ -# define STM32_BKP_DR18_OFFSET 0x005c /* Backup data register 18 */ -# define STM32_BKP_DR19_OFFSET 0x0060 /* Backup data register 19 */ -# define STM32_BKP_DR20_OFFSET 0x0064 /* Backup data register 20 */ -# define STM32_BKP_DR21_OFFSET 0x0068 /* Backup data register 21 */ -# define STM32_BKP_DR22_OFFSET 0x006c /* Backup data register 22 */ -# define STM32_BKP_DR23_OFFSET 0x0070 /* Backup data register 23 */ -# define STM32_BKP_DR24_OFFSET 0x0074 /* Backup data register 24 */ -# define STM32_BKP_DR25_OFFSET 0x0078 /* Backup data register 25 */ -# define STM32_BKP_DR26_OFFSET 0x007c /* Backup data register 26 */ -# define STM32_BKP_DR27_OFFSET 0x0080 /* Backup data register 27 */ -# define STM32_BKP_DR28_OFFSET 0x0084 /* Backup data register 28 */ -# define STM32_BKP_DR29_OFFSET 0x0088 /* Backup data register 29 */ -# define STM32_BKP_DR30_OFFSET 0x008c /* Backup data register 30 */ -# define STM32_BKP_DR31_OFFSET 0x0090 /* Backup data register 31 */ -# define STM32_BKP_DR32_OFFSET 0x0094 /* Backup data register 32 */ -# define STM32_BKP_DR33_OFFSET 0x0098 /* Backup data register 33 */ -# define STM32_BKP_DR34_OFFSET 0x009c /* Backup data register 34 */ -# define STM32_BKP_DR35_OFFSET 0x00a0 /* Backup data register 35 */ -# define STM32_BKP_DR36_OFFSET 0x00a4 /* Backup data register 36 */ -# define STM32_BKP_DR37_OFFSET 0x00a8 /* Backup data register 37 */ -# define STM32_BKP_DR38_OFFSET 0x00ac /* Backup data register 38 */ -# define STM32_BKP_DR39_OFFSET 0x00b0 /* Backup data register 39 */ -# define STM32_BKP_DR40_OFFSET 0x00b4 /* Backup data register 40 */ -# define STM32_BKP_DR41_OFFSET 0x00b8 /* Backup data register 41 */ -# define STM32_BKP_DR42_OFFSET 0x00bc /* Backup data register 42 */ -#endif - -/* Register Addresses *******************************************************/ - -#define STM32_BKP_RTCCR (STM32_BKP_BASE+STM32_BKP_RTCCR_OFFSET) -#define STM32_BKP_CR (STM32_BKP_BASE+STM32_BKP_CR_OFFSET) -#define STM32_BKP_CSR (STM32_BKP_BASE+STM32_BKP_CSR_OFFSET) - -#define STM32_BKP_DR(n) (STM32_BKP_BASE+STM32_BKP_DR_OFFSET(n)) -#define STM32_BKP_DR1 (STM32_BKP_BASE+STM32_BKP_DR1_OFFSET) -#define STM32_BKP_DR2 (STM32_BKP_BASE+STM32_BKP_DR2_OFFSET) -#define STM32_BKP_DR3 (STM32_BKP_BASE+STM32_BKP_DR3_OFFSET) -#define STM32_BKP_DR4 (STM32_BKP_BASE+STM32_BKP_DR4_OFFSET) -#define STM32_BKP_DR5 (STM32_BKP_BASE+STM32_BKP_DR5_OFFSET) -#define STM32_BKP_DR6 (STM32_BKP_BASE+STM32_BKP_DR6_OFFSET) -#define STM32_BKP_DR7 (STM32_BKP_BASE+STM32_BKP_DR7_OFFSET) -#define STM32_BKP_DR8 (STM32_BKP_BASE+STM32_BKP_DR8_OFFSET) -#define STM32_BKP_DR9 (STM32_BKP_BASE+STM32_BKP_DR9_OFFSET) -#define STM32_BKP_DR10 (STM32_BKP_BASE+STM32_BKP_DR10_OFFSET) - -#if defined(CONFIG_STM32_HIGHDENSITY) || defined(CONFIG_STM32_CONNECTIVITYLINE) -# define STM32_BKP_DR11 (STM32_BKP_BASE+STM32_BKP_DR11_OFFSET) -# define STM32_BKP_DR12 (STM32_BKP_BASE+STM32_BKP_DR12_OFFSET) -# define STM32_BKP_DR13 (STM32_BKP_BASE+STM32_BKP_DR13_OFFSET) -# define STM32_BKP_DR14 (STM32_BKP_BASE+STM32_BKP_DR14_OFFSET) -# define STM32_BKP_DR15 (STM32_BKP_BASE+STM32_BKP_DR15_OFFSET) -# define STM32_BKP_DR16 (STM32_BKP_BASE+STM32_BKP_DR16_OFFSET) -# define STM32_BKP_DR17 (STM32_BKP_BASE+STM32_BKP_DR17_OFFSET) -# define STM32_BKP_DR18 (STM32_BKP_BASE+STM32_BKP_DR18_OFFSET) -# define STM32_BKP_DR19 (STM32_BKP_BASE+STM32_BKP_DR19_OFFSET) -# define STM32_BKP_DR20 (STM32_BKP_BASE+STM32_BKP_DR20_OFFSET) -# define STM32_BKP_DR21 (STM32_BKP_BASE+STM32_BKP_DR21_OFFSET) -# define STM32_BKP_DR22 (STM32_BKP_BASE+STM32_BKP_DR22_OFFSET) -# define STM32_BKP_DR23 (STM32_BKP_BASE+STM32_BKP_DR23_OFFSET) -# define STM32_BKP_DR24 (STM32_BKP_BASE+STM32_BKP_DR24_OFFSET) -# define STM32_BKP_DR25 (STM32_BKP_BASE+STM32_BKP_DR25_OFFSET) -# define STM32_BKP_DR26 (STM32_BKP_BASE+STM32_BKP_DR26_OFFSET) -# define STM32_BKP_DR27 (STM32_BKP_BASE+STM32_BKP_DR27_OFFSET) -# define STM32_BKP_DR28 (STM32_BKP_BASE+STM32_BKP_DR28_OFFSET) -# define STM32_BKP_DR29 (STM32_BKP_BASE+STM32_BKP_DR29_OFFSET) -# define STM32_BKP_DR30 (STM32_BKP_BASE+STM32_BKP_DR30_OFFSET) -# define STM32_BKP_DR31 (STM32_BKP_BASE+STM32_BKP_DR31_OFFSET) -# define STM32_BKP_DR32 (STM32_BKP_BASE+STM32_BKP_DR32_OFFSET) -# define STM32_BKP_DR33 (STM32_BKP_BASE+STM32_BKP_DR33_OFFSET) -# define STM32_BKP_DR34 (STM32_BKP_BASE+STM32_BKP_DR34_OFFSET) -# define STM32_BKP_DR35 (STM32_BKP_BASE+STM32_BKP_DR35_OFFSET) -# define STM32_BKP_DR36 (STM32_BKP_BASE+STM32_BKP_DR36_OFFSET) -# define STM32_BKP_DR37 (STM32_BKP_BASE+STM32_BKP_DR37_OFFSET) -# define STM32_BKP_DR38 (STM32_BKP_BASE+STM32_BKP_DR38_OFFSET) -# define STM32_BKP_DR39 (STM32_BKP_BASE+STM32_BKP_DR39_OFFSET) -# define STM32_BKP_DR40 (STM32_BKP_BASE+STM32_BKP_DR40_OFFSET) -# define STM32_BKP_DR41 (STM32_BKP_BASE+STM32_BKP_DR41_OFFSET) -# define STM32_BKP_DR42 (STM32_BKP_BASE+STM32_BKP_DR42_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* RTC clock calibration register */ - -#define BKP_RTCCR_CAL_SHIFT (0) /* Bits 6-0: Calibration value */ -#define BKP_RTCCR_CAL_MASK (0x7f << BKP_RTCCR_CAL_SHIFT) -#define BKP_RTCCR_CCO (1 << 7) /* Bit 7: Calibration Clock Output */ -#define BKP_RTCCR_ASOE (1 << 8) /* Bit 8: Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS (1 << 9) /* Bit 9: Alarm or Second Output Selection */ - -/* Backup control register */ - -#define BKP_CR_TPE (1 << 0) /* Bit 0: TAMPER pin enable */ -#define BKP_CR_TPAL (1 << 1) /* Bit 1: TAMPER pin active level */ - -/* Backup control/status register */ - -#define BKP_CSR_CTE (1 << 0) /* Bit 0: Clear Tamper event */ -#define BKP_CSR_CTI (1 << 1) /* Bit 1: Clear Tamper Interrupt */ -#define BKP_CSR_TPIE (1 << 2) /* Bit 2: TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF (1 << 8) /* Bit 8: Tamper Event Flag */ -#define BKP_CSR_TIF (1 << 9) /* Bit 9: Tamper Interrupt Flag */ - -/* Backup data register */ - -#define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ -#define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/stm32/hardware/stm32_dac_v1.h deleted file mode 100644 index 669c27af662a2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dac_v1.h +++ /dev/null @@ -1,315 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* This is implementation for STM32 DAC IPv1 - F1, F2, F3, F4, F7, L1, L4 */ - -#define HAVE_IP_DAC_M3M4_V1 -#undef HAVE_IP_DAC_M3M4_V2 /* No DAC IPv2 */ - -/* Register Offsets *********************************************************/ - -#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NDAC > 0 -/* DAC1 */ - -# define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) -# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) -# define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) -# define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) - -#endif - -#if STM32_NDAC > 2 -/* DAC2 */ - -# define STM32_DAC2_CR (STM32_DAC2_BASE + STM32_DAC_CR_OFFSET) -# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE + STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE + STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE + STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE + STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE + STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE + STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE + STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE + STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE + STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE + STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC2_DOR1 (STM32_DAC2_BASE + STM32_DAC_DOR1_OFFSET) -# define STM32_DAC2_DOR2 (STM32_DAC2_BASE + STM32_DAC_DOR2_OFFSET) -# define STM32_DAC2_SR (STM32_DAC2_BASE + STM32_DAC_SR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* DAC control register */ - -/* These definitions may be used for 16-bit values of either channel */ - -#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel enable */ -#define DAC_CR_BOFF (1 << 1) /* Bit 1: 1=DAC channel output buffer disable */ -#define DAC_CR_BOFF_EN (0 << 1) /* Bit 1: 0=DAC channel output buffer enable */ -#define DAC_CR_TEN (1 << 2) /* Bit 2: DAC channel trigger enable */ -#define DAC_CR_TSEL_SHIFT (3) /* Bits 3-5: DAC channel trigger selection */ -#define DAC_CR_TSEL_MASK (7 << DAC_CR_TSEL_SHIFT) -# define DAC_CR_TSEL_TIM6 (0 << DAC_CR_TSEL_SHIFT) /* Timer 6 TRGO event */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL_TIM3 (1 << DAC_CR_TSEL_SHIFT) /* Timer 3 TRGO event */ -#else -# define DAC_CR_TSEL_TIM8 (1 << DAC_CR_TSEL_SHIFT) /* Timer 8 TRGO event */ -#endif -# define DAC_CR_TSEL_TIM7 (2 << DAC_CR_TSEL_SHIFT) /* Timer 7 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL_TIM15 (3 << DAC_CR_TSEL_SHIFT) /* Timer 15 TRGO event, or */ -# define DAC_CR_TSEL_HRT1TRG1 (3 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG1 event */ -#else -# define DAC_CR_TSEL_TIM5 (3 << DAC_CR_TSEL_SHIFT) /* Timer 5 TRGO event */ -#endif -# define DAC_CR_TSEL_TIM2 (4 << DAC_CR_TSEL_SHIFT) /* Timer 2 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL_HRT1TRG2 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG2 event, or */ -# define DAC_CR_TSEL_HRT1TRG3 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG3 event */ -#else -# define DAC_CR_TSEL_TIM4 (5 << DAC_CR_TSEL_SHIFT) /* Timer 4 TRGO event */ -#endif -# define DAC_CR_TSEL_EXT9 (6 << DAC_CR_TSEL_SHIFT) /* External line9 */ -# define DAC_CR_TSEL_SW (7 << DAC_CR_TSEL_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation */ -#define DAC_CR_WAVE_MASK (3 << DAC_CR_WAVE_SHIFT) -# define DAC_CR_WAVE_DISABLED (0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE_NOISE (1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE_TRIANGLE (2 << DAC_CR_WAVE_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel mask/amplitude selector */ -#define DAC_CR_MAMP_MASK (15 << DAC_CR_MAMP_SHIFT) -# define DAC_CR_MAMP_AMP1 (0 << DAC_CR_MAMP_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP_AMP3 (1 << DAC_CR_MAMP_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP_AMP7 (2 << DAC_CR_MAMP_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP_AMP15 (3 << DAC_CR_MAMP_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP_AMP31 (4 << DAC_CR_MAMP_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP_AMP63 (5 << DAC_CR_MAMP_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP_AMP127 (6 << DAC_CR_MAMP_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP_AMP255 (7 << DAC_CR_MAMP_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP_AMP511 (8 << DAC_CR_MAMP_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP_AMP1023 (9 << DAC_CR_MAMP_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP_AMP2047 (10 << DAC_CR_MAMP_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP_AMP4095 (11 << DAC_CR_MAMP_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel DMA enable */ -#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel DMA Underrun Interrupt enable */ - -/* These definitions may be used with the full, 32-bit register */ - -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ -#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */ -#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */ -#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT) -# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */ -#else -# define DAC_CR_TSEL1_TIM8 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 8 TRGO event */ -#endif -# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */ -# define DAC_CR_TSEL1_HRT1TRG1 (3 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG1 event (DAC1 only) */ -#else -# define DAC_CR_TSEL1_TIM5 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 5 TRGO event */ -#endif -# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL1_HRT1TRG2 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG2 event (DAC1), or */ -# define DAC_CR_TSEL1_HRT1TRG3 (5 << DAC_CR_TSEL1_SHIFT) /* HRTIM1 DACTRG3 event (DAC2) */ -#else -# define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */ -#endif -# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */ -# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */ -#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT) -# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ -#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT) -# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */ - -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ -#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */ -#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */ -#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT) -# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL2_TIM3 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 3 TRGO event */ -#else -# define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */ -#endif -# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL2_TIM15 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 15 TRGO event, or */ -# define DAC_CR_TSEL2_HRT1TRG1 (3 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG1 event */ -#else -# define DAC_CR_TSEL2_TIM5 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 5 TRGO event */ -#endif -# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */ -#if defined(CONFIG_STM32_STM32F33XX) -# define DAC_CR_TSEL2_HRT1TRG2 (5 << DAC_CR_TSEL2_SHIFT) /* HRTIM1 DACTRG2 event */ -#else -# define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */ -#endif -# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */ -# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */ -#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */ -#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT) -# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ -#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */ -#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT) -# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */ -# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */ -# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */ -# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */ -# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */ -# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */ -# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */ -# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */ -# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */ -# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */ -# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */ -# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */ -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ - -/* DAC software trigger register */ - -#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1)) -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ - -/* DAC channel 1/2 12-bit right-aligned data holding register */ - -#define DAC_DHR12R_MASK (0x0fff) - -/* DAC channel 1/2 12-bit left aligned data holding register */ - -#define DAC_DHR12L_MASK (0xfff0) - -/* DAC channel 1/2 8-bit right aligned data holding register */ - -#define DAC_DHR8R_MASK (0x00ff) - -/* Dual DAC 12-bit right-aligned data holding register */ - -#define DAC_DHR12RD_DACC_SHIFT(n) (((n)-1) << 4) -#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) - -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) - -/* Dual DAC 12-bit left-aligned data holding register */ - -#define DAC_DHR12LD_DACC_SHIFT(n) ((((n)-1) << 4) + 4) -#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) - -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) - -/* DUAL DAC 8-bit right aligned data holding register */ - -#define DAC_DHR8RD_DACC_SHIFT(n) (((n)-1) << 3) -#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) - -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) - -/* DAC channel 1/2 data output register */ - -#define DAC_DOR_MASK (0x0fff) - -/* DAC status register */ - -#define DAC_SR_DMAUDR(n) (1 << ((((n)-1) << 4) + 13)) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/stm32/hardware/stm32_dma.h deleted file mode 100644 index d1caacc4ea678..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ /dev/null @@ -1,55 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* Include the correct DMA register definitions for - * selected STM32 DMA IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 - * - STM32 DMA IP version 2 - F2, F4, F7, H7 - */ - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) && defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# error Only one STM32 DMA IP version must be selected -#endif - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ - defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ - defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ - defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) -# include "stm32_dma_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) -# include "stm32_dma_v2.h" -#else -# error "STM32 DMA IP version not specified" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma2d.h b/arch/arm/src/stm32/hardware/stm32_dma2d.h deleted file mode 100644 index 5f885095e2eaa..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma2d.h +++ /dev/null @@ -1,237 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma2d.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "hardware/stm32_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_DMA2D_NCLUT 256 /* Number of entries in the CLUT */ - -/* DMA2D Register Offsets ***************************************************/ - -#define STM32_DMA2D_CR_OFFSET 0x0000 /* DMA2D Control Register */ -#define STM32_DMA2D_ISR_OFFSET 0x0004 /* DMA2D Interrupt Status Register */ -#define STM32_DMA2D_IFCR_OFFSET 0x0008 /* DMA2D Interrupt Flag Clear Register */ -#define STM32_DMA2D_FGMAR_OFFSET 0x000c /* DMA2D Foreground Memory Address Register */ -#define STM32_DMA2D_FGOR_OFFSET 0x0010 /* DMA2D Foreground Offset Register */ -#define STM32_DMA2D_BGMAR_OFFSET 0x0014 /* DMA2D Background Memory Address Register */ -#define STM32_DMA2D_BGOR_OFFSET 0x0018 /* DMA2D Background Offset Register */ -#define STM32_DMA2D_FGPFCCR_OFFSET 0x001c /* DMA2D Foreground PFC Control Register */ -#define STM32_DMA2D_FGCOLR_OFFSET 0x0020 /* DMA2D Foreground Color Register */ -#define STM32_DMA2D_BGPFCCR_OFFSET 0x0024 /* DMA2D Background PFC Control Register */ -#define STM32_DMA2D_BGCOLR_OFFSET 0x0028 /* DMA2D Background Color Register */ -#define STM32_DMA2D_FGCMAR_OFFSET 0x002c /* DMA2D Foreground CLUT Memory Address Register */ -#define STM32_DMA2D_BGCMAR_OFFSET 0x0030 /* DMA2D Background CLUT Memory Address Register */ -#define STM32_DMA2D_OPFCCR_OFFSET 0x0034 /* DMA2D Output PFC Control Register */ -#define STM32_DMA2D_OCOLR_OFFSET 0x0038 /* DMA2D Output Color Register */ -#define STM32_DMA2D_OMAR_OFFSET 0x003c /* DMA2D Output Memory Address Register */ -#define STM32_DMA2D_OOR_OFFSET 0x0040 /* DMA2D Output Offset Register */ -#define STM32_DMA2D_NLR_OFFSET 0x0044 /* DMA2D Number Of Line Register */ -#define STM32_DMA2D_LWR_OFFSET 0x0048 /* DMA2D Line Watermark Register */ -#define STM32_DMA2D_AMTCR_OFFSET 0x004c /* DMA2D AHB Master Time Configuration Register */ - -/* DMA2D Register Addresses *************************************************/ - -#define STM32_DMA2D_CR (STM32_DMA2D_BASE + STM32_DMA2D_CR_OFFSET) -#define STM32_DMA2D_ISR (STM32_DMA2D_BASE + STM32_DMA2D_ISR_OFFSET) -#define STM32_DMA2D_IFCR (STM32_DMA2D_BASE + STM32_DMA2D_IFCR_OFFSET) -#define STM32_DMA2D_FGMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGMAR_OFFSET) -#define STM32_DMA2D_FGOR (STM32_DMA2D_BASE + STM32_DMA2D_FGOR_OFFSET) -#define STM32_DMA2D_BGMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGMAR_OFFSET) -#define STM32_DMA2D_BGOR (STM32_DMA2D_BASE + STM32_DMA2D_BGOR_OFFSET) -#define STM32_DMA2D_FGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_FGPFCCR_OFFSET) -#define STM32_DMA2D_FGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_FGCOLR_OFFSET) -#define STM32_DMA2D_BGPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_BGPFCCR_OFFSET) -#define STM32_DMA2D_BGCOLR (STM32_DMA2D_BASE + STM32_DMA2D_BGCOLR_OFFSET) -#define STM32_DMA2D_FGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_FGCMAR_OFFSET) -#define STM32_DMA2D_BGCMAR (STM32_DMA2D_BASE + STM32_DMA2D_BGCMAR_OFFSET) -#define STM32_DMA2D_OPFCCR (STM32_DMA2D_BASE + STM32_DMA2D_OPFCCR_OFFSET) -#define STM32_DMA2D_OCOLR (STM32_DMA2D_BASE + STM32_DMA2D_OCOLR_OFFSET) -#define STM32_DMA2D_OMAR (STM32_DMA2D_BASE + STM32_DMA2D_OMAR_OFFSET) -#define STM32_DMA2D_OOR (STM32_DMA2D_BASE + STM32_DMA2D_OOR_OFFSET) -#define STM32_DMA2D_NLR (STM32_DMA2D_BASE + STM32_DMA2D_NLR_OFFSET) -#define STM32_DMA2D_LWR (STM32_DMA2D_BASE + STM32_DMA2D_LWR_OFFSET) - -/* DMA2D Register Bit Definitions *******************************************/ - -/* DMA2D Control Register */ - -#define DMA2D_CR_START (1 << 0) /* Start Bit */ -#define DMA2D_CR_SUSP (1 << 1) /* Suspend Bit */ -#define DMA2D_CR_ABORT (1 << 2) /* Abort Bit */ -#define DMA2D_CR_TEIE (1 << 8) /* Transfer Error Interrupt Enable Bit */ -#define DMA2D_CR_TCIE (1 << 9) /* Transfer Complete Interrupt Enable Bit */ -#define DMA2D_CR_TWIE (1 << 10) /* Transfer Watermark Interrupt Enable Bit */ -#define DMA2D_CR_CAEIE (1 << 11) /* CLUT Access Error Interrupt Enable Bit */ -#define DMA2D_CR_CTCIE (1 << 12) /* CLUT Transfer Complete Interrupt Enable Bit */ -#define DMA2D_CR_CEIE (1 << 13) /* Configuration Error Interrupt Enable Bit */ -#define DMA2D_CR_MODE_SHIFT (16) /* Bits 16-17 DMA2D mode Bits */ -#define DMA2D_CR_MODE_MASK (3 << DMA2D_CR_MODE_SHIFT) -#define DMA2D_CR_MODE(n) ((uint32_t)(n) << DMA2D_CR_MODE_SHIFT) - -/* DMA2D Interrupt Status Register */ - -#define DMA2D_ISR_TEIF (1 << 0) /* Transfer error interrupt flag */ -#define DMA2D_ISR_TCIF (1 << 1) /* Transfer Complete Interrupt flag */ -#define DMA2D_ISR_TWIF (1 << 2) /* Transfer Watermark Interrupt flag */ -#define DMA2D_ISR_CAEIF (1 << 3) /* CLUT Access Error Interrupt flag */ -#define DMA2D_ISR_CTCIF (1 << 4) /* CLUT Transfer Complete Interrupt flag */ -#define DMA2D_ISR_CEIF (1 << 5) /* Configuration Error Interrupt flag */ - -/* DMA2D Interrupt Flag Clear Register */ - -#define DMA2D_IFCR_CTEIF (1 << 0) /* Clear Transfer Interrupt Flag */ -#define DMA2D_IFCR_CTCIF (1 << 1) /* Clear Transfer Complete Interrupt Flag */ -#define DMA2D_IFCR_CTWIF (1 << 2) /* Clear Transfer Watermark Interrupt Flag */ -#define DMA2D_IFCR_CAECIF (1 << 3) /* Clear CLUT Access Error Interrupt Flag */ -#define DMA2D_IFCR_CCTCIF (1 << 4) /* Clear CLUT Transfer Complete Interrupt Flag */ -#define DMA2D_IFCR_CCEIF (1 << 5) /* Clear Configuration Error Interrupt Flag */ - -/* DMA2D Foreground Memory Access Register */ - -/* DMA2D Background Memory Access Register */ - -/* DMA2D Foreground/Background Offset Register */ - -#define DMA2D_XGOR_SHIFT (0) /* Bits 0-13 Line Offset */ -#define DMA2D_XGOR_MASK (0x3fff << DMA2D_XGOR_SHIFT) -#define DMA2D_XGOR(n) ((uint32_t)(n) << DMA2D_XGOR_SHIFT) - -/* DMA2D Foreground/Background PFC Control Register */ - -#define DMA2D_XGPFCCR_CM_SHIFT (0) /* Bits 0-3 Color Mode */ -#define DMA2D_XGPFCCR_CM_MASK (0xf << DMA2D_XGPFCCR_CM_SHIFT) -#define DMA2D_XGPFCCR_CM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CM_SHIFT) -#define DMA2D_XGPFCCR_CCM (1 << 4) /* CLUT Color Mode */ -#define DMA2D_XGPFCCR_START (1 << 5) /* Start */ -#define DMA2D_XGPFCCR_CS_SHIFT (8) /* Bits 8-15 CLUT Size */ -#define DMA2D_XGPFCCR_CS_MASK (0xff << DMA2D_XGPFCCR_CS_SHIFT) -#define DMA2D_XGPFCCR_CS(n) ((uint32_t)(n) << DMA2D_XGPFCCR_CS_SHIFT) -#define DMA2D_XGPFCCR_AM_SHIFT (16) /* Bits 16-17 Alpha Mode */ -#define DMA2D_XGPFCCR_AM_MASK (3 << DMA2D_XGPFCCR_AM_SHIFT) -#define DMA2D_XGPFCCR_AM(n) ((uint32_t)(n) << DMA2D_XGPFCCR_AM_SHIFT) -#define DMA2D_XGPFCCR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ -#define DMA2D_XGPFCCR_ALPHA_MASK (0xff << DMA2D_XGPFCCR_ALPHA_SHIFT) -#define DMA2D_XGPFCCR_ALPHA(n) ((uint32_t)(n) << DMA2D_XGPFCCR_ALPHA_SHIFT) - -/* DMA2D PFC alpha mode */ - -#define STM32_DMA2D_PFCCR_AM_NONE 0 -#define STM32_DMA2D_PFCCR_AM_CONST 1 -#define STM32_DMA2D_PFCCR_AM_PIXEL 2 - -/* DMA2D Foreground/Background Color Register */ - -#define DMA2D_XGCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ -#define DMA2D_XGCOLR_BLUE_MASK (0xff << DMA2D_XGCOLR_BLUE_SHIFT) -#define DMA2D_XGCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_XGCOLR_BLUE_SHIFT) -#define DMA2D_XGCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ -#define DMA2D_XGCOLR_GREEN_MASK (0xff << DMA2D_XGCOLR_GREEN_SHIFT) -#define DMA2D_XGCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_XGCOLR_GREEN_SHIFT) -#define DMA2D_XGCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ -#define DMA2D_XGCOLR_RED_MASK (0xff << DMA2D_XGCOLR_RED_SHIFT) -#define DMA2D_XGCOLR_RED(n) ((uint32_t)(n) << DMA2D_XGCOLR_RED_SHIFT) - -/* DMA2D Foreground CLUT Memory Address Register */ - -/* DMA2D Background CLUT Memory Address Register */ - -/* DMA2D Output PFC Control Register */ - -#define DMA2D_OPFCCR_CM_SHIFT (0) /* Bits 0-2 Color Mode */ -#define DMA2D_OPFCCR_CM_MASK (7 << DMA2D_OPFCCR_CM_SHIFT) -#define DMA2D_OPFCCR_CM(n) ((uint32_t)(n) << DMA2D_OPFCCR_CM_SHIFT) - -/* DMA2D PFC Pixel Format */ - -#define DMA2D_PF_ARGB8888 0 -#define DMA2D_PF_RGB888 1 -#define DMA2D_PF_RGB565 2 -#define DMA2D_PF_ARGB1555 3 -#define DMA2D_PF_ARGB14444 4 -#define DMA2D_PF_L8 5 -#define DMA2D_PF_AL44 6 -#define DMA2D_PF_AL88 7 -#define DMA2D_PF_L4 8 -#define DMA2D_PF_A8 9 -#define DMA2D_PF_A4 10 - -/* DMA2D Output Color Register */ - -#define DMA2D_OCOLR_BLUE_SHIFT (0) /* Bits 0-7 Blue Value */ -#define DMA2D_OCOLR_BLUE_MASK (0xff << DMA2D_OCOLR_BLUE_SHIFT) -#define DMA2D_OCOLR_BLUE(n) ((uint32_t)(n) << DMA2D_OCOLR_BLUE_SHIFT) -#define DMA2D_OCOLR_GREEN_SHIFT (8) /* Bits 8-15 Green Value */ -#define DMA2D_OCOLR_GREEN_MASK (0xff << DMA2D_OCOLR_GREEN_SHIFT) -#define DMA2D_OCOLR_GREEN(n) ((uint32_t)(n) << DMA2D_OCOLR_GREEN_SHIFT) -#define DMA2D_OCOLR_RED_SHIFT (16) /* Bits 16-23 Red Value */ -#define DMA2D_OCOLR_RED_MASK (0xff << DMA2D_OCOLR_RED_SHIFT) -#define DMA2D_OCOLR_RED(n) ((uint32_t)(n) << DMA2D_OCOLR_RED_SHIFT) -#define DMA2D_OCOLR_ALPHA_SHIFT (24) /* Bits 24-31 Alpha Value */ -#define DMA2D_OCOLR_ALPHA_MASK (0xff << DMA2D_OCOLR_ALPHA_SHIFT) -#define DMA2D_OCOLR_ALPHA(n) ((uint32_t)(n) << DMA2D_OCOLR_ALPHA_SHIFT) - -/* DMA2D Output Memory Address Register */ - -/* DMA2D Output Offset Register */ - -#define DMA2D_OOR_LO_SHIFT (0) /* Bits 0-13 Line Offset */ -#define DMA2D_OOR_LO_MASK (0x3fff << DMA2D_OOR_LO_SHIFT) -#define DMA2D_OOR_LO(n) ((uint32_t)(n) << DMA2D_OOR_LO_SHIFT) - -/* DMA2D Number Of Line Register */ - -#define DMA2D_NLR_NL_SHIFT (0) /* Bits 0-15 Number Of Lines */ -#define DMA2D_NLR_NL_MASK (0xffff << DMA2D_NLR_NL_SHIFT) -#define DMA2D_NLR_NL(n) ((uint32_t)(n) << DMA2D_NLR_NL_SHIFT) -#define DMA2D_NLR_PL_SHIFT (16) /* Bits 16-29 Pixel per Lines */ -#define DMA2D_NLR_PL_MASK (0x3fff << DMA2D_NLR_PL_SHIFT) -#define DMA2D_NLR_PL(n) ((uint32_t)(n) << DMA2D_NLR_PL_SHIFT) - -/* DMA2D Line Watermark Register */ - -#define DMA2D_LWR_LW_SHIFT (0) /* Bits 0-15 Line Watermark */ -#define DMA2D_LWR_LW_MASK (0xffff << DMA2D_LWR_LW_SHIFT) -#define DMA2D_LWR_LW(n) ((uint32_t)(n) << DMA2D_LWR_LW_SHIFT) - -/* DMA2D AHB Master Timer Configuration Register */ - -#define DMA2D_AMTCR_EN (1 << 0) /* Enable */ -#define DMA2D_AMTCR_DT_SHIFT (0) /* Bits 8-15 Dead Time */ -#define DMA2D_AMTCR_DT_MASK (0xff << DMA2D_AMTCR_DT_SHIFT) -#define DMA2D_AMTCR_DT(n) ((uint32_t)(n) << DMA2D_AMTCR_DT_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v2.h b/arch/arm/src/stm32/hardware/stm32_dma_v2.h deleted file mode 100644 index 916ddc1380461..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_dma_v2.h +++ /dev/null @@ -1,561 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* This is implementation for STM32 DMA IP version 2 - F2, F4, F7, H7 */ - -#define HAVE_IP_DMA_V2 1 -#undef HAVE_IP_DMA_V1 - -/* 2 DMA controllers */ - -#define DMA1 (0) -#define DMA2 (1) - -/* 8 DMA streams */ - -#define DMA_STREAM0 (0) -#define DMA_STREAM1 (1) -#define DMA_STREAM2 (2) -#define DMA_STREAM3 (3) -#define DMA_STREAM4 (4) -#define DMA_STREAM5 (5) -#define DMA_STREAM6 (6) -#define DMA_STREAM7 (7) - -/* 8 DMA channels */ - -#define DMA_CHAN0 (0) -#define DMA_CHAN1 (1) -#define DMA_CHAN2 (2) -#define DMA_CHAN3 (3) -#define DMA_CHAN4 (4) -#define DMA_CHAN5 (5) -#define DMA_CHAN6 (6) -#define DMA_CHAN7 (7) - -/* Register Offsets *********************************************************/ - -#define STM32_DMA_LISR_OFFSET 0x0000 /* DMA low interrupt status register */ -#define STM32_DMA_HISR_OFFSET 0x0004 /* DMA high interrupt status register */ -#define STM32_DMA_LIFCR_OFFSET 0x0008 /* DMA low interrupt flag clear register */ -#define STM32_DMA_HIFCR_OFFSET 0x000c /* DMA high interrupt flag clear register */ - -#define STM32_DMA_OFFSET(n) (0x0010+0x0018*(n)) -#define STM32_DMA_SCR_OFFSET 0x0000 /* DMA stream n configuration register */ -#define STM32_DMA_SNDTR_OFFSET 0x0004 /* DMA stream n number of data register */ -#define STM32_DMA_SPAR_OFFSET 0x0008 /* DMA stream n peripheral address register */ -#define STM32_DMA_SM0AR_OFFSET 0x000c /* DMA stream n memory 0 address register */ -#define STM32_DMA_SM1AR_OFFSET 0x0010 /* DMA stream n memory 1 address register */ -#define STM32_DMA_SFCR_OFFSET 0x0014 /* DMA stream n FIFO control register */ - -#define STM32_DMA_S0CR_OFFSET 0x0010 /* DMA stream 0 configuration register */ -#define STM32_DMA_S1CR_OFFSET 0x0028 /* DMA stream 1 configuration register */ -#define STM32_DMA_S2CR_OFFSET 0x0040 /* DMA stream 2 configuration register */ -#define STM32_DMA_S3CR_OFFSET 0x0058 /* DMA stream 3 configuration register */ -#define STM32_DMA_S4CR_OFFSET 0x0070 /* DMA stream 4 configuration register */ -#define STM32_DMA_S5CR_OFFSET 0x0088 /* DMA stream 5 configuration register */ -#define STM32_DMA_S6CR_OFFSET 0x00a0 /* DMA stream 6 configuration register */ -#define STM32_DMA_S7CR_OFFSET 0x00b8 /* DMA stream 7 configuration register */ - -#define STM32_DMA_S0NDTR_OFFSET 0x0014 /* DMA stream 0 number of data register */ -#define STM32_DMA_S1NDTR_OFFSET 0x002c /* DMA stream 1 number of data register */ -#define STM32_DMA_S2NDTR_OFFSET 0x0044 /* DMA stream 2 number of data register */ -#define STM32_DMA_S3NDTR_OFFSET 0x005c /* DMA stream 3 number of data register */ -#define STM32_DMA_S4NDTR_OFFSET 0x0074 /* DMA stream 4 number of data register */ -#define STM32_DMA_S5NDTR_OFFSET 0x008c /* DMA stream 5 number of data register */ -#define STM32_DMA_S6NDTR_OFFSET 0x00a4 /* DMA stream 6 number of data register */ -#define STM32_DMA_S7NDTR_OFFSET 0x00bc /* DMA stream 7 number of data register */ - -#define STM32_DMA_S0PAR_OFFSET 0x0018 /* DMA stream 0 peripheral address register */ -#define STM32_DMA_S1PAR_OFFSET 0x0030 /* DMA stream 1 peripheral address register */ -#define STM32_DMA_S2PAR_OFFSET 0x0048 /* DMA stream 2 peripheral address register */ -#define STM32_DMA_S3PAR_OFFSET 0x0060 /* DMA stream 3 peripheral address register */ -#define STM32_DMA_S4PAR_OFFSET 0x0078 /* DMA stream 4 peripheral address register */ -#define STM32_DMA_S5PAR_OFFSET 0x0090 /* DMA stream 5 peripheral address register */ -#define STM32_DMA_S6PAR_OFFSET 0x00a8 /* DMA stream 6 peripheral address register */ -#define STM32_DMA_S7PAR_OFFSET 0x00c0 /* DMA stream 7 peripheral address register */ - -#define STM32_DMA_S0M0AR_OFFSET 0x001c /* DMA stream 0 memory 0 address register */ -#define STM32_DMA_S1M0AR_OFFSET 0x0034 /* DMA stream 1 memory 0 address register */ -#define STM32_DMA_S2M0AR_OFFSET 0x004c /* DMA stream 2 memory 0 address register */ -#define STM32_DMA_S3M0AR_OFFSET 0x0064 /* DMA stream 3 memory 0 address register */ -#define STM32_DMA_S4M0AR_OFFSET 0x007c /* DMA stream 4 memory 0 address register */ -#define STM32_DMA_S5M0AR_OFFSET 0x0094 /* DMA stream 5 memory 0 address register */ -#define STM32_DMA_S6M0AR_OFFSET 0x00ac /* DMA stream 6 memory 0 address register */ -#define STM32_DMA_S7M0AR_OFFSET 0x00c4 /* DMA stream 7 memory 0 address register */ - -#define STM32_DMA_S0M1AR_OFFSET 0x0020 /* DMA stream 0 memory 1 address register */ -#define STM32_DMA_S1M1AR_OFFSET 0x0038 /* DMA stream 1 memory 1 address register */ -#define STM32_DMA_S2M1AR_OFFSET 0x0050 /* DMA stream 2 memory 1 address register */ -#define STM32_DMA_S3M1AR_OFFSET 0x0068 /* DMA stream 3 memory 1 address register */ -#define STM32_DMA_S4M1AR_OFFSET 0x0080 /* DMA stream 4 memory 1 address register */ -#define STM32_DMA_S5M1AR_OFFSET 0x0098 /* DMA stream 5 memory 1 address register */ -#define STM32_DMA_S6M1AR_OFFSET 0x00b0 /* DMA stream 6 memory 1 address register */ -#define STM32_DMA_S7M1AR_OFFSET 0x00c8 /* DMA stream 7 memory 1 address register */ - -#define STM32_DMA_S0FCR_OFFSET 0x0024 /* DMA stream 0 FIFO control register */ -#define STM32_DMA_S1FCR_OFFSET 0x003c /* DMA stream 1 FIFO control register */ -#define STM32_DMA_S2FCR_OFFSET 0x0054 /* DMA stream 2 FIFO control register */ -#define STM32_DMA_S3FCR_OFFSET 0x006c /* DMA stream 3 FIFO control register */ -#define STM32_DMA_S4FCR_OFFSET 0x0084 /* DMA stream 4 FIFO control register */ -#define STM32_DMA_S5FCR_OFFSET 0x009c /* DMA stream 5 FIFO control register */ -#define STM32_DMA_S6FCR_OFFSET 0x00b4 /* DMA stream 6 FIFO control register */ -#define STM32_DMA_S7FCR_OFFSET 0x00cc /* DMA stream 7 FIFO control register */ - -/* Register Addresses *******************************************************/ - -#define STM32_DMA1_LISRC (STM32_DMA1_BASE+STM32_DMA_LISR_OFFSET) -#define STM32_DMA1_HISRC (STM32_DMA1_BASE+STM32_DMA_HISR_OFFSET) -#define STM32_DMA1_LIFCR (STM32_DMA1_BASE+STM32_DMA_LIFCR_OFFSET) -#define STM32_DMA1_HIFCR (STM32_DMA1_BASE+STM32_DMA_HIFCR_OFFSET) - -#define STM32_DMA1_SCR(n) (STM32_DMA1_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0CR (STM32_DMA1_BASE+STM32_DMA_S0CR_OFFSET) -#define STM32_DMA1_S1CR (STM32_DMA1_BASE+STM32_DMA_S1CR_OFFSET) -#define STM32_DMA1_S2CR (STM32_DMA1_BASE+STM32_DMA_S2CR_OFFSET) -#define STM32_DMA1_S3CR (STM32_DMA1_BASE+STM32_DMA_S3CR_OFFSET) -#define STM32_DMA1_S4CR (STM32_DMA1_BASE+STM32_DMA_S4CR_OFFSET) -#define STM32_DMA1_S5CR (STM32_DMA1_BASE+STM32_DMA_S5CR_OFFSET) -#define STM32_DMA1_S6CR (STM32_DMA1_BASE+STM32_DMA_S6CR_OFFSET) -#define STM32_DMA1_S7CR (STM32_DMA1_BASE+STM32_DMA_S7CR_OFFSET) - -#define STM32_DMA1_SNDTR(n) (STM32_DMA1_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0NDTR (STM32_DMA1_BASE+STM32_DMA_S0NDTR_OFFSET) -#define STM32_DMA1_S1NDTR (STM32_DMA1_BASE+STM32_DMA_S1NDTR_OFFSET) -#define STM32_DMA1_S2NDTR (STM32_DMA1_BASE+STM32_DMA_S2NDTR_OFFSET) -#define STM32_DMA1_S3NDTR (STM32_DMA1_BASE+STM32_DMA_S3NDTR_OFFSET) -#define STM32_DMA1_S4NDTR (STM32_DMA1_BASE+STM32_DMA_S4NDTR_OFFSET) -#define STM32_DMA1_S5NDTR (STM32_DMA1_BASE+STM32_DMA_S5NDTR_OFFSET) -#define STM32_DMA1_S6NDTR (STM32_DMA1_BASE+STM32_DMA_S6NDTR_OFFSET) -#define STM32_DMA1_S7NDTR (STM32_DMA1_BASE+STM32_DMA_S7NDTR_OFFSET) - -#define STM32_DMA1_SPAR(n) (STM32_DMA1_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0PAR (STM32_DMA1_BASE+STM32_DMA_S0PAR_OFFSET) -#define STM32_DMA1_S1PAR (STM32_DMA1_BASE+STM32_DMA_S1PAR_OFFSET) -#define STM32_DMA1_S2PAR (STM32_DMA1_BASE+STM32_DMA_S2PAR_OFFSET) -#define STM32_DMA1_S3PAR (STM32_DMA1_BASE+STM32_DMA_S3PAR_OFFSET) -#define STM32_DMA1_S4PAR (STM32_DMA1_BASE+STM32_DMA_S4PAR_OFFSET) -#define STM32_DMA1_S5PAR (STM32_DMA1_BASE+STM32_DMA_S5PAR_OFFSET) -#define STM32_DMA1_S6PAR (STM32_DMA1_BASE+STM32_DMA_S6PAR_OFFSET) -#define STM32_DMA1_S7PAR (STM32_DMA1_BASE+STM32_DMA_S7PAR_OFFSET) - -#define STM32_DMA1_SM0AR(n) (STM32_DMA1_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0M0AR (STM32_DMA1_BASE+STM32_DMA_S0M0AR_OFFSET) -#define STM32_DMA1_S1M0AR (STM32_DMA1_BASE+STM32_DMA_S1M0AR_OFFSET) -#define STM32_DMA1_S2M0AR (STM32_DMA1_BASE+STM32_DMA_S2M0AR_OFFSET) -#define STM32_DMA1_S3M0AR (STM32_DMA1_BASE+STM32_DMA_S3M0AR_OFFSET) -#define STM32_DMA1_S4M0AR (STM32_DMA1_BASE+STM32_DMA_S4M0AR_OFFSET) -#define STM32_DMA1_S5M0AR (STM32_DMA1_BASE+STM32_DMA_S5M0AR_OFFSET) -#define STM32_DMA1_S6M0AR (STM32_DMA1_BASE+STM32_DMA_S6M0AR_OFFSET) -#define STM32_DMA1_S7M0AR (STM32_DMA1_BASE+STM32_DMA_S7M0AR_OFFSET) - -#define STM32_DMA1_SM1AR(n) (STM32_DMA1_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0M1AR (STM32_DMA1_BASE+STM32_DMA_S0M1AR_OFFSET) -#define STM32_DMA1_S1M1AR (STM32_DMA1_BASE+STM32_DMA_S1M1AR_OFFSET) -#define STM32_DMA1_S2M1AR (STM32_DMA1_BASE+STM32_DMA_S2M1AR_OFFSET) -#define STM32_DMA1_S3M1AR (STM32_DMA1_BASE+STM32_DMA_S3M1AR_OFFSET) -#define STM32_DMA1_S4M1AR (STM32_DMA1_BASE+STM32_DMA_S4M1AR_OFFSET) -#define STM32_DMA1_S5M1AR (STM32_DMA1_BASE+STM32_DMA_S5M1AR_OFFSET) -#define STM32_DMA1_S6M1AR (STM32_DMA1_BASE+STM32_DMA_S6M1AR_OFFSET) -#define STM32_DMA1_S7M1AR (STM32_DMA1_BASE+STM32_DMA_S7M1AR_OFFSET) - -#define STM32_DMA1_SFCR(n) (STM32_DMA1_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA1_S0FCR (STM32_DMA1_BASE+STM32_DMA_S0FCR_OFFSET) -#define STM32_DMA1_S1FCR (STM32_DMA1_BASE+STM32_DMA_S1FCR_OFFSET) -#define STM32_DMA1_S2FCR (STM32_DMA1_BASE+STM32_DMA_S2FCR_OFFSET) -#define STM32_DMA1_S3FCR (STM32_DMA1_BASE+STM32_DMA_S3FCR_OFFSET) -#define STM32_DMA1_S4FCR (STM32_DMA1_BASE+STM32_DMA_S4FCR_OFFSET) -#define STM32_DMA1_S5FCR (STM32_DMA1_BASE+STM32_DMA_S5FCR_OFFSET) -#define STM32_DMA1_S6FCR (STM32_DMA1_BASE+STM32_DMA_S6FCR_OFFSET) -#define STM32_DMA1_S7FCR (STM32_DMA1_BASE+STM32_DMA_S7FCR_OFFSET) - -#define STM32_DMA2_LISRC (STM32_DMA2_BASE+STM32_DMA_LISR_OFFSET) -#define STM32_DMA2_HISRC (STM32_DMA2_BASE+STM32_DMA_HISR_OFFSET) -#define STM32_DMA2_LIFCR (STM32_DMA2_BASE+STM32_DMA_LIFCR_OFFSET) -#define STM32_DMA2_HIFCR (STM32_DMA2_BASE+STM32_DMA_HIFCR_OFFSET) - -#define STM32_DMA2_SCR(n) (STM32_DMA2_BASE+STM32_DMA_SCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0CR (STM32_DMA2_BASE+STM32_DMA_S0CR_OFFSET) -#define STM32_DMA2_S1CR (STM32_DMA2_BASE+STM32_DMA_S1CR_OFFSET) -#define STM32_DMA2_S2CR (STM32_DMA2_BASE+STM32_DMA_S2CR_OFFSET) -#define STM32_DMA2_S3CR (STM32_DMA2_BASE+STM32_DMA_S3CR_OFFSET) -#define STM32_DMA2_S4CR (STM32_DMA2_BASE+STM32_DMA_S4CR_OFFSET) -#define STM32_DMA2_S5CR (STM32_DMA2_BASE+STM32_DMA_S5CR_OFFSET) -#define STM32_DMA2_S6CR (STM32_DMA2_BASE+STM32_DMA_S6CR_OFFSET) -#define STM32_DMA2_S7CR (STM32_DMA2_BASE+STM32_DMA_S7CR_OFFSET) - -#define STM32_DMA2_SNDTR(n) (STM32_DMA2_BASE+STM32_DMA_SNDTR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0NDTR (STM32_DMA2_BASE+STM32_DMA_S0NDTR_OFFSET) -#define STM32_DMA2_S1NDTR (STM32_DMA2_BASE+STM32_DMA_S1NDTR_OFFSET) -#define STM32_DMA2_S2NDTR (STM32_DMA2_BASE+STM32_DMA_S2NDTR_OFFSET) -#define STM32_DMA2_S3NDTR (STM32_DMA2_BASE+STM32_DMA_S3NDTR_OFFSET) -#define STM32_DMA2_S4NDTR (STM32_DMA2_BASE+STM32_DMA_S4NDTR_OFFSET) -#define STM32_DMA2_S5NDTR (STM32_DMA2_BASE+STM32_DMA_S5NDTR_OFFSET) -#define STM32_DMA2_S6NDTR (STM32_DMA2_BASE+STM32_DMA_S6NDTR_OFFSET) -#define STM32_DMA2_S7NDTR (STM32_DMA2_BASE+STM32_DMA_S7NDTR_OFFSET) - -#define STM32_DMA2_SPAR(n) (STM32_DMA2_BASE+STM32_DMA_SPAR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0PAR (STM32_DMA2_BASE+STM32_DMA_S0PAR_OFFSET) -#define STM32_DMA2_S1PAR (STM32_DMA2_BASE+STM32_DMA_S1PAR_OFFSET) -#define STM32_DMA2_S2PAR (STM32_DMA2_BASE+STM32_DMA_S2PAR_OFFSET) -#define STM32_DMA2_S3PAR (STM32_DMA2_BASE+STM32_DMA_S3PAR_OFFSET) -#define STM32_DMA2_S4PAR (STM32_DMA2_BASE+STM32_DMA_S4PAR_OFFSET) -#define STM32_DMA2_S5PAR (STM32_DMA2_BASE+STM32_DMA_S5PAR_OFFSET) -#define STM32_DMA2_S6PAR (STM32_DMA2_BASE+STM32_DMA_S6PAR_OFFSET) -#define STM32_DMA2_S7PAR (STM32_DMA2_BASE+STM32_DMA_S7PAR_OFFSET) - -#define STM32_DMA2_SM0AR(n) (STM32_DMA2_BASE+STM32_DMA_SM0AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0M0AR (STM32_DMA2_BASE+STM32_DMA_S0M0AR_OFFSET) -#define STM32_DMA2_S1M0AR (STM32_DMA2_BASE+STM32_DMA_S1M0AR_OFFSET) -#define STM32_DMA2_S2M0AR (STM32_DMA2_BASE+STM32_DMA_S2M0AR_OFFSET) -#define STM32_DMA2_S3M0AR (STM32_DMA2_BASE+STM32_DMA_S3M0AR_OFFSET) -#define STM32_DMA2_S4M0AR (STM32_DMA2_BASE+STM32_DMA_S4M0AR_OFFSET) -#define STM32_DMA2_S5M0AR (STM32_DMA2_BASE+STM32_DMA_S5M0AR_OFFSET) -#define STM32_DMA2_S6M0AR (STM32_DMA2_BASE+STM32_DMA_S6M0AR_OFFSET) -#define STM32_DMA2_S7M0AR (STM32_DMA2_BASE+STM32_DMA_S7M0AR_OFFSET) - -#define STM32_DMA2_SM1AR(n) (STM32_DMA2_BASE+STM32_DMA_SM1AR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0M1AR (STM32_DMA2_BASE+STM32_DMA_S0M1AR_OFFSET) -#define STM32_DMA2_S1M1AR (STM32_DMA2_BASE+STM32_DMA_S1M1AR_OFFSET) -#define STM32_DMA2_S2M1AR (STM32_DMA2_BASE+STM32_DMA_S2M1AR_OFFSET) -#define STM32_DMA2_S3M1AR (STM32_DMA2_BASE+STM32_DMA_S3M1AR_OFFSET) -#define STM32_DMA2_S4M1AR (STM32_DMA2_BASE+STM32_DMA_S4M1AR_OFFSET) -#define STM32_DMA2_S5M1AR (STM32_DMA2_BASE+STM32_DMA_S5M1AR_OFFSET) -#define STM32_DMA2_S6M1AR (STM32_DMA2_BASE+STM32_DMA_S6M1AR_OFFSET) -#define STM32_DMA2_S7M1AR (STM32_DMA2_BASE+STM32_DMA_S7M1AR_OFFSET) - -#define STM32_DMA2_SFCR(n) (STM32_DMA2_BASE+STM32_DMA_SFCR_OFFSET+STM32_DMA_OFFSET(n)) -#define STM32_DMA2_S0FCR (STM32_DMA2_BASE+STM32_DMA_S0FCR_OFFSET) -#define STM32_DMA2_S1FCR (STM32_DMA2_BASE+STM32_DMA_S1FCR_OFFSET) -#define STM32_DMA2_S2FCR (STM32_DMA2_BASE+STM32_DMA_S2FCR_OFFSET) -#define STM32_DMA2_S3FCR (STM32_DMA2_BASE+STM32_DMA_S3FCR_OFFSET) -#define STM32_DMA2_S4FCR (STM32_DMA2_BASE+STM32_DMA_S4FCR_OFFSET) -#define STM32_DMA2_S5FCR (STM32_DMA2_BASE+STM32_DMA_S5FCR_OFFSET) -#define STM32_DMA2_S6FCR (STM32_DMA2_BASE+STM32_DMA_S6FCR_OFFSET) -#define STM32_DMA2_S7FCR (STM32_DMA2_BASE+STM32_DMA_S7FCR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define DMA_STREAM_MASK 0x3f -#define DMA_STREAM_FEIF_BIT (1 << 0) /* Bit 0: Stream FIFO error interrupt flag */ -#define DMA_STREAM_DMEIF_BIT (1 << 2) /* Bit 2: Stream direct mode error interrupt flag */ -#define DMA_STREAM_TEIF_BIT (1 << 3) /* Bit 3: Stream Transfer Error flag */ -#define DMA_STREAM_HTIF_BIT (1 << 4) /* Bit 4: Stream Half Transfer flag */ -#define DMA_STREAM_TCIF_BIT (1 << 5) /* Bit 5: Stream Transfer Complete flag */ - -/* DMA interrupt status register and interrupt flag clear register field - * definitions - */ - -#define DMA_INT_STREAM0_SHIFT (0) /* Bits 0-5: DMA Stream 0 interrupt */ -#define DMA_INT_STREAM0_MASK (DMA_STREAM_MASK << DMA_INT_STREAM0_SHIFT) -#define DMA_INT_STREAM1_SHIFT (6) /* Bits 6-11: DMA Stream 1 interrupt */ -#define DMA_INT_STREAM1_MASK (DMA_STREAM_MASK << DMA_INT_STREAM1_SHIFT) -#define DMA_INT_STREAM2_SHIFT (16) /* Bits 16-21: DMA Stream 2 interrupt */ -#define DMA_INT_STREAM2_MASK (DMA_STREAM_MASK << DMA_INT_STREAM2_SHIFT) -#define DMA_INT_STREAM3_SHIFT (22) /* Bits 22-27: DMA Stream 3 interrupt */ -#define DMA_INT_STREAM3_MASK (DMA_STREAM_MASK << DMA_INT_STREAM3_SHIFT) - -#define DMA_INT_STREAM4_SHIFT (0) /* Bits 0-5: DMA Stream 4 interrupt */ -#define DMA_INT_STREAM4_MASK (DMA_STREAM_MASK << DMA_INT_STREAM4_SHIFT) -#define DMA_INT_STREAM5_SHIFT (6) /* Bits 6-11: DMA Stream 5 interrupt */ -#define DMA_INT_STREAM5_MASK (DMA_STREAM_MASK << DMA_INT_STREAM5_SHIFT) -#define DMA_INT_STREAM6_SHIFT (16) /* Bits 16-21: DMA Stream 6 interrupt */ -#define DMA_INT_STREAM6_MASK (DMA_STREAM_MASK << DMA_INT_STREAM6_SHIFT) -#define DMA_INT_STREAM7_SHIFT (22) /* Bits 22-27: DMA Stream 7 interrupt */ -#define DMA_INT_STREAM7_MASK (DMA_STREAM_MASK << DMA_INT_STREAM7_SHIFT) - -/* DMA stream configuration register */ - -#define DMA_SCR_EN (1 << 0) /* Bit 0: Stream enable */ -#define DMA_SCR_DMEIE (1 << 1) /* Bit 1: Direct mode error interrupt enable */ -#define DMA_SCR_TEIE (1 << 2) /* Bit 2: Transfer error interrupt enable */ -#define DMA_SCR_HTIE (1 << 3) /* Bit 3: Half Transfer interrupt enable */ -#define DMA_SCR_TCIE (1 << 4) /* Bit 4: Transfer complete interrupt enable */ -#define DMA_SCR_PFCTRL (1 << 5) /* Bit 5: Peripheral flow controller */ -#define DMA_SCR_DIR_SHIFT (6) /* Bits 6-7: Data transfer direction */ -#define DMA_SCR_DIR_MASK (3 << DMA_SCR_DIR_SHIFT) -# define DMA_SCR_DIR_P2M (0 << DMA_SCR_DIR_SHIFT) /* 00: Peripheral-to-memory */ -# define DMA_SCR_DIR_M2P (1 << DMA_SCR_DIR_SHIFT) /* 01: Memory-to-peripheral */ -# define DMA_SCR_DIR_M2M (2 << DMA_SCR_DIR_SHIFT) /* 10: Memory-to-memory */ - -#define DMA_SCR_CIRC (1 << 8) /* Bit 8: Circular mode */ -#define DMA_SCR_PINC (1 << 9) /* Bit 9: Peripheral increment mode */ -#define DMA_SCR_MINC (1 << 10) /* Bit 10: Memory increment mode */ -#define DMA_SCR_PSIZE_SHIFT (11) /* Bits 11-12: Peripheral size */ -#define DMA_SCR_PSIZE_MASK (3 << DMA_SCR_PSIZE_SHIFT) -# define DMA_SCR_PSIZE_8BITS (0 << DMA_SCR_PSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_SCR_PSIZE_16BITS (1 << DMA_SCR_PSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_SCR_PSIZE_32BITS (2 << DMA_SCR_PSIZE_SHIFT) /* 10: 32-bits */ - -#define DMA_SCR_MSIZE_SHIFT (13) /* Bits 13-14: Memory size */ -#define DMA_SCR_MSIZE_MASK (3 << DMA_SCR_MSIZE_SHIFT) -# define DMA_SCR_MSIZE_8BITS (0 << DMA_SCR_MSIZE_SHIFT) /* 00: 8-bits */ -# define DMA_SCR_MSIZE_16BITS (1 << DMA_SCR_MSIZE_SHIFT) /* 01: 16-bits */ -# define DMA_SCR_MSIZE_32BITS (2 << DMA_SCR_MSIZE_SHIFT) /* 10: 32-bits */ - -#define DMA_SCR_PINCOS (1 << 15) /* Bit 15: Peripheral increment offset size */ -#define DMA_SCR_PL_SHIFT (16) /* Bits 16-17: Stream Priority level */ -#define DMA_SCR_PL_MASK (3 << DMA_SCR_PL_SHIFT) -# define DMA_SCR_PRILO (0 << DMA_SCR_PL_SHIFT) /* 00: Low */ -# define DMA_SCR_PRIMED (1 << DMA_SCR_PL_SHIFT) /* 01: Medium */ -# define DMA_SCR_PRIHI (2 << DMA_SCR_PL_SHIFT) /* 10: High */ -# define DMA_SCR_PRIVERYHI (3 << DMA_SCR_PL_SHIFT) /* 11: Very high */ - -#define DMA_SCR_DBM (1 << 18) /* Bit 15: Double buffer mode */ -#define DMA_SCR_CT (1 << 19) /* Bit 19: Current target */ -#define DMA_SCR_PBURST_SHIFT (21) /* Bits 21-22: Peripheral burst transfer configuration */ -#define DMA_SCR_PBURST_MASK (3 << DMA_SCR_PBURST_SHIFT) -# define DMA_SCR_PBURST_SINGLE (0 << DMA_SCR_PBURST_SHIFT) /* 00: Single transfer */ -# define DMA_SCR_PBURST_INCR4 (1 << DMA_SCR_PBURST_SHIFT) /* 01: Incremental burst of 4 beats */ -# define DMA_SCR_PBURST_INCR8 (2 << DMA_SCR_PBURST_SHIFT) /* 10: Incremental burst of 8 beats */ -# define DMA_SCR_PBURST_INCR16 (3 << DMA_SCR_PBURST_SHIFT) /* 11: Incremental burst of 16 beats */ - -#define DMA_SCR_MBURST_SHIFT (23) /* Bits 23-24: Memory burst transfer configuration */ -#define DMA_SCR_MBURST_MASK (3 << DMA_SCR_MBURST_SHIFT) -# define DMA_SCR_MBURST_SINGLE (0 << DMA_SCR_MBURST_SHIFT) /* 00: Single transfer */ -# define DMA_SCR_MBURST_INCR4 (1 << DMA_SCR_MBURST_SHIFT) /* 01: Incremental burst of 4 beats */ -# define DMA_SCR_MBURST_INCR8 (2 << DMA_SCR_MBURST_SHIFT) /* 10: Incremental burst of 8 beats */ -# define DMA_SCR_MBURST_INCR16 (3 << DMA_SCR_MBURST_SHIFT) /* 11: Incremental burst of 16 beats */ - -#define DMA_SCR_CHSEL_SHIFT (25) /* Bits 25-27: Channel selection */ -#define DMA_SCR_CHSEL_MASK (7 << DMA_SCR_CHSEL_SHIFT) -# define DMA_SCR_CHSEL(n) ((n) << DMA_SCR_CHSEL_SHIFT) - -#define DMA_SCR_ALLINTS (DMA_SCR_DMEIE|DMA_SCR_TEIE|DMA_SCR_HTIE|DMA_SCR_TCIE) - -/* DMA stream number of data register */ - -#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */ -#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT) - -/* DMA stream n FIFO control register */ - -#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */ -#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT) -# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */ -# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */ -# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */ -# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */ - -#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */ -#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */ -#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT) -# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */ -# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */ -# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */ -# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */ -# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */ -# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */ - - /* Bit 6: Reserved */ -#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */ - /* Bits 8-31: Reserved */ - -/* DMA Stream mapping. - * Each DMA stream has a mapping to several possible sources/sinks of data. - * The requests from peripherals assigned to a stream are simply OR'ed - * together before entering the DMA block. This means that only one request - * on a given stream can be enabled at once. - * - * Alternative stream selections are provided with a numeric suffix like _1, - * _2, etc. The DMA driver, however, will use the pin selection without the - * numeric suffix. Additional definitions are required in the board.h file. - * For example, if SPI3_RX connects via DMA STREAM0, then following should - * be application-specific mapping should be used: - * - * #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1 - */ - -#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c)) -#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1) -#define STM32_DMA_STREAM(m) (((m) >> 3) & 7) -#define STM32_DMA_CHANNEL(m) ((m) & 7) - -#define DMAMAP_SPI3_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN0) -#define DMAMAP_SPI3_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_SPI2_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN0) -#define DMAMAP_SPI2_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN0) -#define DMAMAP_SPI3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN0) -#define DMAMAP_SPI3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN0) - -#define DMAMAP_I2C1_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN1) -#define DMAMAP_TIM7_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN1) -#define DMAMAP_TIM7_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN1) -#define DMAMAP_I2C1_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN1) -#define DMAMAP_I2C1_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN1) -#define DMAMAP_I2C1_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN1) - -#define DMAMAP_TIM4_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_I2S2_EXT_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN2) -#define DMAMAP_TIM4_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN2) -#define DMAMAP_I2S2_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN2) -#define DMAMAP_I2S3_EXT_TX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN2) -#define DMAMAP_TIM4_UP STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN2) -#define DMAMAP_TIM4_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN2) - -#define DMAMAP_I2S3_EXT_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN3) -#define DMAMAP_TIM2_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN3) -#define DMAMAP_TIM2_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_I2C3_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_I2S2_EXT_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN3) -#define DMAMAP_I2C3_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN3) -#define DMAMAP_TIM2_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN3) -#define DMAMAP_TIM2_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) -#define DMAMAP_TIM2_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN3) -#define DMAMAP_TIM2_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) -#define DMAMAP_TIM2_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN3) - -#define DMAMAP_UART5_RX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN4) -#define DMAMAP_USART3_RX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN4) -#define DMAMAP_UART4_RX STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN4) -#define DMAMAP_USART3_TX_1 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN4) -#define DMAMAP_UART4_TX STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN4) -#define DMAMAP_USART2_RX STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN4) -#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4) -#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4) - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5) -# define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5) -#endif -#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) -#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5) -#endif -#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) -#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5) -#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5) -#endif -#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5) - -#define DMAMAP_TIM5_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM5_UP_1 STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM5_CH4_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM5_TRIG_1 STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM5_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN6) -#define DMAMAP_TIM5_CH4_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM5_TRIG_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM5_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM5_UP_2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN6) - -#define DMAMAP_TIM6_UP STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7) -#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7) -#define DMAMAP_DAC1_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7) -#define DMAMAP_DAC1_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7) -#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7) - -#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0) -#define DMAMAP_TIM8_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_TIM8_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_TIM8_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN0) -#define DMAMAP_ADC1_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN0) -#define DMAMAP_TIM1_CH1_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH2_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) -#define DMAMAP_TIM1_CH3_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN0) - -#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1) -#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1) -#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1) -# define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1) -#endif -#define DMAMAP_DCMI_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN1) - -#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2) -#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2) -# define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2) -#endif -#define DMAMAP_CRYP_OUT STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN2) -#define DMAMAP_CRYP_IN STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN2) -#define DMAMAP_HASH_IN STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN2) - -#define DMAMAP_SPI1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN3) -#define DMAMAP_SPI1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN3) -#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3) -#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3) - -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4) -# define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4) -#endif -#define DMAMAP_USART1_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN4) -#define DMAMAP_SDIO_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN4) -#define DMAMAP_USART1_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN4) -#define DMAMAP_SDIO_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN4) -#define DMAMAP_USART1_TX STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN4) - -#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5) -#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5) -# define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5) -#endif -#define DMAMAP_USART6_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN5) -#define DMAMAP_USART6_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN5) - -#define DMAMAP_TIM1_TRIG_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN6) -#define DMAMAP_TIM1_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN6) -#define DMAMAP_TIM1_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN6) -#define DMAMAP_TIM1_CH1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN6) -#define DMAMAP_TIM1_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_TRIG_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_COM STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN6) -#define DMAMAP_TIM1_UP STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN6) -#define DMAMAP_TIM1_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN6) - -#define DMAMAP_TIM8_UP STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN7) -#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7) -#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7) -#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7) -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F469) -# define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7) -# define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7) -#endif -#define DMAMAP_TIM8_CH4 STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_eth.h b/arch/arm/src/stm32/hardware/stm32_eth.h deleted file mode 100644 index d95a6441c49a2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_eth.h +++ /dev/null @@ -1,877 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_eth.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#if STM32_NETHERNET > 0 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* MAC Registers */ - -#define STM32_ETH_MACCR_OFFSET 0x0000 /* Ethernet MAC configuration register */ -#define STM32_ETH_MACFFR_OFFSET 0x0004 /* Ethernet MAC frame filter register */ -#define STM32_ETH_MACHTHR_OFFSET 0x0008 /* Ethernet MAC hash table high register */ -#define STM32_ETH_MACHTLR_OFFSET 0x000c /* Ethernet MAC hash table low register */ -#define STM32_ETH_MACMIIAR_OFFSET 0x0010 /* Ethernet MAC MII address register */ -#define STM32_ETH_MACMIIDR_OFFSET 0x0014 /* Ethernet MAC MII data register */ -#define STM32_ETH_MACFCR_OFFSET 0x0018 /* Ethernet MAC flow control register */ -#define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ -#define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ -#define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ -#endif -#define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ -#define STM32_ETH_MACIMR_OFFSET 0x003c /* Ethernet MAC interrupt mask register */ -#define STM32_ETH_MACA0HR_OFFSET 0x0040 /* Ethernet MAC address 0 high register */ -#define STM32_ETH_MACA0LR_OFFSET 0x0044 /* Ethernet MAC address 0 low register */ -#define STM32_ETH_MACA1HR_OFFSET 0x0048 /* Ethernet MAC address 1 high register */ -#define STM32_ETH_MACA1LR_OFFSET 0x004c /* Ethernet MAC address1 low register */ -#define STM32_ETH_MACA2HR_OFFSET 0x0050 /* Ethernet MAC address 2 high register */ -#define STM32_ETH_MACA2LR_OFFSET 0x0054 /* Ethernet MAC address 2 low register */ -#define STM32_ETH_MACA3HR_OFFSET 0x0058 /* Ethernet MAC address 3 high register */ -#define STM32_ETH_MACA3LR_OFFSET 0x005c /* Ethernet MAC address 3 low register */ - -/* MMC Registers */ - -#define STM32_ETH_MMCCR_OFFSET 0x0100 /* Ethernet MMC control register */ -#define STM32_ETH_MMCRIR_OFFSET 0x0104 /* Ethernet MMC receive interrupt register */ -#define STM32_ETH_MMCTIR_OFFSET 0x0108 /* Ethernet MMC transmit interrupt register */ -#define STM32_ETH_MMCRIMR_OFFSET 0x010c /* Ethernet MMC receive interrupt mask register */ -#define STM32_ETH_MMCTIMR_OFFSET 0x0110 /* Ethernet MMC transmit interrupt mask register */ -#define STM32_ETH_MMCTGFSCCR_OFFSET 0x014c /* Ethernet MMC transmitted good frames counter register (single collision) */ -#define STM32_ETH_MMCTGFMSCCR_OFFSET 0x0150 /* Ethernet MMC transmitted good frames counter register (multiple-collision) */ -#define STM32_ETH_MMCTGFCR_OFFSET 0x0168 /* Ethernet MMC transmitted good frames counter register */ -#define STM32_ETH_MMCRFCECR_OFFSET 0x0194 /* Ethernet MMC received frames with CRC error counter register */ -#define STM32_ETH_MMCRFAECR_OFFSET 0x0198 /* Ethernet MMC received frames with alignment error counter */ -#define STM32_ETH_MMCRGUFCR_OFFSET 0x01c4 /* MMC received good unicast frames counter register */ - -/* IEEE 1588 time stamp registers */ - -#define STM32_ETH_PTPTSCR_OFFSET 0x0700 /* Ethernet PTP time stamp control register */ -#define STM32_ETH_PTPSSIR_OFFSET 0x0704 /* Ethernet PTP subsecond increment register */ -#define STM32_ETH_PTPTSHR_OFFSET 0x0708 /* Ethernet PTP time stamp high register */ -#define STM32_ETH_PTPTSLR_OFFSET 0x070c /* Ethernet PTP time stamp low register */ -#define STM32_ETH_PTPTSHUR_OFFSET 0x0710 /* Ethernet PTP time stamp high update register */ -#define STM32_ETH_PTPTSLUR_OFFSET 0x0714 /* Ethernet PTP time stamp low update register */ -#define STM32_ETH_PTPTSAR_OFFSET 0x0718 /* Ethernet PTP time stamp addend register */ -#define STM32_ETH_PTPTTHR_OFFSET 0x071c /* Ethernet PTP target time high register */ -#define STM32_ETH_PTPTTLR_OFFSET 0x0720 /* Ethernet PTP target time low register */ -#define STM32_ETH_PTPTSSR_OFFSET 0x0728 /* Ethernet PTP time stamp status register */ -#define STM32_ETH_PTPPPSCR_OFFSET 0x072c /* Ethernet PTP PPS control register */ - -/* DMA Registers */ - -#define STM32_ETH_DMABMR_OFFSET 0x1000 /* Ethernet DMA bus mode register */ -#define STM32_ETH_DMATPDR_OFFSET 0x1004 /* Ethernet DMA transmit poll demand register */ -#define STM32_ETH_DMARPDR_OFFSET 0x1008 /* Ethernet DMA receive poll demand register */ -#define STM32_ETH_DMARDLAR_OFFSET 0x100c /* Ethernet DMA receive descriptor list address register */ -#define STM32_ETH_DMATDLAR_OFFSET 0x1010 /* Ethernet DMA transmit descriptor list address register */ -#define STM32_ETH_DMASR_OFFSET 0x1014 /* Ethernet DMA status register */ -#define STM32_ETH_DMAOMR_OFFSET 0x1018 /* Ethernet DMA operation mode register */ -#define STM32_ETH_DMAIER_OFFSET 0x101c /* Ethernet DMA interrupt enable register */ -#define STM32_ETH_DMAMFBOC_OFFSET 0x1020 /* Ethernet DMA missed frame and buffer overflow counter register */ -#define STM32_ETH_DMARSWTR_OFFSET 0x1024 /* Ethernet DMA receive status watchdog timer register */ -#define STM32_ETH_DMACHTDR_OFFSET 0x1048 /* Ethernet DMA current host transmit descriptor register */ -#define STM32_ETH_DMACHRDR_OFFSET 0x104c /* Ethernet DMA current host receive descriptor register */ -#define STM32_ETH_DMACHTBAR_OFFSET 0x1050 /* Ethernet DMA current host transmit buffer address register */ -#define STM32_ETH_DMACHRBAR_OFFSET 0x1054 /* Ethernet DMA current host receive buffer address register */ - -/* Register Base Addresses **************************************************/ - -/* MAC Registers */ - -#define STM32_ETH_MACCR (STM32_ETHERNET_BASE+STM32_ETH_MACCR_OFFSET) -#define STM32_ETH_MACFFR (STM32_ETHERNET_BASE+STM32_ETH_MACFFR_OFFSET) -#define STM32_ETH_MACHTHR (STM32_ETHERNET_BASE+STM32_ETH_MACHTHR_OFFSET) -#define STM32_ETH_MACHTLR (STM32_ETHERNET_BASE+STM32_ETH_MACHTLR_OFFSET) -#define STM32_ETH_MACMIIAR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIAR_OFFSET) -#define STM32_ETH_MACMIIDR (STM32_ETHERNET_BASE+STM32_ETH_MACMIIDR_OFFSET) -#define STM32_ETH_MACFCR (STM32_ETHERNET_BASE+STM32_ETH_MACFCR_OFFSET) -#define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) -#define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) -#define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) -#endif -#define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) -#define STM32_ETH_MACIMR (STM32_ETHERNET_BASE+STM32_ETH_MACIMR_OFFSET) -#define STM32_ETH_MACA0HR (STM32_ETHERNET_BASE+STM32_ETH_MACA0HR_OFFSET) -#define STM32_ETH_MACA0LR (STM32_ETHERNET_BASE+STM32_ETH_MACA0LR_OFFSET) -#define STM32_ETH_MACA1HR (STM32_ETHERNET_BASE+STM32_ETH_MACA1HR_OFFSET) -#define STM32_ETH_MACA1LR (STM32_ETHERNET_BASE+STM32_ETH_MACA1LR_OFFSET) -#define STM32_ETH_MACA2HR (STM32_ETHERNET_BASE+STM32_ETH_MACA2HR_OFFSET) -#define STM32_ETH_MACA2LR (STM32_ETHERNET_BASE+STM32_ETH_MACA2LR_OFFSET) -#define STM32_ETH_MACA3HR (STM32_ETHERNET_BASE+STM32_ETH_MACA3HR_OFFSET) -#define STM32_ETH_MACA3LR (STM32_ETHERNET_BASE+STM32_ETH_MACA3LR_OFFSET) - -/* MMC Registers */ - -#define STM32_ETH_MMCC (STM32_ETHERNET_BASE+STM32_ETH_MMCCR_OFFSET) -#define STM32_ETH_MMCRIR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIR_OFFSET) -#define STM32_ETH_MMCTIR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIR_OFFSET) -#define STM32_ETH_MMCRIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCRIMR_OFFSET) -#define STM32_ETH_MMCTIMR (STM32_ETHERNET_BASE+STM32_ETH_MMCTIMR_OFFSET) -#define STM32_ETH_MMCTGFSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFSCCR_OFFSET) -#define STM32_ETH_MMCTGFMSCCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFMSCCR_OFFSET) -#define STM32_ETH_MMCTGFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCTGFCR_OFFSET) -#define STM32_ETH_MMCRFCECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFCECR_OFFSET) -#define STM32_ETH_MMCRFAECR (STM32_ETHERNET_BASE+STM32_ETH_MMCRFAECR_OFFSET) -#define STM32_ETH_MMCRGUFCR (STM32_ETHERNET_BASE+STM32_ETH_MMCRGUFCR_OFFSET) - -/* IEEE 1588 time stamp registers */ - -#define STM32_ETH_PTPTSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSCR_OFFSET) -#define STM32_ETH_PTPSSIR (STM32_ETHERNET_BASE+STM32_ETH_PTPSSIR_OFFSET) -#define STM32_ETH_PTPTSHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHR_OFFSET) -#define STM32_ETH_PTPTSLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLR_OFFSET) -#define STM32_ETH_PTPTSHUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSHUR_OFFSET) -#define STM32_ETH_PTPTSLUR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSLUR_OFFSET) -#define STM32_ETH_PTPTSAR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSAR_OFFSET) -#define STM32_ETH_PTPTTHR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTHR_OFFSET) -#define STM32_ETH_PTPTTLR (STM32_ETHERNET_BASE+STM32_ETH_PTPTTLR_OFFSET) -#define STM32_ETH_PTPTSSR (STM32_ETHERNET_BASE+STM32_ETH_PTPTSSR_OFFSET) -#define STM32_ETH_PTPPPSCR (STM32_ETHERNET_BASE+STM32_ETH_PTPPPSCR_OFFSET) - -/* DMA Registers */ - -#define STM32_ETH_DMABMR (STM32_ETHERNET_BASE+STM32_ETH_DMABMR_OFFSET) -#define STM32_ETH_DMATPDR (STM32_ETHERNET_BASE+STM32_ETH_DMATPDR_OFFSET) -#define STM32_ETH_DMARPDR (STM32_ETHERNET_BASE+STM32_ETH_DMARPDR_OFFSET) -#define STM32_ETH_DMARDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMARDLAR_OFFSET) -#define STM32_ETH_DMATDLAR (STM32_ETHERNET_BASE+STM32_ETH_DMATDLAR_OFFSET) -#define STM32_ETH_DMASR (STM32_ETHERNET_BASE+STM32_ETH_DMASR_OFFSET) -#define STM32_ETH_DMAOMR (STM32_ETHERNET_BASE+STM32_ETH_DMAOMR_OFFSET) -#define STM32_ETH_DMAIER (STM32_ETHERNET_BASE+STM32_ETH_DMAIER_OFFSET) -#define STM32_ETH_DMAMFBOC (STM32_ETHERNET_BASE+STM32_ETH_DMAMFBOC_OFFSET) -#define STM32_ETH_DMARSWTR (STM32_ETHERNET_BASE+STM32_ETH_DMARSWTR_OFFSET) -#define STM32_ETH_DMACHTDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTDR_OFFSET) -#define STM32_ETH_DMACHRDR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRDR_OFFSET) -#define STM32_ETH_DMACHTBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHTBAR_OFFSET) -#define STM32_ETH_DMACHRBAR (STM32_ETHERNET_BASE+STM32_ETH_DMACHRBAR_OFFSET) - -/* Register Bit-Field Definitions *******************************************/ - -/* MAC Registers */ - -/* Ethernet MAC configuration register */ - -#define ETH_MACCR_RE (1 << 2) /* Bit 2: Receiver enable */ -#define ETH_MACCR_TE (1 << 3) /* Bit 3: Transmitter enable */ -#define ETH_MACCR_DC (1 << 4) /* Bit 4: Deferral check */ -#define ETH_MACCR_BL_SHIFT (5) /* Bits 5-6: Back-off limit */ -#define ETH_MACCR_BL_MASK (3 << ETH_MACCR_BL_SHIFT) -# define ETH_MACCR_BL_10 (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */ -# define ETH_MACCR_BL_8 (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */ -# define ETH_MACCR_BL_4 (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */ -# define ETH_MACCR_BL_1 (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */ - -#define ETH_MACCR_APCS (1 << 7) /* Bit 7: Automatic pad/CRC stripping */ -#define ETH_MACCR_RD (1 << 9) /* Bit 9: Retry disable */ -#define ETH_MACCR_IPCO (1 << 10) /* Bit 10: IPv4 checksum offload */ -#define ETH_MACCR_DM (1 << 11) /* Bit 11: Duplex mode */ -#define ETH_MACCR_LM (1 << 12) /* Bit 12: Loopback mode */ -#define ETH_MACCR_ROD (1 << 13) /* Bit 13: Receive own disable */ -#define ETH_MACCR_FES (1 << 14) /* Bit 14: Fast Ethernet speed */ -#define ETH_MACCR_CSD (1 << 16) /* Bit 16: Carrier sense disable */ -#define ETH_MACCR_IFG_SHIFT (17) /* Bits 17-19: Interframe gap */ -#define ETH_MACCR_IFG_MASK (7 << ETH_MACCR_IFG_SHIFT) -# define ETH_MACCR_IFG(n) ((12-((n) >> 3)) << ETH_MACCR_IFG_SHIFT) /* n bit times, n=40,48,..96 */ - -#define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ -#define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ -#endif - -/* Ethernet MAC frame filter register */ - -#define ETH_MACFFR_PM (1 << 0) /* Bit 0: Promiscuous mode */ -#define ETH_MACFFR_HU (1 << 1) /* Bit 1: Hash unicast */ -#define ETH_MACFFR_HM (1 << 2) /* Bit 2: Hash multicast */ -#define ETH_MACFFR_DAIF (1 << 3) /* Bit 3: Destination address inverse filtering */ -#define ETH_MACFFR_PAM (1 << 4) /* Bit 4: Pass all multicast */ -#define ETH_MACFFR_BFD (1 << 5) /* Bit 5: Broadcast frames disable */ -#define ETH_MACFFR_PCF_SHIFT (6) /* Bits 6-7: Pass control frames */ -#define ETH_MACFFR_PCF_MASK (3 << ETH_MACFFR_PCF_SHIFT) -# define ETH_MACFFR_PCF_NONE (0 << ETH_MACFFR_PCF_SHIFT) /* Prevents all control frames */ -# define ETH_MACFFR_PCF_PAUSE (1 << ETH_MACFFR_PCF_SHIFT) /* Prevents all except Pause control frames */ -# define ETH_MACFFR_PCF_ALL (2 << ETH_MACFFR_PCF_SHIFT) /* Forwards all control frames */ -# define ETH_MACFFR_PCF_FILTER (3 << ETH_MACFFR_PCF_SHIFT) /* Forwards all that pass address filter */ - -#define ETH_MACFFR_SAIF (1 << 8) /* Bit 8: Source address inverse filtering */ -#define ETH_MACFFR_SAF (1 << 9) /* Bit 9: Source address filter */ -#define ETH_MACFFR_HPF (1 << 10) /* Bit 10: Hash or perfect filter */ -#define ETH_MACFFR_RA (1 << 31) /* Bit 31: Receive all */ - -/* Ethernet MAC hash table high/low registers (32-bit values) */ - -/* Ethernet MAC MII address register */ - -#define ETH_MACMIIAR_MB (1 << 0) /* Bit 0: MII busy */ -#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */ -#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */ -#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT) -#if 0 /* Per the reference manual */ -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */ -# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ -#else /* Per the driver example */ -# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */ -# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */ -# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */ -# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */ -# define ETH_MACMIIAR_CR_150_180 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-180 MHz HCLK/102 */ -#endif -#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */ -#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT) -#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */ -#define ETH_MACMIIAR_PA_MASK (31 << ETH_MACMIIAR_PA_SHIFT) - -/* Ethernet MAC MII data register */ - -#define ETH_MACMIIDR_MASK (0xffff) - -/* Ethernet MAC flow control register */ - -#define ETH_MACFCR_FCB_BPA (1 << 0) /* Bit 0: Flow control busy/back pressure activate */ -#define ETH_MACFCR_TFCE (1 << 1) /* Bit 1: Transmit flow control enable */ -#define ETH_MACFCR_RFCE (1 << 2) /* Bit 2: Receive flow control enable */ -#define ETH_MACFCR_UPFD (1 << 3) /* Bit 3: Unicast pause frame detect */ -#define ETH_MACFCR_PLT_SHIFT (4) /* Bits 4-5: Pause low threshold */ -#define ETH_MACFCR_PLT_MASK (3 << ETH_MACFCR_PLT_SHIFT) -# define ETH_MACFCR_PLT_M4 (0 << ETH_MACFCR_PLT_SHIFT) /* 00 Pause - 4 slot times */ -# define ETH_MACFCR_PLT_M28 (1 << ETH_MACFCR_PLT_SHIFT) /* 01 Pause - 28 slot times */ -# define ETH_MACFCR_PLT_M144 (2 << ETH_MACFCR_PLT_SHIFT) /* 10 Pause - 144 slot times */ -# define ETH_MACFCR_PLT_M256 (3 << ETH_MACFCR_PLT_SHIFT) /* 11 Pause -s 256 slot times */ - -#define ETH_MACFCR_ZQPD (1 << 7) /* Bit 7: Zero-quanta pause disable */ -#define ETH_MACFCR_PT_SHIFT (16) /* Bits 16-31: Pause time */ -#define ETH_MACFCR_PT_MASK (0xffff << ETH_MACFCR_PT_SHIFT) - -/* Ethernet MAC VLAN tag register */ - -#define ETH_MACVLANTR_VLANTI_SHIFT (0) /* Bits 0-15: VLAN tag identifier (for receive frames) */ -#define ETH_MACVLANTR_VLANTI_MASK (0xffff << ETH_MACVLANTR_VLANTI_SHIFT) -#define ETH_MACVLANTR_VLANTC (1 << 16) /* Bit 16: 12-bit VLAN tag comparison */ - -/* Ethernet MAC remote wakeup frame filter reg. Provides 32-bit access to - * remote remote wake-up filters. - */ - -/* Ethernet MAC PMT control and status register */ - -#define ETH_MACPMTCSR_PD (1 << 0) /* Bit 0: Power down */ -#define ETH_MACPMTCSR_MPE (1 << 1) /* Bit 1: Magic Packet enable */ -#define ETH_MACPMTCSR_WFE (1 << 2) /* Bit 2: Wakeup frame enable */ -#define ETH_MACPMTCSR_MPR (1 << 5) /* Bit 5: Magic packet received */ -#define ETH_MACPMTCSR_WFR (1 << 6) /* Bit 6: Wakeup frame received */ -#define ETH_MACPMTCSR_GU (1 << 9) /* Bit 9: Global unicast */ - -/* Ethernet MAC debug register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) - -#define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ -#define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ -#define ETH_MACDBGR_MSFRWCS_MASK (3 << ETH_MACDBGR_MSFRWCS_SHIFT) - -#define ETH_MACDBGR_RFWRA (1 << 4) /* Bit 4: Rx FIFO write controller active */ -#define ETH_MACDBGR_RFRCS_SHIFT (5) /* Bits 5-6: Rx FIFO read controller status */ -#define ETH_MACDBGR_RFRCS_MASK (3 << ETH_MACDBGR_RFRCS_SHIFT) -# define ETH_MACDBGR_RFRCS_IDLE (0 << ETH_MACDBGR_RFRCS_SHIFT) /* 00: IDLE state */ -# define ETH_MACDBGR_RFRCS_RFRAME (1 << ETH_MACDBGR_RFRCS_SHIFT) /* 01: Reading frame data */ -# define ETH_MACDBGR_RFRCS_RSTATUS (2 << ETH_MACDBGR_RFRCS_SHIFT) /* 10: Reading frame status (or time-stamp) */ -# define ETH_MACDBGR_RFRCS_FLUSHING (3 << ETH_MACDBGR_RFRCS_SHIFT) /* 11: Flushing the frame data and status */ - -#define ETH_MACDBGR_RFFL_SHIFT (8) /* Bits 8-9: Rx FIFO fill level */ -#define ETH_MACDBGR_RFFL_MASK (3 << ETH_MACDBGR_RFFL_SHIFT) -# define ETH_MACDBGR_RFFL_EMPTY (0 << ETH_MACDBGR_RFFL_SHIFT) /* 00: RxFIFO empty */ -# define ETH_MACDBGR_RFFL_DEACT (1 << ETH_MACDBGR_RFFL_SHIFT) /* 01: RxFIFO fill-level below flow-control de-activate threshold */ -# define ETH_MACDBGR_RFFL_ACTIV (2 << ETH_MACDBGR_RFFL_SHIFT) /* 10: RxFIFO fill-level above flow-control activate threshold */ -# define ETH_MACDBGR_RFFL_FULL (3 << ETH_MACDBGR_RFFL_SHIFT) /* 11: RxFIFO full */ - -#define ETH_MACDBGR_MMTEA (1 << 16) /* Bit 16: MAC MII transmit engine active */ -#define ETH_MACDBGR_MTFCS_SHIFT (17) /* Bits 17-18: MAC transmit frame controller status */ -#define ETH_MACDBGR_MTFCS_MASK (3 << ETH_MACDBGR_MTFCS_SHIFT) -# define ETH_MACDBGR_MTFCS_IDLE (0 << ETH_MACDBGR_MTFCS_SHIFT) /* 00: Idle */ -# define ETH_MACDBGR_MTFCS_WAITING (1 << ETH_MACDBGR_MTFCS_SHIFT) /* 01: Waiting for Status of previous frame or IFG/backoff period to be over */ -# define ETH_MACDBGR_MTFCS_PAUSE (2 << ETH_MACDBGR_MTFCS_SHIFT) /* 10: Generating and transmitting a Pause control frame */ -# define ETH_MACDBGR_MTFCS_FRAME (3 << ETH_MACDBGR_MTFCS_SHIFT) /* 11: Transferring input frame for transmission */ - -#define ETH_MACDBGR_MTP (1 << 19) /* Bit 19: MAC transmitter in pause */ -#define ETH_MACDBGR_TFRS_SHIFT (20) /* Bits 20-21: Tx FIFO read status */ -#define ETH_MACDBGR_TFRS_MASK (3 << ETH_MACDBGR_TFRS_SHIFT) -# define ETH_MACDBGR_TFRS_IDLE (0 << ETH_MACDBGR_TFRS_SHIFT) /* 00: Idle state */ -# define ETH_MACDBGR_TFRS_READ (1 << ETH_MACDBGR_TFRS_SHIFT) /* 01: Read state */ -# define ETH_MACDBGR_TFRS_WAITING (2 << ETH_MACDBGR_TFRS_SHIFT) /* 10: Waiting for TxStatus from MAC transmitter */ -# define ETH_MACDBGR_TFRS_WRITING (3 << ETH_MACDBGR_TFRS_SHIFT) /* 11: Writing the received TxStatus or flushing the TxFIFO */ - -#define ETH_MACDBGR_TFWA (1 << 22) /* Bit 22: Tx FIFO write active */ -#define ETH_MACDBGR_TFNE (1 << 24) /* Bit 24: Tx FIFO not empty */ -#define ETH_MACDBGR_TFF (1 << 25) /* Bit 25: Tx FIFO full */ - -#endif - -/* Ethernet MAC interrupt status register */ - -#define ETH_MACSR_PMTS (1 << 3) /* Bit 3: PMT status */ -#define ETH_MACSR_MMCS (1 << 4) /* Bit 4: MMC status */ -#define ETH_MACSR_MMCRS (1 << 5) /* Bit 5: MMC receive status */ -#define ETH_MACSR_MMCTS (1 << 6) /* Bit 6: MMC transmit status */ -#define ETH_MACSR_TSTS (1 << 9) /* Bit 9: Time stamp trigger status */ - -/* Ethernet MAC interrupt mask register */ - -#define ETH_MACIMR_PMTIM (1 << 3) /* Bit 3: PMT interrupt mask */ -#define ETH_MACIMR_TSTIM (1 << 9) /* Bit 9: Time stamp trigger interrupt mask */ -#define ETH_MACIMR_ALLINTS (ETH_MACIMR_PMTIM|ETH_MACIMR_TSTIM) - -/* Ethernet MAC address 0 high register */ - -#define ETH_MACA0HR_MACA0H_SHIFT (0) /* Bits 0-15: MAC address0 high [47:32] */ -#define ETH_MACA0HR_MACA0H_MASK (0xffff << ETH_MACA0HR_MACA0H_SHIFT) -#define ETH_MACA0HR_MO (1 << 31) /* Bit 31:Always */ - -/* Ethernet MAC address 0 low register (MAC address0 low [31:0]) */ - -/* Ethernet MAC address 1 high register */ - -#define ETH_MACA1HR_MACA1H_SHIFT (0) /* Bits 0-15: MAC address1 high [47:32] */ -#define ETH_MACA1HR_MACA1H_MASK (0xffff << ETH_MACA1HR_MACA1H_SHIFT) -#define ETH_MACA1HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA1HR_MBC_MASK (0x3f << ETH_MACA1HR_MBC_SHIFT) -# define ETH_MACA1HR_MBC_40_47 (0x20 << ETH_MACA1HR_MBC_SHIFT) /* Bit 29: ETH_MACA1HR [8-15] */ -# define ETH_MACA1HR_MBC_32_39 (0x10 << ETH_MACA1HR_MBC_SHIFT) /* Bit 28: ETH_MACA1HR [0-7] */ -# define ETH_MACA1HR_MBC_24_31 (0x08 << ETH_MACA1HR_MBC_SHIFT) /* Bit 27: ETH_MACA1LR [24-31] */ -# define ETH_MACA1HR_MBC_16_23 (0x04 << ETH_MACA1HR_MBC_SHIFT) /* Bit 26: ETH_MACA1LR [16-23] */ -# define ETH_MACA1HR_MBC_8_15 (0x02 << ETH_MACA1HR_MBC_SHIFT) /* Bit 25: ETH_MACA1LR [8-15] */ -# define ETH_MACA1HR_MBC_0_7 (0x01 << ETH_MACA1HR_MBC_SHIFT) /* Bit 24: ETH_MACA1LR [0-7] */ - -#define ETH_MACA1HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA1HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address1 low register (MAC address1 low [31:0]) */ - -/* Ethernet MAC address 2 high register */ - -#define ETH_MACA2HR_MACA2H_SHIFT (0) /* Bits 0-15: MAC address2 high [47:32] */ -#define ETH_MACA2HR_MACA2H_MASK (0xffff << ETH_MACA2HR_MACA2H_SHIFT) -#define ETH_MACA2HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA2HR_MBC_MASK (0x3f << ETH_MACA2HR_MBC_SHIFT) -# define ETH_MACA2HR_MBC_40_47 (0x20 << ETH_MACA2HR_MBC_SHIFT) /* Bit 29: ETH_MACA2HR [8-15] */ -# define ETH_MACA2HR_MBC_32_39 (0x10 << ETH_MACA2HR_MBC_SHIFT) /* Bit 28: ETH_MACA2HR [0-7] */ -# define ETH_MACA2HR_MBC_24_31 (0x08 << ETH_MACA2HR_MBC_SHIFT) /* Bit 27: ETH_MACA2LR [24-31] */ -# define ETH_MACA2HR_MBC_16_23 (0x04 << ETH_MACA2HR_MBC_SHIFT) /* Bit 26: ETH_MACA2LR [16-23] */ -# define ETH_MACA2HR_MBC_8_15 (0x02 << ETH_MACA2HR_MBC_SHIFT) /* Bit 25: ETH_MACA2LR [8-15] */ -# define ETH_MACA2HR_MBC_0_7 (0x01 << ETH_MACA2HR_MBC_SHIFT) /* Bit 24: ETH_MACA2LR [0-7] */ - -#define ETH_MACA2HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA2HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address 2 low register (MAC address2 low [31:0]) */ - -/* Ethernet MAC address 3 high register */ - -#define ETH_MACA3HR_MACA3H_SHIFT (0) /* Bits 0-15: MAC address3 high [47:32] */ -#define ETH_MACA3HR_MACA3H_MASK (0xffff << ETH_MACA3HR_MACA3H_SHIFT) -#define ETH_MACA3HR_MBC_SHIFT (24) /* Bits 24-29: Mask byte control */ -#define ETH_MACA3HR_MBC_MASK (0x3f << ETH_MACA3HR_MBC_SHIFT) -# define ETH_MACA3HR_MBC_40_47 (0x20 << ETH_MACA3HR_MBC_SHIFT) /* Bit 29: ETH_MACA3HR [8-15] */ -# define ETH_MACA3HR_MBC_32_39 (0x10 << ETH_MACA3HR_MBC_SHIFT) /* Bit 28: ETH_MACA3HR [0-7] */ -# define ETH_MACA3HR_MBC_24_31 (0x08 << ETH_MACA3HR_MBC_SHIFT) /* Bit 27: ETH_MACA3LR [24-31] */ -# define ETH_MACA3HR_MBC_16_23 (0x04 << ETH_MACA3HR_MBC_SHIFT) /* Bit 26: ETH_MACA3LR [16-23] */ -# define ETH_MACA3HR_MBC_8_15 (0x02 << ETH_MACA3HR_MBC_SHIFT) /* Bit 25: ETH_MACA3LR [8-15] */ -# define ETH_MACA3HR_MBC_0_7 (0x01 << ETH_MACA3HR_MBC_SHIFT) /* Bit 24: ETH_MACA3LR [0-7] */ - -#define ETH_MACA3HR_SA (1 << 30) /* Bit 30: Source address */ -#define ETH_MACA3HR_AE (1 << 31) /* Bit 31: Address enable */ - -/* Ethernet MAC address 3 low register (MAC address3 low [31:0]) */ - -/* MMC Registers */ - -/* Ethernet MMC control register */ - -#define ETH_MMCCR_CR (1 << 0) /* Bit 0: Counter reset */ -#define ETH_MMCCR_CSR (1 << 1) /* Bit 1: Counter stop rollover */ -#define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ -#define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ -#define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ -#endif - -/* Ethernet MMC receive interrupt and interrupt mask registers */ - -#define ETH_MMCRI_RFCE (1 << 5) /* Bit 5: Received frame CRC error */ -#define ETH_MMCRI_RFAE (1 << 6) /* Bit 6: Received frames alignment error */ -#define ETH_MMCRI_RGUF (1 << 17) /* Bit 17: Received good unicast frames */ - -/* Ethernet MMC transmit interrupt and interrupt mask register */ - -#define ETH_MMCTI_TGFSC (1 << 14) /* Bit 14: Transmitted good frames single collision */ -#define ETH_MMCTI_TGFMSC (1 << 15) /* Bit 15: Transmitted good frames more single collision */ -#define ETH_MMCTI_TGF (1 << 21) /* Bit 21: Transmitted good frames */ - -/* 32-bit counters: - * - * Ethernet MMC transmitted good frames counter register (single collision) - * Ethernet MMC transmitted good frames counter register (multiple-collision) - * Ethernet MMC transmitted good frames counter register - * Ethernet MMC received frames with CRC error counter register - * Ethernet MMC received frames with alignment error counter - * MMC received good unicast frames counter register - */ - -/* IEEE 1588 time stamp registers */ - -/* Ethernet PTP time stamp control register */ - -#define ETH_PTPTSCR_TSE (1 << 0) /* Bit 0: Time stamp enable */ -#define ETH_PTPTSCR_TSFCU (1 << 1) /* Bit 1: Time stamp fine or coarse update */ -#define ETH_PTPTSCR_TSSTI (1 << 2) /* Bit 2: Time stamp system time initialize */ -#define ETH_PTPTSCR_TSSTU (1 << 3) /* Bit 3: Time stamp system time update */ -#define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ -#define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -#define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ -#define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ -#define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSCR_TSSPTPOEFE (1 << 11) /* Bit 11: Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSCR_TSSIPV6FE (1 << 12) /* Bit 12: Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSCR_TSSIPV4FE (1 << 13) /* Bit 13: Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSCR_TSSEME (1 << 14) /* Bit 14: Time stamp snapshot for event message enable */ -#define ETH_PTPTSCR_TSSMRME (1 << 15) /* Bit 15: Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSCR_TSCNT_SHIFT (16) /* Bits 16-17: Time stamp clock node type */ -#define ETH_PTPTSCR_TSCNT_MASK (3 << ETH_PTPTSCR_TSCNT_SHIFT) -# define ETH_PTPTSCR_TSCNT_ORDINARY (0 << ETH_PTPTSCR_TSCNT_SHIFT) /* 00: Ordinary clock */ -# define ETH_PTPTSCR_TSCNT_BOUNDARY (1 << ETH_PTPTSCR_TSCNT_SHIFT) /* 01: Boundary clock */ -# define ETH_PTPTSCR_TSCNT_E2E (2 << ETH_PTPTSCR_TSCNT_SHIFT) /* 10: End-to-end transparent clock */ -# define ETH_PTPTSCR_TSCNT_P2P (3 << ETH_PTPTSCR_TSCNT_SHIFT) /* 11: Peer-to-peer transparent clock */ - -#define ETH_PTPTSCR_TSPFFMAE (1 << 18) /* Bit 18: Time stamp PTP frame filtering MAC address enable */ -#endif - -/* Ethernet PTP subsecond increment register */ - -#define ETH_PTPSSIR_MASK (0xff) - -/* Ethernet PTP time stamp high register (32-bit) */ - -/* Ethernet PTP time stamp low register */ - -#define ETH_PTPTSLR_STPNS (1 << 31) /* Bit 31: System time positive or negative sign */ -#define ETH_PTPTSLR_MASK (0x7fffffff) /* Bits 0-30: System time subseconds */ - -/* Ethernet PTP time stamp high update register (32-bit) */ - -/* Ethernet PTP time stamp low update register */ - -#define ETH_PTPTSLU_TSUPNS (1 << 31) /* Bit 31: System time positive or negative sign */ -#define ETH_PTPTSLU_MASK (0x7fffffff) /* Bits 0-30: Time stamp update subsecond */ - -/* Ethernet PTP time stamp addend register (32-bit) */ - -/* Ethernet PTP target time high register (32-bit) */ - -/* Ethernet PTP target time low register (32-bit) */ - -/* Ethernet PTP time stamp status register */ - -#define ETH_PTPTSSR_TSSO (1 << 0) /* Bit 0: Time stamp second overflow */ -#define ETH_PTPTSSR_TSTTR (1 << 1) /* Bit 1: Time stamp target time reached */ - -/* Ethernet PTP PPS control register */ - -#define ETH_PTPPPSCR_PPSFREQ_SHIFT (0) /* Bits 0-3: PPS frequency selection */ -#define ETH_PTPPPSCR_PPSFREQ_MASK (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) -# define ETH_PTPPPSCR_PPSFREQ_1HZ (0 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1 Hz with pulse width of 125/100 ms for binary/digital rollover */ -# define ETH_PTPPPSCR_PPSFREQ_2HZ (1 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_4HZ (2 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_8HZ (3 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_16HZ (4 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_32HZ (5 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_64HZ (6 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 64 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_128HZ (7 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 128 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_256HZ (8 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 256 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_512HZ (9 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 512 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_1KHZ (10 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 1024 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_2KHZ (11 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 2048 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_4KHZ (12 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 4096 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_8KHZ (13 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 8192 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_16KHZ (14 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 16384 Hz with 50% duty cycle */ -# define ETH_PTPPPSCR_PPSFREQ_32KHZ (15 << ETH_PTPPPSCR_PPSFREQ_SHIFT) /* 32768 Hz with 50% duty cycle */ - -/* DMA Registers */ - -/* Ethernet DMA bus mode register */ - -#define ETH_DMABMR_SR (1 << 0) /* Bit 0: Software reset */ -#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */ -#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */ -#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT) -# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT) -#define ETH_DMABMR_EDFE (1 << 7) /* Bit 7: Enhanced descriptor format enable */ -#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */ - -# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ -#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT) - -#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */ -#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT) -# define ETH_DMABMR_RTPR_1TO1 (0 << ETH_DMABMR_RTPR_SHIFT) /* 00: 1:1 */ -# define ETH_DMABMR_RTPR_2TO1 (1 << ETH_DMABMR_RTPR_SHIFT) /* 01: 2:1 */ -# define ETH_DMABMR_RTPR_3TO1 (2 << ETH_DMABMR_RTPR_SHIFT) /* 10: 3:1 */ -# define ETH_DMABMR_RTPR_4TO1 (3 << ETH_DMABMR_RTPR_SHIFT) /* 11: 4:1 */ - -#define ETH_DMABMR_FB (1 << 16) /* Bit 16: Fixed burst */ -#define ETH_DMABMR_RDP_SHIFT (17) /* Bits 17-22: Rx DMA PBL */ -#define ETH_DMABMR_RDP_MASK (0x3f << ETH_DMABMR_RDP_SHIFT) -# define ETH_DMABMR_RDP(n) ((n) << ETH_DMABMR_RDP_SHIFT) /* n=1, 2, 4, 8, 16, 32 */ - -#define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ -#define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ -#define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ -#endif - -/* Ethernet DMA transmit poll demand register (32-bit) */ - -/* Ethernet DMA receive poll demand register (32-bit) */ - -/* Ethernet DMA receive descriptor list address register (32-bit address) */ - -/* Ethernet DMA transmit descriptor list address register (32-bit address) */ - -/* Interrupt bit definitions common between the DMA status register (DMASR) - * and the DMA interrupt enable register (DMAIER). - */ - -#define ETH_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ -#define ETH_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */ -#define ETH_DMAINT_TBUI (1 << 2) /* Bit 2: Transmit buffer unavailable interrupt */ -#define ETH_DMAINT_TJTI (1 << 3) /* Bit 3: Transmit jabber timeout interrupt */ -#define ETH_DMAINT_ROI (1 << 4) /* Bit 4: Overflow interrupt */ -#define ETH_DMAINT_TUI (1 << 5) /* Bit 5: Underflow interrupt */ -#define ETH_DMAINT_RI (1 << 6) /* Bit 6: Receive interrupt */ -#define ETH_DMAINT_RBUI (1 << 7) /* Bit 7: Receive buffer unavailable interrupt */ -#define ETH_DMAINT_RPSI (1 << 8) /* Bit 8: Receive process stopped interrupt */ -#define ETH_DMAINT_RWTI (1 << 9) /* Bit 9: Receive watchdog timeout interrupt */ -#define ETH_DMAINT_ETI (1 << 10) /* Bit 10: Early transmit interrupt */ -#define ETH_DMAINT_FBEI (1 << 13) /* Bit 13: Fatal bus error interrupt */ -#define ETH_DMAINT_ERI (1 << 14) /* Bit 14: Early receive interrupt */ -#define ETH_DMAINT_AIS (1 << 15) /* Bit 15: Abnormal interrupt summary */ -#define ETH_DMAINT_NIS (1 << 16) /* Bit 16: Normal interrupt summary */ - -/* Ethernet DMA status register (in addition to the interrupt bits above */ - -#define ETH_DMASR_RPS_SHIFT (17) /* Bits 17-19: Receive process state */ -#define ETH_DMASR_RPS_MASK (7 << ETH_DMASR_RPS_SHIFT) -# define ETH_DMASR_RPS_STOPPED (0 << ETH_DMASR_RPS_SHIFT) /* 000: Stopped: Reset or Stop Receive Command issued */ -# define ETH_DMASR_RPS_RXDESC (1 << ETH_DMASR_RPS_SHIFT) /* 001: Running: Fetching receive transfer descriptor */ -# define ETH_DMASR_RPS_WAITING (3 << ETH_DMASR_RPS_SHIFT) /* 011: Running: Waiting for receive packet */ -# define ETH_DMASR_RPS_SUSPENDED (4 << ETH_DMASR_RPS_SHIFT) /* 100: Suspended: Receive descriptor unavailable */ -# define ETH_DMASR_RPS_CLOSING (5 << ETH_DMASR_RPS_SHIFT) /* 101: Running: Closing receive descriptor */ -# define ETH_DMASR_RPS_TRANSFER (6 << ETH_DMASR_RPS_SHIFT) /* 111: Running: Transferring the receive data to memory */ - -#define ETH_DMASR_TPS_SHIFT (20) /* Bits 20-22: Transmit process state */ -#define ETH_DMASR_TPS_MASK (7 << ETH_DMASR_TPS_SHIFT) -# define ETH_DMASR_TPS_STOPPED (0 << ETH_DMASR_TPS_SHIFT) /* 000: Stopped; Reset or Stop Transmit Command issued */ -# define ETH_DMASR_TPS_TXDESC (1 << ETH_DMASR_TPS_SHIFT) /* 001: Running; Fetching transmit transfer descriptor */ -# define ETH_DMASR_TPS_WAITING (2 << ETH_DMASR_TPS_SHIFT) /* 010: Running; Waiting for status */ -# define ETH_DMASR_TPS_TRANSFER (3 << ETH_DMASR_TPS_SHIFT) /* 011: Running; Reading data and queuing to transmit (TxFIFO) */ -# define ETH_DMASR_TPS_SUSPENDED (6 << ETH_DMASR_TPS_SHIFT) /* 110: Suspended; Transmit descriptor unavailable or buffer underflow */ -# define ETH_DMASR_TPS_CLOSING (7 << ETH_DMASR_TPS_SHIFT) /* 111: Running; Closing transmit descriptor */ - -#define ETH_DMASR_EBS_SHIFT (23) /* Bits 23-25: Error bits status */ -#define ETH_DMASR_EBS_MASK (7 << ETH_DMASR_EBS_SHIFT) -#define ETH_DMASR_EBS_TXDMS (1 << ETH_DMASR_EBS_SHIFT) /* Bit 23 1 Error during data transfer by TxDMA */ -#define ETH_DMASR_EBS_READ (2 << ETH_DMASR_EBS_SHIFT) /* Bit 24 1 Error during read transfer */ -#define ETH_DMASR_EBS_DESC (4 << ETH_DMASR_EBS_SHIFT) /* Bit 25 1 Error during descriptor access */ - -#define ETH_DMASR_MMCS (1 << 27) /* Bit 27: MMC status */ -#define ETH_DMASR_PMTS (1 << 28) /* Bit 28: PMT status */ -#define ETH_DMASR_TSTS (1 << 29) /* Bit 29: Time stamp trigger status */ - -/* Ethernet DMA operation mode register */ - -#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */ -#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */ -#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */ -#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT) -# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT) -#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */ -#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */ -#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */ -#define ETH_DMAOMR_TTC_SHIFT (14) /* Bits 14-16: Transmit threshold control */ -#define ETH_DMAOMR_TTC_MASK (7 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_64 (0 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_128 (1 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_192 (2 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_256 (3 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_40 (4 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_32 (5 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_24 (6 << ETH_DMAOMR_TTC_SHIFT) -# define ETH_DMAOMR_TTC_16 (7 << ETH_DMAOMR_TTC_SHIFT) -#define ETH_DMAOMR_FTF (1 << 20) /* Bit 20: Flush transmit FIFO */ -#define ETH_DMAOMR_TSF (1 << 21) /* Bit 21: Transmit store and forward */ -#define ETH_DMAOMR_DFRF (1 << 24) /* Bit 24: Disable flushing of received frames */ -#define ETH_DMAOMR_RSF (1 << 25) /* Bit 25: Receive store and forward */ -#define ETH_DMAOMR_DTCEFD (1 << 26) /* Bit 26: Dropping of TCP/IP checksum error frames disable */ - -/* Ethernet DMA missed frame and buffer overflow counter register */ - -#define ETH_DMAMFBOC_MFC_SHIFT (0) /* Bits 0-15: Missed frames by the controller */ -#define ETH_DMAMFBOC_MFC_MASK (0xffff << ETH_DMAMFBOC_MFC_SHIFT) -#define ETH_DMAMFBOC_OMFC (1 << 16) /* Bit 16: Overflow bit for missed frame counter */ -#define ETH_DMAMFBOC_MFA_SHIFT (17) /* Bits 17-27: Missed frames by the application */ -#define ETH_DMAMFBOC_MFA_MASK (0x7ff << ETH_DMAMFBOC_MFA_SHIFT) -#define ETH_DMAMFBOC_OFOC (1 << 28) /* Bit 28: Overflow bit for FIFO overflow counter */ - -/* Ethernet DMA receive status watchdog timer register */ - -#define ETH_DMARSWTR_MASK (0xff) - -/* Ethernet DMA current host transmit descriptor register - * (32-bit address) - */ - -/* Ethernet DMA current host receive descriptor register - * (32-bit address) - */ - -/* Ethernet DMA current host transmit buffer address register - * (32-bit address) - */ - -/* Ethernet DMA current host receive buffer address register - * (32-bit address) - */ - -/* DMA Descriptors **********************************************************/ - -/* TDES0: Transmit descriptor Word0 */ - -#define ETH_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ -#define ETH_TDES0_UF (1 << 1) /* Bit 1: Underflow error */ -#define ETH_TDES0_ED (1 << 2) /* Bit 2: Excessive deferral */ -#define ETH_TDES0_CC_SHIFT (3) /* Bits 3-6: Collision count */ -#define ETH_TDES0_CC_MASK (15 << ETH_TDES0_CC_SHIFT) -#define ETH_TDES0_VF (1 << 7) /* Bit 7: VLAN frame */ -#define ETH_TDES0_EC (1 << 8) /* Bit 8: Excessive collision */ -#define ETH_TDES0_LCO (1 << 9) /* Bit 9: Late collision */ -#define ETH_TDES0_NC (1 << 10) /* Bit 10: No carrier */ -#define ETH_TDES0_LCA (1 << 11) /* Bit 11: Loss of carrier */ -#define ETH_TDES0_IPE (1 << 12) /* Bit 12: IP payload error */ -#define ETH_TDES0_FF (1 << 13) /* Bit 13: Frame flushed */ -#define ETH_TDES0_JT (1 << 14) /* Bit 14: Jabber timeout */ -#define ETH_TDES0_ES (1 << 15) /* Bit 15: Error summary */ -#define ETH_TDES0_IHE (1 << 16) /* Bit 16: IP header error */ -#define ETH_TDES0_TTSS (1 << 17) /* Bit 17: Transmit time stamp status */ -#define ETH_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ -#define ETH_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ -#define ETH_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ -#define ETH_TDES0_CIC_MASK (3 << ETH_TDES0_CIC_SHIFT) -# define ETH_TDES0_CIC_DISABLED (0 << ETH_TDES0_CIC_SHIFT) /* Checksum disabled */ -# define ETH_TDES0_CIC_IH (1 << ETH_TDES0_CIC_SHIFT) /* IP header checksum enabled */ -# define ETH_TDES0_CIC_IHPL (2 << ETH_TDES0_CIC_SHIFT) /* IP header and payload checksum enabled */ -# define ETH_TDES0_CIC_ALL (3 << ETH_TDES0_CIC_SHIFT) /* IP Header, payload, and pseudo-header checksum enabled */ - -#define ETH_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ -#define ETH_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ -#define ETH_TDES0_DC (1 << 27) /* Bit 27: Disable CRC */ -#define ETH_TDES0_FS (1 << 28) /* Bit 28: First segment */ -#define ETH_TDES0_LS (1 << 29) /* Bit 29: Last segment */ -#define ETH_TDES0_IC (1 << 30) /* Bit 30: Interrupt on completion */ -#define ETH_TDES0_OWN (1 << 31) /* Bit 31: Own bit */ - -/* TDES1: Transmit descriptor Word1 */ - -#define ETH_TDES1_TBS1_SHIFT (0) /* Bits 0-12: Transmit buffer 1 size */ -#define ETH_TDES1_TBS1_MASK (0x1fff << ETH_TDES1_TBS1_SHIFT) -#define ETH_TDES1_TBS2_SHIFT (16) /* Bits 16-28: Transmit buffer 2 size */ -#define ETH_TDES1_TBS2_MASK (0x1fff << ETH_TDES1_TBS2_SHIFT) - -/* TDES2: Transmit descriptor Word2 (32-bit address) */ - -/* TDES3: Transmit descriptor Word3 (32-bit address) */ - -/* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ - -/* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ - -/* RDES0: Receive descriptor Word0 */ - -#define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ -#endif -#define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ -#define ETH_RDES0_DBE (1 << 2) /* Bit 2: Dribble bit error */ -#define ETH_RDES0_RE (1 << 3) /* Bit 3: Receive error */ -#define ETH_RDES0_RWT (1 << 4) /* Bit 4: Receive watchdog timeout */ -#define ETH_RDES0_FT (1 << 5) /* Bit 5: Frame type */ -#define ETH_RDES0_LCO (1 << 6) /* Bit 6: Late collision */ -#define ETH_RDES0_TSV (1 << 7) /* Bit 7: Time stamp valid */ -#define ETH_RDES0_IPHCE (1 << 7) /* Bit 7: IPv header checksum error */ -#define ETH_RDES0_LS (1 << 8) /* Bit 8: Last descriptor */ -#define ETH_RDES0_FS (1 << 9) /* Bit 9: First descriptor */ -#define ETH_RDES0_VLAN (1 << 10) /* Bit 10: VLAN tag */ -#define ETH_RDES0_OE (1 << 11) /* Bit 11: Overflow error */ -#define ETH_RDES0_LE (1 << 12) /* Bit 12: Length error */ -#define ETH_RDES0_SAF (1 << 13) /* Bit 13: Source address filter fail */ -#define ETH_RDES0_DE (1 << 14) /* Bit 14: Descriptor error */ -#define ETH_RDES0_ES (1 << 15) /* Bit 15: Error summary */ -#define ETH_RDES0_FL_SHIFT (16) /* Bits 16-29: Frame length */ -#define ETH_RDES0_FL_MASK (0x3fff << ETH_RDES0_FL_SHIFT) -#define ETH_RDES0_AFM (1 << 30) /* Bit 30: Destination address filter fail */ -#define ETH_RDES0_OWN (1 << 31) /* Bit 31: Own bit */ - -/* RDES1: Receive descriptor Word1 */ - -#define ETH_RDES1_RBS1_SHIFT (0) /* Bits 0-12: Receive buffer 1 size */ -#define ETH_RDES1_RBS1_MASK (0x1fff << ETH_RDES1_RBS1_SHIFT) - /* Bit 13: Reserved */ -#define ETH_RDES1_RCH (1 << 14) /* Bit 14: Second address chained */ -#define ETH_RDES1_RER (1 << 15) /* Bit 15: Receive end of ring */ -#define ETH_RDES1_RBS2_SHIFT (16) /* Bits 16-28: Receive buffer 2 size */ -#define ETH_RDES1_RBS2_MASK (0x1fff << ETH_RDES1_RBS2_SHIFT) -#define ETH_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ - -/* RDES2: Receive descriptor Word2 (32-bit address) */ - -/* RDES3: Receive descriptor Word3 (32-bit address) */ - -/* RDES4: Receive descriptor Word4 */ - -#define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ -#define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) -# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ -# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ -# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ - -#define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ -#define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ -#define ETH_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ -#define ETH_RDES4_IPV4PR (1 << 6) /* Bit 6: IPv4 packet received */ -#define ETH_RDES4_IPV6PR (1 << 7) /* Bit 7: IPv6 packet received */ -#define ETH_RDES4_PMT_SHIFT (8) /* Bits 8-11: PTP message type */ -#define ETH_RDES4_PMT_MASK (15 << ETH_RDES4_PMT_SHIFT) -# define ETH_RDES4_PMT_NONE (0 << ETH_RDES4_PMT_SHIFT) /* No PTP message received */ -# define ETH_RDES4_PMT_SYNC (1 << ETH_RDES4_PMT_SHIFT) /* SYNC (all clock types) */ -# define ETH_RDES4_PMT_FOLLOWUP (2 << ETH_RDES4_PMT_SHIFT) /* Follow_Up (all clock types) */ -# define ETH_RDES4_PMT_DELAYREQ (3 << ETH_RDES4_PMT_SHIFT) /* Delay_Req (all clock types) */ -# define ETH_RDES4_PMT_DELAYRESP (4 << ETH_RDES4_PMT_SHIFT) /* Delay_Resp (all clock types) */ -# define ETH_RDES4_PMT_PDELREQAM (5 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Req (in peer-to-peer - * transparent clock) or Announce (in - * ordinary or boundary clock) */ -# define ETH_RDES4_PMT_PDELREQMM (6 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp (in peer-to-peer - * transparent clock) or Management (in - * ordinary or boundary clock) */ -# define ETH_RDES4_PMT_PDELREQFUS (7 << ETH_RDES4_PMT_SHIFT) /* Pdelay_Resp_Follow_Up (in - * peer-to-peer transparent clock) or - * Signaling (for ordinary or boundary - * clock) */ - -#define ETH_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ -#define ETH_RDES4_PV (1 << 13) /* Bit 13: PTP version */ - -/* RDES5: Receive descriptor Word5 - Reserved */ - -/* RDES6: Receive descriptor Word6 (32-bit time stamp) */ - -/* RDES7: Receive descriptor Word7 (32-bit time stamp) */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Ethernet TX DMA Descriptor */ - -struct eth_txdesc_s -{ - /* Normal DMA descriptor words */ - - volatile uint32_t tdes0; /* Status */ - volatile uint32_t tdes1; /* Control and buffer1/2 lengths */ - volatile uint32_t tdes2; /* Buffer1 address pointer */ - volatile uint32_t tdes3; /* Buffer2 or next descriptor address pointer */ - - /* Enhanced DMA descriptor words with time stamp */ - -#ifdef CONFIG_STM32_ETH_ENHANCEDDESC - volatile uint32_t tdes4; /* Reserved */ - volatile uint32_t tdes5; /* Reserved */ - volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ - volatile uint32_t tdes7; /* Time Stamp High value for transmit and receive */ -#endif -}; - -/* Ethernet RX DMA Descriptor */ - -struct eth_rxdesc_s -{ - volatile uint32_t rdes0; /* Status */ - volatile uint32_t rdes1; /* Control and buffer1/2 lengths */ - volatile uint32_t rdes2; /* Buffer1 address pointer */ - volatile uint32_t rdes3; /* Buffer2 or next descriptor address pointer */ - - /* Enhanced DMA descriptor words with time stamp and PTP support */ - -#ifdef CONFIG_STM32_ETH_ENHANCEDDESC - volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ - volatile uint32_t rdes5; /* Reserved */ - volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ - volatile uint32_t rdes7; /* Time Stamp High value for transmit and receive */ -#endif -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ASSEMBLY__ */ -#endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/stm32/hardware/stm32_fmc.h deleted file mode 100644 index 149b3ab6de91a..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_fmc.h +++ /dev/null @@ -1,392 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_FMC_BCR_OFFSET(n) (8 * ((n) - 1)) -#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ -#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ -#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ -#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ - -#define STM32_FMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) -#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ -#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ -#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ -#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ - -#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) -#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ -#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ -#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ -#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ - -#define STM32_FMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) -#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) -#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) -#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ -#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ -#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ - -#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) -#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ -#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ -#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ - -#define STM32_FMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ - -#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) -#define STM32_FMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ -#define STM32_FMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ - -#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 1 */ -#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 2 */ - -#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 1 */ -#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 2 */ - -#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ -#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ -#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ - -/* Register Addresses *******************************************************/ - -#define STM32_FMC_BCR(n) (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n)) -#define STM32_FMC_BCR1 (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET) -#define STM32_FMC_BCR2 (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET) -#define STM32_FMC_BCR3 (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET) -#define STM32_FMC_BCR4 (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET) - -#define STM32_FMC_BTR(n) (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n)) -#define STM32_FMC_BTR1 (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET) -#define STM32_FMC_BTR2 (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET) -#define STM32_FMC_BTR3 (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET) -#define STM32_FMC_BTR4 (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET) - -#define STM32_FMC_BWTR(n) (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n)) -#define STM32_FMC_BWTR1 (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET) -#define STM32_FMC_BWTR2 (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET) -#define STM32_FMC_BWTR3 (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET) -#define STM32_FMC_BWTR4 (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET) - -#define STM32_FMC_PCR(n) (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n)) -#define STM32_FMC_PCR2 (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET) -#define STM32_FMC_PCR3 (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET) -#define STM32_FMC_PCR4 (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET) - -#define STM32_FMC_SR(n) (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n)) -#define STM32_FMC_SR2 (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET) -#define STM32_FMC_SR3 (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET) -#define STM32_FMC_SR4 (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET) - -#define STM32_FMC_PMEM(n) (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n)) -#define STM32_FMC_PMEM2 (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET) -#define STM32_FMC_PMEM3 (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET) -#define STM32_FMC_PMEM4 (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET) - -#define STM32_FMC_PATT(n) (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n)) -#define STM32_FMC_PATT2 (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET) -#define STM32_FMC_PATT3 (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET) -#define STM32_FMC_PATT4 (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET) - -#define STM32_FMC_PIO4 (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET) - -#define STM32_FMC_ECCR(n) (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n)) -#define STM32_FMC_ECCR2 (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET) -#define STM32_FMC_ECCR3 (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET) - -#define STM32_FMC_SDCR1 (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET) -#define STM32_FMC_SDCR2 (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET) - -#define STM32_FMC_SDTR1 (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET) -#define STM32_FMC_SDTR2 (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET) - -#define STM32_FMC_SDCMR (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET) -#define STM32_FMC_SDRTR (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET) -#define STM32_FMC_SDSR (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ -#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ -#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */ -#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT) -# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT) -#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ -#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT) -# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT) -#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */ -#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ -#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ -#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ -#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ -#define FMC_BCR_WREN (1 << 12) /* Write enable bit */ -#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ -#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ -#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ - -#define FMC_BCR_RSTVALUE 0x000003d2 - -#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT) -# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT) -# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT) -# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ -#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT) -# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT) -# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT) -# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT) -# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) - -#define FMC_BTR_RSTVALUE 0xffffffff - -#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT) -# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT) -# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT) -# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT) -# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ -#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT) -# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT) -# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT) - -#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ -#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ -#define FMC_PCR_PTYP (1 << 3) /* Memory type */ -#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ -#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT) -# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT) -#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ -#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ -#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT) -# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ -#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK) -# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ -#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT) -# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */ -# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */ -# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ -# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ -# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ - -#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ -#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */ -#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ -#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ -#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ -#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ -#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */ - -#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ -#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT) -# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ -#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT) -# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ -#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT) -# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ -#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT) -# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ -#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT) -# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ -#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT) -# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ -#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT) -# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ -#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT) -# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ -#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT) -# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ -#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT) -# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ -#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT) -# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ -#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT) -# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FMC_SDCR_RESERVED (0x1ffff << 15) /* reserved bits */ - -#define FMC_SDCR_RPIPE_0 (0 << 13) /* read pipe */ -#define FMC_SDCR_RPIPE_1 (1 << 13) -#define FMC_SDCR_RPIPE_2 (2 << 13) -#define FMC_SDCR_READBURST (1 << 12) /* read burst */ -#define FMC_SDCR_SDCLK_DISABLE (0 << 10) /* sdram clock */ -#define FMC_SDCR_SDCLK_2X (2 << 10) -#define FMC_SDCR_SDCLK_3X (3 << 10) -#define FMC_SDCR_WP (1 << 9) /* write protect */ -#define FMC_SDCR_CAS_LATENCY_1 (1 << 7) /* cas latency */ -#define FMC_SDCR_CAS_LATENCY_2 (2 << 7) -#define FMC_SDCR_CAS_LATENCY_3 (3 << 7) -#define FMC_SDCR_NBANKS_2 (0 << 6) /* number of internal banks */ -#define FMC_SDCR_NBANKS_4 (1 << 6) -#define FMC_SDCR_WIDTH_8 (0 << 4) /* memory width */ -#define FMC_SDCR_WIDTH_16 (1 << 4) -#define FMC_SDCR_WIDTH_32 (2 << 4) -#define FMC_SDCR_ROWS_11 (0 << 2) /* number of rows */ -#define FMC_SDCR_ROWS_12 (1 << 2) -#define FMC_SDCR_ROWS_13 (2 << 2) -#define FMC_SDCR_COLS_8 (0 << 0) /* number of columns */ -#define FMC_SDCR_COLS_9 (1 << 0) -#define FMC_SDCR_COLS_10 (2 << 0) -#define FMC_SDCR_COLS_11 (3 << 0) - -#define FMC_SDTR_RESERVED (15 << 28) /* reserved bits */ -#define FMC_SDTR_TMRD(n) (((n & 15) - 1) << 0) -#define FMC_SDTR_TXSR(n) (((n & 15) - 1) << 4) -#define FMC_SDTR_TRAS(n) (((n & 15) - 1) << 8) -#define FMC_SDTR_TRC(n) (((n & 15) - 1) << 12) -#define FMC_SDTR_TWR(n) (((n & 15) - 1) << 16) -#define FMC_SDTR_TRP(n) (((n & 15) - 1) << 20) -#define FMC_SDTR_TRCD(n) (((n & 15) - 1) << 24) - -/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet. - * They should be standard, but it's probably a good idea to review - * the datasheet for your SDRAM device. - */ -#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */ -#define FMC_SDCMR_MDR_BURST_LENGTH_1 ((0 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_2 ((1 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_4 ((2 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_8 ((3 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_LENGTH_FULL ((7 << 0) << 9) -#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL ((0 << 3) << 9) -#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE ((1 << 3) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_1 ((1 << 4) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_2 ((2 << 4) << 9) -#define FMC_SDCMR_MDR_CAS_LATENCY_3 ((3 << 4) << 9) -#define FMC_SDCMR_MDR_MODE_NORMAL ((0 << 7) << 9) -#define FMC_SDCMR_MDR_WBL_BURST ((0 << 9) << 9) -#define FMC_SDCMR_MDR_WBL_SINGLE ((1 << 9) << 9) -#define FMC_SDCMR_NRFS(n) (((n & 15) - 1) << 5) -#define FMC_SDCMR_BANK_1 (1 << 4) -#define FMC_SDCMR_BANK_2 (1 << 3) -#define FMC_SDCMR_CMD_NORMAL (0 << 0) -#define FMC_SDCMR_CMD_CLK_ENABLE (1 << 0) -#define FMC_SDCMR_CMD_PALL (2 << 0) -#define FMC_SDCMR_CMD_AUTO_REFRESH (3 << 0) -#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0) -#define FMC_SDCMR_CMD_SELF_REFRESH (5 << 0) -#define FMC_SDCMR_CMD_POWER_DOWN (6 << 0) - -#define FMC_SDSR_RE (1 << 0) -#define FMC_SDSR_BUSY (1 << 5) -#define FMC_SDSR_MODES1_NORMAL (0 << 1) -#define FMC_SDSR_MODES1_SELF_REFRESH (1 << 1) -#define FMC_SDSR_MODES1_POWER_DOWN (2 << 1) -#define FMC_SDSR_MODES2_NORMAL (0 << 3) -#define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) -#define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fsmc.h b/arch/arm/src/stm32/hardware/stm32_fsmc.h deleted file mode 100644 index b53230f351c5a..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_fsmc.h +++ /dev/null @@ -1,301 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fsmc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_FSMC_BCR_OFFSET(n) (8 * ((n) - 1)) -#define STM32_FSMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */ -#define STM32_FSMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */ -#define STM32_FSMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */ -#define STM32_FSMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */ - -#define STM32_FSMC_BTR_OFFSET(n) (8 * ((n) - 1) + 0x0004) -#define STM32_FSMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */ -#define STM32_FSMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */ -#define STM32_FSMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */ -#define STM32_FSMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */ - -#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104) -#define STM32_FSMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */ -#define STM32_FSMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */ -#define STM32_FSMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */ -#define STM32_FSMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */ - -#define STM32_FSMC_PCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0040) -#define STM32_FSMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FSMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FSMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FSMC_SR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0044) -#define STM32_FSMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */ -#define STM32_FSMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */ -#define STM32_FSMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */ - -#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048) -#define STM32_FSMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */ -#define STM32_FSMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */ -#define STM32_FSMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */ - -#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c) -#define STM32_FSMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */ -#define STM32_FSMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */ -#define STM32_FSMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */ - -#define STM32_FSMC_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */ - -#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054) -#define STM32_FSMC_ECCR2_OFFSET 0x0074 /* ECC result register 2 */ -#define STM32_FSMC_ECCR3_OFFSET 0x0094 /* ECC result register 3 */ - -/* Register Addresses *******************************************************/ - -#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n)) -#define STM32_FSMC_BCR1 (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET) -#define STM32_FSMC_BCR2 (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET) -#define STM32_FSMC_BCR3 (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET) -#define STM32_FSMC_BCR4 (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET) - -#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n)) -#define STM32_FSMC_BTR1 (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET) -#define STM32_FSMC_BTR2 (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET) -#define STM32_FSMC_BTR3 (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET) -#define STM32_FSMC_BTR4 (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET) - -#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n)) -#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET) -#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET) -#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET) -#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET) - -#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n)) -#define STM32_FSMC_PCR2 (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET) -#define STM32_FSMC_PCR3 (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET) -#define STM32_FSMC_PCR4 (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET) - -#define STM32_FSMC_SR(n) (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n)) -#define STM32_FSMC_SR2 (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET) -#define STM32_FSMC_SR3 (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET) -#define STM32_FSMC_SR4 (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET) - -#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n)) -#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET) -#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET) -#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET) - -#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n)) -#define STM32_FSMC_PATT2 (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET) -#define STM32_FSMC_PATT3 (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET) -#define STM32_FSMC_PATT4 (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET) - -#define STM32_FSMC_PIO4 (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET) - -#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n)) -#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET) -#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */ -#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */ -#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */ -#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT) -# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT) -#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */ -#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT) -# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT) -# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT) -#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */ -#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */ -#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */ -#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */ -#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */ -#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ -#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ -#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ -#endif -#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ - -#define FSMC_BCR_RSTVALUE 0x000003d2 - -#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT) -# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT) -# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT) -# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */ -#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT) -# define FSMC_BTR_BUSTURN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT) -# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */ -#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT) -# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT) -# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) - -#define FSMC_BTR_RSTVALUE 0xffffffff - -#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */ -#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT) -# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */ -#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT) -# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/ - -#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */ -#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT) -# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */ -#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT) -# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */ - -#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */ -#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT) -# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */ - -#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */ -#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT) -# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT) - -#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */ -#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */ -#define FSMC_PCR_PTYP (1 << 3) /* Memory type */ -#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */ -#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT) -# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT) -# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT) -#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */ -#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */ -#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT) -# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */ -#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK) -# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */ - -#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */ -#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT) -# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */ -# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */ -# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ -# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */ -# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */ -# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */ - -#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */ -#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */ -#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */ -#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */ -#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */ -#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */ -#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */ - -#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */ -#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT) -# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */ -#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT) -# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */ -#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT) -# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */ -#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT) -# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */ -#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT) -# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */ -#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT) -# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */ -#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT) -# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */ -#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT) -# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#define FSMC_PIO4_IOSET_SHIFT (0) /* IO memory setup time */ -#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT) -# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */ - -#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IO memory wait time */ -#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT) -# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */ - -#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IO memory hold time */ -#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT) -# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */ - -#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IO memory databus HiZ time */ -#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) -# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/stm32/hardware/stm32_i2c_v1.h deleted file mode 100644 index 85ef897b18c1b..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v1.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H - -/* This file provide definitions for the STM32 I2C IP core 1 - *(F1, F2, F4 and L1) - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32_I2C_DR_OFFSET 0x0010 /* Data register (16-bit) */ -#define STM32_I2C_SR1_OFFSET 0x0014 /* Status register 1 (16-bit) */ -#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */ -#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */ -#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */ -#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ - defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412) -# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */ -#endif - -/* Register Addresses *******************************************************/ - -#if STM32_NI2C > 0 -# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C1_DR (STM32_I2C1_BASE+STM32_I2C_DR_OFFSET) -# define STM32_I2C1_SR1 (STM32_I2C1_BASE+STM32_I2C_SR1_OFFSET) -# define STM32_I2C1_SR2 (STM32_I2C1_BASE+STM32_I2C_SR2_OFFSET) -# define STM32_I2C1_CCR (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET) -# define STM32_I2C1_TRISE (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET) -# ifdef STM32_I2C_FLTR_OFFSET -# define STM32_I2C1_FLTR (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET) -# endif -#endif - -#if STM32_NI2C > 1 -# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C2_DR (STM32_I2C2_BASE+STM32_I2C_DR_OFFSET) -# define STM32_I2C2_SR1 (STM32_I2C2_BASE+STM32_I2C_SR1_OFFSET) -# define STM32_I2C2_SR2 (STM32_I2C2_BASE+STM32_I2C_SR2_OFFSET) -# define STM32_I2C2_CCR (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET) -# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET) -# ifdef STM32_I2C_FLTR_OFFSET -# define STM32_I2C2_FLTR (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET) -# endif -#endif - -#if STM32_NI2C > 2 -# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C3_DR (STM32_I2C3_BASE+STM32_I2C_DR_OFFSET) -# define STM32_I2C3_SR1 (STM32_I2C3_BASE+STM32_I2C_SR1_OFFSET) -# define STM32_I2C3_SR2 (STM32_I2C3_BASE+STM32_I2C_SR2_OFFSET) -# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET) -# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET) -# ifdef STM32_I2C_FLTR_OFFSET -# define STM32_I2C3_FLTR (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET) -# endif -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ -#define I2C_CR1_SMBUS (1 << 1) /* Bit 1: SMBus Mode */ -#define I2C_CR1_SMBTYPE (1 << 3) /* Bit 3: SMBus Type */ -#define I2C_CR1_ENARP (1 << 4) /* Bit 4: ARP Enable */ -#define I2C_CR1_ENPEC (1 << 5) /* Bit 5: PEC Enable */ -#define I2C_CR1_ENGC (1 << 6) /* Bit 6: General Call Enable */ -#define I2C_CR1_NOSTRETCH (1 << 7) /* Bit 7: Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_START (1 << 8) /* Bit 8: Start Generation */ -#define I2C_CR1_STOP (1 << 9) /* Bit 9: Stop Generation */ -#define I2C_CR1_ACK (1 << 10) /* Bit 10: Acknowledge Enable */ -#define I2C_CR1_POS (1 << 11) /* Bit 11: Acknowledge/PEC Position (for data reception) */ -#define I2C_CR1_PEC (1 << 12) /* Bit 12: Packet Error Checking */ -#define I2C_CR1_ALERT (1 << 13) /* Bit 13: SMBus Alert */ -#define I2C_CR1_SWRST (1 << 15) /* Bit 15: Software Reset */ - -/* Control register 2 */ - -#define I2C_CR2_FREQ_SHIFT (0) /* Bits 5-0: Peripheral Clock Frequency */ -#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT) -#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */ -#define I2C_CR2_ITEVFEN (1 << 9) /* Bit 9: Event Interrupt Enable */ -#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */ -#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */ -#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */ - -#define I2C_CR2_ALLINTS (I2C_CR2_ITERREN|I2C_CR2_ITEVFEN|I2C_CR2_ITBUFEN) - -/* Own address register 1 */ - -#define I2C_OAR1_ADD0 (1 << 0) /* Bit 0: Interface Address */ -#define I2C_OAR1_ADD8_SHIFT (1) /* Bits 7-1: Interface Address */ -#define I2C_OAR1_ADD8_MASK (0x007f << I2C_OAR1_ADD8_SHIFT) -#define I2C_OAR1_ADD10_SHIFT (1) /* Bits 9-1: Interface Address (10-bit addressing mode)*/ -#define I2C_OAR1_ADD10_MASK (0x01ff << I2C_OAR1_ADD10_SHIFT) -#define I2C_OAR1_ONE (1 << 14) /* Bit 14: Must be configured and kept at 1 */ -#define I2C_OAR1_ADDMODE (1 << 15) /* Bit 15: Addressing Mode (Slave mode) */ - -/* Own address register 2 */ - -#define I2C_OAR2_ENDUAL (1 << 0) /* Bit 0: Dual addressing mode enable */ -#define I2C_OAR2_ADD2_SHIFT (1) /* Bits 7-1: Interface address */ -#define I2C_OAR2_ADD2_MASK (0x7f << I2C_OAR2_ADD2_SHIFT) - -/* Data register */ - -#define I2C_DR_SHIFT (0) /* Bits 7-0: 8-bit Data Register */ -#define I2C_DR_MASK (0x00ff << I2C_DR_SHIFT) - -/* Status register 1 */ - -#define I2C_SR1_SB (1 << 0) /* Bit 0: Start Bit (Master mode) */ -#define I2C_SR1_ADDR (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_BTF (1 << 2) /* Bit 2: Byte Transfer Finished */ -#define I2C_SR1_ADD10 (1 << 3) /* Bit 3: 10-bit header sent (Master mode) */ -#define I2C_SR1_STOPF (1 << 4) /* Bit 4: Stop detection (Slave mode) */ - /* Bit 5: Reserved */ -#define I2C_SR1_RXNE (1 << 6) /* Bit 6: Data Register not Empty (receivers) */ -#define I2C_SR1_TXE (1 << 7) /* Bit 7: Data Register Empty (transmitters) */ -#define I2C_SR1_BERR (1 << 8) /* Bit 8: Bus Error */ -#define I2C_SR1_ARLO (1 << 9) /* Bit 9: Arbitration Lost (master mode) */ -#define I2C_SR1_AF (1 << 10) /* Bit 10: Acknowledge Failure */ -#define I2C_SR1_OVR (1 << 11) /* Bit 11: Overrun/Underrun */ -#define I2C_SR1_PECERR (1 << 12) /* Bit 12: PEC Error in reception */ - /* Bit 13: Reserved */ -#define I2C_SR1_TIMEOUT (1 << 14) /* Bit 14: Timeout or Tlow Error */ -#define I2C_SR1_SMBALERT (1 << 15) /* Bit 15: SMBus Alert */ - -#define I2C_SR1_ERRORMASK (I2C_SR1_BERR|I2C_SR1_ARLO|I2C_SR1_AF|I2C_SR1_OVR|\ - I2C_SR1_PECERR|I2C_SR1_TIMEOUT|I2C_SR1_SMBALERT) - -/* Status register 2 */ - -#define I2C_SR2_MSL (1 << 0) /* Bit 0: Master/Slave */ -#define I2C_SR2_BUSY (1 << 1) /* Bit 1: Bus Busy */ -#define I2C_SR2_TRA (1 << 2) /* Bit 2: Transmitter/Receiver */ -#define I2C_SR2_GENCALL (1 << 4) /* Bit 4: General Call Address (Slave mode) */ -#define I2C_SR2_SMBDEFAULT (1 << 5) /* Bit 5: SMBus Device Default Address (Slave mode) */ -#define I2C_SR2_SMBHOST (1 << 6) /* Bit 6: SMBus Host Header (Slave mode) */ -#define I2C_SR2_DUALF (1 << 7) /* Bit 7: Dual Flag (Slave mode) */ -#define I2C_SR2_PEC_SHIFT (8) /* Bits 15-8: Packet Error Checking Register */ -#define I2C_SR2_PEC_MASK (0xff << I2C_SR2_PEC_SHIFT) - -/* Clock control register */ - -#define I2C_CCR_CCR_SHIFT (0) /* Bits 11-0: Clock Control Register in Fast/Standard mode (Master mode) */ -#define I2C_CCR_CCR_MASK (0x0fff << I2C_CCR_CCR_SHIFT) -#define I2C_CCR_DUTY (1 << 14) /* Bit 14: Fast Mode Duty Cycle */ -#define I2C_CCR_FS (1 << 15) /* Bit 15: Fast Mode Selection */ - -/* TRISE Register */ - -#define I2C_TRISE_SHIFT (0) /* Bits 5-0: Maximum Rise Time in Fast/Standard mode (Master mode) */ -#define I2C_TRISE_MASK (0x3f << I2C_TRISE_SHIFT) - -/* FLTR Register */ - -#ifdef STM32_I2C_FLTR_OFFSET -# define I2C_FLTR_ANOFF (1 << 4) /* Bit 4: Analog noise filter disable */ -# define I2C_FLTR_DNF_SHIFT 0 /* Bits 0-3: Digital noise filter */ -# define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT) -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/stm32/hardware/stm32_i2c_v2.h deleted file mode 100644 index e1cf74909828d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H - -/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, - * G4, H7, L0 and L4). - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NI2C > 0 -# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 1 -# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -#if STM32_NI2C > 2 -# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) -# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) -# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) -# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) -# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) -# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) -# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) -# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) -# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) -# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) -# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */ -#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */ -#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */ -#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */ -#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */ -#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */ -#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */ -#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */ -#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */ -#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT) -# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */ -#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */ -#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */ -#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */ -#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */ -#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */ -#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */ -#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */ -#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */ -#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */ -#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */ -#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */ - -/* Control register 2 */ - -#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */ -#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT) -#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */ -#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT) -#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */ -#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */ -#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */ -#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */ -#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */ -#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */ -#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */ -#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT) -#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */ -#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */ -#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */ - -/* Own address register 1 */ - -#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */ -#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT) -#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT) -#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */ -#define I2C_OAR1_ONE (1 << 14) /* Bit 14: always keep on in software */ -#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */ - -/* Own address register 2 */ - -#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */ -#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT) -#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */ -#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT) -# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */ -# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */ -# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */ -# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */ -# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */ -# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */ -# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */ -# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */ -#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */ - -/* Timing register */ - -#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */ -#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT) -# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */ - -#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */ -#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT) -# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */ - -#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */ -#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT) -# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */ - -#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */ -#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT) -# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */ - -#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */ -#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT) -# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */ - -/* Timeout register */ - -#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */ -#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT) -# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT) -#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */ -#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */ -#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */ -#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT) -# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT) -#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */ - -/* Interrupt and Status register and interrupt clear register */ - -/* Common interrupt bits */ - -#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */ -#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */ -#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */ -#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */ -#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */ -#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */ -#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */ -#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */ -#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */ - -/* Fields unique to the Interrupt and Status register */ - -#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */ -#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */ -#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */ -#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */ -#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */ -#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */ -#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */ -#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */ -#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT) - -#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT) - -#define I2C_ICR_CLEARMASK (I2C_INT_ADDR | I2C_INT_NACK | I2C_INT_STOP | I2C_INT_BERR | I2C_INT_ARLO \ - | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT | I2C_INT_ALERT) - -/* Packet error checking register */ - -#define I2C_PECR_MASK (0xff) - -/* Receive data register */ - -#define I2C_RXDR_MASK (0xff) - -/* Transmit data register */ - -#define I2C_TXDR_MASK (0xff) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_lcd.h b/arch/arm/src/stm32/hardware/stm32_lcd.h deleted file mode 100644 index 806fbe38b5a60..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_lcd.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_lcd.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/* These definitions are valid only if the MCU supports a segment LCD */ - -#if STM32_NLCD > 0 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_LCD_CR_OFFSET 0x0000 /* LCD control register */ -#define STM32_LCD_FCR_OFFSET 0x0004 /* LCD frame control register */ -#define STM32_LCD_SR_OFFSET 0x0008 /* LCD status register */ -#define STM32_LCD_CLR_OFFSET 0x000c /* LCD clear register */ - -#define STM32_LCD_RAM_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn */ -#define STM32_LCD_RAML_OFFSET(n) (0x0014 + ((n) << 3)) /* LCD display memory, COMn, S00-S31 */ -#define STM32_LCD_RAMH_OFFSET(n) (0x0018 + ((n) << 3)) /* LCD display memory, COMn, S32-S39 */ - -#define STM32_LCD_RAM0L_OFFSET 0x0014 /* LCD display memory, COM0, S00-S31 */ -#define STM32_LCD_RAM0H_OFFSET 0x0018 /* LCD display memory, COM0, S32-S39 */ -#define STM32_LCD_RAM1L_OFFSET 0x001c /* LCD display memory, COM1, S00-S31 */ -#define STM32_LCD_RAM1H_OFFSET 0x0020 /* LCD display memory, COM1, S32-S39 */ -#define STM32_LCD_RAM2L_OFFSET 0x0024 /* LCD display memory, COM2, S00-S31 */ -#define STM32_LCD_RAM2H_OFFSET 0x0028 /* LCD display memory, COM2, S32-S39 */ -#define STM32_LCD_RAM3L_OFFSET 0x002c /* LCD display memory, COM3, S00-S31 */ -#define STM32_LCD_RAM3H_OFFSET 0x0020 /* LCD display memory, COM3, S32-S39 */ -#define STM32_LCD_RAM4L_OFFSET 0x0034 /* LCD display memory, COM4, S00-S31 */ -#define STM32_LCD_RAM4H_OFFSET 0x0038 /* LCD display memory, COM4, S32-S39 */ -#define STM32_LCD_RAM5L_OFFSET 0x003c /* LCD display memory, COM5, S00-S31 */ -#define STM32_LCD_RAM5H_OFFSET 0x0040 /* LCD display memory, COM5, S32-S39 */ -#define STM32_LCD_RAM6L_OFFSET 0x0044 /* LCD display memory, COM6, S00-S31 */ -#define STM32_LCD_RAM6H_OFFSET 0x0048 /* LCD display memory, COM6, S32-S39 */ -#define STM32_LCD_RAM7L_OFFSET 0x004c /* LCD display memory, COM7, S00-S31 */ -#define STM32_LCD_RAM7H_OFFSET 0x0050 /* LCD display memory, COM7, S32-S39 */ - -/* Register Addresses *******************************************************/ - -#define STM32_LCD_CR (STM32_LCD_BASE+STM32_LCD_CR_OFFSET) -#define STM32_LCD_FCR (STM32_LCD_BASE+STM32_LCD_FCR_OFFSET) -#define STM32_LCD_SR (STM32_LCD_BASE+STM32_LCD_SR_OFFSET) -#define STM32_LCD_CLR (STM32_LCD_BASE+STM32_LCD_CLR_OFFSET) - -#define STM32_LCD_RAM(n) (STM32_LCD_BASE+STM32_LCD_RAM_OFFSET(n)) -#define STM32_LCD_RAML(n) (STM32_LCD_BASE+STM32_LCD_RAML_OFFSET(n)) -#define STM32_LCD_RAMH(n) (STM32_LCD_BASE+STM32_LCD_RAMH_OFFSET(n)) - -#define STM32_LCD_RAM0L (STM32_LCD_BASE+STM32_LCD_RAM0L_OFFSET) -#define STM32_LCD_RAM0H (STM32_LCD_BASE+STM32_LCD_RAM0H_OFFSET) -#define STM32_LCD_RAM1L (STM32_LCD_BASE+STM32_LCD_RAM1L_OFFSET) -#define STM32_LCD_RAM1H (STM32_LCD_BASE+STM32_LCD_RAM1H_OFFSET) -#define STM32_LCD_RAM2L (STM32_LCD_BASE+STM32_LCD_RAM2L_OFFSET) -#define STM32_LCD_RAM2H (STM32_LCD_BASE+STM32_LCD_RAM2H_OFFSET) -#define STM32_LCD_RAM3L (STM32_LCD_BASE+STM32_LCD_RAM3L_OFFSET) -#define STM32_LCD_RAM3H (STM32_LCD_BASE+STM32_LCD_RAM3H_OFFSET) -#define STM32_LCD_RAM4L (STM32_LCD_BASE+STM32_LCD_RAM4L_OFFSET) -#define STM32_LCD_RAM4H (STM32_LCD_BASE+STM32_LCD_RAM4H_OFFSET) -#define STM32_LCD_RAM5L (STM32_LCD_BASE+STM32_LCD_RAM5L_OFFSET) -#define STM32_LCD_RAM5H (STM32_LCD_BASE+STM32_LCD_RAM5H_OFFSET) -#define STM32_LCD_RAM6L (STM32_LCD_BASE+STM32_LCD_RAM6L_OFFSET) -#define STM32_LCD_RAM6H (STM32_LCD_BASE+STM32_LCD_RAM6H_OFFSET) -#define STM32_LCD_RAM7L (STM32_LCD_BASE+STM32_LCD_RAM7L_OFFSET) -#define STM32_LCD_RAM7H (STM32_LCD_BASE+STM32_LCD_RAM7H_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* LCD control register */ - -#define LCD_CR_LCDEN (1 << 0) /* Bit 0: LCD controller enable */ -#define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */ -#define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */ -#define LCD_CR_DUTY_MASK (7 << LCD_CR_DUTY_SHIFT) -# define LCD_CR_DUTY_STATIC (0 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ -# define LCD_CR_DUTY_1TO2 (1 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ -# define LCD_CR_DUTY_1TO3 (2 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ -# define LCD_CR_DUTY_1TO4 (3 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ -# define LCD_CR_DUTY_1TO8 (4 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ - -#define LCD_CR_BIAS_SHIFT (5) /* Bits 5-6: Bias selector */ -#define LCD_CR_BIAS_MASK (3 << LCD_CR_BIAS_SHIFT) -# define LCD_CR_BIAS_1TO4 (0 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */ -# define LCD_CR_BIAS_1TO2 (1 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */ -# define LCD_CR_BIAS_1TO3 (2 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */ - -#define LCD_CR_MUX_SEG (1 << 7) /* Bit 7: Mux segment enable */ - /* Bits 8-31 Reserved */ - -/* LCD frame control register */ - -#define LCD_FCR_HD (1 << 0) /* Bit 0: High drive enable */ -#define LCD_FCR_SOFIE (1 << 1) /* Bit 1: Start of frame interrupt enable */ - /* Bit 2 Reserved */ -#define LCD_FCR_UDDIE (1 << 3) /* Bit 3: Update display done interrupt enable */ -#define LCD_FCR_PON_SHIFT (4) /* Bits 4-6: Pulse ON duration */ -#define LCD_FCR_PON_MASK (7 << LCD_FCR_PON_SHIFT) -# define LCD_FCR_PON(n) ((n) << LCD_FCR_PON_SHIFT) /* n=0-7 */ - -#define LCD_FCR_DEAD_SHIFT (7) /* Bits 7-9: Dead time duration */ -#define LCD_FCR_DEAD_MASK (7 << LCD_FCR_DEAD_SHIFT) -# define LCD_FCR_DEAD_NONE (0 << LCD_FCR_DEAD_SHIFT) -# define LCD_FCR_DEAD(n) ((n) << LCD_FCR_DEAD_SHIFT) /* n=1..7 */ - -#define LCD_FCR_CC_SHIFT (10) /* Bits 10-12: Contrast control */ -#define LCD_FCR_CC_MASK (7 << LCD_FCR_CC_SHIFT) -# define LCD_FCR_CC_VLCD(n) ((n) << LCD_FCR_CC_SHIFT) /* VLCDn, n=0..7 */ - -#define LCD_FCR_BLINKF_SHIFT (13) /* Bits 13-15: Blink frequency selection */ -#define LCD_FCR_BLINKF_MASK (7 << LCD_FCR_BLINKF_SHIFT) -# define LCD_FCR_BLINKF_DIV8 (0 << LCD_FCR_BLINKF_SHIFT) /* 000: fLCD/8 */ -# define LCD_FCR_BLINKF_DIV16 (1 << LCD_FCR_BLINKF_SHIFT) /* 001: fLCD/16 */ -# define LCD_FCR_BLINKF_DIV32 (2 << LCD_FCR_BLINKF_SHIFT) /* 010: fLCD/32 */ -# define LCD_FCR_BLINKF_DIV64 (3 << LCD_FCR_BLINKF_SHIFT) /* 011: fLCD/64 */ -# define LCD_FCR_BLINKF_DIV128 (4 << LCD_FCR_BLINKF_SHIFT) /* 100: fLCD/128 */ -# define LCD_FCR_BLINKF_DIV256 (5 << LCD_FCR_BLINKF_SHIFT) /* 101: fLCD/256 */ -# define LCD_FCR_BLINKF_DIV512 (6 << LCD_FCR_BLINKF_SHIFT) /* 110: fLCD/512 */ -# define LCD_FCR_BLINKF_DIV1024 (7 << LCD_FCR_BLINKF_SHIFT) /* 111: fLCD/1024 */ - -#define LCD_FCR_BLINK_SHIFT (16) /* Bits 16-17: Blink mode selection */ -#define LCD_FCR_BLINK_MASK (3 << LCD_FCR_BLINK_SHIFT) -# define LCD_FCR_BLINK_DISABLE (0 << LCD_FCR_BLINK_SHIFT) /* 00: Blink disabled */ -# define LCD_FCR_BLINK_S0C0 (1 << LCD_FCR_BLINK_SHIFT) /* 01: Blink enabled on SEG[0], COM[0] (1 pixel) */ -# define LCD_FCR_BLINK_S0CALL (2 << LCD_FCR_BLINK_SHIFT) /* 10: Blink enabled on SEG[0], all COMs */ -# define LCD_FCR_BLINK_SALLCALL (3 << LCD_FCR_BLINK_SHIFT) /* 11: Blink enabled on all SEGs and all COMs */ - -#define LCD_FCR_DIV_SHIFT (18) /* Bits 18-21: DIV clock divider */ -#define LCD_FCR_DIV_MASK (15 << LCD_FCR_DIV_SHIFT) -# define LCD_FCR_DIV(n) (((n)-16) << LCD_FCR_DIV_SHIFT) /* n=16-31 */ - -#define LCD_FCR_PS_SHIFT (22) /* Bits 22-25: PS 16-bit prescaler */ -#define LCD_FCR_PS_MASK (15 << LCD_FCR_PS_SHIFT) -# define LCD_FCR_PS_DIV1 (0 << LCD_FCR_PS_SHIFT) /* 0000: ck_ps = LCDCLK */ -# define LCD_FCR_PS_DIV2 (1 << LCD_FCR_PS_SHIFT) /* 0001: ck_ps = LCDCLK/2 */ -# define LCD_FCR_PS_DIV4 (2 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4 */ -# define LCD_FCR_PS_DIV8 (3 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8 */ -# define LCD_FCR_PS_DIV16 (4 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16 */ -# define LCD_FCR_PS_DIV32 (5 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32 */ -# define LCD_FCR_PS_DIV64 (6 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/64 */ -# define LCD_FCR_PS_DIV128 (7 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/128 */ -# define LCD_FCR_PS_DIV256 (8 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/256 */ -# define LCD_FCR_PS_DIV512 (9 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/512 */ -# define LCD_FCR_PS_DIV1024 (10 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/1024 */ -# define LCD_FCR_PS_DIV2048 (11 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/2048 */ -# define LCD_FCR_PS_DIV4096 (12 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4096 */ -# define LCD_FCR_PS_DIV8192 (13 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8192 */ -# define LCD_FCR_PS_DIV16384 (14 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16384 */ -# define LCD_FCR_PS_DIV32768 (15 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32768 */ - - /* Bits 26-31 Reserved */ - -/* LCD status register */ - -#define LCD_SR_ENS (1 << 0) /* Bit 0: LCD enabled status */ -#define LCD_SR_SOF (1 << 1) /* Bit 1: Start of frame flag */ -#define LCD_SR_UDR (1 << 2) /* Bit 2: Update display request */ -#define LCD_SR_UDD (1 << 3) /* Bit 3: Update Display Done */ -#define LCD_SR_RDY (1 << 4) /* Bit 4: Ready flag */ -#define LCD_SR_FCRSF (1 << 5) /* Bit 5: LCD Frame Control Register Synchronization flag */ - /* Bits 6-31 Reserved */ - -/* LCD clear register */ - - /* Bit 0 Reserved */ -#define LCD_CLR_SOFC (1 << 1) /* Bit 1: Start of frame flag clear */ - /* Bit 2 Reserved */ -#define LCD_CLR_UDDC (1 << 2) /* Bit 3: Update display done clear */ - /* Bits 31:2-31 Reserved */ - -/* LCD display memory, COMn, S00-S31 */ - -#define LCD_RAML_S(n) (1 << (n)) - -/* LCD display memory, COMn, S32-S39 */ - -#define LCD_RAMH_S(n) (1 << ((n)-32)) - -#endif /* STM32_NLCD */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_ltdc.h b/arch/arm/src/stm32/hardware/stm32_ltdc.h deleted file mode 100644 index 3d7b9fd3d0233..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_ltdc.h +++ /dev/null @@ -1,368 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_ltdc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "hardware/stm32_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_LTDC_NCLUT 256 /* Number of entries in the CLUTs */ - -/* LCDC Register Offsets ****************************************************/ - -#define STM32_LTDC_SSCR_OFFSET 0x0008 /* LTDC Synchronization Size Config Register */ -#define STM32_LTDC_BPCR_OFFSET 0x000c /* LTDC Back Porch Configuration Register */ -#define STM32_LTDC_AWCR_OFFSET 0x0010 /* LTDC Active Width Configuration Register */ -#define STM32_LTDC_TWCR_OFFSET 0x0014 /* LTDC Total Width Configuration Register */ -#define STM32_LTDC_GCR_OFFSET 0x0018 /* LTDC Global Control Register */ - /* 0x0020 Reserved */ -#define STM32_LTDC_SRCR_OFFSET 0x0024 /* LTDC Shadow Reload Configuration Register */ - /* 0x0028 Reserved */ -#define STM32_LTDC_BCCR_OFFSET 0x002c /* LTDC Background Color Configuration Register */ - /* 0x0030 Reserved */ -#define STM32_LTDC_IER_OFFSET 0x0034 /* LTDC Interrupt Enable Register */ -#define STM32_LTDC_ISR_OFFSET 0x0038 /* LTDC Interrupt Status Register */ -#define STM32_LTDC_ICR_OFFSET 0x003c /* LTDC Interrupt Clear Register */ -#define STM32_LTDC_LIPCR_OFFSET 0x0040 /* LTDC Line Interrupt Position Config Register */ -#define STM32_LTDC_CPSR_OFFSET 0x0044 /* LTDC Current Position Status Register */ -#define STM32_LTDC_CDSR_OFFSET 0x0048 /* LTDC Current Display Status Register */ - /* 0x004c-0x0080 Reserved */ - -#define STM32_LTDC_L1CR_OFFSET 0x0084 /* LTDC Layer 1 Control Register */ -#define STM32_LTDC_L1WHPCR_OFFSET 0x0088 /* LTDC Layer 1 Window Horiz Pos Config Register */ -#define STM32_LTDC_L1WVPCR_OFFSET 0x008c /* LTDC Layer 1 Window Vert Pos Config Register */ -#define STM32_LTDC_L1CKCR_OFFSET 0x0090 /* LTDC Layer 1 Color Keying Config Register */ -#define STM32_LTDC_L1PFCR_OFFSET 0x0094 /* LTDC Layer 1 Pixel Format Configuration Register */ -#define STM32_LTDC_L1CACR_OFFSET 0x0098 /* LTDC Layer 1 Constant Alpha Config Register */ -#define STM32_LTDC_L1DCCR_OFFSET 0x009c /* LTDC Layer 1 Default Color Config Register */ -#define STM32_LTDC_L1BFCR_OFFSET 0x00a0 /* LTDC Layer 1 Blending Factors Config Register */ - /* 0x00A4-0x00A8 Reserved */ -#define STM32_LTDC_L1CFBAR_OFFSET 0x00ac /* LTDC Layer 1 Color Frame Buffer Address Register */ -#define STM32_LTDC_L1CFBLR_OFFSET 0x00b0 /* LTDC Layer 1 Color Frame Buffer Length Register */ -#define STM32_LTDC_L1CFBLNR_OFFSET 0x00b4 /* LTDC Layer 1 Color Frame Buffer Line Number Register */ - /* 0x00B8-0x00C0 Reserved */ -#define STM32_LTDC_L1CLUTWR_OFFSET 0x00c4 /* LTDC Layer 1 CLUT Write Register */ - /* 0x00C8-0x0100 Reserved */ -#define STM32_LTDC_L2CR_OFFSET 0x0104 /* LTDC Layer 2 Control Register */ -#define STM32_LTDC_L2WHPCR_OFFSET 0x0108 /* LTDC Layer 2 Window Horiz Pos Config Register */ -#define STM32_LTDC_L2WVPCR_OFFSET 0x010c /* LTDC Layer 2 Window Vert Pos Config Register */ -#define STM32_LTDC_L2CKCR_OFFSET 0x0110 /* LTDC Layer 2 Color Keying Config Register */ -#define STM32_LTDC_L2PFCR_OFFSET 0x0114 /* LTDC Layer 2 Pixel Format Configuration Register */ -#define STM32_LTDC_L2CACR_OFFSET 0x0118 /* LTDC Layer 2 Constant Alpha Config Register */ -#define STM32_LTDC_L2DCCR_OFFSET 0x011c /* LTDC Layer 2 Default Color Config Register */ -#define STM32_LTDC_L2BFCR_OFFSET 0x0120 /* LTDC Layer 2 Blending Factors Config Register */ - /* 0x0124-0x0128 Reserved */ -#define STM32_LTDC_L2CFBAR_OFFSET 0x012c /* LTDC Layer 2 Color Frame Buffer Address Register */ -#define STM32_LTDC_L2CFBLR_OFFSET 0x0130 /* LTDC Layer 2 Color Frame Buffer Length Register */ -#define STM32_LTDC_L2CFBLNR_OFFSET 0x0134 /* LTDC Layer 2 Color Frame Buffer Line Number Register */ - /* 0x0138-0x0130 Reserved */ -#define STM32_LTDC_L2CLUTWR_OFFSET 0x0144 /* LTDC Layer 2 CLUT Write Register */ - /* 0x0148-0x03ff Reserved */ - -/* LTDC Register Addresses **************************************************/ - -#define STM32_LTDC_SSCR (STM32_LTDC_BASE + STM32_LTDC_SSCR_OFFSET) -#define STM32_LTDC_BPCR (STM32_LTDC_BASE + STM32_LTDC_BPCR_OFFSET) -#define STM32_LTDC_AWCR (STM32_LTDC_BASE + STM32_LTDC_AWCR_OFFSET) -#define STM32_LTDC_TWCR (STM32_LTDC_BASE + STM32_LTDC_TWCR_OFFSET) -#define STM32_LTDC_GCR (STM32_LTDC_BASE + STM32_LTDC_GCR_OFFSET) -#define STM32_LTDC_SRCR (STM32_LTDC_BASE + STM32_LTDC_SRCR_OFFSET) -#define STM32_LTDC_BCCR (STM32_LTDC_BASE + STM32_LTDC_BCCR_OFFSET) -#define STM32_LTDC_IER (STM32_LTDC_BASE + STM32_LTDC_IER_OFFSET) -#define STM32_LTDC_ISR (STM32_LTDC_BASE + STM32_LTDC_ISR_OFFSET) -#define STM32_LTDC_ICR (STM32_LTDC_BASE + STM32_LTDC_ICR_OFFSET) -#define STM32_LTDC_LIPCR (STM32_LTDC_BASE + STM32_LTDC_LIPCR_OFFSET) -#define STM32_LTDC_CPSR (STM32_LTDC_BASE + STM32_LTDC_CPSR_OFFSET) -#define STM32_LTDC_CDSR (STM32_LTDC_BASE + STM32_LTDC_CDSR_OFFSET) - -#define STM32_LTDC_L1CR (STM32_LTDC_BASE + STM32_LTDC_L1CR_OFFSET) -#define STM32_LTDC_L1WHPCR (STM32_LTDC_BASE + STM32_LTDC_L1WHPCR_OFFSET) -#define STM32_LTDC_L1WVPCR (STM32_LTDC_BASE + STM32_LTDC_L1WVPCR_OFFSET) -#define STM32_LTDC_L1CKCR (STM32_LTDC_BASE + STM32_LTDC_L1CKCR_OFFSET) -#define STM32_LTDC_L1PFCR (STM32_LTDC_BASE + STM32_LTDC_L1PFCR_OFFSET) -#define STM32_LTDC_L1CACR (STM32_LTDC_BASE + STM32_LTDC_L1CACR_OFFSET) -#define STM32_LTDC_L1DCCR (STM32_LTDC_BASE + STM32_LTDC_L1DCCR_OFFSET) -#define STM32_LTDC_L1BFCR (STM32_LTDC_BASE + STM32_LTDC_L1BFCR_OFFSET) -#define STM32_LTDC_L1CFBAR (STM32_LTDC_BASE + STM32_LTDC_L1CFBAR_OFFSET) -#define STM32_LTDC_L1CFBLR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLR_OFFSET) -#define STM32_LTDC_L1CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L1CFBLNR_OFFSET) -#define STM32_LTDC_L1CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L1CLUTWR_OFFSET) - -#define STM32_LTDC_L2CR (STM32_LTDC_BASE + STM32_LTDC_L2CR_OFFSET) -#define STM32_LTDC_L2WHPCR (STM32_LTDC_BASE + STM32_LTDC_L2WHPCR_OFFSET) -#define STM32_LTDC_L2WVPCR (STM32_LTDC_BASE + STM32_LTDC_L2WVPCR_OFFSET) -#define STM32_LTDC_L2CKCR (STM32_LTDC_BASE + STM32_LTDC_L2CKCR_OFFSET) -#define STM32_LTDC_L2PFCR (STM32_LTDC_BASE + STM32_LTDC_L2PFCR_OFFSET) -#define STM32_LTDC_L2CACR (STM32_LTDC_BASE + STM32_LTDC_L2CACR_OFFSET) -#define STM32_LTDC_L2DCCR (STM32_LTDC_BASE + STM32_LTDC_L2DCCR_OFFSET) -#define STM32_LTDC_L2BFCR (STM32_LTDC_BASE + STM32_LTDC_L2BFCR_OFFSET) -#define STM32_LTDC_L2CFBAR (STM32_LTDC_BASE + STM32_LTDC_L2CFBAR_OFFSET) -#define STM32_LTDC_L2CFBLR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLR_OFFSET) -#define STM32_LTDC_L2CFBLNR (STM32_LTDC_BASE + STM32_LTDC_L2CFBLNR_OFFSET) -#define STM32_LTDC_L2CLUTWR (STM32_LTDC_BASE + STM32_LTDC_L2CLUTWR_OFFSET) - -/* LTDC Register Bit Definitions ********************************************/ - -/* LTDC Synchronization Size Configuration Register */ - -#define LTDC_SSCR_VSH_SHIFT (0) /* Bits 0-10: Vertical Sync Height (scan lines) */ -#define LTDC_SSCR_VSH_MASK (0x7ff << LTDC_SSCR_VSH_SHIFT) -# define LTDC_SSCR_VSH(n) ((uint32_t)(n) << LTDC_SSCR_VSH_SHIFT) -#define LTDC_SSCR_HSW_SHIFT (16) /* Bits 16-27: Horizontal Sync Width (pixel clocks) */ -#define LTDC_SSCR_HSW_MASK (0xfff << LTDC_SSCR_HSW_SHIFT) -# define LTDC_SSCR_HSW(n) ((uint32_t)(n) << LTDC_SSCR_HSW_SHIFT) - -/* LTDC Back Porch Configuration Register */ - -#define LTDC_BPCR_AVBP_SHIFT (0) /* Bits 0-10: Accumulated Vertical back porch (scan lines) */ -#define LTDC_BPCR_AVBP_MASK (0x7ff << LTDC_BPCR_AVBP_SHIFT) -# define LTDC_BPCR_AVBP(n) ((uint32_t)(n) << LTDC_BPCR_AVBP_SHIFT) -#define LTDC_BPCR_AHBP_SHIFT (16) /* Bits 16-27: Accumulated Horizontal back porch (pixel clocks) */ -#define LTDC_BPCR_AHBP_MASK (0xfff << LTDC_BPCR_AVBP_SHIFT) -# define LTDC_BPCR_AHBP(n) ((uint32_t)(n) << LTDC_BPCR_AHBP_SHIFT) - -/* LTDC Active Width Configuration Register */ - -#define LTDC_AWCR_AAH_SHIFT (0) /* Bits 0-10: Accumulated Active Height (scan lines) */ -#define LTDC_AWCR_AAH_MASK (0x7ff << LTDC_AWCR_AAH_SHIFT) -# define LTDC_AWCR_AAH(n) ((uint32_t)(n) << LTDC_AWCR_AAH_SHIFT) -#define LTDC_AWCR_AAW_SHIFT (16) /* Bits 16-27: Accumulated Active Width (pixel clocks) */ -#define LTDC_AWCR_AAW_MASK (0xfff << LTDC_AWCR_AAW_SHIFT) -# define LTDC_AWCR_AAW(n) ((uint32_t)(n) << LTDC_AWCR_AAW_SHIFT) - -/* LTDC Total Width Configuration Register */ - -#define LTDC_TWCR_TOTALH_SHIFT (0) /* Bits 0-10: Total Height (scan lines) */ -#define LTDC_TWCR_TOTALH_MASK (0x7ff << LTDC_TWCR_TOTALH_SHIFT) -# define LTDC_TWCR_TOTALH(n) ((uint32_t)(n) << LTDC_TWCR_TOTALH_SHIFT) -#define LTDC_TWCR_TOTALW_SHIFT (16) /* Bits 16-27: Total Width (pixel clocks) */ -#define LTDC_TWCR_TOTALW_MASK (0xfff << LTDC_TWCR_TOTALW_SHIFT) -# define LTDC_TWCR_TOTALW(n) ((uint32_t)(n) << LTDC_TWCR_TOTALW_SHIFT) - -/* LTDC Global Control Register */ - -#define LTDC_GCR_LTDCEN (1 << 0) /* Bit 0: LCD-TFT Controller Enable Bit */ -#define LTDC_GCR_DBW_SHIFT (4) /* Bits 4-6: Dither Blue Width */ -#define LTDC_GCR_DBW_MASK (0x7 << LTDC_GCR_DBW_SHIFT) -# define LTDC_GCR_DBW(n) ((uint32_t)(n) << LTDC_GCR_DBW_SHIFT) -#define LTDC_GCR_DGW_SHIFT (8) /* Bits 8-10: Dither Green Width */ -#define LTDC_GCR_DGW_MASK (0x7 << LTDC_GCR_DGW_SHIFT) -# define LTDC_GCR_DGW(n) ((uint32_t)(n) << LTDC_GCR_DGW_SHIFT) -#define LTDC_GCR_DRW_SHIFT (12) /* Bits 12-14: Dither Red Width */ -#define LTDC_GCR_DRW_MASK (0x7 << LTDC_GCR_DRW_SHIFT) -# define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT) -#define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */ -#define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */ -#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */ -#define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */ -#define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */ - -/* LTDC Shadow Reload Configuration Register */ - -#define LTDC_SRCR_IMR (1 << 0) /* Bit 0: Immediate Reload */ -#define LTDC_SRCR_VBR (1 << 1) /* Bit 1: Vertical Blanking Reload */ - -/* LTDC Background Color Configuration Register */ - -#define LTDC_BCCR_BCBLUE_SHIFT (0) /* Bits 0-7: Background Color Blue Value */ -#define LTDC_BCCR_BCBLUE_MASK (0xff << LTDC_BCCR_BCBLUE_SHIFT) -# define LTDC_BCCR_BCBLUE(n) ((uint32_t)(n) << LTDC_BCCR_BCBLUE_SHIFT) -#define LTDC_BCCR_BCGREEN_SHIFT (8) /* Bits 8-15: Background Color Green Value */ -#define LTDC_BCCR_BCGREEN_MASK (0xff << LTDC_BCCR_BCGREEN_SHIFT) -# define LTDC_BCCR_BCGREEN(n) ((uint32_t)(n) << LTDC_BCCR_BCGREEN_SHIFT) -#define LTDC_BCCR_BCRED_SHIFT (16) /* Bits 16-23: Background Color Red Value */ -#define LTDC_BCCR_BCRED_MASK (0xff << LTDC_BCCR_BCRED_SHIFT) -# define LTDC_BCCR_BCRED(n) ((uint32_t)(n) << LTDC_BCCR_BCRED_SHIFT) - -/* LTDC Interrupt Enable Register */ - -#define LTDC_IER_LIE (1 << 0) /* Bit 0: Line Interrupt Enable */ -#define LTDC_IER_FUIE (1 << 1) /* Bit 1: FIFO Underrun Interrupt Enable */ -#define LTDC_IER_TERRIE (1 << 2) /* Bit 2: Transfer Error Interrupt Enable */ -#define LTDC_IER_RRIE (1 << 3) /* Bit 3: Register Reload Interrupt Enable */ - -/* LTDC Interrupt Status Register */ - -#define LTDC_ISR_LIF (1 << 0) /* Bit 0: Line Interrupt Flag */ -#define LTDC_ISR_FUIF (1 << 1) /* Bit 1: FIFO Underrun Interrupt Flag */ -#define LTDC_IER_TERRIF (1 << 2) /* Bit 2: Transfer Error Interrupt Flag */ -#define LTDC_ISR_RRIF (1 << 3) /* Bit 3: Register Reload Interrupt Flag */ - -/* LTDC Interrupt Clear Register */ - -#define LTDC_ICR_CLIF (1 << 0) /* Bit 0: Clear Line Interrupt Flag */ -#define LTDC_ICR_CFUIF (1 << 1) /* Bit 1: Clear FIFO Underrun Interrupt Flag */ -#define LTDC_ICR_CTERRIF (1 << 2) /* Bit 2: Clear Transfer Error Interrupt Flag */ -#define LTDC_ICR_CRRIF (1 << 3) /* Bit 3: Clear Register Reload Interrupt Flag */ - -/* LTDC Line Interrupt Posittion Configuration Register */ - -#define LTDC_LIPCR_LIPOS_SHIFT (0) /* Bits 0-10: Line Interrupt Position */ -#define LTDC_LIPCR_LIPOS_MASK (0x7ff << LTDC_LIPCR_LIPOS_SHIFT) -# define LTDC_LIPCR_LIPOS(n) ((uint32_t)(n) << LTDC_LIPCR_LIPOS_SHIFT) - -/* LTDC Current Position Status Register */ - -#define LTDC_CPSR_CYPOS_SHIFT (0) /* Bits 0-15: Current Y Position */ -#define LTDC_CPSR_CYPOS_MASK (0xffff << LTDC_CPSR_CYPOS_SHIFT) -# define LTDC_CPSR_CYPOS(n) ((uint32_t)(n) << LTDC_CPSR_CYPOS_SHIFT) -#define LTDC_CPSR_CXPOS_SHIFT (16) /* Bits 15-31: Current X Position */ -#define LTDC_CPSR_CXPOS_MASK (0xffff << LTDC_CPSR_CXPOS_SHIFT) -# define LTDC_CPSR_CXPOS(n) ((uint32_t)(n) << LTDC_CPSR_CXPOS_SHIFT) - -/* LTDC Current Display Status Register */ - -#define LTDC_CDSR_VDES (1 << 0) /* Bit 0: Vertical Data Enable display Status */ -#define LTDC_CDSR_HDES (1 << 1) /* Bit 1: Horizontal Data Enable display Status */ -#define LTDC_CDSR_VSYNCS (1 << 2) /* Bit 2: Vertical Sync display Status */ -#define LTDC_CDSR_HSYNCS (1 << 3) /* Bit 3: Horizontal Sync display Status */ - -/* LTDC Layer x Control Register */ - -#define LTDC_LXCR_LEN (1 << 0) /* Bit 0: Layer Enable */ -#define LTDC_LXCR_COLKEN (1 << 1) /* Bit 1: Color Keying Enable */ -#define LTDC_LXCR_CLUTEN (1 << 4) /* Bit 4: Color Look-Up Table Enable */ - -/* LTDC Layer x Window Horizontal Position Configuration Register */ - -#define LTDC_LXWHPCR_WHSTPOS_SHIFT (0) /* Bits 0-11: Window Horizontal Start Position */ -#define LTDC_LXWHPCR_WHSTPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSTPOS_SHIFT) -# define LTDC_LXWHPCR_WHSTPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSTPOS_SHIFT) -#define LTDC_LXWHPCR_WHSPPOS_SHIFT (16) /* Bits 16-27: Window Horizontal Stop Position */ -#define LTDC_LXWHPCR_WHSPPOS_MASK (0xFFF << LTDC_LXWHPCR_WHSPPOS_SHIFT) -# define LTDC_LXWHPCR_WHSPPOS(n) ((uint32_t)(n) << LTDC_LXWHPCR_WHSPPOS_SHIFT) - -/* LTDC Layer x Window Vertical Position Configuration Register */ - -#define LTDC_LXWVPCR_WVSTPOS_SHIFT (0) /* Bits 0-10: Window Vertical Start Position */ -#define LTDC_LXWVPCR_WVSTPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSTPOS_SHIFT) -# define LTDC_LXWVPCR_WVSTPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSTPOS_SHIFT) -#define LTDC_LXWVPCR_WVSPPOS_SHIFT (16) /* Bits 16-26: Window Vertical Stop Position */ -#define LTDC_LXWVPCR_WVSPPOS_MASK (0x7ff << LTDC_LXWVPCR_WVSPPOS_SHIFT) -# define LTDC_LXWVPCR_WVSPPOS(n) ((uint32_t)(n) << LTDC_LXWVPCR_WVSPPOS_SHIFT) - -/* LTDC Layer x Color Keying Configuration Register */ - -#define LTDC_LXCKCR_CKBLUE_SHIFT (0) /* Bits 0-7: Color Key Blue Value */ -#define LTDC_LXCKCR_CKBLUE_MASK (0xff << LTDC_LXCKCR_CKBLUE_SHIFT) -# define LTDC_LXCKCR_CKBLUE(n) ((uint32_t)(n) << LTDC_LXCKCR_CKBLUE_SHIFT) -#define LTDC_LXCKCR_CKGREEN_SHIFT (8) /* Bits 8-15: Color Key Green Value */ -#define LTDC_LXCKCR_CKGREEN_MASK (0xff << LTDC_LXCKCR_CKGREEN_SHIFT) -# define LTDC_LXCKCR_CKGREEN(n) ((uint32_t)(n) << LTDC_LXCKCR_CKGREEN_SHIFT) -#define LTDC_LXCKCR_CKRED_SHIFT (16) /* Bits 16-23: Color Key Red Value */ -#define LTDC_LXCKCR_CKRED_MASK (0xff << LTDC_LXCKCR_CKRED_SHIFT) -# define LTDC_LXCKCR_CKRED(n) ((uint32_t)(n) << LTDC_LXCKCR_CKRED_SHIFT) - -/* LTDC Layer x Pixel Format Configuration Register */ - -#define LTDC_LXPFCR_PF_SHIFT (0) /* Bits 0-2: Pixel Format */ -#define LTDC_LXPFCR_PF_MASK (0x7 << LTDC_LXPFCR_PF_SHIFT) -# define LTDC_LXPFCR_PF(n) ((uint32_t)(n) << LTDC_LXPFCR_PF_SHIFT) - -#define LTDC_PF_ARGB8888 0 -#define LTDC_PF_RGB888 1 -#define LTDC_PF_RGB565 2 -#define LTDC_PF_ARGB1555 3 -#define LTDC_PF_ARGB4444 4 -#define LTDC_PF_L8 5 /* 8-bit Luninance (CLUT lookup) */ -#define LTDC_PF_AL44 6 /* 4-bit Alpha, 4-bit Luminance */ -#define LTDC_PF_AL88 7 /* 8-bit Alpha, 8-bit Luminance */ - -/* LTDC Layer x Constant Alpha Configuration Register */ - -#define LTDC_LXCACR_CONSTA_SHIFT (0) /* Bits 0-7: Constant Alpha */ -#define LTDC_LXCACR_CONSTA_MASK (0x7 << LTDC_LXCACR_CONSTA_SHIFT) -# define LTDC_LXCACR_CONSTA(n) ((uint32_t)(n) << LTDC_LXCACR_CONSTA_SHIFT) - -/* LTDC Layer x Default Color Configuration Register */ - -#define LTDC_LXDCCR_DCBLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ -#define LTDC_LXDCCR_DCBLUE_MASK (0xff << LTDC_LXDCCR_DCBLUE_SHIFT) -# define LTDC_LXDCCR_DCBLUE(n) ((uint32_t)(n) << LTDC_LXDCCR_DCBLUE_SHIFT) -#define LTDC_LXDCCR_DCGREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ -#define LTDC_LXDCCR_DCGREEN_MASK (0xff << LTDC_LXDCCR_DCGREEN_SHIFT) -# define LTDC_LXDCCR_DCGREEN(n) ((uint32_t)(n) << LTDC_LXDCCR_DCGREEN_SHIFT) -#define LTDC_LXDCCR_DCRED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ -#define LTDC_LXDCCR_DCRED_MASK (0xff << LTDC_LXDCCR_DCRED_SHIFT) -# define LTDC_LXDCCR_DCRED(n) ((uint32_t)(n) << LTDC_LXDCCR_DCRED_SHIFT) -#define LTDC_LXDCCR_DCALPHA_SHIFT (24) /* Bits 24-31: Default Color Alpha Value */ -#define LTDC_LXDCCR_DCALPHA_MASK (0xff << LTDC_LXDCCR_DCALPHA_SHIFT) -# define LTDC_LXDCCR_DCALPHA(n) ((uint32_t)(n) << LTDC_LXDCCR_DCALPHA_SHIFT) - -/* LTDC Layer x Blending Factors Configuration Register */ - -#define LTDC_LXBFCR_BF2_SHIFT (0) /* Bits 0-2: Blending Factor 2 */ -#define LTDC_LXBFCR_BF2_MASK (0x7 << LTDC_LXBFCR_BF2_SHIFT) -# define LTDC_LXBFCR_BF2(n) ((uint32_t)(n) << LTDC_LXBFCR_BF2_SHIFT) -#define LTDC_LXBFCR_BF1_SHIFT (8) /* Bits 8-10: Blending Factor 1 */ -#define LTDC_LXBFCR_BF1_MASK (0x7 << LTDC_LXBFCR_BF1_SHIFT) -# define LTDC_LXBFCR_BF1(n) ((uint32_t)(n) << LTDC_LXBFCR_BF1_SHIFT) - -#define LTDC_BF1_CONST_ALPHA 0x04 /* Constant Alpha */ -#define LTDC_BF1_PIXEL_ALPHA 0x06 /* Pixel Alpha x Constant Alpha */ -#define LTDC_BF2_CONST_ALPHA 0x05 /* Constant Alpha */ -#define LTDC_BF2_PIXEL_ALPHA 0x07 /* Pixel Alpha x Constant Alpha */ - -/* LTDC Layer x Color Frame Buffer Length Configuration Register */ - -#define LTDC_LXCFBLR_CFBLL_SHIFT (0) /* Bits 0-12: Color Frame Buffer Line Length */ -#define LTDC_LXCFBLR_CFBLL_MASK (0x1fff << LTDC_LXCFBLR_CFBLL_SHIFT) -# define LTDC_LXCFBLR_CFBLL(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBLL_SHIFT) -#define LTDC_LXCFBLR_CFBP_SHIFT (16) /* Bits 16-28: Color Frame Buffer Pitch */ -#define LTDC_LXCFBLR_CFBP_MASK (0x1fff << LTDC_LXCFBLR_CFBP_SHIFT) -# define LTDC_LXCFBLR_CFBP(n) ((uint32_t)(n) << LTDC_LXCFBLR_CFBP_SHIFT) - -/* LTDC Layer x Color Frame Buffer Line Number Register */ - -#define LTDC_LXCFBLNR_LN_SHIFT (0) /* Bits 0-10: Color Frame Buffer Line Number */ -#define LTDC_LXCFBLNR_LN_MASK (0x7ff << LTDC_LXCFBLNR_LN_SHIFT) -# define LTDC_LXCFBLNR_LN(n) ((uint32_t)(n) << LTDC_LXCFBLNR_LN_SHIFT) - -/* LTDC Layer x CLUT Write Register */ - -#define LTDC_LXCLUTWR_BLUE_SHIFT (0) /* Bits 0-7: Default Color Blue Value */ -#define LTDC_LXCLUTWR_BLUE_MASK (0xff << LTDC_LXCLUTWR_BLUE_SHIFT) -# define LTDC_LXCLUTWR_BLUE(n) ((uint32_t)(n) << LTDC_LXCLUTWR_BLUE_SHIFT) -#define LTDC_LXCLUTWR_GREEN_SHIFT (8) /* Bits 8-15: Default Color Green Value */ -#define LTDC_LXCLUTWR_GREEN_MASK (0xff << LTDC_LXCLUTWR_GREEN_SHIFT) -# define LTDC_LXCLUTWR_GREEN(n) ((uint32_t)(n) << LTDC_LXCLUTWR_GREEN_SHIFT) -#define LTDC_LXCLUTWR_RED_SHIFT (16) /* Bits 16-23: Default Color Red Value */ -#define LTDC_LXCLUTWR_RED_MASK (0xff << LTDC_LXCLUTWR_RED_SHIFT) -# define LTDC_LXCLUTWR_RED(n) ((uint32_t)(n) << LTDC_LXCLUTWR_RED_SHIFT) -#define LTDC_LXCLUTWR_CLUTADD_SHIFT (24) /* Bits 24-31: CLUT Address */ -#define LTDC_LXCLUTWR_CLUTADD_MASK (0xff << LTDC_LXCLUTWR_CLUTADD_SHIFT) -# define LTDC_LXCLUTWR_CLUTADD(n) ((uint32_t)(n) << LTDC_LXCLUTWR_CLUTADD_SHIFT) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_otghs.h b/arch/arm/src/stm32/hardware/stm32_otghs.h deleted file mode 100644 index 59583ad96997d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_otghs.h +++ /dev/null @@ -1,1111 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_otghs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* General definitions */ - -#define OTGHS_EPTYPE_CTRL (0) /* Control */ -#define OTGHS_EPTYPE_ISOC (1) /* Isochronous */ -#define OTGHS_EPTYPE_BULK (2) /* Bulk */ -#define OTGHS_EPTYPE_INTR (3) /* Interrupt */ - -#define OTGHS_PID_DATA0 (0) -#define OTGHS_PID_DATA2 (1) -#define OTGHS_PID_DATA1 (2) -#define OTGHS_PID_MDATA (3) /* Non-control */ -#define OTGHS_PID_SETUP (3) /* Control */ - -/* Register Offsets *********************************************************/ - -/* Core global control and status registers */ - -#define STM32_OTGHS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32_OTGHS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32_OTGHS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32_OTGHS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32_OTGHS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32_OTGHS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32_OTGHS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32_OTGHS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32_OTGHS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32_OTGHS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32_OTGHS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32_OTGHS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32_OTGHS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32_OTGHS_GCCFG_OFFSET 0x0038 /* general core configuration register */ -#define STM32_OTGHS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32_OTGHS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32_OTGHS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) -#define STM32_OTGHS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32_OTGHS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32_OTGHS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ - -/* Host-mode control and status registers */ - -#define STM32_OTGHS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32_OTGHS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32_OTGHS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32_OTGHS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32_OTGHS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32_OTGHS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32_OTGHS_HPRT_OFFSET 0x0440 /* Host port control and status register */ - -#define STM32_OTGHS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32_OTGHS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32_OTGHS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32_OTGHS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32_OTGHS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ - -#define STM32_OTGHS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32_OTGHS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32_OTGHS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32_OTGHS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32_OTGHS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32_OTGHS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32_OTGHS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32_OTGHS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32_OTGHS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ -#define STM32_OTGHS_HCCHAR8_OFFSET 0x0600 /* Host channel-8 characteristics register */ -#define STM32_OTGHS_HCCHAR9_OFFSET 0x0620 /* Host channel-9 characteristics register */ -#define STM32_OTGHS_HCCHAR10_OFFSET 0x0640 /* Host channel-10 characteristics register */ -#define STM32_OTGHS_HCCHAR11_OFFSET 0x0660 /* Host channel-11 characteristics register */ - -#define STM32_OTGHS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32_OTGHS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32_OTGHS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32_OTGHS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32_OTGHS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32_OTGHS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32_OTGHS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32_OTGHS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32_OTGHS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ -#define STM32_OTGHS_HCINT8_OFFSET 0x0608 /* Host channel-8 interrupt register */ -#define STM32_OTGHS_HCINT9_OFFSET 0x0628 /* Host channel-9 interrupt register */ -#define STM32_OTGHS_HCINT10_OFFSET 0x0648 /* Host channel-10 interrupt register */ -#define STM32_OTGHS_HCINT11_OFFSET 0x0668 /* Host channel-11 interrupt register */ - -#define STM32_OTGHS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32_OTGHS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK8_OFFSET 0x060c /* Host channel-8 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK9_OFFSET 0x062c /* Host channel-9 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK10_OFFSET 0x064c /* Host channel-10 interrupt mask register */ -#define STM32_OTGHS_HCINTMSK11_OFFSET 0x068c /* Host channel-11 interrupt mask register */ - -#define STM32_OTGHS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32_OTGHS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32_OTGHS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32_OTGHS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32_OTGHS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32_OTGHS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32_OTGHS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32_OTGHS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32_OTGHS_HCTSIZ7_OFFSET 0x06f0 /* Host channel-7 interrupt register */ -#define STM32_OTGHS_HCTSIZ8_OFFSET 0x0610 /* Host channel-8 interrupt register */ -#define STM32_OTGHS_HCTSIZ9_OFFSET 0x0630 /* Host channel-9 interrupt register */ -#define STM32_OTGHS_HCTSIZ10_OFFSET 0x0650 /* Host channel-10 interrupt register */ -#define STM32_OTGHS_HCTSIZ11_OFFSET 0x05f0 /* Host channel-11 interrupt register */ - -/* Device-mode control and status registers */ - -#define STM32_OTGHS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32_OTGHS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32_OTGHS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32_OTGHS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32_OTGHS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32_OTGHS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32_OTGHS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32_OTGHS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32_OTGHS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32_OTGHS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ - -#define STM32_OTGHS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGHS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32_OTGHS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32_OTGHS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32_OTGHS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ - -#define STM32_OTGHS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGHS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32_OTGHS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32_OTGHS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32_OTGHS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ - -#define STM32_OTGHS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32_OTGHS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32_OTGHS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32_OTGHS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32_OTGHS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGHS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32_OTGHS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32_OTGHS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ - -#define STM32_OTGHS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTGHS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32_OTGHS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ - -#define STM32_OTGHS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGHS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32_OTGHS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ - -#define STM32_OTGHS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGHS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32_OTGHS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32_OTGHS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32_OTGHS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ - -#define STM32_OTGHS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32_OTGHS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32_OTGHS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32_OTGHS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32_OTGHS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGHS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32_OTGHS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTGHS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ - -/* Power and clock gating registers */ - -#define STM32_OTGHS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGHS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTGHS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) - -#define STM32_OTGHS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32_OTGHS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32_OTGHS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ - -/* Register Addresses *******************************************************/ - -#define STM32_OTGHS_GOTGCTL (STM32_OTGHS_BASE+STM32_OTGHS_GOTGCTL_OFFSET) -#define STM32_OTGHS_GOTGINT (STM32_OTGHS_BASE+STM32_OTGHS_GOTGINT_OFFSET) -#define STM32_OTGHS_GAHBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GAHBCFG_OFFSET) -#define STM32_OTGHS_GUSBCFG (STM32_OTGHS_BASE+STM32_OTGHS_GUSBCFG_OFFSET) -#define STM32_OTGHS_GRSTCTL (STM32_OTGHS_BASE+STM32_OTGHS_GRSTCTL_OFFSET) -#define STM32_OTGHS_GINTSTS (STM32_OTGHS_BASE+STM32_OTGHS_GINTSTS_OFFSET) -#define STM32_OTGHS_GINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_GINTMSK_OFFSET) -#define STM32_OTGHS_GRXSTSR (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSR_OFFSET) -#define STM32_OTGHS_GRXSTSP (STM32_OTGHS_BASE+STM32_OTGHS_GRXSTSP_OFFSET) -#define STM32_OTGHS_GRXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_GRXFSIZ_OFFSET) -#define STM32_OTGHS_HNPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXFSIZ_OFFSET) -#define STM32_OTGHS_DIEPTXF0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF0_OFFSET) -#define STM32_OTGHS_HNPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HNPTXSTS_OFFSET) -#define STM32_OTGHS_GCCFG (STM32_OTGHS_BASE+STM32_OTGHS_GCCFG_OFFSET) -#define STM32_OTGHS_CID (STM32_OTGHS_BASE+STM32_OTGHS_CID_OFFSET) -#define STM32_OTGHS_HPTXFSIZ (STM32_OTGHS_BASE+STM32_OTGHS_HPTXFSIZ_OFFSET) - -#define STM32_OTGHS_DIEPTXF(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF_OFFSET(n)) -#define STM32_OTGHS_DIEPTXF1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF1_OFFSET) -#define STM32_OTGHS_DIEPTXF2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF2_OFFSET) -#define STM32_OTGHS_DIEPTXF3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTXF3_OFFSET) - -/* Host-mode control and status registers */ - -#define STM32_OTGHS_HCFG (STM32_OTGHS_BASE+STM32_OTGHS_HCFG_OFFSET) -#define STM32_OTGHS_HFIR (STM32_OTGHS_BASE+STM32_OTGHS_HFIR_OFFSET) -#define STM32_OTGHS_HFNUM (STM32_OTGHS_BASE+STM32_OTGHS_HFNUM_OFFSET) -#define STM32_OTGHS_HPTXSTS (STM32_OTGHS_BASE+STM32_OTGHS_HPTXSTS_OFFSET) -#define STM32_OTGHS_HAINT (STM32_OTGHS_BASE+STM32_OTGHS_HAINT_OFFSET) -#define STM32_OTGHS_HAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_HAINTMSK_OFFSET) -#define STM32_OTGHS_HPRT (STM32_OTGHS_BASE+STM32_OTGHS_HPRT_OFFSET) - -#define STM32_OTGHS_CHAN(n) (STM32_OTGHS_BASE+STM32_OTGHS_CHAN_OFFSET(n)) - -#define STM32_OTGHS_HCCHAR(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR_OFFSET(n)) -#define STM32_OTGHS_HCCHAR0 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR0_OFFSET) -#define STM32_OTGHS_HCCHAR1 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR1_OFFSET) -#define STM32_OTGHS_HCCHAR2 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR2_OFFSET) -#define STM32_OTGHS_HCCHAR3 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR3_OFFSET) -#define STM32_OTGHS_HCCHAR4 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR4_OFFSET) -#define STM32_OTGHS_HCCHAR5 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR5_OFFSET) -#define STM32_OTGHS_HCCHAR6 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR6_OFFSET) -#define STM32_OTGHS_HCCHAR7 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR7_OFFSET) -#define STM32_OTGHS_HCCHAR8 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR8_OFFSET) -#define STM32_OTGHS_HCCHAR9 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR9_OFFSET) -#define STM32_OTGHS_HCCHAR10 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR10_OFFSET) -#define STM32_OTGHS_HCCHAR11 (STM32_OTGHS_BASE+STM32_OTGHS_HCCHAR11_OFFSET) - -#define STM32_OTGHS_HCINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINT_OFFSET(n)) -#define STM32_OTGHS_HCINT0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT0_OFFSET) -#define STM32_OTGHS_HCINT1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT1_OFFSET) -#define STM32_OTGHS_HCINT2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT2_OFFSET) -#define STM32_OTGHS_HCINT3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT3_OFFSET) -#define STM32_OTGHS_HCINT4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT4_OFFSET) -#define STM32_OTGHS_HCINT5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT5_OFFSET) -#define STM32_OTGHS_HCINT6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT6_OFFSET) -#define STM32_OTGHS_HCINT7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT7_OFFSET) -#define STM32_OTGHS_HCINT8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT8_OFFSET) -#define STM32_OTGHS_HCINT9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT9_OFFSET) -#define STM32_OTGHS_HCINT10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT10_OFFSET) -#define STM32_OTGHS_HCINT11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINT11_OFFSET) - -#define STM32_OTGHS_HCINTMSK(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK_OFFSET(n)) -#define STM32_OTGHS_HCINTMSK0 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK0_OFFSET) -#define STM32_OTGHS_HCINTMSK1 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK1_OFFSET) -#define STM32_OTGHS_HCINTMSK2 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK2_OFFSET) -#define STM32_OTGHS_HCINTMSK3 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK3_OFFSET) -#define STM32_OTGHS_HCINTMSK4 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK4_OFFSET) -#define STM32_OTGHS_HCINTMSK5 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK5_OFFSET) -#define STM32_OTGHS_HCINTMSK6 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK6_OFFSET) -#define STM32_OTGHS_HCINTMSK7 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK7_OFFSET) -#define STM32_OTGHS_HCINTMSK8 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK8_OFFSET) -#define STM32_OTGHS_HCINTMSK9 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK9_OFFSET) -#define STM32_OTGHS_HCINTMSK10 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK10_OFFSET) -#define STM32_OTGHS_HCINTMSK11 (STM32_OTGHS_BASE+STM32_OTGHS_HCINTMSK11_OFFSET) - -#define STM32_OTGHS_HCTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ_OFFSET(n)) -#define STM32_OTGHS_HCTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ0_OFFSET) -#define STM32_OTGHS_HCTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ1_OFFSET) -#define STM32_OTGHS_HCTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ2_OFFSET) -#define STM32_OTGHS_HCTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ3_OFFSET) -#define STM32_OTGHS_HCTSIZ4 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ4_OFFSET) -#define STM32_OTGHS_HCTSIZ5 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ5_OFFSET) -#define STM32_OTGHS_HCTSIZ6 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ6_OFFSET) -#define STM32_OTGHS_HCTSIZ7 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ7_OFFSET) -#define STM32_OTGHS_HCTSIZ8 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ8_OFFSET) -#define STM32_OTGHS_HCTSIZ9 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ9_OFFSET) -#define STM32_OTGHS_HCTSIZ10 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ10_OFFSET) -#define STM32_OTGHS_HCTSIZ11 (STM32_OTGHS_BASE+STM32_OTGHS_HCTSIZ11_OFFSET) - -/* Device-mode control and status registers */ - -#define STM32_OTGHS_DCFG (STM32_OTGHS_BASE+STM32_OTGHS_DCFG_OFFSET) -#define STM32_OTGHS_DCTL (STM32_OTGHS_BASE+STM32_OTGHS_DCTL_OFFSET) -#define STM32_OTGHS_DSTS (STM32_OTGHS_BASE+STM32_OTGHS_DSTS_OFFSET) -#define STM32_OTGHS_DIEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPMSK_OFFSET) -#define STM32_OTGHS_DOEPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DOEPMSK_OFFSET) -#define STM32_OTGHS_DAINT (STM32_OTGHS_BASE+STM32_OTGHS_DAINT_OFFSET) -#define STM32_OTGHS_DAINTMSK (STM32_OTGHS_BASE+STM32_OTGHS_DAINTMSK_OFFSET) -#define STM32_OTGHS_DVBUSDIS (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSDIS_OFFSET) -#define STM32_OTGHS_DVBUSPULSE (STM32_OTGHS_BASE+STM32_OTGHS_DVBUSPULSE_OFFSET) -#define STM32_OTGHS_DIEPEMPMSK (STM32_OTGHS_BASE+STM32_OTGHS_DIEPEMPMSK_OFFSET) - -#define STM32_OTGHS_DIEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEP_OFFSET(n)) - -#define STM32_OTGHS_DIEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL_OFFSET(n)) -#define STM32_OTGHS_DIEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL0_OFFSET) -#define STM32_OTGHS_DIEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL1_OFFSET) -#define STM32_OTGHS_DIEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL2_OFFSET) -#define STM32_OTGHS_DIEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPCTL3_OFFSET) - -#define STM32_OTGHS_DIEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT_OFFSET(n)) -#define STM32_OTGHS_DIEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT0_OFFSET) -#define STM32_OTGHS_DIEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT1_OFFSET) -#define STM32_OTGHS_DIEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT2_OFFSET) -#define STM32_OTGHS_DIEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPINT3_OFFSET) - -#define STM32_OTGHS_DIEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ_OFFSET(n)) -#define STM32_OTGHS_DIEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ0_OFFSET) -#define STM32_OTGHS_DIEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ1_OFFSET) -#define STM32_OTGHS_DIEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ2_OFFSET) -#define STM32_OTGHS_DIEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DIEPTSIZ3_OFFSET) - -#define STM32_OTGHS_DTXFSTS(n) (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS_OFFSET(n)) -#define STM32_OTGHS_DTXFSTS0 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS0_OFFSET) -#define STM32_OTGHS_DTXFSTS1 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS1_OFFSET) -#define STM32_OTGHS_DTXFSTS2 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS2_OFFSET) -#define STM32_OTGHS_DTXFSTS3 (STM32_OTGHS_BASE+STM32_OTGHS_DTXFSTS3_OFFSET) - -#define STM32_OTGHS_DOEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEP_OFFSET(n)) - -#define STM32_OTGHS_DOEPCTL(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL_OFFSET(n)) -#define STM32_OTGHS_DOEPCTL0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL0_OFFSET) -#define STM32_OTGHS_DOEPCTL1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL1_OFFSET) -#define STM32_OTGHS_DOEPCTL2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL2_OFFSET) -#define STM32_OTGHS_DOEPCTL3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPCTL3_OFFSET) - -#define STM32_OTGHS_DOEPINT(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT_OFFSET(n)) -#define STM32_OTGHS_DOEPINT0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT0_OFFSET) -#define STM32_OTGHS_DOEPINT1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT1_OFFSET) -#define STM32_OTGHS_DOEPINT2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT2_OFFSET) -#define STM32_OTGHS_DOEPINT3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPINT3_OFFSET) - -#define STM32_OTGHS_DOEPTSIZ(n) (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ_OFFSET(n)) -#define STM32_OTGHS_DOEPTSIZ0 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ0_OFFSET) -#define STM32_OTGHS_DOEPTSIZ1 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ1_OFFSET) -#define STM32_OTGHS_DOEPTSIZ2 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ2_OFFSET) -#define STM32_OTGHS_DOEPTSIZ3 (STM32_OTGHS_BASE+STM32_OTGHS_DOEPTSIZ3_OFFSET) - -/* Power and clock gating registers */ - -#define STM32_OTGHS_PCGCCTL (STM32_OTGHS_BASE+STM32_OTGHS_PCGCCTL_OFFSET) - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGHS_DFIFO_DEP(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP_OFFSET(n)) -#define STM32_OTGHS_DFIFO_HCH(n) (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH_OFFSET(n)) - -#define STM32_OTGHS_DFIFO_DEP0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP0_OFFSET) -#define STM32_OTGHS_DFIFO_HCH0 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH0_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP1_OFFSET) -#define STM32_OTGHS_DFIFO_HCH1 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH1_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP2_OFFSET) -#define STM32_OTGHS_DFIFO_HCH2 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH2_OFFSET) - -#define STM32_OTGHS_DFIFO_DEP3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_DEP3_OFFSET) -#define STM32_OTGHS_DFIFO_HCH3 (STM32_OTGHS_BASE+STM32_OTGHS_DFIFO_HCH3_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Core global control and status registers */ - -/* Control and status register */ - -#define OTGHS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ -#define OTGHS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ - /* Bits 2-72 Reserved, must be kept at reset value */ -#define OTGHS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ -#define OTGHS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ -#define OTGHS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ -#define OTGHS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ - /* Bits 12-15: Reserved, must be kept at reset value */ -#define OTGHS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ -#define OTGHS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ -#define OTGHS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ -#define OTGHS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* Interrupt register */ - -/* Bits 1:0 Reserved, - * must be kept at reset value - */ -#define OTGHS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ - /* Bits 3-7: Reserved, must be kept at reset value */ -#define OTGHS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ -#define OTGHS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ - /* Bits 16:10 Reserved, must be kept at reset value */ -#define OTGHS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ -#define OTGHS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ -#define OTGHS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ - /* Bits 2-31: Reserved, must be kept at reset value */ - -/* AHB configuration register */ - -#define OTGHS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ - /* Bits 1-6: Reserved, must be kept at reset value */ -#define OTGHS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ -#define OTGHS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* USB configuration register */ - -#define OTGHS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ -#define OTGHS_GUSBCFG_TOCAL_MASK (7 << OTGHS_GUSBCFG_TOCAL_SHIFT) - /* Bits 3-5: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ - /* Bit 7: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ -#define OTGHS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ -#define OTGHS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ -#define OTGHS_GUSBCFG_TRDT_MASK (15 << OTGHS_GUSBCFG_TRDT_SHIFT) -# define OTGHS_GUSBCFG_TRDT(n) ((n) << OTGHS_GUSBCFG_TRDT_SHIFT) - /* Bits 14-28: Reserved, must be kept at reset value */ -#define OTGHS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ -#define OTGHS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ -#define OTGHS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* Reset register */ - -#define OTGHS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ -#define OTGHS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ -#define OTGHS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ - /* Bit 3 Reserved, must be kept at reset value */ -#define OTGHS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ -#define OTGHS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ -#define OTGHS_GRSTCTL_TXFNUM_SHIFT (10) /* Bits 6-10: TxFIFO number */ -#define OTGHS_GRSTCTL_TXFNUM_MASK (31 << OTGHS_GRSTCTL_TXFNUM_SHIFT) -# define OTGHS_GRSTCTL_TXFNUM_HNONPER (0 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ -# define OTGHS_GRSTCTL_TXFNUM_HPER (1 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ -# define OTGHS_GRSTCTL_TXFNUM_HALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ -# define OTGHS_GRSTCTL_TXFNUM_D(n) ((n) << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ -# define OTGHS_GRSTCTL_TXFNUM_DALL (16 << OTGHS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ - -/* Bits 11-31: Reserved, - * must be kept at reset value - */ -#define OTGHS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ - -/* Core interrupt and Interrupt mask registers */ - -#define OTGHS_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ -# define OTGHS_GINTSTS_DEVMODE (0) -# define OTGHS_GINTSTS_HOSTMODE (OTGHS_GINTSTS_CMOD) -#define OTGHS_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ -#define OTGHS_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ -#define OTGHS_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ -#define OTGHS_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ -#define OTGHS_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ -#define OTGHS_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ -#define OTGHS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ - /* Bits 8-9: Reserved, must be kept at reset value */ -#define OTGHS_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ -#define OTGHS_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ -#define OTGHS_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ -#define OTGHS_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ -#define OTGHS_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ -#define OTGHS_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ - /* Bits 16 Reserved, must be kept at reset value */ -#define OTGHS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ -#define OTGHS_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ -#define OTGHS_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ -#define OTGHS_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ -#define OTGHS_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer */ -#define OTGHS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ - /* Bits 22-23: Reserved, must be kept at reset value */ -#define OTGHS_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ -#define OTGHS_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ -#define OTGHS_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ - /* Bit 27 Reserved, must be kept at reset value */ -#define OTGHS_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ -#define OTGHS_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ -#define OTGHS_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ -#define OTGHS_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ - -/* Receive status debug read/OTG status read and pop registers (host mode) */ - -#define OTGHS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ -#define OTGHS_GRXSTSH_CHNUM_MASK (15 << OTGHS_GRXSTSH_CHNUM_SHIFT) -#define OTGHS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGHS_GRXSTSH_BCNT_MASK (0x7ff << OTGHS_GRXSTSH_BCNT_SHIFT) -#define OTGHS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGHS_GRXSTSH_DPID_MASK (3 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA0 (0 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA2 (1 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_DATA1 (2 << OTGHS_GRXSTSH_DPID_SHIFT) -# define OTGHS_GRXSTSH_DPID_MDATA (3 << OTGHS_GRXSTSH_DPID_SHIFT) -#define OTGHS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGHS_GRXSTSH_PKTSTS_MASK (15 << OTGHS_GRXSTSH_PKTSTS_SHIFT) -# define OTGHS_GRXSTSH_PKTSTS_INRECVD (2 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ -# define OTGHS_GRXSTSH_PKTSTS_INDONE (3 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ -# define OTGHS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ -# define OTGHS_GRXSTSH_PKTSTS_HALTED (7 << OTGHS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ - -/* Bits 21-31: Reserved, - * must be kept at reset value - */ - -/* Receive status debug read/OTG status read and pop registers - * (device mode) - */ - -#define OTGHS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ -#define OTGHS_GRXSTSD_EPNUM_MASK (15 << OTGHS_GRXSTSD_EPNUM_SHIFT) -#define OTGHS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGHS_GRXSTSD_BCNT_MASK (0x7ff << OTGHS_GRXSTSD_BCNT_SHIFT) -#define OTGHS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGHS_GRXSTSD_DPID_MASK (3 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA0 (0 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA2 (1 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_DATA1 (2 << OTGHS_GRXSTSD_DPID_SHIFT) -# define OTGHS_GRXSTSD_DPID_MDATA (3 << OTGHS_GRXSTSD_DPID_SHIFT) -#define OTGHS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGHS_GRXSTSD_PKTSTS_MASK (15 << OTGHS_GRXSTSD_PKTSTS_SHIFT) -# define OTGHS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ -# define OTGHS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ -# define OTGHS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ -# define OTGHS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ -# define OTGHS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGHS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ - -#define OTGHS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ -#define OTGHS_GRXSTSD_FRMNUM_MASK (15 << OTGHS_GRXSTSD_FRMNUM_SHIFT) - /* Bits 25-31: Reserved, must be kept at reset value */ - -/* Receive FIFO size register */ - -#define OTGHS_GRXFSIZ_MASK (0xffff) - -/* Host non-periodic transmit FIFO size register */ - -#define OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ -#define OTGHS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFSA_SHIFT) -#define OTGHS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ -#define OTGHS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGHS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGHS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGHS_HNPTXFSIZ_NPTXFD_SHIFT) - -/* Endpoint 0 Transmit FIFO size */ - -#define OTGHS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ -#define OTGHS_DIEPTXF0_TX0FD_MASK (0xffff << OTGHS_DIEPTXF0_TX0FD_SHIFT) -#define OTGHS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ -#define OTGHS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGHS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGHS_DIEPTXF0_TX0FSA_MIN (16 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGHS_DIEPTXF0_TX0FSA_MAX (256 << OTGHS_DIEPTXF0_TX0FSA_SHIFT) - -/* Non-periodic transmit FIFO/queue status register */ - -#define OTGHS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ -#define OTGHS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) -# define OTGHS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGHS_HNPTXSTS_NPTXFSAV_SHIFT) -#define OTGHS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ -#define OTGHS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) -# define OTGHS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGHS_HNPTXSTS_NPTQXSAV_SHIFT) -#define OTGHS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ -#define OTGHS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGHS_HNPTXSTS_NPTXQTOP_SHIFT) -# define OTGHS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGHS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ -# define OTGHS_HNPTXSTS_TYPE_MASK (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) -# define OTGHS_HNPTXSTS_TYPE_INOUT (0 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGHS_HNPTXSTS_TYPE_ZLP (1 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ -# define OTGHS_HNPTXSTS_TYPE_HALT (3 << OTGHS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ - -# define OTGHS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGHS_HNPTXSTS_CHNUM_MASK (15 << OTGHS_HNPTXSTS_CHNUM_SHIFT) -# define OTGHS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGHS_HNPTXSTS_EPNUM_MASK (15 << OTGHS_HNPTXSTS_EPNUM_SHIFT) - /* Bit 31 Reserved, must be kept at reset value */ - -/* General core configuration register */ - -/* Bits 15:0 Reserved, - * must be kept at reset value - */ -#define OTGHS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ - /* Bit 17 Reserved, must be kept at reset value */ -#define OTGHS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing “A” device */ -#define OTGHS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing “B” device */ -#define OTGHS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ -#define OTGHS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ - /* Bits 31:22 Reserved, must be kept at reset value */ - -/* Core ID register (32-bit product ID) */ - -/* Host periodic transmit FIFO size register */ - -#define OTGHS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ -#define OTGHS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGHS_HPTXFSIZ_PTXSA_SHIFT) -#define OTGHS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ -#define OTGHS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGHS_HPTXFSIZ_PTXFD_SHIFT) - -/* Device IN endpoint transmit FIFOn size register */ - -#define OTGHS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ -#define OTGHS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGHS_DIEPTXF_INEPTXSA_SHIFT) -#define OTGHS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ -#define OTGHS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGHS_DIEPTXF_INEPTXFD_SHIFT) -# define OTGHS_DIEPTXF_INEPTXFD_MIN (16 << OTGHS_DIEPTXF_INEPTXFD_MASK) - -/* Host-mode control and status registers */ - -/* Host configuration register */ - -#define OTGHS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ -#define OTGHS_HCFG_FSLSPCS_MASK (3 << OTGHS_HCFG_FSLSPCS_SHIFT) -# define OTGHS_HCFG_FSLSPCS_FS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ -# define OTGHS_HCFG_FSLSPCS_LS48MHz (1 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ -# define OTGHS_HCFG_FSLSPCS_LS6MHz (2 << OTGHS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ - -#define OTGHS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ - /* Bits 31:3 Reserved, must be kept at reset value */ - -/* Host frame interval register */ - -#define OTGHS_HFIR_MASK (0xffff) - -/* Host frame number/frame time remaining register */ - -#define OTGHS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ -#define OTGHS_HFNUM_FRNUM_MASK (0xffff << OTGHS_HFNUM_FRNUM_SHIFT) -#define OTGHS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ -#define OTGHS_HFNUM_FTREM_MASK (0xffff << OTGHS_HFNUM_FTREM_SHIFT) - -/* Host periodic transmit FIFO/queue status register */ - -#define OTGHS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ -#define OTGHS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) -# define OTGHS_HPTXSTS_PTXFSAVL_FULL (0 << OTGHS_HPTXSTS_PTXFSAVL_SHIFT) -#define OTGHS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ -#define OTGHS_HPTXSTS_PTXQSAV_MASK (0xff << OTGHS_HPTXSTS_PTXQSAV_SHIFT) -# define OTGHS_HPTXSTS_PTXQSAV_FULL (0 << OTGHS_HPTXSTS_PTXQSAV_SHIFT) -#define OTGHS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ -#define OTGHS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGHS_HPTXSTS_PTXQTOP_SHIFT) -# define OTGHS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGHS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ -# define OTGHS_HPTXSTS_TYPE_MASK (3 << OTGHS_HPTXSTS_TYPE_SHIFT) -# define OTGHS_HPTXSTS_TYPE_INOUT (0 << OTGHS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGHS_HPTXSTS_TYPE_ZLP (1 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ -# define OTGHS_HPTXSTS_TYPE_HALT (3 << OTGHS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ - -# define OTGHS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGHS_HPTXSTS_EPNUM_MASK (15 << OTGHS_HPTXSTS_EPNUM_SHIFT) -# define OTGHS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGHS_HPTXSTS_CHNUM_MASK (15 << OTGHS_HPTXSTS_CHNUM_SHIFT) -# define OTGHS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ - -/* Host all channels interrupt and all channels interrupt mask registers */ - -#define OTGHS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ - -/* Host port control and status register */ - -#define OTGHS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ -#define OTGHS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ -#define OTGHS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ -#define OTGHS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ -#define OTGHS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ -#define OTGHS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ -#define OTGHS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ -#define OTGHS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ -#define OTGHS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ - /* Bit 9: Reserved, must be kept at reset value */ -#define OTGHS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ -#define OTGHS_HPRT_PLSTS_MASK (3 << OTGHS_HPRT_PLSTS_SHIFT) -# define OTGHS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ -# define OTGHS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ -#define OTGHS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ -#define OTGHS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ -#define OTGHS_HPRT_PTCTL_MASK (15 << OTGHS_HPRT_PTCTL_SHIFT) -# define OTGHS_HPRT_PTCTL_DISABLED (0 << OTGHS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ -# define OTGHS_HPRT_PTCTL_J (1 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_J mode */ -# define OTGHS_HPRT_PTCTL_L (2 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_K mode */ -# define OTGHS_HPRT_PTCTL_SE0_NAK (3 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGHS_HPRT_PTCTL_PACKET (4 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ -# define OTGHS_HPRT_PTCTL_FORCE (5 << OTGHS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGHS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ -#define OTGHS_HPRT_PSPD_MASK (3 << OTGHS_HPRT_PSPD_SHIFT) -# define OTGHS_HPRT_PSPD_FS (1 << OTGHS_HPRT_PSPD_SHIFT) /* Full speed */ -# define OTGHS_HPRT_PSPD_LS (2 << OTGHS_HPRT_PSPD_SHIFT) /* Low speed */ - -/* Bits 19-31: Reserved, - * must be kept at reset value - */ - -/* Host channel-n characteristics register */ - -#define OTGHS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_HCCHAR_MPSIZ_MASK (0x7ff << OTGHS_HCCHAR_MPSIZ_SHIFT) -#define OTGHS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ -#define OTGHS_HCCHAR_EPNUM_MASK (15 << OTGHS_HCCHAR_EPNUM_SHIFT) -#define OTGHS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ -# define OTGHS_HCCHAR_EPDIR_OUT (0) -# define OTGHS_HCCHAR_EPDIR_IN OTGHS_HCCHAR_EPDIR - /* Bit 16 Reserved, must be kept at reset value */ -#define OTGHS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ -#define OTGHS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_HCCHAR_EPTYP_MASK (3 << OTGHS_HCCHAR_EPTYP_SHIFT) -# define OTGHS_HCCHAR_EPTYP_CTRL (0 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Control */ -# define OTGHS_HCCHAR_EPTYP_ISOC (1 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_HCCHAR_EPTYP_BULK (2 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_HCCHAR_EPTYP_INTR (3 << OTGHS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ - -#define OTGHS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ -#define OTGHS_HCCHAR_MCNT_MASK (3 << OTGHS_HCCHAR_MCNT_SHIFT) -#define OTGHS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ -#define OTGHS_HCCHAR_DAD_MASK (0x7f << OTGHS_HCCHAR_DAD_SHIFT) -#define OTGHS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ -#define OTGHS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ -#define OTGHS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ - -/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ - -#define OTGHS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ -#define OTGHS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ -#define OTGHS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ -#define OTGHS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ -#define OTGHS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ -#define OTGHS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ -#define OTGHS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ -#define OTGHS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ -#define OTGHS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ - /* Bits 11-31 Reserved, must be kept at reset value */ - -/* Host channel-n interrupt register */ - -#define OTGHS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_HCTSIZ_XFRSIZ_SHIFT) -#define OTGHS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ -#define OTGHS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGHS_HCTSIZ_PKTCNT_SHIFT) -#define OTGHS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ -#define OTGHS_HCTSIZ_DPID_MASK (3 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA0 (0 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA2 (1 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_DATA1 (2 << OTGHS_HCTSIZ_DPID_SHIFT) -# define OTGHS_HCTSIZ_DPID_MDATA (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Non-control */ -# define OTGHS_HCTSIZ_PID_SETUP (3 << OTGHS_HCTSIZ_DPID_SHIFT) /* Control */ - -/* Bit 31 Reserved, - * must be kept at reset value - */ - -/* Device-mode control and status registers */ - -/* Device configuration register */ - -#define OTGHS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ -#define OTGHS_DCFG_DSPD_MASK (3 << OTGHS_DCFG_DSPD_SHIFT) -# define OTGHS_DCFG_DSPD_FS (3 << OTGHS_DCFG_DSPD_SHIFT) /* Full speed */ - -#define OTGHS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ - /* Bit 3: Reserved, must be kept at reset value */ -#define OTGHS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ -#define OTGHS_DCFG_DAD_MASK (0x7f << OTGHS_DCFG_DAD_SHIFT) -#define OTGHS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ -#define OTGHS_DCFG_PFIVL_MASK (3 << OTGHS_DCFG_PFIVL_SHIFT) -# define OTGHS_DCFG_PFIVL_80PCT (0 << OTGHS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ -# define OTGHS_DCFG_PFIVL_85PCT (1 << OTGHS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ -# define OTGHS_DCFG_PFIVL_90PCT (2 << OTGHS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ -# define OTGHS_DCFG_PFIVL_95PCT (3 << OTGHS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ - -/* Bits 13-31 Reserved, - * must be kept at reset value - */ - -/* Device control register */ - -#define OTGHS_TESTMODE_DISABLED (0) /* Test mode disabled */ -#define OTGHS_TESTMODE_J (1) /* Test_J mode */ -#define OTGHS_TESTMODE_K (2) /* Test_K mode */ -#define OTGHS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ -#define OTGHS_TESTMODE_PACKET (4) /* Test_Packet mode */ -#define OTGHS_TESTMODE_FORCE (5) /* Test_Force_Enable */ - -#define OTGHS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ -#define OTGHS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ -#define OTGHS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ -#define OTGHS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ -#define OTGHS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ -#define OTGHS_DCTL_TCTL_MASK (7 << OTGHS_DCTL_TCTL_SHIFT) -# define OTGHS_DCTL_TCTL_DISABLED (0 << OTGHS_DCTL_TCTL_SHIFT) /* Test mode disabled */ -# define OTGHS_DCTL_TCTL_J (1 << OTGHS_DCTL_TCTL_SHIFT) /* Test_J mode */ -# define OTGHS_DCTL_TCTL_K (2 << OTGHS_DCTL_TCTL_SHIFT) /* Test_K mode */ -# define OTGHS_DCTL_TCTL_SE0_NAK (3 << OTGHS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGHS_DCTL_TCTL_PACKET (4 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ -# define OTGHS_DCTL_TCTL_FORCE (5 << OTGHS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGHS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ -#define OTGHS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ -#define OTGHS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ -#define OTGHS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ -#define OTGHS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ - /* Bits 12-31: Reserved, must be kept at reset value */ - -/* Device status register */ - -#define OTGHS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ -#define OTGHS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ -#define OTGHS_DSTS_ENUMSPD_MASK (3 << OTGHS_DSTS_ENUMSPD_SHIFT) -# define OTGHS_DSTS_ENUMSPD_FS (3 << OTGHS_DSTS_ENUMSPD_MASK) /* Full speed */ - -/* Bits 4-7: Reserved, - * must be kept at reset value - */ -#define OTGHS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ -#define OTGHS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ -#define OTGHS_DSTS_SOFFN_MASK (0x3fff << OTGHS_DSTS_SOFFN_SHIFT) -#define OTGHS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ -#define OTGHS_DSTS_SOFFN_EVEN 0 -#define OTGHS_DSTS_SOFFN_ODD OTGHS_DSTS_SOFFN0 - /* Bits 22-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint common interrupt mask register */ - -#define OTGHS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGHS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ -#define OTGHS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ -#define OTGHS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ -#define OTGHS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint common interrupt mask register */ - -#define OTGHS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGHS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ -#define OTGHS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -/* Device all endpoints interrupt and All endpoints interrupt - * mask registers - */ - -#define OTGHS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ -#define OTGHS_DAINT_IEP_MASK (0xffff << OTGHS_DAINT_IEP_SHIFT) -# define OTGHS_DAINT_IEP(n) (1 << (n)) -#define OTGHS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ -#define OTGHS_DAINT_OEP_MASK (0xffff << OTGHS_DAINT_OEP_SHIFT) -# define OTGHS_DAINT_OEP(n) (1 << ((n)+16)) - -/* Device VBUS discharge time register */ - -#define OTGHS_DVBUSDIS_MASK (0xffff) - -/* Device VBUS pulsing time register */ - -#define OTGHS_DVBUSPULSE_MASK (0xfff) - -/* Device IN endpoint FIFO empty interrupt mask register */ - -#define OTGHS_DIEPEMPMSK(n) (1 << (n)) - -/* Device control IN endpoint 0 control register */ - -#define OTGHS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGHS_DIEPCTL0_MPSIZ_MASK (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) -# define OTGHS_DIEPCTL0_MPSIZ_64 (0 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_32 (1 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_16 (2 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGHS_DIEPCTL0_MPSIZ_8 (3 << OTGHS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DIEPCTL0_EPTYP_MASK (3 << OTGHS_DIEPCTL0_EPTYP_SHIFT) -# define OTGHS_DIEPCTL0_EPTYP_CTRL (0 << OTGHS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGHS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGHS_DIEPCTL0_TXFNUM_MASK (15 << OTGHS_DIEPCTL0_TXFNUM_SHIFT) -#define OTGHS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device control IN endpoint n control register */ - -#define OTGHS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DIEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGHS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGHS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ -# define OTGHS_DIEPCTL_EVEN (0) -# define OTGHS_DIEPCTL_ODD OTGHS_DIEPCTL_EONUM -# define OTGHS_DIEPCTL_DATA0 (0) -# define OTGHS_DIEPCTL_DATA1 OTGHS_DIEPCTL_EONUM -#define OTGHS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DIEPCTL_EPTYP_MASK (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) -# define OTGHS_DIEPCTL_EPTYP_CTRL (0 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGHS_DIEPCTL_EPTYP_ISOC (1 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_DIEPCTL_EPTYP_BULK (2 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_DIEPCTL_EPTYP_INTR (3 << OTGHS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGHS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGHS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGHS_DIEPCTL_TXFNUM_MASK (15 << OTGHS_DIEPCTL_TXFNUM_SHIFT) -#define OTGHS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGHS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGHS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ -#define OTGHS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ -#define OTGHS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGHS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGHS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ -#define OTGHS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGHS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ -#define OTGHS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ - /* Bits 8-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint 0 transfer size register */ - -#define OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGHS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DIEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGHS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ -#define OTGHS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGHS_DIEPTSIZ0_PKTCNT_SHIFT) - /* Bits 21-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint n transfer size register */ - -#define OTGHS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DIEPTSIZ_XFRSIZ_SHIFT) -#define OTGHS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGHS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DIEPTSIZ_PKTCNT_SHIFT) -#define OTGHS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ -#define OTGHS_DIEPTSIZ_MCNT_MASK (3 << OTGHS_DIEPTSIZ_MCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint TxFIFO status register */ - -#define OTGHS_DTXFSTS_MASK (0xffff) - -/* Device OUT endpoint 0 control register */ - -#define OTGHS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGHS_DOEPCTL0_MPSIZ_MASK (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) -# define OTGHS_DOEPCTL0_MPSIZ_64 (0 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_32 (1 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_16 (2 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGHS_DOEPCTL0_MPSIZ_8 (3 << OTGHS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGHS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DOEPCTL0_EPTYP_MASK (3 << OTGHS_DOEPCTL0_EPTYP_SHIFT) -# define OTGHS_DOEPCTL0_EPTYP_CTRL (0 << OTGHS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -#define OTGHS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGHS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device OUT endpoint n control register */ - -#define OTGHS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGHS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGHS_DOEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGHS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ -# define OTGHS_DOEPCTL_DATA0 (0) -# define OTGHS_DOEPCTL_DATA1 OTGHS_DOEPCTL_DPID -#define OTGHS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ -# define OTGHS_DOEPCTL_EVEN (0) -# define OTGHS_DOEPCTL_ODD OTGHS_DOEPCTL_EONUM -#define OTGHS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGHS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGHS_DOEPCTL_EPTYP_MASK (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) -# define OTGHS_DOEPCTL_EPTYP_CTRL (0 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGHS_DOEPCTL_EPTYP_ISOC (1 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGHS_DOEPCTL_EPTYP_BULK (2 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGHS_DOEPCTL_EPTYP_INTR (3 << OTGHS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ - -#define OTGHS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGHS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGHS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGHS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGHS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGHS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ -#define OTGHS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ -#define OTGHS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ -#define OTGHS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGHS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGHS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGHS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGHS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ -#define OTGHS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGHS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-0 transfer size register */ - -#define OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGHS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGHS_DOEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGHS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ - /* Bits 20-28: Reserved, must be kept at reset value */ -#define OTGHS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGHS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ0_STUPCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-n transfer size register */ - -#define OTGHS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGHS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGHS_DOEPTSIZ_XFRSIZ_SHIFT) -#define OTGHS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGHS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGHS_DOEPTSIZ_PKTCNT_SHIFT) -#define OTGHS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGHS_DOEPTSIZ_STUPCNT_MASK (3 << OTGHS_DOEPTSIZ_STUPCNT_SHIFT) -#define OTGHS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ -#define OTGHS_DOEPTSIZ_RXDPID_MASK (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGHS_DOEPTSIZ_RXDPID_MDATA (3 << OTGHS_DOEPTSIZ_RXDPID_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Power and clock gating control register */ - -#define OTGHS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ -#define OTGHS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ - /* Bits 2-3: Reserved, must be kept at reset value */ -#define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtc.h b/arch/arm/src/stm32/hardware/stm32_rtc.h deleted file mode 100644 index fc768d7aa027d..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_rtc.h +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RTC_CRH_OFFSET 0x0000 /* RTC control register High (16-bit) */ -#define STM32_RTC_CRL_OFFSET 0x0004 /* RTC control register low (16-bit) */ -#define STM32_RTC_PRLH_OFFSET 0x0008 /* RTC prescaler load register high (16-bit) */ -#define STM32_RTC_PRLL_OFFSET 0x000c /* RTC prescaler load register low (16-bit) */ -#define STM32_RTC_DIVH_OFFSET 0x0010 /* RTC prescaler divider register high (16-bit) */ -#define STM32_RTC_DIVL_OFFSET 0x0014 /* RTC prescaler divider register low (16-bit) */ -#define STM32_RTC_CNTH_OFFSET 0x0018 /* RTC counter register high (16-bit) */ -#define STM32_RTC_CNTL_OFFSET 0x001c /* RTC counter register low (16-bit) */ -#define STM32_RTC_ALRH_OFFSET 0x0020 /* RTC alarm register high (16-bit) */ -#define STM32_RTC_ALRL_OFFSET 0x0024 /* RTC alarm register low (16-bit) */ - -/* Register Addresses *******************************************************/ - -#define STM32_RTC_CRH (STM32_RTC_BASE+STM32_RTC_CRH_OFFSET) -#define STM32_RTC_CRL (STM32_RTC_BASE+STM32_RTC_CRL_OFFSET) -#define STM32_RTC_PRLH (STM32_RTC_BASE+STM32_RTC_PRLH_OFFSET) -#define STM32_RTC_PRLL (STM32_RTC_BASE+STM32_RTC_PRLL_OFFSET) -#define STM32_RTC_DIVH (STM32_RTC_BASE+STM32_RTC_DIVH_OFFSET) -#define STM32_RTC_DIVL (STM32_RTC_BASE+STM32_RTC_DIVL_OFFSET) -#define STM32_RTC_CNTH (STM32_RTC_BASE+STM32_RTC_CNTH_OFFSET) -#define STM32_RTC_CNTL (STM32_RTC_BASE+STM32_RTC_CNTL_OFFSET) -#define STM32_RTC_ALRH (STM32_RTC_BASE+STM32_RTC_ALRH_OFFSET) -#define STM32_RTC_ALRL (STM32_RTC_BASE+STM32_RTC_ALRL_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* RTC control register High (16-bit) */ - -#define RTC_CRH_SECIE (1 << 0) /* Bit 0 : Second Interrupt Enable */ -#define RTC_CRH_ALRIE (1 << 1) /* Bit 1: Alarm Interrupt Enable */ -#define RTC_CRH_OWIE (1 << 2) /* Bit 2: OverfloW Interrupt Enable */ - -/* RTC control register low (16-bit) */ - -#define RTC_CRL_SECF (1 << 0) /* Bit 0: Second Flag */ -#define RTC_CRL_ALRF (1 << 1) /* Bit 1: Alarm Flag */ -#define RTC_CRL_OWF (1 << 2) /* Bit 2: Overflow Flag */ -#define RTC_CRL_RSF (1 << 3) /* Bit 3: Registers Synchronized Flag */ -#define RTC_CRL_CNF (1 << 4) /* Bit 4: Configuration Flag */ -#define RTC_CRL_RTOFF (1 << 5) /* Bit 5: RTC operation OFF */ - -/* RTC prescaler load register high (16-bit) */ - -#define RTC_PRLH_PRL_SHIFT (0) /* Bits 3-0: RTC Prescaler Reload Value High */ -#define RTC_PRLH_PRL_MASK (0x0f << RTC_PRLH_PRL_SHIFT) - -/* RTC prescaler divider register high (16-bit) */ - -#define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ -#define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_sdio.h b/arch/arm/src/stm32/hardware/stm32_sdio.h deleted file mode 100644 index 4c732893275c8..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_sdio.h +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_sdio.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_SDIO_POWER_OFFSET 0x0000 /* SDIO power control register */ -#define STM32_SDIO_CLKCR_OFFSET 0x0004 /* SDI clock control register */ -#define STM32_SDIO_ARG_OFFSET 0x0008 /* SDIO argument register */ -#define STM32_SDIO_CMD_OFFSET 0x000c /* SDIO command register */ -#define STM32_SDIO_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ -#define STM32_SDIO_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDIO_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ -#define STM32_SDIO_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ -#define STM32_SDIO_RESP3_OFFSET 0x001c /* SDIO response 3 register */ -#define STM32_SDIO_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ -#define STM32_SDIO_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ -#define STM32_SDIO_DLEN_OFFSET 0x0028 /* SDIO data length register */ -#define STM32_SDIO_DCTRL_OFFSET 0x002c /* SDIO data control register */ -#define STM32_SDIO_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ -#define STM32_SDIO_STA_OFFSET 0x0034 /* SDIO status register */ -#define STM32_SDIO_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ -#define STM32_SDIO_MASK_OFFSET 0x003c /* SDIO mask register */ -#define STM32_SDIO_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ -#define STM32_SDIO_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ - -/* Register Addresses *******************************************************/ - -#define STM32_SDIO_POWER (STM32_SDIO_BASE+STM32_SDIO_POWER_OFFSET) -#define STM32_SDIO_CLKCR (STM32_SDIO_BASE+STM32_SDIO_CLKCR_OFFSET) -#define STM32_SDIO_ARG (STM32_SDIO_BASE+STM32_SDIO_ARG_OFFSET) -#define STM32_SDIO_CMD (STM32_SDIO_BASE+STM32_SDIO_CMD_OFFSET) -#define STM32_SDIO_RESPCMD (STM32_SDIO_BASE+STM32_SDIO_RESPCMD_OFFSET) -#define STM32_SDIO_RESP(n) (STM32_SDIO_BASE+STM32_SDIO_RESP_OFFSET(n)) -#define STM32_SDIO_RESP1 (STM32_SDIO_BASE+STM32_SDIO_RESP1_OFFSET) -#define STM32_SDIO_RESP2 (STM32_SDIO_BASE+STM32_SDIO_RESP2_OFFSET) -#define STM32_SDIO_RESP3 (STM32_SDIO_BASE+STM32_SDIO_RESP3_OFFSET) -#define STM32_SDIO_RESP4 (STM32_SDIO_BASE+STM32_SDIO_RESP4_OFFSET) -#define STM32_SDIO_DTIMER (STM32_SDIO_BASE+STM32_SDIO_DTIMER_OFFSET) -#define STM32_SDIO_DLEN (STM32_SDIO_BASE+STM32_SDIO_DLEN_OFFSET) -#define STM32_SDIO_DCTRL (STM32_SDIO_BASE+STM32_SDIO_DCTRL_OFFSET) -#define STM32_SDIO_DCOUNT (STM32_SDIO_BASE+STM32_SDIO_DCOUNT_OFFSET) -#define STM32_SDIO_STA (STM32_SDIO_BASE+STM32_SDIO_STA_OFFSET) -#define STM32_SDIO_ICR (STM32_SDIO_BASE+STM32_SDIO_ICR_OFFSET) -#define STM32_SDIO_MASK (STM32_SDIO_BASE+STM32_SDIO_MASK_OFFSET) -#define STM32_SDIO_FIFOCNT (STM32_SDIO_BASE+STM32_SDIO_FIFOCNT_OFFSET) -#define STM32_SDIO_FIFO (STM32_SDIO_BASE+STM32_SDIO_FIFO_OFFSET) - -/* Bit-band (BB) base addresses *********************************************/ - -#define STM32_SDIO_OFFSET (STM32_SDIO_BASE-STM32_PERIPH_BASE) - -#define STM32_SDIO_POWER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_POWER_OFFSET)<<5)) -#define STM32_SDIO_CLKCR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CLKCR_OFFSET)<<5)) -#define STM32_SDIO_ARG_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ARG_OFFSET)<<5)) -#define STM32_SDIO_CMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_CMD_OFFSET)<<5)) -#define STM32_SDIO_RESPCMD_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESPCMD_OFFSET)<<5)) -#define STM32_SDIO_RESP_BB(n) (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP_OFFSET(n))<<5)) -#define STM32_SDIO_RESP1_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP1_OFFSET)<<5)) -#define STM32_SDIO_RESP2_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP2_OFFSET)<<5)) -#define STM32_SDIO_RESP3_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP3_OFFSET)<<5)) -#define STM32_SDIO_RESP4_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_RESP4_OFFSET)<<5)) -#define STM32_SDIO_DTIMER_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DTIMER_OFFSET)<<5)) -#define STM32_SDIO_DLEN_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DLEN_OFFSET)<<5)) -#define STM32_SDIO_DCTRL_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCTRL_OFFSET)<<5)) -#define STM32_SDIO_DCOUNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_DCOUNT_OFFSET)<<5)) -#define STM32_SDIO_STA_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_STA_OFFSET)<<5)) -#define STM32_SDIO_ICR_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_ICR_OFFSET)<<5)) -#define STM32_SDIO_MASK_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_MASK_OFFSET)<<5)) -#define STM32_SDIO_FIFOCNT_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFOCNT_OFFSET)<<5)) -#define STM32_SDIO_FIFO_BB (STM32_PERIPHBB_BASE+((STM32_SDIO_OFFSET+STM32_SDIO_FIFO_OFFSET)<<5)) - -/* Register Bitfield Definitions ********************************************/ - -#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) -# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define SDIO_POWER_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) -#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) -# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ -# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ -# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ - -#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define SDIO_CLKCR_RESET (0) /* Reset value */ -#define SDIO_ARG_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKEN_BB (STM32_SDIO_CLKCR_BB + (8 * 4)) -#define SDIO_CLKCR_PWRSAV_BB (STM32_SDIO_CLKCR_BB + (9 * 4)) -#define SDIO_CLKCR_BYPASS_BB (STM32_SDIO_CLKCR_BB + (10 * 4)) -#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDIO_CLKCR_BB + (13 * 4)) -#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDIO_CLKCR_BB + (14 * 4)) - -#define SDIO_CMD_CMDINDEX_SHIFT (0) -#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) -#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) -# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ - -#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define SDIO_CMD_RESET (0) /* Reset value */ - -#define SDIO_CMD_WAITINT_BB (STM32_SDIO_CMD_BB + (8 * 4)) -#define SDIO_CMD_WAITPEND_BB (STM32_SDIO_CMD_BB + (9 * 4)) -#define SDIO_CMD_CPSMEN_BB (STM32_SDIO_CMD_BB + (10 * 4)) -#define SDIO_CMD_SUSPEND_BB (STM32_SDIO_CMD_BB + (11 * 4)) -#define SDIO_CMD_ENCMD_BB (STM32_SDIO_CMD_BB + (12 * 4)) -#define SDIO_CMD_NIEN_BB (STM32_SDIO_CMD_BB + (13 * 4)) -#define SDIO_CMD_ATACMD_BB (STM32_SDIO_CMD_BB + (14 * 4)) - -#define SDIO_RESPCMD_SHIFT (0) -#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) - -#define SDIO_DTIMER_RESET (0) /* Reset value */ - -#define SDIO_DLEN_SHIFT (0) -#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) - -#define SDIO_DLEN_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define SDIO_DCTRL_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN_BB (STM32_SDIO_DCTRL_BB + (0 * 4)) -#define SDIO_DCTRL_DTDIR_BB (STM32_SDIO_DCTRL_BB + (1 * 4)) -#define SDIO_DCTRL_DTMODE_BB (STM32_SDIO_DCTRL_BB + (2 * 4)) -#define SDIO_DCTRL_DMAEN_BB (STM32_SDIO_DCTRL_BB + (3 * 4)) -#define SDIO_DCTRL_RWSTART_BB (STM32_SDIO_DCTRL_BB + (8 * 4)) -#define SDIO_DCTRL_RWSTOP_BB (STM32_SDIO_DCTRL_BB + (9 * 4)) -#define SDIO_DCTRL_RWMOD_BB (STM32_SDIO_DCTRL_BB + (10 * 4)) -#define SDIO_DCTRL_SDIOEN_BB (STM32_SDIO_DCTRL_BB + (11 * 4)) - -#define SDIO_DATACOUNT_SHIFT (0) -#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) - -#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define SDIO_ICR_RESET 0x00c007ff -#define SDIO_ICR_STATICFLAGS 0x000005ff - -#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define SDIO_MASK_RESET (0) - -#define SDIO_FIFOCNT_SHIFT (0) -#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h deleted file mode 100644 index bf1cfaf5f755c..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ /dev/null @@ -1,1307 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v1v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* TIM version **************************************************************/ - -/* Chip has extended version of ADV Timers (F3/F7/H7/L4/L4+): - * - CCMR3, CCR5 and CCR6 registers - * - OC5 and OC6 - * - 32-bit CCMR register - * - UIFREMAP bit in CR1 register - * - TRGO2 configuration in CR2 register - * - OCCS bit and 4-bit SMS in SMCR register - * - * Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+): - * - UIFREMAP bit in CR1 register - * - 4-bit SMS in SMCR register - */ - -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) -# define HAVE_IP_TIMERS_M3M4_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) -# define HAVE_IP_TIMERS_M3M4_V1 -#else -# error -#endif - -/* TIM16 has OR register (F3/L4) */ - -#ifdef CONFIG_STM32_STM32F30XX -# define HAVE_TIM16_OR -#endif - -/* General Timers have CCxNP bits (not in F1) */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) -# define HAVE_GTIM_CCXNP -#endif - -/* Register Offsets *********************************************************/ - -/* Basic Timers - TIM6 and TIM7 */ - -#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ - -/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, - * and TIM14 - * For the STM32F10xx all timers are 16-bit. - * For the STM32F20xx and STM32F40xx, TIM2 and 5 are 32-bit - * The STM32 F1 Value Line and the STM32 F3 have variant general purpose - * registers that are not yet fully covered in this header file. - */ - -#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit, TIM2-5 only) */ -#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit) */ -#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit, TIM2-5 only) */ -#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit* or 32-bit STM3240 TIM2 and 5 only) */ -#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit STM3240 TIM2/5 only) */ -#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 or STM2 F3 TIM15 only) */ -#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ -#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit STM32 F4 TIM2/5 only) */ -#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit, TIM2-5 only) */ - -/* The Option register is available on in the - * - * STM32 F1 value line, F2 and F4: TIM2, TIM5, and TIM11 - * STM32 F3 (and possibly the F1 value line): TIM16 - */ - -#define STM32_GTIM_OR_OFFSET 0x0050 /* Timer 2/5/11/16 option register */ - -/* Advanced Timers - TIM1, TIM8 and TIM20 */ - -#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ - -/* Note that many of the above registers are 32-bits wide on the F3 */ - -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -# define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (32-bit) */ -# define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 6 (32-bit) */ -#endif - -/* Register Addresses *******************************************************/ - -/* Advanced Timers - TIM1 and TIM8 */ - -#if STM32_NATIM > 0 -# define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) -# endif -#endif - -#if STM32_NATIM > 1 -# define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) -# define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) -# define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) -# define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) -# define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) -# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) -# define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) -# define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) -# define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) -# define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) -# define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) -# define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) -# endif -#endif - -/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA. - * For the STM32F10xx all timers are 16-bit. - * For the STM32F2xx and STM32F40xx, TIM2 and 5 are 32-bit - */ - -#if STM32_NGTIM > 0 -# define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) -# endif -#endif - -#if STM32_NGTIM > 1 -# define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 2 -# define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 3 -# define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) -# define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) -# endif -#endif - -#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) -#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) -#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) - -#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM16_CCMR2 (STM32_TIM16_BASE+STM32_GTIM_CCMR2_OFFSET) -#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) - -#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) -#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) -#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) -#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) -#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) -#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) -#define STM32_TIM17_CCMR2 (STM32_TIM17_BASE+STM32_GTIM_CCMR2_OFFSET) -#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) -#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) -#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) -#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) -#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) -#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) -#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) -#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) -#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) - -/* 16-bit General Timers - TIM9-14 without DMA. Note that (1) these timers - * support only a subset of the general timer registers are supported, and - * (2) TIM9 and TIM12 differ from the others. - */ - -#if STM32_NGTIMNDMA > 0 -# define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM9_SR (STM32_TIM9_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM9_EGR (STM32_TIM9_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM9_CCMR1 (STM32_TIM9_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM9_CCER (STM32_TIM9_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM9_CNT (STM32_TIM9_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM9_PSC (STM32_TIM9_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM9_ARR (STM32_TIM9_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM9_CCR1 (STM32_TIM9_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) -#endif - -#if STM32_NGTIMNDMA > 1 -# define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM10_EGR (STM32_TIM10_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM10_CCMR1 (STM32_TIM10_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM10_CCER (STM32_TIM10_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM10_CNT (STM32_TIM10_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM10_PSC (STM32_TIM10_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM10_ARR (STM32_TIM10_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -#if STM32_NGTIMNDMA > 2 -# define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM11_EGR (STM32_TIM11_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM11_CCMR1 (STM32_TIM11_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM11_CCER (STM32_TIM11_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM11_CNT (STM32_TIM11_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM11_PSC (STM32_TIM11_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM11_ARR (STM32_TIM11_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM11_CCR1 (STM32_TIM11_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) -#endif - -#if STM32_NGTIMNDMA > 3 -# define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) -# define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM12_SR (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM12_EGR (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM12_CCMR1 (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM12_CCER (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM12_CNT (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM12_PSC (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM12_ARR (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM12_CCR1 (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) -#endif - -#if STM32_NGTIMNDMA > 4 -# define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM13_EGR (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM13_CCMR1 (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM13_CCER (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM13_CNT (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM13_PSC (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM13_ARR (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -#if STM32_NGTIMNDMA > 5 -# define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) -# define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) -# define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) -# define STM32_TIM14_EGR (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET) -# define STM32_TIM14_CCMR1 (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM14_CCER (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET) -# define STM32_TIM14_CNT (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET) -# define STM32_TIM14_PSC (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET) -# define STM32_TIM14_ARR (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET) -# define STM32_TIM14_CCR1 (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET) -#endif - -/* Basic Timers - TIM6 and TIM7 */ - -#if STM32_NBTIM > 0 -# define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) -#endif - -#if STM32_NBTIM > 1 -# define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) -# define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) -# define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) -# define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) -# define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) -# define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) -# define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) -# define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define ATIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned mode selection */ -#define ATIM_CR1_CMS_MASK (3 << ATIM_CR1_CMS_SHIFT) -# define ATIM_CR1_EDGE (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define ATIM_CR1_CENTER1 (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define ATIM_CR1_CENTER2 (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define ATIM_CR1_CENTER3 (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define ATIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock division */ -#define ATIM_CR1_CKD_MASK (3 << ATIM_CR1_CKD_SHIFT) -# define ATIM_CR1_TCKINT (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define ATIM_CR1_2TCKINT (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define ATIM_CR1_4TCKINT (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ -#endif - -/* Control register 2 */ - -#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ -#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ -#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define ATIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define ATIM_CR2_MMS_MASK (7 << ATIM_CR2_MMS_SHIFT) -# define ATIM_CR2_MMS_RESET (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define ATIM_CR2_MMS_ENABLE (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define ATIM_CR2_MMS_UPDATE (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define ATIM_CR2_MMS_COMPP (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS_OC1REF (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define ATIM_CR2_MMS_OC2REF (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define ATIM_CR2_MMS_OC3REF (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define ATIM_CR2_MMS_OC4REF (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ -#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ -# define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -# define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -# define ATIM_CR2_MMS2_MASK (15 << ATIM_CR2_MMS2_SHIFT) -# define ATIM_CR2_MMS2_RESET (0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define ATIM_CR2_MMS2_ENABLE (1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define ATIM_CR2_MMS2_UPDATE (2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0*/ -# define ATIM_CR2_MMS2_COMPP (3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS2_OC1REF (4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC2REF (5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC3REF (6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC4REF (7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC5REF (8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC6REF (9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4 (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC6 (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ -#endif - -/* Slave mode control register */ - -#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define ATIM_SMCR_SMS_MASK (7 << ATIM_SMCR_SMS_SHIFT) -# define ATIM_SMCR_DISAB (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define ATIM_SMCR_ENCMD1 (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define ATIM_SMCR_ENCMD2 (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define ATIM_SMCR_ENCMD3 (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define ATIM_SMCR_RESET (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define ATIM_SMCR_GATED (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define ATIM_SMCR_TRIGGER (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define ATIM_SMCR_EXTCLK1 (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -#endif -#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define ATIM_SMCR_TS_MASK (7 << ATIM_SMCR_TS_SHIFT) -# define ATIM_SMCR_ITR0 (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */ -# define ATIM_SMCR_ITR1 (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */ -# define ATIM_SMCR_ITR2 (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */ -# define ATIM_SMCR_ITR3 (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */ -# define ATIM_SMCR_T1FED (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define ATIM_SMCR_TI1FP1 (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define ATIM_SMCR_T12FP2 (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define ATIM_SMCR_ETRF (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define ATIM_SMCR_ETF_MASK (0x0f << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_SMCR_FDTSd165 (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_SMCR_FDTSd166 (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_SMCR_FDTSd168 (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_SMCR_FDTSd325 (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_SMCR_FDTSd326 (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_SMCR_FDTSd328 (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define ATIM_SMCR_ETPS_MASK (3 << ATIM_SMCR_ETPS_SHIFT) -# define ATIM_SMCR_PSCOFF (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define ATIM_SMCR_ETRPd2 (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define ATIM_SMCR_ETRPd4 (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define ATIM_SMCR_ETRPd8 (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ -#endif - -/* DMA/Interrupt enable register */ - -#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -/* Status register */ - -#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define ATIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ -#endif -#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ -# define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ -#endif - -/* Event generation register */ - -#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ -#endif - -/* Capture/compare mode register 1 -- Output compare mode */ - -#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ -#endif - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define ATIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define ATIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define ATIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define ATIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define ATIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define ATIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define ATIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define ATIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define ATIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ -#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */ -#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */ -#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */ -#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */ - -/* Capture/compare mode register 1 -- Input capture mode */ - -/* Bits 1-0: - * (same as output compare mode) - */ - -#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define ATIM_CCMR1_IC1PSC_MASK (3 << ATIM_CCMR1_IC1PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11:10: Input Capture 2 Prescaler */ -#define ATIM_CCMR1_IC2PSC_MASK (3 << ATIM_CCMR1_IC2PSC_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) - /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define ATIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define ATIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define ATIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define ATIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define ATIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define ATIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define ATIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define ATIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define ATIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define ATIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define ATIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define ATIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define ATIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define ATIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define ATIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define ATIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define ATIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define ATIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define ATIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define ATIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode */ - -#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define ATIM_CCMR2_CC3S_MASK (3 << ATIM_CCMR2_CC3S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define ATIM_CCMR2_OC3M_MASK (7 << ATIM_CCMR2_OC3M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define ATIM_CCMR2_CC4S_MASK (3 << ATIM_CCMR2_CC4S_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define ATIM_CCMR2_OC4M_MASK (7 << ATIM_CCMR2_OC4M_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ -#endif - -/* Capture/compare mode register 2 - Input Capture Mode */ - -/* Bits 1-0: - * (same as output compare mode) - */ - -#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define ATIM_CCMR1_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - /* Bits 9:8 (same as output compare mode) */ -#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11:10: Input Capture 4 Prescaler */ -#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) - /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) - /* (See common (unshifted) bit field definitions above) */ - -/* Capture/compare mode register 3 -- Output compare mode */ - -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -# define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -# define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 6-4: Output Compare 5 Mode */ -# define ATIM_CCMR3_OC5M_MASK (7 << ATIM_CCMR3_OC5M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -# define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ -# define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -# define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -# define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 14-12: Output Compare 7 Mode */ -# define ATIM_CCMR3_OC6M_MASK (7 << ATIM_CCMR3_OC6M_SHIFT) - /* (See common (unshifted) bit field definitions below) */ -# define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ -# define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ -# define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ -#endif - -/* Capture/compare enable register */ - -#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output Polarity */ -#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary output enable */ -#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary output polarity */ -#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output Polarity */ -#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary output enable */ -#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary output polarity */ -#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity */ -#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */ -#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */ -#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */ -#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity - * NOTE: Some ST documents show CC4NP bit but there is - * no CC4N output, so it does not make sense! - */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ -# define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */ -# define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ -# define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */ -#endif -#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* 16-bit counter register */ - -#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ -#endif - -/* Repetition counter register */ - -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_RCR_REP_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ -# define ATIM_RCR_REP_MASK (0xffff << ATIM_RCR_REP_SHIFT) -# define ATIM_RCR_REP_MAX 32768 /* REVISIT */ -#else -# define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -# define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT) -# define ATIM_RCR_REP_MAX 128 -#endif - -/* Capture/compare registers (CCR) */ - -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ -# define ATIM_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ -# define ATIM_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ -#endif - -#define ATIM_CCR_MASK (0xffff) - -/* Break and dead-time register */ - -#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) -#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) -# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ -#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -# define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT) -# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -# define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -# define ATIM_BDTR_BK2F_MASK (15 << ATIM_BDTR_BK2F_SHIFT) -# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ -# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -# define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -# define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ -#endif - -/* DMA control register */ - -#define ATIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) -#define ATIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) -# define ATIM_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Control register 1 (TIM2-5 and TIM9-14) */ - -#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */ -#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction (TIM2-5 only) */ -#define GTIM_CR1_CMS_SHIFT (5) /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */ -#define GTIM_CR1_CMS_MASK (3 << GTIM_CR1_CMS_SHIFT) -# define GTIM_CR1_EDGE (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode. */ -# define GTIM_CR1_CENTER1 (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define GTIM_CR1_CENTER2 (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define GTIM_CR1_CENTER3 (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define GTIM_CR1_CKD_SHIFT (8) /* Bits 9-8: Clock Division */ -#define GTIM_CR1_CKD_MASK (3 << GTIM_CR1_CKD_SHIFT) -# define GTIM_CR1_TCKINT (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */ -# define GTIM_CR1_2TCKINT (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */ -# define GTIM_CR1_4TCKINT (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ -#endif - -/* Control register 2 (TIM2-5, TIM9-12, and TIM15-17 only) */ - -#define GTIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */ -#define GTIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/compare control update selection (TIM15-17 only) */ -#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */ -#define GTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection (not TIM16) */ -#define GTIM_CR2_MMS_MASK (7 << GTIM_CR2_MMS_SHIFT) -# define GTIM_CR2_MMS_RESET (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define GTIM_CR2_MMS_ENABLE (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define GTIM_CR2_MMS_UPDATE (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */ -# define GTIM_CR2_MMS_COMPP (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */ -# define GTIM_CR2_MMS_OC1REF (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC2REF (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */ -# define GTIM_CR2_MMS_OC3REF (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -# define GTIM_CR2_MMS_OC4REF (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */ -#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection (not TIM16) */ -#define GTIM_CR2_OIS1 (1 << 8) /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */ -#define GTIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */ -#define GTIM_CR2_OIS2 (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */ - -/* Slave mode control register (TIM2-5 and TIM15 only) */ - -#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 2-0: Slave Mode Selection */ -#define GTIM_SMCR_SMS_MASK (7 << GTIM_SMCR_SMS_SHIFT) -# define GTIM_SMCR_DISAB (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */ -# define GTIM_SMCR_ENCMD1 (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */ -# define GTIM_SMCR_ENCMD2 (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */ -# define GTIM_SMCR_ENCMD3 (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */ -# define GTIM_SMCR_RESET (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */ -# define GTIM_SMCR_GATED (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */ -# define GTIM_SMCR_TRIGGER (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */ -# define GTIM_SMCR_EXTCLK1 (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */ -#define GTIM_SMCR_TS_SHIFT (4) /* Bits 6-4: Trigger Selection */ -#define GTIM_SMCR_TS_MASK (7 << GTIM_SMCR_TS_SHIFT) -# define GTIM_SMCR_ITR0 (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */ -# define GTIM_SMCR_ITR1 (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */ -# define GTIM_SMCR_ITR2 (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */ -# define GTIM_SMCR_ITR3 (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */ -# define GTIM_SMCR_TI1FED (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */ -# define GTIM_SMCR_TI1FP1 (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */ -# define GTIM_SMCR_TI2FP2 (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */ -# define GTIM_SMCR_ETRF (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */ -#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/Slave mode */ -#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 11-8: External Trigger Filter (not TIM15) */ -#define GTIM_SMCR_ETF_MASK (0x0f << GTIM_SMCR_ETF_SHIFT) -# define GTIM_SMCR_NOFILT (0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define GTIM_SMCR_FCKINT2 (1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_SMCR_FCKINT4 (2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_SMCR_FCKINT8 (3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_SMCR_FDTSd26 (4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_SMCR_FDTSd28 (5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_SMCR_FDTSd36 (6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_SMCR_FDTSd38 (7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_SMCR_FDTSd86 (8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_SMCR_FDTSd88 (9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_SMCR_FDTSd165 (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_SMCR_FDTSd166 (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_SMCR_FDTSd168 (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_SMCR_FDTSd325 (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_SMCR_FDTSd326 (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_SMCR_FDTSd328 (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 13-12: External Trigger Prescaler (not TIM15) */ -#define GTIM_SMCR_ETPS_MASK (3 << GTIM_SMCR_ETPS_SHIFT) -# define GTIM_SMCR_PSCOFF (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define GTIM_SMCR_ETRPd2 (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define GTIM_SMCR_ETRPd4 (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define GTIM_SMCR_ETRPd8 (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External Clock enable */ -#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External Trigger Polarity */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ -#endif - -/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */ - -#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */ -#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */ -#define GTIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */ -#define GTIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable (TIM15-17 only) */ -#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */ -#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */ -#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */ -#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */ -#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */ - -/* Status register */ - -#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ -#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/compare 1 interrupt flag */ -#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */ -#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */ -#define GTIM_SR_COMIF (1 << 5) /* Bit 5: COM interrupt flag (TIM15-17 only) */ -#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */ -#define GTIM_SR_BIF (1 << 7) /* Bit 7: Break interrupt flag (TIM15-17 only) */ -#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture flag */ -#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */ -#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */ -#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */ - -/* Event generation register (TIM2-5 and TIM9-14) */ - -#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/compare 1 generation */ -#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */ -#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */ -#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */ -#define GTIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */ -#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */ -#define GTIM_EGR_BG (1 << 7) /* Bit 7: Break generation (TIM15-17 only) */ - -/* Capture/compare mode register 1 - Output compare mode - * (TIM2-5 and TIM9-14) - */ - -#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 1-0: Capture/Compare 1 Selection */ -#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 6-4: Output Compare 1 Mode */ -#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 9-8: Capture/Compare 2 Selection */ -#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions below) */ -#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 14-12: Output Compare 2 Mode */ -#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) - /* (See common CCMR Output Compare Mode definitions below) */ -#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -# define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ -#endif - -/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */ - -#define GTIM_CCMR_CCS_CCOUT (0) /* 00: CCx channel output */ -#define GTIM_CCMR_CCS_CCIN1 (1) /* 01: CCx channel input, ICx is TIx */ -#define GTIM_CCMR_CCS_CCIN2 (2) /* 10: CCx channel input, ICx is TIy */ -#define GTIM_CCMR_CCS_CCINTRC (3) /* 11: CCx channel input, ICx is TRC */ - -/* Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define GTIM_CCMR_MODE_FRZN (0) /* 000: Frozen */ -#define GTIM_CCMR_MODE_CHACT (1) /* 001: Channel x active on match */ -#define GTIM_CCMR_MODE_CHINACT (2) /* 010: Channel x inactive on match */ -#define GTIM_CCMR_MODE_OCREFTOG (3) /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define GTIM_CCMR_MODE_OCREFLO (4) /* 100: OCxREF forced low */ -#define GTIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */ -#define GTIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */ -#define GTIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */ - -/* Capture/compare mode register 1 - Input capture mode - * (TIM2-5 and TIM9-14) - */ - -/* Bits 1-0 - * (Same as Output Compare Mode) - */ -#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 3-2: Input Capture 1 Prescaler */ -#define GTIM_CCMR1_IC1PSC_MASK (3 << GTIM_CCMR1_IC1PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 7-4: Input Capture 1 Filter */ -#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 11-10: Input Capture 2 Prescaler */ -#define GTIM_CCMR1_IC2PSC_MASK (3 << GTIM_CCMR1_IC2PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 15-12: Input Capture 2 Filter */ -#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define GTIM_CCMR_ICPSC_NOPSC (0) /* 00: no prescaler, capture each edge */ -#define GTIM_CCMR_ICPSC_EVENTS2 (1) /* 01: capture once every 2 events */ -#define GTIM_CCMR_ICPSC_EVENTS4 (2) /* 10: capture once every 4 events */ -#define GTIM_CCMR_ICPSC_EVENTS8 (3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define GTIM_CCMR_ICF_NOFILT (0) /* 0000: No filter, sampling at fDTS */ -#define GTIM_CCMR_ICF_FCKINT2 (1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define GTIM_CCMR_ICF_FCKINT4 (2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define GTIM_CCMR_ICF_FCKINT8 (3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define GTIM_CCMR_ICF_FDTSd26 (4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define GTIM_CCMR_ICF_FDTSd28 (5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define GTIM_CCMR_ICF_FDTSd46 (6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define GTIM_CCMR_ICF_FDTSd48 (7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define GTIM_CCMR_ICF_FDTSd86 (8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define GTIM_CCMR_ICF_FDTSd88 (9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define GTIM_CCMR_ICF_FDTSd165 (10) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define GTIM_CCMR_ICF_FDTSd166 (11) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define GTIM_CCMR_ICF_FDTSd168 (12) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define GTIM_CCMR_ICF_FDTSd325 (13) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define GTIM_CCMR_ICF_FDTSd326 (14) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define GTIM_CCMR_ICF_FDTSd328 (15) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */ - -#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 1-0: Capture/Compare 3 Selection */ -#define GTIM_CCMR2_CC3S_MASK (3 << GTIM_CCMR2_CC3S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 6-4: Output Compare 3 Mode */ -#define GTIM_CCMR2_OC3M_MASK (7 << GTIM_CCMR2_OC3M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 9-8: Capture/Compare 4 Selection */ -#define GTIM_CCMR2_CC4S_MASK (3 << GTIM_CCMR2_CC4S_SHIFT) - /* (See common CCMR Capture/Compare Selection definitions above) */ -#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 14-12: Output Compare 4 Mode */ -#define GTIM_CCMR2_OC4M_MASK (7 << GTIM_CCMR2_OC4M_SHIFT) - /* (See common CCMR Output Compare Mode definitions above) */ -#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */ - -/* Bits 1-0 - * (Same as Output Compare Mode) - */ -#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 3-2: Input Capture 3 Prescaler */ -#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 7-4: Input Capture 3 Filter */ -#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - /* Bits 9-8: (Same as Output Compare Mode) */ -#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 11-10: Input Capture 4 Prescaler */ -#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) - /* (See common CCMR Input Capture Prescaler definitions below) */ -#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 15-12: Input Capture 4 Filter */ -#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) - /* (See common CCMR Input Capture Filter definitions below) */ - -/* Capture/compare enable register (TIM2-5 and TIM9-14) */ - -#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#ifdef HAVE_GTIM_CCXNP -# define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */ -#endif -#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */ -#define GTIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */ -#ifdef HAVE_GTIM_CCXNP -# define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */ -#endif -#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */ -#define GTIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */ -#ifdef HAVE_GTIM_CCXNP -# define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */ -#endif -#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */ -#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */ -#ifdef HAVE_GTIM_CCXNP -# define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity - * NOTE: Some ST documents show CC4NP bit but there is - * no CC4N output, so it does not make sense! - */ -#endif -#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* 16-bit counter register */ - -#define GTIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define GTIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#ifdef HAVE_IP_TIMERS_M3M4_V2 -# define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ -#endif - -/* DMA control register */ - -#define GTIM_DCR_DBA_SHIFT (0) /* Bits 4-0: DMA Base Address */ -#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) -#define GTIM_DCR_DBL_SHIFT (8) /* Bits 12-8: DMA Burst Length */ -#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) - -/* Timer 2/5 option register */ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define TIM2_OR_ITR1_RMP_SHIFT (10) /* Bits 10-11: Internal trigger 1 remap */ -# define TIM2_OR_ITR1_RMP_MASK (3 << TIM2_OR_ITR1_RMP_SHIFT) -# define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */ -# define TIM2_OR_ITR1_PTP (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */ -# define TIM2_OR_ITR1_OTGFSSOF (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */ -# define TIM2_OR_ITR1_OTGHSSOF (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */ - -# define TIM5_OR_TI4_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -# define TIM5_OR_TI4_RMP_MASK (3 << TIM5_OR_TI4_RMP_SHIFT) -# define TIM5_OR_TI4_GPIO (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */ -# define TIM5_OR_TI4_LSI (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */ -# define TIM5_OR_TI4_LSE (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */ -# define TIM5_OR_TI4_RTC (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */ - -# define TIM11_OR_TI1_RMP_SHIFT (6) /* Bits 6-7: Internal trigger 4 remap */ -# define TIM11_OR_TI1_RMP_MASK (3 << TIM11_OR_TI1_RMP_SHIFT) -# define TIM11_OR_TI1_GPIO (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */ -# define TIM11_OR_TI1_HSERTC (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */ -#endif - -/* Timer 16 Option Register */ - -#ifdef HAVE_TIM16_OR -# define TIM16_OR_RMP_SHIFT (0) /* Bits 0-1: Timer 16 input 1 connection */ -# define TIM16_OR_RMP_MASK (3 << TIM16_OR_RMP_SHIFT) -# define TIM16_OR_RMP_GPRIO (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to GPIO */ -# define TIM16_OR_RMP_RTC (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to RTC_clock */ -# define TIM16_OR_RMP_HSEd32 (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to HSE/32 */ -# define TIM16_OR_RMP_MCO (3 << TIM16_OR_RMP_SHIFT) /* TIM16 TI1 is connected to MCO */ -#endif - -/* Control register 1 */ - -#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ - -/* Control register 2 */ - -#define BTIM_CR2_MMS_SHIFT (4) /* Bits 6-4: Master Mode Selection */ -#define BTIM_CR2_MMS_MASK (7 << BTIM_CR2_MMS_SHIFT) -# define BTIM_CR2_RESET (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define BTIM_CR2_ENAB (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define BTIM_CR2_UPDT (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ - -/* DMA/Interrupt enable register */ - -#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ - -/* Status register */ - -#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update interrupt flag */ - -/* Event generation register */ - -#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/stm32/hardware/stm32_tim_v3.h deleted file mode 100644 index eb6e5421394e8..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ /dev/null @@ -1,1440 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v3.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* BTIM: Basic Timers - TIM6 and TIM7 */ - -#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (32-bit register, 16-bit counter) */ -#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit) */ - -/* GTIM: General Timers - * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 - * - * Caution! TIM2/5, TIM3/4, TIM15, and TIM16/17 are slightly different and - * have different registers, register sizes, and register bitfields! - * - * Some registers are marked with the following notes: - * - * Note 1: The register is 32-bit but its contents have different variants - * for TIM3/4 and TIM2/5, TIM15 - * Note 2: This register not available on TIM15 - * Note 3: This register not available on TIM16/17 - */ - -#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit TIM2-5; 16-bit TIM15-17) */ -#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit TIM2-5, TIM15, See Note 3) */ -#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (32-bit TIM2-5; 16-bit TIM15) */ -#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (32-bit TIM2-5; 16-bit TIM15-17) */ -#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit) */ -#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (32-bit, See Note 1) */ -#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit, See Note 1) */ -#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit, TIM15 only) */ -#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (32-bit, See Note 1) */ -#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (32-bit, See Notes 1, 3) */ -#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (32-bit, See Notes 1, 3) */ -#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (32-bit, See Notes 1, 3) */ -#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit, TIM15-17 only) */ -#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 (TIM16/17 only) */ -#define STM32_GTIM_DTR2_OFFSET 0x0054 /* Dead-time register 2 (32-bit, TIM15-17 only) */ -#define STM32_GTIM_ECR_OFFSET 0x0058 /* Encoder control register (32-bit, See Notes 2, 3) */ -#define STM32_GTIM_TISEL_OFFSET 0x005c /* Timer input selection register (32-bit) */ -#define STM32_GTIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ -#define STM32_GTIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ -#define STM32_GTIM_DCR_OFFSET 0x03dc /* DMA control register (16-bit, TIM2-5 only) */ -#define STM32_GTIM_DMAR_OFFSET 0x03e0 /* DMA address for burst mode (16-bit, TIM2-5 only) */ - -/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ - -#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (32-bit) */ -#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (32-bit) */ -#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (32-bit) */ -#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit) */ -#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (32-bit) */ -#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (32-bit register, 16-bit counter) */ -#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (32-bit) */ -#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (32-bit) */ -#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (32-bit) */ -#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (32-bit) */ -#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (32-bit) */ -#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (32-bit) */ -#define STM32_ATIM_CCR5_OFFSET 0x0048 /* Capture/compare register 5 (32-bit) */ -#define STM32_ATIM_CCR6_OFFSET 0x004c /* Capture/compare register 6 (32-bit) */ -#define STM32_ATIM_CCMR3_OFFSET 0x0050 /* Capture/compare mode register 3 (32-bit) */ -#define STM32_ATIM_DTR2_OFFSET 0x0054 /* Dead-time register 2 (32-bit) */ -#define STM32_ATIM_ECR_OFFSET 0x0058 /* Encoder control register (32-bit) */ -#define STM32_ATIM_TISEL_OFFSET 0x005c /* Timer input selection register (32-bit) */ -#define STM32_ATIM_AF1_OFFSET 0x0060 /* Alternate function option register 1 (32-bit) */ -#define STM32_ATIM_AF2_OFFSET 0x0064 /* Alternate function option register 2 (32-bit) */ -#define STM32_ATIM_DCR_OFFSET 0x03dc /* DMA control register (32-bit) */ -#define STM32_ATIM_DMAR_OFFSET 0x03e0 /* DMA address for full transfer (32-bit) */ - -/* Register Addresses *******************************************************/ - -/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ - -#if STM32_NATIM > 0 -# define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) -# define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) -# define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) -# define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) -# define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) -# define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) -# define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) -# define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) -# define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) -# define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) -# define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) -# define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM1_DTR2 (STM32_TIM1_BASE + STM32_ATIM_DTR2_OFFSET) -# define STM32_TIM1_ECR (STM32_TIM1_BASE + STM32_ATIM_ECR_OFFSET) -# define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_ATIM_TISEL_OFFSET) -# define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_ATIM_AF1_OFFSET) -# define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_ATIM_AF2_OFFSET) -# define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) -# define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) -#endif - -#if STM32_NATIM > 1 -# define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) -# define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) -# define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) -# define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) -# define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) -# define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) -# define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) -# define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) -# define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) -# define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) -# define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) -# define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM8_DTR2 (STM32_TIM8_BASE + STM32_ATIM_DTR2_OFFSET) -# define STM32_TIM8_ECR (STM32_TIM8_BASE + STM32_ATIM_ECR_OFFSET) -# define STM32_TIM8_TISEL (STM32_TIM8_BASE + STM32_ATIM_TISEL_OFFSET) -# define STM32_TIM8_AF1 (STM32_TIM8_BASE + STM32_ATIM_AF1_OFFSET) -# define STM32_TIM8_AF2 (STM32_TIM8_BASE + STM32_ATIM_AF2_OFFSET) -# define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) -# define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) -#endif - -#if STM32_NATIM > 2 -# define STM32_TIM20_CR1 (STM32_TIM20_BASE + STM32_ATIM_CR1_OFFSET) -# define STM32_TIM20_CR2 (STM32_TIM20_BASE + STM32_ATIM_CR2_OFFSET) -# define STM32_TIM20_SMCR (STM32_TIM20_BASE + STM32_ATIM_SMCR_OFFSET) -# define STM32_TIM20_DIER (STM32_TIM20_BASE + STM32_ATIM_DIER_OFFSET) -# define STM32_TIM20_SR (STM32_TIM20_BASE + STM32_ATIM_SR_OFFSET) -# define STM32_TIM20_EGR (STM32_TIM20_BASE + STM32_ATIM_EGR_OFFSET) -# define STM32_TIM20_CCMR1 (STM32_TIM20_BASE + STM32_ATIM_CCMR1_OFFSET) -# define STM32_TIM20_CCMR2 (STM32_TIM20_BASE + STM32_ATIM_CCMR2_OFFSET) -# define STM32_TIM20_CCER (STM32_TIM20_BASE + STM32_ATIM_CCER_OFFSET) -# define STM32_TIM20_CNT (STM32_TIM20_BASE + STM32_ATIM_CNT_OFFSET) -# define STM32_TIM20_PSC (STM32_TIM20_BASE + STM32_ATIM_PSC_OFFSET) -# define STM32_TIM20_ARR (STM32_TIM20_BASE + STM32_ATIM_ARR_OFFSET) -# define STM32_TIM20_RCR (STM32_TIM20_BASE + STM32_ATIM_RCR_OFFSET) -# define STM32_TIM20_CCR1 (STM32_TIM20_BASE + STM32_ATIM_CCR1_OFFSET) -# define STM32_TIM20_CCR2 (STM32_TIM20_BASE + STM32_ATIM_CCR2_OFFSET) -# define STM32_TIM20_CCR3 (STM32_TIM20_BASE + STM32_ATIM_CCR3_OFFSET) -# define STM32_TIM20_CCR4 (STM32_TIM20_BASE + STM32_ATIM_CCR4_OFFSET) -# define STM32_TIM20_BDTR (STM32_TIM20_BASE + STM32_ATIM_BDTR_OFFSET) -# define STM32_TIM20_CCR5 (STM32_TIM20_BASE + STM32_ATIM_CCR5_OFFSET) -# define STM32_TIM20_CCR6 (STM32_TIM20_BASE + STM32_ATIM_CCR6_OFFSET) -# define STM32_TIM20_CCMR3 (STM32_TIM20_BASE + STM32_ATIM_CCMR3_OFFSET) -# define STM32_TIM20_DTR2 (STM32_TIM20_BASE + STM32_ATIM_DTR2_OFFSET) -# define STM32_TIM20_ECR (STM32_TIM20_BASE + STM32_ATIM_ECR_OFFSET) -# define STM32_TIM20_TISEL (STM32_TIM20_BASE + STM32_ATIM_TISEL_OFFSET) -# define STM32_TIM20_AF1 (STM32_TIM20_BASE + STM32_ATIM_AF1_OFFSET) -# define STM32_TIM20_AF2 (STM32_TIM20_BASE + STM32_ATIM_AF2_OFFSET) -# define STM32_TIM20_DCR (STM32_TIM20_BASE + STM32_ATIM_DCR_OFFSET) -# define STM32_TIM20_DMAR (STM32_TIM20_BASE + STM32_ATIM_DMAR_OFFSET) -#endif - -/* GTIM: General Timers - * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 - */ - -#if STM32_NGTIM > 0 -# define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM2_ECR (STM32_TIM2_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM2_AF2 (STM32_TIM2_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 1 -# define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM3_ECR (STM32_TIM3_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM3_TISEL (STM32_TIM3_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM3_AF1 (STM32_TIM3_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM3_AF2 (STM32_TIM3_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 2 -# define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM4_ECR (STM32_TIM4_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM4_TISEL (STM32_TIM4_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM4_AF1 (STM32_TIM4_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM4_AF2 (STM32_TIM4_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 3 -# define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM5_ECR (STM32_TIM5_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM5_TISEL (STM32_TIM5_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM5_AF1 (STM32_TIM5_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM5_AF2 (STM32_TIM5_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 4 -# define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM15_CCMR2 (STM32_TIM15_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM15_CCR3 (STM32_TIM15_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM15_CCR4 (STM32_TIM15_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM15_ECR (STM32_TIM15_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM15_TISEL (STM32_TIM15_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM15_AF1 (STM32_TIM15_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM15_AF2 (STM32_TIM15_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 5 -# define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM16_SMCR (STM32_TIM16_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM16_CCMR2 (STM32_TIM16_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM16_CCR2 (STM32_TIM16_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM16_CCR3 (STM32_TIM16_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM16_CCR4 (STM32_TIM16_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM16_ECR (STM32_TIM16_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM16_AF2 (STM32_TIM16_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -#if STM32_NGTIM > 6 -# define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) -# define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) -# define STM32_TIM17_SMCR (STM32_TIM17_BASE + STM32_GTIM_SMCR_OFFSET) -# define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) -# define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) -# define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) -# define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) -# define STM32_TIM17_CCMR2 (STM32_TIM17_BASE + STM32_GTIM_CCMR2_OFFSET) -# define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) -# define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) -# define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) -# define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) -# define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) -# define STM32_TIM17_CCR2 (STM32_TIM17_BASE + STM32_GTIM_CCR2_OFFSET) -# define STM32_TIM17_CCR3 (STM32_TIM17_BASE + STM32_GTIM_CCR3_OFFSET) -# define STM32_TIM17_CCR4 (STM32_TIM17_BASE + STM32_GTIM_CCR4_OFFSET) -# define STM32_TIM17_ECR (STM32_TIM17_BASE + STM32_GTIM_ECR_OFFSET) -# define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_GTIM_TISEL_OFFSET) -# define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_GTIM_AF1_OFFSET) -# define STM32_TIM17_AF2 (STM32_TIM17_BASE + STM32_GTIM_AF2_OFFSET) -# define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) -# define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) -#endif - -/* BTIM: Basic Timers - TIM6 and TIM7 */ - -#if STM32_NBTIM > 0 -# define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) -# define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) -# define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) -# define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) -# define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) -# define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) -# define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) -# define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) -#endif - -#if STM32_NBTIM > 1 -# define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) -# define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) -# define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) -# define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) -# define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) -# define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) -# define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) -# define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) -#endif - -/* Register Bitfield Definitions - ATIM *************************************/ - -/* ATIM: Advanced Timers - TIM1, TIM8, and TIM20 */ - -/* ATIM Control register 1 (CR1) */ - -#define ATIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define ATIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define ATIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define ATIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define ATIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define ATIM_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define ATIM_CR1_CMS_MASK (0x3 << ATIM_CR1_CMS_SHIFT) -# define ATIM_CR1_EDGE (0x0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define ATIM_CR1_CENTER1 (0x1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define ATIM_CR1_CENTER2 (0x2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define ATIM_CR1_CENTER3 (0x3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define ATIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define ATIM_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define ATIM_CR1_CKD_MASK (0x3 << ATIM_CR1_CKD_SHIFT) -# define ATIM_CR1_TCKINT (0x0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=1*tCK_INT */ -# define ATIM_CR1_2TCKINT (0x1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define ATIM_CR1_4TCKINT (0x2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ -#define ATIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ -#define ATIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering enable */ - -/* ATIM Control register 2 (CR2) */ - -#define ATIM_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare Preloaded Control */ -#define ATIM_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare Control Update Selection */ -#define ATIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define ATIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ -#define ATIM_CR2_MMS_MASK (0x200007 << ATIM_CR2_MMS_SHIFT) -# define ATIM_CR2_MMS_RESET (0x0 << ATIM_CR2_MMS_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRGO */ -# define ATIM_CR2_MMS_ENABLE (0x1 << ATIM_CR2_MMS_SHIFT) /* 0001: Enable - CNT_EN is TRGO */ -# define ATIM_CR2_MMS_UPDATE (0x2 << ATIM_CR2_MMS_SHIFT) /* 0010: Update event is TRGO */ -# define ATIM_CR2_MMS_COMPP (0x3 << ATIM_CR2_MMS_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS_OC1REF (0x4 << ATIM_CR2_MMS_SHIFT) /* 0100: Compare OC1REF is TRGO */ -# define ATIM_CR2_MMS_OC2REF (0x5 << ATIM_CR2_MMS_SHIFT) /* 0101: Compare OC2REF is TRGO */ -# define ATIM_CR2_MMS_OC3REF (0x6 << ATIM_CR2_MMS_SHIFT) /* 0110: Compare OC3REF is TRGO */ -# define ATIM_CR2_MMS_OC4REF (0x7 << ATIM_CR2_MMS_SHIFT) /* 0111: Compare OC4REF is TRGO */ -# define ATIM_CR2_MMS_ENCODER (0x200000 << ATIM_CR2_MMS_SHIFT) /* 1000: Encoder clock is TRGO */ -#define ATIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -#define ATIM_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define ATIM_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define ATIM_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define ATIM_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define ATIM_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define ATIM_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define ATIM_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define ATIM_CR2_OIS4N (1 << 15) /* Bit 15: Output Idle state 4 (OC4N output) */ -#define ATIM_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ -#define ATIM_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -#define ATIM_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -#define ATIM_CR2_MMS2_MASK (0xf << ATIM_CR2_MMS2_SHIFT) -# define ATIM_CR2_MMS2_RESET (0x0 << ATIM_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define ATIM_CR2_MMS2_ENABLE (0x1 << ATIM_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define ATIM_CR2_MMS2_UPDATE (0x2 << ATIM_CR2_MMS2_SHIFT) /* 0010: Update event is TRGH0 */ -# define ATIM_CR2_MMS2_COMPP (0x3 << ATIM_CR2_MMS2_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define ATIM_CR2_MMS2_OC1REF (0x4 << ATIM_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC2REF (0x5 << ATIM_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC3REF (0x6 << ATIM_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC4REF (0x7 << ATIM_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC5REF (0x8 << ATIM_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define ATIM_CR2_MMS2_OC6REF (0x9 << ATIM_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4 (0xa << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC6 (0xb << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define ATIM_CR2_MMS2_CMPOC4R6R (0xc << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC4R6F (0xd << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define ATIM_CR2_MMS2_CMPOC5R6R (0xe << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define ATIM_CR2_MMS2_CMPOC5R6F (0xf << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ - -/* ATIM Slave mode control register (SMCR) */ - -#define ATIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define ATIM_SMCR_SMS_MASK (0x10007 << ATIM_SMCR_SMS_SHIFT) -# define ATIM_SMCR_DISAB (0x0 << ATIM_SMCR_SMS_SHIFT) /* 0000: Slave mode disabled */ -# define ATIM_SMCR_ENCMD1 (0x1 << ATIM_SMCR_SMS_SHIFT) /* 0001: Encoder mode 1 */ -# define ATIM_SMCR_ENCMD2 (0x2 << ATIM_SMCR_SMS_SHIFT) /* 0010: Encoder mode 2 */ -# define ATIM_SMCR_ENCMD3 (0x3 << ATIM_SMCR_SMS_SHIFT) /* 0011: Encoder mode 3 */ -# define ATIM_SMCR_RESET (0x4 << ATIM_SMCR_SMS_SHIFT) /* 0100: Reset Mode */ -# define ATIM_SMCR_GATED (0x5 << ATIM_SMCR_SMS_SHIFT) /* 0101: Gated Mode */ -# define ATIM_SMCR_TRIGGER (0x6 << ATIM_SMCR_SMS_SHIFT) /* 0110: Trigger Mode */ -# define ATIM_SMCR_EXTCLK1 (0x7 << ATIM_SMCR_SMS_SHIFT) /* 0111: External Clock Mode 1 */ -# define ATIM_SMCR_RESET_TRIGGER (0x10000 << ATIM_SMCR_SMS_SHIFT) /* 1000: Combined reset + trigger */ -# define ATIM_SMCR_GATED_RESET (0x10001 << ATIM_SMCR_SMS_SHIFT) /* 1001: Combined gated + reset */ -# define ATIM_SMCR_ENCMD4 (0x10002 << ATIM_SMCR_SMS_SHIFT) /* 1010: Encoder mode 4 */ -# define ATIM_SMCR_ENCMD5 (0x10003 << ATIM_SMCR_SMS_SHIFT) /* 1011: Encoder mode 5 */ -# define ATIM_SMCR_ENCMD6 (0x10004 << ATIM_SMCR_SMS_SHIFT) /* 1100: Encoder mode 6 */ -# define ATIM_SMCR_ENCMD7 (0x10005 << ATIM_SMCR_SMS_SHIFT) /* 1101: Encoder mode 7 */ -# define ATIM_SMCR_ENCMD8 (0x10006 << ATIM_SMCR_SMS_SHIFT) /* 1110: Encoder mode 8 */ -# define ATIM_SMCR_ENCMD9 (0x10007 << ATIM_SMCR_SMS_SHIFT) /* 1111: Encoder mode 9 */ -#define ATIM_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -#define ATIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define ATIM_SMCR_TS_MASK (0x30007 << ATIM_SMCR_TS_SHIFT) -# define ATIM_SMCR_ITR0 (0x0 << ATIM_SMCR_TS_SHIFT) /* 00 000: Internal trigger 0 (ITR0) */ -# define ATIM_SMCR_ITR1 (0x1 << ATIM_SMCR_TS_SHIFT) /* 00 001: Internal trigger 1 (ITR1) */ -# define ATIM_SMCR_ITR2 (0x2 << ATIM_SMCR_TS_SHIFT) /* 00 010: Internal trigger 2 (ITR2) */ -# define ATIM_SMCR_ITR3 (0x3 << ATIM_SMCR_TS_SHIFT) /* 00 011: Internal trigger 3 (ITR3) */ -# define ATIM_SMCR_TI1FED (0x4 << ATIM_SMCR_TS_SHIFT) /* 00 100: TI1 Edge Detector (TI1F_ED) */ -# define ATIM_SMCR_TI1FP1 (0x5 << ATIM_SMCR_TS_SHIFT) /* 00 101: Filtered Timer Input 1 (TI1FP1) */ -# define ATIM_SMCR_TI2FP2 (0x6 << ATIM_SMCR_TS_SHIFT) /* 00 110: Filtered Timer Input 2 (TI2FP2) */ -# define ATIM_SMCR_ETRF (0x7 << ATIM_SMCR_TS_SHIFT) /* 00 111: External Trigger Input (ETRF) */ -# define ATIM_SMCR_ITR4 (0x1000 << ATIM_SMCR_TS_SHIFT) /* 01 000: Internal Trigger 0 ITR4 */ -# define ATIM_SMCR_ITR5 (0x1001 << ATIM_SMCR_TS_SHIFT) /* 01 001: Internal Trigger 1 ITR5 */ -# define ATIM_SMCR_ITR6 (0x1002 << ATIM_SMCR_TS_SHIFT) /* 01 010: Internal Trigger 1 ITR6 */ -# define ATIM_SMCR_ITR7 (0x1003 << ATIM_SMCR_TS_SHIFT) /* 01 011: Internal Trigger 1 ITR7 */ -# define ATIM_SMCR_ITR8 (0x1004 << ATIM_SMCR_TS_SHIFT) /* 01 100: Internal Trigger 1 ITR8 */ -# define ATIM_SMCR_ITR9 (0x1005 << ATIM_SMCR_TS_SHIFT) /* 01 101: Internal Trigger 1 ITR9 */ -# define ATIM_SMCR_ITR10 (0x1006 << ATIM_SMCR_TS_SHIFT) /* 01 110: Internal Trigger 1 ITR10 */ -#define ATIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define ATIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define ATIM_SMCR_ETF_MASK (0xf << ATIM_SMCR_ETF_SHIFT) -# define ATIM_SMCR_NOFILT (0x0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define ATIM_SMCR_FCKINT2 (0x1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_SMCR_FCKINT4 (0x2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_SMCR_FCKINT8 (0x3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_SMCR_FDTSd26 (0x4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_SMCR_FDTSd28 (0x5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_SMCR_FDTSd46 (0x6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_SMCR_FDTSd48 (0x7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_SMCR_FDTSd86 (0x8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_SMCR_FDTSd88 (0x9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_SMCR_FDTSd165 (0xa << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_SMCR_FDTSd166 (0xb << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_SMCR_FDTSd168 (0xc << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_SMCR_FDTSd325 (0xd << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_SMCR_FDTSd326 (0xe << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_SMCR_FDTSd328 (0xf << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define ATIM_SMCR_ETPS_MASK (0x3 << ATIM_SMCR_ETPS_SHIFT) -# define ATIM_SMCR_PSCOFF (0x0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define ATIM_SMCR_ETRPd2 (0x1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define ATIM_SMCR_ETRPd4 (0x2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define ATIM_SMCR_ETRPd8 (0x3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define ATIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define ATIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#define ATIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ -#define ATIM_SMCR_SMSPE (1 << 24) /* Bit 24: SMS preload enable */ -#define ATIM_SMCR_SMSPS (1 << 25) /* Bit 25: SMS preload source */ - -/* ATIM DMA/Interrupt enable register (DIER) */ - -#define ATIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define ATIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define ATIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define ATIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define ATIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define ATIM_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define ATIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define ATIM_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define ATIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define ATIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define ATIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define ATIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define ATIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define ATIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define ATIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ -#define ATIM_DIER_IDXIE (1 << 20) /* Bit 20: Index interrupt enable */ -#define ATIM_DIER_DIRIE (1 << 21) /* Bit 21: Direction change interrupt enable */ -#define ATIM_DIER_IERRIE (1 << 22) /* Bit 22: Index error interrupt enable */ -#define ATIM_DIER_TERRIE (1 << 23) /* Bit 23: Transition error interrupt enable */ - -/* ATIM Status register (SR) */ - -#define ATIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ -#define ATIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 Interrupt Flag */ -#define ATIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 Interrupt Flag */ -#define ATIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 Interrupt Flag */ -#define ATIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 Interrupt Flag */ -#define ATIM_SR_COMIF (1 << 5) /* Bit 5: Com Interrupt Flag */ -#define ATIM_SR_TIF (1 << 6) /* Bit 6: Trigger Interrupt Flag */ -#define ATIM_SR_BIF (1 << 7) /* Bit 7: Break Interrupt Flag */ -#define ATIM_SR_B2IF (1 << 8) /* Bit 8: Break 2 Interrupt Flag */ -#define ATIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define ATIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define ATIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define ATIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define ATIM_SR_SBIF (1 << 13) /* Bit 13: System Break Interrupt Flag */ -#define ATIM_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 Interrupt Flag */ -#define ATIM_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 Interrupt Flag */ -#define ATIM_SR_IDXF (1 << 20) /* Bit 20: Index Interrupt Flag */ -#define ATIM_SR_DIRF (1 << 21) /* Bit 21: Direction Change Interrupt Flag */ -#define ATIM_SR_IERRF (1 << 22) /* Bit 22: Index Error Interrupt Flag */ -#define ATIM_SR_TERRF (1 << 23) /* Bit 23: Transition Error Interrupt Flag */ - -/* ATIM Event generation register (EGR) */ - -#define ATIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define ATIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define ATIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define ATIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define ATIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define ATIM_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define ATIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define ATIM_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#define ATIM_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ - -/* ATIM Capture/compare mode register 1 (CCMR1) - Output Compare Mode */ - -#define ATIM_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define ATIM_CCMR1_CC1S_MASK (3 << ATIM_CCMR1_CC1S_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define ATIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define ATIM_CCMR1_OC1M_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode */ -#define ATIM_CCMR1_OC1M_MASK (7 << ATIM_CCMR1_OC1M_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define ATIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define ATIM_CCMR1_CC2S_MASK (3 << ATIM_CCMR1_CC2S_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define ATIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define ATIM_CCMR1_OC2M_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode */ -#define ATIM_CCMR1_OC2M_MASK (7 << ATIM_CCMR1_OC2M_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - -/* ATIM Common CCMR (unshifted) Capture/Compare Selection - * bit-field definitions - */ - -#define ATIM_CCMR_CCS_CCOUT (0x0) /* 00: CCx channel output */ -#define ATIM_CCMR_CCS_CCIN1 (0x1) /* 01: CCx channel input, ICx is TIx */ -#define ATIM_CCMR_CCS_CCIN2 (0x2) /* 10: CCx channel input, ICx is TIy */ -#define ATIM_CCMR_CCS_CCINTRC (0x3) /* 11: CCx channel input, ICx is TRC */ - -/* ATIM Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define ATIM_CCMR_MODE_FRZN (0x0) /* 0000: Frozen */ -#define ATIM_CCMR_MODE_CHACT (0x1) /* 0001: Channel x active on match */ -#define ATIM_CCMR_MODE_CHINACT (0x2) /* 0010: Channel x inactive on match */ -#define ATIM_CCMR_MODE_OCREFTOG (0x3) /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */ -#define ATIM_CCMR_MODE_OCREFLO (0x4) /* 0100: OCxREF forced low */ -#define ATIM_CCMR_MODE_OCREFHI (0x5) /* 0101: OCxREF forced high */ -#define ATIM_CCMR_MODE_PWM1 (0x6) /* 0110: PWM mode 1 */ -#define ATIM_CCMR_MODE_PWM2 (0x7) /* 0111: PWM mode 2 */ -#define ATIM_CCMR_MODE_OPM1 (0x8) /* 1000: Retriggerable OPM mode 1 */ -#define ATIM_CCMR_MODE_OPM2 (0x9) /* 1001: Retriggerable OPM mode 2 */ -#define ATIM_CCMR_MODE_COMBINED1 (0xc) /* 1100: Combined PWM mode 1 */ -#define ATIM_CCMR_MODE_COMBINED2 (0xd) /* 1101: Combined PWM mode 2 */ -#define ATIM_CCMR_MODE_ASYMMETRIC1 (0xe) /* 1110: Asymmetric PWM mode 1 */ -#define ATIM_CCMR_MODE_ASYMMETRIC2 (0xf) /* 1111: Asymmetric PWM mode 2 */ - -/* ATIM Capture/compare mode register 1 (CCMR1) - Input Capture Mode - * Bits 0-1 and Bits 8-9 are same as Output Compare Mode - */ - -#define ATIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define ATIM_CCMR1_IC1PSC_MASK (0x3 << ATIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define ATIM_CCMR1_IC1F_MASK (0x0f << ATIM_CCMR1_IC1F_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define ATIM_CCMR1_IC2PSC_MASK (0x3 << ATIM_CCMR1_IC2PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define ATIM_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define ATIM_CCMR1_IC2F_MASK (0x0f << ATIM_CCMR1_IC2F_SHIFT) /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define ATIM_CCMR_ICPSC_NOPSC (0x0) /* 00: no prescaler, capture each edge */ -#define ATIM_CCMR_ICPSC_EVENTS2 (0x1) /* 01: capture once every 2 events */ -#define ATIM_CCMR_ICPSC_EVENTS4 (0x2) /* 10: capture once every 4 events */ -#define ATIM_CCMR_ICPSC_EVENTS8 (0x3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define ATIM_CCMR_ICF_NOFILT (0x0) /* 0000: No filter, sampling at fDTS */ -#define ATIM_CCMR_ICF_FCKINT2 (0x1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define ATIM_CCMR_ICF_FCKINT4 (0x2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define ATIM_CCMR_ICF_FCKINT8 (0x3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define ATIM_CCMR_ICF_FDTSd26 (0x4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define ATIM_CCMR_ICF_FDTSd28 (0x5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define ATIM_CCMR_ICF_FDTSd46 (0x6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define ATIM_CCMR_ICF_FDTSd48 (0x7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define ATIM_CCMR_ICF_FDTSd86 (0x8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define ATIM_CCMR_ICF_FDTSd88 (0x9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define ATIM_CCMR_ICF_FDTSd165 (0xa) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define ATIM_CCMR_ICF_FDTSd166 (0xb) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define ATIM_CCMR_ICF_FDTSd168 (0xc) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define ATIM_CCMR_ICF_FDTSd325 (0xd) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define ATIM_CCMR_ICF_FDTSd326 (0xe) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define ATIM_CCMR_ICF_FDTSd328 (0xf) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* ATIM Capture/compare mode register 2 (CCMR2) - Output Compare Mode */ - -#define ATIM_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define ATIM_CCMR2_CC3S_MASK (0x3 << ATIM_CCMR2_CC3S_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define ATIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define ATIM_CCMR2_OC3M_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode */ -#define ATIM_CCMR2_OC3M_MASK (0x7 << ATIM_CCMR2_OC3M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define ATIM_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define ATIM_CCMR2_CC4S_MASK (0x3 << ATIM_CCMR2_CC4S_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define ATIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define ATIM_CCMR2_OC4M_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode */ -#define ATIM_CCMR2_OC4M_MASK (0x7 << ATIM_CCMR2_OC4M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -#define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ - -/* ATIM Capture/compare mode register 2 (CCMR2) - Input Capture Mode - * Bits 0-1 and Bits 8-9 are same as Output Compare Mode - */ - -#define ATIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define ATIM_CCMR2_IC3PSC_MASK (3 << ATIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define ATIM_CCMR2_IC3F_MASK (0x0f << ATIM_CCMR2_IC3F_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define ATIM_CCMR2_IC4PSC_MASK (3 << ATIM_CCMR2_IC4PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define ATIM_CCMR2_IC4F_MASK (0x0f << ATIM_CCMR2_IC4F_SHIFT) /* (See common (unshifted) bit field definitions above) */ - -/* ATIM Capture/compare mode register 3 (CCMR3) */ - -#define ATIM_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define ATIM_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define ATIM_CCMR3_OC5M_SHIFT (4) /* Bits 4-6: Output Compare 5 Mode */ -#define ATIM_CCMR3_OC5M_MASK (0x7 << ATIM_CCMR3_OC5M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ -#define ATIM_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -#define ATIM_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -#define ATIM_CCMR3_OC6M_SHIFT (12) /* Bits 12-14: Output Compare 7 Mode */ -#define ATIM_CCMR3_OC6M_MASK (0x7 << ATIM_CCMR3_OC6M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define ATIM_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */ -#define ATIM_CCMR3_OC5M (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */ -#define ATIM_CCMR3_OC6M (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */ - -/* ATIM Capture/compare enable register (CCER) */ - -#define ATIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 Output Enable */ -#define ATIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 Output Polarity */ -#define ATIM_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 Complementary Output Enable */ -#define ATIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary Output Polarity */ -#define ATIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 Output Enable */ -#define ATIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 Output Polarity */ -#define ATIM_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 Complementary Output Enable */ -#define ATIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary Output Polarity */ -#define ATIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 Output Enable */ -#define ATIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 Output Polarity */ -#define ATIM_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 Complementary Output Enable */ -#define ATIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary Output Polarity */ -#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ -#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ -#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ -#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 Output Enable */ -#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 Output Polarity */ -#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 Output Enable */ -#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 Output Polarity */ -#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* ATIM Counter (CNT) */ - -#define ATIM_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define ATIM_CNT_MASK (0xffff << ATIM_CNT_SHIFT) -#define ATIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -/* ATIM Prescaler (PSC) */ - -#define ATIM_PSC_SHIFT (0) -#define ATIM_PSC_MASK (0xffff << ATIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ - -/* ATIM Auto-reload register (ARR) */ - -#define ATIM_ARR_SHIFT (0) -#define ATIM_ARR_MASK (0xffffffff << ATIM_ARR_SHIFT) /* Bits 0-31: Auto reload register */ - -/* ATIM Repetition counter register (RCR) */ - -#define ATIM_RCR_SHIFT (0) -#define ATIM_RCR_MASK (0xffff << ATIM_RCR_SHIFT) /* Bits 0-15: Repetition counter register */ - -/* ATIM Capture/compare register 1 (CCR1 - CCR6) */ - -#define ATIM_CCR_SHIFT (0) -#define ATIM_CCR_MASK (0xfffff << ATIM_CCR_SHIFT) /* Bits 0-19: Capture/compare 1 value */ -#define ATIM_CCR5_GC5C1 (1 << 29) /* CCR5 only, Bit 29: Group Channel 5 and Channel 1 */ -#define ATIM_CCR5_GC5C2 (1 << 30) /* CCR5 only, Bit 30: Group Channel 5 and Channel 2 */ -#define ATIM_CCR5_GC5C3 (1 << 31) /* CCR5 only, Bit 31: Group Channel 5 and Channel 3 */ - -/* ATIM Break and dead-time register (BDTR) */ - -#define ATIM_BDTR_DTG_SHIFT (0) /* Bits 0-7: Dead-Time Generator set-up */ -#define ATIM_BDTR_DTG_MASK (0xff << ATIM_BDTR_DTG_SHIFT) -#define ATIM_BDTR_LOCK_SHIFT (8) /* Bits 8-9: Lock Configuration */ -#define ATIM_BDTR_LOCK_MASK (3 << ATIM_BDTR_LOCK_SHIFT) -# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ -#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define ATIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define ATIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define ATIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ - -#define ATIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define ATIM_BDTR_BKF_MASK (15 << ATIM_BDTR_BKF_SHIFT) -# define ATIM_BDTR_BKF_NOFILT (0 << ATIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define ATIM_BDTR_BKF_FCKINT2 (1 << ATIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BKF_FCKINT4 (2 << ATIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BKF_FCKINT8 (3 << ATIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BKF_FDTSd26 (4 << ATIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BKF_FDTSd28 (5 << ATIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BKF_FDTSd36 (6 << ATIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BKF_FDTSd38 (7 << ATIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BKF_FDTSd86 (8 << ATIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BKF_FDTSd88 (9 << ATIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BKF_FDTSd165 (10 << ATIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BKF_FDTSd166 (11 << ATIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BKF_FDTSd168 (12 << ATIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BKF_FDTSd325 (13 << ATIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BKF_FDTSd326 (14 << ATIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BKF_FDTSd328 (15 << ATIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -#define ATIM_BDTR_BK2F_MASK (15 << ATIM_BDTR_BK2F_SHIFT) -# define ATIM_BDTR_BK2F_NOFILT (0 << ATIM_BDTR_BK2F_SHIFT) /* 0000: No filter, BRK 2 acts asynchronously */ -# define ATIM_BDTR_BK2F_FCKINT2 (1 << ATIM_BDTR_BK2F_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define ATIM_BDTR_BK2F_FCKINT4 (2 << ATIM_BDTR_BK2F_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define ATIM_BDTR_BK2F_FCKINT8 (3 << ATIM_BDTR_BK2F_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd26 (4 << ATIM_BDTR_BK2F_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd28 (5 << ATIM_BDTR_BK2F_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd36 (6 << ATIM_BDTR_BK2F_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd38 (7 << ATIM_BDTR_BK2F_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd86 (8 << ATIM_BDTR_BK2F_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd88 (9 << ATIM_BDTR_BK2F_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ -#define ATIM_BDTR_BK_DSRM (1 << 26) /* Bit 26: Break disarm */ -#define ATIM_BDTR_BK2_DSRM (1 << 27) /* Bit 27: Break 2 disarm */ -#define ATIM_BDTR_BK_BID (1 << 28) /* Bit 28: Break bidirectional */ -#define ATIM_BDTR_BK2_BID (1 << 29) /* Bit 29: Break 2 bidirectional */ - -/* ATIM Dead-time register 2 (DTR2) */ - -#define ATIM_DTR2_DTGF_SHIFT (0) /* Dead time falling edge generator setup */ -#define ATIM_DTR2_DTGF_MASK (0xff << ATIM_DTR2_DTGF_SHIFT) -#define ATIM_DTR2_DTAE (1 << 16) /* Dead time asymmetric enable */ -#define ATIM_DTR2_DTPE (1 << 17) /* Dead time preload enable */ - -/* ATIM Encoder control register (ECR) */ - -#define ATIM_ECR_IE (1 << 0) /* Index enable (indicates if index resets counter): 0=no, 1=yes */ -#define ATIM_ECR_IDIR_SHIFT (1) /* Index direction */ -#define ATIM_ECR_IDIR_MASK (0x3 << ATIM_ECR_IDIR_SHIFT) -# define ATIM_ECR_IDIR_BOTH (0x0 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter in both directions */ -# define ATIM_ECR_IDIR_UP (0x1 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting up */ -# define ATIM_ECR_IDIR_DOWN (0x2 << ATIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting down */ -#define ATIM_ECR_FIDX (1 << 5) /* First index: 0=index always resets counter, 1=only first index resets counter */ -#define ATIM_ECR_IPOS_SHIFT (6) /* Index reset position */ -#define ATIM_ECR_IPOS_MASK (0x3 << ATIM_ECR_IPOS_SHIFT) -# define ATIM_ECR_IPOS_00 (0x0 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,0 */ -# define ATIM_ECR_IPOS_01 (0x1 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,1 */ -# define ATIM_ECR_IPOS_10 (0x2 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,0 */ -# define ATIM_ECR_IPOS_11 (0x3 << ATIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,1 */ -#define ATIM_ECR_PW_SHIFT (16) /* Pulse duration in units of t[PWG], see ATIM_ECR_PWPRSC_MASK */ -#define ATIM_ECR_PW_MASK (0xff << ATIM_ECR_PW_SHIFT) -#define ATIM_ECR_PWPRSC_SHIFT (24) /* Pulse width prescaler */ -#define ATIM_ECR_PWPRSC_MASK (0x7 << ATIM_ECR_PWPRSC_SHIFT) /* t[PWG] = (2^(PWPRSC[2:0])) * t[tim_ker_ck] */ - -/* ATIM Timer input selection register (TISEL) */ - -#define ATIM_TISEL_TI1SEL_SHIFT (0) -#define ATIM_TISEL_TI1SEL_MASK (0xf << TIM_TISEL_TI1SEL_SHIFT) - -#define ATIM_TISEL_TI2SEL_SHIFT (8) -#define ATIM_TISEL_TI2SEL_MASK (0xf << TIM_TISEL_TI2SEL_SHIFT) - -#define ATIM_TISEL_TI3SEL_SHIFT (16) -#define ATIM_TISEL_TI3SEL_MASK (0xf << TIM_TISEL_TI3SEL_SHIFT) - -#define ATIM_TISEL_TI4SEL_SHIFT (24) -#define ATIM_TISEL_TI4SEL_MASK (0xf << TIM_TISEL_TI4SEL_SHIFT) - -/* ATIM Alternate function option register 1 (AF1) */ - -#define ATIM_AF1_BKINE (1 << 0) /* BRK BKIN input enable */ -#define ATIM_AF1_BKCMP1E (1 << 1) /* BRK COMP1 enable */ -#define ATIM_AF1_BKCMP2E (1 << 2) /* BRK COMP2 enable */ -#define ATIM_AF1_BKCMP3E (1 << 3) /* BRK COMP3 enable */ -#define ATIM_AF1_BKCMP4E (1 << 4) /* BRK COMP4 enable */ -#define ATIM_AF1_BKCMP5E (1 << 5) /* BRK COMP5 enable */ -#define ATIM_AF1_BKCMP6E (1 << 6) /* BRK COMP6 enable */ -#define ATIM_AF1_BKCMP7E (1 << 7) /* BRK COMP7 enable */ -#define ATIM_AF1_BKINP (1 << 9) /* BRK BKIN input polarity */ -#define ATIM_AF1_BKCMP1P (1 << 10) /* BRK COMP1 input polarity */ -#define ATIM_AF1_BKCMP2P (1 << 11) /* BRK COMP2 input polarity */ -#define ATIM_AF1_BKCMP3P (1 << 12) /* BRK COMP3 input polarity */ -#define ATIM_AF1_BKCMP4P (1 << 13) /* BRK COMP4 input polarity */ -#define ATIM_AF1_ETRSEL_SHIFT (14) /* ETR source selection) */ -#define ATIM_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_Pos) - -/* ATIM Alternate function option register 2 (AF2) */ - -#define ATIM_AF2_BK2INE (1 << 0) /* BRK2 BKIN input enable */ -#define ATIM_AF2_BK2CMP1E (1 << 1) /* BRK2 COMP1 enable */ -#define ATIM_AF2_BK2CMP2E (1 << 2) /* BRK2 COMP2 enable */ -#define ATIM_AF2_BK2CMP3E (1 << 3) /* BRK2 COMP3 enable */ -#define ATIM_AF2_BK2CMP4E (1 << 4) /* BRK2 COMP4 enable */ -#define ATIM_AF2_BK2CMP5E (1 << 5) /* BRK2 COMP5 enable */ -#define ATIM_AF2_BK2CMP6E (1 << 6) /* BRK2 COMP6 enable */ -#define ATIM_AF2_BK2CMP7E (1 << 7) /* BRK2 COMP7 enable */ -#define ATIM_AF2_BK2INP (1 << 9) /* BRK2 BKIN input polarity */ -#define ATIM_AF2_BK2CMP1P (1 << 10) /* BRK2 COMP1 input polarity */ -#define ATIM_AF2_BK2CMP2P (1 << 11) /* BRK2 COMP2 input polarity */ -#define ATIM_AF2_BK2CMP3P (1 << 12) /* BRK2 COMP3 input polarity */ -#define ATIM_AF2_BK2CMP4P (1 << 13) /* BRK2 COMP4 input polarity */ -#define ATIM_AF2_OCRSEL_SHIFT (16) /* ocref_clr source selection */ -#define ATIM_AF2_OCRSEL_MASK (0x7 << TIM1_AF2_OCRSEL_Pos) - -/* ATIM DMA control register (DCR) */ - -#define ATIM_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define ATIM_DCR_DBA_MASK (0x1f << ATIM_DCR_DBA_SHIFT) -#define ATIM_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define ATIM_DCR_DBL_MASK (0x1f << ATIM_DCR_DBL_SHIFT) -# define ATIM_DCR_DBL(n) (((n) - 1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Register Bitfield Definitions - GTIM *************************************/ - -/* GTIM: General Timers - * 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5 - * 16-bit General Timers with DMA: TIM15, TIM16, and TIM17 - * - * Caution! TIM2/5, TIM3/4, TIM15, and TIM16/17 are slightly different and - * have different registers, register sizes, and register bitfields! - */ - -/* GTIM Control register 1 (CR1) */ - -#define GTIM_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define GTIM_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define GTIM_CR1_URS (1 << 2) /* Bit 2: Update request source */ -#define GTIM_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define GTIM_CR1_DIR (1 << 4) /* Bit 4: Direction */ -#define GTIM_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define GTIM_CR1_CMS_MASK (0x3 << GTIM_CR1_CMS_SHIFT) -# define GTIM_CR1_EDGE (0x0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define GTIM_CR1_CENTER1 (0x1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define GTIM_CR1_CENTER2 (0x2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define GTIM_CR1_CENTER3 (0x3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ -#define GTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define GTIM_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define GTIM_CR1_CKD_MASK (0x3 << GTIM_CR1_CKD_SHIFT) -# define GTIM_CR1_TCKINT (0x0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS=1*tCK_INT */ -# define GTIM_CR1_2TCKINT (0x1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define GTIM_CR1_4TCKINT (0x2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ -#define GTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping */ -#define GTIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering enable */ - -/* GTIM Control register 2 (CR2) */ - -#define GTIM_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA Selection */ -#define GTIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ -#define GTIM_CR2_MMS_MASK (0x200007 << GTIM_CR2_MMS_SHIFT) -# define GTIM_CR2_MMS_RESET (0x0 << GTIM_CR2_MMS_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRGO */ -# define GTIM_CR2_MMS_ENABLE (0x1 << GTIM_CR2_MMS_SHIFT) /* 0001: Enable - CNT_EN is TRGO */ -# define GTIM_CR2_MMS_UPDATE (0x2 << GTIM_CR2_MMS_SHIFT) /* 0010: Update event is TRGO */ -# define GTIM_CR2_MMS_COMPP (0x3 << GTIM_CR2_MMS_SHIFT) /* 0010: Compare Pulse - CC1IF flag */ -# define GTIM_CR2_MMS_OC1REF (0x4 << GTIM_CR2_MMS_SHIFT) /* 0100: Compare OC1REF is TRGO */ -# define GTIM_CR2_MMS_OC2REF (0x5 << GTIM_CR2_MMS_SHIFT) /* 0101: Compare OC2REF is TRGO */ -# define GTIM_CR2_MMS_OC3REF (0x6 << GTIM_CR2_MMS_SHIFT) /* 0110: Compare OC3REF is TRGO */ -# define GTIM_CR2_MMS_OC4REF (0x7 << GTIM_CR2_MMS_SHIFT) /* 0111: Compare OC4REF is TRGO */ -# define GTIM_CR2_MMS_ENCODER (0x200000 << GTIM_CR2_MMS_SHIFT) /* 1000: Encoder clock is TRGO */ -#define GTIM_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ - -/* GTIM Slave mode control register (SMCR) */ - -#define GTIM_SMCR_SMS_SHIFT (0) /* Bits 0-2: Slave mode selection */ -#define GTIM_SMCR_SMS_MASK (0x10007 << GTIM_SMCR_SMS_SHIFT) -# define GTIM_SMCR_DISAB (0x0 << GTIM_SMCR_SMS_SHIFT) /* 0000: Slave mode disabled */ -# define GTIM_SMCR_ENCMD1 (0x1 << GTIM_SMCR_SMS_SHIFT) /* 0001: Encoder mode 1 */ -# define GTIM_SMCR_ENCMD2 (0x2 << GTIM_SMCR_SMS_SHIFT) /* 0010: Encoder mode 2 */ -# define GTIM_SMCR_ENCMD3 (0x3 << GTIM_SMCR_SMS_SHIFT) /* 0011: Encoder mode 3 */ -# define GTIM_SMCR_RESET (0x4 << GTIM_SMCR_SMS_SHIFT) /* 0100: Reset Mode */ -# define GTIM_SMCR_GATED (0x5 << GTIM_SMCR_SMS_SHIFT) /* 0101: Gated Mode */ -# define GTIM_SMCR_TRIGGER (0x6 << GTIM_SMCR_SMS_SHIFT) /* 0110: Trigger Mode */ -# define GTIM_SMCR_EXTCLK1 (0x7 << GTIM_SMCR_SMS_SHIFT) /* 0111: External Clock Mode 1 */ -# define GTIM_SMCR_RESET_TRIGGER (0x10000 << GTIM_SMCR_SMS_SHIFT) /* 1000: Combined reset + trigger */ -# define GTIM_SMCR_GATED_RESET (0x10001 << GTIM_SMCR_SMS_SHIFT) /* 1001: Combined gated + reset */ -# define GTIM_SMCR_ENCMD4 (0x10002 << GTIM_SMCR_SMS_SHIFT) /* 1010: Encoder mode 4 */ -# define GTIM_SMCR_ENCMD5 (0x10003 << GTIM_SMCR_SMS_SHIFT) /* 1011: Encoder mode 5 */ -# define GTIM_SMCR_ENCMD6 (0x10004 << GTIM_SMCR_SMS_SHIFT) /* 1100: Encoder mode 6 */ -# define GTIM_SMCR_ENCMD7 (0x10005 << GTIM_SMCR_SMS_SHIFT) /* 1101: Encoder mode 7 */ -# define GTIM_SMCR_ENCMD8 (0x10006 << GTIM_SMCR_SMS_SHIFT) /* 1110: Encoder mode 8 */ -# define GTIM_SMCR_ENCMD9 (0x10007 << GTIM_SMCR_SMS_SHIFT) /* 1111: Encoder mode 9 */ -#define GTIM_SMCR_TS_SHIFT (4) /* Bits 4-6: Trigger selection */ -#define GTIM_SMCR_TS_MASK (0x30007 << GTIM_SMCR_TS_SHIFT) -# define GTIM_SMCR_ITR0 (0x0 << GTIM_SMCR_TS_SHIFT) /* 00 000: Internal trigger 0 (ITR0) */ -# define GTIM_SMCR_ITR1 (0x1 << GTIM_SMCR_TS_SHIFT) /* 00 001: Internal trigger 1 (ITR1) */ -# define GTIM_SMCR_ITR2 (0x2 << GTIM_SMCR_TS_SHIFT) /* 00 010: Internal trigger 2 (ITR2) */ -# define GTIM_SMCR_ITR3 (0x3 << GTIM_SMCR_TS_SHIFT) /* 00 011: Internal trigger 3 (ITR3) */ -# define GTIM_SMCR_TI1FED (0x4 << GTIM_SMCR_TS_SHIFT) /* 00 100: TI1 Edge Detector (TI1F_ED) */ -# define GTIM_SMCR_TI1FP1 (0x5 << GTIM_SMCR_TS_SHIFT) /* 00 101: Filtered Timer Input 1 (TI1FP1) */ -# define GTIM_SMCR_TI2FP2 (0x6 << GTIM_SMCR_TS_SHIFT) /* 00 110: Filtered Timer Input 2 (TI2FP2) */ -# define GTIM_SMCR_ETRF (0x7 << GTIM_SMCR_TS_SHIFT) /* 00 111: External Trigger Input (ETRF) */ -# define GTIM_SMCR_ITR4 (0x1000 << GTIM_SMCR_TS_SHIFT) /* 01 000: Internal Trigger 0 ITR4 */ -# define GTIM_SMCR_ITR5 (0x1001 << GTIM_SMCR_TS_SHIFT) /* 01 001: Internal Trigger 1 ITR5 */ -# define GTIM_SMCR_ITR6 (0x1002 << GTIM_SMCR_TS_SHIFT) /* 01 010: Internal Trigger 1 ITR6 */ -# define GTIM_SMCR_ITR7 (0x1003 << GTIM_SMCR_TS_SHIFT) /* 01 011: Internal Trigger 1 ITR7 */ -# define GTIM_SMCR_ITR8 (0x1004 << GTIM_SMCR_TS_SHIFT) /* 01 100: Internal Trigger 1 ITR8 */ -# define GTIM_SMCR_ITR9 (0x1005 << GTIM_SMCR_TS_SHIFT) /* 01 101: Internal Trigger 1 ITR9 */ -# define GTIM_SMCR_ITR10 (0x1006 << GTIM_SMCR_TS_SHIFT) /* 01 110: Internal Trigger 1 ITR10 */ -#define GTIM_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define GTIM_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define GTIM_SMCR_ETF_MASK (0xf << GTIM_SMCR_ETF_SHIFT) -# define GTIM_SMCR_NOFILT (0x0 << GTIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */ -# define GTIM_SMCR_FCKINT2 (0x1 << GTIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_SMCR_FCKINT4 (0x2 << GTIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_SMCR_FCKINT8 (0x3 << GTIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_SMCR_FDTSd26 (0x4 << GTIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_SMCR_FDTSd28 (0x5 << GTIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_SMCR_FDTSd46 (0x6 << GTIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_SMCR_FDTSd48 (0x7 << GTIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_SMCR_FDTSd86 (0x8 << GTIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_SMCR_FDTSd88 (0x9 << GTIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_SMCR_FDTSd165 (0xa << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_SMCR_FDTSd166 (0xb << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_SMCR_FDTSd168 (0xc << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_SMCR_FDTSd325 (0xd << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_SMCR_FDTSd326 (0xe << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_SMCR_FDTSd328 (0xf << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define GTIM_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define GTIM_SMCR_ETPS_MASK (0x3 << GTIM_SMCR_ETPS_SHIFT) -# define GTIM_SMCR_PSCOFF (0x0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define GTIM_SMCR_ETRPd2 (0x1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define GTIM_SMCR_ETRPd4 (0x2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define GTIM_SMCR_ETRPd8 (0x3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ -#define GTIM_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define GTIM_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -#define GTIM_SMCR_SMS (1 << 16) /* Bit 16: Slave mode selection - bit 3 */ -#define GTIM_SMCR_SMSPE (1 << 24) /* Bit 24: SMS preload enable */ -#define GTIM_SMCR_SMSPS (1 << 25) /* Bit 25: SMS preload source */ - -/* GTIM DMA/Interrupt enable register (DIER) */ - -#define GTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define GTIM_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define GTIM_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define GTIM_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define GTIM_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define GTIM_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define GTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define GTIM_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define GTIM_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define GTIM_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define GTIM_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define GTIM_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define GTIM_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ -#define GTIM_DIER_IDXIE (1 << 20) /* Bit 20: Index interrupt enable */ -#define GTIM_DIER_DIRIE (1 << 21) /* Bit 21: Direction change interrupt enable */ -#define GTIM_DIER_IERRIE (1 << 22) /* Bit 22: Index error interrupt enable */ -#define GTIM_DIER_TERRIE (1 << 23) /* Bit 23: Transition error interrupt enable */ - -/* GTIM Status register (SR) */ - -#define GTIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ -#define GTIM_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 Interrupt Flag */ -#define GTIM_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 Interrupt Flag */ -#define GTIM_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 Interrupt Flag */ -#define GTIM_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 Interrupt Flag */ -#define GTIM_SR_TIF (1 << 6) /* Bit 6: Trigger Interrupt Flag */ -#define GTIM_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define GTIM_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define GTIM_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define GTIM_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define GTIM_SR_IDXF (1 << 20) /* Bit 20: Index Interrupt Flag */ -#define GTIM_SR_DIRF (1 << 21) /* Bit 21: Direction Change Interrupt Flag */ -#define GTIM_SR_IERRF (1 << 22) /* Bit 22: Index Error Interrupt Flag */ -#define GTIM_SR_TERRF (1 << 23) /* Bit 23: Transition Error Interrupt Flag */ - -/* GTIM Event generation register (EGR) */ - -#define GTIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define GTIM_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define GTIM_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define GTIM_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define GTIM_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define GTIM_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ - -/* GTIM Capture/compare mode registers (CCMR1) - Output Compare Mode */ - -#define GTIM_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define GTIM_CCMR1_CC1S_MASK (3 << GTIM_CCMR1_CC1S_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define GTIM_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define GTIM_CCMR1_OC1M_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode */ -#define GTIM_CCMR1_OC1M_MASK (7 << GTIM_CCMR1_OC1M_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1Clear Enable */ -#define GTIM_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define GTIM_CCMR1_CC2S_MASK (3 << GTIM_CCMR1_CC2S_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define GTIM_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define GTIM_CCMR1_OC2M_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode */ -#define GTIM_CCMR1_OC2M_MASK (7 << GTIM_CCMR1_OC2M_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ -#define GTIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */ -#define GTIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */ - -/* GTIM Common CCMR (unshifted) Capture/Compare Selection - * bit-field definitions - */ - -#define GTIM_CCMR_CCS_CCOUT (0x0) /* 00: CCx channel output */ -#define GTIM_CCMR_CCS_CCIN1 (0x1) /* 01: CCx channel input, ICx is TIx */ -#define GTIM_CCMR_CCS_CCIN2 (0x2) /* 10: CCx channel input, ICx is TIy */ -#define GTIM_CCMR_CCS_CCINTRC (0x3) /* 11: CCx channel input, ICx is TRC */ - -/* GTIM Common CCMR (unshifted) Compare Mode bit field definitions */ - -#define GTIM_CCMR_MODE_FRZN (0x0) /* 0000: Frozen */ -#define GTIM_CCMR_MODE_CHACT (0x1) /* 0001: Channel x active on match */ -#define GTIM_CCMR_MODE_CHINACT (0x2) /* 0010: Channel x inactive on match */ -#define GTIM_CCMR_MODE_OCREFTOG (0x3) /* 0011: OCxREF toggle GTIM_CNT=GTIM_CCRx */ -#define GTIM_CCMR_MODE_OCREFLO (0x4) /* 0100: OCxREF forced low */ -#define GTIM_CCMR_MODE_OCREFHI (0x5) /* 0101: OCxREF forced high */ -#define GTIM_CCMR_MODE_PWM1 (0x6) /* 0110: PWM mode 1 */ -#define GTIM_CCMR_MODE_PWM2 (0x7) /* 0111: PWM mode 2 */ -#define GTIM_CCMR_MODE_OPM1 (0x8) /* 1000: Retriggerable OPM mode 1 */ -#define GTIM_CCMR_MODE_OPM2 (0x9) /* 1001: Retriggerable OPM mode 2 */ -#define GTIM_CCMR_MODE_COMBINED1 (0xc) /* 1100: Combined PWM mode 1 */ -#define GTIM_CCMR_MODE_COMBINED2 (0xd) /* 1101: Combined PWM mode 2 */ -#define GTIM_CCMR_MODE_ASYMMETRIC1 (0xe) /* 1110: Asymmetric PWM mode 1 */ -#define GTIM_CCMR_MODE_ASYMMETRIC2 (0xf) /* 1111: Asymmetric PWM mode 2 */ - -/* GTIM Capture/compare mode register 1 (CCMR1) - Input Capture Mode - * Bits 0-1 and Bits 8-9 are same as Output Compare Mode - */ - -#define GTIM_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define GTIM_CCMR1_IC1PSC_MASK (0x3 << GTIM_CCMR1_IC1PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define GTIM_CCMR1_IC1F_MASK (0x0f << GTIM_CCMR1_IC1F_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define GTIM_CCMR1_IC2PSC_MASK (0x3 << GTIM_CCMR1_IC2PSC_SHIFT) /* (See common (unshifted) bit field definitions below) */ -#define GTIM_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define GTIM_CCMR1_IC2F_MASK (0x0f << GTIM_CCMR1_IC2F_SHIFT) /* (See common (unshifted) bit field definitions below) */ - -/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */ - -#define GTIM_CCMR_ICPSC_NOPSC (0x0) /* 00: no prescaler, capture each edge */ -#define GTIM_CCMR_ICPSC_EVENTS2 (0x1) /* 01: capture once every 2 events */ -#define GTIM_CCMR_ICPSC_EVENTS4 (0x2) /* 10: capture once every 4 events */ -#define GTIM_CCMR_ICPSC_EVENTS8 (0x3) /* 11: capture once every 8 events */ - -/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */ - -#define GTIM_CCMR_ICF_NOFILT (0x0) /* 0000: No filter, sampling at fDTS */ -#define GTIM_CCMR_ICF_FCKINT2 (0x1) /* 0001: fSAMPLING=fCK_INT, N=2 */ -#define GTIM_CCMR_ICF_FCKINT4 (0x2) /* 0010: fSAMPLING=fCK_INT, N=4 */ -#define GTIM_CCMR_ICF_FCKINT8 (0x3) /* 0011: fSAMPLING=fCK_INT, N=8 */ -#define GTIM_CCMR_ICF_FDTSd26 (0x4) /* 0100: fSAMPLING=fDTS/2, N=6 */ -#define GTIM_CCMR_ICF_FDTSd28 (0x5) /* 0101: fSAMPLING=fDTS/2, N=8 */ -#define GTIM_CCMR_ICF_FDTSd46 (0x6) /* 0110: fSAMPLING=fDTS/4, N=6 */ -#define GTIM_CCMR_ICF_FDTSd48 (0x7) /* 0111: fSAMPLING=fDTS/4, N=8 */ -#define GTIM_CCMR_ICF_FDTSd86 (0x8) /* 1000: fSAMPLING=fDTS/8, N=6 */ -#define GTIM_CCMR_ICF_FDTSd88 (0x9) /* 1001: fSAMPLING=fDTS/8, N=8 */ -#define GTIM_CCMR_ICF_FDTSd165 (0xa) /* 1010: fSAMPLING=fDTS/16, N=5 */ -#define GTIM_CCMR_ICF_FDTSd166 (0xb) /* 1011: fSAMPLING=fDTS/16, N=6 */ -#define GTIM_CCMR_ICF_FDTSd168 (0xc) /* 1100: fSAMPLING=fDTS/16, N=8 */ -#define GTIM_CCMR_ICF_FDTSd325 (0xd) /* 1101: fSAMPLING=fDTS/32, N=5 */ -#define GTIM_CCMR_ICF_FDTSd326 (0xe) /* 1110: fSAMPLING=fDTS/32, N=6 */ -#define GTIM_CCMR_ICF_FDTSd328 (0xf) /* 1111: fSAMPLING=fDTS/32, N=8 */ - -/* GTIM Capture/compare mode register 2 (CCMR2) - Output Compare Mode */ - -#define GTIM_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define GTIM_CCMR2_CC3S_MASK (0x3 << GTIM_CCMR2_CC3S_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define GTIM_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define GTIM_CCMR2_OC3M_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode */ -#define GTIM_CCMR2_OC3M_MASK (0x7 << GTIM_CCMR2_OC3M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ -#define GTIM_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define GTIM_CCMR2_CC4S_MASK (0x3 << GTIM_CCMR2_CC4S_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define GTIM_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define GTIM_CCMR2_OC4M_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode */ -#define GTIM_CCMR2_OC4M_MASK (0x7 << GTIM_CCMR2_OC4M_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ -#define GTIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */ -#define GTIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */ - -/* GTIM Capture/compare mode register 2 (CCMR2) - Input Capture Mode - * Bits 0-1 and Bits 8-9 are same as Output Compare Mode - */ - -#define GTIM_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define GTIM_CCMR2_IC3PSC_MASK (3 << GTIM_CCMR2_IC3PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define GTIM_CCMR2_IC3F_MASK (0x0f << GTIM_CCMR2_IC3F_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define GTIM_CCMR2_IC4PSC_MASK (3 << GTIM_CCMR2_IC4PSC_SHIFT) /* (See common (unshifted) bit field definitions above) */ -#define GTIM_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define GTIM_CCMR2_IC4F_MASK (0x0f << GTIM_CCMR2_IC4F_SHIFT) /* (See common (unshifted) bit field definitions above) */ - -/* GTIM Capture/compare enable register (CCER) */ - -#define GTIM_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 Output Enable */ -#define GTIM_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 Output Polarity */ -#define GTIM_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 Complementary Output Polarity */ -#define GTIM_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 Output Enable */ -#define GTIM_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 Output Polarity */ -#define GTIM_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 Complementary Output Polarity */ -#define GTIM_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 Output Enable */ -#define GTIM_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 Output Polarity */ -#define GTIM_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 Complementary Output Polarity */ -#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */ -#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */ -#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */ -#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */ - -/* GTIM Counter (CNT) */ - -#define GTIM_CNT_SHIFT (0) /* Bits 0-15, 0-30, or 0-31: Timer counter value */ -#define GTIM_CNT_MASK16 (0xffff << GTIM_CNT_SHIFT) /* Bits 0-15 - 16-bit counter value */ -#define GTIM_CNT_MASK31 (0x7fffffff << GTIM_CNT_SHIFT) /* Bits 0-30 - 31-bit counter value, 32-bit counters only */ -#define GTIM_CNT_MASK32 (0xffffffff << GTIM_CNT_SHIFT) /* Bits 0-31 - 32-bit counter value, 32-bit counters only */ -#define GTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy, if not using this bit for counter */ - -/* GTIM Prescaler (PSC) */ - -#define GTIM_PSC_SHIFT (0) -#define GTIM_PSC_MASK (0xffff << GTIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ - -/* GTIM Auto-reload register (ARR) */ - -#define GTIM_ARR_SHIFT (0) -#define GTIM_ARR_MASK_20 (0xfffff << GTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register */ -#define GTIM_ARR_MASK_32 (0xffffffff << GTIM_ARR_SHIFT) /* Bits 0-31: Auto reload register, 32-bit counters only */ - -/* GTIM Repetition counter register (16-bit, TIM15 only) */ - -#define GTIM_RCR_SHIFT (0) -#define GTIM_RCR_MASK (0xff << GTIM_RCR_SHIFT) - -/* GTIM Capture/compare register 1 (CCR1 - CCR4) */ - -#define GTIM_CCR_SHIFT (0) -#define GTIM_CCR_MASK_20 (0xfffff << GTIM_CCR_SHIFT) /* Bits 0-19: Capture/compare 1 value */ -#define GTIM_CCR_MASK_32 (0xffffffff << GTIM_CCR_SHIFT) /* Bits 0-31: Capture/compare 1 value, 32-bit timers only */ - -/* GTIM Break and dead-time register (BDTR) - TIM15-TIM17 only */ - -#define GTIM_BDTR_DTG_SHIFT (0) /* Bits 0-7: Dead-Time Generator set-up */ -#define GTIM_BDTR_DTG_MASK (0xff << GTIM_BDTR_DTG_SHIFT) -#define GTIM_BDTR_LOCK_SHIFT (8) /* Bits 8-9: Lock Configuration */ -#define GTIM_BDTR_LOCK_MASK (3 << GTIM_BDTR_LOCK_SHIFT) -# define GTIM_BDTR_LOCKOFF (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define GTIM_BDTR_LOCK1 (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define GTIM_BDTR_LOCK2 (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define GTIM_BDTR_LOCK3 (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ -#define GTIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define GTIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define GTIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define GTIM_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define GTIM_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define GTIM_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ - -#define GTIM_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define GTIM_BDTR_BKF_MASK (15 << GTIM_BDTR_BKF_SHIFT) -# define GTIM_BDTR_BKF_NOFILT (0 << GTIM_BDTR_BKF_SHIFT) /* 0000: No filter, BRK acts asynchronously */ -# define GTIM_BDTR_BKF_FCKINT2 (1 << GTIM_BDTR_BKF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */ -# define GTIM_BDTR_BKF_FCKINT4 (2 << GTIM_BDTR_BKF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */ -# define GTIM_BDTR_BKF_FCKINT8 (3 << GTIM_BDTR_BKF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */ -# define GTIM_BDTR_BKF_FDTSd26 (4 << GTIM_BDTR_BKF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */ -# define GTIM_BDTR_BKF_FDTSd28 (5 << GTIM_BDTR_BKF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */ -# define GTIM_BDTR_BKF_FDTSd36 (6 << GTIM_BDTR_BKF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */ -# define GTIM_BDTR_BKF_FDTSd38 (7 << GTIM_BDTR_BKF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */ -# define GTIM_BDTR_BKF_FDTSd86 (8 << GTIM_BDTR_BKF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */ -# define GTIM_BDTR_BKF_FDTSd88 (9 << GTIM_BDTR_BKF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */ -# define GTIM_BDTR_BKF_FDTSd165 (10 << GTIM_BDTR_BKF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */ -# define GTIM_BDTR_BKF_FDTSd166 (11 << GTIM_BDTR_BKF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */ -# define GTIM_BDTR_BKF_FDTSd168 (12 << GTIM_BDTR_BKF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */ -# define GTIM_BDTR_BKF_FDTSd325 (13 << GTIM_BDTR_BKF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */ -# define GTIM_BDTR_BKF_FDTSd326 (14 << GTIM_BDTR_BKF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ -# define GTIM_BDTR_BKF_FDTSd328 (15 << GTIM_BDTR_BKF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ -#define GTIM_BDTR_BK_DSRM (1 << 26) /* Bit 26: Break disarm */ -#define GTIM_BDTR_BK_BID (1 << 28) /* Bit 28: Break bidirectional */ - -/* GTIM Option register 1 (OR1) - TIM16, TIM17 only */ - -#define GTIM_OR1_HSE32EN (1 << 0) /* Bit 1: HSE divide by 32 for tim_ti1_in3 */ - -/* GTIM Dead-time register 2 (DTR2) */ - -#define GTIM_DTR2_DTGF_SHIFT (0) /* Dead time falling edge generator setup */ -#define GTIM_DTR2_DTGF_MASK (0xff << GTIM_DTR2_DTGF_SHIFT) -#define GTIM_DTR2_DTAE (1 << 16) /* Dead time asymmetric enable */ -#define GTIM_DTR2_DTPE (1 << 17) /* Dead time preload enable */ - -/* GTIM Encoder control register (ECR) */ - -#define GTIM_ECR_IE (1 << 0) /* Index enable (indicates if index resets counter): 0=no, 1=yes */ -#define GTIM_ECR_IDIR_SHIFT (1) /* Index direction */ -#define GTIM_ECR_IDIR_MASK (0x3 << GTIM_ECR_IDIR_SHIFT) -# define GTIM_ECR_IDIR_BOTH (0x0 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter in both directions */ -# define GTIM_ECR_IDIR_UP (0x1 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting up */ -# define GTIM_ECR_IDIR_DOWN (0x2 << GTIM_ECR_IDIR_SHIFT) /* Index resets the counter when counting down */ -#define GTIM_ECR_FIDX (1 << 5) /* First index: 0=index always resets counter, 1=only first index resets counter */ -#define GTIM_ECR_IPOS_SHIFT (6) /* Index reset position */ -#define GTIM_ECR_IPOS_MASK (0x3 << GTIM_ECR_IPOS_SHIFT) -# define GTIM_ECR_IPOS_00 (0x0 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,0 */ -# define GTIM_ECR_IPOS_01 (0x1 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 0,1 */ -# define GTIM_ECR_IPOS_10 (0x2 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,0 */ -# define GTIM_ECR_IPOS_11 (0x3 << GTIM_ECR_IPOS_SHIFT) /* Index resets position when channels A,B = 1,1 */ -#define GTIM_ECR_PW_SHIFT (16) /* Pulse duration in units of t[PWG], see GTIM_ECR_PWPRSC_MASK */ -#define GTIM_ECR_PW_MASK (0xff << GTIM_ECR_PW_SHIFT) -#define GTIM_ECR_PWPRSC_SHIFT (24) /* Pulse width prescaler */ -#define GTIM_ECR_PWPRSC_MASK (0x7 << GTIM_ECR_PWPRSC_SHIFT) /* t[PWG] = (2^(PWPRSC[2:0])) * t[tim_ker_ck] */ - -/* GTIM Timer input selection register (TISEL) */ - -#define GTIM_TISEL_TI1SEL_SHIFT (0) /* TIM2-TIM5, TIM15-TIM17 */ -#define GTIM_TISEL_TI1SEL_MASK (0xf << TIM_TISEL_TI1SEL_SHIFT) - -#define GTIM_TISEL_TI2SEL_SHIFT (8) /* TIM2-TIM5, TIM15 */ -#define GTIM_TISEL_TI2SEL_MASK (0xf << TIM_TISEL_TI2SEL_SHIFT) - -#define GTIM_TISEL_TI3SEL_SHIFT (16) /* TIM2-TIM5 */ -#define GTIM_TISEL_TI3SEL_MASK (0xf << TIM_TISEL_TI3SEL_SHIFT) - -#define GTIM_TISEL_TI4SEL_SHIFT (24) /* TIM2-TIM5 */ -#define GTIM_TISEL_TI4SEL_MASK (0xf << TIM_TISEL_TI4SEL_SHIFT) - -/* GTIM Alternate function option register 1 (AF1) */ - -#define GTIM_AF1_BKINE (1 << 0) /* BRK BKIN input enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP1E (1 << 1) /* BRK COMP1 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP2E (1 << 2) /* BRK COMP2 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP3E (1 << 3) /* BRK COMP3 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP4E (1 << 4) /* BRK COMP4 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP5E (1 << 5) /* BRK COMP5 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP6E (1 << 6) /* BRK COMP6 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP7E (1 << 7) /* BRK COMP7 enable TIM15-TIM17 only */ -#define GTIM_AF1_BKINP (1 << 9) /* BRK BKIN input polarity TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP1P (1 << 10) /* BRK COMP1 input polarity TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP2P (1 << 11) /* BRK COMP2 input polarity TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP3P (1 << 12) /* BRK COMP3 input polarity TIM15-TIM17 only */ -#define GTIM_AF1_BKCMP4P (1 << 13) /* BRK COMP4 input polarity TIM15-TIM17 only */ -#define GTIM_AF1_ETRSEL_SHIFT (14) /* ETR source selection) TIM2-TIM5 only */ -#define GTIM_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_Pos) - -/* GTIM Alternate function option register 2 (AF2) */ - -#define GTIM_AF2_OCRSEL_SHIFT (16) /* ocref_clr source selection */ -#define GTIM_AF2_OCRSEL_MASK (0x7 << TIM1_AF2_OCRSEL_Pos) - -/* GTIM DMA control register (DCR) */ - -#define GTIM_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define GTIM_DCR_DBA_MASK (0x1f << GTIM_DCR_DBA_SHIFT) -#define GTIM_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define GTIM_DCR_DBL_MASK (0x1f << GTIM_DCR_DBL_SHIFT) -# define GTIM_DCR_DBL(n) (((n) - 1) << GTIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* Register Bitfield Definitions - BTIM *************************************/ - -/* BTIM: Basic Timers - TIM6 and TIM7 */ - -/* BTIM Control register 1 (CR1) */ - -#define BTIM_CR1_CEN (1 << 0) /* Bit 0: Counter Enable */ -#define BTIM_CR1_UDIS (1 << 1) /* Bit 1: Update Disable */ -#define BTIM_CR1_URS (1 << 2) /* Bit 2: Update Request Source */ -#define BTIM_CR1_OPM (1 << 3) /* Bit 3: One Pulse Mode */ -#define BTIM_CR1_ARPE (1 << 7) /* Bit 7: Auto-Reload Preload enable */ -#define BTIM_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remapping: 1=copy UIF bit to bit 32 of CNT register */ -#define BTIM_CR1_DITHEN (1 << 12) /* Bit 12: Dithering Enable (can change only when CEN bit is 0) */ - -/* BTIM Control register 2 (CR2) */ - -#define BTIM_CR2_MMS_SHIFT (4) /* Bits 4-6: Master Mode Selection */ -#define BTIM_CR2_MMS_MASK (0x7 << BTIM_CR2_MMS_SHIFT) -# define BTIM_CR2_RESET (0x0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */ -# define BTIM_CR2_ENAB (0x1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */ -# define BTIM_CR2_UPDT (0x2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */ - -/* BTIM DMA/Interrupt enable register (DIER) */ - -#define BTIM_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define BTIM_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ - -/* BTIM Status register (SR) */ - -#define BTIM_SR_UIF (1 << 0) /* Bit 0: Update Interrupt Flag */ - -/* BTIM Event generation register (EGR) */ - -#define BTIM_EGR_UG (1 << 0) /* Bit 0: Update Generation */ - -/* BTIM Counter (CNT) */ - -#define BTIM_CNT_SHIFT (0) /* Bits 0-15: 16-bit timer counter value */ -#define BTIM_CNT_MASK (0xffff << BTIM_CNT_SHIFT) -#define BTIM_CCER_UIFCPY (1 << 31) /* Bit 31: UIF copy, if BTIM_CR1_UIFREMAP */ - -/* BTIM Prescaler (PSC) */ - -#define BTIM_PSC_SHIFT (0) -#define BTIM_PSC_MASK (0xffff << BTIM_PSC_SHIFT) /* Bits 0-15: Prescaler value */ - -/* BTIM Auto-reload register (ARR) */ - -#define BTIM_ARR_SHIFT (0) /* Bits 0-15 or 0-19: Auto reload register */ -#define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */ -#define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbfs.h b/arch/arm/src/stm32/hardware/stm32_usbfs.h deleted file mode 100644 index 1d83a91e3f0d2..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32_usbfs.h +++ /dev/null @@ -1,250 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_USBFS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ - -#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ - -/* Common Registers */ - -#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ - -#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Addresses *******************************************************/ - -/* Endpoint Registers */ - -#define STM32_USB_EPR(n) (STM32_USB_BASE+STM32_USB_EPR_OFFSET(n)) -#define STM32_USB_EP0R (STM32_USB_BASE+STM32_USB_EP0R_OFFSET) -#define STM32_USB_EP1R (STM32_USB_BASE+STM32_USB_EP1R_OFFSET) -#define STM32_USB_EP2R (STM32_USB_BASE+STM32_USB_EP2R_OFFSET) -#define STM32_USB_EP3R (STM32_USB_BASE+STM32_USB_EP3R_OFFSET) -#define STM32_USB_EP4R (STM32_USB_BASE+STM32_USB_EP4R_OFFSET) -#define STM32_USB_EP5R (STM32_USB_BASE+STM32_USB_EP5R_OFFSET) -#define STM32_USB_EP6R (STM32_USB_BASE+STM32_USB_EP6R_OFFSET) -#define STM32_USB_EP7R (STM32_USB_BASE+STM32_USB_EP7R_OFFSET) - -/* Common Registers */ - -#define STM32_USB_CNTR (STM32_USB_BASE+STM32_USB_CNTR_OFFSET) -#define STM32_USB_ISTR (STM32_USB_BASE+STM32_USB_ISTR_OFFSET) -#define STM32_USB_FNR (STM32_USB_BASE+STM32_USB_FNR_OFFSET) -#define STM32_USB_DADDR (STM32_USB_BASE+STM32_USB_DADDR_OFFSET) -#define STM32_USB_BTABLE (STM32_USB_BASE+STM32_USB_BTABLE_OFFSET) -#define STM32_USB_LPMCSR (STM32_USB_BASE+STM32_USB_LPMCSR_OFFSET) -#define STM32_USB_BCDR (STM32_USB_BASE+STM32_USB_BCDR_OFFSET) - -/* Buffer Descriptor Table (Relatative to BTABLE address) */ - -#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE+STM32_USB_BTABLE_RADDR(ep,o)) -#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) -#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) -#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) -#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* USB endpoint register */ - -#define USB_EPR_EA_SHIFT (0) /* Bits 3:0 [3:0]: Endpoint Address */ -#define USB_EPR_EA_MASK (0X0f << USB_EPR_EA_SHIFT) -#define USB_EPR_STATTX_SHIFT (4) /* Bits 5-4: Status bits, for transmission transfers */ -#define USB_EPR_STATTX_MASK (3 << USB_EPR_STATTX_SHIFT) -# define USB_EPR_STATTX_DIS (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */ -# define USB_EPR_STATTX_STALL (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */ -# define USB_EPR_STATTX_NAK (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */ -# define USB_EPR_STATTX_VALID (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */ -# define USB_EPR_STATTX_DTOG1 (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */ -# define USB_EPR_STATTX_DTOG2 (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */ - -#define USB_EPR_DTOG_TX (1 << 6) /* Bit 6: Data Toggle, for transmission transfers */ -#define USB_EPR_CTR_TX (1 << 7) /* Bit 7: Correct Transfer for transmission */ -#define USB_EPR_EP_KIND (1 << 8) /* Bit 8: Endpoint Kind */ -#define USB_EPR_EPTYPE_SHIFT (9) /* Bits 10-9: Endpoint type */ -#define USB_EPR_EPTYPE_MASK (3 << USB_EPR_EPTYPE_SHIFT) -# define USB_EPR_EPTYPE_BULK (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */ -# define USB_EPR_EPTYPE_CONTROL (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */ -# define USB_EPR_EPTYPE_ISOC (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */ -# define USB_EPR_EPTYPE_INTERRUPT (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */ - -#define USB_EPR_SETUP (1 << 11) /* Bit 11: Setup transaction completed */ -#define USB_EPR_STATRX_SHIFT (12) /* Bits 13-12: Status bits, for reception transfers */ -#define USB_EPR_STATRX_MASK (3 << USB_EPR_STATRX_SHIFT) -# define USB_EPR_STATRX_DIS (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */ -# define USB_EPR_STATRX_STALL (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */ -# define USB_EPR_STATRX_NAK (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */ -# define USB_EPR_STATRX_VALID (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */ -# define USB_EPR_STATRX_DTOG1 (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ -# define USB_EPR_STATRX_DTOG2 (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */ - -#define USB_EPR_DTOG_RX (1 << 14) /* Bit 14: Data Toggle, for reception transfers */ -#define USB_EPR_CTR_RX (1 << 15) /* Bit 15: Correct Transfer for reception */ - -/* USB control register */ - -#define USB_CNTR_FRES (1 << 0) /* Bit 0: Force USB Reset */ -#define USB_CNTR_PDWN (1 << 1) /* Bit 1: Power down */ -#define USB_CNTR_LPMODE (1 << 2) /* Bit 2: Low-power mode */ -#define USB_CNTR_FSUSP (1 << 3) /* Bit 3: Force suspend */ -#define USB_CNTR_RESUME (1 << 4) /* Bit 4: Resume request */ -#define USB_CNTR_ESOFM (1 << 8) /* Bit 8: Expected Start Of Frame Interrupt Mask */ -#define USB_CNTR_SOFM (1 << 9) /* Bit 9: Start Of Frame Interrupt Mask */ -#define USB_CNTR_RESETM (1 << 10) /* Bit 10: USB Reset Interrupt Mask */ -#define USB_CNTR_SUSPM (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */ -#define USB_CNTR_WKUPM (1 << 12) /* Bit 12: Wakeup Interrupt Mask */ -#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */ -#define USB_CNTR_DMAOVRNM (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */ -#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */ - -#define USB_CNTR_ALLINTS (USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|USB_CNTR_SUSPM|\ - USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_DMAOVRNM|USB_CNTR_CTRM) - -/* USB interrupt status register */ - -#define USB_ISTR_EPID_SHIFT (0) /* Bits 3-0: Endpoint Identifier */ -#define USB_ISTR_EPID_MASK (0x0f << USB_ISTR_EPID_SHIFT) -#define USB_ISTR_DIR (1 << 4) /* Bit 4: Direction of transaction */ -#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */ -#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */ -#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */ -#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */ -#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */ -#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */ -#define USB_ISTR_DMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */ -#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */ - -#define USB_ISTR_ALLINTS (USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|USB_ISTR_SUSP|\ - USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_DMAOVRN|USB_ISTR_CTR) - -/* USB frame number register */ - -#define USB_FNR_FN_SHIFT (0) /* Bits 10-0: Frame Number */ -#define USB_FNR_FN_MASK (0x07ff << USB_FNR_FN_SHIFT) -#define USB_FNR_LSOF_SHIFT (11) /* Bits 12-11: Lost SOF */ -#define USB_FNR_LSOF_MASK (3 << USB_FNR_LSOF_SHIFT) -#define USB_FNR_LCK (1 << 13) /* Bit 13: Locked */ -#define USB_FNR_RXDM (1 << 14) /* Bit 14: Receive Data - Line Status */ -#define USB_FNR_RXDP (1 << 15) /* Bit 15: Receive Data + Line Status */ - -/* USB device address */ - -#define USB_DADDR_ADD_SHIFT (0) /* Bits 6-0: Device Address */ -#define USB_DADDR_ADD_MASK (0x7f << USB_DADDR_ADD_SHIFT) -#define USB_DADDR_EF (1 << 7) /* Bit 7: Enable Function */ - -/* Buffer table address */ - -#define USB_BTABLE_SHIFT (3) /* Bits 15:3: Buffer Table */ -#define USB_BTABLE_MASK (0x1fff << USB_BTABLE_SHIFT) - -/* Transmission buffer address */ - -#define USB_ADDR_TX_ZERO (1 << 0) /* Bit 0 Must always be written as ‘0’ */ -#define USB_ADDR_TX_SHIFT (1) /* Bits 15-1: Transmission Buffer Address */ -#define USB_ADDR_TX_MASK (0x7fff << USB_ADDR_ADDR_TX_SHIFT) - -/* Transmission byte count */ - -#define USB_COUNT_TX_SHIFT (0) /* Bits 9-0: Transmission Byte Count */ -#define USB_COUNT_TX_MASK (0x03ff << USB_COUNT_COUNT_TX_SHIFT) - -/* Reception buffer address */ - -#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */ -#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */ -#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT) - -/* Reception byte count */ - -#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */ -#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */ -#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT) -#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ -#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) - -/* LPM control and status register */ - -#define USB_LPMCSR_LPMEN (1 << 0) /* Bit 0: LPM support enable */ -#define USB_LPMCSR_LPMACK (1 << 1) /* Bit 1: LPM Token acknowledge enable */ -#define USB_LPMCSR_REMWAKE (1 << 3) /* Bit 3: bRemoteWake value */ -#define USB_LPMCSR_BESL_SHIFT (4) /* Bits 7-4: BESL value */ -#define USB_LPMCSR_BESL_MASK (0x0f << USB_LPMCSR_BESL_SHIFT) - -/* Battery charging detector */ - -#define USB_BCDR_BCDEN (1 << 0) /* Bit 0: Battery charging detector (BCD) enable */ -#define USB_BCDR_DCDEN (1 << 1) /* Bit 1: Data contact detection (DCD) mode enable */ -#define USB_BCDR_PDEN (1 << 2) /* Bit 2: Primary detection (PD) mode enable */ -#define USB_BCDR_SDEN (1 << 3) /* Bit 3: Secondary detection (SD) mode enable */ -#define USB_BCDR_DCDET (1 << 4) /* Bit 4: Data contact detection (DCD) status */ -#define USB_BCDR_PDET (1 << 5) /* Bit 5: Primary detection (PD) status */ -#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */ -#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ -#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ - -#endif /* CONFIG_STM32_USBFS */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h deleted file mode 100644 index b499a2cc55714..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h +++ /dev/null @@ -1,206 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h deleted file mode 100644 index ee01472c30a48..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h deleted file mode 100644 index 18fc6f1b8b974..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h +++ /dev/null @@ -1,341 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ - -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */ -# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */ -# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */ -#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT) -#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/ -#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ - -#define USART_ISR_ALLBITS (0x007fdfff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -#define USART_ICR_ALLBITS (0x00121b5f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F1/F2/F4 Status register */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h deleted file mode 100644 index edfb2a0cc7159..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 6 -# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 7 -# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h deleted file mode 100644 index 199b4098af427..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h +++ /dev/null @@ -1,1115 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* General definitions */ - -#define OTGFS_EPTYPE_CTRL (0) /* Control */ -#define OTGFS_EPTYPE_ISOC (1) /* Isochronous */ -#define OTGFS_EPTYPE_BULK (2) /* Bulk */ -#define OTGFS_EPTYPE_INTR (3) /* Interrupt */ - -#define OTGFS_PID_DATA0 (0) -#define OTGFS_PID_DATA2 (1) -#define OTGFS_PID_DATA1 (2) -#define OTGFS_PID_MDATA (3) /* Non-control */ -#define OTGFS_PID_SETUP (3) /* Control */ - -/* Register Offsets *********************************************************/ - -/* Core global control and status registers */ - -#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ - -#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) -#define STM32_OTGFS_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */ -#define STM32_OTGFS_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */ -#define STM32_OTGFS_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */ - -/* Host-mode control and status registers */ - -#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ - -#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ - -#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32_OTGFS_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */ -#define STM32_OTGFS_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */ -#define STM32_OTGFS_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */ -#define STM32_OTGFS_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */ -#define STM32_OTGFS_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */ -#define STM32_OTGFS_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */ -#define STM32_OTGFS_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */ -#define STM32_OTGFS_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */ - -#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32_OTGFS_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */ -#define STM32_OTGFS_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */ -#define STM32_OTGFS_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */ -#define STM32_OTGFS_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */ -#define STM32_OTGFS_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */ -#define STM32_OTGFS_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */ -#define STM32_OTGFS_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */ -#define STM32_OTGFS_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */ - -#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32_OTGFS_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */ -#define STM32_OTGFS_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */ - -#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) -#define STM32_OTGFS_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */ -#define STM32_OTGFS_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */ -#define STM32_OTGFS_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */ -#define STM32_OTGFS_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */ -#define STM32_OTGFS_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */ -#define STM32_OTGFS_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */ -#define STM32_OTGFS_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */ -#define STM32_OTGFS_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */ - -/* Device-mode control and status registers */ - -#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ - -#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ - -#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32_OTGFS_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */ -#define STM32_OTGFS_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */ -#define STM32_OTGFS_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */ -#define STM32_OTGFS_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */ - -#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32_OTGFS_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */ -#define STM32_OTGFS_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */ -#define STM32_OTGFS_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */ -#define STM32_OTGFS_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32_OTGFS_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */ -#define STM32_OTGFS_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */ - -#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32_OTGFS_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */ -#define STM32_OTGFS_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */ - -#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ - -#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32_OTGFS_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */ -#define STM32_OTGFS_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */ -#define STM32_OTGFS_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */ -#define STM32_OTGFS_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */ - -#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32_OTGFS_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */ -#define STM32_OTGFS_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */ -#define STM32_OTGFS_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */ -#define STM32_OTGFS_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */ - -#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) -#define STM32_OTGFS_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */ -#define STM32_OTGFS_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */ - -/* Power and clock gating registers */ - -#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) - -#define STM32_OTGFS_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */ - -#define STM32_OTGFS_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */ -#define STM32_OTGFS_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */ - -/* Register Addresses *******************************************************/ - -#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) -#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) -#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) -#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) -#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) -#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) -#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) -#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) -#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) -#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) -#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) -#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) -#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) -#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) -#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) - -#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) -#define STM32_OTGFS_DIEPTXF1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF1_OFFSET) -#define STM32_OTGFS_DIEPTXF2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF2_OFFSET) -#define STM32_OTGFS_DIEPTXF3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF3_OFFSET) - -/* Host-mode control and status registers */ - -#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) -#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) -#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) -#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) -#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) -#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) -#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) - -#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) - -#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32_OTGFS_HCCHAR0 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR0_OFFSET) -#define STM32_OTGFS_HCCHAR1 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR1_OFFSET) -#define STM32_OTGFS_HCCHAR2 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR2_OFFSET) -#define STM32_OTGFS_HCCHAR3 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR3_OFFSET) -#define STM32_OTGFS_HCCHAR4 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR4_OFFSET) -#define STM32_OTGFS_HCCHAR5 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR5_OFFSET) -#define STM32_OTGFS_HCCHAR6 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR6_OFFSET) -#define STM32_OTGFS_HCCHAR7 (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR7_OFFSET) - -#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32_OTGFS_HCINT0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT0_OFFSET) -#define STM32_OTGFS_HCINT1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT1_OFFSET) -#define STM32_OTGFS_HCINT2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT2_OFFSET) -#define STM32_OTGFS_HCINT3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT3_OFFSET) -#define STM32_OTGFS_HCINT4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT4_OFFSET) -#define STM32_OTGFS_HCINT5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT5_OFFSET) -#define STM32_OTGFS_HCINT6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT6_OFFSET) -#define STM32_OTGFS_HCINT7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINT7_OFFSET) - -#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32_OTGFS_HCINTMSK0 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK0_OFFSET) -#define STM32_OTGFS_HCINTMSK1 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK1_OFFSET) -#define STM32_OTGFS_HCINTMSK2 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK2_OFFSET) -#define STM32_OTGFS_HCINTMSK3 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK3_OFFSET) -#define STM32_OTGFS_HCINTMSK4 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK4_OFFSET) -#define STM32_OTGFS_HCINTMSK5 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK5_OFFSET) -#define STM32_OTGFS_HCINTMSK6 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK6_OFFSET) -#define STM32_OTGFS_HCINTMSK7 (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK7_OFFSET)_ - -#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) -#define STM32_OTGFS_HCTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ0_OFFSET) -#define STM32_OTGFS_HCTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ1_OFFSET) -#define STM32_OTGFS_HCTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ2_OFFSET) -#define STM32_OTGFS_HCTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ3_OFFSET) -#define STM32_OTGFS_HCTSIZ4 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ4_OFFSET) -#define STM32_OTGFS_HCTSIZ5 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ5_OFFSET) -#define STM32_OTGFS_HCTSIZ6 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ6_OFFSET) -#define STM32_OTGFS_HCTSIZ7 (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ7_OFFSET) - -/* Device-mode control and status registers */ - -#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) -#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) -#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) -#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) -#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) -#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) -#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) -#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) -#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) -#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) - -#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) - -#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32_OTGFS_DIEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL0_OFFSET) -#define STM32_OTGFS_DIEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL1_OFFSET) -#define STM32_OTGFS_DIEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL2_OFFSET) -#define STM32_OTGFS_DIEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL3_OFFSET) - -#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32_OTGFS_DIEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT0_OFFSET) -#define STM32_OTGFS_DIEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT1_OFFSET) -#define STM32_OTGFS_DIEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT2_OFFSET) -#define STM32_OTGFS_DIEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT3_OFFSET) - -#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32_OTGFS_DIEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ0_OFFSET) -#define STM32_OTGFS_DIEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ1_OFFSET) -#define STM32_OTGFS_DIEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ2_OFFSET) -#define STM32_OTGFS_DIEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ3_OFFSET) - -#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32_OTGFS_DTXFSTS0 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS0_OFFSET) -#define STM32_OTGFS_DTXFSTS1 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS1_OFFSET) -#define STM32_OTGFS_DTXFSTS2 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS2_OFFSET) -#define STM32_OTGFS_DTXFSTS3 (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS3_OFFSET) - -#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) - -#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32_OTGFS_DOEPCTL0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL0_OFFSET) -#define STM32_OTGFS_DOEPCTL1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL1_OFFSET) -#define STM32_OTGFS_DOEPCTL2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL2_OFFSET) -#define STM32_OTGFS_DOEPCTL3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL3_OFFSET) - -#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32_OTGFS_DOEPINT0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT0_OFFSET) -#define STM32_OTGFS_DOEPINT1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT1_OFFSET) -#define STM32_OTGFS_DOEPINT2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT2_OFFSET) -#define STM32_OTGFS_DOEPINT3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT3_OFFSET) - -#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) -#define STM32_OTGFS_DOEPTSIZ0 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ0_OFFSET) -#define STM32_OTGFS_DOEPTSIZ1 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ1_OFFSET) -#define STM32_OTGFS_DOEPTSIZ2 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ2_OFFSET) -#define STM32_OTGFS_DOEPTSIZ3 (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ3_OFFSET) - -/* Power and clock gating registers */ - -#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) - -/* Data FIFO (DFIFO) access registers */ - -#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) - -#define STM32_OTGFS_DFIFO_DEP0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP0_OFFSET) -#define STM32_OTGFS_DFIFO_HCH0 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH0_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP1_OFFSET) -#define STM32_OTGFS_DFIFO_HCH1 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH1_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP2_OFFSET) -#define STM32_OTGFS_DFIFO_HCH2 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH2_OFFSET) - -#define STM32_OTGFS_DFIFO_DEP3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP3_OFFSET) -#define STM32_OTGFS_DFIFO_HCH3 (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH3_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Core global control and status registers */ - -/* Control and status register */ - -#define OTGFS_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ -#define OTGFS_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */ -# define OTGFS_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */ -# define OTGFS_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */ -# define OTGFS_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */ -# define OTGFS_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */ -# define OTGFS_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */ -#endif -#define OTGFS_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ -#define OTGFS_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ -#define OTGFS_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ -#define OTGFS_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */ -#endif - /* Bits 13-15: Reserved, must be kept at reset value */ -#define OTGFS_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ -#define OTGFS_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ -#define OTGFS_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ -#define OTGFS_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */ -#endif -/* Bits 21-31: Reserved, - * must be kept at reset value - */ - -/* Interrupt register */ - -/* Bits 1:0 Reserved, - * must be kept at reset value - */ -#define OTGFS_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ - /* Bits 3-7: Reserved, must be kept at reset value */ -#define OTGFS_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ -#define OTGFS_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ - /* Bits 16:10 Reserved, must be kept at reset value */ -#define OTGFS_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ -#define OTGFS_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ -#define OTGFS_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */ -#endif - /* Bits 21-31: Reserved, must be kept at reset value */ - -/* AHB configuration register */ - -#define OTGFS_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ - /* Bits 1-6: Reserved, must be kept at reset value */ -#define OTGFS_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ -#define OTGFS_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* USB configuration register */ - -#define OTGFS_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ -#define OTGFS_GUSBCFG_TOCAL_MASK (7 << OTGFS_GUSBCFG_TOCAL_SHIFT) - /* Bits 3-5: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ - /* Bit 7: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ -#define OTGFS_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ -#define OTGFS_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ -#define OTGFS_GUSBCFG_TRDT_MASK (15 << OTGFS_GUSBCFG_TRDT_SHIFT) -# define OTGFS_GUSBCFG_TRDT(n) ((n) << OTGFS_GUSBCFG_TRDT_SHIFT) - /* Bits 14-28: Reserved, must be kept at reset value */ -#define OTGFS_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ -#define OTGFS_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ -#define OTGFS_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ - /* Bits 20-31: Reserved, must be kept at reset value */ - -/* Reset register */ - -#define OTGFS_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ -#define OTGFS_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ -#define OTGFS_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ - /* Bit 3 Reserved, must be kept at reset value */ -#define OTGFS_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ -#define OTGFS_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ -#define OTGFS_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ -#define OTGFS_GRSTCTL_TXFNUM_MASK (31 << OTGFS_GRSTCTL_TXFNUM_SHIFT) -# define OTGFS_GRSTCTL_TXFNUM_HNONPER (0 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ -# define OTGFS_GRSTCTL_TXFNUM_HPER (1 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ -# define OTGFS_GRSTCTL_TXFNUM_HALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ -# define OTGFS_GRSTCTL_TXFNUM_D(n) ((n) << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ -# define OTGFS_GRSTCTL_TXFNUM_DALL (16 << OTGFS_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ - -/* Bits 11-31: Reserved, - * must be kept at reset value - */ -#define OTGFS_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ - -/* Core interrupt and Interrupt mask registers */ - -#define OTGFS_GINTSTS_CMOD (1 << 0) /* Bit 0: ro Current mode of operation */ -# define OTGFS_GINTSTS_DEVMODE (0) -# define OTGFS_GINTSTS_HOSTMODE (OTGFS_GINTSTS_CMOD) -#define OTGFS_GINT_MMIS (1 << 1) /* Bit 1: rc_w1 Mode mismatch interrupt */ -#define OTGFS_GINT_OTG (1 << 2) /* Bit 2: ro OTG interrupt */ -#define OTGFS_GINT_SOF (1 << 3) /* Bit 3: rc_w1 Start of frame */ -#define OTGFS_GINT_RXFLVL (1 << 4) /* Bit 4: ro RxFIFO non-empty */ -#define OTGFS_GINT_NPTXFE (1 << 5) /* Bit 5: ro Non-periodic TxFIFO empty */ -#define OTGFS_GINT_GINAKEFF (1 << 6) /* Bit 6: ro Global IN non-periodic NAK effective */ -#define OTGFS_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ -#define OTGFS_GINT_RES89 (3 << 8) /* Bits 8-9: Reserved, must be kept at reset value */ -#define OTGFS_GINT_ESUSP (1 << 10) /* Bit 10: rc_w1 Early suspend */ -#define OTGFS_GINT_USBSUSP (1 << 11) /* Bit 11: rc_w1 USB suspend */ -#define OTGFS_GINT_USBRST (1 << 12) /* Bit 12: rc_w1 USB reset */ -#define OTGFS_GINT_ENUMDNE (1 << 13) /* Bit 13: rc_w1 Enumeration done */ -#define OTGFS_GINT_ISOODRP (1 << 14) /* Bit 14: rc_w1 Isochronous OUT packet dropped interrupt */ -#define OTGFS_GINT_EOPF (1 << 15) /* Bit 15: rc_w1 End of periodic frame interrupt */ -#define OTGFS_GINT_RES16 (1 << 16) /* Bit 16 Reserved, must be kept at reset value */ -#define OTGFS_GINTMSK_EPMISM (1 << 17) /* Bit 17: Reserved in GINT rw Endpoint mismatch interrupt mask */ -#define OTGFS_GINT_IEP (1 << 18) /* Bit 18: ro IN endpoint interrupt */ -#define OTGFS_GINT_OEP (1 << 19) /* Bit 19: ro OUT endpoint interrupt */ -#define OTGFS_GINT_IISOIXFR (1 << 20) /* Bit 20: rc_w1 Incomplete isochronous IN transfer */ -#define OTGFS_GINT_IISOOXFR (1 << 21) /* Bit 21: rc_w1 Incomplete isochronous OUT transfer (device) */ -#define OTGFS_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ -# define OTGFS_GINT_RSTDET (1 << 23) /* Bits 23: asserted when a reset is detected on the USB in partial */ -#else -# define OTGFS_GINT_RES2223 (3 << 22) /* Bits 22-23: Reserved, must be kept at reset value */ -#endif -#define OTGFS_GINT_HPRT (1 << 24) /* Bit 24: ro Host port interrupt */ -#define OTGFS_GINT_HC (1 << 25) /* Bit 25: ro Host channels interrupt */ -#define OTGFS_GINT_PTXFE (1 << 26) /* Bit 26: ro Periodic TxFIFO empty */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -#define OTGFS_GINT_LPMINT (1 << 27) /* Bit 27 LPM interrupt */ -#else -#define OTGFS_GINT_RES27 (1 << 27) /* Bit 27 Reserved, must be kept at reset value */ -#endif -#define OTGFS_GINT_CIDSCHG (1 << 28) /* Bit 28: rc_w1 Connector ID status change */ -#define OTGFS_GINT_DISC (1 << 29) /* Bit 29: rc_w1 Disconnect detected interrupt */ -#define OTGFS_GINT_SRQ (1 << 30) /* Bit 30: rc_w1 Session request/new session detected interrupt */ -#define OTGFS_GINT_WKUP (1 << 31) /* Bit 31: rc_w1 Resume/remote wakeup detected interrupt */ - -/* Receive status debug read/OTG status read and pop registers - * (host mode) - */ - -#define OTGFS_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ -#define OTGFS_GRXSTSH_CHNUM_MASK (15 << OTGFS_GRXSTSH_CHNUM_SHIFT) -#define OTGFS_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGFS_GRXSTSH_BCNT_MASK (0x7ff << OTGFS_GRXSTSH_BCNT_SHIFT) -#define OTGFS_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGFS_GRXSTSH_DPID_MASK (3 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA0 (0 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA2 (1 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_DATA1 (2 << OTGFS_GRXSTSH_DPID_SHIFT) -# define OTGFS_GRXSTSH_DPID_MDATA (3 << OTGFS_GRXSTSH_DPID_SHIFT) -#define OTGFS_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGFS_GRXSTSH_PKTSTS_MASK (15 << OTGFS_GRXSTSH_PKTSTS_SHIFT) -# define OTGFS_GRXSTSH_PKTSTS_INRECVD (2 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ -# define OTGFS_GRXSTSH_PKTSTS_INDONE (3 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ -# define OTGFS_GRXSTSH_PKTSTS_DTOGERR (5 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ -# define OTGFS_GRXSTSH_PKTSTS_HALTED (7 << OTGFS_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ - -/* Bits 21-31: Reserved, - * must be kept at reset value - */ - -/* Receive status debug read/OTG status read and pop registers - * (device mode) - */ - -#define OTGFS_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ -#define OTGFS_GRXSTSD_EPNUM_MASK (15 << OTGFS_GRXSTSD_EPNUM_SHIFT) -#define OTGFS_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ -#define OTGFS_GRXSTSD_BCNT_MASK (0x7ff << OTGFS_GRXSTSD_BCNT_SHIFT) -#define OTGFS_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ -#define OTGFS_GRXSTSD_DPID_MASK (3 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA0 (0 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA2 (1 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_DATA1 (2 << OTGFS_GRXSTSD_DPID_SHIFT) -# define OTGFS_GRXSTSD_DPID_MDATA (3 << OTGFS_GRXSTSD_DPID_SHIFT) -#define OTGFS_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ -#define OTGFS_GRXSTSD_PKTSTS_MASK (15 << OTGFS_GRXSTSD_PKTSTS_SHIFT) -# define OTGFS_GRXSTSD_PKTSTS_OUTNAK (1 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ -# define OTGFS_GRXSTSD_PKTSTS_OUTRECVD (2 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ -# define OTGFS_GRXSTSD_PKTSTS_OUTDONE (3 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ -# define OTGFS_GRXSTSD_PKTSTS_SETUPDONE (4 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ -# define OTGFS_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTGFS_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ - -#define OTGFS_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ -#define OTGFS_GRXSTSD_FRMNUM_MASK (15 << OTGFS_GRXSTSD_FRMNUM_SHIFT) - /* Bits 25-31: Reserved, must be kept at reset value */ - -/* Receive FIFO size register */ - -#define OTGFS_GRXFSIZ_MASK (0xffff) - -/* Host non-periodic transmit FIFO size register */ - -#define OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ -#define OTGFS_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFSA_SHIFT) -#define OTGFS_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ -#define OTGFS_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGFS_HNPTXFSIZ_NPTXFD_MIN (16 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) -# define OTGFS_HNPTXFSIZ_NPTXFD_MAX (256 << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT) - -/* Endpoint 0 Transmit FIFO size */ - -#define OTGFS_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ -#define OTGFS_DIEPTXF0_TX0FD_MASK (0xffff << OTGFS_DIEPTXF0_TX0FD_SHIFT) -#define OTGFS_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ -#define OTGFS_DIEPTXF0_TX0FSA_MASK (0xffff << OTGFS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGFS_DIEPTXF0_TX0FSA_MIN (16 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) -# define OTGFS_DIEPTXF0_TX0FSA_MAX (256 << OTGFS_DIEPTXF0_TX0FSA_SHIFT) - -/* Non-periodic transmit FIFO/queue status register */ - -#define OTGFS_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ -#define OTGFS_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) -# define OTGFS_HNPTXSTS_NPTXFSAV_FULL (0 << OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) -#define OTGFS_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ -#define OTGFS_HNPTXSTS_NPTQXSAV_MASK (0xff << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) -# define OTGFS_HNPTXSTS_NPTQXSAV_FULL (0 << OTGFS_HNPTXSTS_NPTQXSAV_SHIFT) -#define OTGFS_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ -#define OTGFS_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTGFS_HNPTXSTS_NPTXQTOP_SHIFT) -# define OTGFS_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGFS_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ -# define OTGFS_HNPTXSTS_TYPE_MASK (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) -# define OTGFS_HNPTXSTS_TYPE_INOUT (0 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGFS_HNPTXSTS_TYPE_ZLP (1 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ -# define OTGFS_HNPTXSTS_TYPE_HALT (3 << OTGFS_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ - -# define OTGFS_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGFS_HNPTXSTS_CHNUM_MASK (15 << OTGFS_HNPTXSTS_CHNUM_SHIFT) -# define OTGFS_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGFS_HNPTXSTS_EPNUM_MASK (15 << OTGFS_HNPTXSTS_EPNUM_SHIFT) - /* Bit 31 Reserved, must be kept at reset value */ - -/* General core configuration register */ - -/* Bits 0-15: Reserved, - * must be kept at reset value - */ -#define OTGFS_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ - /* Bit 17 Reserved, must be kept at reset value */ -#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define OTGFS_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */ -#else -# define OTGFS_GCCFG_VBUSASEN (1 << 18) /* Bit 18: Enable the VBUS sensing A device */ -# define OTGFS_GCCFG_VBUSBSEN (1 << 19) /* Bit 19: Enable the VBUS sensing B device */ -# define OTGFS_GCCFG_SOFOUTEN (1 << 20) /* Bit 20: SOF output enable */ -# define OTGFS_GCCFG_NOVBUSSENS (1 << 21) /* Bit 21: VBUS sensing disable option */ -#endif - /* Bits 22-31: Reserved, must be kept at reset value */ - -/* Core ID register (32-bit product ID) */ - -/* Host periodic transmit FIFO size register */ - -#define OTGFS_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ -#define OTGFS_HPTXFSIZ_PTXSA_MASK (0xffff << OTGFS_HPTXFSIZ_PTXSA_SHIFT) -#define OTGFS_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ -#define OTGFS_HPTXFSIZ_PTXFD_MASK (0xffff << OTGFS_HPTXFSIZ_PTXFD_SHIFT) - -/* Device IN endpoint transmit FIFOn size register */ - -#define OTGFS_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ -#define OTGFS_DIEPTXF_INEPTXSA_MASK (0xffff << OTGFS_DIEPTXF_INEPTXSA_SHIFT) -#define OTGFS_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ -#define OTGFS_DIEPTXF_INEPTXFD_MASK (0xffff << OTGFS_DIEPTXF_INEPTXFD_SHIFT) -# define OTGFS_DIEPTXF_INEPTXFD_MIN (16 << OTGFS_DIEPTXF_INEPTXFD_MASK) - -/* Host-mode control and status registers */ - -/* Host configuration register */ - -#define OTGFS_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ -#define OTGFS_HCFG_FSLSPCS_MASK (3 << OTGFS_HCFG_FSLSPCS_SHIFT) -# define OTGFS_HCFG_FSLSPCS_FS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ -# define OTGFS_HCFG_FSLSPCS_LS48MHz (1 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ -# define OTGFS_HCFG_FSLSPCS_LS6MHz (2 << OTGFS_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ - -#define OTGFS_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ - /* Bits 31:3 Reserved, must be kept at reset value */ - -/* Host frame interval register */ - -#define OTGFS_HFIR_MASK (0xffff) - -/* Host frame number/frame time remaining register */ - -#define OTGFS_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ -#define OTGFS_HFNUM_FRNUM_MASK (0xffff << OTGFS_HFNUM_FRNUM_SHIFT) -#define OTGFS_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ -#define OTGFS_HFNUM_FTREM_MASK (0xffff << OTGFS_HFNUM_FTREM_SHIFT) - -/* Host periodic transmit FIFO/queue status register */ - -#define OTGFS_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ -#define OTGFS_HPTXSTS_PTXFSAVL_MASK (0xffff << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) -# define OTGFS_HPTXSTS_PTXFSAVL_FULL (0 << OTGFS_HPTXSTS_PTXFSAVL_SHIFT) -#define OTGFS_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ -#define OTGFS_HPTXSTS_PTXQSAV_MASK (0xff << OTGFS_HPTXSTS_PTXQSAV_SHIFT) -# define OTGFS_HPTXSTS_PTXQSAV_FULL (0 << OTGFS_HPTXSTS_PTXQSAV_SHIFT) -#define OTGFS_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ -#define OTGFS_HPTXSTS_PTXQTOP_MASK (0x7f << OTGFS_HPTXSTS_PTXQTOP_SHIFT) -# define OTGFS_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ -# define OTGFS_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ -# define OTGFS_HPTXSTS_TYPE_MASK (3 << OTGFS_HPTXSTS_TYPE_SHIFT) -# define OTGFS_HPTXSTS_TYPE_INOUT (0 << OTGFS_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ -# define OTGFS_HPTXSTS_TYPE_ZLP (1 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ -# define OTGFS_HPTXSTS_TYPE_HALT (3 << OTGFS_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ - -# define OTGFS_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ -# define OTGFS_HPTXSTS_EPNUM_MASK (15 << OTGFS_HPTXSTS_EPNUM_SHIFT) -# define OTGFS_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ -# define OTGFS_HPTXSTS_CHNUM_MASK (15 << OTGFS_HPTXSTS_CHNUM_SHIFT) -# define OTGFS_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ - -/* Host all channels interrupt and all channels interrupt mask registers */ - -#define OTGFS_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ - -/* Host port control and status register */ - -#define OTGFS_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ -#define OTGFS_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ -#define OTGFS_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ -#define OTGFS_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ -#define OTGFS_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ -#define OTGFS_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ -#define OTGFS_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ -#define OTGFS_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ -#define OTGFS_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ - /* Bit 9: Reserved, must be kept at reset value */ -#define OTGFS_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ -#define OTGFS_HPRT_PLSTS_MASK (3 << OTGFS_HPRT_PLSTS_SHIFT) -# define OTGFS_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ -# define OTGFS_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ -#define OTGFS_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ -#define OTGFS_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ -#define OTGFS_HPRT_PTCTL_MASK (15 << OTGFS_HPRT_PTCTL_SHIFT) -# define OTGFS_HPRT_PTCTL_DISABLED (0 << OTGFS_HPRT_PTCTL_SHIFT) /* Test mode disabled */ -# define OTGFS_HPRT_PTCTL_J (1 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_J mode */ -# define OTGFS_HPRT_PTCTL_L (2 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_K mode */ -# define OTGFS_HPRT_PTCTL_SE0_NAK (3 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGFS_HPRT_PTCTL_PACKET (4 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ -# define OTGFS_HPRT_PTCTL_FORCE (5 << OTGFS_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGFS_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ -#define OTGFS_HPRT_PSPD_MASK (3 << OTGFS_HPRT_PSPD_SHIFT) -# define OTGFS_HPRT_PSPD_FS (1 << OTGFS_HPRT_PSPD_SHIFT) /* Full speed */ -# define OTGFS_HPRT_PSPD_LS (2 << OTGFS_HPRT_PSPD_SHIFT) /* Low speed */ - -/* Bits 19-31: Reserved, - * must be kept at reset value - */ - -/* Host channel-n characteristics register */ - -#define OTGFS_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_HCCHAR_MPSIZ_MASK (0x7ff << OTGFS_HCCHAR_MPSIZ_SHIFT) -#define OTGFS_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ -#define OTGFS_HCCHAR_EPNUM_MASK (15 << OTGFS_HCCHAR_EPNUM_SHIFT) -#define OTGFS_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ -# define OTGFS_HCCHAR_EPDIR_OUT (0) -# define OTGFS_HCCHAR_EPDIR_IN OTGFS_HCCHAR_EPDIR - -/* Bit 16 Reserved, - * must be kept at reset value - */ -#define OTGFS_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ -#define OTGFS_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_HCCHAR_EPTYP_MASK (3 << OTGFS_HCCHAR_EPTYP_SHIFT) -# define OTGFS_HCCHAR_EPTYP_CTRL (0 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Control */ -# define OTGFS_HCCHAR_EPTYP_ISOC (1 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_HCCHAR_EPTYP_BULK (2 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_HCCHAR_EPTYP_INTR (3 << OTGFS_HCCHAR_EPTYP_SHIFT) /* Interrupt */ - -#define OTGFS_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ -#define OTGFS_HCCHAR_MCNT_MASK (3 << OTGFS_HCCHAR_MCNT_SHIFT) -#define OTGFS_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ -#define OTGFS_HCCHAR_DAD_MASK (0x7f << OTGFS_HCCHAR_DAD_SHIFT) -#define OTGFS_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ -#define OTGFS_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ -#define OTGFS_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ - -/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ - -#define OTGFS_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ -#define OTGFS_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ -#define OTGFS_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ -#define OTGFS_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ -#define OTGFS_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ -#define OTGFS_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ -#define OTGFS_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ -#define OTGFS_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ -#define OTGFS_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ - -/* Bits 11-31 Reserved, - * must be kept at reset value - */ - -/* Host channel-n interrupt register */ - -#define OTGFS_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_HCTSIZ_XFRSIZ_SHIFT) -#define OTGFS_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ -#define OTGFS_HCTSIZ_PKTCNT_MASK (0x3ff << OTGFS_HCTSIZ_PKTCNT_SHIFT) -#define OTGFS_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ -#define OTGFS_HCTSIZ_DPID_MASK (3 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA0 (0 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA2 (1 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_DATA1 (2 << OTGFS_HCTSIZ_DPID_SHIFT) -# define OTGFS_HCTSIZ_DPID_MDATA (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Non-control */ -# define OTGFS_HCTSIZ_PID_SETUP (3 << OTGFS_HCTSIZ_DPID_SHIFT) /* Control */ - -/* Bit 31 Reserved, - * must be kept at reset value - */ - -/* Device-mode control and status registers */ - -/* Device configuration register */ - -#define OTGFS_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ -#define OTGFS_DCFG_DSPD_MASK (3 << OTGFS_DCFG_DSPD_SHIFT) -# define OTGFS_DCFG_DSPD_FS (3 << OTGFS_DCFG_DSPD_SHIFT) /* Full speed */ - -#define OTGFS_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ - /* Bit 3: Reserved, must be kept at reset value */ -#define OTGFS_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ -#define OTGFS_DCFG_DAD_MASK (0x7f << OTGFS_DCFG_DAD_SHIFT) -#define OTGFS_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ -#define OTGFS_DCFG_PFIVL_MASK (3 << OTGFS_DCFG_PFIVL_SHIFT) -# define OTGFS_DCFG_PFIVL_80PCT (0 << OTGFS_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ -# define OTGFS_DCFG_PFIVL_85PCT (1 << OTGFS_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ -# define OTGFS_DCFG_PFIVL_90PCT (2 << OTGFS_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ -# define OTGFS_DCFG_PFIVL_95PCT (3 << OTGFS_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ - -/* Bits 13-31 Reserved, - * must be kept at reset value - */ - -/* Device control register */ - -#define OTGFS_TESTMODE_DISABLED (0) /* Test mode disabled */ -#define OTGFS_TESTMODE_J (1) /* Test_J mode */ -#define OTGFS_TESTMODE_K (2) /* Test_K mode */ -#define OTGFS_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ -#define OTGFS_TESTMODE_PACKET (4) /* Test_Packet mode */ -#define OTGFS_TESTMODE_FORCE (5) /* Test_Force_Enable */ - -#define OTGFS_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ -#define OTGFS_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ -#define OTGFS_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ -#define OTGFS_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ -#define OTGFS_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ -#define OTGFS_DCTL_TCTL_MASK (7 << OTGFS_DCTL_TCTL_SHIFT) -# define OTGFS_DCTL_TCTL_DISABLED (0 << OTGFS_DCTL_TCTL_SHIFT) /* Test mode disabled */ -# define OTGFS_DCTL_TCTL_J (1 << OTGFS_DCTL_TCTL_SHIFT) /* Test_J mode */ -# define OTGFS_DCTL_TCTL_K (2 << OTGFS_DCTL_TCTL_SHIFT) /* Test_K mode */ -# define OTGFS_DCTL_TCTL_SE0_NAK (3 << OTGFS_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ -# define OTGFS_DCTL_TCTL_PACKET (4 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Packet mode */ -# define OTGFS_DCTL_TCTL_FORCE (5 << OTGFS_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ - -#define OTGFS_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ -#define OTGFS_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ -#define OTGFS_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ -#define OTGFS_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ -#define OTGFS_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ - /* Bits 12-31: Reserved, must be kept at reset value */ - -/* Device status register */ - -#define OTGFS_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ -#define OTGFS_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ -#define OTGFS_DSTS_ENUMSPD_MASK (3 << OTGFS_DSTS_ENUMSPD_SHIFT) -# define OTGFS_DSTS_ENUMSPD_FS (3 << OTGFS_DSTS_ENUMSPD_MASK) /* Full speed */ - -/* Bits 4-7: Reserved, - * must be kept at reset value - */ -#define OTGFS_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ -#define OTGFS_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ -#define OTGFS_DSTS_SOFFN_MASK (0x3fff << OTGFS_DSTS_SOFFN_SHIFT) -#define OTGFS_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ -#define OTGFS_DSTS_SOFFN_EVEN 0 -#define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 - /* Bits 22-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint common interrupt mask register */ - -#define OTGFS_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGFS_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ -#define OTGFS_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ -#define OTGFS_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ -#define OTGFS_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint common interrupt mask register */ - -#define OTGFS_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ -#define OTGFS_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ -#define OTGFS_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -/* Device all endpoints interrupt and All endpoints interrupt mask - * registers - */ - -#define OTGFS_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ -#define OTGFS_DAINT_IEP_MASK (0xffff << OTGFS_DAINT_IEP_SHIFT) -# define OTGFS_DAINT_IEP(n) (1 << (n)) -#define OTGFS_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ -#define OTGFS_DAINT_OEP_MASK (0xffff << OTGFS_DAINT_OEP_SHIFT) -# define OTGFS_DAINT_OEP(n) (1 << ((n)+16)) - -/* Device VBUS discharge time register */ - -#define OTGFS_DVBUSDIS_MASK (0xffff) - -/* Device VBUS pulsing time register */ - -#define OTGFS_DVBUSPULSE_MASK (0xfff) - -/* Device IN endpoint FIFO empty interrupt mask register */ - -#define OTGFS_DIEPEMPMSK(n) (1 << (n)) - -/* Device control IN endpoint 0 control register */ - -#define OTGFS_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGFS_DIEPCTL0_MPSIZ_MASK (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) -# define OTGFS_DIEPCTL0_MPSIZ_64 (0 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_32 (1 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_16 (2 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGFS_DIEPCTL0_MPSIZ_8 (3 << OTGFS_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGFS_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DIEPCTL0_EPTYP_MASK (3 << OTGFS_DIEPCTL0_EPTYP_SHIFT) -# define OTGFS_DIEPCTL0_EPTYP_CTRL (0 << OTGFS_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGFS_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGFS_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGFS_DIEPCTL0_TXFNUM_MASK (15 << OTGFS_DIEPCTL0_TXFNUM_SHIFT) -#define OTGFS_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device control IN endpoint n control register */ - -#define OTGFS_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_DIEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DIEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGFS_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGFS_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ -# define OTGFS_DIEPCTL_EVEN (0) -# define OTGFS_DIEPCTL_ODD OTGFS_DIEPCTL_EONUM -# define OTGFS_DIEPCTL_DATA0 (0) -# define OTGFS_DIEPCTL_DATA1 OTGFS_DIEPCTL_EONUM -#define OTGFS_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DIEPCTL_EPTYP_MASK (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) -# define OTGFS_DIEPCTL_EPTYP_CTRL (0 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGFS_DIEPCTL_EPTYP_ISOC (1 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_DIEPCTL_EPTYP_BULK (2 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_DIEPCTL_EPTYP_INTR (3 << OTGFS_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ - -/* Bit 20: Reserved, - * must be kept at reset value - */ -#define OTGFS_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ -#define OTGFS_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ -#define OTGFS_DIEPCTL_TXFNUM_MASK (15 << OTGFS_DIEPCTL_TXFNUM_SHIFT) -#define OTGFS_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGFS_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGFS_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ -#define OTGFS_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ -#define OTGFS_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGFS_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGFS_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ -#define OTGFS_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGFS_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ -#define OTGFS_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ - /* Bits 8-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint 0 transfer size register */ - -#define OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGFS_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DIEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGFS_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ -#define OTGFS_DIEPTSIZ0_PKTCNT_MASK (3 << OTGFS_DIEPTSIZ0_PKTCNT_SHIFT) - /* Bits 21-31: Reserved, must be kept at reset value */ - -/* Device IN endpoint n transfer size register */ - -#define OTGFS_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DIEPTSIZ_XFRSIZ_SHIFT) -#define OTGFS_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGFS_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DIEPTSIZ_PKTCNT_SHIFT) -#define OTGFS_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ -#define OTGFS_DIEPTSIZ_MCNT_MASK (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint TxFIFO status register */ - -#define OTGFS_DTXFSTS_MASK (0xffff) - -/* Device OUT endpoint 0 control register */ - -#define OTGFS_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ -#define OTGFS_DOEPCTL0_MPSIZ_MASK (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) -# define OTGFS_DOEPCTL0_MPSIZ_64 (0 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_32 (1 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_16 (2 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ -# define OTGFS_DOEPCTL0_MPSIZ_8 (3 << OTGFS_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - -/* Bits 2-14: Reserved, - * must be kept at reset value - */ -#define OTGFS_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DOEPCTL0_EPTYP_MASK (3 << OTGFS_DOEPCTL0_EPTYP_SHIFT) -# define OTGFS_DOEPCTL0_EPTYP_CTRL (0 << OTGFS_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - -#define OTGFS_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGFS_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device OUT endpoint n control register */ - -#define OTGFS_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ -#define OTGFS_DOEPCTL_MPSIZ_MASK (0x7ff << OTGFS_DOEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ -#define OTGFS_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */ -# define OTGFS_DOEPCTL_DATA0 (0) -# define OTGFS_DOEPCTL_DATA1 OTGFS_DOEPCTL_DPID -#define OTGFS_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ -# define OTGFS_DOEPCTL_EVEN (0) -# define OTGFS_DOEPCTL_ODD OTGFS_DOEPCTL_EONUM -#define OTGFS_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ -#define OTGFS_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ -#define OTGFS_DOEPCTL_EPTYP_MASK (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) -# define OTGFS_DOEPCTL_EPTYP_CTRL (0 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Control */ -# define OTGFS_DOEPCTL_EPTYP_ISOC (1 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ -# define OTGFS_DOEPCTL_EPTYP_BULK (2 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Bulk */ -# define OTGFS_DOEPCTL_EPTYP_INTR (3 << OTGFS_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ - -#define OTGFS_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ -#define OTGFS_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ -#define OTGFS_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ -#define OTGFS_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ -#define OTGFS_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ -#define OTGFS_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ -#define OTGFS_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ -#define OTGFS_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ -#define OTGFS_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ -#define OTGFS_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ - -/* Device endpoint-n interrupt register */ - -#define OTGFS_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ -#define OTGFS_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ -#define OTGFS_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ -#define OTGFS_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ - /* Bit 5: Reserved, must be kept at reset value */ -#define OTGFS_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ - /* Bits 7-31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-0 transfer size register */ - -#define OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ -#define OTGFS_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ -#define OTGFS_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ - /* Bits 20-28: Reserved, must be kept at reset value */ -#define OTGFS_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGFS_DOEPTSIZ0_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Device OUT endpoint-n transfer size register */ - -#define OTGFS_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ -#define OTGFS_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT) -#define OTGFS_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ -#define OTGFS_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTGFS_DOEPTSIZ_PKTCNT_SHIFT) -#define OTGFS_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ -#define OTGFS_DOEPTSIZ_STUPCNT_MASK (3 << OTGFS_DOEPTSIZ_STUPCNT_SHIFT) -#define OTGFS_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ -#define OTGFS_DOEPTSIZ_RXDPID_MASK (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA0 (0 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA2 (1 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_DATA1 (2 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) -# define OTGFS_DOEPTSIZ_RXDPID_MDATA (3 << OTGFS_DOEPTSIZ_RXDPID_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ - -/* Power and clock gating control register */ - -#define OTGFS_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ -#define OTGFS_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ - /* Bits 2-3: Reserved, must be kept at reset value */ -#define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ - /* Bits 5-31: Reserved, must be kept at reset value */ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h deleted file mode 100644 index 98990ba21e39e..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h +++ /dev/null @@ -1,439 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ - -/* Register Addresses *******************************************************/ -#if (STM32_NLPUART > 0) -# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 0) -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 1) -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 2) -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 3) -# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 4) -# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control Register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */ -#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */ -#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */ - -#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1) - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \ - USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -#define LPUART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control Register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */ -#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */ -#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */ -#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */ -# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */ -# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */ -# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */ -#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */ -#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */ -#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */ -#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */ -#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */ -#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */ -# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */ -# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */ -# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */ -#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */ -#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */ -#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT) - -/* Control Register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */ -#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */ -#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */ -#define USART_CR3_DEP (1 << 15) -#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */ -#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK) -#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */ -#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */ -# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */ -# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */ -#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */ -#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */ -#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */ -#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */ -#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */ -# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */ -#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */ -#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */ -# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */ - -/* BAUD Rate Register */ - -/* Full BRR field */ - -#define USART_BRR_SHIFT (0) -#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT) -# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK) - -/* Partial BRR field BRR[3:0]: - * - * When OVER8 = 0: BRR[3:0] = USARTDIV[3:0] - * - * When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and - * BRR[3] must be kept cleared. - */ - -#define USART_BRR_0_3_SHIFT (0) -#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT) -# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK) - -/* Partial BRR field BRR[15:4]: - * BRR[15:4] = USARTDIV[15:4] - */ - -#define USART_BRR_4_15_SHIFT (4) -#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT) -# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK) - -/* Guard Time and Prescaler Register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK) -#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK) - -/* Receiver Timeout Register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK) -#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */ - -/* Interrupt and Status Register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */ -#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */ -#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */ -#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */ -#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */ -#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt Flag Clear Register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */ - -/* Receive Data Register */ - -#define USART_RDR_SHIFT (0) -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) -# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK) - -/* Transmit Data Register */ - -#define USART_TDR_SHIFT (0) -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK) - -/* Prescaler Register */ - -#define USART_PRESC_PRESCALER_SHIFT (0) -#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* Compatibility with F1/F2/F4 Status Register names */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -#define USART_CR1_M USART_CR1_M0 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h deleted file mode 100644 index 5a1a52ca69e48..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h +++ /dev/null @@ -1,525 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_IP_DAC_M3M4_V2 -#undef HAVE_IP_DAC_M3M4_V1 /* No DAC IPv1 */ - -/* Register Offsets *********************************************************/ - -#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ -#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ -#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ -#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC channel 1 sample and hold time register */ -#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC channel 2 sample and hold time register */ -#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC sample and hold time register */ -#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC sample and hold refresh time register */ -#define STM32_DAC_STR1_OFFSET 0x0058 /* DAC channel 1 sawtooth register */ -#define STM32_DAC_STR2_OFFSET 0x005c /* DAC channel 2 sawtooth register */ -#define STM32_DAC_STMODR_OFFSET 0x0060 /* DAC sawtooth mode register */ - -/* Register Addresses *******************************************************/ - -#ifdef CONFIG_STM32_HAVE_DAC1 -/* DAC1 */ - -# define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET) -# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE + STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE + STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE + STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE + STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE + STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE + STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE + STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE + STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE + STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE + STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC1_DOR1 (STM32_DAC1_BASE + STM32_DAC_DOR1_OFFSET) -# define STM32_DAC1_DOR2 (STM32_DAC1_BASE + STM32_DAC_DOR2_OFFSET) -# define STM32_DAC1_SR (STM32_DAC1_BASE + STM32_DAC_SR_OFFSET) -# define STM32_DAC1_CCR (STM32_DAC1_BASE + STM32_DAC_CCR_OFFSET) -# define STM32_DAC1_MCR (STM32_DAC1_BASE + STM32_DAC_MCR_OFFSET) -# define STM32_DAC1_SHSR1 (STM32_DAC1_BASE + STM32_DAC_SHSR1_OFFSET) -# define STM32_DAC1_SHSR2 (STM32_DAC1_BASE + STM32_DAC_SHSR2_OFFSET) -# define STM32_DAC1_SHHR (STM32_DAC1_BASE + STM32_DAC_SHHR_OFFSET) -# define STM32_DAC1_SHRR (STM32_DAC1_BASE + STM32_DAC_SHRR_OFFSET) -# define STM32_DAC1_STR1 (STM32_DAC1_BASE + STM32_DAC_STR1_OFFSET) -# define STM32_DAC1_STR2 (STM32_DAC1_BASE + STM32_DAC_STR2_OFFSET) -# define STM32_DAC1_STMODR (STM32_DAC1_BASE + STM32_DAC_STMODR_OFFSET) - -#endif /* CONFIG_STM32_HAVE_DAC1 */ - -#ifdef CONFIG_STM32_HAVE_DAC2 -/* DAC2 */ - -# define STM32_DAC2_CR (STM32_DAC2_BASE + STM32_DAC_CR_OFFSET) -# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE + STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE + STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE + STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE + STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE + STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE + STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE + STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE + STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE + STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE + STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC2_DOR1 (STM32_DAC2_BASE + STM32_DAC_DOR1_OFFSET) -# define STM32_DAC2_DOR2 (STM32_DAC2_BASE + STM32_DAC_DOR2_OFFSET) -# define STM32_DAC2_SR (STM32_DAC2_BASE + STM32_DAC_SR_OFFSET) -# define STM32_DAC2_CCR (STM32_DAC2_BASE + STM32_DAC_CCR_OFFSET) -# define STM32_DAC2_MCR (STM32_DAC2_BASE + STM32_DAC_MCR_OFFSET) -# define STM32_DAC2_SHSR1 (STM32_DAC2_BASE + STM32_DAC_SHSR1_OFFSET) -# define STM32_DAC2_SHSR2 (STM32_DAC2_BASE + STM32_DAC_SHSR2_OFFSET) -# define STM32_DAC2_SHHR (STM32_DAC2_BASE + STM32_DAC_SHHR_OFFSET) -# define STM32_DAC2_SHRR (STM32_DAC2_BASE + STM32_DAC_SHRR_OFFSET) -# define STM32_DAC2_STR1 (STM32_DAC2_BASE + STM32_DAC_STR1_OFFSET) -# define STM32_DAC2_STR2 (STM32_DAC2_BASE + STM32_DAC_STR2_OFFSET) -# define STM32_DAC2_STMODR (STM32_DAC2_BASE + STM32_DAC_STMODR_OFFSET) - -#endif /* CONFIG_STM32_HAVE_DAC2 */ - -#ifdef CONFIG_STM32_HAVE_DAC3 -/* DAC3 */ - -# define STM32_DAC3_CR (STM32_DAC3_BASE + STM32_DAC_CR_OFFSET) -# define STM32_DAC3_SWTRIGR (STM32_DAC3_BASE + STM32_DAC_SWTRIGR_OFFSET) -# define STM32_DAC3_DHR12R1 (STM32_DAC3_BASE + STM32_DAC_DHR12R1_OFFSET) -# define STM32_DAC3_DHR12L1 (STM32_DAC3_BASE + STM32_DAC_DHR12L1_OFFSET) -# define STM32_DAC3_DHR8R1 (STM32_DAC3_BASE + STM32_DAC_DHR8R1_OFFSET) -# define STM32_DAC3_DHR12R2 (STM32_DAC3_BASE + STM32_DAC_DHR12R2_OFFSET) -# define STM32_DAC3_DHR12L2 (STM32_DAC3_BASE + STM32_DAC_DHR12L2_OFFSET) -# define STM32_DAC3_DHR8R2 (STM32_DAC3_BASE + STM32_DAC_DHR8R2_OFFSET) -# define STM32_DAC3_DHR12RD (STM32_DAC3_BASE + STM32_DAC_DHR12RD_OFFSET) -# define STM32_DAC3_DHR12LD (STM32_DAC3_BASE + STM32_DAC_DHR12LD_OFFSET) -# define STM32_DAC3_DHR8RD (STM32_DAC3_BASE + STM32_DAC_DHR8RD_OFFSET) -# define STM32_DAC3_DOR1 (STM32_DAC3_BASE + STM32_DAC_DOR1_OFFSET) -# define STM32_DAC3_DOR2 (STM32_DAC3_BASE + STM32_DAC_DOR2_OFFSET) -# define STM32_DAC3_SR (STM32_DAC3_BASE + STM32_DAC_SR_OFFSET) -# define STM32_DAC3_CCR (STM32_DAC3_BASE + STM32_DAC_CCR_OFFSET) -# define STM32_DAC3_MCR (STM32_DAC3_BASE + STM32_DAC_MCR_OFFSET) -# define STM32_DAC3_SHSR1 (STM32_DAC3_BASE + STM32_DAC_SHSR1_OFFSET) -# define STM32_DAC3_SHSR2 (STM32_DAC3_BASE + STM32_DAC_SHSR2_OFFSET) -# define STM32_DAC3_SHHR (STM32_DAC3_BASE + STM32_DAC_SHHR_OFFSET) -# define STM32_DAC3_SHRR (STM32_DAC3_BASE + STM32_DAC_SHRR_OFFSET) -# define STM32_DAC3_STR1 (STM32_DAC3_BASE + STM32_DAC_STR1_OFFSET) -# define STM32_DAC3_STR2 (STM32_DAC3_BASE + STM32_DAC_STR2_OFFSET) -# define STM32_DAC3_STMODR (STM32_DAC3_BASE + STM32_DAC_STMODR_OFFSET) - -#endif /* CONFIG_STM32_HAVE_DAC3 */ - -/* Register Bitfield Definitions ********************************************/ - -/* DAC control register (CR) */ - -/* These definitions may be used for 16-bit values of either channel: Leave - * as-is for use with DAC channel 1 or shift left by 16 for use with DAC - * channel 2. - */ - -#define DAC_CR_EN (1 << 0) /* Bit 0: DAC channel enable */ -#define DAC_CR_TEN (1 << 1) /* Bit 2: DAC channel trigger enable */ -#define DAC_CR_TSEL_SHIFT (2) /* Bits 2-5: DAC channel trigger selection */ -#define DAC_CR_TSEL_MASK (0xf << DAC_CR_TSEL_SHIFT) /* Possible values for TSEL follow: */ -# define DAC_CR_TSEL_SW (0x0 << DAC_CR_TSEL_SHIFT) /* SWTRIG1 */ -# define DAC_CR_TSEL_TIM8 (0x1 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg1 - TIM8_TRGO */ -# define DAC_CR_TSEL_TIM7 (0x2 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg2 - TIM7_TRGO */ -# define DAC_CR_TSEL_TIM15 (0x3 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg3 - TIM15_TRGO */ -# define DAC_CR_TSEL_TIM2 (0x4 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg4 - TIM2_TRGO */ -# define DAC_CR_TSEL_TIM4 (0x5 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg5 - TIM4_TRGO */ -# define DAC_CR_TSEL_EXTI9 (0x6 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg6 - EXTI9 */ -# define DAC_CR_TSEL_TIM6 (0x7 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg7 - TIM6_TRGO */ -# define DAC_CR_TSEL_TIM3 (0x8 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg8 - TIM3_TRGO */ -# define DAC_CR_TSEL_HRT1RTRG1 (0x9 << DAC_CR_TSEL_SHIFT) /* dac_chx_trg9 - htrim_dac_reset_trg1 */ -# define DAC_CR_TSEL_HRT1RTRG2 (0xa << DAC_CR_TSEL_SHIFT) /* dac_chx_trg10 - htrim_dac_reset_trg2 */ -# define DAC_CR_TSEL_HRT1RTRG3 (0xb << DAC_CR_TSEL_SHIFT) /* dac_chx_trg11 - htrim_dac_reset_trg3 */ -# define DAC_CR_TSEL_HRT1RTRG4 (0xc << DAC_CR_TSEL_SHIFT) /* dac_chx_trg12 - htrim_dac_reset_trg4 */ -# define DAC_CR_TSEL_HRT1RTRG5 (0xd << DAC_CR_TSEL_SHIFT) /* dac_chx_trg13 - htrim_dac_reset_trg5 */ -# define DAC_CR_TSEL_HRT1RTRG6 (0xe << DAC_CR_TSEL_SHIFT) /* dac_chx_trg14 - htrim_dac_reset_trg6 */ -# define DAC_CR_TSEL_HRT1TRG1 (0xf << DAC_CR_TSEL_SHIFT) /* dac_chx_trg15 - htrim_dac_trg1 */ -#define DAC_CR_WAVE_SHIFT (6) /* Bits 6-7: DAC channel noise/triangle wave generation enable */ -#define DAC_CR_WAVE_MASK (0x3 << DAC_CR_WAVE_SHIFT) /* Possible values for WAVE follow: */ -# define DAC_CR_WAVE_DISABLED (0x0 << DAC_CR_WAVE_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE_NOISE (0x1 << DAC_CR_WAVE_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE_TRIANGLE (0x2 << DAC_CR_WAVE_SHIFT) /* Triangle wave generation enabled */ -# define DAC_CR_WAVE_SAWTOOTH (0x3 << DAC_CR_WAVE_SHIFT) /* Sawtooth wave generation enabled */ -#define DAC_CR_MAMP_SHIFT (8) /* Bits 8-11: DAC channel mask/amplitude selector */ -#define DAC_CR_MAMP_MASK (0xf << DAC_CR_MAMP_SHIFT) /* Possible values for MASK follow: */ -# define DAC_CR_MAMP_BIT0 (0x0 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ -# define DAC_CR_MAMP_BITS1_0 (0x1 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ -# define DAC_CR_MAMP_BITS2_0 (0x2 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ -# define DAC_CR_MAMP_BITS3_0 (0x3 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ -# define DAC_CR_MAMP_BITS4_0 (0x4 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ -# define DAC_CR_MAMP_BITS5_0 (0x5 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ -# define DAC_CR_MAMP_BITS6_0 (0x6 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ -# define DAC_CR_MAMP_BITS7_0 (0x7 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ -# define DAC_CR_MAMP_BITS8_0 (0x8 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ -# define DAC_CR_MAMP_BITS9_0 (0x9 << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ -# define DAC_CR_MAMP_BITS10_0 (0xa << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ -# define DAC_CR_MAMP_BITS11_0 (0xb << DAC_CR_MAMP_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ -# define DAC_CR_MAMP_AMP1 (0x0 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ -# define DAC_CR_MAMP_AMP3 (0x1 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ -# define DAC_CR_MAMP_AMP7 (0x2 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ -# define DAC_CR_MAMP_AMP15 (0x3 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ -# define DAC_CR_MAMP_AMP31 (0x4 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ -# define DAC_CR_MAMP_AMP63 (0x5 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ -# define DAC_CR_MAMP_AMP127 (0x6 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ -# define DAC_CR_MAMP_AMP255 (0x7 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ -# define DAC_CR_MAMP_AMP511 (0x8 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ -# define DAC_CR_MAMP_AMP1023 (0x9 << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ -# define DAC_CR_MAMP_AMP2047 (0xa << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ -# define DAC_CR_MAMP_AMP4095 (0xb << DAC_CR_MAMP_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ -#define DAC_CR_DMAEN (1 << 12) /* Bit 12: DAC channel DMA enable */ -#define DAC_CR_DMAUDRIE (1 << 13) /* Bit 13: DAC channel DMA underrun interrupt enable */ -#define DAC_CR_CEN (1 << 14) /* Bit 14: DAC channel calibration enable */ - -/* These definitions may be used with the full, 32-bit register */ - -#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */ -#define DAC_CR_TEN1 (1 << 1) /* Bit 2: DAC channel 1 trigger enable */ -#define DAC_CR_TSEL1_SHIFT (2) /* Bits 2-5: DAC channel 1 trigger selection */ -#define DAC_CR_TSEL1_MASK (0xf << DAC_CR_TSEL1_SHIFT) /* Possible values for TSEL1 follow: */ -# define DAC_CR_TSEL1_SW (0x0 << DAC_CR_TSEL1_SHIFT) /* SWTRIG1 */ -# define DAC_CR_TSEL1_TIM8 (0x1 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg1 - TIM8_TRGO */ -# define DAC_CR_TSEL1_TIM7 (0x2 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg2 - TIM7_TRGO */ -# define DAC_CR_TSEL1_TIM15 (0x3 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg3 - TIM15_TRGO */ -# define DAC_CR_TSEL1_TIM2 (0x4 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg4 - TIM2_TRGO */ -# define DAC_CR_TSEL1_TIM4 (0x5 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg5 - TIM4_TRGO */ -# define DAC_CR_TSEL1_EXTI9 (0x6 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg6 - EXTI9 */ -# define DAC_CR_TSEL1_TIM6 (0x7 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg7 - TIM6_TRGO */ -# define DAC_CR_TSEL1_TIM3 (0x8 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg8 - TIM3_TRGO */ -# define DAC_CR_TSEL1_HRT1RTRG1 (0x9 << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg9 - htrim_dac_reset_trg1 */ -# define DAC_CR_TSEL1_HRT1RTRG2 (0xa << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg10 - htrim_dac_reset_trg2 */ -# define DAC_CR_TSEL1_HRT1RTRG3 (0xb << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg11 - htrim_dac_reset_trg3 */ -# define DAC_CR_TSEL1_HRT1RTRG4 (0xc << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg12 - htrim_dac_reset_trg4 */ -# define DAC_CR_TSEL1_HRT1RTRG5 (0xd << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg13 - htrim_dac_reset_trg5 */ -# define DAC_CR_TSEL1_HRT1RTRG6 (0xe << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg14 - htrim_dac_reset_trg6 */ -# define DAC_CR_TSEL1_HRT1TRG1 (0xf << DAC_CR_TSEL1_SHIFT) /* dac_ch1_trg15 - htrim_dac_trg1 */ -#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation enable */ -#define DAC_CR_WAVE1_MASK (0x3 << DAC_CR_WAVE1_SHIFT) /* Possible values for WAVE1 follow: */ -# define DAC_CR_WAVE1_DISABLED (0x0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE1_TRIANGLE (0x2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */ -# define DAC_CR_WAVE1_SAWTOOTH (0x3 << DAC_CR_WAVE1_SHIFT) /* Sawtooth wave generation enabled */ -#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */ -#define DAC_CR_MAMP1_MASK (0xf << DAC_CR_MAMP1_SHIFT) /* Possible values for MASK1 follow: */ -# define DAC_CR_MAMP1_BIT0 (0x0 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ -# define DAC_CR_MAMP1_BITS1_0 (0x1 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ -# define DAC_CR_MAMP1_BITS2_0 (0x2 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ -# define DAC_CR_MAMP1_BITS3_0 (0x3 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ -# define DAC_CR_MAMP1_BITS4_0 (0x4 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ -# define DAC_CR_MAMP1_BITS5_0 (0x5 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ -# define DAC_CR_MAMP1_BITS6_0 (0x6 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ -# define DAC_CR_MAMP1_BITS7_0 (0x7 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ -# define DAC_CR_MAMP1_BITS8_0 (0x8 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ -# define DAC_CR_MAMP1_BITS9_0 (0x9 << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ -# define DAC_CR_MAMP1_BITS10_0 (0xa << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ -# define DAC_CR_MAMP1_BITS11_0 (0xb << DAC_CR_MAMP1_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ -# define DAC_CR_MAMP1_AMP1 (0x0 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ -# define DAC_CR_MAMP1_AMP3 (0x1 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ -# define DAC_CR_MAMP1_AMP7 (0x2 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ -# define DAC_CR_MAMP1_AMP15 (0x3 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ -# define DAC_CR_MAMP1_AMP31 (0x4 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ -# define DAC_CR_MAMP1_AMP63 (0x5 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ -# define DAC_CR_MAMP1_AMP127 (0x6 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ -# define DAC_CR_MAMP1_AMP255 (0x7 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ -# define DAC_CR_MAMP1_AMP511 (0x8 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ -# define DAC_CR_MAMP1_AMP1023 (0x9 << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ -# define DAC_CR_MAMP1_AMP2047 (0xa << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ -# define DAC_CR_MAMP1_AMP4095 (0xb << DAC_CR_MAMP1_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ -#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */ -#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun interrupt enable */ -#define DAC_CR_CEN1 (1 << 14) /* Bit 14: DAC channel 1 calibration enable */ - -#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */ -#define DAC_CR_TEN2 (1 << 17) /* Bit 17: DAC channel 2 trigger enable */ -#define DAC_CR_TSEL2_SHIFT (18) /* Bits 18-21: DAC channel 2 trigger selection */ -#define DAC_CR_TSEL2_MASK (0xf << DAC_CR_TSEL2_SHIFT) /* Possible values for TSEL2 follow: */ -# define DAC_CR_TSEL2_SW (0x0 << DAC_CR_TSEL2_SHIFT) /* SWTRIG2 */ -# define DAC_CR_TSEL2_TIM8 (0x1 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg1 - TIM8_TRGO */ -# define DAC_CR_TSEL2_TIM7 (0x2 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg2 - TIM7_TRGO */ -# define DAC_CR_TSEL2_TIM15 (0x3 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg3 - TIM15_TRGO */ -# define DAC_CR_TSEL2_TIM2 (0x4 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg4 - TIM2_TRGO */ -# define DAC_CR_TSEL2_TIM4 (0x5 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg5 - TIM4_TRGO */ -# define DAC_CR_TSEL2_EXTI9 (0x6 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg6 - EXTI9 */ -# define DAC_CR_TSEL2_TIM6 (0x7 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg7 - TIM6_TRGO */ -# define DAC_CR_TSEL2_TIM3 (0x8 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg8 - TIM3_TRGO */ -# define DAC_CR_TSEL2_HRT1RTRG1 (0x9 << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg9 - htrim_dac_reset_trg1 */ -# define DAC_CR_TSEL2_HRT1RTRG2 (0xa << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg10 - htrim_dac_reset_trg2 */ -# define DAC_CR_TSEL2_HRT1RTRG3 (0xb << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg11 - htrim_dac_reset_trg3 */ -# define DAC_CR_TSEL2_HRT1RTRG4 (0xc << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg12 - htrim_dac_reset_trg4 */ -# define DAC_CR_TSEL2_HRT1RTRG5 (0xd << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg13 - htrim_dac_reset_trg5 */ -# define DAC_CR_TSEL2_HRT1RTRG6 (0xe << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg14 - htrim_dac_reset_trg6 */ -# define DAC_CR_TSEL2_HRT1TRG1 (0xf << DAC_CR_TSEL2_SHIFT) /* dac_ch2_trg15 - htrim_dac_trg1 */ -#define DAC_CR_WAVE2_SHIFT (22) /* Bits 22-23: DAC channel 2 noise/triangle wave generation enable */ -#define DAC_CR_WAVE2_MASK (0x3 << DAC_CR_WAVE2_SHIFT) /* Possible values for WAVE2 follow: */ -# define DAC_CR_WAVE2_DISABLED (0x0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */ -# define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */ -# define DAC_CR_WAVE2_TRIANGLE (0x2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */ -# define DAC_CR_WAVE2_SAWTOOTH (0x3 << DAC_CR_WAVE2_SHIFT) /* Sawtooth wave generation enabled */ -#define DAC_CR_MAMP2_SHIFT (24) /* Bits 24-27: DAC channel 2 mask/amplitude selector */ -#define DAC_CR_MAMP2_MASK (0xf << DAC_CR_MAMP2_SHIFT) /* Possible values for MASK2 follow: */ -# define DAC_CR_MAMP2_BIT0 (0x0 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bit 0 of LFSR */ -# define DAC_CR_MAMP2_BITS1_0 (0x1 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[1:0] of LFSR */ -# define DAC_CR_MAMP2_BITS2_0 (0x2 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[2:0] of LFSR */ -# define DAC_CR_MAMP2_BITS3_0 (0x3 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[3:0] of LFSR */ -# define DAC_CR_MAMP2_BITS4_0 (0x4 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[4:0] of LFSR */ -# define DAC_CR_MAMP2_BITS5_0 (0x5 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[5:0] of LFSR */ -# define DAC_CR_MAMP2_BITS6_0 (0x6 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[6:0] of LFSR */ -# define DAC_CR_MAMP2_BITS7_0 (0x7 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[7:0] of LFSR */ -# define DAC_CR_MAMP2_BITS8_0 (0x8 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[8:0] of LFSR */ -# define DAC_CR_MAMP2_BITS9_0 (0x9 << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[9:0] of LFSR */ -# define DAC_CR_MAMP2_BITS10_0 (0xa << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[10:0] of LFSR */ -# define DAC_CR_MAMP2_BITS11_0 (0xb << DAC_CR_MAMP2_SHIFT) /* In wave generation mode, unmask bits[11:0] of LFSR */ -# define DAC_CR_MAMP2_AMP1 (0x0 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 1 */ -# define DAC_CR_MAMP2_AMP3 (0x1 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 3 */ -# define DAC_CR_MAMP2_AMP7 (0x2 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 7 */ -# define DAC_CR_MAMP2_AMP15 (0x3 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 15 */ -# define DAC_CR_MAMP2_AMP31 (0x4 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 31 */ -# define DAC_CR_MAMP2_AMP63 (0x5 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 63 */ -# define DAC_CR_MAMP2_AMP127 (0x6 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 127 */ -# define DAC_CR_MAMP2_AMP255 (0x7 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 255 */ -# define DAC_CR_MAMP2_AMP511 (0x8 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 511 */ -# define DAC_CR_MAMP2_AMP1023 (0x9 << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 1023 */ -# define DAC_CR_MAMP2_AMP2047 (0xa << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 2047 */ -# define DAC_CR_MAMP2_AMP4095 (0xb << DAC_CR_MAMP2_SHIFT) /* In triangle generation mode, triangle amplitude 4095 */ -#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */ -#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun interrupt enable */ -#define DAC_CR_CEN2 (1 << 30) /* Bit 30: DAC channel 2 calibration enable */ - -/* DAC software trigger register (SWTRGR) */ - -#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n) - 1)) /* Software trigger */ -#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */ -#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */ - -#define DAC_SWTRIGR_SWTRIGB(n) (1 << ((n) - 1)) /* Software trigger B for sawtooth generation */ -#define DAC_SWTRIGR_SWTRIGB1 (1 << 0) /* Bit 16: DAC channel 1 software trigger B for sawtooth increment */ -#define DAC_SWTRIGR_SWTRIGB2 (1 << 1) /* Bit 17: DAC channel 2 software trigger B for sawtooth increment */ - -/* DAC channels 1/2 12-bit right-aligned data holding register - * (DHR12R1, DHR12R2) - */ - -#define DAC_DHR12R_MASK_SHIFT (0) /* DAC channel 1/2 right-aligned data */ -#define DAC_DHR12R_MASK (0xfff << DAC_DHR12R_MASK_SHIFT) -#define DAC_DHR12R_MASKB_SHIFT (16) /* DAC channel 1/2 right-aligned data B for Double Data Mode */ -#define DAC_DHR12R_MASKB (0xfff << DAC_DHR12R_MASKB_SHIFT) - -/* DAC channel 1/2 12-bit left aligned data holding register - * (DHR12L1, DHR12L2) - */ - -#define DAC_DHR12L_MASK_SHIFT (4) /* DAC channel 1/2 left-aligned data */ -#define DAC_DHR12L_MASK (0xfff << DAC_DHR12L_MASK_SHIFT) -#define DAC_DHR12L_MASKB_SHIFT (20) /* DAC channel 1/2 left-aligned data B for Double Data Mode */ -#define DAC_DHR12L_MASKB (0xfff << DAC_DHR12L_MASKB_SHIFT) - -/* DAC channel 1/2 8-bit right aligned data holding register - * (DHR8R1, DHR8R2) - */ - -#define DAC_DHR8R_MASK_SHIFT (0) /* DAC channel 1/2 right-aligned data */ -#define DAC_DHR8R_MASK (0xff << DAC_DHR8R_MASK_SHIFT) -#define DAC_DHR8R_MASKB_SHIFT (8) /* DAC channel 1/2 right-aligned data B for Double Data Mode */ -#define DAC_DHR8R_MASKB (0xff << DAC_DHR8R_MASKB_SHIFT) - -/* Dual DAC 12-bit right-aligned data holding register (DHR12RD) */ - -#define DAC_DHR12RD_DACC_SHIFT(n) (((n) - 1) << 4) -#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n)) - -#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC1_SHIFT) -#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */ -#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT) - -/* Dual DAC 12-bit left-aligned data holding register (DHR12LD) */ - -#define DAC_DHR12LD_DACC_SHIFT(n) ((((n) - 1) << 4) + 4) -#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n)) - -#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT) -#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */ -#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT) - -/* DUAL DAC 8-bit right aligned data holding register (DHR8RD) */ - -#define DAC_DHR8RD_DACC_SHIFT(n) (((n) - 1) << 3) -#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n)) - -#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT) -#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */ -#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT) - -/* DAC channel 1/2 data output register (DOR1, DOR2) */ - -#define DAC_DOR_MASK_SHIFT (0) /* DAC channel 1/2 data output */ -#define DAC_DOR_MASK (0xfff << DAC_DOR_MASK_SHIFT) -#define DAC_DOR_MASKB_SHIFT (16) /* DAC channel 1/2 data output B for Double Data Mode */ -#define DAC_DOR_MASKB (0xfff << DAC_DOR_MASKB_SHIFT) - -/* DAC status register (SR) */ - -#define DAC_SR_DACRDY(n) (1 << ((((n) - 1) << 4) + 11)) -#define DAC_SR_DAC1RDY (1 << 11) /* Bit 13: DAC channel 1 ready status bit */ -#define DAC_SR_DAC2RDY (1 << 27) /* Bit 27: DAC channel 2 ready status bit */ - -#define DAC_SR_DORSTAT(n) (1 << ((((n) - 1) << 4) + 12)) -#define DAC_SR_DORSTAT1 (1 << 12) /* Bit 13: DAC channel 1 output register status bit */ -#define DAC_SR_DORSTAT2 (1 << 28) /* Bit 29: DAC channel 2 output register status bit */ - -#define DAC_SR_DMAUDR(n) (1 << ((((n) - 1) << 4) + 13)) -#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ -#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ - -#define DAC_SR_CAL_FLAG(n) (1 << ((((n) - 1) << 4) + 14)) -#define DAC_SR_CAL_FLAG1 (1 << 14) /* Bit 13: DAC channel 1 calibration offset status */ -#define DAC_SR_CAL_FLAG2 (1 << 30) /* Bit 29: DAC channel 2 calibration offset status */ - -#define DAC_SR_BWST(n) (1 << ((((n) - 1) << 4) + 15)) -#define DAC_SR_BWST1 (1 << 15) /* Bit 13: DAC channel 1 busy writing sample time flag */ -#define DAC_SR_BWST2 (1 << 31) /* Bit 29: DAC channel 2 busy writing sample time flag */ - -/* DAC calibration control register (CCR) */ - -#define DAC_CCR_OTRIM_SHIFT(n) (((n) - 1) << 4) -#define DAC_CCR_OTRIM_MASK(n) (0x1f << DAC_CCR_OTRIM_SHIFT(n)) - -#define DAC_CCR_OTRIM1_SHIFT (0) /* DAC channel 1 offset trimming value */ -#define DAC_CCR_OTRIM1_MASK (0x1f << DAC_CCR_OTRIM1_SHIFT) -#define DAC_CCR_OTRIM2_SHIFT (16) /* DAC channel 2 offset trimming value */ -#define DAC_CCR_OTRIM2_MASK (0x1f << DAC_CCR_OTRIM2_SHIFT) - -/* DAC mode control register (MCR) */ - -#define DAC_MCR_MODE_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 mode */ -#define DAC_MCR_MODE_MASK(n) (0x7 << DAC_MCR_MODE_SHIFT(n)) -# define DAC_MCR_MODE_0(n) (0x0 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE_1(n) (0x1 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE_2(n) (0x2 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to external pin with buffer disabled */ -# define DAC_MCR_MODE_3(n) (0x3 << DAC_MCR_MODE_SHIFT(n)) /* Normal mode, connect to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE_4(n) (0x4 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE_5(n) (0x5 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE_6(n) (0x6 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE_7(n) (0x7 << DAC_MCR_MODE_SHIFT(n)) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ - -#define DAC_MCR_MODE1_SHIFT (0) /* DAC channel 1 mode */ -#define DAC_MCR_MODE1_MASK (0x7 << DAC_MCR_MODE1_SHIFT) -# define DAC_MCR_MODE1_0 (0x0 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE1_1 (0x1 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE1_2 (0x2 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to external pin with buffer disabled */ -# define DAC_MCR_MODE1_3 (0x3 << DAC_MCR_MODE1_SHIFT) /* Normal mode, connect to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE1_4 (0x4 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE1_5 (0x5 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE1_6 (0x6 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE1_7 (0x7 << DAC_MCR_MODE1_SHIFT) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ - -#define DAC_MCR_MODE2_SHIFT (16) /* DAC channel 2 mode */ -#define DAC_MCR_MODE2_MASK (0x7 << DAC_MCR_MODE2_SHIFT) -# define DAC_MCR_MODE2_0 (0x0 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE2_1 (0x1 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE2_2 (0x2 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to external pin with buffer disabled */ -# define DAC_MCR_MODE2_3 (0x3 << DAC_MCR_MODE2_SHIFT) /* Normal mode, connect to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE2_4 (0x4 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin with buffer enabled */ -# define DAC_MCR_MODE2_5 (0x5 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer enabled */ -# define DAC_MCR_MODE2_6 (0x6 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to external pin and to on-chip peripherals with buffer disabled */ -# define DAC_MCR_MODE2_7 (0x7 << DAC_MCR_MODE2_SHIFT) /* Sample & hold mode, connect to on-chip peripherals with buffer disabled */ - -#define DAC_MCR_DMADOUBLE(n) (1 << ((((n) - 1) << 4) + 8)) /* DAC Channel 1/2 DMA double data mode */ -#define DAC_MCR_DMADOUBLE1 (1 << 8) /* DAC Channel 1 DMA double data mode */ -#define DAC_MCR_DMADOUBLE2 (1 << 24) /* DAC Channel 2 DMA double data mode */ - -#define DAC_MCR_SINFORMAT(n) (1 << ((((n) - 1) << 4) + 9)) /* DAC Channel 1/2 enable signed format */ -#define DAC_MCR_SINFORMAT1 (1 << 9) /* DAC Channel 1 enable signed format */ -#define DAC_MCR_SINFORMAT2 (1 << 25) /* DAC Channel 2 enable signed format */ - -#define DAC_MCR_HFSEL_SHIFT (14) /* High-frequency interface mode selection */ -#define DAC_MCR_HFSEL_MASK (0x3 << DAC_MCR_HFSEL_SHIFT) -# define DAC_MCR_HFSEL_DISABLED (0x0 << DAC_MCR_HFSEL_SHIFT) /* High-frequency disabled */ -# define DAC_MCR_HFSEL_AHB_80MHz (0x1 << DAC_MCR_HFSEL_SHIFT) /* High-frequency for AHB > 80 MHz */ -# define DAC_MCR_HFSEL_AHB_160MHz (0x2 << DAC_MCR_HFSEL_SHIFT) /* High-frequency for AHB > 160 MHz */ -# define DAC_MCR_HFSEL_RESERVED (0x3 << DAC_MCR_HFSEL_SHIFT) /* Reserved */ - -/* DAC channel 1/2 sample and hold sample time register (SHSR1, SHSR2) */ - -#define DAC_SHSR_TSAMPLE_SHIFT (0) /* DAC channel 1/2 Sample phase time = (TSAMPLE + 1) * LSI/LSE clock period */ -#define DAC_SHSR_TSAMPLE_MASK (0x3ff << DAC_SHSR1_TSAMPLE1_SHIFT) - -/* DAC sample and hold time register (SHHR) */ - -#define DAC_SHHR_THOLD_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 Hold time = THOLD * LSI/LSE clock period */ -#define DAC_SHHR_THOLD_MASK(n) (0x3ff << DAC_SHHR_THOLD_SHIFT(n)) - -#define DAC_SHHR_THOLD1_SHIFT (0) /* DAC channel 1 Hold time */ -#define DAC_SHHR_THOLD1_MASK (0x3ff << DAC_SHHR_THOLD1_SHIFT) -#define DAC_SHHR_THOLD2_SHIFT (16) /* DAC channel 2 Hold time */ -#define DAC_SHHR_THOLD2_MASK (0x3ff << DAC_SHHR_THOLD2_SHIFT) - -/* DAC sample and hold refresh time register (SHRR) */ - -#define DAC_SHHR_TREFRESH_SHIFT(n) (((n) - 1) << 4) /* DAC channel 1/2 Refresh time = TREFRESH * LSI/LSE clock period */ -#define DAC_SHHR_TREFRESH_MASK(n) (0xff << DAC_SHHR_THOLD_SHIFT(n)) - -#define DAC_SHRR_TREFRESH1_SHIFT (0) /* DAC channel 1 Refresh time */ -#define DAC_SHRR_TREFRESH1_MASK (0xff << DAC_SHRR_TREFRESH1_SHIFT) -#define DAC_SHRR_TREFRESH2_SHIFT (16) /* DAC channel 2 Refresh time */ -#define DAC_SHRR_TREFRESH2_MASK (0xff << DAC_SHRR_TREFRESH2_SHIFT) - -/* DAC channel 1/2 sawtooth register register (STR1, STR2) */ - -#define DAC_STR_STRSTDATA_SHIFT (0) /* DAC channel 1 Sawtooth starting value */ -#define DAC_STR_STRSTDATA_MASK (0xfff << DAC_STR1_STRSTDATA1_SHIFT) -#define DAC_STR_STDIR (1 << 12) /* DAC channel 1 Sawtooth direction setting */ -#define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */ -#define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h deleted file mode 100644 index f3cb64060db67..0000000000000 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0x1ff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* L15 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */ diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h deleted file mode 100644 index 66b91b72e864a..0000000000000 --- a/arch/arm/src/stm32/stm32.h +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_H -#define __ARCH_ARM_SRC_STM32_STM32_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "arm_internal.h" - -/* Peripherals **************************************************************/ - -#include "chip.h" -#include "stm32_adc.h" -#include "stm32_can.h" -#include "stm32_comp.h" -#include "stm32_dbgmcu.h" -#include "stm32_dma.h" -#include "stm32_dac.h" -#include "stm32_exti.h" -#include "stm32_flash.h" -#include "stm32_fmc.h" -#include "stm32_fsmc.h" -#include "stm32_gpio.h" -#include "stm32_i2c.h" -#include "stm32_ltdc.h" -#include "stm32_opamp.h" -#include "stm32_pwr.h" -#include "stm32_rcc.h" -#include "stm32_rtc.h" -#include "stm32_sdio.h" -#include "stm32_spi.h" -#include "stm32_i2s.h" -#include "stm32_tim.h" -#include "stm32_uart.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) -# include "stm32_usbdev.h" -#endif -#include "stm32_wdg.h" -#include "stm32_lowputc.h" -#include "stm32_eth.h" - -#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32/stm32_lowputc.h b/arch/arm/src/stm32/stm32_lowputc.h deleted file mode 100644 index 76629be9c542d..0000000000000 --- a/arch/arm/src/stm32/stm32_lowputc.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.h b/arch/arm/src/stm32/stm32_mpuinit.h deleted file mode 100644 index f4af906ef4e2c..0000000000000 --- a/arch/arm/src/stm32/stm32_mpuinit.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H -#define __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mpuinitialize - * - * Description: - * Configure the MPU to permit user-space access to only unrestricted MCU - * resources. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void stm32_mpuinitialize(void); -#else -# define stm32_mpuinitialize() -#endif - -/**************************************************************************** - * Name: stm32_mpu_uheap - * - * Description: - * Map the user heap region. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void stm32_mpu_uheap(uintptr_t start, size_t size); -#else -# define stm32_mpu_uheap(start,size) -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32/stm32_pm.h b/arch/arm/src/stm32/stm32_pm.h deleted file mode 100644 index 7d66d3b209f11..0000000000000 --- a/arch/arm/src/stm32/stm32_pm.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pm.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PM_H -#define __ARCH_ARM_SRC_STM32_STM32_PM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmstop - * - * Description: - * Enter STOP mode. - * - * Input Parameters: - * lpds - true: To further reduce power consumption in Stop mode, put the - * internal voltage regulator in low-power mode using the LPDS bit - * of the Power control register (PWR_CR). - * - * Returned Value: - * Zero means that the STOP was successfully entered and the system has - * been re-awakened. The internal voltage regulator is back to its - * original state. Otherwise, STOP mode did not occur and a negated - * errno value is returned to indicate the cause of the failure. - * - ****************************************************************************/ - -int stm32_pmstop(bool lpds); - -/**************************************************************************** - * Name: stm32_pmstandby - * - * Description: - * Enter STANDBY mode. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, this function will not return (STANDBY mode can only be - * terminated with a reset event). Otherwise, STANDBY mode did not occur - * and a negated errno value is returned to indicate the cause of the - * failure. - * - ****************************************************************************/ - -int stm32_pmstandby(void); - -/**************************************************************************** - * Name: stm32_pmsleep - * - * Description: - * Enter SLEEP mode. - * - * Input Parameters: - * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it - * exits the lowest priority ISR. - * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep - * mode as soon as WFI or WFE instruction is executed. - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pmsleep(bool sleeponexit); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c deleted file mode 100644 index 5d1c3715b6aaf..0000000000000 --- a/arch/arm/src/stm32/stm32_rcc.c +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" -#include "stm32_rtc.h" -#include "stm32_flash.h" -#include "stm32.h" -#include "stm32_waste.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, - "Configure BOARD_LOOPSPERMSEC to non-default value."); - -/* Allow up to 100 milliseconds for the high speed clock to become ready. - * that is a very long delay, but if the clock does not become ready we are - * hosed anyway. - */ - -#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include chip-specific clocking initialization logic */ - -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "stm32f10xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "stm32f20xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "stm32f30xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "stm32f37xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_rcc.c" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -# define STM32_RCC_XXX STM32_RCC_CSR -# define RCC_XXX_YYYRST RCC_CSR_RTCRST -#else -# define STM32_RCC_XXX STM32_RCC_BDCR -# define RCC_XXX_YYYRST RCC_BDCR_BDRST -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rcc_resetbkp - * - * Description: - * The RTC needs to reset the Backup Domain to change RTCSEL and resetting - * the Backup Domain renders to disabling the LSE as consequence. - * In order to avoid resetting the Backup Domain when we already - * configured LSE we will reset the Backup Domain early (here). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) -static inline void rcc_resetbkp(void) -{ - uint32_t regval; - - /* Check if the RTC is already configured */ - - stm32_pwr_initbkp(false); - - regval = getreg32(RTC_MAGIC_REG); - if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) - { - stm32_pwr_enablebkp(true); - - /* We might be changing RTCSEL - to ensure such changes work, we must - * reset the backup domain (having backed up the RTC_MAGIC token) - */ - - modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); - modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); - - stm32_pwr_enablebkp(false); - } -} -#else -# define rcc_resetbkp() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all peripherals enabled in the NuttX - * configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void) -{ - /* Make sure that we are starting in the reset state */ - - rcc_reset(); - - /* Reset backup domain if appropriate */ - - rcc_resetbkp(); - -#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif - - /* Enable peripheral clocking */ - - rcc_enableperipherals(); - -#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION - /* Enable I/O Compensation */ - - stm32_iocompensation(); -#endif -} - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings - * in board.h. This function is only available to support low-power - * modes of operation: When re-awakening from deep-sleep modes, it is - * necessary to re-enable/re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void) -{ -#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - - /* Invoke Board Custom Clock Configuration */ - - stm32_board_clockconfig(); - -#else - - /* Invoke standard, fixed clock configuration based on definitions - * in board.h - */ - - stm32_stdclockconfig(); - -#endif -} -#endif diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h deleted file mode 100644 index cfead6ee3e43b..0000000000000 --- a/arch/arm/src/stm32/stm32_rcc.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_rcc.h" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mco1config - * - * Description: - * Selects the clock source to output on MCO1 pin (PA8). PA8 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO1 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE, - * RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL} - * div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2, - * RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco1config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcoconfig - * - * Description: - * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. - * PA8 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO definitions from - * chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, - * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, - * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) -static inline void stm32_mcoconfig(uint32_t source) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO_MASK); - regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcodivconfig - * - * Description: - * Selects the clock source to output and clock divider on MC pin (PA4) for - * stm32l1xxx. PA4 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCOSEL definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK, - * RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK, - * RCC_CFGR_MCOSEL_HSECLK, RCC_CFGR_MCOSEL_PLLCLK, - * RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK} - * divider - One of the definitions for the RCC_CFGR_MCOPRE definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2, - * RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCOSEL_MASK); - regval |= (source & RCC_CFGR_MCOSEL_MASK); - regval &= ~(RCC_CFGR_MCOPRE_MASK); - regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mco2config - * - * Description: - * Selects the clock source to output on MCO2 pin (PC9). PC9 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO2 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S, - * RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL} - * div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2, - * RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco2config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all periperipherals enabled in the - * NuttX configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_board_clockconfig - * - * Description: - * Any STM32 board may replace the "standard" board clock configuration - * logic with its own, custom clock configuration logic. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32_board_clockconfig(void); -#endif - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings in - * board.h. - * This function is only available to support low-power modes of operation: - * When re-awakening from deep-sleep modes, it is necessary to re-enable/ - * re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void); -#endif - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32/stm32_start.h deleted file mode 100644 index 4d0e326dc491e..0000000000000 --- a/arch/arm/src/stm32/stm32_start.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_start.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H -#define __ARCH_ARM_SRC_STM32_STM32_START_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after - * clocking and memory have been configured but before caches have been - * enabled and before any devices have been initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.h b/arch/arm/src/stm32/stm32_userspace.h deleted file mode 100644 index 8cdb47e52ff37..0000000000000 --- a/arch/arm/src/stm32/stm32_userspace.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H -#define __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void stm32_userspace(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32f1/CMakeLists.txt b/arch/arm/src/stm32f1/CMakeLists.txt new file mode 100644 index 0000000000000..2126b9b6e336a --- /dev/null +++ b/arch/arm/src/stm32f1/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f1/Kconfig b/arch/arm/src/stm32f1/Kconfig new file mode 100644 index 0000000000000..a7281777268bc --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig @@ -0,0 +1,482 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F1 configuration" + +if ARCH_CHIP_STM32F1 + +choice + prompt "STM32F1 Chip Selection" + default ARCH_CHIP_STM32F103ZE + depends on ARCH_CHIP_STM32F1 + +config ARCH_CHIP_STM32F100C8 + bool "STM32F100C8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100CB + bool "STM32F100CB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100R8 + bool "STM32F100R8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RB + bool "STM32F100RB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RC + bool "STM32F100RC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RD + bool "STM32F100RD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RE + bool "STM32F100RE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100V8 + bool "STM32F100V8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VB + bool "STM32F100VB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VC + bool "STM32F100VC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VD + bool "STM32F100VD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VE + bool "STM32F100VE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F102CB + bool "STM32F102CB" + select STM32_STM32F10XX + select STM32F1_USBACCESSLINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103T8 + bool "STM32F103T8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103TB + bool "STM32F103TB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103C4 + bool "STM32F103C4" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_LOWDENSITY + +config ARCH_CHIP_STM32F103C8 + bool "STM32F103C8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103CB + bool "STM32F103CB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103R8 + bool "STM32F103R8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RB + bool "STM32F103RB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RC + bool "STM32F103RC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RD + bool "STM32F103RD" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RE + bool "STM32F103RE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RG + bool "STM32F103RG" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103V8 + bool "STM32F103V8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VB + bool "STM32F103VB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VC + bool "STM32F103VC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VE + bool "STM32F103VE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103ZE + bool "STM32F103ZE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105VB + bool "STM32F105VBT7" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105RB + bool "STM32F105RB" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F107VC + bool "STM32F107VC" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM4 + +endchoice + +endif + +config STM32_STM32F10XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY + select ARCH_CORTEXM3 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32F1_VALUELINE + bool + default n + select STM32_VALUELINE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY + +config STM32F1_CONNECTIVITYLINE + bool + default n + select STM32_CONNECTIVITYLINE + select STM32_HAVE_OTGFS + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + +config STM32F1_PERFORMANCELINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + +config STM32F1_USBACCESSLINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_SPI2 + + +config STM32F1_MEDIUMPLUSDENSITY + bool + default n + +config STM32F1_HIGHDENSITY + bool + default n + select STM32_HIGHDENSITY + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_MEDIUMDENSITY + bool + default n + select STM32_MEDIUMDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_LOWDENSITY + bool + default n + select STM32_LOWDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 if !STM32F1_VALUELINE + +# Compatibility symbols kept private to STM32F1 selection. Existing driver +# code still keys off these historical names. + +config STM32_VALUELINE + bool + +config STM32_CONNECTIVITYLINE + bool + +config STM32_HIGHDENSITY + bool + +config STM32_MEDIUMDENSITY + bool + +config STM32_LOWDENSITY + bool + +source "arch/arm/src/stm32f1/Kconfig.pinmap" diff --git a/arch/arm/src/stm32f1/Kconfig.pinmap b/arch/arm/src/stm32f1/Kconfig.pinmap new file mode 100644 index 0000000000000..f04d44944be0f --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig.pinmap @@ -0,0 +1,182 @@ +menu "Alternate Pin Mapping" + depends on STM32_STM32F10XX + +choice + prompt "CAN1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_CAN1 + default STM32_CAN1_NO_REMAP + +config STM32_CAN1_NO_REMAP + bool "No pin remapping" + +config STM32_CAN1_REMAP1 + bool "CAN1 alternate pin remapping #1" + +config STM32_CAN1_REMAP2 + bool "CAN1 alternate pin remapping #2" + +endchoice + +config STM32_CAN2_REMAP + bool "CAN2 Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_CAN2 + +config STM32_CEC_REMAP + bool "CEC Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_CEC + +config STM32_ETH_REMAP + bool "Ethernet Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_ETHMAC + +config STM32_I2C1_REMAP + bool "I2C1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2C1 + +config STM32_SPI1_REMAP + bool "SPI1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI1 + +config STM32_SPI3_REMAP + bool "SPI3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI3 && !STM32F1_VALUELINE + +config STM32_I2S3_REMAP + bool "I2S3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2S3 && !STM32F1_VALUELINE + +choice + prompt "TIM1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM1 + default STM32_TIM1_NO_REMAP + +config STM32_TIM1_NO_REMAP + bool "No pin remapping" + +config STM32_TIM1_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM1_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +choice + prompt "TIM2 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM2 + default STM32_TIM2_NO_REMAP + +config STM32_TIM2_NO_REMAP + bool "No pin remapping" + +config STM32_TIM2_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM2_PARTIAL_REMAP_1 + bool "Partial pin remapping #1" + +config STM32_TIM2_PARTIAL_REMAP_2 + bool "Partial pin remapping #2" + +endchoice + +choice + prompt "TIM3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM3 + default STM32_TIM3_NO_REMAP + +config STM32_TIM3_NO_REMAP + bool "No pin remapping" + +config STM32_TIM3_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +config STM32_TIM4_REMAP + bool "TIM4 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM4 + +config STM32_TIM9_REMAP + bool "TIM9 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM9 + +config STM32_TIM10_REMAP + bool "TIM10 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM10 + +config STM32_TIM11_REMAP + bool "TIM11 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM11 + +config STM32_TIM12_REMAP + bool "TIM12 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM12 + +config STM32_TIM13_REMAP + bool "TIM13 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM13 + +config STM32_TIM14_REMAP + bool "TIM14 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM14 + +config STM32_TIM15_REMAP + bool "TIM15 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM15 + +config STM32_TIM16_REMAP + bool "TIM16 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM16 + +config STM32_TIM17_REMAP + bool "TIM17 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM17 + +config STM32_USART1_REMAP + bool "USART1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART1 + +config STM32_USART2_REMAP + bool "USART2 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART2 + +choice + prompt "USART3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_USART3 + default STM32_USART3_NO_REMAP + +config STM32_USART3_NO_REMAP + bool "No pin remapping" + +config STM32_USART3_FULL_REMAP + bool "Full pin remapping" + +config STM32_USART3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +endmenu diff --git a/arch/arm/src/stm32f1/Make.defs b/arch/arm/src/stm32f1/Make.defs new file mode 100644 index 0000000000000..0f8a65ef5a865 --- /dev/null +++ b/arch/arm/src/stm32f1/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f1/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f1/chip.h b/arch/arm/src/stm32f1/chip.h new file mode 100644 index 0000000000000..9f3e121b8db11 --- /dev/null +++ b/arch/arm/src/stm32f1/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_CHIP_H +#define __ARCH_ARM_SRC_STM32F1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F1_CHIP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..027e14eaf9b69 --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f10xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..ed4b8e68f0f51 --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_VALUELINE) +# include "hardware/stm32f100_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# include "hardware/stm32f102_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ + defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ + defined(CONFIG_ARCH_CHIP_STM32F103CB) +# include "hardware/stm32f103c_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RG) +# include "hardware/stm32f103r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103VE) +# include "hardware/stm32f103v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# include "hardware/stm32f103z_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# include "hardware/stm32f105v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# include "hardware/stm32f105r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# include "hardware/stm32f107v_pinmap.h" +#else +# error "Unsupported STM32F1 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f100_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h index e50de324c47dd..56174b632211a 100644 --- a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f100_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2009 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f102_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h index a54ff133eab24..8d85291705b77 100644 --- a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f102_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103c_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h index fa8052df02656..b11796ad7bd29 100644 --- a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103c_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h index 0f5596cd8b0a9..7ad6aa3e63bc0 100644 --- a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h index 8d15dd04fd4f6..3074b6fec4398 100644 --- a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103z_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h index 95a21a58da3bb..1af5f6ef0d15f 100644 --- a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103z_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h index 5701c4af5030a..5956145aa28cb 100644 --- a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h index a0f07baaa035c..b4ce3444d97ed 100644 --- a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f107v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h index e034bf01647a5..7433722c087a8 100644 --- a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f107v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h index 9dd7264b6f1f5..4ba272eebf596 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h index c11e00c13b6fa..ec755efb47b86 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h index 457fea592df83..54828425c3c5e 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f1/stm32.h b/arch/arm/src/stm32f1/stm32.h new file mode 100644 index 0000000000000..5707089d7b890 --- /dev/null +++ b/arch/arm/src/stm32f1/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f1/stm32_rcc.c b/arch/arm/src/stm32f1/stm32_rcc.c new file mode 100644 index 0000000000000..f78d3e0a1897b --- /dev/null +++ b/arch/arm/src/stm32f1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f10xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxx_rcc.c rename to arch/arm/src/stm32f1/stm32f10xxx_rcc.c index fa8c0debe6946..8b2604a55a22b 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxx_rcc.c + * arch/arm/src/stm32f1/stm32f10xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f2/CMakeLists.txt b/arch/arm/src/stm32f2/CMakeLists.txt new file mode 100644 index 0000000000000..79b7a47029770 --- /dev/null +++ b/arch/arm/src/stm32f2/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig new file mode 100644 index 0000000000000..2b99327b6dbf0 --- /dev/null +++ b/arch/arm/src/stm32f2/Kconfig @@ -0,0 +1,179 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F2 configuration" + +if ARCH_CHIP_STM32F2 + +choice + prompt "STM32F2 Chip Selection" + depends on ARCH_CHIP_STM32F2 + +config ARCH_CHIP_STM32F205RG + bool "STM32F205RG" + select STM32_STM32F20XX + select STM32_STM32F205 + +config ARCH_CHIP_STM32F207VC + bool "STM32F207VC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VE + bool "STM32F207VE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VF + bool "STM32F207VF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VG + bool "STM32F207VG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IC + bool "STM32F207IC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IE + bool "STM32F207IE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IF + bool "STM32F207IF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IG + bool "STM32F207IG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZC + bool "STM32F207ZC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZE + bool "STM32F207ZE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZF + bool "STM32F207ZF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZG + bool "STM32F207ZG" + select STM32_STM32F20XX + select STM32_STM32F207 + +endchoice + +endif + +config STM32_STM32F20XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_HAVE_DCMI + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_OTGFS + select STM32_HAVE_OTGHS + select STM32_HAVE_SPI1 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F205 + bool + default n + +config STM32_STM32F207 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_ETHMAC diff --git a/arch/arm/src/stm32f2/Make.defs b/arch/arm/src/stm32f2/Make.defs new file mode 100644 index 0000000000000..b98256025f3e6 --- /dev/null +++ b/arch/arm/src/stm32f2/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f2/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f2/chip.h b/arch/arm/src/stm32f2/chip.h new file mode 100644 index 0000000000000..4b555d13fb72a --- /dev/null +++ b/arch/arm/src/stm32f2/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_CHIP_H +#define __ARCH_ARM_SRC_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F2_CHIP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..4037ce463e154 --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..e9a0e492b35ef --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h index ebb059482823f..32ab85cc3dfa0 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h index 189e5a7a0814a..d55645a1ac50f 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h index aa7f4da6bfb45..544806fd18111 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h index c447c70bf6a54..31af35f07a1bf 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h index 954c04663318d..c4ad192e1ee00 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f2/stm32.h b/arch/arm/src/stm32f2/stm32.h new file mode 100644 index 0000000000000..9069ebcbca61e --- /dev/null +++ b/arch/arm/src/stm32f2/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f2/stm32_rcc.c b/arch/arm/src/stm32f2/stm32_rcc.c new file mode 100644 index 0000000000000..7452375136a26 --- /dev/null +++ b/arch/arm/src/stm32f2/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f20xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f20xxx_rcc.c rename to arch/arm/src/stm32f2/stm32f20xxx_rcc.c index eb9e97e0ed8bf..30c8f34740dfb 100644 --- a/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxx_rcc.c + * arch/arm/src/stm32f2/stm32f20xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f3/CMakeLists.txt b/arch/arm/src/stm32f3/CMakeLists.txt new file mode 100644 index 0000000000000..36707fa80f197 --- /dev/null +++ b/arch/arm/src/stm32f3/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f3/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig new file mode 100644 index 0000000000000..5fd4db20b0185 --- /dev/null +++ b/arch/arm/src/stm32f3/Kconfig @@ -0,0 +1,614 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F3 configuration" + +if ARCH_CHIP_STM32F3 + +choice + prompt "STM32F3 Chip Selection" + depends on ARCH_CHIP_STM32F3 + +config ARCH_CHIP_STM32F302K6 + bool "STM32F302K6" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302K8 + bool "STM32F302K8" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302C6 + bool "STM32F302C6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302C8 + bool "STM32F302C8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R6 + bool "STM32F302R6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R8 + bool "STM32F302R8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302CB + bool "STM32F302CB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302CC + bool "STM32F302CC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302RB + bool "STM32F302RB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302RC + bool "STM32F302RC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VB + bool "STM32F302VB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VC + bool "STM32F302VC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F303K6 + bool "STM32F303K6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303K8 + bool "STM32F303K8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303C6 + bool "STM32F303C6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303C8 + bool "STM32F303C8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303CB + bool "STM32F303CB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303CC + bool "STM32F303CC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RB + bool "STM32F303RB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RC + bool "STM32F303RC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RD + bool "STM32F303RD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RE + bool "STM32F303RE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VB + bool "STM32F303VB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VC + bool "STM32F303VC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VD + bool "STM32F303VD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303VE + bool "STM32F303VE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZD + bool "STM32F303ZD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZE + bool "STM32F303ZE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F334K4 + bool "STM32F334K4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K6 + bool "STM32F334K6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K8 + bool "STM32F334K8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C4 + bool "STM32F334C4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C6 + bool "STM32F334C6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C8 + bool "STM32F334C8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R4 + bool "STM32F334R4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R6 + bool "STM32F334R6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R8 + bool "STM32F334R8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F372C8 + bool "STM32F372C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372R8 + bool "STM32F372R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372V8 + bool "STM32F372V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CB + bool "STM32F372CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RB + bool "STM32F372RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VB + bool "STM32F372VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CC + bool "STM32F372CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RC + bool "STM32F372RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VC + bool "STM32F372VC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373C8 + bool "STM32F373C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373R8 + bool "STM32F373R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373V8 + bool "STM32F373V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CB + bool "STM32F373CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RB + bool "STM32F373RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VB + bool "STM32F373VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CC + bool "STM32F373CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RC + bool "STM32F373RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VC + bool "STM32F373VC" + select STM32_STM32F37XX + +endchoice + +endif + +config STM32_STM32F30XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F302 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_USBDEV + +config STM32_STM32F303 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM7 + +config STM32_STM32F33XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP6 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F37XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SDADC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 diff --git a/arch/arm/src/stm32f3/Make.defs b/arch/arm/src/stm32f3/Make.defs new file mode 100644 index 0000000000000..e847b60c00751 --- /dev/null +++ b/arch/arm/src/stm32f3/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f3/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f3/chip.h b/arch/arm/src/stm32f3/chip.h new file mode 100644 index 0000000000000..c3961139c12ee --- /dev/null +++ b/arch/arm/src/stm32f3/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_CHIP_H +#define __ARCH_ARM_SRC_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F3_CHIP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..475cd8800a33c --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_memorymap.h" +#else +# error "Unsupported STM32F3 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..35a22b5600934 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_pinmap.h" +#else +# error "Unsupported STM32F3 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h index 47087489a38c3..247900fd222e8 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h index 23667f3b7c974..9471911d8c4cb 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h index d92b45de89a95..02c86632c64d0 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h index 9d86d13a7040d..10d8c30c617b5 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h index 74900826244b4..e9fa174e4e7cd 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_comp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h index d12e43317d560..0cc9a568c7b93 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_comp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h index 7c6ff331f9ae3..94480b138758a 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h index eb59aba7e218e..ce0e3889d20af 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h index 3235866bcee08..a2a1a269b9657 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h index 3d3be1182a6e3..e5e55225381b2 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h index 1e26281fb4380..05348c760ecc6 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h index 5c3764b2d4ded..a3270a48b35c9 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h index fd05c2477b9fa..26baaf49cd444 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h index f830d6868dc02..f26a6c33f29b9 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h index a0f658aa6d7d0..ef555856d7c47 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h index f75141295021c..908ccda789f19 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016 Studelec SA. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h index 6849a95cbb639..d6a726471485b 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f3/stm32.h b/arch/arm/src/stm32f3/stm32.h new file mode 100644 index 0000000000000..f7eb0f45c819d --- /dev/null +++ b/arch/arm/src/stm32f3/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f3/stm32_rcc.c b/arch/arm/src/stm32f3/stm32_rcc.c new file mode 100644 index 0000000000000..32d4bbca0f3cd --- /dev/null +++ b/arch/arm/src/stm32f3/stm32_rcc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#if defined(CONFIG_STM32_STM32F30XX) +# include "stm32f30xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "stm32f33xxx_rcc.c" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "stm32f37xxx_rcc.c" +#else +# error "Unsupported STM32F3 chip" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f30xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f30xxx_rcc.c index 8c0f606c7651e..79eeff67e83e3 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f30xxx_rcc.c + * arch/arm/src/stm32f3/stm32f30xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f33xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f33xxx_rcc.c index bf3edc0727579..d55f756b53b44 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f33xxx_rcc.c + * arch/arm/src/stm32f3/stm32f33xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f37xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f37xxx_rcc.c index 6c8a157a48ec8..c640835f69645 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f37xxx_rcc.c + * arch/arm/src/stm32f3/stm32f37xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f4/CMakeLists.txt b/arch/arm/src/stm32f4/CMakeLists.txt new file mode 100644 index 0000000000000..7b5008db37150 --- /dev/null +++ b/arch/arm/src/stm32f4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig new file mode 100644 index 0000000000000..c7dc917898e57 --- /dev/null +++ b/arch/arm/src/stm32f4/Kconfig @@ -0,0 +1,619 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F4 configuration" + +if ARCH_CHIP_STM32F4 + +choice + prompt "STM32F4 Chip Selection" + depends on ARCH_CHIP_STM32F4 + +config ARCH_CHIP_STM32F401CB + bool "STM32F401CB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RB + bool "STM32F401RB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VB + bool "STM32F401VB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CC + bool "STM32F401CC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RC + bool "STM32F401RC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VC + bool "STM32F401VC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CD + bool "STM32F401CD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RD + bool "STM32F401RD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VD + bool "STM32F401VD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401CE + bool "STM32F401CE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RE + bool "STM32F401RE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VE + bool "STM32F401VE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F410RB + bool "STM32F410RB" + select STM32_STM32F4XXX + select STM32_STM32F410 + +config ARCH_CHIP_STM32F411CE + bool "STM32F411CE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411RE + bool "STM32F411RE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411VE + bool "STM32F411VE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F412CE + bool "STM32F412CE" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F412ZG + bool "STM32F412ZG" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F405RG + bool "STM32F405RG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405VG + bool "STM32F405VG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405ZG + bool "STM32F405ZG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F407VE + bool "STM32F407VE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407VG + bool "STM32F407VG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZE + bool "STM32F407ZE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZG + bool "STM32F407ZG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IE + bool "STM32F407IE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IG + bool "STM32F407IG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F427V + bool "STM32F427V" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427Z + bool "STM32F427Z" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427I + bool "STM32F427I" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F429V + bool "STM32F429V" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429Z + bool "STM32F429Z" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429I + bool "STM32F429I" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429B + bool "STM32F429B" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429N + bool "STM32F429N" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F446M + bool "STM32F446M" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446R + bool "STM32F446R" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446V + bool "STM32F446V" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446Z + bool "STM32F446Z" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F469A + bool "STM32F469A" + select STM32_STM32F4XXX + select STM32_STM32F469 + +config ARCH_CHIP_STM32F469I + bool "STM32F469I" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469B + bool "STM32F469B" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469N + bool "STM32F469N" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +endchoice + +endif + +config STM32_STM32F4XXX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_DCMI + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_F4 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F401xBC + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401xDE + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401 + bool + default n + select ARCH_CORTEXM4 + select STM32_STM32F4XXX + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F410 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI5 + select STM32_HAVE_DAC1 + +config STM32_STM32F411 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F412 + bool + default n + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_USART3 + select STM32_HAVE_USART2 + select STM32_HAVE_USART6 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2SPLL + +config STM32_STM32F405 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_OTGFS + +config STM32_STM32F407 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_OTGFS + +# This is really 427/437, but we treat the two the same. + +config STM32_STM32F427 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SPI6 + select STM32_HAVE_I2SPLL + +# This is really 429/439, but we treat the two the same. + +config STM32_STM32F429 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F446 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + +# This is really 469/479, but we treat the two the same. + +config STM32_STM32F469 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 diff --git a/arch/arm/src/stm32f4/Make.defs b/arch/arm/src/stm32f4/Make.defs new file mode 100644 index 0000000000000..061c17116243d --- /dev/null +++ b/arch/arm/src/stm32f4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f4/chip.h b/arch/arm/src/stm32f4/chip.h new file mode 100644 index 0000000000000..647bbd778c82e --- /dev/null +++ b/arch/arm/src/stm32f4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_CHIP_H +#define __ARCH_ARM_SRC_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F4_CHIP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..c2b208c9c2719 --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f40xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..35b04147293aa --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h @@ -0,0 +1,25 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F412) +# include "hardware/stm32f412xx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_pinmap.h" +#else +# error "Unsupported STM32F4 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h index 95ce98d3d930e..167dedbd48409 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h index 72fe218a4441b..c1549f7b99444 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h index 0b40bdd84223e..4f97953d1606c 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h index 08bd4e7328ed3..d4e56f3f29654 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h index 19da1a40b392b..9beeef94ebbcf 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h index 0ecba4ca90387..305547e1888df 100644 --- a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f4/stm32.h b/arch/arm/src/stm32f4/stm32.h new file mode 100644 index 0000000000000..56a9dbc8151a7 --- /dev/null +++ b/arch/arm/src/stm32f4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f4/stm32_rcc.c b/arch/arm/src/stm32f4/stm32_rcc.c new file mode 100644 index 0000000000000..0c03fece5cda6 --- /dev/null +++ b/arch/arm/src/stm32f4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f40xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f40xxx_alarm.h b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h similarity index 98% rename from arch/arm/src/stm32/stm32f40xxx_alarm.h rename to arch/arm/src/stm32f4/stm32f40xxx_alarm.h index 98daa796e7b24..04e096a63cb65 100644 --- a/arch/arm/src/stm32/stm32f40xxx_alarm.h +++ b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_alarm.h + * arch/arm/src/stm32f4/stm32f40xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rcc.c rename to arch/arm/src/stm32f4/stm32f40xxx_rcc.c index 453ced82d2b37..f5f8dc84a6f71 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32f40xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index 14f9ccda0202e..327dc5c59a78a 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -49,7 +49,7 @@ #include "stm32_rcc.h" #include "stm32_can.h" -/* Ported form arch/arm/src/stm32/stm32_can_sock.c */ +/* Ported form arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 5932b37c80d13..9f51388aaee5b 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -78,7 +78,8 @@ * * Currently, up to two FOC instances are supported. * - * This implementation is based on arch/arm/src/stm32/stm32_foc.c + * This implementation is based on + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c */ /* Verify system configuration **********************************************/ diff --git a/arch/arm/src/stm32g4/CMakeLists.txt b/arch/arm/src/stm32g4/CMakeLists.txt new file mode 100644 index 0000000000000..24e6c94b34226 --- /dev/null +++ b/arch/arm/src/stm32g4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32g4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig new file mode 100644 index 0000000000000..627f83754ce15 --- /dev/null +++ b/arch/arm/src/stm32g4/Kconfig @@ -0,0 +1,336 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G4 configuration" + +if ARCH_CHIP_STM32G4 + +choice + prompt "STM32G4 Chip Selection" + depends on ARCH_CHIP_STM32G4 + +config ARCH_CHIP_STM32G431K + bool "STM32G431K" + select STM32_STM32G43XX + select STM32_STM32G4XXK + select STM32_STM32G431K + +config ARCH_CHIP_STM32G431C + bool "STM32G431C" + select STM32_STM32G43XX + select STM32_STM32G4XXC + select STM32_STM32G431C + +config ARCH_CHIP_STM32G431R + bool "STM32G431R" + select STM32_STM32G43XX + select STM32_STM32G4XXR + select STM32_STM32G431R + +config ARCH_CHIP_STM32G431M + bool "STM32G431M" + select STM32_STM32G43XX + select STM32_STM32G4XXM + select STM32_STM32G431M + +config ARCH_CHIP_STM32G431V + bool "STM32G431V" + select STM32_STM32G43XX + select STM32_STM32G4XXV + select STM32_STM32G431V + +config ARCH_CHIP_STM32G474C + bool "STM32G474C" + select STM32_STM32G47XX + select STM32_STM32G4XXC + select STM32_STM32G474C + +config ARCH_CHIP_STM32G474M + bool "STM32G474M" + select STM32_STM32G47XX + select STM32_STM32G4XXM + select STM32_STM32G474M + +config ARCH_CHIP_STM32G474R + bool "STM32G474R" + select STM32_STM32G47XX + select STM32_STM32G4XXR + select STM32_STM32G474R + select STM32_HAVE_USBFS + +config ARCH_CHIP_STM32G474Q + bool "STM32G474Q" + select STM32_STM32G47XX + select STM32_STM32G4XXQ + select STM32_STM32G474Q + +config ARCH_CHIP_STM32G474V + bool "STM32G474V" + select STM32_STM32G47XX + select STM32_STM32G4XXV + select STM32_STM32G474V + +endchoice + +endif + +config STM32_STM32G4XXX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V3 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_COMP_M3M4_V2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC + select STM32_HAVE_IP_DAC_M3M4_V2 + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_G4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32G4_CAT2 + bool + default n + +config STM32_STM32G4_CAT3 + bool + default n + +config STM32_STM32G4_CAT4 + bool + default n + +config STM32_STM32G4XXK + bool + default n + +config STM32_STM32G4XXC + bool + default n + +config STM32_STM32G4XXR + bool + default n + +config STM32_STM32G4XXM + bool + default n + +config STM32_STM32G4XXV + bool + default n + +config STM32_STM32G4XXP + bool + default n + +config STM32_STM32G4XXQ + bool + default n + +config STM32_STM32G43XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT2 + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC3 + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G431K + bool + default n + +config STM32_STM32G431C + bool + default n + select STM32_HAVE_USART3 + +config STM32_STM32G431R + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431M + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431V + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G47XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT3 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_ADC5 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP5 + select STM32_HAVE_COMP6 + select STM32_HAVE_COMP7 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DAC3 + select STM32_HAVE_DAC4 + select STM32_HAVE_FSMC + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_OPAMP4 + select STM32_HAVE_OPAMP5 + select STM32_HAVE_OPAMP6 + select STM32_HAVE_QSPI + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM20 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G474C + bool + default n + select STM32_HAVE_FDCAN3 + +config STM32_STM32G474M + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474R + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474Q + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474V + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 diff --git a/arch/arm/src/stm32g4/Make.defs b/arch/arm/src/stm32g4/Make.defs new file mode 100644 index 0000000000000..e8ec4e1184e64 --- /dev/null +++ b/arch/arm/src/stm32g4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32g4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32g4/chip.h b/arch/arm/src/stm32g4/chip.h new file mode 100644 index 0000000000000..2be83d370f594 --- /dev/null +++ b/arch/arm/src/stm32g4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_CHIP_H +#define __ARCH_ARM_SRC_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32G4_CHIP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..5c737c84db3e1 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..24148a4582831 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h rename to arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h index 4e2a6445bfa4e..21a1dc772c5a3 100644 --- a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h +++ b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h + * arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h index ce52049659085..6712ccc160f99 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h index 44701877d520e..0061b3e7fd49d 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h index 1f28684b1368f..c8ef978d5cccb 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h index 860e449abacd9..2d3ad17853477 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h index 82d1c4b86429b..92b1d059c20ec 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h index 53806263bc7e0..009b98fe1f5ae 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h index a6cd76129e0ed..78197031a2cdd 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h index 4a9ec781e0708..aff65335c071e 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h index c0e5c6669cb3a..d664710669c03 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h index a5d58546c6ca7..7e7c994dc30e1 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h index 661060cb87681..7136812cdf6e6 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h index e0d72cf4cf186..fe1b4330269dc 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h index 89cddf6e59b66..d607bd4d2b586 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h index b8a5dc9546c20..04f177f6ce8a2 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h index c5af4b8e15790..20bf5247308ef 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h index 543d369f3ebf7..6070eeea00fb7 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h index a7fdf99c74b94..4de4a00d94e69 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h index 5591bfe744a53..4b3d532c27f37 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32g4/stm32.h b/arch/arm/src/stm32g4/stm32.h new file mode 100644 index 0000000000000..07776d682753f --- /dev/null +++ b/arch/arm/src/stm32g4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32g4/stm32_rcc.c b/arch/arm/src/stm32g4/stm32_rcc.c new file mode 100644 index 0000000000000..49cfab73fb945 --- /dev/null +++ b/arch/arm/src/stm32g4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g4xxxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32g4xxxx_rcc.c b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxxx_rcc.c rename to arch/arm/src/stm32g4/stm32g4xxxx_rcc.c index 8f93746577855..f92d785d74287 100644 --- a/arch/arm/src/stm32/stm32g4xxxx_rcc.c +++ b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxxx_rcc.c + * arch/arm/src/stm32g4/stm32g4xxxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l1/CMakeLists.txt b/arch/arm/src/stm32l1/CMakeLists.txt new file mode 100644 index 0000000000000..1067ff1910153 --- /dev/null +++ b/arch/arm/src/stm32l1/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32l1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig new file mode 100644 index 0000000000000..5b185142fa864 --- /dev/null +++ b/arch/arm/src/stm32l1/Kconfig @@ -0,0 +1,353 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L1 configuration" + +if ARCH_CHIP_STM32L1 + +choice + prompt "STM32L1 Chip Selection" + depends on ARCH_CHIP_STM32L1 + +config ARCH_CHIP_STM32L151C6 + bool "STM32L151C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151C8 + bool "STM32L151C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151CB + bool "STM32L151CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R6 + bool "STM32L151R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R8 + bool "STM32L151R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151RB + bool "STM32L151RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V6 + bool "STM32L151V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V8 + bool "STM32L151V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151VB + bool "STM32L151VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L152C6 + bool "STM32L152C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152C8 + bool "STM32L152C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152CB + bool "STM32L152CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152R6 + bool "STM32L152R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152R8 + bool "STM32L152R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152RB + bool "STM32L152RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152V6 + bool "STM32L152V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152V8 + bool "STM32L152V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152VB + bool "STM32L152VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152CC + bool "STM32L152CC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152RC + bool "STM32L152RC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152VC + bool "STM32L152VC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L151RE + bool "STM32L151RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152RE + bool "STM32L152RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151VE + bool "STM32L151VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152VE + bool "STM32L152VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151QE + bool "STM32L151QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152QE + bool "STM32L152QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151ZE + bool "STM32L151ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152ZE + bool "STM32L152ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L162ZD + bool "STM32L162ZD" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L162VE + bool "STM32L162VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with + 4x44/8x40 LCD interface + +endchoice + +endif + +config STM32_STM32L15XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_ENERGYLITE + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_RTC_SUBSECONDS if !STM32L1_LOWDENSITY + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + + +config STM32L1_MEDIUMPLUSDENSITY + bool + default n + +config STM32L1_HIGHDENSITY + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_MEDIUMDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_LOWDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 diff --git a/arch/arm/src/stm32l1/Make.defs b/arch/arm/src/stm32l1/Make.defs new file mode 100644 index 0000000000000..f0e835622db56 --- /dev/null +++ b/arch/arm/src/stm32l1/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32l1/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32l1/chip.h b/arch/arm/src/stm32l1/chip.h new file mode 100644 index 0000000000000..b0857c705039f --- /dev/null +++ b/arch/arm/src/stm32l1/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_CHIP_H +#define __ARCH_ARM_SRC_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32L1_CHIP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h new file mode 100644 index 0000000000000..bbe24f67a2ca6 --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h new file mode 100644 index 0000000000000..9bbf21f22811c --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_aes.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h index c68fbc44d66e0..101ad5e19c4be 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_aes.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h index 49dd7919b2268..903605e60af5e 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h index b1c2ba9ce8339..4a59b4c86caac 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h index 9211c8c64bec7..75294a51a742c 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h index 0217a9a79d948..c557971f1a356 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h index 3e6dfa2ddbe24..9cba220f8c207 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l1/stm32.h b/arch/arm/src/stm32l1/stm32.h new file mode 100644 index 0000000000000..2aed55b33cac0 --- /dev/null +++ b/arch/arm/src/stm32l1/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32l1/stm32_rcc.c b/arch/arm/src/stm32l1/stm32_rcc.c new file mode 100644 index 0000000000000..044d6aea475dd --- /dev/null +++ b/arch/arm/src/stm32l1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l15xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32l15xxx_alarm.h b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_alarm.h rename to arch/arm/src/stm32l1/stm32l15xxx_alarm.h index 52267bf83c0b8..1d5e789cec91c 100644 --- a/arch/arm/src/stm32/stm32l15xxx_alarm.h +++ b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_alarm.h + * arch/arm/src/stm32l1/stm32l15xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rcc.c rename to arch/arm/src/stm32l1/stm32l15xxx_rcc.c index 043e46beca372..f7f08c0f656ba 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rcc.c + * arch/arm/src/stm32l1/stm32l15xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/Kconfig b/boards/Kconfig index bf39f97fd5b93..ba2cb60b87f05 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -4486,52 +4486,52 @@ if ARCH_BOARD_PIC32CZCA70_CURIOSITY source "boards/arm/samv7/pic32czca70-curiosity/Kconfig" endif if ARCH_BOARD_B_G474E_DPOW1 -source "boards/arm/stm32/b-g474e-dpow1/Kconfig" +source "boards/arm/stm32g4/b-g474e-dpow1/Kconfig" endif if ARCH_BOARD_B_G431B_ESC1 -source "boards/arm/stm32/b-g431b-esc1/Kconfig" +source "boards/arm/stm32g4/b-g431b-esc1/Kconfig" endif if ARCH_BOARD_NUCLEO_G431KB -source "boards/arm/stm32/nucleo-g431kb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431kb/Kconfig" endif if ARCH_BOARD_NUCLEO_G431RB -source "boards/arm/stm32/nucleo-g431rb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431rb/Kconfig" endif if ARCH_BOARD_B_L072Z_LRWAN1 -source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig" +source "boards/arm/stm32l0/b-l072z-lrwan1/Kconfig" endif if ARCH_BOARD_NUCLEO_F072RB -source "boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig" +source "boards/arm/stm32f0/nucleo-f072rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F091RC -source "boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig" +source "boards/arm/stm32f0/nucleo-f091rc/Kconfig" endif if ARCH_BOARD_NUCLEO_G070RB -source "boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g070rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G071RB -source "boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G0B1RE -source "boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig" +source "boards/arm/stm32g0/nucleo-g0b1re/Kconfig" endif if ARCH_BOARD_NUCLEO_L073RZ -source "boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig" +source "boards/arm/stm32l0/nucleo-l073rz/Kconfig" endif if ARCH_BOARD_STM32F051_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f051-discovery/Kconfig" endif if ARCH_BOARD_STM32L0538_DISCO -source "boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig" +source "boards/arm/stm32l0/stm32l0538-disco/Kconfig" endif if ARCH_BOARD_STM32F072_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f072-discovery/Kconfig" endif if ARCH_BOARD_NUCLEO_C071RB -source "boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig" +source "boards/arm/stm32c0/nucleo-c071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_C092RC -source "boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig" +source "boards/arm/stm32c0/nucleo-c092rc/Kconfig" endif if ARCH_BOARD_NUCLEO_F722ZE source "boards/arm/stm32f7/nucleo-f722ze/Kconfig" @@ -4651,151 +4651,151 @@ if ARCH_BOARD_NUCLEO_WB55RG source "boards/arm/stm32wb/nucleo-wb55rg/Kconfig" endif if ARCH_BOARD_AXOLOTI -source "boards/arm/stm32/axoloti/Kconfig" +source "boards/arm/stm32f4/axoloti/Kconfig" endif if ARCH_BOARD_CLICKER2_STM32 -source "boards/arm/stm32/clicker2-stm32/Kconfig" +source "boards/arm/stm32f4/clicker2-stm32/Kconfig" endif if ARCH_BOARD_CLOUDCTRL -source "boards/arm/stm32/cloudctrl/Kconfig" +source "boards/arm/stm32f1/cloudctrl/Kconfig" endif if ARCH_BOARD_EMW3162 -source "boards/arm/stm32/emw3162/Kconfig" +source "boards/arm/stm32f2/emw3162/Kconfig" endif if ARCH_BOARD_FIRE_STM32 -source "boards/arm/stm32/fire-stm32v2/Kconfig" +source "boards/arm/stm32f1/fire-stm32v2/Kconfig" endif if ARCH_BOARD_HYMINI_STM32V -source "boards/arm/stm32/hymini-stm32v/Kconfig" +source "boards/arm/stm32f1/hymini-stm32v/Kconfig" endif if ARCH_BOARD_MAPLE -source "boards/arm/stm32/maple/Kconfig" +source "boards/arm/stm32f1/maple/Kconfig" endif if ARCH_BOARD_ET_STM32_STAMP -source "boards/arm/stm32/et-stm32-stamp/Kconfig" +source "boards/arm/stm32f1/et-stm32-stamp/Kconfig" endif if ARCH_BOARD_MIKROE_STM32F4 -source "boards/arm/stm32/mikroe-stm32f4/Kconfig" +source "boards/arm/stm32f4/mikroe-stm32f4/Kconfig" endif if ARCH_BOARD_NUCLEO_F103RB -source "boards/arm/stm32/nucleo-f103rb/Kconfig" +source "boards/arm/stm32f1/nucleo-f103rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F207ZG -source "boards/arm/stm32/nucleo-f207zg/Kconfig" +source "boards/arm/stm32f2/nucleo-f207zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F302R8 -source "boards/arm/stm32/nucleo-f302r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f302r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F303RE -source "boards/arm/stm32/nucleo-f303re/Kconfig" +source "boards/arm/stm32f3/nucleo-f303re/Kconfig" endif if ARCH_BOARD_NUCLEO_F303ZE -source "boards/arm/stm32/nucleo-f303ze/Kconfig" +source "boards/arm/stm32f3/nucleo-f303ze/Kconfig" endif if ARCH_BOARD_NUCLEO_F334R8 -source "boards/arm/stm32/nucleo-f334r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f334r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F410RB -source "boards/arm/stm32/nucleo-f410rb/Kconfig" +source "boards/arm/stm32f4/nucleo-f410rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F412ZG -source "boards/arm/stm32/nucleo-f412zg/Kconfig" +source "boards/arm/stm32f4/nucleo-f412zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F446RE -source "boards/arm/stm32/nucleo-f446re/Kconfig" +source "boards/arm/stm32f4/nucleo-f446re/Kconfig" endif if ARCH_BOARD_NUCLEO_F401RE -source "boards/arm/stm32/nucleo-f401re/Kconfig" +source "boards/arm/stm32f4/nucleo-f401re/Kconfig" endif if ARCH_BOARD_NUCLEO_F411RE -source "boards/arm/stm32/nucleo-f411re/Kconfig" +source "boards/arm/stm32f4/nucleo-f411re/Kconfig" endif if ARCH_BOARD_STM32F401RC_RS485 -source "boards/arm/stm32/stm32f401rc-rs485/Kconfig" +source "boards/arm/stm32f4/stm32f401rc-rs485/Kconfig" endif if ARCH_BOARD_NUCLEO_F429ZI -source "boards/arm/stm32/nucleo-f429zi/Kconfig" +source "boards/arm/stm32f4/nucleo-f429zi/Kconfig" endif if ARCH_BOARD_NUCLEO_L152RE -source "boards/arm/stm32/nucleo-l152re/Kconfig" +source "boards/arm/stm32l1/nucleo-l152re/Kconfig" endif if ARCH_BOARD_ODRIVE36 -source "boards/arm/stm32/odrive36/Kconfig" +source "boards/arm/stm32f4/odrive36/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32E407 -source "boards/arm/stm32/olimex-stm32-e407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-e407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H405 -source "boards/arm/stm32/olimex-stm32-h405/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h405/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H407 -source "boards/arm/stm32/olimex-stm32-h407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P107 -source "boards/arm/stm32/olimex-stm32-p107/Kconfig" +source "boards/arm/stm32f1/olimex-stm32-p107/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P207 -source "boards/arm/stm32/olimex-stm32-p207/Kconfig" +source "boards/arm/stm32f2/olimex-stm32-p207/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P407 -source "boards/arm/stm32/olimex-stm32-p407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-p407/Kconfig" endif if ARCH_BOARD_OLIMEXINO_STM32 -source "boards/arm/stm32/olimexino-stm32/Kconfig" +source "boards/arm/stm32f1/olimexino-stm32/Kconfig" endif if ARCH_BOARD_OMNIBUSF4 -source "boards/arm/stm32/omnibusf4/Kconfig" +source "boards/arm/stm32f4/omnibusf4/Kconfig" endif if ARCH_BOARD_PHOTON -source "boards/arm/stm32/photon/Kconfig" +source "boards/arm/stm32f2/photon/Kconfig" endif if ARCH_BOARD_SHENZHOU -source "boards/arm/stm32/shenzhou/Kconfig" +source "boards/arm/stm32f1/shenzhou/Kconfig" endif if ARCH_BOARD_STM3210E_EVAL -source "boards/arm/stm32/stm3210e-eval/Kconfig" +source "boards/arm/stm32f1/stm3210e-eval/Kconfig" endif if ARCH_BOARD_STM3220G_EVAL -source "boards/arm/stm32/stm3220g-eval/Kconfig" +source "boards/arm/stm32f2/stm3220g-eval/Kconfig" endif if ARCH_BOARD_STM3240G_EVAL -source "boards/arm/stm32/stm3240g-eval/Kconfig" +source "boards/arm/stm32f4/stm3240g-eval/Kconfig" endif if ARCH_BOARD_STM32_TINY -source "boards/arm/stm32/stm32_tiny/Kconfig" +source "boards/arm/stm32f1/stm32_tiny/Kconfig" endif if ARCH_BOARD_STM32_BUTTERFLY2 -source "boards/arm/stm32/stm32butterfly2/Kconfig" +source "boards/arm/stm32f1/stm32butterfly2/Kconfig" endif if ARCH_BOARD_STM32F103_MINIMUM -source "boards/arm/stm32/stm32f103-minimum/Kconfig" +source "boards/arm/stm32f1/stm32f103-minimum/Kconfig" endif if ARCH_BOARD_STM32F411_MINIMUM -source "boards/arm/stm32/stm32f411-minimum/Kconfig" +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig" endif if ARCH_BOARD_STM32F334_DISCO -source "boards/arm/stm32/stm32f334-disco/Kconfig" +source "boards/arm/stm32f3/stm32f334-disco/Kconfig" endif if ARCH_BOARD_STM32F3_DISCOVERY -source "boards/arm/stm32/stm32f3discovery/Kconfig" +source "boards/arm/stm32f3/stm32f3discovery/Kconfig" endif if ARCH_BOARD_STM32F411E_DISCO -source "boards/arm/stm32/stm32f411e-disco/Kconfig" +source "boards/arm/stm32f4/stm32f411e-disco/Kconfig" endif if ARCH_BOARD_STM32F429I_DISCO -source "boards/arm/stm32/stm32f429i-disco/Kconfig" +source "boards/arm/stm32f4/stm32f429i-disco/Kconfig" endif if ARCH_BOARD_STM32F4_DISCOVERY -source "boards/arm/stm32/stm32f4discovery/Kconfig" +source "boards/arm/stm32f4/stm32f4discovery/Kconfig" endif if ARCH_BOARD_STM32L_DISCOVERY -source "boards/arm/stm32/stm32ldiscovery/Kconfig" +source "boards/arm/stm32l1/stm32ldiscovery/Kconfig" endif if ARCH_BOARD_STM32VL_DISCOVERY -source "boards/arm/stm32/stm32vldiscovery/Kconfig" +source "boards/arm/stm32f1/stm32vldiscovery/Kconfig" endif if ARCH_BOARD_VIEWTOOL_STM32F107 -source "boards/arm/stm32/viewtool-stm32f107/Kconfig" +source "boards/arm/stm32f1/viewtool-stm32f107/Kconfig" endif if ARCH_BOARD_OLIMEX_STRP711 source "boards/arm/str71x/olimex-strp711/Kconfig" diff --git a/boards/arm/stm32/axoloti/CMakeLists.txt b/boards/arm/stm32/axoloti/CMakeLists.txt deleted file mode 100644 index 47501793832b2..0000000000000 --- a/boards/arm/stm32/axoloti/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/axoloti/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/axoloti/configs/nsh/defconfig b/boards/arm/stm32/axoloti/configs/nsh/defconfig deleted file mode 100644 index 1527d1283178c..0000000000000 --- a/boards/arm/stm32/axoloti/configs/nsh/defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STANDARD_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="axoloti" -CONFIG_ARCH_BOARD_AXOLOTI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F427I=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_MM_REGIONS=2 -CONFIG_RAW_BINARY=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART6_BAUD=31250 -CONFIG_USART6_RXBUFSIZE=128 -CONFIG_USART6_TXBUFSIZE=32 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/axoloti/include/board.h b/boards/arm/stm32/axoloti/include/board.h deleted file mode 100644 index 41d122815b3f8..0000000000000 --- a/boards/arm/stm32/axoloti/include/board.h +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Clocking - * The Axoloti board has an external 8MHz crystal. - * The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be - * configured at that system clock rate, so the core clock is 168MHz. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, - * SDIO and RNG clock : Enabled - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/**************************************************************************** - * LED Definitions - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_RED BOARD_LED2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/**************************************************************************** - * Button Definitions - * There are two buttons on the axoloti, one of them is GPIO connected. The - * other is a reset button and is not under software control. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/**************************************************************************** - * UARTs - * The MIDI in/out ports of the axoloti are connected on USART6. - * It maybe convenient to run a serial port connected to the header pins, - * so we can optionally use USART1 for that. - */ - -/* USART1 - console on header pins */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* AF7, PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* AF7, PB6 */ - -/* USART6 - midi in/out */ - -#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \ - GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL) - -#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \ - GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN) - -/**************************************************************************** - * I2C Bus - * Turn on the internal pullups since there are no external pullups. - */ - -/* I2C1 - for external devices */ - -#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -#define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -/* I2C3 - for the ADAU1961 codec */ - -#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \ - GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) - -/**************************************************************************** - * SAI Bus - * Used with the ADAU1961 CODEC - * PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1) - * PE4_SAI1_FS_A (GPIO_SAI1_FS_A) - * PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A) - * PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2) - * PA8_MCO1 - */ - -#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */ -#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */ - -#define STM32_SAI1_FREQUENCY (48000 * 2 * 256) /* TODO ?? */ - -/* DAC DMA to Codec - * dma 2, stream 1, channel 0 - * memory to peripheral - * 32 bits - */ -#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1 - -/* ADC DMA from Codec - * dma 2, stream 4, channel 1, - * peripheral to memory - * 32 bits - */ -#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2 - -/**************************************************************************** - * SDIO - * Used for the SD card interface. - * d0 (AF12, PC8) - * d1 (AF12, PC9) - * d2 (AF12, PC10) - * d3 (AF12, PC11) - * clk (AF12, PC12) - * cmd (AF12, PD2) - * cd1 PD13 - */ - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* dma 2, stream 6, channel 4 */ - -#define DMAMAP_SDIO DMAMAP_SDIO_2 - -#endif /* __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/axoloti/scripts/Make.defs b/boards/arm/stm32/axoloti/scripts/Make.defs deleted file mode 100644 index e284200c3badc..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/axoloti/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/axoloti/scripts/kernel-space.ld b/boards/arm/stm32/axoloti/scripts/kernel-space.ld deleted file mode 100644 index 64edc323381f0..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/scripts/ld.script b/boards/arm/stm32/axoloti/scripts/ld.script deleted file mode 100644 index c7bb602cb211c..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/ld.script +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and - * 256KiB of SRAM. SRAM is split up into four blocks: - * - * 1) 112KiB of SRAM beginning at address 0x2000:0000 - * 2) 16KiB of SRAM beginning at address 0x2001:c000 - * 3) 64KiB of SRAM beginning at address 0x2002:0000 - * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/scripts/memory.ld b/boards/arm/stm32/axoloti/scripts/memory.ld deleted file mode 100644 index 2815db533fba4..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and - * 256KiB of SRAM. SRAM is split up into four blocks: - * - * 1) 112KiB of SRAM beginning at address 0x2000:0000 - * 2) 16KiB of SRAM beginning at address 0x2001:c000 - * 3) 64KiB of SRAM beginning at address 0x2002:0000 - * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/axoloti/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/axoloti/scripts/user-space.ld b/boards/arm/stm32/axoloti/scripts/user-space.ld deleted file mode 100644 index 0a24aa25f6cec..0000000000000 --- a/boards/arm/stm32/axoloti/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/axoloti/src/CMakeLists.txt b/boards/arm/stm32/axoloti/src/CMakeLists.txt deleted file mode 100644 index c232216905b87..0000000000000 --- a/boards/arm/stm32/axoloti/src/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/axoloti/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_AUDIO_ADAU1961) - list(APPEND SRCS stm32_adau1961.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_USBHOST) - list(APPEND SRCS stm32_usbhost.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/axoloti/src/Make.defs b/boards/arm/stm32/axoloti/src/Make.defs deleted file mode 100644 index e13a8e8280230..0000000000000 --- a/boards/arm/stm32/axoloti/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32/axoloti/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_STM32_FMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_AUDIO_ADAU1961),y) -CSRCS += stm32_adau1961.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_USBHOST),y) -CSRCS += stm32_usbhost.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/axoloti/src/stm32_boot.c b/boards/arm/stm32/axoloti/src/stm32_boot.c deleted file mode 100644 index eda2b87a77412..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_boot.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "axoloti.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_OTGFS) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/axoloti/src/stm32_bringup.c b/boards/arm/stm32/axoloti/src/stm32_bringup.c deleted file mode 100644 index 0232a265bf966..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_bringup.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGHS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "axoloti.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#ifdef HAVE_SDRAM - /* Initialize access to the SDRAM device */ - - ret = stm32_sdram_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_sdram_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_sdio_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_usbhost_initialize failed %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "usbmonitor_start failed %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "btn_lower_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_REI2C - /* Register the rei2c driver */ - - ret = rei2c_initialize("/dev/re0"); - if (ret < 0) - { - syslog(LOG_ERR, "rei2c_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "userled_lower_initialize failed %d\n", ret); - } -#endif - -#ifdef HAVE_ADAU1961 - /* Configure ADAU1961 audio */ - - ret = stm32_adau1961_initialize(1); - if (ret != OK) - { - syslog(LOG_ERR, "stm32_adau1961_initialize failed %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "failed to mount procfs at %s %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/axoloti/src/stm32_buttons.c b/boards/arm/stm32/axoloti/src/stm32_buttons.c deleted file mode 100644 index 2fc688a660c57..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "axoloti.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each axoloti button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. - * EXTI interrupts are configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A HI value means that the key is pressed. */ - - bool pressed = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (pressed) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = - stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/axoloti/src/stm32_extmem.c b/boards/arm/stm32/axoloti/src/stm32_extmem.c deleted file mode 100644 index a1558ff885cd6..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_extmem.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "axoloti.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FMC -#warning "FMC is not enabled" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Axoloti SDRAM GPIO configuration */ - -static const uint32_t g_sdram_config[] = -{ - /* Data lines */ - - GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, - GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, - GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, - GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, - - /* Address lines */ - - GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, - GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, - GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, - GPIO_FMC_A12, - - /* Control lines */ - - GPIO_FMC_BA0, /* ba0 */ - GPIO_FMC_BA1, /* ba1 */ - GPIO_FMC_NBL0, /* ldqm */ - GPIO_FMC_NBL1, /* udqm */ - GPIO_FMC_SDCLK, /* clk */ - GPIO_FMC_SDCKE0_1, /* cke */ - GPIO_FMC_SDNWE_2, /* we */ - GPIO_FMC_SDNCAS, /* cas */ - GPIO_FMC_SDNRAS, /* ras */ - GPIO_FMC_SDNE0_1, /* cs0 */ - GPIO_FMC_SDNE1_2, /* cs1 */ -}; - -#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdram_memtest - * - * Description: - * Test the SDRAM. - * - ****************************************************************************/ - -#define RAND_A 22695477 -#define RAND_C 1 -#define TEST_ITERATIONS 16 - -int stm32_sdram_memtest(void *base, uint32_t size) -{ - volatile int iter; - volatile int i; - - /* Linear write with linear congruential generator values */ - - for (iter = 0; iter < TEST_ITERATIONS; iter++) - { - uint32_t x = iter; - - /* Write */ - - for (i = 0; i < size / 4; i++) - { - x = (RAND_A * x) + RAND_C; - ((volatile uint32_t *)base)[i] = x; - } - - /* Read/verify */ - - x = iter; - for (i = 0; i < size / 4; i++) - { - x = (RAND_A * x) + RAND_C; - if (((volatile uint32_t *)base)[i] != x) - { - return -1; - } - } - } - - /* Scattered byte write at linear congruential generator addresses */ - - for (iter = 0; iter < TEST_ITERATIONS; iter++) - { - uint32_t x = iter; - - /* Write */ - - for (i = 0; i < 1024 * 1024; i++) - { - x = (RAND_A * x) + RAND_C; - ((volatile uint8_t *)base)[x & (size - 1)] = (uint8_t) i; - } - - /* Read/verify */ - - x = iter; - for (i = 0; i < 1024 * 1024; i++) - { - x = (RAND_A * x) + RAND_C; - if (((volatile uint8_t *)base)[x & (size - 1)] != (uint8_t) i) - { - return -1; - } - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sdram_initialize - * - * Description: - * Called from stm32_bringup to initialize external SDRAM access. - * The Axoloti uses an Alliance Memory AS4C4M16SA SDRAM. - * - ****************************************************************************/ - -int stm32_sdram_initialize(void) -{ - uint32_t val; - int i; - - /* Configure SDRAM GPIOs */ - - for (i = 0; i < NUM_SDRAM_GPIOS; i++) - { - stm32_configgpio(g_sdram_config[i]); - } - - /* Enable the FMC */ - - stm32_fmc_enable(); - - /* Go through the SDRAM initialization steps per the reference manual. - * The sdclk period is set to 2 x hclk. That is: 168 /2 = 84 MHz - * This gives a clock period of about 11.9 ns - */ - - /* Step 1: - * Program the memory device features into the FMC_SDCRx register. The - * SDRAM clock frequency, RBURST and RPIPE must be programmed in the - * FMC_SDCR1 register. - */ - - val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ - FMC_SDCR_READBURST | /* read burst enabled */ - FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ - FMC_SDCR_CAS_LATENCY_2 | /* cas latency = 2 cycles */ - FMC_SDCR_NBANKS_4 | /* 4 internal banks */ - FMC_SDCR_WIDTH_16 | /* width = 16 bits */ - FMC_SDCR_ROWS_12 | /* numrows = 12 */ - FMC_SDCR_COLS_8; /* numcols = 8 bits */ - stm32_fmc_sdram_set_control(1, val); - - /* Step 2: - * Program the memory device timing into the FMC_SDTRx register. The - * TRP and TRC timings must be programmed in the FMC_SDTR1 register. - */ - - val = FMC_SDTR_TRCD(2) | /* ras to cas delay 21ns => 2x11.90ns */ - FMC_SDTR_TRP(2) | /* row precharge 21ns => 2x11.90ns */ - FMC_SDTR_TRC(6) | /* row cycle time 63ns => 6x11.9ns */ - FMC_SDTR_TRAS(4) | /* row active time 42ns = >4x11.9ns */ - FMC_SDTR_TWR(4) | /* write to precharge 42ns => 4x11.9ns */ - FMC_SDTR_TXSR(6) | /* exit self refresh 65ns => 6x11.9ns */ - FMC_SDTR_TMRD(2); /* load mode register to active 2 clks */ - stm32_fmc_sdram_set_timing(1, val); - - /* Step 3: - * Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 - * and/or CTB2) in the FMC_SDCMR register to start delivering the clock - * to the memory (SDCKE is driven high). - */ - - val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_CLK_ENABLE; - stm32_fmc_sdram_command(val); - - /* Step 4: - * Wait during the prescribed delay period. Typical delay is around 100 - * μs (refer to the SDRAM datasheet for the required delay after - * power-up). - */ - - nxsched_usleep(1000); - - /* Step 5: - * Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 - * and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All” - * command. - */ - - val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_PALL; - stm32_fmc_sdram_command(val); - - /* Step 6: - * Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 - * and/or CTB2) as well as the number of consecutive Auto-refresh - * commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM - * datasheet for the number of Auto-refresh commands that should be - * issued. Typical number is 8. - */ - - val = FMC_SDCMR_NRFS(5) | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_AUTO_REFRESH; - stm32_fmc_sdram_command(val); - - /* Step 7: - * Configure the MRD field according to your SDRAM device, set the MODE - * bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) - * in the FMC_SDCMR register to issue a "Load Mode Register" command in - * order to program the SDRAM. In particular: - * a) The CAS latency must be selected following configured value in - * FMC_SDCR1/2 registers - * b) The Burst Length (BL) of 1 must be selected by configuring the - * M[2:0] bits to 000 in the mode register (refer to the SDRAM - * datasheet). If the Mode Register is not the same for both SDRAM - * banks, this step has to be repeated twice, once for each bank, - * and the Target Bank bits set accordingly. - */ - - val = FMC_SDCMR_MDR_BURST_LENGTH_2 | - FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL | - FMC_SDCMR_MDR_CAS_LATENCY_2 | - FMC_SDCMR_MDR_MODE_NORMAL | - FMC_SDCMR_MDR_WBL_SINGLE | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_LOAD_MODE; - stm32_fmc_sdram_command(val); - - /* Step 8: - * Program the refresh rate in the FMC_SDRTR register - * The refresh rate corresponds to the delay between refresh cycles. Its - * value must be adapted to SDRAM devices. - */ - - stm32_fmc_sdram_set_refresh_rate(1292); /* (64ms/4096rows) x 84MHz) - 20 */ - - /* Step 9: - * For mobile SDRAM devices, to program the extended mode register it - * should be done once the SDRAM device is initialized: First, a dummy - * read access should be performed while BA1=1 and BA=0 (refer to SDRAM - * address mapping section for BA[1:0] address mapping) in order to select - * the extended mode register instead of Load mode register and then - * program the needed value. - */ - - /* Setting EMRS is optional and we're not bothering ... */ - - /* Enable memory writes for bank 1 */ - - stm32_fmc_sdram_write_protect(1, false); - - /* Wait for the controller to be ready */ - - stm32_fmc_sdram_wait(); - return OK; -} diff --git a/boards/arm/stm32/axoloti/src/stm32_sdio.c b/boards/arm/stm32/axoloti/src/stm32_sdio.c deleted file mode 100644 index 58b957bc57ae6..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_sdio.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "axoloti.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -#undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver. - * First, get an instance of the SDIO interface - */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/axoloti/src/stm32_usbhost.c b/boards/arm/stm32/axoloti/src/stm32_usbhost.c deleted file mode 100644 index c4b42ffc54aca..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_usbhost.c +++ /dev/null @@ -1,265 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_usbhost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otghs.h" -#include "axoloti.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -#define HAVE_USB 1 -#else -#warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#undef HAVE_USB -#endif - -#ifndef CONFIG_AXOLOTI_USBHOST_PRIO -#define CONFIG_AXOLOTI_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_AXOLOTI_USBHOST_STACKSIZE -#define CONFIG_AXOLOTI_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - uinfo("Running\n"); - - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Axoloti board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be provided - * be each platform that implements the STM32 OTG HS host interface - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. Should - * be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor for - * device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - ret = kthread_create("usbhost", CONFIG_AXOLOTI_USBHOST_PRIO, - CONFIG_AXOLOTI_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/axoloti/src/stm32_userleds.c b/boards/arm/stm32/axoloti/src/stm32_userleds.c deleted file mode 100644 index c1aae2069041d..0000000000000 --- a/boards/arm/stm32/axoloti/src/stm32_userleds.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "axoloti.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt b/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt deleted file mode 100644 index 8651bd8562263..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g431b-esc1/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig deleted file mode 100644 index 493be180951fe..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CAN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=23 -CONFIG_STM32_FDCAN1_NTSEG2=8 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig deleted file mode 100644 index 273c6b7a87458..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=10 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=23 -CONFIG_STM32_FDCAN1_NTSEG2=8 -CONFIG_STM32_FDCAN_SOCKET=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig deleted file mode 100644 index b1072cad33010..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y -CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_SHUNTS=2 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y -CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig deleted file mode 100644 index f8aec241b4ba5..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y -CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_SHUNTS=2 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y -CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig deleted file mode 100644 index 46c71c62c2b0a..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g431b-esc1" -CONFIG_ARCH_BOARD_B_G431B_ESC1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431C=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32/b-g431b-esc1/include/board.h deleted file mode 100644 index f5568827ce88d..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/include/board.h +++ /dev/null @@ -1,380 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define STM32_BOARD_XTAL 8000000 /* 8MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL /* Y2 on board */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSI - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSI */ - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE - -/* Main PLL Configuration. - * - * PLL source is HSE = 8MHz - * PLLN = 85, PLLM = 2, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 8MHz x 85 / 2 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(2) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSE */ - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -#ifdef CONFIG_STM32_FDCAN -# ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE -# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) -# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) -# else -# error For now FDCAN supported only if HSE enabled -# endif -#endif - -/* LED definitions **********************************************************/ - -/* The B-G431B-ESC1 has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo G431RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The B-G431B-ESC supports one buttons controllabe by software: - * - * B1 USER: user button connected to the I/O PC10. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* ADC1 */ - -#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA0 */ -#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA1 */ -#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA2 */ -#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA3 */ -#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PB14 */ -#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PF0 */ -#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PB12 */ -#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PB1 */ -#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PB11 */ -#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PB0 */ - -/* USART2 (ST LINK Virtual Console and J3 pads) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */ -#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_4 | GPIO_SPEED_50MHz) /* TIM1 CH1N - PC13 - U low */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1 | GPIO_SPEED_50MHz) /* TIM1 CH2N - PA12 - V low */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3 | GPIO_SPEED_50MHz) /* TIM1 CH3N - PB15 - W low */ - -/* TIM4 QE configuration ****************************************************/ - -#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH1 - PB6 */ -#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH2 - PB7 */ - -/* OPAMP configuration ******************************************************/ - -#define GPIO_OPAMP1_VINM0 (GPIO_OPAMP1_VINM0_0) /* PA3 */ -#define GPIO_OPAMP1_VINP0 (GPIO_OPAMP1_VINP0_0) /* PA1 */ -#define GPIO_OPAMP1_VOUT (GPIO_OPAMP1_VOUT_0) /* PA2 */ - -#define GPIO_OPAMP2_VINM0 (GPIO_OPAMP2_VINM0_0) /* PA5 */ -#define GPIO_OPAMP2_VINP0 (GPIO_OPAMP2_VINP0_0) /* PA7 */ -#define GPIO_OPAMP2_VOUT (GPIO_OPAMP2_VOUT_0) /* PA6 */ - -#define GPIO_OPAMP3_VINM0 (GPIO_OPAMP3_VINM0_0) /* PB2 */ -#define GPIO_OPAMP3_VINP0 (GPIO_OPAMP3_VINP0_0) /* PB0 */ -#define GPIO_OPAMP3_VOUT (GPIO_OPAMP3_VOUT_0) /* PB1 */ - -/* CAN configuration ********************************************************/ - -#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_1 | GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2 | GPIO_SPEED_50MHz) /* PB9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs deleted file mode 100644 index 0a510303baa4b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g431b-esc1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script b/boards/arm/stm32/b-g431b-esc1/scripts/ld.script deleted file mode 100644 index aae24391abfd7..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431CB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431CB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt b/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt deleted file mode 100644 index 76a72b59c7a86..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt +++ /dev/null @@ -1,50 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/b-g431b-esc1/src/Make.defs b/boards/arm/stm32/b-g431b-esc1/src/Make.defs deleted file mode 100644 index 2d49b9a66c91e..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g431b-esc1/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c deleted file mode 100644 index ec5bbf09cf59c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c deleted file mode 100644 index 12e9e93bf6e60..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c deleted file mode 100644 index 3b5cf90e92647..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device - must be before ADC setup */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver - TIM4 */ - - ret = board_qencoder_initialize(0, 4); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c deleted file mode 100644 index 3e7c93b00f732..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c deleted file mode 100644 index 5a8c005e9ba3b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_fdcan.h" -#include "b-g431b-esc1.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM -# define BG431BESC1_CANTERM (true) -#else -# define BG431BESC1_CANTERM (false) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ - - can = stm32_fdcaninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - /* Configure CAN_TERM pin for output */ - - stm32_configgpio(GPIO_CANTERM); - - /* Set CAN_TERM pin high or low */ - - stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); - - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c deleted file mode 100644 index 1841bc9e6cd7c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM -# define BG431BESC1_CANTERM (true) -#else -# define BG431BESC1_CANTERM (false) -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ - - ret = stm32_fdcansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get FDCAN interface %d\n", ret); - return ret; - } - - /* Configure CAN_TERM pin for output */ - - stm32_configgpio(GPIO_CANTERM); - - /* Set CAN_TERM pin high or low */ - - stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); - - return OK; -} diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c deleted file mode 100644 index 6b22e655b382b..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c +++ /dev/null @@ -1,766 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "hardware/stm32g4xxxx_opamp.h" - -#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) -# include "hardware/stm32g4xxxx_pwr.h" -#endif - -#include "stm32_foc.h" - -#ifdef CONFIG_SENSORS_QENCODER -# include "stm32_qencoder.h" -#endif - -#include "arm_internal.h" -#include "b-g431b-esc1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* We don't use phase 2 feedback as it is no connected to ADC1 */ - -#if CONFIG_MOTOR_FOC_SHUNTS != 2 -# error Only 2-shunts configuration is supported -#endif - -/* Configuration specific for L6387ED: - * 1. PWM channels must have positive polarity - * 2. PWM complementary channels must have positive polarity - */ - -#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY -# error -#endif - -#if CONFIG_STM32_TIM1_CH1POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH2POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH3POL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH1NPOL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH2NPOL != 0 -# error -#endif -#if CONFIG_STM32_TIM1_CH3NPOL != 0 -# error -#endif - -/* SYSCFG must be enabled for OPAMP */ - -#ifndef CONFIG_STM32_SYSCFG -# error -#endif - -/* Aux ADC needs DMA enabled and workaround for G4 ADC CHAN0 enabled */ - -#ifdef CONFIG_ADC -# ifndef CONFIG_STM32_ADC1_DMA -# error -# endif -# ifndef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# error -# endif -#endif - -/* REVISIT: */ - -#define PWM_DEADTIME (20) -#define PWM_DEADTIME_NS (500) - -/* Devpath for FOC driver */ - -#define FOC_DEVPATH "/dev/foc0" - -/* Board parameters: - * Current shunt resistance = 0.003 - * PGA gain = 16 - * Current sense gain = -9.14 (inverted current) - * Vbus sense gain = 0.0962 - * Vbus min = 7V - * Vbus max = 25V (6S LiPo battery pack) - * Iout max = 40A peak - * IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 - * ADC_REF_VOLTAGE = 3.3 - * ADC_VAL_MAX = 4095 - * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX - * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = -0.02939 - * VBUS_RATIO = 1/VBUS_gain = 10.4 - */ - -/* OPAMP gain */ - -#define CURRENT_PGA_GAIN 16 - -/* Center-aligned PWM duty cycle limits */ - -#define MAX_DUTY_B16 ftob16(0.95f) - -/* ADC sample time */ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_2p5 -#define VOLTAGE_SAMPLE_TIME ADC_SMPR_2p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_640p5 -#define POT_SAMPLE_TIME ADC_SMPR_640p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS -# define BG431BESC1_FOC_VBUS 1 -#else -# define BG431BESC1_FOC_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT -# define BG431BESC1_FOC_POT 1 -#else -# define BG431BESC1_FOC_POT 0 -#endif - -#define ADC1_REGULAR (BG431BESC1_FOC_VBUS + BG431BESC1_FOC_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -/* ADC2 channels used for BEMF sensing */ - -# define ADC2_INJECTED (CONFIG_MOTOR_FOC_PHASES) -# define ADC2_REGULAR (0) -# define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) -#endif - -/* Check ADC1 configuration */ - -#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND -# if ADC1_INJECTED != (CONFIG_STM32_ADC1_INJECTED_CHAN - 1) -# error -# endif -#else -# if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -# endif -#endif - -#if CONFIG_STM32_ADC1_RESOLUTION != 0 -# error -#endif - -/* Qenco configuration - only TIM4 */ - -#ifdef CONFIG_SENSORS_QENCODER -# ifndef CONFIG_STM32_TIM4_QE -# error -# endif -# if CONFIG_STM32_TIM4_QEPSC != 0 -# error -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev); -static int board_foc_shutdown(struct foc_dev_s *dev); -static int board_foc_calibration(struct foc_dev_s *dev, bool state); -static int board_foc_fault_clear(struct foc_dev_s *dev); -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); -static int board_foc_current_get(struct foc_dev_s *dev, - int16_t *curr_raw, - foc_current_t *curr); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -static int board_foc_voltage_get(struct foc_dev_s *dev, - int16_t *volt_raw, - foc_voltage_t *volt); -#endif -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info); -#ifdef CONFIG_MOTOR_FOC_TRACE -static int board_foc_trace_init(struct foc_dev_s *dev); -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* OPAMP configuration: - * - connected with ADC through output pin (OPAINTOEN=0) - * - Current U+ - OPAMP1_VINP0 (PA1) - * - Current U- - OPAMP1_VINP0 (PA3) - * - Current V+ - OPAMP2_VINP0 (PA7) - * - Current V- - OPAMP2_VINP0 (PA5) - * - Current W+ - OPAMP3_VINP0 (PB0) - * - Current W- - OPAMP3_VINP0 (PB2) - * - * ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN3 (OPAMP1_VOUT/PA2) - * - Current Phase U -> Not used, no ADC1 connection - * - Current Phase W -> ADC1 INJ2 -> ADC1_IN12 (OPAMP3_VOUT/PB12) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN1 (PA0) - * - POT -> ADC1 REG -> ADC1_IN11 (PB12) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase U low -> TIM1_CH1N (PC13) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase V low -> TIM1_CH2N (PA12) - * - Phase W high -> TIM1_CH3 (PA10) - * - Phase W low -> TIM1_CH3N (PB15) - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - 1, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - 11, /* ADC1 REG - POT */ -#endif - 3, /* ADC1 INJ1 - PHASE 1 */ - 12, /* ADC1 INJ2 - PHASE 3 */ -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - GPIO_ADC1_IN1, -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - GPIO_ADC1_IN11, -#endif - GPIO_ADC1_IN3, - GPIO_ADC1_IN12, -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS - { - .channel = 1, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT - { - .channel = 11, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 3, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 12, - .sample_time = CURRENT_SAMPLE_TIME - }, -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -static uint8_t g_adc2_chan[] = -{ - 17, /* ADC2 INJ1 - PHASE 1 */ - 5, /* ADC2 INJ2 - PHASE 2 */ - 14, /* ADC2 INJ3 - PHASE 3 */ -}; - -static uint32_t g_adc2_pins[] = -{ - GPIO_ADC2_IN17, - GPIO_ADC2_IN5, - GPIO_ADC2_IN14, -}; - -/* ADC2 sample time configuration */ - -static adc_channel_t g_adc2_stime[] = -{ - { - .channel = 17, - .sample_time = VOLTAGE_SAMPLE_TIME - }, - { - .channel = 5, - .sample_time = VOLTAGE_SAMPLE_TIME - }, - { - .channel = 14, - .sample_time = VOLTAGE_SAMPLE_TIME - }, -}; - -/* Board specific ADC configuration for BEMF */ - -static struct stm32_foc_adc_s g_vadc_cfg = -{ - .chan = g_adc2_chan, - .pins = g_adc2_pins, - .stime = g_adc2_stime, - .nchan = ADC2_NCHANNELS, - .regch = ADC2_REGULAR, - .intf = 2 -}; -#endif - -/* Board specific ops */ - -static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = -{ - .setup = board_foc_setup, - .shutdown = board_foc_shutdown, - .calibration = board_foc_calibration, - .fault_clear = board_foc_fault_clear, - .pwm_start = board_foc_pwm_start, - .current_get = board_foc_current_get, -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - .voltage_get = board_foc_voltage_get, -#endif - .info_get = board_foc_info_get, -#ifdef CONFIG_MOTOR_FOC_TRACE - .trace_init = board_foc_trace_init, - .trace = board_foc_trace -#endif -}; - -/* Board specific data */ - -static struct stm32_foc_board_data_s g_stm32_foc_board_data = -{ - .adc_cfg = &g_adc_cfg, -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - .vadc_cfg = &g_vadc_cfg, -#endif - .pwm_dt = PWM_DEADTIME -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc_board = -{ - .data = &g_stm32_foc_board_data, - .ops = &g_stm32_foc_board_ops, -}; - -/* Global pointer to the upper FOC driver */ - -static struct foc_dev_s *g_foc_dev = NULL; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_foc_setup - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev) -{ - uint32_t regval = 0; - - DEBUGASSERT(dev); - - UNUSED(dev); - - /* OPAMP1/2/3 pins: - * OPAMP1_VINM - PA3 (VINM0) - * OPAMP1_VINP - PA1 (VINP0) - * OPAMP2_VINM - PA5 (VINM0) - * OPAMP2_VINP - PA7 (VINP0) - * OPAMP3_VINM - PB2 (VINM0) - * OPAMP3_VINP - PB0 (VINP0) - */ - - /* Configure GPIO */ - - stm32_configgpio(GPIO_OPAMP1_VINM0); - stm32_configgpio(GPIO_OPAMP1_VINP0); - stm32_configgpio(GPIO_OPAMP1_VOUT); - stm32_configgpio(GPIO_OPAMP2_VINM0); - stm32_configgpio(GPIO_OPAMP2_VINP0); - stm32_configgpio(GPIO_OPAMP2_VOUT); - stm32_configgpio(GPIO_OPAMP3_VINM0); - stm32_configgpio(GPIO_OPAMP3_VINP0); - stm32_configgpio(GPIO_OPAMP3_VOUT); -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - stm32_configgpio(GPIO_GPIOBEMF); -#endif - - /* Configure OPAMP inputs */ - - regval += (OPAMP_CSR_VPSEL_VINP0 | OPAMP_CSR_VMSEL_PGA); - - /* PGA mode, non-inverting configuration with external bias on VINM0 */ - -#if CURRENT_PGA_GAIN == 16 - regval += ((0b01011 << OPAMP_CSR_PGAGAIN_SHIFT) & OPAMP_CSR_PGAGAIN_MASK); -#else -# error Not supported -#endif - - /* Enable high-speed mode */ - - regval += OPAMP_CSR_OPAHSM; - - /* Write configuration */ - - putreg32(regval, STM32_OPAMP1_CSR); - putreg32(regval, STM32_OPAMP2_CSR); - putreg32(regval, STM32_OPAMP3_CSR); - - /* Enable OPAMPs in separate write */ - - regval += OPAMP_CSR_OPAMPEN; - - putreg32(regval, STM32_OPAMP1_CSR); - putreg32(regval, STM32_OPAMP2_CSR); - putreg32(regval, STM32_OPAMP3_CSR); - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - /* Keep GPIO_BEMF low to create BEMF voltage divider */ - - stm32_gpiowrite(GPIO_GPIOBEMF, false); -#endif - - return OK; -} - -/**************************************************************************** - * Name: board_foc_shutdown - ****************************************************************************/ - -static int board_foc_shutdown(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_calibration - ****************************************************************************/ - -static int board_foc_calibration(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_fault_clear - ****************************************************************************/ - -static int board_foc_fault_clear(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_pwm_start - ****************************************************************************/ - -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_current_get - ****************************************************************************/ - -static int board_foc_current_get(struct foc_dev_s *dev, - int16_t *curr_raw, - foc_current_t *curr) -{ - DEBUGASSERT(dev); - DEBUGASSERT(curr_raw); - DEBUGASSERT(curr); - - /* Get currents */ - - curr[0] = curr_raw[0]; - curr[2] = curr_raw[1]; - - /* Phase 2 reconstruction */ - - curr[1] = -(curr_raw[0] + curr_raw[1]); - - return OK; -} - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE -/**************************************************************************** - * Name: board_foc_voltage_get - ****************************************************************************/ - -static int board_foc_voltage_get(struct foc_dev_s *dev, - int16_t *volt_raw, - foc_voltage_t *volt) -{ - DEBUGASSERT(dev); - DEBUGASSERT(volt_raw); - DEBUGASSERT(volt); - - /* Get voltages */ - - volt[0] = volt_raw[0]; - volt[1] = volt_raw[1]; - volt[2] = volt_raw[2]; - - return OK; -} -#endif - -/**************************************************************************** - * Name: board_foc_info_get - ****************************************************************************/ - -static int board_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) -{ - DEBUGASSERT(dev); - DEBUGASSERT(info); - - UNUSED(dev); - - /* PWM */ - - info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; - info->hw_cfg.pwm_max = MAX_DUTY_B16; - - /* ADC BEMF */ - -#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE - info->hw_cfg.bemf_scale = 0; /* TODO */ -#endif - - /* ADC Current - dynamic current scale not supported */ - - info->hw_cfg.iphase_max = 40000; - info->hw_cfg.iphase_scale = -2939; - - return OK; -} - -#ifdef CONFIG_MOTOR_FOC_TRACE -/**************************************************************************** - * Name: board_foc_trace_init - ****************************************************************************/ - -static int board_foc_trace_init(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* Not supported */ - - return -1; -} - -/**************************************************************************** - * Name: board_foc_trace - ****************************************************************************/ - -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - struct foc_dev_s *foc = NULL; - int ret = OK; - - /* Initialize only once */ - - if (g_foc_dev == NULL) - { -#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) - /* Disable USB Type-C and Power Delivery Dead Battery */ - - modifyreg32(STM32_PWR_CR3, 0, PWR_CR3_UCPD1_DBDIS); -#endif - -#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_STM32_QENCODER_INDEX_PIN) - /* Configure encoder index GPIO */ - - ret = stm32_qe_index_init(4, QENCODER_TIM4_INDEX_GPIO); - if (ret < 0) - { - mtrerr("Failed to register encoder index pin %d\n", ret); - ret = -EACCES; - goto errout; - } -#endif - - /* Initialize arch specific FOC lower-half */ - - foc = stm32_foc_initialize(0, &g_stm32_foc_board); - if (foc == NULL) - { - ret = -errno; - mtrerr("Failed to initialize STM32 FOC: %d\n", ret); - goto errout; - } - - DEBUGASSERT(foc->lower); - - /* Register FOC device */ - - ret = foc_register(FOC_DEVPATH, foc); - if (ret < 0) - { - mtrerr("Failed to register FOC device: %d\n", ret); - goto errout; - } - - /* Store pointer to driver */ - - g_foc_dev = foc; - } - -errout: - return ret; -} - -#ifdef CONFIG_ADC -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc = NULL; - int ret = OK; - static bool initialized = false; - - /* Initialize only once */ - - if (initialized == false) - { - if (g_foc_dev == NULL) - { - mtrerr("Failed to get g_foc_dev device\n"); - ret = -EACCES; - goto errout; - } - - /* Register regular channel ADC */ - - adc = stm32_foc_adcget(g_foc_dev); - if (adc == NULL) - { - mtrerr("Failed to get ADC device: %d\n", ret); - goto errout; - } - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - mtrerr("adc_register failed: %d\n", ret); - goto errout; - } - - initialized = true; - } - -errout: - return ret; -} -#endif diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c b/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c deleted file mode 100644 index 2606087a8fa8c..0000000000000 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "b-g431b-esc1.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt deleted file mode 100644 index f0b7d812e4415..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig deleted file mode 100644 index 3625c3af8d889..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DRIVERS_SMPS=y -CONFIG_EXAMPLES_SMPS=y -CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" -CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBDSP=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y -CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=128 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_INJECTED_CHAN=2 -CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG2=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_DEADTIME=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_DT=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH2=y -CONFIG_STM32_HRTIM_TIMD=y -CONFIG_STM32_HRTIM_TIMD_DT=y -CONFIG_STM32_HRTIM_TIMD_PWM=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig deleted file mode 100644 index 0b9c303e3a46d..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig deleted file mode 100644 index b6bc84bd10ac8..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="b-g474e-dpow1" -CONFIG_ARCH_BOARD_B_G474E_DPOW1=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/b-g474e-dpow1/include/board.h b/boards/arm/stm32/b-g474e-dpow1/include/board.h deleted file mode 100644 index 03a0e8edd1a70..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/include/board.h +++ /dev/null @@ -1,256 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#undef STM32_BOARD_XTAL /* Not installed by default */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#undef STM32_HSE_FREQUENCY /* Not installed by default */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The B-G474E-DPOW1 Discovery kit has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 (Blue) */ -#define BOARD_LED2 1 /* User LD3 (Orange) */ -#define BOARD_LED3 2 /* User LD4 (Green) */ -#define BOARD_LED4 3 /* User LD5 (Red)*/ -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs - * on the board. The following definitions describe how NuttX controls the - * LEDs: - * - * |--------------------|-------------------------|------------| - * | SYMBOL | Meaning | LED states | - * |--------------------|-------------------------|------------| - * | LED_STARTED | NuttX has been started | 0 0 0 0 | - * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | - * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | - * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | - * | LED_INIRQ | In an interrupt | No change | - * | LED_SIGNAL | In a signal handler | No change | - * | LED_ASSERTION | An assertion failed | No change | - * | LED_PANIC | The system has crashed | 0 B 0 0 | - * | LED_IDLE | STM32 is in sleep mode | Not used | - * |--------------------|-------------------------|------------| - * - * LED states legend: - * 0 = off - * 1 = on - * B = blink - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* Alternate function pin selections ****************************************/ - -/* USART3 (ST LINK V3E Virtual Console) */ - -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ -#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ - -/* Board configuration for SMPS example: - * PB12 - HRTIM1_CHC1 - * PB13 - HRTIM1_CHC2 - * PB14 - HRTIM1_CHD1 - * PB15 - HRTIM1_CHD2 - * VIN - ADC Channel 2 (PA1) - * VOUT - ADC Channel 4 (PA3) - */ - -#if defined(CONFIG_EXAMPLES_SMPS) - -/* HRTIM configuration ******************************************************/ - -/* Timer C configuration - Buck operations */ - -#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMC_MODE HRTIM_MODE_CONT -#define HRTIM_TIMC_UPDATE 0 -#define HRTIM_TIMC_RESET 0 - -#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMC_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMC_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMC_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMC_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMC_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMC_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMC_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMC_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMC_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -/* Timer D configuration - Boost operations */ - -#define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMD_MODE HRTIM_MODE_CONT -#define HRTIM_TIMD_UPDATE 0 -#define HRTIM_TIMD_RESET 0 - -#define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMD_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMD_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMD_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMD_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMD_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMD_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMD_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMD_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMD_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_CC4 - -/* DMA channels *************************************************************/ - -#endif /* CONFIG_EXAMPLES_SMPS */ - -/* HRTIM */ - -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 - -#endif /* __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs deleted file mode 100644 index 57c27ead5ec10..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script b/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script deleted file mode 100644 index 64c1953f7fcef..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu b/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu deleted file mode 100644 index d27ca98a1445b..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. The FLASH bootloader is located there and - * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k - * if dual bank mode), so our executable will begin at 0x0800:6000, leaving - * 488KiB. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt b/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt deleted file mode 100644 index 87e3c2b6ee9b7..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_DRIVERS_SMPS) - list(APPEND SRCS stm32_smps.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs b/boards/arm/stm32/b-g474e-dpow1/src/Make.defs deleted file mode 100644 index e91f93fd7a573..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/b-g474e-dpow1/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_DRIVERS_SMPS),y) -CSRCS += stm32_smps.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c deleted file mode 100644 index 1591f068d43bd..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "b-g474e-dpow1.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, true); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, true); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, true); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, false); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, false); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, false); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c deleted file mode 100644 index f901b448b028d..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "b-g474e-dpow1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_ARCH_LEDS) - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_DRIVERS_SMPS - /* Initialize smps and register the smps driver */ - - ret = stm32_smps_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c deleted file mode 100644 index b2496a63d859b..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c +++ /dev/null @@ -1,1262 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_adc.h" - -#include - -#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) - -#ifndef CONFIG_LIBDSP -# error CONFIG_LIBDSP is required -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) -# error "SMPS example requires HRTIM1 support" -#endif - -#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) -# error "SMPS example requires ADC1 support" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ADC1 channels used in this example */ - -#define ADC1_NCHANNELS 2 - -/* ADC1 injected channels numeration */ - -#define V_IN_ADC_INJ_CHANNEL 0 -#define V_OUT_ADC_INJ_CHANNEL 1 - -/* Voltage reference for ADC */ - -#define ADC_REF_VOLTAGE ((float)3.3) - -/* ADC resolution */ - -#define ADC_VAL_MAX 4095 - -/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ - -#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) - -/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ - -#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) - -/* Some absolute limits */ - -#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 -#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 -#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 - -#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA -# error "Output current limit great than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV -# error "Output voltage limit greater than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV -# error "Input voltage limit greater than absolute limit!" -#endif - -/* Maximum output voltage for boost converter in float */ - -#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) - -/* At this time only PID controller implemented */ - -#define SMPS_CONTROLLER_PID 1 - -/* Converter's finite accuracy */ - -#define SMPS_VOLTAGE_ACCURACY ((float)0.01) - -/* Buck-boost mode threshold */ - -#define SMPS_BUCKBOOST_RANGE ((float)0.5) - -/* PID controller configuration */ - -#define PID_KP ((float)1.0) -#define PID_KI ((float)0.1) -#define PID_KD ((float)0.0) - -/* Converter frequencies: - * - TIMC_PWM_FREQ - buck converter 250kHz - * - TIMD_PWM_FREQ - boost converter 250kHz - */ - -#define TIMC_PWM_FREQ 250000 -#define TIMD_PWM_FREQ 250000 - -/* Deadtime configuration */ - -#define DT_RISING 0x0B0 -#define DT_FALLING 0x0B0 - -/* Helper macros */ - -#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ - HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMC_CH1|HRTIM_OUT_TIMC_CH2| \ - HRTIM_OUT_TIMD_CH1|HRTIM_OUT_TIMD_CH2, state); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Current converter mode */ - -enum converter_mode_e -{ - CONVERTER_MODE_INIT, /* Initial mode */ - CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ - CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ - CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ -}; - -/* SMPS lower drivers structure */ - -struct smps_lower_dev_s -{ - struct hrtim_dev_s *hrtim; /* PWM generation */ - struct stm32_adc_dev_s *adc; /* input and output voltage sense */ - struct comp_dev_s *comp; /* not used in this demo - only as reference */ - struct dac_dev_s *dac; /* not used in this demo - only as reference */ - struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ -}; - -/* Private data for smps */ - -struct smps_priv_s -{ - uint8_t conv_mode; /* Converter mode */ - uint16_t v_in_raw; /* Voltage input RAW value */ - uint16_t v_out_raw; /* Voltage output RAW value */ - float v_in; /* Voltage input real value in V */ - float v_out; /* Voltage output real value in V */ - bool running; /* Running flag */ - pid_controller_f32_t pid; /* PID controller */ - float *c_limit_tab; /* Current limit tab */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev); -static int smps_shutdown(struct smps_dev_s *dev); -static int smps_start(struct smps_dev_s *dev); -static int smps_stop(struct smps_dev_s *dev); -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param); -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits); -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state); -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); -static int smps_fault_get(struct smps_dev_s *dev, - uint8_t *fault); -static int smps_fault_clean(struct smps_dev_s *dev, - uint8_t fault); -static int smps_ioctl(struct smps_dev_s *dev, int cmd, - unsigned long arg); - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct smps_lower_dev_s g_smps_lower; -struct smps_priv_s g_smps_priv; -struct smps_s g_smps; - -struct smps_ops_s g_smps_ops = -{ - .setup = smps_setup, - .shutdown = smps_shutdown, - .start = smps_start, - .stop = smps_stop, - .params_set = smps_params_set, - .mode_set = smps_mode_set, - .limits_set = smps_limits_set, - .fault_set = smps_fault_set, - .state_get = smps_state_get, - .fault_get = smps_fault_get, - .fault_clean = smps_fault_clean, - .ioctl = smps_ioctl -}; - -struct smps_dev_s g_smps_dev = -{ - .ops = &g_smps_ops, - .priv = &g_smps, - .lower = NULL -}; - -/* ADC configuration: - * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) - * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) - * - * ADC channels configured in injected mode. - * - * Transistors configuration in buck mode: - * - T6 - ON - * - T2 - OFF - * - T5 and T1 - buck operation - * Transistors configuration in boost mode: - * - T5 - ON - * - T1 - OFF - * - T6 and T2 - boost operation - * Transistors configuration in buck-boost mode: - * - T5 and T1 - buck operation - * - T6 and T2 - boost operation - * - * HRTIM outputs configuration: - * - T5 -> PB12 -> HRTIM_CHC1 - * - T6 -> PB14 -> HRTIM_CHD1 - * - T1 -> PB13 -> HRTIM_CHC2 - * - T2 -> PB15 -> HRTIM_CHD2 - */ - -/* ADC channel list */ - -static const uint8_t g_adc1chan[ADC1_NCHANNELS] = -{ - 2, - 4 -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_adc1pins[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN2_0, /* PA1 - V_IN */ - GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: smps_setup - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct hrtim_dev_s *hrtim = NULL; - struct stm32_adc_dev_s *adc = NULL; - struct smps_priv_s *priv; - struct adc_channel_s channels[ADC1_NCHANNELS]; - struct adc_sample_time_s stime; - int ret = OK; - int i = 0; - - /* Initialize smps structure */ - - smps->opmode = SMPS_OPMODE_INIT; - smps->state.state = SMPS_STATE_INIT; - smps->priv = &g_smps_priv; - - /* Check lower half drivers */ - - hrtim = lower->hrtim; - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get hrtim "); - ret = ERROR; - goto errout; - } - - adc = lower->adc; - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC lower level interface"); - ret = ERROR; - goto errout; - } - - /* Update ADC sample time */ - - for (i = 0; i < ADC1_NCHANNELS; i += 1) - { - channels[i].sample_time = ADC_SMPR_92p5; - channels[i].channel = g_adc1chan[i]; - } - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ADC1_NCHANNELS; - stime.channel = channels; - - STM32_ADC_SAMPLETIME_SET(adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(adc); - - /* TODO: create current limit table */ - - UNUSED(priv); - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_shutdown - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_shutdown(struct smps_dev_s *dev) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - - /* Stop smps if running */ - - if (priv->running == true) - { - smps_stop(dev); - } - - /* Reset smps structure */ - - memset(smps, 0, sizeof(struct smps_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_start - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_start(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - volatile uint64_t per = 0; - uint64_t fclk = 0; - int ret = OK; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Reset SMPS private structure */ - - memset(priv, 0, sizeof(struct smps_priv_s)); - -#ifdef SMPS_CONTROLLER_PID - /* Initialize PID controller */ - - pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); - - /* Set PID controller saturation */ - - pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); - - /* Reset PI integral if saturated */ - - pi_ireset_enable(&priv->pid, true); -#endif - - /* Get TIMC period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMC); - per = fclk / TIMC_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timc pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMC_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMC period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMC, (uint16_t)per); - - /* Get TIMD period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMD); - per = fclk / TIMD_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timd pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMD_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMD period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMD, (uint16_t)per); - - /* ADC trigger on TIMC CMP4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP4, 10000); - - /* Configure TIMER C and TIMER D deadtime mode - * - * NOTE: In deadtime mode we have to configure output 1 only - * (SETx1, RSTx1), output 2 configuration is not significant. - */ - - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - - /* Set T5 and T2 to a low state. - * Deadtime mode force T1 and T6 to a high state. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_RST_PER); - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_RST_PER); - - /* Set running flag */ - - priv->running = true; - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); - - /* Enable ADC JEOS interrupts */ - - STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); - - /* Enable ADC12 interrupts */ - - up_enable_irq(STM32_IRQ_ADC12); - - /* Start injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, true); - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_stop - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_stop(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Stop injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, false); - - /* Disable ADC JEOS interrupts */ - - STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); - - /* Disable ADC12 interrupts */ - - up_disable_irq(STM32_IRQ_ADC12); - - /* Reset running flag */ - - priv->running = false; - - return OK; -} - -/**************************************************************************** - * Name: smps_params_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only output voltage */ - - smps->param.v_out = param->v_out; - - /* REVISIT: use current and power parameters ? */ - - if (param->i_out > 0) - { - pwrwarn("WARNING: Output current parameters not used in this demo\n"); - } - - if (param->p_out > 0) - { - pwrwarn("WARNING: Output power parameters not used in this demo\n"); - } - - return ret; -} - -/**************************************************************************** - * Name: smps_mode_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only constant voltage mode supported */ - - if (mode == SMPS_OPMODE_CV) - { - smps->opmode = mode; - } - else - { - pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); - ret = ERROR; - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_limits_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Some assertions */ - - if (limits->v_out <= 0) - { - pwrerr("ERROR: Output voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_in <= 0) - { - pwrerr("ERROR: Input voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->i_out <= 0) - { - pwrerr("ERROR: Output current limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) - { - limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output voltage limiit > SMPS absolute output voltage " - "limit. Set output voltage limit to %.2f.\n", - limits->v_out); - } - - if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) - { - limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS input voltage limiit > SMPS absolute input voltage " - "limit. Set input voltage limit to %.2f.\n", - limits->v_in); - } - - if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) - { - limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output current limiit > SMPS absolute output current " - "limit. Set output current limit to %.2f.\n", - limits->i_out); - } - - /* Set output voltage limit */ - - smps->limits.v_out = limits->v_out; - - /* Set input voltage limit */ - - smps->limits.v_in = limits->v_in; - - /* Set current limit */ - - smps->limits.i_out = limits->i_out; - - /* Lock limits */ - - smps->limits.lock = true; - -errout: - return ret; -} - -/**************************************************************************** - * Name: smps_state_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - - /* Copy locally stored feedbacks data to status structure */ - - smps->state.fb.v_in = g_smps_priv.v_in; - smps->state.fb.v_out = g_smps_priv.v_out; - - /* Return state structure to caller */ - - memcpy(state, &smps->state, sizeof(struct smps_state_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_fault_set - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_fault_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_fault_clean - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_state_get - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_controller - * - * Description: - * - * Returned Value: - * - ****************************************************************************/ - -static float smps_controller(struct smps_priv_s *priv, float err) -{ - float out = 0.0; - -#ifdef SMPS_CONTROLLER_PID - out = pid_controller(&priv->pid, err); -#else -# error "At this time only PID controller implemented" -#endif - - return out; -} - -/**************************************************************************** - * Name: smps_duty_set - * - * Description: - * - * Returned Value: - * - ****************************************************************************/ - -static void smps_duty_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - float out) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - uint8_t mode = priv->conv_mode; - uint16_t cmp = 0; - float duty = 0.0; - uint16_t per = 0; - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - /* Do nothing */ - - break; - } - - case CONVERTER_MODE_BUCK: - { - if (out >= priv->v_in) out = priv->v_in; - if (out < 0.0) out = 0.0; - - duty = out / priv->v_in; - -#warning TODO: current limit in buck mode - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - cmp = (uint16_t)(per * duty); - - if (cmp > per - 30) cmp = per - 30; - - /* Set T5 duty cycle. T1 is complementary to T5 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BOOST: - { - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T2 duty cycle. T6 is complementary to T2 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Buck converter is set to fixed duty cycle (80%). - * Now we need set boost converter - */ - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in buck boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T2 duty cycle. T6 is complementary to T2 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } -} - -/**************************************************************************** - * Name: smps_conv_mode_set - * - * Description: - * Change converter mode (buck/boost/buck-boost). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - - /* Disable all outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - break; - } - - case CONVERTER_MODE_BUCK: - { - /* Set T2 low (T6 high) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_PER); - - /* Set T5 to a high state on PER and reset on CMP1. - * T1 is complementary to T5. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BOOST: - { - /* Set T4 high (T11 low) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_NONE); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, - 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, - HRTIM_TIMER_TIMC))); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } - - /* Set mode in private data */ - - priv->conv_mode = mode; - - /* Enable outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); -} - -/**************************************************************************** - * Name: adc12_handler - ****************************************************************************/ - -static void adc12_handler(void) -{ - struct smps_dev_s *dev = &g_smps_dev; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct smps_lower_dev_s *lower = dev->lower; - struct stm32_adc_dev_s *adc = lower->adc; - uint32_t pending; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - float err; - float out; - uint8_t mode; - - pending = STM32_ADC_INT_GET(adc); - - if (pending & ADC_INT_JEOC && priv->running == true) - { - /* Get raw ADC values */ - - priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); - priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); - - /* Convert raw values to real values */ - - priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; - priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; - - /* According to measured voltages we set converter - * in appropriate mode - */ - - if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage greater than input voltage - set - * boost converter - */ - - mode = CONVERTER_MODE_BOOST; - } - - else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage lower than input voltage - set - * buck converter - */ - - mode = CONVERTER_MODE_BUCK; - } - - else - { - /* Desired output voltage close to input voltage - set - * buck-boost converter - */ - - mode = CONVERTER_MODE_BUCKBOOST; - } - - /* Configure converter to the new mode if needed */ - - if (priv->conv_mode != mode) - { - smps_conv_mode_set(priv, lower, mode); - } - - /* Get regulator error */ - - err = smps->param.v_out - priv->v_out; - - if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) - { - /* PID controller */ - - out = smps_controller(priv, err); - - /* Update duty cycle */ - - smps_duty_set(priv, lower, out); - } - } - - /* Clear pending */ - - STM32_ADC_INT_ACK(adc, pending); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_smps_setup - * - * Description: - * Initialize SMPS driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_smps_setup(void) -{ - struct smps_lower_dev_s *lower = &g_smps_lower; - struct smps_dev_s *smps = &g_smps_dev; - struct hrtim_dev_s *hrtim = NULL; - struct adc_dev_s *adc = NULL; - static bool initialized = false; - int ret = OK; - int i; - - /* Initialize only once */ - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1pins[i]); - } - - /* Get the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC %d interface\n", 1); - return -ENODEV; - } - - /* Initialize SMPS lower driver interfaces */ - - lower->hrtim = hrtim; - lower->adc = adc->ad_priv; - lower->comp = NULL; - lower->dac = NULL; - lower->opamp = NULL; - - /* Attach ADC12 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Setup ADC hardware */ - - adc->ad_ops->ao_setup(adc); - - /* We do not need register character drivers for SMPS lower - * peripherals. All control should be done via SMPS character - * driver. - */ - - ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); - if (ret < 0) - { - pwrerr("ERROR: smps_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - -errout: - return ret; -} - -#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c b/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c deleted file mode 100644 index badccd03daae3..0000000000000 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "b-g474e-dpow1.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * Initialize the user LEDs before use. Note: For this function to be - * available to user application logic, CONFIG_ARCH_LEDS must not be - * defined. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Allow user application logic to control LEDs one at a time. Note: For - * this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * led: Index to the LED, which may be one of the defines BOARD_LED1, - * BOARD_LED2, BOARD_LED3, or BOARD_LED4. - * ledon: true to turn the LED on, false to turn it off. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, ledon); - break; - - case BOARD_LED2: - stm32_gpiowrite(GPIO_LED2, ledon); - break; - - case BOARD_LED3: - stm32_gpiowrite(GPIO_LED3, ledon); - break; - - case BOARD_LED4: - stm32_gpiowrite(GPIO_LED4, ledon); - break; - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Allow user application logic to control all LEDs in one function call. - * Note: For this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * ledset: Bitmask indicating the new state for all LEDs, where a set bit - * indicates LED on and a clear bit indicates LED off. To - * construct the bitmask, using a bitwise OR of the defines - * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or - * BOARD_LED4_BIT. - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32/clicker2-stm32/CMakeLists.txt deleted file mode 100644 index 40b17adb6cbf6..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/clicker2-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig deleted file mode 100644 index ab40dd86d1e54..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/clicker2-stm32/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig deleted file mode 100644 index 5ac5c06b41f9b..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ /dev/null @@ -1,108 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig deleted file mode 100644 index 167735240cfcd..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig deleted file mode 100644 index 54fe586554946..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ /dev/null @@ -1,93 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_TELNET=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STAR=y -CONFIG_NET_STARHUB=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig deleted file mode 100644 index 5278c9e1f68fd..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ /dev/null @@ -1,109 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="MRF24J40" -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STAR=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig deleted file mode 100644 index 241e636355d92..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig deleted file mode 100644 index 9ba8e7f754ded..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=3 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_INTBUFSIZE=396 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig deleted file mode 100644 index 47920cf847c04..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ /dev/null @@ -1,104 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="clicker2-stm32" -CONFIG_ARCH_BOARD_CLICKER2_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_CLICKER2_STM32_MB1_XBEE=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 -CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_NETTEST_TARGET2=y -CONFIG_EXAMPLES_UDP=y -CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 -CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 -CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 -CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 -CONFIG_EXAMPLES_UDP_TARGET2=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_XBEE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LIBC_HOSTNAME="XBee" -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=160 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/clicker2-stm32/include/board.h b/boards/arm/stm32/clicker2-stm32/include/board.h deleted file mode 100644 index e13c619319b26..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/include/board.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC - * crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The Mikroe Clicker2 STM32 has two user controllable LEDs: - * - * LD1 - PE12, Active high output illuminates - * LD2 - PE15, Active high output illuminates - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the Clicker2 for STM32. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt N/C ON - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 3 -#define LED_ASSERTION 3 -#define LED_PANIC 4 - -/* Button definitions *******************************************************/ - -/* The Mikroe Clicker2 STM32 has two buttons available to software: - * - * T2 - PE0, Low sensed when pressed - * T3 - PA10, Low sensed when pressed - */ - -#define BUTTON_T2 0 -#define BUTTON_T3 1 -#define NUM_BUTTONS 2 - -#define BUTTON_T2_BIT (1 << BUTTON_T2) -#define BUTTON_T3_BIT (1 << BUTTON_T3) - -/* Alternate function pin selections ****************************************/ - -/* U[S]ARTs - * - * USART2 - mikroBUS1 - * USART3 - mikroBUS2 - * - * Assuming RS-232 connverted connected on mikroMB1/12 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ - -/* SPI - * - * SPI2 - mikroBUS2 - * SPI3 - mikroBUS1 - */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PC12 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PC11 */ -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PB15 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PB14 */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ - -/* I2C - * - * I2C2 - mikroBUS2 - * I2C3 - mikroBUS1 - */ - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) /* PB10 */ -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) /* PB11 */ - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) /* PC9 */ - -/* Analog - * - * mikroBUS1 ADC: PA2-MB1_AN - * mikroBUS1 ADC: PA3-MB2_AN - */ - -/* PWM - * - * mikroBUS1 ADC: PE9-MB1-PWM (TIM1, channel 1) - * mikroBUS1 ADC: PD12-MB2-PWM (TIM4, channel 1) - */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) /* PD12 */ - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/clicker2-stm32/kernel/Makefile b/boards/arm/stm32/clicker2-stm32/kernel/Makefile deleted file mode 100644 index 5807644db2b12..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c deleted file mode 100644 index 0274e2ab46574..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by - * the linker script. - */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32/clicker2-stm32/scripts/Make.defs deleted file mode 100644 index c20f435cec414..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld b/boards/arm/stm32/clicker2-stm32/scripts/flash.ld deleted file mode 100644 index 31444fc0659b4..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : - { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld b/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld deleted file mode 100644 index d67c215eb7eb5..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : - { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : - { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld b/boards/arm/stm32/clicker2-stm32/scripts/memory.ld deleted file mode 100644 index 75ae8743baf4c..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld b/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld deleted file mode 100644 index 1e89ef45fd06f..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : - { - *(.userspace) - } > uflash - - .text : - { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : - { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : - { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : - { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt b/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt deleted file mode 100644 index cb3d46c6c34a6..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt +++ /dev/null @@ -1,65 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_IEEE802154_MRF24J40) - list(APPEND SRCS stm32_mrf24j40.c) -endif() - -if(CONFIG_IEEE802154_XBEE) - list(APPEND SRCS stm32_xbee.c) -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_FS_AUTOMOUNTER) - list(APPEND SRCS stm32_automount.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/clicker2-stm32/src/Make.defs b/boards/arm/stm32/clicker2-stm32/src/Make.defs deleted file mode 100644 index 6079d7268eae5..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/clicker2-stm32/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_IEEE802154_MRF24J40),y) -CSRCS += stm32_mrf24j40.c -endif - -ifeq ($(CONFIG_IEEE802154_XBEE),y) -CSRCS += stm32_xbee.c -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_FS_AUTOMOUNTER),y) -CSRCS += stm32_automount.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c deleted file mode 100644 index 0f3fa6dd71284..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c deleted file mode 100644 index ea8eaced9400d..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on - * board the Clicker2 for STM32. The following definitions describe how - * NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt N/C ON - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - * - * VALUE - * -------------------------------------------- -------- -------- - * 0 OFF OFF - * 1 ON OFF - * 2 N/C ON - * 3 N/C N/C - * 4 OFF ON - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void board_led1_on(int led) -{ - bool ledon = false; - - switch (led) - { - case 0: /* LED1=OFF */ - case 4: /* LED1=OFF */ - break; - - case 1: /* LED1=ON */ - ledon = true; - break; - - case 2: /* LED1=N/C */ - case 3: /* LED1=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED1, ledon); -} - -static void board_led2_on(int led) -{ - bool ledon = false; - - switch (led) - { - case 0: /* LED2=OFF */ - case 1: /* LED2=OFF */ - break; - - case 2: /* LED2=ON */ - case 4: /* LED2=ON */ - ledon = true; - break; - - case 3: /* LED2=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED2, ledon); -} - -static void board_led1_off(int led) -{ - switch (led) - { - case 0: /* LED1=OFF */ - case 1: /* LED1=OFF */ - case 4: /* LED1=OFF */ - break; - - case 2: /* LED1=N/C */ - case 3: /* LED1=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED1, false); -} - -static void board_led2_off(int led) -{ - switch (led) - { - case 0: /* LED2=OFF */ - case 1: /* LED2=OFF */ - case 2: /* LED2=OFF */ - case 4: /* LED2=OFF */ - break; - - case 3: /* LED2=N/C */ - default: - return; - } - - stm32_gpiowrite(GPIO_LED2, false); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - board_led1_on(led); - board_led2_on(led); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - board_led1_off(led); - board_led2_off(led); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c deleted file mode 100644 index 7c6c0bd27c793..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "clicker2-stm32.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usb_configure() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - stm32_usb_configure(); -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - - ret = stm32_bringup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_bringup() failed: %d\n", ret); - return; - } - -#ifdef CONFIG_CLICKER2_STM32_SYSLOG_FILE - - /* Delay some time for the automounter to finish mounting before - * bringing up file syslog. - */ - - nxsched_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); - - syslog_channel_t *channel; - channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); - if (channel == NULL) - { - syslog(LOG_ERR, "ERROR: syslog_file_channel() failed\n"); - return; - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c b/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c deleted file mode 100644 index 3dd96d97b7ee0..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c +++ /dev/null @@ -1,193 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_RNDIS -# include -# include -#endif - -#include "stm32.h" -#include "clicker2-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_RNDIS -# ifndef CONFIG_CLICKER2_STM32_RNDIS_MACADDR -# define CONFIG_CLICKER2_STM32_RNDIS_MACADDR 0xfadedeadbeef -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_BEE) || defined(CONFIG_CLICKER2_STM32_MB2_BEE) - /* Configure MRF24J40 wireless */ - - ret = stm32_mrf24j40_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed: %d\n", - ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_XBEE) || defined(CONFIG_CLICKER2_STM32_MB2_XBEE) - /* Configure XBee wireless */ - - ret = stm32_xbee_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_xbee_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT) || \ - defined(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT) - /* Configure uSD automounter */ - - ret = stm32_automount_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_automount_initialize() failed: %d\n", - ret); - } -#endif - -#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) || defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) - /* Configure uSD card slot */ - - ret = stm32_mmcsd_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mmcsd_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RNDIS - uint8_t mac[IFHWADDRLEN]; - - mac[0] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 5)) & 0xff; - mac[1] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 4)) & 0xff; - mac[2] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 0)) & 0xff; - - /* Register USB RNDIS Driver */ - - ret = usbdev_rndis_initialize(mac); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: usbdev_rndis_initialize() failed %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c b/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c deleted file mode 100644 index ccae882484fbf..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure BUTTONS T2-T3 GPIOs for input */ - - stm32_configgpio(GPIO_BTN_T2); - stm32_configgpio(GPIO_BTN_T3); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key. A low value will be sensed when the - * button is pressed. - */ - - if (!stm32_gpioread(GPIO_BTN_T2)) - { - ret |= BUTTON_T2_BIT; - } - - if (!stm32_gpioread(GPIO_BTN_T3)) - { - ret |= BUTTON_T3_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint32_t btncfg; - - btncfg = (id == BUTTON_T2) ? GPIO_BTN_T2 : GPIO_BTN_T3; - return stm32_gpiosetevent(btncfg, true, true, true, irqhandler, arg); -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32/clicker2-stm32/src/stm32_can.c deleted file mode 100644 index ac1db032f958a..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c deleted file mode 100644 index a9988f5017f3f..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c +++ /dev/null @@ -1,423 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_spi.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_MMCSD_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) && \ - !defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) -# error Only the Mikroe uSD click boards are supported -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# error Mountpoints are required for MMCSD support -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -# ifndef CONFIG_STM32_SPI3 -# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI3 -# endif -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -# ifndef CONFIG_STM32_SPI2 -# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI2 -# endif -#endif - -#ifdef CONFIG_SCHED_LPWORK -# define MMCSDWORK LPWORK -#elif defined (CONFIG_SCHED_HPWORK) -# define MMCSDWORK HPWORK -#else -# error High or low priority work queue required for MMCSD support -#endif - -/* Card Detect - * - * mikroBUS1 Card Detect (AN pin): PE10-MB1_INT - * mikroBUS2 Card Detect (AN pin: PE14-MB2_INT - * - * There is a pull-up on the uSD click board` - */ - -#define GPIO_MB1_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) -#define GPIO_MB2_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN3) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure holds static information unique to one MMCSD slot */ - -struct stm32_mmcsd_state_s -{ - uint8_t spidev; /* SPI bus used for MMCSD */ - uint8_t slotno; /* Slot number */ - int minor; /* The MMC/SD minor device number */ - uint32_t cdcfg; /* Card detect PIO pin configuration */ - xcpt_t handler; /* Interrupt handler */ - bool cd; /* TRUE: card is inserted */ - spi_mediachange_t callback; /* SPI media change callback */ - void *cbarg; /* Argument to pass to media change callback */ - struct work_s work; /* For deferring card detect interrupt work */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state); -static void stm32_mmcsd_carddetect(void *arg); -static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *); - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, - void *regs, - void *arg); -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, - void *regs, - void *arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* MMCSD device state */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg); - -static struct stm32_mmcsd_state_s g_mb1_mmcsd = -{ - .spidev = 3, - .slotno = MB1_MMCSD_SLOTNO, - .minor = MB1_MMCSD_MINOR, - .cdcfg = GPIO_MB1_CD, - .handler = stm32_mb1_mmcsd_carddetect, - .callback = NULL, - .cbarg = NULL, -}; -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg); - -static struct stm32_mmcsd_state_s g_mb2_mmcsd = -{ - .spidev = 2, - .slotno = MB2_MMCSD_SLOTNO, - .minor = MB2_MMCSD_MINOR, - .cdcfg = GPIO_MB2_CD, - .handler = stm32_mb2_mmcsd_carddetect, - .callback = NULL, - .cbarg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cardinserted_internal - * - * Description: - * Check if a card is inserted into the selected MMCSD slot - * - ****************************************************************************/ - -static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state) -{ - bool inserted; - - /* Get the state of the PIO pin */ - - inserted = stm32_gpioread(state->cdcfg); - finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES"); - return !inserted; -} - -/**************************************************************************** - * Name: stm32_mmcsd_carddetect, stm32_mb1_mmcsd_carddetect, and - * stm32_mb2_mmcsd_carddetect - * - * Description: - * Card detect interrupt handlers - * - ****************************************************************************/ - -static void stm32_mmcsd_carddetect(void *arg) -{ - bool cd; - struct stm32_mmcsd_state_s *state = - (struct stm32_mmcsd_state_s *)arg; - - /* Get the current card insertion state */ - - cd = stm32_cardinserted_internal(state); - - /* Has the card detect state changed? */ - - if (cd != state->cd) - { - /* Yes... remember that new state and inform the HSMCI driver */ - - state->cd = cd; - - /* Report the new state to the SPI driver */ - - if (state->callback) - { - state->callback(state->cbarg); - } - } - -#ifdef HAVE_AUTOMOUNTER - /* Let the automounter know about the insertion event */ - - stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); -#endif -} - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD -static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg) -{ - if (work_available(&g_mb1_mmcsd.work)) - { - return work_queue(MMCSDWORK, &g_mb1_mmcsd.work, stm32_mmcsd_carddetect, - &g_mb1_mmcsd, 0); - } - - return OK; -} -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD -static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg) -{ - if (work_available(&g_mb2_mmcsd.work)) - { - return work_queue(MMCSDWORK, &g_mb2_mmcsd.work, stm32_mmcsd_carddetect, - &g_mb2_mmcsd, 0); - } - - return OK; -} -#endif - -static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *state) -{ - struct spi_dev_s *spi; - int ret; - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(state->spidev); - if (spi == NULL) - { - spierr("ERROR: Failed to initialize SPI bus %d\n", state->spidev); - return -ENODEV; - } - - ret = mmcsd_spislotinitialize(state->minor, state->slotno, spi); - if (ret < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - state->spidev, state->slotno); - return ret; - } - - /* Initialize Card Detect pin and enable interrupt on edges */ - - stm32_configgpio(state->cdcfg); - stm32_gpiosetevent(state->cdcfg, true, true, true, state->handler, NULL); - - state->cd = stm32_cardinserted_internal(state); - if (state->callback) - { - state->callback(state->cbarg); - } - -#ifdef HAVE_AUTOMOUNTER - /* Let the automounter know about the insertion event */ - - stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); -#endif - - mcinfo("INFO: mmcsd%d card has been initialized successfully\n", - state->minor); - return OK; -} - -/**************************************************************************** - * Public Function - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize the MMCSD device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mmcsd_initialize(void) -{ - int ret; - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - finfo("Configuring MMCSD on mikroBUS1\n"); - - ret = stm32_mmcsd_setup(&g_mb1_mmcsd); - if (ret < 0) - { - mcerr("ERROR: Failed to initialize MMCSD on mikroBus1: %d\n", ret); - } -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - finfo("Configuring MMCSD on mikroBUS2\n"); - ret = stm32_mmcsd_setup(&g_mb2_mmcsd); - if (ret < 0) - { - mcerr("ERROR: Failed to initialize MMCSD on mikroBus2: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Name: stm32_cardinserted - * - * Description: - * Check if a card is inserted into the selected MMCSD slot - * - ****************************************************************************/ - -bool stm32_cardinserted(int slotno) -{ - struct stm32_mmcsd_state_s *state; - - /* Get the MMCSD description */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - if (slotno == g_mb1_mmcsd.slotno) - { - state = &g_mb1_mmcsd; - } -#endif -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - - if (slotno == g_mb2_mmcsd.slotno) - { - state = &g_mb2_mmcsd; - } -#endif - - if (!state) - { - ferr("ERROR: No state for slotno %d\n", slotno); - return false; - } - - /* Return the state of the CD pin */ - - return stm32_cardinserted_internal(state); -} - -/**************************************************************************** - * Name: stm32_spi2register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi2 device\n"); -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - g_mb2_mmcsd.callback = callback; - g_mb2_mmcsd.cbarg = arg; -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_spi3register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi3 device\n"); -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - g_mb1_mmcsd.callback = callback; - g_mb1_mmcsd.cbarg = arg; -#endif - return OK; -} - -#endif /* CONFIG_MMCSD_SPI */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c deleted file mode 100644 index 35b8324947995..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c +++ /dev/null @@ -1,328 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "clicker2-stm32.h" - -#ifdef CONFIG_IEEE802154_MRF24J40 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_DRIVERS_WIRELESS -# error Wireless support requires CONFIG_DRIVERS_WIRELESS -#endif - -#if !defined(CONFIG_CLICKER2_STM32_MB1_BEE) && \ - !defined(CONFIG_CLICKER2_STM32_MB2_BEE) -# error Only the Mikroe BEE board is supported -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE -# ifndef CONFIG_STM32_SPI3 -# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI3 -# endif -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE -# ifndef CONFIG_STM32_SPI2 -# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI2 -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_priv_s -{ - struct mrf24j40_lower_s dev; - xcpt_t handler; - void *arg; - uint32_t intcfg; - uint8_t spidev; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MRF24J40 driver from differences in GPIO interrupt handling - * varying boards and MCUs. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg); -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state); -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MRF24J40 - * driver. This structure provides information about the configuration - * of the MRF24J40 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE -static struct stm32_priv_s g_mrf24j40_mb1_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MB1_INT, - .spidev = 3, -}; -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE -static struct stm32_priv_s g_mrf24j40_mb2_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MB2_INT, - .spidev = 2, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the MRF24J40 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - DEBUGASSERT(priv != NULL); - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); - -#ifdef CONFIG_CLICKER2_STM32_MRF24J40LH_VERBOSE - wlinfo("state:%d\n", (int)state); -#endif - - /* Attach and enable, or detach and disable */ - - if (state) - { - stm32_gpiosetevent(priv->intcfg, false, true, true, - priv->handler, priv->arg); - } - else - { - stm32_gpiosetevent(priv->intcfg, false, false, false, - NULL, NULL); - } -} - -/**************************************************************************** - * Name: stm32_mrf24j40_devsetup - * - * Description: - * Initialize one the MRF24J40 device in one mikroBUS slot - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) -{ - struct ieee802154_radio_s *radio; - MACHANDLE mac; - struct spi_dev_s *spi; - int ret; - - /* Configure the interrupt pin */ - - stm32_configgpio(priv->intcfg); - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(priv->spidev); - if (spi == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Initialize and register the SPI MRF24J40 device */ - - radio = mrf24j40_init(spi, &priv->dev); - if (radio == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ - - mac = mac802154_create(radio); - if (mac == NULL) - { - wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); - return -ENODEV; - } - -#ifdef CONFIG_IEEE802154_NETDEV - /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC interface instance in a - * network device driver via mac802154dev_register(). - */ - - ret = mac802154netdev_register(mac); - if (ret < 0) - { - wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", - 0, ret); - return ret; - } -#endif - -#ifdef CONFIG_IEEE802154_MACDEV - /* If want to call these APIs from userspace, you have to wrap the MAC - * interface in a character device viamac802154dev_register(). - */ - - ret = mac802154dev_register(mac, 0); - if (ret < 0) - { - wlerr("ERROR:"); - wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", - 0, ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mrf24j40_initialize - * - * Description: - * Initialize the MRF24J40 device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mrf24j40_initialize(void) -{ - int ret; - -#ifdef CONFIG_CLICKER2_STM32_MB1_BEE - wlinfo("Configuring BEE in mikroBUS1\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); - } -#endif - -#ifdef CONFIG_CLICKER2_STM32_MB2_BEE - wlinfo("Configuring BEE in mikroBUS2\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb2_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS2: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} -#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c deleted file mode 100644 index 26df2d0e6d353..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "clicker2-stm32.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 - * STM32 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_CLICKER2_STM32_MB1_SPI) - /* Enable chip select for mikroBUS1 */ - - stm32_configgpio(GPIO_MB1_CS); -#endif -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_CLICKER2_STM32_MB2_SPI) - /* Enable chip select for mikroBUS2 */ - - stm32_configgpio(GPIO_MB2_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_IEEE802154_MRF24J40 - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif -#ifdef CONFIG_IEEE802154_XBEE - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif -#ifdef CONFIG_MMCSD_SPI - case SPIDEV_MMCSD(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB2_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - status = stm32_cardinserted(MB2_MMCSD_SLOTNO); - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - switch (devid) - { -#ifdef CONFIG_IEEE802154_MRF24J40 - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif -#ifdef CONFIG_IEEE802154_XBEE - case SPIDEV_IEEE802154(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif -#ifdef CONFIG_MMCSD_SPI - case SPIDEV_MMCSD(0): - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MB1_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - status |= stm32_cardinserted(MB1_MMCSD_SLOTNO); - } -#endif - - return status; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c deleted file mode 100644 index 5739adee9832d..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include "stm32_otgfs.h" -#include "stm32_gpio.h" -#include "clicker2-stm32.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO */ - - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c b/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c deleted file mode 100644 index 0ad9207c75189..0000000000000 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "clicker2-stm32.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - gpioconfig_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, true); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/CMakeLists.txt b/boards/arm/stm32/cloudctrl/CMakeLists.txt deleted file mode 100644 index 17ccd5a4c7821..0000000000000 --- a/boards/arm/stm32/cloudctrl/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/cloudctrl/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig deleted file mode 100644 index 4a1bfe1b92b1b..0000000000000 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="cloudctrl" -CONFIG_ARCH_BOARD_CLOUDCTRL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYINIT=y -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/cloudctrl/include/board.h b/boards/arm/stm32/cloudctrl/include/board.h deleted file mode 100644 index 93955bad8b774..0000000000000 --- a/boards/arm/stm32/cloudctrl/include/board.h +++ /dev/null @@ -1,409 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. From above, we already have PLL3 input - * frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_KEY1 0 /* Name printed on board */ -#define BUTTON_KEY2 1 -#define BUTTON_KEY3 2 -#define NUM_BUTTONS 3 - -#define BUTTON_USERKEY BUTTON_KEY1 /* Names in schematic */ -#define BUTTON_TAMPER BUTTON_KEY2 -#define BUTTON_WAKEUP BUTTON_KEY3 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) -#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) - -#define BUTTON_USERKEY_BIT BUTTON_KEY1_BIT -#define BUTTON_TAMPER_BIT BUTTON_KEY2_BIT -#define BUTTON_WAKEUP_BIT BUTTON_KEY3_BIT - -/* Relays */ - -#define NUM_RELAYS 2 - -/* Pin selections ***********************************************************/ - -/* Ethernet - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of - * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is - * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in - * 48 PB11 MII_TX_EN Ethernet PHY RMII mode. - * 51 PB12 MII_TXD0 Ethernet PHY - * 52 PB13 MII_TXD1 Ethernet PHY - * 16 PC1 MII_MDC Ethernet PHY - * 34 PC5 MII_INT Ethernet PHY - * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * - * The board desdign can support a 50MHz external clock to drive the PHY - * (U9). However, on my board, U9 is not present. - * - * 67 PA8 MCO DM9161AEP - */ - -#ifdef CONFIG_STM32_ETHMAC -# ifndef CONFIG_STM32_ETH_REMAP -# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" -# endif -# ifndef CONFIG_STM32_RMII -# error "STM32 Ethernet requires CONFIG_STM32_RMII" -# endif -# ifndef CONFIG_STM32_RMII_MCO -# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" -# endif -#endif - -/* USB - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USB_VBUS MINI-USB-AB. JP3 - * 69 PA10 USB_ID MINI-USB-AB. JP5 - * 70 PA11 USB_DM MINI-USB-AB - * 71 PA12 USB_DP MINI-USB-AB - * 95 PB8 USB_PWR Drives USB VBUS - */ - -/* UARTS/USARTS - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 - * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) - */ - -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) -# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" -#endif - -#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) -# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" -#endif - -/* SPI - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" -#endif - -#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) -# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" -#endif - -/* DAC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 29 PA4 DAC_OUT1 To CON5(CN14) - * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 - */ - -/* ADC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) - * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) - * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 - */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the Shenzhou board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm32_lcdclear(uint16_t color); - -/**************************************************************************** - * Relay control functions - * - * Description: - * Non-standard functions for relay control from the Shenzhou board. - * - * NOTE: These must match the prototypes in include/nuttx/arch.h - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_RELAYS -void up_relaysinit(void); -void relays_setstat(int relays, bool stat); -bool relays_getstat(int relays); -void relays_setstats(uint32_t relays_stat); -uint32_t relays_getstats(void); -void relays_onoff(int relays, uint32_t mdelay); -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); -void relays_resetmode(int relays); -void relays_powermode(int relays); -void relays_resetmodes(uint32_t relays_stat); -void relays_powermodes(uint32_t relays_stat); -#endif - -/**************************************************************************** - * Chip ID functions - * - * Description: - * Non-standard functions to obtain chip ID information. - * - ****************************************************************************/ - -const char *stm32_getchipid(void); -const char *stm32_getchipid_string(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/cloudctrl/scripts/Make.defs b/boards/arm/stm32/cloudctrl/scripts/Make.defs deleted file mode 100644 index ef5f8e0d7da1d..0000000000000 --- a/boards/arm/stm32/cloudctrl/scripts/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/cloudctrl/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = cloudctrl-dfu.ld -else - LDSCRIPT = cloudctrl.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt b/boards/arm/stm32/cloudctrl/src/CMakeLists.txt deleted file mode 100644 index 2c62ad02c35df..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt +++ /dev/null @@ -1,67 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/cloudctrl/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_chipid.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_RELAYS) - list(APPEND SRCS stm32_relays.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_PHYINIT) - list(APPEND SRCS stm32_phyinit.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/cloudctrl-dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/cloudctrl.ld") -endif() diff --git a/boards/arm/stm32/cloudctrl/src/Make.defs b/boards/arm/stm32/cloudctrl/src/Make.defs deleted file mode 100644 index 746c1618cf64c..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/cloudctrl/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_chipid.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_RELAYS),y) -CSRCS += stm32_relays.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_PHYINIT),y) -CSRCS += stm32_phyinit.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/cloudctrl/src/stm32_adc.c b/boards/arm/stm32/cloudctrl/src/stm32_adc.c deleted file mode 100644 index 075adeb257a01..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_adc.c +++ /dev/null @@ -1,164 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "cloudctrl.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. The only internal signal for ADC - * testing is the potentiometer input: - * - * ADC1_IN10(PC0) Potentiometer - * - * External signals are also available on CON5 CN14: - * - * ADC_IN8 (PB0) CON5 CN14 Pin2 - * ADC_IN9 (PB1) CON5 CN14 Pin1 - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 /* {10, 8, 9}; */ -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN10 -}; - -/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c deleted file mode 100644 index f4ecba575e85d..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define CLOUDCTRL_LED1 (1 << 0) -#define CLOUDCTRL_LED2 (1 << 1) -#define CLOUDCTRL_LED3 (1 << 2) -#define CLOUDCTRL_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((CLOUDCTRL_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((CLOUDCTRL_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((CLOUDCTRL_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((clrbits & CLOUDCTRL_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & CLOUDCTRL_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & CLOUDCTRL_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & CLOUDCTRL_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((setbits & CLOUDCTRL_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & CLOUDCTRL_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & CLOUDCTRL_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((setbits & CLOUDCTRL_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_boot.c b/boards/arm/stm32/cloudctrl/src/stm32_boot.c deleted file mode 100644 index cd489c2ae3deb..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_boot.c +++ /dev/null @@ -1,200 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - - /* Initialize and register the W25 FLASH file system. */ - -#ifdef HAVE_W25 - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - -#ifdef HAVE_USBHOST - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - return; - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c b/boards/arm/stm32/cloudctrl/src/stm32_buttons.c deleted file mode 100644 index cc0e9ea8ea209..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "cloudctrl.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each cloudctrl button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c b/boards/arm/stm32/cloudctrl/src/stm32_chipid.c deleted file mode 100644 index c2f6f75cf00a4..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_chipid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -const char *stm32_getchipid(void) -{ - static char cpuid[12]; - int i; - - for (i = 0; i < 12; i++) - { - cpuid[i] = getreg8(0x1ffff7e8 + i); - } - - return cpuid; -} - -const char *stm32_getchipid_string(void) -{ - static char cpuid[27]; - int c; - int i; - - for (i = 0, c = 0; i < 12; i++) - { - snprintf(&cpuid[c], sizeof(cpuid) - c, - "%02X", getreg8(0x1ffff7e8 + 11 - i)); - c += 2; - if (i % 4 == 3) - { - cpuid[c++] = '-'; - } - } - - cpuid[26] = '\0'; - return cpuid; -} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_relays.c b/boards/arm/stm32/cloudctrl/src/stm32_relays.c deleted file mode 100644 index 0007901ff80bb..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_relays.c +++ /dev/null @@ -1,274 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_relays.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "cloudctrl.h" - -#ifdef CONFIG_ARCH_RELAYS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RELAYS_MIN_RESET_TIME 5 -#define RELAYS_RESET_MTIME 5 -#define RELAYS_POWER_MTIME 50 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_relays_stat = 0; -static bool g_relays_init = false; - -static const uint16_t g_relays[NUM_RELAYS] = -{ - GPIO_RELAYS_R00 -#ifdef GPIO_RELAYS_R01 - , GPIO_RELAYS_R01 -#endif -#ifdef GPIO_RELAYS_R02 - , GPIO_RELAYS_R02 -#endif -#ifdef GPIO_RELAYS_R03 - , GPIO_RELAYS_R03 -#endif -#ifdef GPIO_RELAYS_R04 - , GPIO_RELAYS_R04 -#endif -#ifdef GPIO_RELAYS_R05 - , GPIO_RELAYS_R05 -#endif -#ifdef GPIO_RELAYS_R06 - , GPIO_RELAYS_R06 -#endif -#ifdef GPIO_RELAYS_R07 - , GPIO_RELAYS_R07 -#endif -#ifdef GPIO_RELAYS_R08 - , GPIO_RELAYS_R08 -#endif -#ifdef GPIO_RELAYS_R09 - , GPIO_RELAYS_R09 -#endif -#ifdef GPIO_RELAYS_R10 - , GPIO_RELAYS_R10 -#endif -#ifdef GPIO_RELAYS_R11 - , GPIO_RELAYS_R11 -#endif -#ifdef GPIO_RELAYS_R12 - , GPIO_RELAYS_R12 -#endif -#ifdef GPIO_RELAYS_R13 - , GPIO_RELAYS_R13 -#endif -#ifdef GPIO_RELAYS_R14 - , GPIO_RELAYS_R14 -#endif -#ifdef GPIO_RELAYS_R15 - , GPIO_RELAYS_R15 -#endif -#ifdef GPIO_RELAYS_R16 - , GPIO_RELAYS_R16 -#endif -#ifdef GPIO_RELAYS_R17 - , GPIO_RELAYS_R17 -#endif -#ifdef GPIO_RELAYS_R18 - , GPIO_RELAYS_R18 -#endif -#ifdef GPIO_RELAYS_R19 - , GPIO_RELAYS_R19 -#endif -#ifdef GPIO_RELAYS_R20 - , GPIO_RELAYS_R20 -#endif -#ifdef GPIO_RELAYS_R21 - , GPIO_RELAYS_R21 -#endif -#ifdef GPIO_RELAYS_R22 - , GPIO_RELAYS_R22 -#endif -#ifdef GPIO_RELAYS_R23 - , GPIO_RELAYS_R23 -#endif -#ifdef GPIO_RELAYS_R24 - , GPIO_RELAYS_R24 -#endif -#ifdef GPIO_RELAYS_R25 - , GPIO_RELAYS_R25 -#endif -#ifdef GPIO_RELAYS_R26 - , GPIO_RELAYS_R26 -#endif -#ifdef GPIO_RELAYS_R27 - , GPIO_RELAYS_R27 -#endif -#ifdef GPIO_RELAYS_R28 - , GPIO_RELAYS_R28 -#endif -#ifdef GPIO_RELAYS_R29 - , GPIO_RELAYS_R29 -#endif -#ifdef GPIO_RELAYS_R30 - , GPIO_RELAYS_R30 -#endif -#ifdef GPIO_RELAYS_R31 - , GPIO_RELAYS_R31 -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void up_relaysinit(void) -{ - int i; - - if (g_relays_init) - { - return; - } - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_RELAYS; i++) - { - stm32_configgpio(g_relays[i]); - stm32_gpiowrite(g_relays[i], false); - } - - g_relays_init = true; -} - -void relays_setstat(int relays, bool stat) -{ - if ((unsigned)relays < NUM_RELAYS) - { - stm32_gpiowrite(g_relays[relays], stat); - if (!stat) - { - g_relays_stat &= ~(1 << relays); - } - else - { - g_relays_stat |= (1 << relays); - } - } -} - -bool relays_getstat(int relays) -{ - if ((unsigned)relays < NUM_RELAYS) - { - return (g_relays_stat & (1 << relays)) != 0; - } - - return false; -} - -void relays_setstats(uint32_t relays_stat) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_setstat(i, (relays_stat & (1 << i)) != 0); - } -} - -uint32_t relays_getstats(void) -{ - return (uint32_t)g_relays_stat; -} - -void relays_onoff(int relays, uint32_t mdelay) -{ - if ((unsigned)relays < NUM_RELAYS) - { - if (mdelay > 0) - { - if (relays_getstat(relays)) - { - relays_setstat(relays, false); - nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); - } - - relays_setstat(relays, true); - nxsched_usleep(mdelay * 100 * 1000); - relays_setstat(relays, false); - } - } -} - -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_onoff(i, mdelay); - } -} - -void relays_resetmode(int relays) -{ - relays_onoff(relays, RELAYS_RESET_MTIME); -} - -void relays_powermode(int relays) -{ - relays_onoff(relays, RELAYS_POWER_MTIME); -} - -void relays_resetmodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_RESET_MTIME); -} - -void relays_powermodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_POWER_MTIME); -} - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_spi.c b/boards/arm/stm32/cloudctrl/src/stm32_spi.c deleted file mode 100644 index 9e5e2a3d88c23..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_spi.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "cloudctrl.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the cloudctrl board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ -#endif - - /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ - -#ifdef CONFIG_STM32_SPI3 - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usb.c b/boards/arm/stm32/cloudctrl/src/stm32_usb.c deleted file mode 100644 index ae70668bb50f8..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "cloudctrl.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c deleted file mode 100644 index ab372b7c35533..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c b/boards/arm/stm32/cloudctrl/src/stm32_userleds.c deleted file mode 100644 index d9f75c9aa286b..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "cloudctrl.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-3 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_w25.c b/boards/arm/stm32/cloudctrl/src/stm32_w25.c deleted file mode 100644 index bcd7be927bc9b..0000000000000 --- a/boards/arm/stm32/cloudctrl/src/stm32_w25.c +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" -#include "cloudctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/common b/boards/arm/stm32/common deleted file mode 120000 index f25cef98ae272..0000000000000 --- a/boards/arm/stm32/common +++ /dev/null @@ -1 +0,0 @@ -../common/stm32 \ No newline at end of file diff --git a/boards/arm/stm32/emw3162/CMakeLists.txt b/boards/arm/stm32/emw3162/CMakeLists.txt deleted file mode 100644 index f31385e8a774e..0000000000000 --- a/boards/arm/stm32/emw3162/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/emw3162/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32/emw3162/configs/nsh/defconfig deleted file mode 100644 index 09c55962b4462..0000000000000 --- a/boards/arm/stm32/emw3162/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="emw3162" -CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32/emw3162/configs/wlan/defconfig deleted file mode 100644 index 50a635fa1439e..0000000000000 --- a/boards/arm/stm32/emw3162/configs/wlan/defconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="emw3162" -CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EMW3162_WLAN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=800 -CONFIG_NET_GUARDSIZE=32 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_SDIO_PULLUP=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/emw3162/include/board.h b/boards/arm/stm32/emw3162/include/board.h deleted file mode 100644 index 96825cff434d9..0000000000000 --- a/boards/arm/stm32/emw3162/include/board.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The EMW3162 board features a single 26MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) - * PLLM : 26 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG HS : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 26MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 26000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (26,000,000 / 26) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ---------------------------- ------ - * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ - */ - -#define LED_STARTED 0 /* NuttX has been started OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON */ -#define LED_INIRQ 2 /* In an interrupt N/C */ -#define LED_SIGNAL 2 /* In a signal handler N/C */ -#define LED_ASSERTION 2 /* An assertion failed N/C */ -#define LED_PANIC 3 /* The system has crashed FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* Thus if LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/* Alternate function pin selections ****************************************/ - -/* UART1 */ - -#ifdef CONFIG_STM32_USART1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) -#endif - -/* MCO1 */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* SDIO definitions *********************************************************/ - -/* Note that slower clocking is required when DMA is disabled in order - * to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. - * - * These values have not been tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/emw3162/scripts/Make.defs b/boards/arm/stm32/emw3162/scripts/Make.defs deleted file mode 100644 index bc77620c6b44b..0000000000000 --- a/boards/arm/stm32/emw3162/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/emw3162/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/emw3162/scripts/ld.script b/boards/arm/stm32/emw3162/scripts/ld.script deleted file mode 100644 index 469fdbf5198f5..0000000000000 --- a/boards/arm/stm32/emw3162/scripts/ld.script +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F205RG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 112Kb of SRAM in main SRAM1 and 16 Kb in auxiliary SRAM2. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - - wlan_firmware_image_location = .; - *(.wlan_firmware_image .wlan_firmware_image.*) - wlan_firmware_image_end = .; - - wlan_nvram_image_location = .; - *(.wlan_nvram_image .wlan_nvram_image.*) - wlan_nvram_image_end = .; - - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/emw3162/src/CMakeLists.txt b/boards/arm/stm32/emw3162/src/CMakeLists.txt deleted file mode 100644 index 8c94250123d10..0000000000000 --- a/boards/arm/stm32/emw3162/src/CMakeLists.txt +++ /dev/null @@ -1,38 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/emw3162/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_EMW3162_WLAN) - list(APPEND SRCS stm32_wlan.c) - list(APPEND SRCS stm32_wlan_firmware.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/emw3162/src/Make.defs b/boards/arm/stm32/emw3162/src/Make.defs deleted file mode 100644 index f397baef02ba8..0000000000000 --- a/boards/arm/stm32/emw3162/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/emw3162/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_EMW3162_WLAN),y) -CSRCS += stm32_wlan.c -CSRCS += stm32_wlan_firmware.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/emw3162/src/stm32_autoleds.c b/boards/arm/stm32/emw3162/src/stm32_autoleds.c deleted file mode 100644 index cb2dd8f580b9e..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_autoleds.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* LEDs - * - * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ----------------------- ------ - * SYMBOL Meaning LED - * ------------------- ----------------------- ------ - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt N/C - * LED_SIGNAL In a signal handler N/C - * LED_ASSERTION An assertion failed N/C - * LED_PANIC The system has crashed FLASH - * - * Thus is LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "emw3162.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure EMW3162 LED gpio as output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1 || led == 3) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 3) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_boot.c b/boards/arm/stm32/emw3162/src/stm32_boot.c deleted file mode 100644 index fc3647ca0cf37..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_boot.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "arm_internal.h" -#include "emw3162.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_intitialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board initialization */ - - stm32_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/emw3162/src/stm32_bringup.c b/boards/arm/stm32/emw3162/src/stm32_bringup.c deleted file mode 100644 index 0ffd40553fca8..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_bringup.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include - -#include "emw3162.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * This function initializes and configures all on-board features - * appropriate for the selected configuration. - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_EMW3162_WLAN - /* Initialize wlan driver and hardware */ - - ret = emw3162_wlan_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/emw3162/src/stm32_userleds.c b/boards/arm/stm32/emw3162/src/stm32_userleds.c deleted file mode 100644 index 61d304b6cf600..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_userleds.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include "emw3162.h" - -#include "stm32_gpio.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure EMW3162 LED gpio as output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan.c b/boards/arm/stm32/emw3162/src/stm32_wlan.c deleted file mode 100644 index d8a110dc14fec..0000000000000 --- a/boards/arm/stm32/emw3162/src/stm32_wlan.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_wlan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_sdio.h" - -#include "emw3162.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: bcmf_board_reset - ****************************************************************************/ - -void bcmf_board_reset(int minor, bool reset) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); -} - -/**************************************************************************** - * Name: bcmf_board_power - ****************************************************************************/ - -void bcmf_board_power(int minor, bool power) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_PWRDN, !power); -} - -/**************************************************************************** - * Name: bcmf_board_initialize - ****************************************************************************/ - -void bcmf_board_initialize(int minor) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure MCO1 output to drive EXT_SLEEP_CLK input pin of BCM43362 */ - - stm32_configgpio(GPIO_MCO1); - stm32_mco1config(RCC_CFGR_MCO1_LSE, RCC_CFGR_MCO1PRE_NONE); - - /* Configure PowerDown pin */ - - stm32_configgpio(GPIO_WLAN0_PWRDN); - - /* Shutdown wlan chip */ - - bcmf_board_power(minor, false); - - /* Configure reset pin */ - - stm32_configgpio(GPIO_WLAN0_RESET); - - /* Put wlan chip in reset state */ - - bcmf_board_reset(minor, true); -} - -/**************************************************************************** - * Name: bcmf_board_setup_oob_irq - ****************************************************************************/ - -void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure SDIO card in-band interrupt callback */ - - if (g_sdio_dev != NULL) - { - sdio_set_sdio_card_isr(g_sdio_dev, func, arg); - } -} - -/**************************************************************************** - * Name: bcmf_board_etheraddr - ****************************************************************************/ - -bool bcmf_board_etheraddr(struct ether_addr *ethaddr) -{ - return false; -} - -/**************************************************************************** - * Name: emw3162_wlan_initialize - ****************************************************************************/ - -int emw3162_wlan_initialize() -{ - int ret; - - /* Initialize sdio interface */ - - wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); - - if (!g_sdio_dev) - { - wlerr("ERROR: Failed to initialize SDIO with slot %d\n", - SDIO_WLAN0_SLOTNO); - return ERROR; - } - - /* Bind the SDIO interface to the bcmf driver */ - - ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); - - if (ret != OK) - { - wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); - - /* FIXME deinitialize sdio device */ - - return ERROR; - } - - return OK; -} diff --git a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt deleted file mode 100644 index d1c3d364013d5..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/et-stm32-stamp/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig deleted file mode 100644 index 7d2988de7f7fb..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="et-stm32-stamp" -CONFIG_ARCH_BOARD_ET_STM32_STAMP=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/et-stm32-stamp/include/board.h b/boards/arm/stm32/et-stm32-stamp/include/board.h deleted file mode 100644 index c2d3dd4b1a930..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/include/board.h +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The ET-STM32 Stamp doesn't have an on-board LED. These innocent macros - * can still be here. - */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs deleted file mode 100644 index 702ac50cba50b..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/et-stm32-stamp/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32/et-stm32-stamp/scripts/ld.script deleted file mode 100644 index ddf645d3c6c7d..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script +++ /dev/null @@ -1,123 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - * - ****************************************************************************/ - -/* The STM32F103RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103RET6 has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt b/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt deleted file mode 100644 index 3aa3d6093c62e..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/et-stm32-stamp/src/Make.defs b/boards/arm/stm32/et-stm32-stamp/src/Make.defs deleted file mode 100644 index 009c8104955d9..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/Make.defs +++ /dev/null @@ -1,29 +0,0 @@ -############################################################################ -# boards/arm/stm32/et-stm32-stamp/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c deleted file mode 100644 index b56fe99ba7168..0000000000000 --- a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "et-stm32-stamp.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Empty for now. */ -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32/fire-stm32v2/CMakeLists.txt deleted file mode 100644 index a7c4eb1ccad98..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/fire-stm32v2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig deleted file mode 100644 index a08ecdee55b64..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="fire-stm32v2" -CONFIG_ARCH_BOARD_FIRE_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ENC28J60=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=2 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/fire-stm32v2/include/board.h b/boards/arm/stm32/fire-stm32v2/include/board.h deleted file mode 100644 index 573773b7da393..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/include/board.h +++ /dev/null @@ -1,451 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz crytal - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. - * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/up_autoleds.c. - * The LEDs are used to encode OS-related events as follows: - */ - - /* LED1 LED2 LED3 */ -#define LED_STARTED 0 /* OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ -#define LED_IRQSENABLED 2 /* OFF ON OFF */ -#define LED_STACKCREATED 3 /* OFF OFF OFF */ - -#define LED_INIRQ 4 /* NC NC ON (momentary) */ -#define LED_SIGNAL 4 /* NC NC ON (momentary) */ -#define LED_ASSERTION 4 /* NC NC ON (momentary) */ -#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ -#undef LED_IDLE /* Sleep mode indication not supported */ - -/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ - -#define BUTTON_KEY1 0 -#define BUTTON_KEY2 1 -#define NUM_BUTTONS 2 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) - -/* Pin Remapping ************************************************************/ - -/* USB 2.0 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 70 PA11 PA11-USBDM USB2.0 - * 71 PA12 PA12-USBDP USB2.0 - * 2 PE3 PE3-USB-M USB2.0 - */ - -/* 2.4" TFT + Touchscreen - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen - * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen - * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen - * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen - * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen - * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen - * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen - * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen - * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen - * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen - * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen - * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen - * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen - * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen - * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen - * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen - * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen - * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen - * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen - * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" -#endif - -/* AT24C02 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - */ - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" -#endif - -/* Potentiometer/ADC - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) - * 24 PA1 PC1/ADC123-IN1 - */ - -/* USARTs - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, - * Requires !CONFIG_STM32_USART1_REMAP - * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, - * Requires !CONFIG_STM32_USART1_REMAP - * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, - * Requires !CONFIG_STM32_USART2_REMAP - * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, - * Requires !CONFIG_STM32_USART2_REMAP - */ - -#if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) -# error "USART1 requires CONFIG_STM32_USART1_REMAP=n" -#endif - -#if defined(CONFIG_STM32_USART2) && defined(CONFIG_STM32_USART2_REMAP) -# error "USART2 requires CONFIG_STM32_USART2_REMAP=n" -#endif - -/* 2MBit SPI FLASH - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" -#endif - -/* MP3 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 48 PB11 PB11-MP3-RST MP3 - * 51 PB12 PB12-SPI2-NSS MP3 - * 52 PB13 PB13-SPI2-SCK MP3 - * 53 PB14 PB14-SPI2-MISO MP3 - * 54 PB15 PB15-SPI2-MOSI MP3 - * 63 PC6 PC6-MP3-XDCS MP3 - * 64 PC7 PC7-MP3-DREQ MP3 - */ - -/* SD Card - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 65 PC8 PC8-SDIO-D0 SD card, pulled high - * 66 PC9 PC9-SDIO-D1 SD card, pulled high - * 78 PC10 PC10-SDIO-D2 SD card, pulled high - * 79 PC11 PC10-SDIO-D3 SD card, pulled high - * 80 PC12 PC12-SDIO-CLK SD card - * 83 PD2 PD2-SDIO-CMD SD card, pulled high - */ - -/* CAN - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 95 PB8 PB8-CAN-RX CAN transceiver, Header 2H - * 96 PB9 PB9-CAN-TX CAN transceiver, Header 2H - */ - -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP1) -# error "SPI1 requires CONFIG_STM32_CAN1_REMAP1=y" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: fire_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the M3 Wildfire board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void fire_lcdclear(uint16_t color); -#endif - -#if defined(__cplusplus) -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -#endif /* __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32/fire-stm32v2/scripts/Make.defs deleted file mode 100644 index f51a205edbf4e..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/fire-stm32v2/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = fire-stm32v2-dfu.ld -else - LDSCRIPT = fire-stm32v2.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt b/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt deleted file mode 100644 index 8d9a77eabc3ec..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt +++ /dev/null @@ -1,59 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c) - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ENC28J60) - list(APPEND SRCS stm32_enc28j60.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2-dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2.ld") -endif() diff --git a/boards/arm/stm32/fire-stm32v2/src/Make.defs b/boards/arm/stm32/fire-stm32v2/src/Make.defs deleted file mode 100644 index fdfe1aaa4b39a..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/Make.defs +++ /dev/null @@ -1,55 +0,0 @@ -############################################################################ -# boards/arm/stm32/fire-stm32v2/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ENC28J60),y) -CSRCS += stm32_enc28j60.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c deleted file mode 100644 index 882946b820ace..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings. - * - * OFFBITS ONBITS - * CLR SET CLR SET - * 210 210 210 210 - */ - -#define FIRE_LED1 (1 << 0) -#define FIRE_LED2 (1 << 1) -#define FIRE_LED3 (1 << 2) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (3) -#define OFF_SETBITS_SHIFT (6) -#define OFF_CLRBITS_SHIFT (9) - -#define ON_BITS(v) ((v) & 0x3f) -#define OFF_BITS(v) (((v) >> 6) & 0x03f) -#define SETBITS(b) ((b) & 0x07) -#define CLRBITS(b) (((b) >> 3) & 0x07) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -/* ON OFF - * -------------------------- -- ------------------ ----------------- - * LED1 LED2 LED3 LED1 LED2 LED3 - * -------------------------- -- ------ ----- ----- ----- ----- ----- - * LED_STARTED 0 OFF OFF OFF OFF OFF OFF - * LED_HEAPALLOCATE 1 ON OFF OFF OFF OFF OFF - * LED_IRQSENABLED 2 OFF ON OFF ON OFF OFF - * LED_STACKCREATED 3 OFF OFF OFF OFF ON OFF - * - * LED_INIRQ 4 NC NC ON NC NC OFF - * LED_SIGNAL 4 NC NC ON NC NC OFF - * LED_ASSERTION 4 NC NC ON NC NC OFF - * LED_PANIC 4 NC NC ON NC NC OFF - * -------------------------- -- ------ ----- ----- ----- ----- ----- - */ - -#define LED_STARTED_ON_SETBITS (0) -#define LED_STARTED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0) -#define LED_STARTED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((FIRE_LED1) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS (0) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((FIRE_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((FIRE_LED1|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((FIRE_LED1) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS (0) -#define LED_STACKCREATED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((FIRE_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED3) << OFF_CLRBITS_SHIFT) - -#define LED_FLASH_ON_SETBITS ((FIRE_LED3) << ON_SETBITS_SHIFT) -#define LED_FLASH_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_FLASH_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_FLASH_OFF_CLRBITS ((FIRE_LED3) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_FLASH_ON_SETBITS | LED_FLASH_ON_CLRBITS | - LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & FIRE_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & FIRE_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & FIRE_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & FIRE_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & FIRE_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & FIRE_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c deleted file mode 100644 index 9ee669b3fbc53..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32_i2c.h" -#include "arm_internal.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_W25 1 - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* Only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO -# error "Only one MMC/SD slot: Slot 0" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO -# endif -#endif - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if the USB peripheral or the USB - * device infrastructure is not enabled - */ - -#if !defined(CONFIG_STM32_USB) || !defined(CONFIG_USBDEV) -# undef HAVE_USBDEV -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#if defined(HAVE_MMCSD) || defined(HAVE_W25) - int ret; -#endif - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - -#ifdef HAVE_MMCSD - /* Initialize the SDIO-based MMC/SD slot */ - - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", - CONFIG_NSH_MMCSDSLOTNO, ret); - return; - } -#endif -} -#endif diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c b/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c deleted file mode 100644 index 735bda0f2fd80..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "fire-stm32v2.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - stm32_configgpio(GPIO_BTN_KEY1); - stm32_configgpio(GPIO_BTN_KEY2); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key. - * A LOW value means that the key is pressed. - */ - - if (!stm32_gpioread(GPIO_BTN_KEY1)) - { - ret |= BUTTON_KEY1_BIT; - } - - if (!stm32_gpioread(GPIO_BTN_KEY2)) - { - ret |= BUTTON_KEY2_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration values. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint16_t gpio; - int ret; - - if (id == BUTTON_KEY1) - { - gpio = GPIO_KEY1; - } - else if (id == BUTTON_KEY2) - { - gpio = GPIO_KEY2; - } - else - { - return -EINVAL; - } - - return stm32_gpiosetevent(gpio, true, true, true, irqhandler, arg); -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c deleted file mode 100644 index de824d6ad02b2..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c +++ /dev/null @@ -1,222 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* 2MBit SPI FLASH OR ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_spi.h" - -#include "fire-stm32v2.h" - -#ifdef CONFIG_ENC28J60 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -/* ENC28J60 is on SPI1 */ - -#ifndef CONFIG_STM32_SPI1 -# error "Need CONFIG_STM32_SPI1 in the configuration" -#endif - -/* SPI Assumptions **********************************************************/ - -#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ -#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_lower_s -{ - const struct enc_lower_s lower; /* Low-level MCU interface */ - xcpt_t handler; /* ENC28J60 interrupt handler */ - void *arg; /* Argument that accompanies the interrupt */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg); -static void up_enable(const struct enc_lower_s *lower); -static void up_disable(const struct enc_lower_s *lower); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The - * following structure provides an MCU-independent mechanixm for controlling - * the ENC28J60 GPIO interrupt. - */ - -static struct stm32_lower_s g_enclower = -{ - .lower = - { - .attach = up_attach, - .enable = up_enable, - .disable = up_disable - }, - .handler = NULL, - .arg = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: struct enc_lower_s methods - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void up_enable(const struct enc_lower_s *lower) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - DEBUGASSERT(priv->handler); - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - priv->handler, priv->arg); -} - -/* REVISIT: Since the interrupt is completely torn down, not just disabled, - * in interrupt requests that occurs while the interrupt is disabled will be - * lost. - */ - -static void up_disable(const struct enc_lower_s *lower) -{ - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - NULL, NULL); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -void arm_netinitialize(void) -{ - struct spi_dev_s *spi; - int ret; - - /* Assumptions: - * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in - * boot-up. - */ - - spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); - if (!spi) - { - nerr("ERROR: Failed to initialize SPI port %d\n", - ENC28J60_SPI_PORTNO); - return; - } - - /* Take ENC28J60 out of reset (active low) */ - - stm32_gpiowrite(GPIO_ENC28J60_RESET, true); - - /* Bind the SPI port to the ENC28J60 driver */ - - ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); - if (ret < 0) - { - nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); - return; - } - - ninfo("Bound SPI port %d to ENC28J60 device %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); -} - -#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c deleted file mode 100644 index 5b800a06600ec..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_sdio.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SDIO=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); - return -ENODEV; - } - - finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(minor, sdio); - if (ret != OK) - { - ferr("ERROR:"); - ferr(" Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - } - - finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the M3 Wildfire board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - return OK; -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c deleted file mode 100644 index a1654527d2317..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* 2.4" TFT + Touchscreen. FSMC Bank1 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, - * SPI 2M FLASH - * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 - * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 - * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen - * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen - * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen - * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen - * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen - * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen - * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen - * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen - * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen - * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen - * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen - * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen - * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen - * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen - * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen - * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen - * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen - * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen - * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen - * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen - * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen - * - * NOTE: - * SPI and I2C pin configuration is controlled in the SPI and I2C drivers, - * respectively. - */ - -static const uint16_t g_lcdconfig[NCOMMON_CONFIG] = -{ - /* Address Lines: A16 only */ - - GPIO_NPS_A16, - - /* Data Lines: D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, - GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, - GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, - GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - - /* NOE, NWE, NE1, NBL1 */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1, GPIO_NPS_NBL1, - - /* Backlight GPIO */ - - GPIO_LCD_BACKLIGHT -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig) / sizeof(uint16_t)) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD pin configuration. - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - irqstate_t flags; - int i; - - /* Configure LCD GPIO pis */ - - flags = enter_critical_section(); - for (i = 0; i < NLCD_GPIOS; i++) - { - stm32_configgpio(g_lcdconfig[i]); - } - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); - - putreg32(0xffffffff, STM32_FSMC_BWTR4); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - leave_critical_section(flags); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c deleted file mode 100644 index 309d8d175decb..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the M3 Wildfire board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the TFT/Touchscreen CS GPIO */ - -#if 0 /* Need to study this */ - stm32_configgpio(GPIO_LCD_CS); -#endif - - /* Configure the TFT/Touchscreen and ENC28J60 or SPI-based FLASH PIOs */ - - /* Configure ENC28J60 SPI1 CS (also RESET and interrupt pins) */ - -#ifdef CONFIG_ENC28J60 - stm32_configgpio(GPIO_ENC28J60_CS); - stm32_configgpio(GPIO_ENC28J60_RESET); - stm32_configgpio(GPIO_ENC28J60_INTR); -#else - - /* Configure FLASH SPI1 CS */ - - stm32_configgpio(GPIO_FLASH_CS); -#endif - -#endif /* CONFIG_STM32_SPI1 */ - -#ifdef CONFIG_STM32_SPI2 - /* Configure the MP3 SPI2 CS GPIO */ - - stm32_configgpio(GPIO_MP3_CS); - -#endif /* CONFIG_STM32_SPI2 */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if 0 /* Need to study this */ - if (devid == SPIDEV_LCD) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCD_CS, !selected); - } - else -#endif -#ifdef CONFIG_ENC28J60 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); - } -#else - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_AUDIO) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_MP3_CS, !selected); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c deleted file mode 100644 index 4d592165ae870..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the M3 Wildfire board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup */ - -#if 0 /* REVISIT */ - stm32_configgpio(GPIO_USB_PULLUP); -#endif -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined - * to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); -#if 0 /* REVISIT */ - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c deleted file mode 100644 index dd87c605e78da..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c b/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c deleted file mode 100644 index 15f5e2506f711..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "fire-stm32v2.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - return 3; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Set one LED to the 'ledon' state. The LEDs are pulled up and, hence, - * active low. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], !ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Set each LED to the bit encoded state. The LEDs are pulled up and, - * hence, active low. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c b/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c deleted file mode 100644 index 3dd694251ba43..0000000000000 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" -#include "fire-stm32v2.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32/hymini-stm32v/CMakeLists.txt deleted file mode 100644 index 7cc2354980b45..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/hymini-stm32v/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig deleted file mode 100644 index 966728982c123..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_DISABLE=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_FAT_LCNAMES=y -CONFIG_FS_FAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig deleted file mode 100644 index dd50de960fc5e..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXIMAGE=y -CONFIG_EXAMPLES_NXIMAGE_BPP=16 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_ROMFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_ADS7843E=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_MAXPOWER=100 -CONFIG_LCD_SSD1289=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_SSD1289_PROFILE2=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_TRACE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig deleted file mode 100644 index 6c87e1b256e9f..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_INIT_ENTRYPOINT="msconn_main" -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig deleted file mode 100644 index eb3a920940b70..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_DISABLE=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_BKP=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig deleted file mode 100644 index f5f7b23c3acc5..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="hymini-stm32v" -CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_INIT_ENTRYPOINT="usbserial_main" -CONFIG_PL2303=y -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=49152 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/hymini-stm32v/include/board.h b/boards/arm/stm32/hymini-stm32v/include/board.h deleted file mode 100644 index 9fae5bdda94af..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/include/board.h +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_STM32_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has 2 LEDs that we will encode as: */ -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* The board supports two user buttons - * - * KeyA -- Connected to PC.13 - * KeyB -- Connected to PB.2 - */ - -#define BUTTON_KEYA 0 -#define BUTTON_KEYB 1 - -#define NUM_BUTTONS 2 - -#define BUTTON_KEYA_BIT (1 << BUTTON_KEYA) -#define BUTTON_KEYB_BIT (1 << BUTTON_KEYB) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* TIM3 */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 -#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 -#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 -#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 -#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) - -/* FSMC NPS_A address pins (used by LCD srcs) */ - -#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A23 GPIO_ADJUST_MODE(GPIO_NPS_A23_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A24 GPIO_ADJUST_MODE(GPIO_NPS_A24_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A25 GPIO_ADJUST_MODE(GPIO_NPS_A25_0, GPIO_MODE_50MHz) - -/* FSMC NPS_D pins (used by LCD srcs) */ - -#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE1 GPIO_ADJUST_MODE(GPIO_NPS_NE1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32/hymini-stm32v/scripts/Make.defs deleted file mode 100644 index 40a135bea3b15..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/hymini-stm32v/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/hymini-stm32v/scripts/ld.script b/boards/arm/stm32/hymini-stm32v/scripts/ld.script deleted file mode 100644 index 0f1cc348f8a99..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103VCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and - * 48Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt b/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt deleted file mode 100644 index e31d5a0ca4c72..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt +++ /dev/null @@ -1,43 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -else() - if(CONFIG_LCD_R61505U) - list(APPEND SRCS stm32_r61505u.c) - endif() -endif() - -if(CONFIG_INPUT) - list(APPEND SRCS stm32_ts.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/hymini-stm32v/src/Make.defs b/boards/arm/stm32/hymini-stm32v/src/Make.defs deleted file mode 100644 index d96eeceb4ada9..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/Make.defs +++ /dev/null @@ -1,45 +0,0 @@ -############################################################################ -# boards/arm/stm32/hymini-stm32v/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -else -ifeq ($(CONFIG_LCD_R61505U),y) -CSRCS += stm32_r61505u.c -endif -endif - -ifeq ($(CONFIG_INPUT),y) -CSRCS += stm32_ts.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c b/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c deleted file mode 100644 index 755f41cf03999..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* Check if we can have USB device in NSH */ - -#define NSH_HAVEUSBDEV 1 - -/* Can't support USB features if USB is not enabled */ - -#ifndef CONFIG_USBDEV -# undef NSH_HAVEUSBDEV -#endif - -/* Check if we can have MMC/SD slot support in NSH */ - -#define NSH_HAVEMMCSD 1 - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef NSH_HAVEMMCSD -#endif - -#ifdef NSH_HAVEMMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_MMCSD -static struct sdio_dev_s *g_sdiodev; -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nsh_cdinterrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef NSH_HAVEMMCSD -static int nsh_cdinterrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SD_CD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdiodev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef NSH_HAVEMMCSD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SD_CD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt, NULL); - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - - g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdiodev) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Use SD card detect pin to check if a card is inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SD_CD); - _info("Card detect : %hhu\n", g_sd_inserted); - - sdio_mediachange(g_sdiodev, g_sd_inserted); -#endif - -#ifdef CONFIG_INPUT - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c b/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c deleted file mode 100644 index dccdff634d9ce..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "hymini-stm32v.h" - -#ifdef CONFIG_ARCH_BUTTONS - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_KEYA); - stm32_configgpio(GPIO_BTN_KEYB); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - bool value; - - /* Check that state of each key */ - - /* Pin is pulled up */ - - value = stm32_gpioread(GPIO_BTN_KEYA); - if (!value) - { - /* Button pressed */ - - ret = 1 << BUTTON_KEYA; - } - - /* Pin is pulled down */ - - value = stm32_gpioread(GPIO_BTN_KEYB); - if (value) - { - /* Button pressed */ - - ret |= 1 << BUTTON_KEYB; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - uint32_t pinset = GPIO_BTN_KEYA; - int ret = -EINVAL; - - if (id == 1) - { - pinset = GPIO_BTN_KEYB; - } - - if (id < 2) - { - ret = stm32_gpiosetevent(pinset, true, true, true, irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c b/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c deleted file mode 100644 index f54f78f99ed01..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c +++ /dev/null @@ -1,224 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define HYMINI_STM32_LED1 (1 << 0) -#define HYMINI_STM32_LED2 (1 << 1) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -/* On: !LED1 + !LED2 Off: - */ - -#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((HYMINI_STM32_LED1|HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) - -/* On: LED1+!LED2 Off: N/A */ - -#define LED_HEAPALLOCATE_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS (0) -#define LED_HEAPALLOCATE_OFF_CLRBITS (0) - -/* On: LED2+!LED1 Off: N/A */ - -#define LED_IRQSENABLED_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS (0) -#define LED_IRQSENABLED_OFF_CLRBITS (0) - -/* On: LED1+!LED2 Off: N/A */ - -#define LED_STACKCREATED_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS (0) -#define LED_STACKCREATED_OFF_CLRBITS (0) - -/* On: !LED1 Off: LED1 */ - -#define LED_INIRQ_ON_SETBITS ((0) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((HYMINI_STM32_LED1) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) - -/* On: LED2 Off: !LED2 */ - -#define LED_SIGNAL_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((HYMINI_STM32_LED2) << OFF_CLRBITS_SHIFT) - -/* On: LED1+LED2 Off: - */ - -#define LED_ASSERTION_ON_SETBITS ((HYMINI_STM32_LED2|HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) - -/* On: LED1 Off: LED2 */ - -#define LED_PANIC_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((HYMINI_STM32_LED2) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((HYMINI_STM32_LED1) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & HYMINI_STM32_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & HYMINI_STM32_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & HYMINI_STM32_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & HYMINI_STM32_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1 & LED2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c b/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c deleted file mode 100644 index 75eb1cbfd1778..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the SPI-based touch screen CS GPIO */ - - spiinfo("Configure GPIO for SPI1/CS\n"); - stm32_configgpio(GPIO_TS_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_TS_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c deleted file mode 100644 index 6da455a5bd46f..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c +++ /dev/null @@ -1,489 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -#include /* Should always be included last due to dependencies */ - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* Color depth and format */ - -#define LCD_BPP 16 -#define LCD_COLORFMT FB_FMT_RGB16_565 - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) -# define LCD_XRES 320 -# define LCD_YRES 240 -#else -# define LCD_XRES 240 -# define LCD_YRES 320 -#endif - -#define LCD_BL_TIMER_PERIOD 8999 - -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship - * select signal - */ - -/* RS <==> A16 */ - -#define LCD_INDEX 0x60000000 /* RS = 0 */ -#define LCD_DATA 0x60020000 /* RS = 1 */ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -const uint16_t fsmc_gpios[] = -{ - /* A16... A24 */ - - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, - GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, - GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, - GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, - GPIO_NPS_D15, - - /* NOE, NWE */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, - - /* NE1 */ - - GPIO_NPS_NE1 -}; - -#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) - -/* This is the driver state structure */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). - * Used here to set pwm duty on timer used for backlight. - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - uint32_t duty; - - /* Calculate the new backlight duty. It is a fraction of the timer - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / - CONFIG_LCD_MAXPOWER; - if (duty >= LCD_BL_TIMER_PERIOD) - { - duty = LCD_BL_TIMER_PERIOD - 1; - } - - putreg16((uint16_t)duty, STM32_TIM3_CCR2); - } - else - { - putreg16((uint16_t)0, STM32_TIM3_CCR2); - } -} - -static void init_lcd_backlight(void) -{ - uint16_t ccmr; - uint16_t ccer; - - /* Configure PB5 as TIM3 CH2 output */ - - stm32_configgpio(GPIO_TIM3_CH2OUT); - - /* Enable timer 3 clocking */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - - /* Reset timer 3 */ - - modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); - modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM3_CR1); - - /* Set the Autoreload value */ - - putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); - - /* Set the Prescaler value */ - - putreg16(0, STM32_TIM3_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); - - /* Disable the Channel 2 */ - - ccer = getreg16(STM32_TIM3_CCER); - ccer &= ~ATIM_CCER_CC2E; - putreg16(ccer, STM32_TIM3_CCER); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM3_CCMR1); - ccmr &= ATIM_CCMR1_OC2M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); - - putreg16(0, STM32_TIM3_CCR2); - - /* Select the output polarity level == HIGH */ - - ccer &= ~ATIM_CCER_CC2P; - - /* Enable channel 2 */ - - ccer |= ATIM_CCER_CC2E; - - /* Write the timer configuration */ - - putreg16(ccmr, STM32_TIM3_CCMR1); - putreg16(ccer, STM32_TIM3_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer !!!! */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); - - /* Dump timer3 registers */ - - lcdinfo("APB1ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB1ENR)); - lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR1)); - lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR2)); - lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SMCR)); - lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM3_DIER)); - lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SR)); - lcdinfo("EGR: %04" PRIx32 "\n", getreg32(STM32_TIM3_EGR)); - lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR1)); - lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR2)); - lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCER)); - lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM3_CNT)); - lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM3_PSC)); - lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM3_ARR)); - lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR1)); - lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR2)); - lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR3)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM3_DMAR)); -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize the memory controller (FSMC) - * - ****************************************************************************/ - -static void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(fsmc_gpios, NGPIOS); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) | - FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, - STM32_FSMC_BTR1); - - /* As ext mode is not active the write timing is ignored!! */ - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, - STM32_FSMC_BCR1); -} - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - init_lcd_backlight(); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c deleted file mode 100644 index c5bbfba802af1..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "hymini-stm32v.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO - * (for USB software connect and disconnect), then the board software must - * provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can - * be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c deleted file mode 100644 index 5072bc4531f2b..0000000000000 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" - -/* There is nothing to do here if SDIO support is not selected. */ - -#ifdef CONFIG_STM32_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_HYMINI_STM32V -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1); - - ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); - if (ret != OK) - { - syslog(LOG_ERR, "" - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the Hy-Mini STM32v board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/maple/CMakeLists.txt b/boards/arm/stm32/maple/CMakeLists.txt deleted file mode 100644 index ebbac811ea8c8..0000000000000 --- a/boards/arm/stm32/maple/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/maple/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32/maple/configs/nsh/defconfig deleted file mode 100644 index 83fb1a2b48cdf..0000000000000 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32/maple/configs/nx/defconfig deleted file mode 100644 index 6172ac4e83d7c..0000000000000 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ /dev/null @@ -1,77 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NX_BPP=1 -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_SHARP_MEMLCD=y -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_USBCONSOLE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SPI_BITORDER=y -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2CTIMEOSEC=1 -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32/maple/configs/usbnsh/defconfig deleted file mode 100644 index 4fe25ce070a27..0000000000000 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="maple" -CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103CB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_RAND_ORDER=2 -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NSH_USBCONSOLE=y -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/maple/include/board.h b/boards/arm/stm32/maple/include/board.h deleted file mode 100644 index dd3a2053a28f7..0000000000000 --- a/boards/arm/stm32/maple/include/board.h +++ /dev/null @@ -1,190 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* I2C2 */ - -#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/maple/scripts/Make.defs b/boards/arm/stm32/maple/scripts/Make.defs deleted file mode 100644 index 29529db249b31..0000000000000 --- a/boards/arm/stm32/maple/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/maple/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/maple/scripts/ld.script b/boards/arm/stm32/maple/scripts/ld.script deleted file mode 100644 index afe284a8b80f4..0000000000000 --- a/boards/arm/stm32/maple/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/maple/scripts/ld.script.dfu b/boards/arm/stm32/maple/scripts/ld.script.dfu deleted file mode 100644 index f36caa9525e43..0000000000000 --- a/boards/arm/stm32/maple/scripts/ld.script.dfu +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * maple's DFU bootloader is being used. In that case, the correct - * load .text load address is 0x0800:5000 (leaving 108Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08005000, LENGTH = 108K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/maple/src/CMakeLists.txt b/boards/arm/stm32/maple/src/CMakeLists.txt deleted file mode 100644 index 9eec7a7387bb1..0000000000000 --- a/boards/arm/stm32/maple/src/CMakeLists.txt +++ /dev/null @@ -1,43 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/maple/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c) - -if(CONFIG_NX_LCDDRIVER) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_BOARDCTL) - -endif() - -if(CONFIG_INPUT) - -endif() - -if(CONFIG_USBMSC) - -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/maple/src/Make.defs b/boards/arm/stm32/maple/src/Make.defs deleted file mode 100644 index 90ae23399e304..0000000000000 --- a/boards/arm/stm32/maple/src/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/maple/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c - -ifeq ($(CONFIG_NX_LCDDRIVER),y) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_BOARDCTL),y) -endif - -ifeq ($(CONFIG_INPUT),y) -endif - -ifeq ($(CONFIG_USBMSC),y) -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/maple/src/stm32_boot.c b/boards/arm/stm32/maple/src/stm32_boot.c deleted file mode 100644 index 56d8a61eb6d35..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_boot.c +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called after up_initialize() and board_early_initialize() and just - * before the initial application is started. This additional - * initialization phase may be used, for example, to initialize board- - * specific device drivers for which board_early_initialize() is not - * suitable. - * - * Waiting for events, use of I2C, SPI, etc are permissible in the context - * of board_late_initialize(). That is because board_late_initialize() - * will run on a temporary, internal kernel thread. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/maple/src/stm32_lcd.c b/boards/arm/stm32/maple/src/stm32_lcd.c deleted file mode 100644 index b81dc0df3e78c..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_lcd.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define EXTCOMIN_FREQ 24 -#define TIMER_FREQ 1200 /* 72000000/60000 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *l_lcddev; -static struct spi_dev_s *spi; -static struct stm32_tim_dev_s *tim; -static xcpt_t g_isr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int up_lcdextcominisr(int irq, void *context, void *arg) -{ - STM32_TIM_ACKINT(tim, ATIM_SR_UIF); - if (g_isr == NULL) - { - lcderr("ERROR: error, irq not attached, disabled\n"); - STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); - return OK; - } - - return g_isr(irq, context, arg); -} - -static int up_lcdirqattach(xcpt_t isr, void * arg) -{ - lcdinfo("%s IRQ\n", isr == NULL ? "Detach" : "Attach"); - - if (isr != NULL) - { - STM32_TIM_SETISR(tim, up_lcdextcominisr, arg, ATIM_SR_UIF); - g_isr = isr; - } - else - { - STM32_TIM_SETISR(tim, NULL, NULL, ATIM_SR_UIF); - g_isr = NULL; - } - - return OK; -} - -static void up_lcddispcontrol(bool on) -{ - lcdinfo("set: %s\n", on ? "on" : "off"); - - if (on) - { - stm32_gpiowrite(GPIO_MEMLCD_DISP, 1); - STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE); - } - else - { - stm32_gpiowrite(GPIO_MEMLCD_DISP, 0); - STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); - } -} - -#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW -static void up_lcdsetpolarity(bool pol) -{ - stm32_gpiowrite(GPIO_LED, pol); - stm32_gpiowrite(GPIO_MEMLCD_EXTCOMIN, pol); -} -#endif - -static void up_lcdsetvcomfreq(unsigned int freq) -{ - lcdinfo("freq: %d\n", freq); - DEBUGASSERT(freq >= 1 && freq <= 60); - STM32_TIM_SETPERIOD(tim, TIMER_FREQ / freq); -} - -static struct memlcd_priv_s memlcd_priv = -{ - .attachirq = up_lcdirqattach, - .dispcontrol = up_lcddispcontrol, -#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW - .setpolarity = up_lcdsetpolarity, -#endif - .setvcomfreq = up_lcdsetvcomfreq, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing lcd\n"); - - lcdinfo("init spi1\n"); - spi = stm32_spibus_initialize(1); - DEBUGASSERT(spi); - - lcdinfo("configure related io\n"); - stm32_configgpio(GPIO_MEMLCD_EXTCOMIN); - stm32_configgpio(GPIO_MEMLCD_DISP); - - lcdinfo("configure EXTCOMIN timer\n"); - if (tim == NULL) - { - tim = stm32_tim_init(2); - DEBUGASSERT(tim); - STM32_TIM_SETPERIOD(tim, TIMER_FREQ / EXTCOMIN_FREQ); - STM32_TIM_SETCLOCK(tim, TIMER_FREQ); - STM32_TIM_SETMODE(tim, STM32_TIM_MODE_UP); - } - - lcdinfo("init lcd\n"); - l_lcddev = memlcd_initialize(spi, &memlcd_priv, 0); - DEBUGASSERT(l_lcddev); - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return l_lcddev; -} diff --git a/boards/arm/stm32/maple/src/stm32_leds.c b/boards/arm/stm32/maple/src/stm32_leds.c deleted file mode 100644 index b0ae48072052e..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_leds.c +++ /dev/null @@ -1,120 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED, v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, we simply turn - * it on when the board boots - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - - default: - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - ledinfo("board_autoled_off(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - - default: - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/maple/src/stm32_spi.c b/boards/arm/stm32/maple/src/stm32_spi.c deleted file mode 100644 index 22d6bb192e27a..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_spi.c +++ /dev/null @@ -1,138 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "maple.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the maple board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - stm32_configgpio(GPIO_MEMLCD_CS); -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -# if defined(CONFIG_LCD_SHARP_MEMLCD) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_MEMLCD_CS, selected); - } -# endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -int stm32_spi1cmddata(struct spi_dev_s *dev, - uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -int stm32_spi1cmddata(struct spi_dev_s *dev, - uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/maple/src/stm32_usbdev.c b/boards/arm/stm32/maple/src/stm32_usbdev.c deleted file mode 100644 index 648bfe8a9295c..0000000000000 --- a/boards/arm/stm32/maple/src/stm32_usbdev.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/maple/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "maple.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. Alternatively, if no pull-up GPIO the following EXTERN - * can be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt b/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt deleted file mode 100644 index 1f40202c3298f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig deleted file mode 100644 index cb009bea9044f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ /dev/null @@ -1,136 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_FORMAT_MIDI=y -CONFIG_AUDIO_VS1053=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_LOOP=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_ETC_FATDEVNO=0 -CONFIG_ETC_ROMFS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FS_BINFS=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=30000000 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_MTD_CONFIG=y -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NX=y -CONFIG_NXFONT_SANS17X23B=y -CONFIG_NXFONT_SANS20X27B=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds" -CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_MEDIAPLAYER=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PLATFORM_CONFIGDATA=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_TASK_NAME_SIZE=11 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig deleted file mode 100644 index c2d6d9d08910b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="ostest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/mikroe-stm32f4/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=11 -CONFIG_TESTING_OSTEST=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig deleted file mode 100644 index 690bb98ed8420..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMMTD=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig deleted file mode 100644 index 6a95af7bc2118..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig deleted file mode 100644 index a11ce7db414a0..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_WRITEONLY is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0 -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0 -CONFIG_EXAMPLES_NXLINES_BPP=16 -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig deleted file mode 100644 index c5fb7c7da969a..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NXTEXT=y -CONFIG_EXAMPLES_NXTEXT_BPP=16 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxtext_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MIO283QT2=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SERIF22X28B=y -CONFIG_NXTK_BORDERCOLOR1=0x8410 -CONFIG_NXTK_BORDERCOLOR2=0x4208 -CONFIG_NXTK_BORDERCOLOR3=0xc618 -CONFIG_NXTK_BORDERWIDTH=3 -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig deleted file mode 100644 index 3b71a1d199511..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="mikroe-stm32f4" -CONFIG_ARCH_BOARD_MIKROE_STM32F4=y -CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_MANUFACTURER=0x1C -CONFIG_M25P_MEMORY_TYPE=0x31 -CONFIG_M25P_SUBSECTOR_ERASE=y -CONFIG_MIKROE_FLASH=y -CONFIG_MIKROE_FLASH_PART=y -CONFIG_MIKROE_FLASH_PART_LIST="256,768" -CONFIG_MIKROE_RAMMTD=y -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_MTD_PARTITION=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/mikroe-stm32f4/include/board.h b/boards/arm/stm32/mikroe-stm32f4/include/board.h deleted file mode 100644 index 7c5d365a96b7f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/include/board.h +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. - * The main clock uses the internal 16Mhz RC oscillator. - * - * This is the canonical configuration: - * System Clock source :PLL (HSE) - * SYSCLK(Hz) :168000000 Determined by PLL configuration - * HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler :1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY) - * PLLM :16 (STM32_PLLCFG_PLLM) - * PLLN :36 (STM32_PLLCFG_PLLN) - * PLLP :2 (STM32_PLLCFG_PLLP) - * PLLQ :7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) :5 - * Prefetch Buffer :OFF - * Instruction cache :ON - * Data cache :ON - * Require 48MHz for USB OTG FS, :Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#if 0 -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#endif -#define BOARD_NLEDS 0 - -#if 0 -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_BLUE BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, - * then NuttX will control the 4 LEDs on board the stm32f4discovery. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 0 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#endif /* 0 */ - -/* Alternate function pin selections ****************************************/ - -/* UART2: - * - * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out - * UART2 to the expansion header. - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -/* SPI - Onboard devices use SPI3, plus SPI2 routes to the I/O header */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2 - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile deleted file mode 100644 index 6983f10eff198..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c deleted file mode 100644 index 81c267d2fd5fe..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs deleted file mode 100644 index 36864251081d8..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld deleted file mode 100644 index 1555c66cdded9..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script b/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script deleted file mode 100644 index c576581edc4fd..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld deleted file mode 100644 index a8f5498242e0b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/stm32f4discovery/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld b/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld deleted file mode 100644 index e7e09d43613b1..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt b/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt deleted file mode 100644 index ccadb52a73910..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt +++ /dev/null @@ -1,67 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) - list(APPEND SRCS stm32_clockconfig.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_INPUT) - list(APPEND SRCS stm32_touchscreen.c) -endif() - -if(CONFIG_LCD_MIO283QT2) - list(APPEND SRCS stm32_mio283qt2.c) -endif() - -if(CONFIG_LCD_MIO283QT9A) - list(APPEND SRCS stm32_mio283qt9a.c) -endif() - -if(CONFIG_AUDIO_VS1053) - list(APPEND SRCS stm32_vs1053.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs b/boards/arm/stm32/mikroe-stm32f4/src/Make.defs deleted file mode 100644 index 4d1e116adb868..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs +++ /dev/null @@ -1,73 +0,0 @@ -############################################################################ -# boards/arm/stm32/mikroe-stm32f4/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) -CSRCS += stm32_clockconfig.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_INPUT),y) -CSRCS += stm32_touchscreen.c -endif - -ifeq ($(CONFIG_LCD_MIO283QT2),y) -CSRCS += stm32_mio283qt2.c -endif - -ifeq ($(CONFIG_LCD_MIO283QT9A),y) -CSRCS += stm32_mio283qt9a.c -endif - -ifeq ($(CONFIG_AUDIO_VS1053),y) -CSRCS += stm32_vs1053.c -endif - -ifeq ($(CONFIG_ETC_ROMFS),y) -CSRCS += etc_romfs.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c deleted file mode 100644 index aa2a1c87b0965..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c +++ /dev/null @@ -1,467 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI3 -# include -#endif - -#ifdef CONFIG_MTD_M25P -# include -#endif - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART -#ifdef CONFIG_PLATFORM_CONFIGDATA -# include -#endif -#endif - -#ifdef CONFIG_AUDIO -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "arm_internal.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 -#define NSH_HAVEMMCSD 1 - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SPI3) -# undef NSH_HAVEMMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -# ifndef CONFIG_RAMMTD_BLOCKSIZE -# define CONFIG_RAMMTD_BLOCKSIZE 512 -# endif - -# ifndef CONFIG_RAMMTD_ERASESIZE -# define CONFIG_RAMMTD_ERASESIZE 4096 -# endif - -# ifndef CONFIG_TESTING_SMART_NEBLOCKS -# define CONFIG_TESTING_SMART_NEBLOCKS (22) -# endif - -#ifdef CONFIG_MIKROE_RAMMTD -# ifndef CONFIG_MIKROE_RAMMTD_MINOR -# define CONFIG_MIKROE_RAMMTD_MINOR 1 -# endif -# ifndef CONFIG_MIKROE_RAMMTD_SIZE -# define CONFIG_MIKROE_RAMMTD_SIZE 32 -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* First reset the VS1053 since it tends to produce noise out of power on - * reset - */ - -#ifdef CONFIG_AUDIO_VS1053 - stm32_configgpio(GPIO_VS1053_RST); -#endif - - /* Configure GPIOs for controlling the LCD */ - -#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) - stm32_lcdinitialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#ifdef CONFIG_STM32_SPI3 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif - int ret = OK; - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI3 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 3\n"); - spi = stm32_spibus_initialize(3); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 3\n"); - return; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 3\n"); - - /* Now bind the SPI interface to the M25P8 SPI FLASH driver */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MIKROE_FLASH) - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 3 to the SPI" - " FLASH driver\n"); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI port 3 to the SPI" - " FLASH driver\n"); - -#ifdef CONFIG_MIKROE_FLASH_PART - { - int partno; - int partsize; - int partoffset; - const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partname[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - mtd_part = mtd_partition(mtd, partoffset, - (partsize >> 2) * 16); - partoffset += (partsize >> 2) * 16; - -#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - - #if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partname, sizeof(partname), "p%d", partno); - smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part, - partname); -#endif - } - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_MIKROE_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_MIKROE_FLASH_PART */ - } - - /* Create a RAM MTD device if configured */ - -#if defined(CONFIG_RAMMTD) && defined(CONFIG_MIKROE_RAMMTD) - { - uint8_t *start = - kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024); - mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024); - mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); - - /* Now initialize a SMART Flash block device and bind it to the - * MTD device - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL); -#endif - } - -#endif /* CONFIG_RAMMTD && CONFIG_MIKROE_RAMMTD */ - -#endif /* CONFIG_MTD */ -#endif /* CONFIG_STM32_SPI3 */ - - /* Create the SPI FLASH MTD instance */ - - /* The M25Pxx is not a good media to implement a file system.. - * its block sizes are too large - */ - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef NSH_HAVEMMCSD - /* Bind the spi interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, - CONFIG_NSH_MMCSDSLOTNO, spi); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver:" - " %d\n", ret); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) - /* Configure the TFT LCD module */ - - syslog(LOG_INFO, "Initializing TFT LCD module\n"); - - ret = board_lcd_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize TFT LCD module\n"); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_MIKROE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return; - } -#endif - -#ifdef CONFIG_AUDIO - /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ - - up_vs1053initialize(spi); -#endif -} -#endif diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c deleted file mode 100644 index bcc1ef406e2f4..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c deleted file mode 100644 index f03d247d4adbf..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void up_idlepm(void) -{ -#ifdef CONFIG_RTC_ALARM - struct timespec alarmtime; -#endif - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - _info("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define up_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - up_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c deleted file mode 100644 index d7ce01fddfd5b..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - up_pmbuttons(); -#endif - - /* Initialize the LED PM */ - - up_ledpminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c deleted file mode 100644 index 28cb28a66536f..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "mikroe-stm32f4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be - * configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); - if (!pwm) - { - _err("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c deleted file mode 100644 index 2877044cc8a91..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "mikroe-stm32f4.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI3 - -#ifdef CONFIG_MTD_M25P - stm32_configgpio(GPIO_CS_FLASH); /* FLASH chip select */ -#endif - -#if defined(CONFIG_MMCSD) - stm32_configgpio(GPIO_CS_MMCSD); /* MMC/SD chip select */ - stm32_configgpio(GPIO_SD_CD); /* MMC/SD card detect */ -#endif - -#ifdef CONFIG_AUDIO_VS1053 - stm32_configgpio(GPIO_CS_MP3_DATA); /* MP3 codec chip select for DATA */ - stm32_configgpio(GPIO_CS_MP3_CMD); /* MP3 codec chip select for CMD */ -#endif - - /* Configure the EXP I/O cs for SPI3 */ - - stm32_configgpio(GPIO_CS_EXP_SPI3); /* Expander chip select */ - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_AUDIO_VS1053) - if (devid == SPIDEV_AUDIO_DATA(0)) - { - stm32_gpiowrite(GPIO_CS_MP3_DATA, !selected); - } - else if (devid == SPIDEV_AUDIO_CTRL(0)) - { - stm32_gpiowrite(GPIO_CS_MP3_CMD, !selected); - } - else -#endif - -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_CS_MMCSD, !selected); - } - else -#endif - -#if defined(CONFIG_MTD_M25P) - if (devid == SPIDEV_FLASH(0)) - { - stm32_gpiowrite(GPIO_CS_FLASH, !selected); - } - else -#endif - - /* Must be the expansion header device */ - - if (devid == SPIDEV_EXPANDER(0)) - { - stm32_gpiowrite(GPIO_CS_EXP_SPI3, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t ret = 0; - -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - /* A low value indicates the card is present */ - - if (!stm32_gpioread(GPIO_SD_CD)) - { - ret = SPI_STATUS_PRESENT; - } - } -#endif - - return ret; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c deleted file mode 100644 index d95270676d7f8..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c +++ /dev/null @@ -1,1547 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include "arm_internal.h" -#include "stm32_adc.h" -#include "stm32_gpio.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_INPUT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Reference counting is partially implemented, but not needed in the current - * design. - */ - -#define CONFIG_TOUCHSCREEN_REFCNT -/* Should we try again on bad samples? */ - -#undef CONFIG_TOUCHSCREEN_RESAMPLE - -/* TP uses ADC Channel #2 in a dedicated mode. Ensure ADC2 not selected for - * general use via the menuconfig - */ - -#ifndef CONFIG_STM32_ADC2 -# error Touchpanel Input (CONFIG_INPUT=y) requires enablinga ADC2 (CONFIG_STM32_ADC2=y) -#endif - -/* Work queue support is required */ - -#ifndef CONFIG_SCHED_WORKQUEUE -# warning Work queue support is required (CONFIG_SCHED_WORKQUEUE=y) -#endif - -/* CONFIG_TOUCHSCREEN_THRESHX and CONFIG_TOUCHSCREEN_THRESHY - * Touchscreen data comes in a a very high rate. New touch positions - * will only be reported when the X or Y data changes by these thresholds. - * This trades reduces data rate for some loss in dragging accuracy. The - * touchscreen is configure for 12-bit values so the raw ranges are 0-4096. - * So for example, if your display is 320x240, then THRESHX=3 and THRESHY=4 - * would correspond to one pixel. Default: 4 - */ - -#ifndef CONFIG_TOUCHSCREEN_THRESHX -# define CONFIG_TOUCHSCREEN_THRESHX 12 -#endif - -#ifndef CONFIG_TOUCHSCREEN_THRESHY -# define CONFIG_TOUCHSCREEN_THRESHY 12 -#endif - -#ifndef CONFIG_TOUCHSCREEN_AVG_SAMPLES -# define CONFIG_TOUCHSCREEN_AVG_SAMPLES 2 -#endif - -#ifndef CONFIG_TOUCHSCREEN_NPOLLWAITERS -# define CONFIG_TOUCHSCREEN_NPOLLWAITERS 2 -#endif - -/* Driver support ***********************************************************/ - -/* This format is used to construct the /dev/input[n] device driver path. It - * is defined here so that it will be used consistently in all places. - */ - -#define DEV_FORMAT "/dev/input%d" -#define DEV_NAMELEN 16 - -/* Mikroe-STM32M4 Touchscreen Hardware Definitions ************************** - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * --- ---------------------------------- -------------------- -------------- - * 35 PB0 LCD-YD YD Analog input - * 36 PB1 LCD-XL XL Analog input - * 95 PB8 DRIVEA Drives XR, XL and YU - * 96 PB9 DRIVEB Drives YD - */ - -#define LCD_YD_PIN (0) -#define LCD_XL_PIN (1) -#define LCD_YD_CHANNEL (8) -#define LCD_XL_CHANNEL (9) -#define LCD_DRIVEA_PIN (8) -#define LCD_DRIVEB_PIN (9) - -#define LCD_DRIVEA_BIT (1 << LCD_DRIVEA_PIN) -#define LCD_DRIVEB_BIT (1 << LCD_DRIVEB_PIN) -#define LCD_SAMPX_BITS (LCD_DRIVEA_BIT | (LCD_DRIVEB_BIT << 16)) -#define LCD_SAMPY_BITS (LCD_DRIVEB_BIT | (LCD_DRIVEA_BIT << 16)) -#define LCD_TP_PORT_SETRESET STM32_GPIOB_BSRR - -#define TC_ADC_BASE STM32_ADC2_BASE /* ADC Channel base for TP */ -#define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) - -/* Conversions are performed as 10-bit samples represented as 16-bit */ - -#define MAX_ADC (4096) - -/* A measured value has to be within this range to be considered */ - -#define UPPER_THRESHOLD (MAX_ADC-1) -#define LOWER_THRESHOLD (362) - -/* Delays *******************************************************************/ - -/* All values will be increased by one system timer tick (probably 10MS). */ - -#define TC_PENUP_POLL_TICKS MSEC2TICK(70) /* IDLE polling rate: 70 MSec */ -#define TC_PENDOWN_POLL_TICKS MSEC2TICK(40) /* Active polling rate: 40 MSec */ -#define TC_DEBOUNCE_TICKS MSEC2TICK(16) /* Delay before re-sampling: 16 MSec */ -#define TC_SAMPLE_TICKS MSEC2TICK(4) /* Delay for A/D sampling: 4 MSec */ -#define TC_SETTLE_TICKS MSEC2TICK(10) /* Delay for A/D settling: 10 MSec */ -#define TC_RESAMPLE_TICKS TC_SAMPLE_TICKS - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This enumeration describes the state of touchscreen state machine */ - -enum tc_state_e -{ - TC_READY = 0, /* Ready to begin next sample */ - TC_READY_SETTLE, /* Allowing time for Y DRIVE to settle */ - TC_YPENDOWN, /* Allowing time for the Y pen down sampling */ - TC_DEBOUNCE, /* Allowing a debounce time for the first sample */ - TC_RESAMPLE, /* Restart sampling on a bad measurement */ - TC_YSAMPLE, /* Allowing time for the Y sampling */ - TC_XSETTLE, /* Allowing time for the X to settle after changing DRIVE */ - TC_XSAMPLE, /* Allowing time for the X sampling */ - TC_XRESAMPLE, /* Allow time to resample X */ - TC_PENDOWN, /* Conversion is complete -- pen down */ - TC_PENUP /* Conversion is complete -- pen up */ -}; - -/* This describes the state of one contact */ - -enum tc_contact_e -{ - CONTACT_NONE = 0, /* No contact */ - CONTACT_DOWN, /* First contact */ - CONTACT_MOVE, /* Same contact, possibly different position */ - CONTACT_UP, /* Contact lost */ -}; - -/* This structure describes the results of one touchscreen sample */ - -struct tc_sample_s -{ - uint8_t id; /* Sampled touch point ID */ - uint8_t contact; /* Contact state (see enum tc_contact_e) */ - bool valid; /* True: x,y contain valid, sampled data */ - uint16_t x; /* Thresholded X position */ - uint16_t y; /* Thresholded Y position */ -}; - -/* This structure describes the state of one touchscreen driver instance */ - -struct tc_dev_s -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - uint8_t crefs; /* Number of times the device has been opened */ -#endif - uint8_t state; /* See enum tc_state_e */ - uint8_t nwaiters; /* Number of threads waiting for touchscreen data */ - uint8_t id; /* Current touch point ID */ - volatile bool penchange; /* An unreported event is buffered */ - uint16_t value; /* Partial sample value (Y+ or X-) */ - uint16_t newy; /* New, un-thresholded Y value */ - uint8_t sampcount; /* Count of samples for average so far */ - uint8_t resamplecount; /* Countdown to PENUP */ - mutex_t devlock; /* Manages exclusive access to this structure */ - sem_t waitsem; /* Used to wait for the availability of data */ - struct tc_sample_s sample; /* Last sampled touch point data */ - struct work_s work; /* Supports the state machine delayed processing */ - - /* The following is a list if poll structures of threads waiting for - * driver events. The 'struct pollfd' reference for each open is also - * retained in the f_priv field of the 'struct file'. - */ - - struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS]; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void tc_adc_init(void); -static void tc_adc_start_sample(int pin); -static uint16_t tc_adc_read_sample(void); -static void tc_y_sample(void); -static void tc_x_sample(void); -static inline bool tc_valid_sample(uint16_t sample); - -static void tc_notify(struct tc_dev_s *priv); -static int tc_sample(struct tc_dev_s *priv, - struct tc_sample_s *sample); -static int tc_waitsample(struct tc_dev_s *priv, - struct tc_sample_s *sample); -static void tc_worker(void *arg); - -/* Character driver methods */ - -static int tc_open(struct file *filep); -static int tc_close(struct file *filep); -static ssize_t tc_read(struct file *filep, char *buffer, size_t len); -static int tc_ioctl(struct file *filep, int cmd, unsigned long arg); -static int tc_poll(struct file *filep, struct pollfd *fds, bool setup); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This the vtable that supports the character driver interface */ - -static const struct file_operations g_tc_fops = -{ - tc_open, /* open */ - tc_close, /* close */ - tc_read, /* read */ - NULL, /* write */ - NULL, /* seek */ - tc_ioctl, /* ioctl */ - NULL, /* mmap */ - NULL, /* truncate */ - tc_poll /* poll */ -}; - -/* If only a single touchscreen device is supported, then the driver state - * structure may as well be pre-allocated. - */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE -static struct tc_dev_s g_touchscreen; -static bool g_touchinitdone = false; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: tc_adc_getreg - * - * Description: - * Read the value of an TC ADC channel (#2) register. - * - * Input Parameters: - * offset - The offset to the register to read - * value - * - * Returned Value: - * - ****************************************************************************/ - -static inline uint32_t tc_adc_getreg(int offset) -{ - return getreg32(TC_ADC_BASE + offset); -} - -/**************************************************************************** - * Name: tc_adc_putreg - * - * Description: - * Set the value of an ADC register. - * - * Input Parameters: - * offset - The offset to the register to read - * - * Returned Value: - * - ****************************************************************************/ - -static inline void tc_adc_putreg(int offset, uint32_t value) -{ - putreg32(value, TC_ADC_BASE + offset); -} - -/**************************************************************************** - * Name: tc_adc_init - * - * Description: - * Initialize ADC Channel #2 for use with the touch panel. The touch panel - * uses Channels 8 and 9 (PB0 and PB1) to read the X and Y axis touch - * positions. - * - ****************************************************************************/ - -static void tc_adc_init(void) -{ - irqstate_t flags; - uint32_t regval; - - /* Do an rcc reset to reset the ADC peripheral */ - - /* Disable interrupts. This is necessary because the APB2RTSR register - * is used by several different drivers. - */ - - flags = enter_critical_section(); - - /* Enable ADC reset state */ - - regval = getreg32(STM32_RCC_APB2RSTR); - regval |= RCC_APB2RSTR_ADCRST; - putreg32(regval, STM32_RCC_APB2RSTR); - - /* Release ADC from reset state */ - - regval &= ~RCC_APB2RSTR_ADCRST; - putreg32(regval, STM32_RCC_APB2RSTR); - - /* Initialize the watchdog high threshold register */ - - tc_adc_putreg(STM32_ADC_HTR_OFFSET, 0x00000fff); - - /* Initialize the watchdog low threshold register */ - - tc_adc_putreg(STM32_ADC_LTR_OFFSET, 0x00000000); - - /* Initialize the same sample time for each ADC 55.5 cycles - * - * During sample cycles channel selection bits must remain unchanged. - * - * 000: 1.5 cycles - * 001: 7.5 cycles - * 010: 13.5 cycles - * 011: 28.5 cycles - * 100: 41.5 cycles - * 101: 55.5 cycles - * 110: 71.5 cycles - * 111: 239.5 cycles - */ - - tc_adc_putreg(STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); - tc_adc_putreg(STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); - - /* ADC CR1 Configuration */ - - regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET); - - /* Initialize the Analog watchdog enable */ - - regval &= ~ADC_CR1_AWDEN; - regval |= (LCD_YD_CHANNEL << ADC_CR1_AWDCH_SHIFT); - - /* Enable interrupt flags */ - - /* regval |= ADC_CR1_ALLINTS; */ - - /* Disable Overrun interrupt */ - - regval &= ~ADC_CR1_OVRIE; - - /* Set the resolution of the conversion. We only need 10 bits. */ - - regval |= ADC_CR1_RES_12BIT; - - tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); - - /* ADC CR2 Configuration */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - - /* Clear CONT, continuous mode disable. We will perform single - * sampling on one channel at a time. - */ - - regval &= ~ADC_CR2_CONT; - - /* Set ALIGN (Right = 0) */ - - regval &= ~ADC_CR2_ALIGN; - - /* External trigger disable. We will do SW triggering */ - - regval &= ~ADC_CR2_EXTEN_MASK; - - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); - - /* Configuration of the channel conversion - start with Y sampling */ - - regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - regval |= LCD_YD_CHANNEL; - tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); - - /* Set the number of conversions = 1 */ - - regval = tc_adc_getreg(STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; - regval |= 0 << ADC_SQR1_L_SHIFT; - tc_adc_putreg(STM32_ADC_SQR1_OFFSET, regval); - - /* ADC CCR configuration */ - - regval = getreg32(STM32_ADC_CCR); - regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | - ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATEN | - ADC_CCR_TSVREFE); - regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | - ADC_CCR_ADCPRE_DIV2); - putreg32(regval, STM32_ADC_CCR); - - /* Set ADON to wake up the ADC from Power Down state. */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_ADON; - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); - - /* Restore the IRQ state */ - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: tc_adc_start_sample - * - * Description: - * Perform A/D sampling. Time must be allowed between the start of - * sampling and conversion (approx. 100Ms). - * - ****************************************************************************/ - -static void tc_adc_start_sample(int channel) -{ - uint32_t regval; - - /* Configure the specified channel for ADC conversion. */ - - regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; - regval |= channel; - tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); - - /* Configure the Watchdog for this channel */ - - regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET) & ADC_CR1_AWDCH_MASK; - regval |= (channel << ADC_CR1_AWDCH_SHIFT); - tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); - - /* Start the conversion */ - - regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); - regval |= ADC_CR2_SWSTART; - tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); -} - -/**************************************************************************** - * Name: tc_adc_read_sample - * - * Description: - * Begin A/D conversion. Time must be allowed between the start of - * sampling and conversion (approx. 100Ms). - * - * Assumptions: - * 1) All output pins configured as outputs: - * 2) Appropriate pins are driven high and low - * - ****************************************************************************/ - -static uint16_t tc_adc_read_sample(void) -{ - uint16_t retval; - uint32_t adcsr; - uint16_t count = 0; - - /* Validate the conversion is complete */ - - adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); - while ((adcsr & ADC_SR_EOC) == 0) - { - adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); - count++; - } - - /* Read the sample */ - - retval = tc_adc_getreg(STM32_ADC_DR_OFFSET); - retval &= ADC_DR_RDATA_MASK; - - if (count > 0) - { - iinfo("Count = %d\n", count); - } - - return retval; -} - -/**************************************************************************** - * Name: tc_y_sample - * - * Description: - * Initiate sampling on Y - * - ****************************************************************************/ - -static void tc_y_sample(void) -{ - /* Start the Y axis sampling */ - - tc_adc_start_sample(LCD_XL_CHANNEL); -} - -/**************************************************************************** - * Name: tc_x_sample - * - * Description: - * Initiate sampling on X - * - ****************************************************************************/ - -static void tc_x_sample(void) -{ - /* Start the X axis sampling */ - - tc_adc_start_sample(LCD_YD_CHANNEL); -} - -/**************************************************************************** - * Name: tc_valid_sample - ****************************************************************************/ - -static inline bool tc_valid_sample(uint16_t sample) -{ - return (sample > LOWER_THRESHOLD); -} - -/**************************************************************************** - * Name: tc_notify - ****************************************************************************/ - -static void tc_notify(struct tc_dev_s *priv) -{ - /* If no threads have the driver open, then just dump the state */ - -#ifdef CONFIG_TOUCHSCREEN_REFCNT - if ((priv->crefs == 0) && priv->sample.contact == CONTACT_UP) - { - priv->sample.contact = CONTACT_NONE; - priv->sample.valid = false; - priv->id++; - return; - } -#endif - - /* If there are threads waiting on poll() for touchscreen data to become - * available, then wake them up now. NOTE: we wake up all waiting threads - * because we do not know that they are going to do. If they all try to - * read the data, then some make end up blocking after all. - */ - - poll_notify(priv->fds, CONFIG_TOUCHSCREEN_NPOLLWAITERS, POLLIN); - - /* If there are threads waiting for read data, then signal one of them - * that the read data is available. - */ - - if (priv->nwaiters > 0) - { - /* After posting this semaphore, we need to exit because the - * touchscreen is no longer available. - */ - - nxsem_post(&priv->waitsem); - } -} - -/**************************************************************************** - * Name: tc_sample - * - * Assumptions: pre-emption is disabled - * - ****************************************************************************/ - -static int tc_sample(struct tc_dev_s *priv, - struct tc_sample_s *sample) -{ - int ret = -EAGAIN; - - /* Is there new touchscreen sample data available? */ - - if (priv->penchange) - { - /* Yes.. the state has changed in some way. Return a copy of the - * sampled data. - */ - - memcpy(sample, &priv->sample, sizeof(struct tc_sample_s)); - - /* Now manage state transitions */ - - if (sample->contact == CONTACT_UP) - { - /* Next.. no contact. Increment the ID so that next contact ID - * will be unique. X/Y positions are no longer valid. - */ - - priv->sample.contact = CONTACT_NONE; - priv->sample.valid = false; - priv->id++; - } - else if (sample->contact == CONTACT_DOWN) - { - /* First report -- next report will be a movement */ - - priv->sample.contact = CONTACT_MOVE; - } - - priv->penchange = false; - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: tc_waitsample - ****************************************************************************/ - -static int tc_waitsample(struct tc_dev_s *priv, - struct tc_sample_s *sample) -{ - int ret; - irqstate_t flags; - - /* Interrupts must be disabled when this is called to (1) prevent posting - * of semaphores from interrupt handlers, and (2) to prevent sampled data - * from changing until it has been reported. - */ - - flags = enter_critical_section(); - - /* Now release the mutex that manages mutually exclusive access to - * the device structure. This may cause other tasks to become ready to - * run, but they cannot run yet because pre-emption is disabled. - */ - - nxmutex_unlock(&priv->devlock); - - /* Try to get the a sample... if we cannot, then wait on the semaphore - * that is posted when new sample data is available. - */ - - while (tc_sample(priv, sample) < 0) - { - /* Wait for a change in the touchscreen state */ - - priv->nwaiters++; - ret = nxsem_wait(&priv->waitsem); - priv->nwaiters--; - - if (ret < 0) - { - goto errout; - } - } - - /* Re-acquire the semaphore that manages mutually exclusive access to - * the device structure. We may have to wait here. But we have our - * sample. Interrupts and pre-emption will be re-enabled while we wait. - */ - - ret = nxmutex_lock(&priv->devlock); - -errout: - /* Then re-enable interrupts. We might get interrupt here and there - * could be a new sample. But no new threads will run because we still - * have pre-emption disabled. - */ - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: tc_worker - ****************************************************************************/ - -static void tc_worker(void *arg) -{ - struct tc_dev_s *priv = (struct tc_dev_s *)arg; - uint32_t delay = TC_PENUP_POLL_TICKS; - uint16_t value; - uint16_t newx = 0; - int16_t xdiff; - int16_t ydiff; - - DEBUGASSERT(priv != NULL); - - /* Perform the next action based on the state of the conversions */ - - switch (priv->state) - { - /* The touchscreen is IDLE and we are ready to begin the next sample */ - - case TC_READY: - { - /* Select DRIVE for Y sampling */ - - /* Configure XL, XR with drive voltages and disable YU drive. Note - * that this is configuring the DRIVEA and DRIVEB outputs to enable - * the on-board transistor drive logic to energize the touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; - - /* Allow time for the Y DRIVE to settle */ - - priv->resamplecount = 0; - priv->sampcount = 0; - priv->value = 0; - priv->state = TC_READY_SETTLE; - delay = TC_SETTLE_TICKS; - } - break; - - case TC_READY_SETTLE: - { - /* Start Y sampling */ - - tc_y_sample(); - - /* Allow time for the Y pend down sampling */ - - priv->state = TC_YPENDOWN; - delay = TC_SAMPLE_TICKS; - } - break; - - /* The Y sampling time has elapsed and the Y value should be ready - * for conversion - */ - - case TC_YPENDOWN: - { - /* Convert the Y sample value */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that there is no touch - * and that the sampling period is complete. - */ - - if (!tc_valid_sample(value)) - { - priv->state = TC_PENUP; - } - else - { - /* Allow time for touch inputs to stabilize */ - - priv->state = TC_DEBOUNCE; - delay = TC_DEBOUNCE_TICKS; - } - } - break; - - /* The debounce time period has elapsed and we are ready to re-sample - * the touchscreen. - */ - - case TC_RESAMPLE: - { - /* Select DRIVE for Y sampling */ - - /* Configure XL, XR with drive voltages and disable YU drive. Note - * that this is configuring the DRIVEA and DRIVEB outputs to enable - * the on-board transistor drive logic to energize the touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; - - /* Allow time for the Y DRIVE to settle */ - - priv->state = TC_DEBOUNCE; - delay = TC_SETTLE_TICKS; - } - break; - - case TC_DEBOUNCE: - { - /* (Re-)start Y sampling */ - - tc_y_sample(); - - /* Allow time for the Y sampling */ - - priv->state = TC_YSAMPLE; - delay = TC_SAMPLE_TICKS; - } - break; - - /* The Y sampling period has elapsed and we are ready to perform the - * conversion. - */ - - case TC_YSAMPLE: /* Allowing time for the Y sampling */ - { - /* Read the Y axis position */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that we lost the - * contact before all of the conversions were completed. At - * converted value at the maximum value is probably bad too. - */ - - if (!tc_valid_sample(value)) - { -#ifdef CONFIG_TOUCHSCREEN_RESAMPLE - priv->state = TC_RESAMPLE; - delay = TC_RESAMPLE_TICKS; -#else - priv->state = TC_PENUP; -#endif - } - else - { - value = MAX_ADC - value; - priv->value += value; - if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) - { - priv->state = TC_READY_SETTLE; - delay = 1; - break; - } - - priv->newy = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; - priv->value = 0; - priv->sampcount = 0; - iinfo("Y=%d\n", priv->newy); - - /* Configure YU and YD with drive voltages and disable XR drive. - * Note that this is configuring the DRIVEA and DRIVEB outputs - * to enable the on-board transistor drive logic to energize the - * touch panel. - */ - - *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPX_BITS; - - /* Allow time for the X sampling */ - - priv->state = TC_XSETTLE; - delay = TC_SETTLE_TICKS; - } - } - break; - - case TC_XRESAMPLE: /* Perform X resampling */ - { - if (priv->resamplecount-- == 0) - { - priv->state = TC_PENUP; - break; - } - } - - case TC_XSETTLE: /* Allowing time X to settle after changing DRIVE */ - { - /* The X Drive settling time has elaspsed and it's time to start - * the conversion - */ - - /* Start X sampling */ - - tc_x_sample(); - - /* Allow time for the X sampling */ - - priv->state = TC_XSAMPLE; - delay = TC_SAMPLE_TICKS; - } - break; - - case TC_XSAMPLE: /* Allowing time for the X sampling */ - { - /* Read the converted X axis position */ - - value = tc_adc_read_sample(); - - /* A converted value at the minimum would mean that we lost the - * contact before all of the conversions were completed. At - * converted value at the maximum value is probably bad too. - */ - - if (!tc_valid_sample(value)) - { -#ifdef CONFIG_TOUCHSCREEN_RESAMPLE - priv->state = TC_XRESAMPLE; - if (priv->resamplecount == 0) - priv->resamplecount = 1; - delay = TC_RESAMPLE_TICKS; -#else - priv->state = TC_PENUP; -#endif - } - else - { - /* Calculate the X axis position */ - - priv->value += value; - if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) - { - priv->state = TC_XSETTLE; - delay = 1; - break; - } - - newx = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; - iinfo("X=%d\n", newx); - - /* Samples are available */ - - priv->state = TC_PENDOWN; - } - } - break; - } - - /* Check for terminal conditions.. */ - - /* Check if the sampling resulted in a pen up decision. If so, we need to - * handle the change from pen down to pen up. - */ - - if (priv->state == TC_PENUP) - { - /* Ignore if the pen was already down (CONTACT_NONE == pen up and - * already reported. CONTACT_UP == pen up, but not reported) - */ - - if (priv->sample.contact != CONTACT_NONE && - priv->sample.contact != CONTACT_UP) - { - /* The pen is up. We know from the above test, that this is a - * loss of contact condition. This will be changed to CONTACT_NONE - * after the loss of contact is sampled. - */ - - priv->sample.contact = CONTACT_UP; - - /* Indicate the availability of new sample data for this ID */ - - priv->sample.id = priv->id; - priv->penchange = true; - - /* Notify any waiters that new touchscreen data is available */ - - iinfo("1:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); - - tc_notify(priv); - } - - /* Set up for the next poll */ - - priv->sample.valid = false; - priv->state = TC_READY; - delay = TC_PENUP_POLL_TICKS; - } - - /* Check if the sampling resulted in a pen down decision. */ - - else if (priv->state == TC_PENDOWN) - { - /* It is a pen down event. If the last loss-of-contact event has not - * been processed yet, then we have to ignore the pen down event (or - * else it will look like a drag event) - */ - - if (priv->sample.contact != CONTACT_UP) - { - /* Perform a thresholding operation so that the results will be - * more stable. If the difference from the last sample is small, - * then ignore the event. - */ - - xdiff = (int16_t)priv->sample.x - (int16_t)newx; - if (xdiff < 0) - { - xdiff = -xdiff; - } - - ydiff = (int16_t)priv->sample.y - (int16_t)priv->newy; - if (ydiff < 0) - { - ydiff = -ydiff; - } - - if (xdiff >= CONFIG_TOUCHSCREEN_THRESHX || - ydiff >= CONFIG_TOUCHSCREEN_THRESHY) - { - /* There is some change above the threshold... - * Report the change. - */ - -#ifdef CONFIG_LCD_LANDSCAPE - priv->sample.x = MAX_ADC - priv->newy; - priv->sample.y = newx; -#else - priv->sample.x = newx; - priv->sample.y = priv->newy; -#endif - priv->sample.valid = true; - - /* If this is the first (acknowledged) penddown report, then - * report this as the 1st contact. If contact == CONTACT_DOWN, - * it will be set to set to CONTACT_MOVE after the contact is - * first sampled. - */ - - if (priv->sample.contact != CONTACT_MOVE) - { - /* First contact */ - - priv->sample.contact = CONTACT_DOWN; - } - - /* Indicate the availability of new sample data for this ID */ - - priv->sample.id = priv->id; - priv->penchange = true; - - /* Notify any waiters that nes touchscreen data is available */ - - iinfo("2:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); - - tc_notify(priv); - } - } - - /* Set up for the next poll */ - - priv->state = TC_READY; - delay = TC_PENDOWN_POLL_TICKS; - } - - /* Set up the next sample event */ - - work_queue(HPWORK, &priv->work, tc_worker, priv, delay); -} - -/**************************************************************************** - * Name: tc_open - ****************************************************************************/ - -static int tc_open(struct file *filep) -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - struct inode *inode; - struct tc_dev_s *priv; - uint8_t tmp; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Increment the reference count */ - - tmp = priv->crefs + 1; - if (tmp == 0) - { - /* More than 255 opens; uint8_t overflows to zero */ - - ret = -EMFILE; - goto errout_with_lock; - } - - /* When the reference increments to 1, this is the first open event - * on the driver.. and an opportunity to do any one-time initialization. - */ - - /* Save the new open count on success */ - - priv->crefs = tmp; - -errout_with_lock: - nxmutex_unlock(&priv->devlock); - return ret; -#else - return OK; -#endif -} - -/**************************************************************************** - * Name: tc_close - ****************************************************************************/ - -static int tc_close(struct file *filep) -{ -#ifdef CONFIG_TOUCHSCREEN_REFCNT - struct inode *inode; - struct tc_dev_s *priv; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Decrement the reference count unless it would decrement a negative - * value. When the count decrements to zero, there are no further - * open references to the driver. - */ - - if (priv->crefs >= 1) - { - priv->crefs--; - } - - nxmutex_unlock(&priv->devlock); -#endif - return OK; -} - -/**************************************************************************** - * Name: tc_read - ****************************************************************************/ - -static ssize_t tc_read(struct file *filep, char *buffer, size_t len) -{ - struct inode *inode; - struct tc_dev_s *priv; - struct touch_sample_s *report; - struct tc_sample_s sample; - int ret; - - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Verify that the caller has provided a buffer large enough to receive - * the touch data. - */ - - if (len < SIZEOF_TOUCH_SAMPLE_S(1)) - { - /* We could provide logic to break up a touch report into segments and - * handle smaller reads... but why? - */ - - return -ENOSYS; - } - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Try to read sample data. */ - - ret = tc_sample(priv, &sample); - if (ret < 0) - { - /* Sample data is not available now. We would ave to wait to get - * receive sample data. If the user has specified the O_NONBLOCK - * option, then just return an error. - */ - - if (filep->f_oflags & O_NONBLOCK) - { - ret = -EAGAIN; - goto errout; - } - - /* Wait for sample data */ - - ret = tc_waitsample(priv, &sample); - if (ret < 0) - { - /* We might have been awakened by a signal */ - - goto errout; - } - } - - /* In any event, we now have sampled touchscreen data that we can report - * to the caller. - */ - - report = (struct touch_sample_s *)buffer; - memset(report, 0, SIZEOF_TOUCH_SAMPLE_S(1)); - report->npoints = 1; - report->point[0].id = sample.id; - report->point[0].x = sample.x; - report->point[0].y = sample.y; - - /* Report the appropriate flags */ - - if (sample.contact == CONTACT_UP) - { - /* Pen is now up. Is the positional data valid? This is important to - * know because the release will be sent to the window based on its - * last positional data. - */ - - if (sample.valid) - { - report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID | - TOUCH_POS_VALID | TOUCH_PRESSURE_VALID; - } - else - { - report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID; - } - } - else - { - if (sample.contact == CONTACT_DOWN) - { - /* First contact */ - - report->point[0].flags = TOUCH_DOWN | TOUCH_ID_VALID | - TOUCH_POS_VALID; - } - else /* if (sample->contact == CONTACT_MOVE) */ - { - /* Movement of the same contact */ - - report->point[0].flags = TOUCH_MOVE | TOUCH_ID_VALID | - TOUCH_POS_VALID; - } - } - - ret = SIZEOF_TOUCH_SAMPLE_S(1); - -errout: - nxmutex_unlock(&priv->devlock); - return ret; -} - -/**************************************************************************** - * Name: tc_ioctl - ****************************************************************************/ - -static int tc_ioctl(struct file *filep, int cmd, unsigned long arg) -{ -#if 1 - iinfo("cmd: %d arg: %ld\n", cmd, arg); - return -ENOTTY; /* None yet supported */ -#else - struct inode *inode; - struct tc_dev_s *priv; - int ret; - - iinfo("cmd: %d arg: %ld\n", cmd, arg); - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Get exclusive access to the driver data structure */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - /* Process the IOCTL by command */ - - switch (cmd) - { - /* ADD IOCTL COMMAND CASES HERE */ - - default: - ret = -ENOTTY; - break; - } - - nxmutex_unlock(&priv->devlock); - return ret; -#endif -} - -/**************************************************************************** - * Name: tc_poll - ****************************************************************************/ - -static int tc_poll(struct file *filep, struct pollfd *fds, bool setup) -{ - struct inode *inode; - struct tc_dev_s *priv; - int ret; - int i; - - iinfo("setup: %d\n", (int)setup); - DEBUGASSERT(fds); - inode = filep->f_inode; - - DEBUGASSERT(inode->i_private); - priv = inode->i_private; - - /* Are we setting up the poll? Or tearing it down? */ - - ret = nxmutex_lock(&priv->devlock); - if (ret < 0) - { - return ret; - } - - if (setup) - { - /* Ignore waits that do not include POLLIN */ - - if ((fds->events & POLLIN) == 0) - { - ierr("ERROR: Missing POLLIN: revents: %08" PRIx32 "\n", - fds->revents); - ret = -EDEADLK; - goto errout; - } - - /* This is a request to set up the poll. Find an available - * slot for the poll structure reference - */ - - for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++) - { - /* Find an available slot */ - - if (!priv->fds[i]) - { - /* Bind the poll structure and this slot */ - - priv->fds[i] = fds; - fds->priv = &priv->fds[i]; - break; - } - } - - if (i >= CONFIG_TOUCHSCREEN_NPOLLWAITERS) - { - ierr("ERROR: No available slot found: %d\n", i); - fds->priv = NULL; - ret = -EBUSY; - goto errout; - } - - /* Should we immediately notify on any of the requested events? */ - - if (priv->penchange) - { - poll_notify(&fds, 1, POLLIN); - } - } - else if (fds->priv) - { - /* This is a request to tear down the poll. */ - - struct pollfd **slot = (struct pollfd **)fds->priv; - DEBUGASSERT(slot != NULL); - - /* Remove all memory of the poll setup */ - - *slot = NULL; - fds->priv = NULL; - } - -errout: - nxmutex_unlock(&priv->devlock); - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ - struct tc_dev_s *priv; - char devname[DEV_NAMELEN]; -#ifdef CONFIG_TOUCHSCREEN_MULTIPLE - irqstate_t flags; -#endif - int ret; - - iinfo("minor: %d\n", minor); - DEBUGASSERT(minor >= 0 && minor < 100); - - /* If we only have one touchscreen, check if we already did init */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - if (g_touchinitdone) - { - return OK; - } -#endif - - /* Configure the touchscreen DRIVEA and DRIVEB pins for output */ - - stm32_configgpio(GPIO_TP_DRIVEA); - stm32_configgpio(GPIO_TP_DRIVEB); - - /* Configure Analog inputs for sampling X and Y coordinates */ - - stm32_configgpio(GPIO_TP_XL); - stm32_configgpio(GPIO_TP_YD); - - tc_adc_init(); - - /* Create and initialize a touchscreen device driver instance */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - priv = &g_touchscreen; -#else - priv = kmm_malloc(sizeof(struct tc_dev_s)); - if (!priv) - { - ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct tc_dev_s)); - return -ENOMEM; - } -#endif - - /* Initialize the touchscreen device driver instance */ - - memset(priv, 0, sizeof(struct tc_dev_s)); - nxmutex_init(&priv->devlock); /* Initialize device structure mutex */ - nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ - - /* Register the device as an input device */ - - snprintf(devname, sizeof(devname), DEV_FORMAT, minor); - iinfo("Registering %s\n", devname); - - ret = register_driver(devname, &g_tc_fops, 0666, priv); - if (ret < 0) - { - ierr("ERROR: register_driver() failed: %d\n", ret); - goto errout_with_priv; - } - - /* Schedule work to perform the initial sampling and to set the data - * availability conditions. - */ - - priv->state = TC_READY; - ret = work_queue(HPWORK, &priv->work, tc_worker, priv, 0); - if (ret != 0) - { - ierr("ERROR: Failed to queue work: %d\n", ret); - goto errout_with_priv; - } - - /* And return success (?) */ - -#ifndef CONFIG_TOUCHSCREEN_MULTIPLE - g_touchinitdone = true; -#endif - - return OK; - -errout_with_priv: - nxmutex_destroy(&priv->devlock); - nxsem_destroy(&priv->waitsem); -#ifdef CONFIG_TOUCHSCREEN_MULTIPLE - kmm_free(priv); -#endif - return ret; -} - -#endif /* CONFIG_INPUT */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c deleted file mode 100644 index bba5752941bad..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "mikroe-stm32f4.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB host Mass Storage Class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt deleted file mode 100644 index 3444cc83430de..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig deleted file mode 100644 index 1cf2c0c90efb6..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=4 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig deleted file mode 100644 index f88aae75d79c5..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ /dev/null @@ -1,85 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig deleted file mode 100644 index abb3742b68f24..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig deleted file mode 100644 index 083b57d867fd4..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig deleted file mode 100644 index 15f67d0b52e6f..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f103rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_PARTIAL_REMAP_1=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f103rb/include/board.h b/boards/arm/stm32/nucleo-f103rb/include/board.h deleted file mode 100644 index 6eb712c909cf5..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/include/board.h +++ /dev/null @@ -1,251 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB2 TIM 1 will receive PCLK2 (72MHz) */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo F103RB board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F103RBT6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F103RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F103RB supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F103RBT6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F103RBT6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#ifdef CONFIG_BOARD_STM32_IHM07M1 - -/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with - * the L6230 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -/* Configured in stm32/hardware/stm32f103r_pinmap.h */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) - -/* DIAG/ENABLE */ - -# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_CNF_OUTOD|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM07M1 */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs deleted file mode 100644 index a9ad56f5283cd..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f103rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script b/boards/arm/stm32/nucleo-f103rb/scripts/ld.script deleted file mode 100644 index 26fb217a12ab3..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103RBT6 has 128Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt deleted file mode 100644 index 513418e9419d8..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt +++ /dev/null @@ -1,51 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() - - if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) - endif() -endif() - -if(CONFIG_BOARD_STM32_IHM07M1) - list(APPEND SRCS stm32_foc_ihm07m1.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f103rb/src/Make.defs b/boards/arm/stm32/nucleo-f103rb/src/Make.defs deleted file mode 100644 index fa7a6e9872078..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f103rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) -CSRCS += stm32_foc_ihm07m1.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c deleted file mode 100644 index e3f6006eabc90..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less) */ - -static const uint8_t g_chanlist1[3] = -{ - 0, - 1, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC123_IN0_0, /* PA0/A0 */ - GPIO_ADC123_IN1_0, /* PA1/A1 */ - GPIO_ADC12_IN4_0, /* PA4/A2 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 8, - 11, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC12_IN8_0, /* PB0/A3 */ - GPIO_ADC123_IN11_0, /* PC1/A4 */ - GPIO_ADC123_IN10_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 11, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC12_IN8_0, /* PB0/A3 */ - GPIO_ADC123_IN11_0, /* PC1/A4 */ - GPIO_ADC123_IN10_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c deleted file mode 100644 index 891d76833e2ce..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c deleted file mode 100644 index b2362627a32ec..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c deleted file mode 100644 index 8ea6ec5e144dc..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c +++ /dev/null @@ -1,143 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F103RB_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c deleted file mode 100644 index 5631fb1246a2d..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c deleted file mode 100644 index f22035b78c4b6..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_ihm07m1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_28p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_239p5 -#define POT_SAMPLE_TIME ADC_SMPR_239p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS -# define IHM07M1_VBUS 1 -#else -# define IHM07M1_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT -# define IHM07M1_POT 1 -#else -# define IHM07M1_POT 0 -#endif - -#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -/* Check ADC1 configuration */ - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -/* TIM1 configuration */ - -#ifndef CONFIG_STM32_TIM1_PARTIAL_REMAP -# error -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* FOC ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN0 (PA0) - * - Current Phase U -> ADC1 INJ2 -> ADC1_IN11 (PC1) - * - Current Phase W -> ADC1 INJ3 -> ADC1_I10 (PC0) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN1 (PA1) - * - POT -> ADC1 REG -> ADC1_IN9 (PB1) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase W high -> TIM1_CH3 (PA10) - * - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - 1, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - 9, /* ADC1 REG - POT */ -#endif - 0, /* ADC1 INJ1 - PHASE 1 */ -#if CONFIG_MOTOR_FOC_SHUNTS == 3 - 11, /* ADC1 INJ2 - PHASE 2 */ - 10, /* ADC1 INJ3 - PHASE 3 */ -#endif -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - GPIO_ADC123_IN1_0, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - GPIO_ADC12_IN9_0, -#endif - GPIO_ADC123_IN0_0, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - GPIO_ADC123_IN11_0, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - GPIO_ADC123_IN10_0, -#endif -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - { - .channel = 2, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - { - .channel = 12, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 1, - .sample_time = CURRENT_SAMPLE_TIME - }, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - { - .channel = 7, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - { - .channel = 6, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - return board_ihm07m1_initialize(&g_adc_cfg); -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c deleted file mode 100644 index e17931280d112..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f103rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF103RB_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c deleted file mode 100644 index cb23d594b1149..0000000000000 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f103rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt deleted file mode 100644 index 9fe17612d1738..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig deleted file mode 100644 index 6d856b068e752..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=4 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig deleted file mode 100644 index 36ccf9508fd0b..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig deleted file mode 100644 index b2d25ed4d8968..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f207zg" -CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_PWM=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f207zg/include/board.h b/boards/arm/stm32/nucleo-f207zg/include/board.h deleted file mode 100644 index bf2ce642c59d5..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/include/board.h +++ /dev/null @@ -1,209 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = - * PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = - * VCO input frequency × PLLN, 50 <= PLLN <= 432 - * PLL output clock frequency = - * VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = - * VCO frequency / PLLQ, 2 <= PLLQ <= 15 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 2) * 100 - * = 400,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 400,000,000 / 4 = 100,000,000 - * RNG Clock - * = PLL_VCO / PLLQ - * = 400,000,000 / 8 = 50,000,000 - * - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(100) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 100000000ul - -/* AHB clock (HCLK) is SYSCLK (100MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timers driven from APB1 will be twice PCLK1 (50MHz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ ---- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Button definitions *******************************************************/ - -/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is - * connected to GPIO PC13. A high value will be sensed when the button is - * depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART3 (Nucleo Virtual Console) */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs deleted file mode 100644 index a0ae3c3954b6f..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script b/boards/arm/stm32/nucleo-f207zg/scripts/ld.script deleted file mode 100644 index 0f8ef1906b016..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207ZG has 1Mb of FLASH beginning at address 0x0800:0000, - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1M - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt deleted file mode 100644 index 5ca78ff3da4ae..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f207zg/src/Make.defs b/boards/arm/stm32/nucleo-f207zg/src/Make.defs deleted file mode 100644 index 3962a5368fde3..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c deleted file mode 100644 index 6a7e27ca6b7da..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC3_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 3, - 10, - 13 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN3_0, /* PA3/A0 */ - GPIO_ADC1_IN10_0, /* PC0/A1 */ - GPIO_ADC1_IN13_0, /* PC3/A2 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 9, - 15, - 8 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN9_0, /* PF3/A3 */ - GPIO_ADC3_IN15_0, /* PF5/A4 */ - GPIO_ADC3_IN8_0, /* PF10/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 9, - 15, - 8 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN9_0, /* PF3/A3 */ - GPIO_ADC3_IN15_0, /* PF5/A4 */ - GPIO_ADC3_IN8_0, /* PF10/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c deleted file mode 100644 index 9a1986701ba20..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c deleted file mode 100644 index 3f7ae0c33c105..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_start.h" -#include "nucleo-f207zg.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) - /* Initialize USB */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c deleted file mode 100644 index 149f1cc0930e1..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "nucleo-f207zg.h" - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - syslog(LOG_INFO, "Initialize CDCACM device\n"); - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c deleted file mode 100644 index 861f569c31f68..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns a - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c deleted file mode 100644 index 298ae7ce61721..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f207zg.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF207ZG_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c deleted file mode 100644 index d984030911228..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_otgfs.h" -#include "nucleo-f207zg.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO -# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE -# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the nucleo-144 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO, - CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - /* Set the Power Switch by driving the active low enable pin */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c deleted file mode 100644 index d0ce94829eef2..0000000000000 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f207zg.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. NOTE: since - * there is only a single LED on-board, this is function is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt deleted file mode 100644 index 62e41b7cca4dc..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig deleted file mode 100644 index ebc1520b3f303..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_FS_LARGEFILE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_NAME_MAX=16 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_QUOTE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=255 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig deleted file mode 100644 index cfdaa95faeb2a..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_INITTHREAD_STACKSIZE=1024 -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=64 -CONFIG_IOB_NBUFFERS=5 -CONFIG_IRQ_WORK_STACKSIZE=1024 -CONFIG_LTO_FULL=y -CONFIG_NAME_MAX=0 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_CAN_ERRORS=y -CONFIG_NET_PREALLOC_DEVIF_CALLBACKS=2 -CONFIG_NET_SOCKOPTS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_PROMPT_MAX=8 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=0 -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_SOCKET=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig deleted file mode 100644 index f25864d20f015..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF302R8_HIGHPRI=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig deleted file mode 100644 index 6deed35ec2b7c..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_HELP=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig deleted file mode 100644 index 6ef0621ec8fc5..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM07M1=y -CONFIG_BOARD_STM32_IHM07M1_POT=y -CONFIG_BOARD_STM32_IHM07M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig deleted file mode 100644 index a9d463268ef04..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ /dev/null @@ -1,85 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig deleted file mode 100644 index 1294b209f920f..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ /dev/null @@ -1,111 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_ENVIRON is not set -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_MQUEUE_NOTIFICATION is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_DISABLE_PTHREAD is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_DMESG is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_ENV is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_EXPORT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_KILL is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_MV is not set -# CONFIG_NSH_DISABLE_PRINTF is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_RMDIR is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_SET is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_SOURCE is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_TRUNCATE is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_UNSET is not set -# CONFIG_NSH_DISABLE_UPTIME is not set -# CONFIG_NSH_DISABLE_USLEEP is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f302r8" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F302R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F302R8=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQPRIO=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM_TOOLCHAIN=y -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CLE=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PREALLOC_MQ_IRQ_MSGS=8 -CONFIG_PREALLOC_MQ_MSGS=8 -CONFIG_PTHREAD_MUTEX_ROBUST=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f302r8/include/board.h b/boards/arm/stm32/nucleo-f302r8/include/board.h deleted file mode 100644 index 21d24f4b50e87..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/include/board.h +++ /dev/null @@ -1,308 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F302R8 board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PB13 of the - * STM32F302R8T6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F302R8. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F302R8 supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F302R8T6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F302R8T6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM2 input ***************************************************************/ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) /* PA2 */ - -/* USART1 - * - * At default use: - * USART1_RX - PB7 - * USART1_TX - PB6 - * - * If CONFIG_NUCLEOF302R8_RS485_WAVESHARE=y use configuration to match RS485 - * shield from Waveshare: - * - * USART1_RX - PA10 - * USART1_TX - PA9 - * RS485_DIR - PA8 (arduino D7) - * - */ - -#ifdef CONFIG_NUCLEOF302R8_RS485_WAVESHARE -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ -# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ - GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ - GPIO_PORTA | GPIO_PIN8) -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_50MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ -#endif - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_3|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN_TX_3|GPIO_SPEED_50MHz) /* PB9 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define STM32_TIM1_TRGO 0 - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PA9 */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* PA12 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_3|GPIO_SPEED_50MHz) /* PB1 */ - -/* TIM2 PWM */ - -#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1_ETR_1|GPIO_SPEED_50MHz) /* PA0 */ -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) /* PA1 */ -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) /* PA9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -#ifdef CONFIG_BOARD_STM32_IHM07M1 - -/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with - * the L6230 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -# define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) - -/* DIAG/ENABLE */ - -# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM07M1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs deleted file mode 100644 index d863be25bf563..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script b/boards/arm/stm32/nucleo-f302r8/scripts/ld.script deleted file mode 100644 index cde87e144cb28..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F302R8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 16Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt deleted file mode 100644 index e5e905b763f6d..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_NUCLEOF302R8_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_BOARD_STM32_IHM07M1) - list(APPEND SRCS stm32_foc_ihm07m1.c) -else() - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f302r8/src/Make.defs b/boards/arm/stm32/nucleo-f302r8/src/Make.defs deleted file mode 100644 index 7c9ce0e0b1fe8..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_NUCLEOF302R8_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) -CSRCS += stm32_foc_ihm07m1.c -else -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c deleted file mode 100644 index f4ec3e6b3179e..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ADC1 -# error ADC1 support must be enabled -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# error ADC1 DMA support must be enabled -#endif - -#define ADC1_NCHANNELS 4 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Use CN8 pins 35, 36, 37 and 38 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 6, 7, 8, 9 -}; - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN6_0, /* PC0 */ - GPIO_ADC1_IN7_0, /* PC1 */ - GPIO_ADC1_IN8_0, /* PC2 */ - GPIO_ADC1_IN9_0, /* PC3 */ -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c deleted file mode 100644 index 0175408b56161..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c deleted file mode 100644 index 36c4aa9905c0d..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c deleted file mode 100644 index 4a878d66e0598..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F302R8_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c deleted file mode 100644 index 581c45bda8e11..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c deleted file mode 100644 index 3fae10a1a6a7b..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c deleted file mode 100644 index 7ccf0ad686be4..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c deleted file mode 100644 index 3d061622c9000..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c +++ /dev/null @@ -1,183 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_ihm07m1.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_19p5 -#define VBUS_SAMPLE_TIME ADC_SMPR_601p5 -#define POT_SAMPLE_TIME ADC_SMPR_601p5 - -/* ADC1 channels used in this example */ - -#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) - -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS -# define IHM07M1_VBUS 1 -#else -# define IHM07M1_VBUS 0 -#endif - -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT -# define IHM07M1_POT 1 -#else -# define IHM07M1_POT 0 -#endif - -#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -/* Check ADC1 configuration */ - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -#if CONFIG_STM32_ADC1_RESOLUTION != 0 -# error -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* FOC ADC configuration: - * - Current Phase V -> ADC1 INJ1 -> ADC1_IN1 (PA0) - * - Current Phase U -> ADC1 INJ2 -> ADC1_IN7 (PC1) - * - Current Phase W -> ADC1 INJ3 -> ADC1_IN6 (PC0) - * optional: - * - VBUS -> ADC1 REG -> ADC1_IN2 (PA1) - * - POT -> ADC1 REG -> ADC1_IN12 (PB1) - * - * TIM1 PWM configuration: - * - Phase U high -> TIM1_CH1 (PA8) - * - Phase V high -> TIM1_CH2 (PA9) - * - Phase W high -> TIM1_CH3 (PA10) - * - */ - -static uint8_t g_adc1_chan[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - 2, /* ADC1 REG - VBUS */ -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - 12, /* ADC1 REG - POT */ -#endif - 1, /* ADC1 INJ1 - PHASE 1 */ -#if CONFIG_MOTOR_FOC_SHUNTS == 3 - 7, /* ADC1 INJ2 - PHASE 2 */ - 6, /* ADC1 INJ3 - PHASE 3 */ -#endif -}; - -static uint32_t g_adc1_pins[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - GPIO_ADC1_IN2_0, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - GPIO_ADC1_IN12_0, -#endif - GPIO_ADC1_IN1_0, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - GPIO_ADC1_IN7_0, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - GPIO_ADC1_IN6_0, -#endif -}; - -/* ADC1 sample time configuration */ - -static adc_channel_t g_adc1_stime[] = -{ -#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS - { - .channel = 2, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef CONFIG_BOARD_STM32_IHM07M1_POT - { - .channel = 12, - .sample_time = POT_SAMPLE_TIME - }, -#endif - { - .channel = 1, - .sample_time = CURRENT_SAMPLE_TIME - }, -#if CONFIG_MOTOR_FOC_SHUNTS > 1 - { - .channel = 7, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -#if CONFIG_MOTOR_FOC_SHUNTS > 2 - { - .channel = 6, - .sample_time = CURRENT_SAMPLE_TIME - }, -#endif -}; - -/* Board specific ADC configuration for FOC */ - -static struct stm32_foc_adc_s g_adc_cfg = -{ - .chan = g_adc1_chan, - .pins = g_adc1_pins, - .stime = g_adc1_stime, - .nchan = ADC1_NCHANNELS, - .regch = ADC1_REGULAR, - .intf = 1 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Initialize FOC driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - return board_ihm07m1_initialize(&g_adc_cfg); -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c deleted file mode 100644 index a7775f2b0ece9..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c +++ /dev/null @@ -1,544 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include - -#ifdef CONFIG_NUCLEOF302R8_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if !defined(HIGHPRI_HAVE_TIM1) -# error "Needs TIM1 to trigger ADC DMA" -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) -# error Max 2 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (3) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 1, -#ifdef CONFIG_STM32_ADC1_DMA - 2, - 11, -#endif -#if INJ_NCHANNELS > 0 - 7, -#endif -#if INJ_NCHANNELS > 1 - 6 -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ -#ifdef CONFIG_STM32_ADC1_DMA - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -#endif -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN7_0, /* PC1/A4 */ -#endif -#if INJ_NCHANNELS > 1 - GPIO_ADC1_IN6_0 /* PC0/A5 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc12_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOS) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dmach1_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma1ch1_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; - int i; - - pending = stm32_dma_intget(STM32_DMA1_CHAN1); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(STM32_DMA1_CHAN1, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC12 ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC12); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA1 CH1 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA1CH1 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA1CH1); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected sequence end interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_NUCLEOF302R8_HIGHPRI */ diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c deleted file mode 100644 index 49997999a1c71..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f302r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOF302R8_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c deleted file mode 100644 index 1895649936c1b..0000000000000 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f302r8.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/CMakeLists.txt deleted file mode 100644 index fb2ec37234ebb..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig deleted file mode 100644 index 8bcd928f594fb..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig deleted file mode 100644 index ed465f2924106..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_EXAMPLES_CAN=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="can_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=15 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_SYSLOG_NONE=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig deleted file mode 100644 index 0a7ca25b383e0..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="hello_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig deleted file mode 100644 index ae360cfb4b3fd..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig deleted file mode 100644 index fd970c2a6761e..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_CAN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_SSD1351=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXSTART_EXTERNINIT=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig deleted file mode 100644 index 3f4c63188fe85..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=2 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_CH2OUT=y -CONFIG_STM32_TIM3_CHANNEL1=y -CONFIG_STM32_TIM3_CHANNEL2=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig deleted file mode 100644 index 4576cc7e981d2..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303re" -CONFIG_ARCH_BOARD_NUCLEO_F303RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_EXAMPLES_SERIALRX=y -CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="serialrx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_UART4=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_UART4_BAUD=9600 diff --git a/boards/arm/stm32/nucleo-f303re/include/board.h b/boards/arm/stm32/nucleo-f303re/include/board.h deleted file mode 100644 index d5cb48ca3b4f8..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/include/board.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F303RE board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F303RET6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F303RE. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F303RE supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F303RET6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F303RET6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_25MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_25MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) - -/* UART4 */ - -#define GPIO_UART4_RX (GPIO_UART4_RX_0|GPIO_SPEED_50MHz) -#define GPIO_UART4_TX (GPIO_UART4_TX_0|GPIO_SPEED_50MHz) - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 -#define ADC2_DMA_CHAN DMACHAN_ADC2_1 -#define ADC3_DMA_CHAN DMACHAN_ADC3 -#define ADC4_DMA_CHAN DMACHAN_ADC4_1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32/nucleo-f303re/scripts/Make.defs deleted file mode 100644 index eb1b16a4ac204..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303re/scripts/ld.script b/boards/arm/stm32/nucleo-f303re/scripts/ld.script deleted file mode 100644 index 509bf141fad7e..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303RET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt deleted file mode 100644 index bcc8d69e66ca3..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt +++ /dev/null @@ -1,69 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_LCD_SSD1351) - list(APPEND SRCS stm32_ssd1351.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f303re/src/Make.defs b/boards/arm/stm32/nucleo-f303re/src/Make.defs deleted file mode 100644 index 08749d74cd058..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/Make.defs +++ /dev/null @@ -1,71 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_LCD_SSD1351),y) -CSRCS += stm32_ssd1351.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c deleted file mode 100644 index 7f9f78d1d8e21..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c +++ /dev/null @@ -1,374 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && \ - (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ - defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ - (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) -# error "will not work with this combination of ADCs" -#endif - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV2_PORT) -# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" -# else -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -# endif -#endif - -#if defined(CONFIG_STM32_ADC4) -# if defined(DEV2_PORT) -# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" -# else -# if defined(DEV1_PORT) -# define DEV2_PORT 4 -# else -# define DEV1_PORT 4 -# endif -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 4 -#define ADC2_NCHANNELS 3 -#define ADC3_NCHANNELS 3 -#define ADC4_NCHANNELS 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[4] = -{ - 1, - 2, - 6, - 7, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[4] = -{ - GPIO_ADC1_IN1_0, - GPIO_ADC1_IN2_0, - GPIO_ADC1_IN6_0, - GPIO_ADC1_IN7_0 -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 3, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, - GPIO_ADC2_IN3_0, - GPIO_ADC2_IN4_0 -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 5, - 12 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN1_0, - GPIO_ADC3_IN5_0, - GPIO_ADC3_IN12_0 -}; - -#elif DEV1_PORT == 4 - -#define DEV1_NCHANNELS ADC4_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[1] = -{ - 3 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[1] = -{ - GPIO_ADC4_IN3_0 -}; - -#endif - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 1 - -#define DEV2_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist2[4] = -{ - 1, - 2, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[4] = -{ - GPIO_ADC1_IN1_0, - GPIO_ADC1_IN2_0, - GPIO_ADC1_IN6_0, - GPIO_ADC1_IN7_0 -}; - -#elif DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 3, - 4 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, - GPIO_ADC2_IN3_0, - GPIO_ADC2_IN4_0 -}; - -#elif DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 5, - 12 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN1_0, - GPIO_ADC3_IN5_0, - GPIO_ADC3_IN12_0 -}; - -#elif DEV2_PORT == 4 - -#define DEV2_NCHANNELS ADC4_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[1] = -{ - 3 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[1] = -{ - GPIO_ADC4_IN3_0 -}; - -#endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || - * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4) */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c deleted file mode 100644 index 55c7df56a711d..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c deleted file mode 100644 index 6231f8b5f59c0..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f303re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_SPI - if (stm32_spidev_initialize != NULL) - { - stm32_spidev_initialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_intitialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - - /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. - * Il faut le faire ici - */ - -#ifdef HAVE_DAC - ret = board_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c deleted file mode 100644 index f93ac3a5f9bc2..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c b/boards/arm/stm32/nucleo-f303re/src/stm32_can.c deleted file mode 100644 index e7b25cf16ae33..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#ifdef CONFIG_STM32_CAN1 - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c deleted file mode 100644 index 5d4544d1e8cbf..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_pwm.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEO_F303RE_PWMTIMER); - if (pwm == NULL) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c deleted file mode 100644 index 559b5020f0383..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_SPI - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ - stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SSD1351 D/C n bit to select data (true) or command - * (false). This function must be provided by platform-specific logic. - * This is an implementation of the cmddata method of the SPI interface - * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * spi - SPI device that controls the bus the device that requires the - * CMD/DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for - * example, one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_SSD1351 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_DC, !cmd); - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_SPI */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c b/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c deleted file mode 100644 index b0f3a56d028d2..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-f303re.h" - -#ifdef CONFIG_LCD_SSD1351 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The pin configurations here require that SPI1 is selected */ - -#ifndef CONFIG_STM32_SPI1 -# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" -#endif - -#ifndef CONFIG_SSD1351_SPI4WIRE -# error "The configuration requires the SPI 4-wire interface" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_graphics_setup - * - * Description: - * Called by NX initialization logic to configure the OLED. - * - ****************************************************************************/ - -struct lcd_dev_s *board_graphics_setup(unsigned int devno) -{ - struct spi_dev_s *spi; - struct lcd_dev_s *dev; - - /* Configure the OLED GPIOs. This initial configuration is RESET low, - * putting the OLED into reset state. - */ - - stm32_configgpio(GPIO_OLED_RESET); - - /* Wait a bit then release the OLED from the reset state */ - - up_mdelay(20); - stm32_gpiowrite(GPIO_OLED_RESET, true); - - /* Get the SPI1 port interface */ - - spi = stm32_spibus_initialize(1); - if (spi == NULL) - { - lcderr("ERROR: Failed to initialize SPI port 1\n"); - } - else - { - /* Bind the SPI port to the OLED */ - - dev = ssd1351_initialize(spi, devno); - if (dev == NULL) - { - lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); - } - else - { - lcdinfo("Bound SPI port 1 to OLED %d\n", devno); - - /* And turn the OLED on */ - - dev->setpower(dev, LCD_FULL_ON); - return dev; - } - } - - return NULL; -} - -#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c b/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c deleted file mode 100644 index 221f721b5affa..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "nucleo-f303re.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c b/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c deleted file mode 100644 index af1a488fa10cf..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c deleted file mode 100644 index 121230d908eff..0000000000000 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-f303re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt deleted file mode 100644 index 0892584b29463..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig deleted file mode 100644 index f2d6468fb91a3..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_ADC3_RESOLUTION=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig deleted file mode 100644 index 4e7c31dd5960a..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig deleted file mode 100644 index 2246e4f79306a..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f303ze" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 -CONFIG_EXAMPLES_NXLINES_BPP=1 -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff -CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=255 -CONFIG_LCD_SH1106_OLED_132=y -CONFIG_LCD_SSD1306_I2C=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f303ze/include/board.h b/boards/arm/stm32/nucleo-f303ze/include/board.h deleted file mode 100644 index b604725820c16..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/include/board.h +++ /dev/null @@ -1,207 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ ---- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Button definitions *******************************************************/ - -/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is - * connected to GPIO PC13. A high value will be sensed when the button is - * depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART3 (Nucleo Virtual Console) */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_50MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_50MHz) /* PD8 */ - -/* I2C1 Use Nucleo I2C1 pins */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) /* PB8 - D15 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) /* PB9 - D14 */ - -/* I2C2 Use Nucleo I2C2 pins */ - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2|GPIO_SPEED_50MHz) /* PF1 - D69 */ -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) /* PF0 - D68 */ -#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2|GPIO_SPEED_50MHz) /* PF2 - D70 */ - -/* DMA **********************************************************************/ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 -#define ADC3_DMA_CHAN DMACHAN_ADC3 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs deleted file mode 100644 index fba0285e3737c..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303ze/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script b/boards/arm/stm32/nucleo-f303ze/scripts/ld.script deleted file mode 100644 index c43ec67e0d904..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303ZET6 has 512Kb of FLASH beginning at address 0x0800:0000, - * 64Kb of SRAM and 16kb CCM RAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt deleted file mode 100644 index 5c6e0c74cb3cf..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f303ze/src/Make.defs b/boards/arm/stm32/nucleo-f303ze/src/Make.defs deleted file mode 100644 index 099d67193b38b..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303ze/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_LCD_SSD1306),y) -CSRCS += stm32_lcd.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c deleted file mode 100644 index a5f559fb43276..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC3_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 4, - 6, - 9 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN4_0, /* PA3/A0 */ - GPIO_ADC1_IN6_0, /* PC0/A1 */ - GPIO_ADC1_IN9_0, /* PC3/A2 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c deleted file mode 100644 index b990cdd6219b8..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c deleted file mode 100644 index f2c54d36d4e31..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_start.h" -#include "nucleo-f303ze.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c deleted file mode 100644 index 697969eec6678..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "nucleo-f303ze.h" - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - - UNUSED(ret); - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - return OK; -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c deleted file mode 100644 index 9e82309922da4..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns a - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c deleted file mode 100644 index cb6b3ffe895c4..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f303ze.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_I2C_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c deleted file mode 100644 index f2f7522ee6900..0000000000000 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f303ze.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. NOTE: since - * there is only a single LED on-board, this is function is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt deleted file mode 100644 index ef3be834441c3..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig deleted file mode 100644 index 061b531d0df21..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ /dev/null @@ -1,95 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig deleted file mode 100644 index 91edb447bbc3e..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_HIGHPRI=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC1_INJECTED_CHAN=1 -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG1=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig deleted file mode 100644 index a93dc875a7856..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig deleted file mode 100644 index da76b4a0a0bea..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="spwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_SPWM=y -CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3 -CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_INTERRUPTS=y -CONFIG_STM32_HRTIM_MASTER=y -CONFIG_STM32_HRTIM_MASTER_IRQ=y -CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_HRTIM_TIMA_PWM=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMB=y -CONFIG_STM32_HRTIM_TIMB_PWM=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMD=y -CONFIG_STM32_HRTIM_TIMD_PWM=y -CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y -CONFIG_STM32_HRTIM_TIME=y -CONFIG_STM32_HRTIM_TIME_PWM=y -CONFIG_STM32_HRTIM_TIME_PWM_CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig deleted file mode 100644 index 268872d84fffb..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f334r8" -CONFIG_ARCH_BOARD_NUCLEO_F334R8=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334R8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="spwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NUCLEOF334R8_SPWM=y -CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CH2OUT=y -CONFIG_STM32_TIM1_CH3OUT=y -CONFIG_STM32_TIM1_CH4OUT=y -CONFIG_STM32_TIM1_CHANNEL1=y -CONFIG_STM32_TIM1_CHANNEL2=y -CONFIG_STM32_TIM1_CHANNEL3=y -CONFIG_STM32_TIM1_CHANNEL4=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM6=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f334r8/include/board.h b/boards/arm/stm32/nucleo-f334r8/include/board.h deleted file mode 100644 index e437be709a153..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/include/board.h +++ /dev/null @@ -1,344 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32F334R8. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo F334R8. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo F334R8 supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32F334R8. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F334R8. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_50MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_50MHz) /* PA2 */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ - -/* COMP */ - -/* OPAMP */ - -#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5 -#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14 - -/* Configuration specific to high priority interrupts example: - * - HRTIM Timer A trigger for ADC if DMA transfer and HRTIM - * - TIM1 CC1 trigger for ADC if DMA transfer and TIM1 PWM - * - ADC DMA transfer on DMA1_CH1 - */ - -#ifdef CONFIG_NUCLEOF334R8_HIGHPRI - -#if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_ADC1_DMA) - -/* HRTIM - ADC trigger */ - -#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 -#define HRTIM_TIMA_MODE HRTIM_MODE_CONT -#define HRTIM_TIMA_UPDATE 0 -#define HRTIM_TIMA_RESET 0 - -#define HRTIM_ADC_TRG1 HRTIM_ADCTRG13_APER - -#endif /* CONFIG_STM32_HRTIM1 && CONFIG_STM32_ADC1_DMA*/ -#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ - -#ifdef CONFIG_NUCLEOF334R8_SPWM -# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1 - -/* TIM1 PWM configuration ***************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 */ -# define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* TIM1 CH1N - PA7 */ - /* TIM1 CH2 - PA9 */ -# define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* TIM1 CH2N - PB0 */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 */ -# define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_50MHz) /* TIM1 CH3N - PB1 */ -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH4 - PA11 */ -# endif - -# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1 - -/* HRTIM configuration ******************************************************/ - -# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_MASTER_MODE HRTIM_MODE_CONT - -# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMA_RESET 0 - -# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMB_RESET 0 - -# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMC_RESET 0 - -# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIMD_RESET 0 - -# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128 -# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) -# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER -# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1 -# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU -# define HRTIM_TIME_RESET 0 - -# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1 -# endif - -#endif /* CONFIG_NUCLEOF334R8_SPWM */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ - -/* TIM1 CH2 alias (used by spwm2 config) */ - -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0|GPIO_SPEED_50MHz) - -/* HRTIM1 */ - -#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 -#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 -#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 -#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 -#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 -#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs deleted file mode 100644 index 24b7d458136a4..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script b/boards/arm/stm32/nucleo-f334r8/scripts/ld.script deleted file mode 100644 index 5f4e9d8ae7180..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F334R8 has 64Kb of FLASH beginning at address 0x0800:0000, - * 12Kb of SRAM and 4Kb of CCM SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt deleted file mode 100644 index 30f5bccef47a4..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt +++ /dev/null @@ -1,59 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_NUCLEOF334R8_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_NUCLEOF334R8_SPWM) - list(APPEND SRCS stm32_spwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f334r8/src/Make.defs b/boards/arm/stm32/nucleo-f334r8/src/Make.defs deleted file mode 100644 index 97dbc7a0f51fd..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/Make.defs +++ /dev/null @@ -1,61 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_COMP),y) -CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_OPAMP),y) -CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_NUCLEOF334R8_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_NUCLEOF334R8_SPWM),y) -CSRCS += stm32_spwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c deleted file mode 100644 index a369fe2f4fa1e..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c +++ /dev/null @@ -1,242 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 11 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c deleted file mode 100644 index e2088b7ea6f88..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-f334r8.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c deleted file mode 100644 index 6387f93c8a38c..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f334r8.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c deleted file mode 100644 index 1175e6b17ba3a..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP6)) - -#ifdef CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP6 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - comp = stm32_compinitialize(6); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 6); - return -ENODEV; - } -#endif - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 - * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c deleted file mode 100644 index 7be598a774724..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include - -#ifdef CONFIG_NUCLEOF334R8_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_HRTIM_TIMA) -# define HIGHPRI_HAVE_HRTIM -# endif -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if defined(HIGHPRI_HAVE_HRTIM) && defined(HIGHPRI_HAVE_TIM1) -# error HRTIM TIM A or TIM1 ! -# elif !defined(HIGHPRI_HAVE_HRTIM) && !defined(HIGHPRI_HAVE_TIM1) -# error "Needs HRTIM TIMA or TIM1 to trigger ADC DMA" -# endif -#endif - -#ifdef HIGHPRI_HAVE_HRTIM -# if !defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || !defined(CONFIG_STM32_HRTIM_ADC) -# error -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) -# error Max 2 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (3) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_HRTIM - struct hrtim_dev_s *hrtim; -#endif -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 1, -#ifdef CONFIG_STM32_ADC1_DMA - 2, - 11, -#endif -#if INJ_NCHANNELS > 0 - 7, -#endif -#if INJ_NCHANNELS > 1 - 6 -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ -#ifdef CONFIG_STM32_ADC1_DMA - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -#endif -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN7_0, /* PC1/A4 */ -#endif -#if INJ_NCHANNELS > 1 - GPIO_ADC1_IN6_0 /* PC0/A5 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc12_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOS) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dmach1_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma1ch1_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; - int i; - - pending = stm32_dma_intget(STM32_DMA1_CHAN1); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(STM32_DMA1_CHAN1, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_HRTIM - struct hrtim_dev_s *hrtim; -#endif -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_HRTIM - /* Configure HRTIM */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - printf("ERROR: Failed to get HRTIM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->hrtim = hrtim; - - /* Set Timer A Period */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xffd0); -#endif /* HIGHPRI_HAVE_HRTIM */ - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC12 ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC12); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA1 CH1 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA1CH1 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA1CH1); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected sequence end interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); -#endif - -#ifdef HIGHPRI_HAVE_HRTIM - /* Enable HRTIM TIMA after ADC configuration */ - - HRTIM_TIM_ENABLE(highpri->hrtim, HRTIM_TIMER_TIMA, true); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c deleted file mode 100644 index 6b493ee1cbd1e..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_hrtim.h" - -#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_hrtim_setup - * - * Description: - * Initialize HRTIM driver - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_hrtim_setup(void) -{ - static bool initialized = false; - struct hrtim_dev_s *hrtim = NULL; - int ret; - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - tmrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Register the HRTIM character driver at /dev/hrtim0 */ - - ret = hrtim_register("/dev/hrtim0", hrtim); - if (ret < 0) - { - tmrerr("ERROR: hrtim_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c b/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c deleted file mode 100644 index cdc526cb42757..0000000000000 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_opamp_setup - * - * Description: - * Initialize OPAMP - * - ****************************************************************************/ - -int stm32_opamp_setup(void) -{ - static bool initialized = false; - struct opamp_dev_s *opamp = NULL; - int ret; - - if (!initialized) - { - /* Get the OPAMP interface */ - -#ifdef CONFIG_STM32_OPAMP2 - opamp = stm32_opampinitialize(2); - if (opamp == NULL) - { - aerr("ERROR: Failed to get OPAMP%d interface\n", 2); - return -ENODEV; - } -#endif - - /* Register the OPAMP character driver at /dev/opamp0 */ - - ret = opamp_register("/dev/opamp0", opamp); - if (ret < 0) - { - aerr("ERROR: opamp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/CMakeLists.txt deleted file mode 100644 index fc3725e660d65..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig deleted file mode 100644 index a1b50fd19ba8e..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f401re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F401RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_FB_MODULEINFO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_DEV=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_UG2864HSWEG01=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_SPI_DRIVER=y -CONFIG_SSD1306_FREQUENCY=1000000 -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig deleted file mode 100644 index e4de249cbd58a..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f401re" -CONFIG_ARCH_BOARD_NUCLEO_F401RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f401re/include/board.h b/boards/arm/stm32/nucleo-f401re/include/board.h deleted file mode 100644 index 48a13db82da87..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/include/board.h +++ /dev/null @@ -1,380 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-F401RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 84000000 Determined by PLL - * configuration - * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 16 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. - * Some possible solutions include: - * - * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 4 = 84,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 336,000,000 / 7 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 84000000ul - -/* AHB clock (HCLK) is SYSCLK (84MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F401RE board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs b/boards/arm/stm32/nucleo-f401re/scripts/Make.defs deleted file mode 100644 index a106e21e6af79..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f401re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld b/boards/arm/stm32/nucleo-f401re/scripts/flash.ld deleted file mode 100644 index 4ad627c8819d8..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F401RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 96Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt deleted file mode 100644 index d1e694f440518..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt +++ /dev/null @@ -1,54 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/nucleo-f401re/src/Make.defs b/boards/arm/stm32/nucleo-f401re/src/Make.defs deleted file mode 100644 index 45725b5052ed6..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/Make.defs +++ /dev/null @@ -1,56 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f401re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c - -ifeq ($(CONFIG_VIDEO_FB),y) -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c -endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c deleted file mode 100644 index 2ad4c4e22e8ca..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_adc.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_ADC_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_ADC_DMA -/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0, GPIO_ADC1_IN0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* Configura ADC input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0 -}; - -#endif /* CONFIG_ADC_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c deleted file mode 100644 index 7752b7a61da43..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c +++ /dev/null @@ -1,490 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f401re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ - - /* Open the ADC driver for reading. */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c deleted file mode 100644 index 6dffbce983e5c..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c deleted file mode 100644 index 66eb41c6066f8..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f401re.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c deleted file mode 100644 index d768f5dc584f6..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#undef HAVE_LEDS -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - struct spi_dev_s *spi; - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - -#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) - board_lcd_initialize(); -#endif - -#ifdef CONFIG_VIDEO_FB - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ -#endif - - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F401RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c deleted file mode 100644 index b0a02f7a879d7..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f401re.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c deleted file mode 100644 index 144f5b50c5802..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f401re.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c b/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c deleted file mode 100644 index 5ed40a07fdebb..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "nucleo-f401re.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c deleted file mode 100644 index 2b7cf5fac7921..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f401re.h" - -#include - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef CONFIG_LCD_SSD1306_SPI - stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ - stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CS, !selected); - } -#endif - -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c deleted file mode 100644 index 0415373cc07eb..0000000000000 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f401re.h" - -#include - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (BOARD_LD2_BIT == (1 << led)) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - /* An output of '1' illuminates the LED */ - - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -#ifdef CONFIG_USERLED_LOWER_READSTATE -/**************************************************************************** - * Name: board_userled_getall - ****************************************************************************/ - -void board_userled_getall(uint32_t *ledset) -{ - /* Clear the LED bits */ - - *ledset = 0; - - /* Get LED state. An output of '1' illuminates the LED. */ - - *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); -} - -#endif /* CONFIG_USERLED_LOWER_READSTATE */ - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt deleted file mode 100644 index 9c873cd876538..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig deleted file mode 100644 index 084541c3257e1..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f410rb" -CONFIG_ARCH_BOARD_NUCLEO_F410RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F410RB=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=32768 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=25 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2017 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FLASH_CONFIG_B=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_CLE=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-f410rb/include/board.h b/boards/arm/stm32/nucleo-f410rb/include/board.h deleted file mode 100644 index 0da6ad80797b0..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/include/board.h +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X3 crystals is not populated. - * Therefore the Nucleo-F410RB will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 100000000 Determined by PLL configuration - * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 2 (STM32_PLLCFG_PLLM) - * PLLN : 50 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency � PLLN, - * 50 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 2) * 50 - * = 400,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 400,000,000 / 4 = 100,000,000 - * RNG Clock - * = PLL_VCO / PLLQ - * = 400,000,000 / 8 = 50,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 100000000ul - -/* AHB clock (HCLK) is SYSCLK (100MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (100MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* Timers driven from APB2 will be PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,9,11 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN -#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F410RB board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs deleted file mode 100644 index af0a457b2633d..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f410rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f410rb.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt deleted file mode 100644 index df15551bccbbe..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt +++ /dev/null @@ -1,41 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f410rb.ld") diff --git a/boards/arm/stm32/nucleo-f410rb/src/Make.defs b/boards/arm/stm32/nucleo-f410rb/src/Make.defs deleted file mode 100644 index abd7559d83199..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f410rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c deleted file mode 100644 index cf679ab14d277..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "nucleo-f410rb.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_STM32_ADC1_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_STM32_ADC1_DMA -/* ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 9, 8 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN9_0, GPIO_ADC1_IN8_0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 9 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN9_0 -}; - -#endif /* CONFIG_STM32_ADC1_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - syslog(LOG_ERR, "stm32_adc_setup configuration: %d\n", ADC1_NCHANNELS); - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c deleted file mode 100644 index 4eaaaf20686ff..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f410rb.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c deleted file mode 100644 index d85baaa2d49d3..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nucleo-f410rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c deleted file mode 100644 index 043d8c543a8f0..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c +++ /dev/null @@ -1,70 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include - -#include "nucleo-f410rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c deleted file mode 100644 index 0797e9f5139f5..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f410rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c deleted file mode 100644 index b007a34d32386..0000000000000 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f410rb.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LD2) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/CMakeLists.txt deleted file mode 100644 index 53fe0025e449b..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig deleted file mode 100644 index a3f262eade067..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f411re" -CONFIG_ARCH_BOARD_NUCLEO_F411RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_CANUTILS_CANLIB=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_MCP2515=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MCP2515_PHASESEG1=3 -CONFIG_MCP2515_PROPSEG=1 -CONFIG_MCP2515_SPI_SCK_FREQUENCY=500000 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig deleted file mode 100644 index 7d747965a4ca8..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f411re" -CONFIG_ARCH_BOARD_NUCLEO_F411RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411RE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f411re/include/board.h b/boards/arm/stm32/nucleo-f411re/include/board.h deleted file mode 100644 index 9b16ece415431..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/include/board.h +++ /dev/null @@ -1,377 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEOF411RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-FF411RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 104000000 Determined by PLL - * configuration - * HCLK(Hz) : 104000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 216 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 9 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=104MHz and we must have - * the USB clock= 48MHz. - * - * PLLQ = 13 PLLP = 6 PLLN=390 PLLM=10 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 10) * 390 - * = 624,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 624,000,000 / 6 = 104,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 624,000,000 / 13 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(10) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(390) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_6 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(13) - -#define STM32_SYSCLK_FREQUENCY 104000000ul - -/* AHB clock (HCLK) is SYSCLK (104MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (104MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F411RE board provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: - * the user button is connected to the I/O PC13 (pin 2) of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs b/boards/arm/stm32/nucleo-f411re/scripts/Make.defs deleted file mode 100644 index 88f77e2be62d9..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f411re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld b/boards/arm/stm32/nucleo-f411re/scripts/flash.ld deleted file mode 100644 index 09718dfc8e320..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt deleted file mode 100644 index 9339106e5ded2..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt +++ /dev/null @@ -1,54 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/nucleo-f411re/src/Make.defs b/boards/arm/stm32/nucleo-f411re/src/Make.defs deleted file mode 100644 index 0bab56576f560..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/Make.defs +++ /dev/null @@ -1,56 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f411re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c - -ifeq ($(CONFIG_VIDEO_FB),y) -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c -endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c deleted file mode 100644 index cde6cfc40ae1c..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_adc.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_ADC_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_ADC_DMA -/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0, GPIO_ADC1_IN0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* Configura ADC input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0 -}; - -#endif /* CONFIG_ADC_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c deleted file mode 100644 index 69dcfc850d040..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c +++ /dev/null @@ -1,490 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f411re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ - - /* Open the ADC driver for reading. */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c deleted file mode 100644 index 24b8a3db27ed7..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c deleted file mode 100644 index 88b543398badf..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f411re.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c deleted file mode 100644 index 04836ee845a0e..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#undef HAVE_LEDS -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - struct spi_dev_s *spi; - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - -#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) - board_lcd_initialize(); -#endif - -#ifdef CONFIG_VIDEO_FB - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ -#endif - - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F411RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c deleted file mode 100644 index 7d064a6b2d5e9..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-f411re.h" - -#include - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c deleted file mode 100644 index 558b20fa145a8..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "nucleo-f411re.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c b/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c deleted file mode 100644 index 2de6483c23635..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "nucleo-f411re.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c deleted file mode 100644 index 9a7d4878355aa..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c +++ /dev/null @@ -1,246 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f411re.h" - -#include - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F411RE - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef CONFIG_LCD_SSD1306_SPI - stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ - stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CS, !selected); - } -#endif - -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306_SPI) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c deleted file mode 100644 index 63434897ac3f3..0000000000000 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f411re.h" - -#include - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (BOARD_LD2_BIT == (1 << led)) - { - stm32_gpiowrite(GPIO_LD2, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - /* An output of '1' illuminates the LED */ - - stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); -} - -#ifdef CONFIG_USERLED_LOWER_READSTATE -/**************************************************************************** - * Name: board_userled_getall - ****************************************************************************/ - -void board_userled_getall(uint32_t *ledset) -{ - /* Clear the LED bits */ - - *ledset = 0; - - /* Get LED state. An output of '1' illuminates the LED. */ - - *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); -} - -#endif /* CONFIG_USERLED_LOWER_READSTATE */ - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - DEBUGASSERT(ret == OK); - UNUSED(ret); -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt deleted file mode 100644 index df7b29ff230fd..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig deleted file mode 100644 index 5eeb2976c6693..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BENCHMARK_COREMARK=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_MKRD=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_OPTLEVEL="-O3" -CONFIG_INIT_ENTRYPOINT="coremark_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig deleted file mode 100644 index 1592d27e09ba6..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_HAVE_CXX=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_TIMER=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig deleted file mode 100644 index 0e148998477e3..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f412zg" -CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F412ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_SIZET_LONG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_HAVE_CXX=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_CHILDSTATUS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=262144 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_TESTING_OSTEST=y -CONFIG_TIMER=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/nucleo-f412zg/include/board.h b/boards/arm/stm32/nucleo-f412zg/include/board.h deleted file mode 100644 index 9414bde3d6331..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/include/board.h +++ /dev/null @@ -1,228 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz Crystal - * LSE - not installed - */ - -#define STM32_BOARD_USEHSE 1 -#define STM32_BOARD_XTAL 8000000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 - -/* Main PLL Configuration */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) -#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) - -#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16) -#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) -#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/ - -#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL -#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB -#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (96MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* Timers driven from APB2 will be PCLK2 since no prescale division */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* Alternate function pin selections ****************************************/ - -/* USART2: - * RXD: PD6 CN9 pin 4 - * TXD: PD5 CN9 pin 6 - */ - -# define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) -# define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) - -/* USART3 (ST-LINK Virtual COM Port): - * RXD: PD9 - * TXD: PD8 - */ - -# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) -# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) - -/* USART6: - * RXD: PG9 CN10 pin 16 - * TXD: PG14 CN10 pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) - -/* I2C1: - * SCL: PB8 CN7 pin2 - * SDA: PB9 CN7 pin4 - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -/* SPI1: - * MISO: PA6 CN7 pin 12 - * MOSI: PA7 CN7 pin 14 - * SCK: PA5 CN7 pin 10 - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* CAN1: - * RX: PD0 CN9 pin 25 - * TX: PD1 CN9 pin 27 - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -/* LEDs - * - * The NUCLEO-F412ZG board has 3 user leds. - * LD1: PB0 GREEN - * LD2: PB7 BLUE - * LD3: PB14 RED - */ - -#define BOARD_NLEDS 3 - -#define GPIO_LD1 \ -(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -#define GPIO_LD2 \ -(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -#define GPIO_LD3 \ -(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ -GPIO_SPEED_50MHz) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning - * ------------------- ----------------------- - * LED_STARTED NuttX has been started - * LED_HEAPALLOCATE Heap has been allocated - * LED_IRQSENABLED Interrupts enabled - * LED_STACKCREATED Idle stack created - * LED_INIRQ In an interrupt - * LED_SIGNAL In a signal handler - * LED_ASSERTION An assertion failed - * LED_PANIC The system has crashed - * LED_IDLE MCU is in sleep mode - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 1 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 3 -#define LED_INIRQ 0 -#define LED_SIGNAL 0 -#define LED_ASSERTION 1 -#define LED_PANIC 1 - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs deleted file mode 100644 index 9cc6754a29403..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f412zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include ${TOPDIR}/.config -include ${TOPDIR}/tools/Config.mk -include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f412zg.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHDEFINES = -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt deleted file mode 100644 index b3cae915b2537..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt +++ /dev/null @@ -1,35 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f412zg.ld") diff --git a/boards/arm/stm32/nucleo-f412zg/src/Make.defs b/boards/arm/stm32/nucleo-f412zg/src/Make.defs deleted file mode 100644 index d437533fd2453..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/Make.defs +++ /dev/null @@ -1,38 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f412zg/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - --include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c deleted file mode 100644 index 554db9c523bb6..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - stm32_configgpio(GPIO_LD1); - stm32_configgpio(GPIO_LD2); - stm32_configgpio(GPIO_LD3); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case 1: - stm32_gpiowrite(GPIO_LD1, true); - break; - case 2: - stm32_gpiowrite(GPIO_LD1, true); - stm32_gpiowrite(GPIO_LD2, true); - break; - case 3: - stm32_gpiowrite(GPIO_LD1, true); - stm32_gpiowrite(GPIO_LD2, true); - stm32_gpiowrite(GPIO_LD3, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case 1: - stm32_gpiowrite(GPIO_LD1, false); - break; - case 2: - stm32_gpiowrite(GPIO_LD1, false); - stm32_gpiowrite(GPIO_LD2, false); - break; - case 3: - stm32_gpiowrite(GPIO_LD1, false); - stm32_gpiowrite(GPIO_LD2, false); - stm32_gpiowrite(GPIO_LD3, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c deleted file mode 100644 index f55d0686040e3..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f412zg.h" -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c deleted file mode 100644 index 5b14c9c8f271c..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c deleted file mode 100644 index d3eef5fcdc6c3..0000000000000 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c +++ /dev/null @@ -1,352 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Brian Webb - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "up_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "nucleo-f412zg.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO -# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F411 Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required. - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs. - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor - * for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, - CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface. - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge - * pump or, if 5 V are available on the application board, a basic power - * switch, must be added externally to drive the 5 V VBUS line. The - * external charge pump can be driven by any GPIO output. When the - * application decides to power on VBUS using the chosen GPIO, it must - * also set the port power bit in the host port control and status - * register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, and - * the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt deleted file mode 100644 index 5d868f0710bba..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig deleted file mode 100644 index 540dba0fb4c97..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8742A=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_IGMP=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_ROUTE=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig deleted file mode 100644 index 9f4b9ecb6cdae..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig deleted file mode 100644 index 725c9eb2f4d84..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f429zi" -CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_NOTE=y -CONFIG_DRIVERS_NOTECTL=y -CONFIG_ETH0_PHY_LAN8742A=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_IGMP=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_ROUTE=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_DUMP=y -CONFIG_SCHED_INSTRUMENTATION_FILTER=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_STACK_USAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TRACE=y -CONFIG_SYSTEM_TRACE_STACKSIZE=8192 -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f429zi/include/board.h b/boards/arm/stm32/nucleo-f429zi/include/board.h deleted file mode 100644 index 04829a544e878..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/include/board.h +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Do not include STM32 F4 header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F4 Discovery board features a single 8MHz crystal. Space is - * provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 180000000 Determined by PLL config - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for highspeed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDMMC DMA is on DMA2 - * - * SDMMC1 DMA - * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 - * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 - * - * SDMMC2 DMA - * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 - * DMAMAP_SDMMC3_2 = Channel 11, Stream 5 - */ - -#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 -#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 - -/* FLASH wait states - * - * --------- ---------- ----------- - * VDD MAX SYSCLK WAIT STATES - * --------- ---------- ----------- - * 1.7-2.1 V 180 MHz 8 - * 2.1-2.4 V 216 MHz 9 - * 2.4-2.7 V 216 MHz 8 - * 2.7-3.6 V 216 MHz 7 - * --------- ---------- ----------- - */ - -#define BOARD_FLASH_WAITSTATES 7 - -/* LED definitions **********************************************************/ - -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, - * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. - * The following definitions assume the default Solder Bridges are installed. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_NLEDS 3 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_BLUE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) - -/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * - * SYMBOL Meaning LED state - * Red Green Blue - * ---------------------- -------------------------- ------ ------ --- - */ - -#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ -#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ -#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ -#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ -#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ - -/* Thus if the Green LED is statically on, NuttX has successfully booted and - * is, apparently, running normally. If the Red LED is flashing at - * approximately 2Hz, then a fatal error has been detected and the system - * has halted. - */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: Pushbutton B1, labeled "User", - * is connected to GPIO PI11. - * A high value will be sensed when the button is depressed. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_1|GPIO_SPEED_50MHz) - -#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_ARDUINO) - -/* USART6: - * - * These configurations assume that you are using a standard Arduio RS-232 - * shield with the serial interface with RX on pin D0 and TX on pin D1: - * - * -------- --------------- - * STM32F4 - * ARDUIONO FUNCTION GPIO - * -- ----- --------- ----- - * DO RX USART6_RX PG9 - * D1 TX USART6_TX PG14 - * -- ----- --------- ----- - */ - - # define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) - # define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) -#endif - -/* USART3: - * Use USART3 and the USB virtual COM port - */ - -#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL) - # define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) - # define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) -#endif - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 -#define ADC2_DMA_CHAN DMAMAP_ADC2_1 -#define ADC3_DMA_CHAN DMAMAP_ADC3_1 - -/* SPI - * - * - * PA6 SPI1_MISO CN12-13 - * PA7 SPI1_MOSI CN12-15 - * PA5 SPI1_SCK CN12-11 - * - * PB14 SPI2_MISO CN12-28 - * PB15 SPI2_MOSI CN12-26 - * PB13 SPI2_SCK CN12-30 - * - * PB4 SPI3_MISO CN12-27 - * PB5 SPI3_MOSI CN12-29 - * PB3 SPI3_SCK CN12-31 - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz) - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -/* I2C - * - * - * PB8 I2C1_SCL CN12-3 - * PB9 I2C1_SDA CN12-5 - - * PB10 I2C2_SCL CN11-51 - * PB11 I2C2_SDA CN12-18 - * - * PA8 I2C3_SCL CN12-23 - * PC9 I2C3_SDA CN12-1 - * - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) - -/* The STM32 F4 connects to a SMSC LAN8742A PHY using these pins: - * - * STM32 F4 BOARD LAN8742A - * GPIO SIGNAL PIN NAME - * -------- ------------ ------------- - * PG11 RMII_TX_EN TXEN - * PG13 RMII_TXD0 TXD0 - * PB13 RMII_TXD1 TXD1 - * PC4 RMII_RXD0 RXD0/MODE0 - * PC5 RMII_RXD1 RXD1/MODE1 - * PG2 RMII_RXER RXER/PHYAD0 -- Not used - * PA7 RMII_CRS_DV CRS_DV/MODE2 - * PC1 RMII_MDC MDC - * PA2 RMII_MDIO MDIO - * N/A NRST nRST - * PA1 RMII_REF_CLK nINT/REFCLK0 - * N/A OSC_25M XTAL1/CLKIN - * - * The PHY address is either 0 or 1, depending on the state of PG2 on reset. - * PG2 is not controlled but appears to result in a PHY address of 0. - */ - -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs deleted file mode 100644 index 70114e47e2117..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f429zi/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld b/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld deleted file mode 100644 index 43a2313798fd9..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script b/boards/arm/stm32/nucleo-f429zi/scripts/ld.script deleted file mode 100644 index 7c53a58843444..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld b/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld deleted file mode 100644 index b1be62434027f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of SRAM beginning at address 0x2002:0000 - * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld b/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld deleted file mode 100644 index 03cd4598f1b61..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt deleted file mode 100644 index cfcef00556c11..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt +++ /dev/null @@ -1,73 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-f429zi/src/Make.defs b/boards/arm/stm32/nucleo-f429zi/src/Make.defs deleted file mode 100644 index 2824447d2d6c8..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f429zi/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c deleted file mode 100644 index 25efe68db8b1c..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c +++ /dev/null @@ -1,169 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "nucleo-144.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32F4_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32F4_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32F4_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = - { - 3 - }; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, - * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, - * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = - { - GPIO_ADC1_IN3 - }; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - if (g_pinlist[i] != 0) - { - stm32_configgpio(g_pinlist[i]); - } - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c deleted file mode 100644 index 9dedddc80a92a..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Indexed by BOARD_LED_ */ - -static const uint32_t g_ledmap[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -static bool g_initialized; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static void phy_set_led(int led, bool state) -{ - /* Active High */ - - stm32_gpiowrite(g_ledmap[led], state); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure the LD1 GPIO for output. Initial state is OFF */ - - for (i = 0; i < nitems(g_ledmap); i++) - { - stm32_configgpio(g_ledmap[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - default: - break; - - case LED_HEAPALLOCATE: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_IRQSENABLED: - phy_set_led(BOARD_LED_BLUE, false); - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_STACKCREATED: - phy_set_led(BOARD_LED_GREEN, true); - phy_set_led(BOARD_LED_BLUE, true); - g_initialized = true; - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, true); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, true); - phy_set_led(BOARD_LED_BLUE, true); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, true); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - default: - break; - - case LED_SIGNAL: - phy_set_led(BOARD_LED_GREEN, false); - break; - - case LED_INIRQ: - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_ASSERTION: - phy_set_led(BOARD_LED_RED, false); - phy_set_led(BOARD_LED_BLUE, false); - break; - - case LED_PANIC: - phy_set_led(BOARD_LED_RED, false); - break; - - case LED_IDLE : /* IDLE */ - phy_set_led(BOARD_LED_RED, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c deleted file mode 100644 index f6131a8308b42..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "nucleo-144.h" - -#ifdef CONFIG_STM32_ROMFS -#include "stm32_romfs.h" -#endif - -#ifdef CONFIG_SENSORS_AMG88XX -#include "stm32_amg88xx.h" -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -# include "stm32_i2c.h" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization - * after all memory has been configured and mapped but - * before any devices have been initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) - stm32_usbinitialize(); -#endif - -#if defined(CONFIG_SPI) - /* Configure SPI chip selects */ - - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and - * just before the initial application is started. This additional - * initialization phase may be used, for example, to initialize - * board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - /* Mount the romfs partition */ - - ret = stm32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return; - } -#endif - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_BBSRAM - /* Initialize battery-backed RAM */ - - stm32_bbsram_int(); -#endif - -#if defined(CONFIG_FAT_DMAMEMORY) - if (stm32_dma_alloc_init() < 0) - { - syslog(LOG_ERR, "DMA alloc FAILED"); - } -#endif - -#if defined(CONFIG_NUCLEO_SPI_TEST) - /* Create SPI interfaces */ - - ret = stm32_spidev_bus_test(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", - ret); - return; - } -#endif - -#if defined(CONFIG_MMCSD) - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); - return; - } -#endif - -#if defined(CONFIG_PWM) - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2c_register(1); -#endif - -#ifdef CONFIG_SENSORS_AMG88XX - board_amg88xx_initialize(1); -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c deleted file mode 100644 index 656f3e42fc7f8..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current - * state of all buttons or board_button_irq() may be called to register - * button interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() - * may be called to collect the state of all buttons. board_buttons() - * returns an 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each - * bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value - * is a button enumeration value that uniquely identifies a button - * resource. See the BUTTON_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, - true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c deleted file mode 100644 index b1de5bf8c1663..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c +++ /dev/null @@ -1,323 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int gpin_read(struct gpio_dev_s *dev, bool *value); -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} - -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} - -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c deleted file mode 100644 index 53f1ec4ebd7d7..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c +++ /dev/null @@ -1,149 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-144.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define HAVE_PWM 1 -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - -#if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32_pwminitialize(1); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32_pwminitialize(2); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) - pwm = stm32_pwminitialize(3); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) - pwm = stm32_pwminitialize(4); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm3", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - -#endif - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c deleted file mode 100644 index 80a5399c8cd0f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h deleted file mode 100644 index bd2b62c985499..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c deleted file mode 100644 index ac86209be361f..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c deleted file mode 100644 index 48a4f79442036..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c +++ /dev/null @@ -1,163 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "nucleo-144.h" -#include "stm32_gpio.h" -#include "stm32_sdmmc.h" - -#ifdef CONFIG_MMCSD - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(GPIO_SDMMC1_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDMMC1_NCD); - if (g_sdio_dev && present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDMMC1_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver - * First, get an instance of the SDIO interface - */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c deleted file mode 100644 index 70e933f51ca08..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c +++ /dev/null @@ -1,496 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-144.h" - -#if defined(CONFIG_SPI) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_NUCLEO_SPI1_TEST) -# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) -# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_SPI2_TEST) -# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) -# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" -# endif -#endif - -#if defined(CONFIG_NUCLEO_SPI3_TEST) -# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) -# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 -# else -# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_STM32_SPI1) -static const uint32_t g_spi1gpio[] = -{ -# if defined(GPIO_SPI1_CS0) - GPIO_SPI1_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS1) - GPIO_SPI1_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS2) - GPIO_SPI1_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI1_CS3) - GPIO_SPI1_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_STM32_SPI2) -static const uint32_t g_spi2gpio[] = -{ -# if defined(GPIO_SPI2_CS0) - GPIO_SPI2_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS1) - GPIO_SPI2_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS2) - GPIO_SPI2_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI2_CS3) - GPIO_SPI2_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_STM32_SPI3) -static const uint32_t g_spi3gpio[] = -{ -# if defined(GPIO_SPI3_CS0) - GPIO_SPI3_CS0, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS1) - GPIO_SPI3_CS1, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS2) - GPIO_SPI3_CS2, -# else - 0, -# endif -# if defined(GPIO_SPI3_CS3) - GPIO_SPI3_CS3 -# else - 0 -# endif -}; -#endif - -#if defined(CONFIG_NUCLEO_SPI_TEST) -# if defined(CONFIG_STM32_SPI1) -struct spi_dev_s *spi1; -# endif -# if defined(CONFIG_STM32_SPI2) -struct spi_dev_s *spi2; -# endif -# if defined(CONFIG_STM32_SPI3) -struct spi_dev_s *spi3; -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* Configure SPI CS GPIO for output */ - -#if defined(CONFIG_STM32_SPI1) - for (int i = 0; i < nitems(g_spi1gpio); i++) - { - if (g_spi1gpio[i] != 0) - { - stm32_configgpio(g_spi1gpio[i]); - } - } -#endif - -#if defined(CONFIG_STM32_SPI2) - for (int i = 0; i < nitems(g_spi2gpio); i++) - { - if (g_spi2gpio[i] != 0) - { - stm32_configgpio(g_spi2gpio[i]); - } - } -#endif - -#if defined(CONFIG_STM32_SPI3) - for (int i = 0; i < nitems(g_spi3gpio); i++) - { - if (g_spi3gpio[i] != 0) - { - stm32_configgpio(g_spi3gpio[i]); - } - } -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status - * - * Description: - * The external functions, stm32_spi1/2/3/4/5/6select and - * stm32_spi1/2/3/4/5/6status must be provided by board-specific logic. - * They are implementations of the select and status methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common - * STM32 logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status() - * functions in your board-specific logic. These functions will - * perform chip selection and status operations using GPIOs in - * the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be - * used to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI - * driver to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi1gpio[index] != 0) - { - stm32_gpiowrite(g_spi1gpio[index], !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi2gpio[index] != 0) - { - stm32_gpiowrite(g_spi2gpio[index], !selected); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - uint32_t index = SPIDEVID_INDEX(devid); - - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (g_spi3gpio[index] != 0) - { - stm32_gpiowrite(g_spi3gpio[index], !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI6 -void stm32_spi6select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5/6cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI6 -int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#endif /* CONFIG_SPI_CMDDATA */ - -#if defined(CONFIG_NUCLEO_SPI_TEST) -int stm32_spidev_bus_test(void) -{ - /* Configure and test SPI */ - - uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE; - -#if defined(CONFIG_NUCLEO_SPI1_TEST) - spi1 = stm32_spibus_initialize(1); - - if (!spi1) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ - - SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); - SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); - SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_SPI2_TEST) - spi2 = stm32_spibus_initialize(2); - - if (!spi2) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ - - SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); - SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); - SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - -#if defined(CONFIG_NUCLEO_SPI3_TEST) - spi3 = stm32_spibus_initialize(3); - - if (!spi3) - { - syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ - - SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); - SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); - SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); -#endif - - return OK; -} -#endif /* NUCLEO_SPI_TEST */ -#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c deleted file mode 100644 index 7ad104a61f072..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c +++ /dev/null @@ -1,322 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_otg.h" -#include "nucleo-144.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_NUCLEO144_USBHOST_PRIO -# define CONFIG_NUCLEO144_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE -# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization - * to setup USB-related GPIO pins for the nucleo-144 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the - * USB host functionality. This function will start a thread - * that will monitor for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function - * must be provided be each platform that implements the - * STM32 OTG FS host interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, - * a charge pump or, if 5 V are available on the application board, - * a basic power switch, must be added externally to drive the 5 V - * VBUS line. The external charge pump can be driven by any GPIO - * output. When the application decides to power on VBUS using - * the chosen GPIO, it must also set the port power bit in the host port - * control and status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - /* Set the Power Switch by driving the active low enable pin */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an - * overcurrent condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno - * value is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the - * USBDEV driver is used. This function is called whenever the - * USB enters or leaves suspend mode. This is an opportunity - * for the board logic to shutdown clocks, power, etc. while the - * USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c deleted file mode 100644 index 80d0f0247fc38..0000000000000 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include -#include - -#include "stm32_gpio.h" -#include "nucleo-144.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration and is indexed by - * BOARD_LED_ - */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_GREEN, - GPIO_LED_BLUE, - GPIO_LED_RED, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the - * board_userled_initialize() is available to initialize the LED from user - * application logic. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is - * available to control the LED from user application logic. - * - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < nitems(g_ledcfg)) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board - * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() - * is available to control the LED from user application logic. - * NOTE: since there is only a single LED on-board, this is function - * is not very useful. - * - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-3 GPIOs for output */ - - for (i = 0; i < nitems(g_ledcfg); i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/CMakeLists.txt deleted file mode 100644 index 5b0efd703eb8b..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig deleted file mode 100644 index 44cf45de768df..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=2 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1 -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig deleted file mode 100644 index 03a39c1bc977e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=100 -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN2=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig deleted file mode 100644 index 6fbda28d15b89..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=16 -CONFIG_IOB_NBUFFERS=1024 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_CAN_EXTID=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=176 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_SOCKET=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig deleted file mode 100644 index 4e6f30b3248ab..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DAC=y -CONFIG_EXAMPLES_DAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig deleted file mode 100644 index 196dd1384db81..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig deleted file mode 100644 index 453e2c87c7d6f..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM08M1=y -CONFIG_BOARD_STM32_IHM08M1_POT=y -CONFIG_BOARD_STM32_IHM08M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH1NPOL=1 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH2NPOL=1 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_CH3NPOL=1 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig deleted file mode 100644 index daf78d0af9a1e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM08M1=y -CONFIG_BOARD_STM32_IHM08M1_POT=y -CONFIG_BOARD_STM32_IHM08M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH1NPOL=1 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH2NPOL=1 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_CH3NPOL=1 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig deleted file mode 100644 index e553a334ca160..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PULSECOUNT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM8=y -CONFIG_STM32_TIM8_PULSECOUNT=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig deleted file mode 100644 index 2863a56217ddc..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_ILI9225=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig deleted file mode 100644 index 4a868074d9ea4..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig deleted file mode 100644 index b55efe9b8c152..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm2" -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CRC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig deleted file mode 100644 index 1b02b7f1f6ce1..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQPRIO=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NUCLEO_F446RE_QETIMER=2 -CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=16386 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig deleted file mode 100644 index 4acf305216efc..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DRIVERS_NOTERAM is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-f446re" -CONFIG_ARCH_BOARD_NUCLEO_F446RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F446R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_NOTE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y -CONFIG_SCHED_WAITPID=y -CONFIG_SEGGER_SYSVIEW=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-f446re/include/board.h b/boards/arm/stm32/nucleo-f446re/include/board.h deleted file mode 100644 index 3e4b1ed17570c..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/include/board.h +++ /dev/null @@ -1,444 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3). - * However, as shipped, the X2 and X3 crystals are not populated. - * Therefore the Nucleo-FF446RE will need to run off the 16MHz HSI clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 180000000 Determined by PLL config - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 216 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 9 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 4 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4 - * so we can select a divider of 4 and a multiplier of 45 - * However multiplier must be between 50 and 432 - * so we double again to choose a multiplier of 90, and a divider of 8 - * VCO output frequency must be in range 100...432 MHz - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz) - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - - * PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 4) * 90 - * = 360 MHz - * SYSCLK = PLL_VCO / PLLP - * = 360,000,000 / 2 = 180,000,000 - * USB OTG FS and SDIO Clock - * = TODO 7.5 is not possible - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15) - -#define STM32_SYSCLK_FREQUENCY 180000000ul - -/* AHB clock (HCLK) is SYSCLK (104MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (104MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - * - * REVISIT - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - * - * REVISIT - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - * - * REVISIT - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* ADC 1 */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if !defined(CONFIG_BOARD_STM32_IHM08M1) -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ - GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The Nucleo F446RE and F411RE boards provide a single user LED, LD2. LD2 - * is the green LED connected to Arduino signal D13 corresponding to MCU I/O - * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. - * - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD2 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD2_BIT (1 << BOARD_LD2) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PC13 (pin 2) of - * the STM32 microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* TIM2 input ***************************************************************/ - -#ifndef CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP -# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA8 */ -# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB0 */ -#else -# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ -#endif - -/* TIM3 configuration *******************************************************/ - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) - -/* TIM8 configuration *******************************************************/ - -#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) /* PC6 */ - -#ifdef CONFIG_BOARD_STM32_IHM08M1 - -/* Configuration specific to the X-NUCLEO-IHM08M1 expansion board with - * the L6398 gate drivers. - */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1 /* TIM1 CH1N - PA7 - U low */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1 /* TIM1 CH2N - PB0 - V low */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_1 /* TIM1 CH3N - PB1 - W low */ -#define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* Board LED */ - -# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -/* Debug pin */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5) - -#endif /* CONFIG_BOARD_STM32_IHM08M1 */ - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32/nucleo-f446re/scripts/Make.defs deleted file mode 100644 index 3ce0409127a70..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f446re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f446re.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt deleted file mode 100644 index f9d569a51e955..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_LCD_ILI9225) - list(APPEND SRCS stm32_ili9225.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - if(CONFIG_INPUT_AJOYSTICK) - list(APPEND SRCS stm32_ajoystick.c) - endif() - endif() -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_BOARD_STM32_IHM08M1) - list(APPEND SRCS stm32_foc_ihm08m1.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32/nucleo-f446re/src/Make.defs b/boards/arm/stm32/nucleo-f446re/src/Make.defs deleted file mode 100644 index 968930b97673e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/Make.defs +++ /dev/null @@ -1,81 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f446re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_LCD_ILI9225),y) -CSRCS += stm32_ili9225.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -ifeq ($(CONFIG_INPUT_AJOYSTICK),y) -CSRCS += stm32_ajoystick.c -endif -endif -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) -CSRCS += stm32_foc_ihm08m1.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c deleted file mode 100644 index 5ae9b9dc8efac..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#ifdef CONFIG_STM32_ADC1_DMA -# define ADC1_NCHANNELS 2 -#else -# define ADC1_NCHANNELS 1 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -#ifdef CONFIG_STM32_ADC1_DMA -/* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 1 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0_0, - GPIO_ADC1_IN1_0 -}; - -#else -/* Without DMA, only a single channel can be supported */ - -/* The Itead analog joystick gets input on ADC_IN0 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN0_0 -}; - -#endif /* CONFIG_STM32_ADC1_DMA */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c deleted file mode 100644 index 8e78f8d1adb99..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c +++ /dev/null @@ -1,491 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_adc.h" -#include "hardware/stm32_adc.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Check for pre-requisites and pin conflicts */ - -#ifdef CONFIG_INPUT_AJOYSTICK -# if !defined(CONFIG_ADC) -# error CONFIG_ADC is required for the Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32_ADC1) -# error CONFIG_STM32_ADC1 is required for Itead joystick -# undef CONFIG_INPUT_AJOYSTICK -# endif -#endif /* CONFIG_INPUT_AJOYSTICK */ - -#ifdef CONFIG_INPUT_AJOYSTICK - -/* A no-ADC, buttons only version can be built for testing */ - -#undef NO_JOYSTICK_ADC - -/* Maximum number of ADC channels */ - -#define MAX_ADC_CHANNELS 8 - -/* Dual channel ADC support requires DMA */ - -#ifdef CONFIG_ADC_DMA -# define NJOYSTICK_CHANNELS 2 -#else -# define NJOYSTICK_CHANNELS 1 -#endif - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 3 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT) -#else -/* Number of Joystick buttons */ - -# define AJOY_NGPIOS 7 - -/* Bitset of supported Joystick buttons */ - -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ - AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ - AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ - AJOY_BUTTON_7_BIT ) -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower); -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample); -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower); -static void -ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg); - -static void ajoy_disable(void); -static int ajoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Itead joystick button. Index using AJOY_* - * button definitions in include/nuttx/input/ajoystick.h. - */ - -#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 -}; -#else -static const uint32_t g_joygpio[AJOY_NGPIOS] = -{ - GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, - GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 -}; -#endif - -/* This is the button joystick lower half driver interface */ - -static const struct ajoy_lowerhalf_s g_ajoylower = -{ - .al_supported = ajoy_supported, - .al_sample = ajoy_sample, - .al_buttons = ajoy_buttons, - .al_enable = ajoy_enable, -}; - -#ifndef NO_JOYSTICK_ADC -/* Thread-independent file structure for the open ADC driver */ - -static struct file g_adcfile; -#endif - -/* Current interrupt handler and argument */ - -static ajoy_handler_t g_ajoyhandler; -static void *g_ajoyarg; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: ajoy_supported - * - * Description: - * Return the set of buttons supported on the button joystick device - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_supported(const struct ajoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", AJOY_SUPPORTED); - return (ajoy_buttonset_t)AJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: ajoy_sample - * - * Description: - * Return the current state of all button joystick buttons - * - ****************************************************************************/ - -static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, - struct ajoy_sample_s *sample) -{ -#ifndef NO_JOYSTICK_ADC - struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; - struct adc_msg_s *ptr; - ssize_t nread; - ssize_t offset; - int have; - int i; - - /* Read all of the available samples (handling the case where additional - * channels are enabled). - */ - - nread = file_read(&g_adcfile, adcmsg, - MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); - if (nread < 0) - { - if (nread != -EINTR) - { - ierr("ERROR: read failed: %d\n", (int)nread); - } - - return nread; - } - else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) - { - ierr("ERROR: read too small: %ld\n", (long)nread); - return -EIO; - } - - /* Sample and the raw analog inputs */ - -#ifdef CONFIG_ADC_DMA - have = 0; - -#else - /* If DMA is not supported, then we will have only a single ADC channel */ - - have = 2; - sample->as_y = 0; -#endif - - for (i = 0, offset = 0; - i < MAX_ADC_CHANNELS && offset < nread && have != 3; - i++, offset += sizeof(struct adc_msg_s)) - { - ptr = &adcmsg[i]; - - /* Is this one of the channels that we need? */ - - if ((have & 1) == 0 && ptr->am_channel == 0) - { - int32_t tmp = ptr->am_data; - sample->as_x = (int16_t)tmp; - have |= 1; - - iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); - } - -#ifdef CONFIG_ADC_DMA - if ((have & 2) == 0 && ptr->am_channel == 1) - { - int32_t tmp = ptr->am_data; - sample->as_y = (int16_t)tmp; - have |= 2; - - iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); - } -#endif - } - - if (have != 3) - { - ierr("ERROR: Could not find joystick channels\n"); - return -EIO; - } - -#else - /* ADC support is disabled */ - - sample->as_x = 0; - sample->as_y = 0; -#endif - - /* Sample the discrete button inputs */ - - sample->as_buttons = ajoy_buttons(lower); - iinfo("Returning: %02x\n", sample->as_buttons); - return OK; -} - -/**************************************************************************** - * Name: ajoy_buttons - * - * Description: - * Return the current state of button data (only) - * - ****************************************************************************/ - -static ajoy_buttonset_t -ajoy_buttons(const struct ajoy_lowerhalf_s *lower) -{ - ajoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Button outputs are pulled high. So a sensed low level means that the - * button is pressed. - */ - - if (!stm32_gpioread(g_joygpio[i])) - { - ret |= (1 << i); - } - } - - iinfo("Returning: %02x\n", ret); - return ret; -} - -/**************************************************************************** - * Name: ajoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, - ajoy_buttonset_t press, ajoy_buttonset_t release, - ajoy_handler_t handler, void *arg) -{ - irqstate_t flags; - ajoy_buttonset_t either = press | release; - ajoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - ajoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_ajoyhandler = handler; - g_ajoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, ajoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: ajoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void ajoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < AJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_ajoyhandler = NULL; - g_ajoyarg = NULL; -} - -/**************************************************************************** - * Name: ajoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int ajoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_ajoyhandler); - - if (g_ajoyhandler) - { - g_ajoyhandler(&g_ajoylower, g_ajoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ajoy_initialize - * - * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -int board_ajoy_initialize(void) -{ - int ret; - int i; - -#ifndef NO_JOYSTICK_ADC - iinfo("Initialize ADC driver: /dev/adc0\n"); - - /* Open the ADC driver for reading. - * NOTE: The ADC driver was initialized earlier in the bring-up sequence. - */ - - ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); - if (ret < 0) - { - ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); - return ret; - } -#endif - - /* Configure the GPIO pins as interrupting inputs. NOTE: This is - * unnecessary for interrupting pins since it will also be done by - * stm32_gpiosetevent(). - */ - - for (i = 0; i < AJOY_NGPIOS; i++) - { - /* Configure the PIO as an input */ - - stm32_configgpio(g_joygpio[i]); - } - - /* Register the joystick device as /dev/ajoy0 */ - - iinfo("Initialize joystick driver: /dev/ajoy0\n"); - - ret = ajoy_register("/dev/ajoy0", &g_ajoylower); - if (ret < 0) - { - ierr("ERROR: ajoy_register failed: %d\n", ret); -#ifndef NO_JOYSTICK_ADC - file_close(&g_adcfile); -#endif - } - - return ret; -} - -#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c deleted file mode 100644 index 5ef67f5e802f4..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LD2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LD2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c deleted file mode 100644 index a3af05f05271e..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * broughtvinto the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c deleted file mode 100644 index 893fe82510275..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c +++ /dev/null @@ -1,302 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include - -#ifdef CONFIG_PULSECOUNT -# include "stm32_pulsecount.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE -# include "board_hall3ph.h" -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32_romfs.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_PULSECOUNT - struct pulsecount_lowerhalf_s *pulsecount; -#endif - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_STM32_ROMFS - ret = stm32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!g_sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. There is no - * card detect GPIO. - */ - - sdio_mediachange(g_sdio, true); - - syslog(LOG_INFO, "[boot] Initialized SDIO\n"); -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PULSECOUNT - /* Initialize and register the pulse count driver. */ - - pulsecount = stm32_pulsecountinitialize(8); - if (pulsecount == NULL) - { - syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); - return -ENODEV; - } - - ret = pulsecount_register("/dev/pulsecount0", pulsecount); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F446RE_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_HALL3PHASE - /* Initialize and register the 3-phase Hall effect sensor driver */ - - ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, - GPIO_HALL_PHC); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the hall : %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_AJOYSTICK - /* Initialize and register the joystick driver */ - - ret = board_ajoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Initialize GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c deleted file mode 100644 index c7e976e49baaf..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-f446re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check that state of each USER button. A LOW value means that the key is - * pressed. - */ - - bool released = stm32_gpioread(GPIO_BTN_USER); - return !released; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32/nucleo-f446re/src/stm32_can.c deleted file mode 100644 index dd2c75c98b0c2..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c +++ /dev/null @@ -1,117 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - -#ifdef CONFIG_STM32_CAN1 - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - -#endif -#ifdef CONFIG_STM32_CAN2 - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(2); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can1" */ - - ret = can_register("/dev/can1", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - -#endif - UNUSED(ret); - UNUSED(can); - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c deleted file mode 100644 index e0ea15be89fe6..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c +++ /dev/null @@ -1,85 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret = OK; - - UNUSED(ret); - -#ifdef CONFIG_STM32_CAN1 - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - goto errout; - } -#endif - -#ifdef CONFIG_STM32_CAN2 - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - ret = stm32_cansockinitialize(2); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - goto errout; - } -#endif - -errout: - return ret; -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c deleted file mode 100644 index 1cb743db573d2..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_dac.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "nucleo-f446re.h" - -#ifdef CONFIG_DAC - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_DAC1CH1 -static struct dac_dev_s *g_dac1; -#endif - -#ifdef CONFIG_STM32_DAC1CH2 -static struct dac_dev_s *g_dac2; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC driver. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - int ret; -#ifdef CONFIG_STM32_DAC1CH1 - g_dac1 = stm32_dacinitialize(1); - if (g_dac1 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac1); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif -#ifdef CONFIG_STM32_DAC1CH2 - g_dac2 = stm32_dacinitialize(2); - if (g_dac2 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac1" */ - - ret = dac_register("/dev/dac1", g_dac2); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c deleted file mode 100644 index 43ceabb8ca309..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c deleted file mode 100644 index 9279bbe6630d5..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-f446re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - * Return Value: - * OK on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef CONFIG_PWM - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - -#if defined(CONFIG_STM32_TIM1_PWM) - pwm = stm32_pwminitialize(1); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) - pwm = stm32_pwminitialize(2); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) - pwm = stm32_pwminitialize(3); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) - pwm = stm32_pwminitialize(4); - if (!pwm) - { - pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - ret = pwm_register("/dev/pwm3", pwm); - if (ret < 0) - { - pwmerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - -#endif - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h deleted file mode 100644 index edb106e917d84..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c deleted file mode 100644 index 97b4fd238c999..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - uintptr_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = (uintptr_t)romfs_data_end - (uintptr_t)romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c deleted file mode 100644 index e713d51ed0ca6..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "nucleo-f446re.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 -struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 -struct spi_dev_s *g_spi2; -#endif -#ifdef CONFIG_STM32_SPI3 -struct spi_dev_s *g_spi3; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and - * Nucleo-F411RE boards. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - /* Configure SPI-based devices */ - - g_spi1 = stm32_spibus_initialize(1); - if (!g_spi1) - { - spierr("ERROR: FAILED to initialize SPI port 1\n"); - } - -#ifdef HAVE_MMCSD - stm32_configgpio(GPIO_SPI_CS_SD_CARD); -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Configure SPI-based devices */ - - g_spi2 = stm32_spibus_initialize(2); -#endif - -#ifdef CONFIG_STM32_SPI3 - /* Configure SPI-based devices */ - - g_spi3 = stm32_spibus_initialize(3); - -#ifdef HAVE_LCD - stm32_configgpio(GPIO_LCD_CS); - stm32_configgpio(GPIO_LCD_RS); -#endif - -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef HAVE_MMCSD - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef HAVE_LCD - stm32_gpiowrite(GPIO_LCD_CS, !selected); -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - stm32_gpiowrite(GPIO_LCD_RS, !cmd); - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c deleted file mode 100644 index 4a75e98c49689..0000000000000 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-f446re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LD2, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt deleted file mode 100644 index ce86b7005c12d..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig deleted file mode 100644 index f6f47682d13ac..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_COMP=y -CONFIG_DAC=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_DAC=y -CONFIG_EXAMPLES_DAC_DEVPATH="/dev/dac5" -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2021 -CONFIG_STM32_COMP2=y -CONFIG_STM32_COMP2_HYST=3 -CONFIG_STM32_COMP2_INM=4 -CONFIG_STM32_COMP2_OUT=y -CONFIG_STM32_DAC3=y -CONFIG_STM32_DAC3CH2=y -CONFIG_STM32_DAC3CH2_MODE=3 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig deleted file mode 100644 index d9c35a7176968..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig deleted file mode 100644 index 5d629e84f5c74..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431kb" -CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431K=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PWM=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_YEAR=2021 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431kb/include/board.h b/boards/arm/stm32/nucleo-g431kb/include/board.h deleted file mode 100644 index c5e339abd031c..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/include/board.h +++ /dev/null @@ -1,258 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Nucleo-G431KB supports four ways to configure high-speed clock - * - * - HSI configuration (default): 16 MHz high-speed internal RC oscillator. - * - HSE bypass configuration (from ST-LINK): The input clock is the - * ST-LINK MCO output. The frequency is fixed to 25 MHz, and connected - * to the PF0-OSC_IN of the STM32G4 microcontroller. - * - HSE bypass configuration (from ARDUINO D7): The clock is coming from - * an external oscillator through the pin PF0 (ARDUINO D7 pin 10 of the - * CN4 connector). - * - HSE oscillator configuration: The clock is provided by an external - * 24MHz crystal (X2) available in the PCB. - */ - -#define STM32_BOARD_XTAL 24000000ul /* 24MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The Nucleo-G431KB board has only one user LED, LD2. LD2 is a green LED - * connected to the following STM32G4 pins - * - PB8 (default) - * - PB3 - * It is also connected to Arduino signal D13. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control this LED in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED2 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo-G431KB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo G431KB don't have buttons that are controllable by software: - * - * B1 RESET: push button connected to NRST is used to RESET the - * STM32G431KB. - */ - -/* Alternate function pin selections ****************************************/ - -/* USART2 (STLINK Virtual COM Port) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ - -/* Comparators configuration ************************************************/ - -#define GPIO_COMP2_OUT GPIO_COMP2_OUT_3 /* PA12 */ -#define GPIO_COMP2_INP GPIO_COMP2_INP_2 /* PA7 */ -#define GPIO_COMP2_INM GPIO_COMP2_INM_2 /* PA5 check solder bridge SB2 */ - -/* DMA channels *************************************************************/ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs deleted file mode 100644 index 569fe825159c5..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431kb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32/nucleo-g431kb/scripts/ld.script deleted file mode 100644 index b7f4d0667e9eb..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431KB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431KB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt deleted file mode 100644 index e45962dfe2070..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g431kb/src/Make.defs b/boards/arm/stm32/nucleo-g431kb/src/Make.defs deleted file mode 100644 index 7aa1045c6a8c3..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/Make.defs +++ /dev/null @@ -1,48 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431kb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CSRCS += stm32_dac.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c deleted file mode 100644 index fbb97ddcaeb99..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431kb.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED2) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c deleted file mode 100644 index 4a75293c2de5b..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c deleted file mode 100644 index 7def155d6554a..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_COMP - /* Initialize and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c deleted file mode 100644 index 077454afccd8f..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c +++ /dev/null @@ -1,148 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_STM32_COMP) && (defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4)) - -#ifdef CONFIG_STM32_COMP1 -# if defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP3) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP3 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP1) || \ - defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP3) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret = OK; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP1 - comp = stm32_compinitialize(1); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 1); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP3 - comp = stm32_compinitialize(3); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 3); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_COMP - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return ret; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 || - * CONFIG_STM32_COMP3 || - * CONFIG_STM32_COMP4) */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c deleted file mode 100644 index 97790997116e4..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "nucleo-g431kb.h" - -#ifdef CONFIG_DAC - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_DAC1CH1 -static struct dac_dev_s *g_dac1; -#endif - -#ifdef CONFIG_STM32_DAC3CH2 -static struct dac_dev_s *g_dac5; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC driver. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - int ret; -#ifdef CONFIG_STM32_DAC1CH1 - g_dac1 = stm32_dacinitialize(1); - if (g_dac1 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac1); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif - -#ifdef CONFIG_STM32_DAC3CH2 - g_dac5 = stm32_dacinitialize(5); - if (g_dac5 == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac5" */ - - ret = dac_register("/dev/dac5", g_dac5); - if (ret < 0) - { - aerr("ERROR: dac_register() failed: %d\n", ret); - return ret; - } - -#endif - - UNUSED(ret); - return OK; -} - -#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c deleted file mode 100644 index 01ae0c9276541..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-g431kb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOG431KB_PWM_TIMER); - if (!pwm) - { - tmrerr("Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register(NUCLEOG431KB_PWM_PATH, pwm); - if (ret < 0) - { - tmrerr("pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c deleted file mode 100644 index 072ae0166ae0a..0000000000000 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g431kb.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt deleted file mode 100644 index c8eda596831a3..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig deleted file mode 100644 index c783fa1869d2e..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC2=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig deleted file mode 100644 index ee1142d3bc673..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CAN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STDIO_BUFFER_SIZE=512 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=71 -CONFIG_STM32_FDCAN1_NTSEG2=24 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig deleted file mode 100644 index f63b294d6bc4e..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y -CONFIG_BUILTIN=y -CONFIG_CANUTILS_CANDUMP=y -CONFIG_CANUTILS_CANSEND=y -CONFIG_CANUTILS_LIBCANUTILS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=10 -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_CAN=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FDCAN1=y -CONFIG_STM32_FDCAN1_BITRATE=250000 -CONFIG_STM32_FDCAN1_NTSEG1=71 -CONFIG_STM32_FDCAN1_NTSEG2=24 -CONFIG_STM32_FDCAN_SOCKET=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig deleted file mode 100644 index 755e3605c821c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_CORDIC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_MATH_CORDIC=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_CORDIC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig deleted file mode 100644 index cba47d6c50216..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM16M1=y -CONFIG_BOARD_STM32_IHM16M1_POT=y -CONFIG_BOARD_STM32_IHM16M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FIXED16_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FIXED16=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig deleted file mode 100644 index b1da16e313b60..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_MQUEUE is not set -# CONFIG_DISABLE_PTHREAD is not set -CONFIG_ADC=y -CONFIG_ADC_FIFOSIZE=3 -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=1024 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARMV7M_LIBM=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BOARD_STM32_IHM16M1=y -CONFIG_BOARD_STM32_IHM16M1_POT=y -CONFIG_BOARD_STM32_IHM16M1_VBUS=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DEFAULT_TASK_STACKSIZE=1024 -CONFIG_EXAMPLES_FOC=y -CONFIG_EXAMPLES_FOC_ADC_MAX=4095 -CONFIG_EXAMPLES_FOC_ADC_VREF=3300 -CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 -CONFIG_EXAMPLES_FOC_FLOAT_INST=1 -CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y -CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 -CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 -CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 -CONFIG_EXAMPLES_FOC_RAMP_THR=10000 -CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_ADC=y -CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 -CONFIG_INDUSTRY_FOC=y -CONFIG_INDUSTRY_FOC_FLOAT=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MOTOR=y -CONFIG_MOTOR_FOC=y -CONFIG_MOTOR_FOC_TRACE=y -CONFIG_MQ_MAXMSGSIZE=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_INJECTED_CHAN=3 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FOC=y -CONFIG_STM32_FOC_FOC0=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1_CH1MODE=0 -CONFIG_STM32_TIM1_CH2MODE=0 -CONFIG_STM32_TIM1_CH3MODE=0 -CONFIG_STM32_TIM1_MODE=2 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig deleted file mode 100644 index f760847d8e7aa..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_STACKSIZE=1024 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig deleted file mode 100644 index 9a390b1dbd801..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1NOUT=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CH2NOUT=y -CONFIG_STM32_TIM1_CH2OUT=y -CONFIG_STM32_TIM1_CH3NOUT=y -CONFIG_STM32_TIM1_CH3OUT=y -CONFIG_STM32_TIM1_CH4OUT=y -CONFIG_STM32_TIM1_CHANNEL1=y -CONFIG_STM32_TIM1_CHANNEL2=y -CONFIG_STM32_TIM1_CHANNEL3=y -CONFIG_STM32_TIM1_CHANNEL4=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig deleted file mode 100644 index 1af962f93e9ef..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g431rb" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G431R=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y -CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=22528 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y -CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_QE=y -CONFIG_STM32_TIM2_QEPSC=0 -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32/nucleo-g431rb/include/board.h deleted file mode 100644 index d0276b130af4f..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/include/board.h +++ /dev/null @@ -1,399 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define STM32_BOARD_XTAL 24000000 /* 8MHz */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */ - -#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE - -/* Main PLL Configuration. - * - * PLL source is HSE = 24MHz - * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSE x PLLN / PLLM - * = 24MHz x 86 / 6 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */ - -/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - */ - -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) - -#ifdef CONFIG_STM32_FDCAN -# ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE -# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) -# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) -# else -# error For now FDCAN supported only if HSE enabled -# endif -#endif - -/* LED definitions **********************************************************/ - -/* The NUCLEO-G431RB has four user LEDs. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo G431RB. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo G431RB supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32G431RB. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32G431RB. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* TIM2 input ***************************************************************/ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_3 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ - -/* USART2 (STLINK Virtual COM Port) */ - -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ - -/* PWM configuration ********************************************************/ - -/* TIM1 PWM */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_50MHz) /* PA11 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* PA9 */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1|GPIO_SPEED_50MHz) /* PA12 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* PA10 */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_1|GPIO_SPEED_50MHz) /* PB1 */ -#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) /* PC3 */ - -/* CAN configuration ********************************************************/ - -#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* DMA channels *************************************************************/ - -/* ADC */ - -#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ - -/* USART2 */ - -#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ -#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ - -#ifdef CONFIG_BOARD_STM32_IHM16M1 - -/* Configuration specific for the X-NUCLEO-IHM16M1 expansion board with - * the STSPIN830 driver. - */ - -/* TIM1 configuration *******************************************************/ - -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ -# define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* UVW ENABLE */ - -# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13) -# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14) -# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15) - -/* EN_FAULT */ - -# define GPIO_FOC_ENFAULT (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) - -/* Debug pins */ - -# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) -# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) -# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) -# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN12) - -#endif /* CONFIG_BOARD_STM32_IHM16M1 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs deleted file mode 100644 index 43067ac1b191b..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431rb/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32/nucleo-g431rb/scripts/ld.script deleted file mode 100644 index 75cdcb94d4751..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G431RB has 128 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G431RB has a total of 32 KiB of SRAM in three separate areas: - * - * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. - * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. - * - * CCM SRAM (Routine Booster): - * - * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff - * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt deleted file mode 100644 index f25dfbffa4954..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(NOT CONFIG_STM32_FOC) - if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) - endif() - - if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) - endif() -endif() - -if(CONFIG_BOARD_STM32_IHM16M1) - list(APPEND SRCS stm32_foc_ihm16m1.c) -endif() - -if(CONFIG_MATH_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g431rb/src/Make.defs b/boards/arm/stm32/nucleo-g431rb/src/Make.defs deleted file mode 100644 index 14403c2270048..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g431rb/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifneq ($(CONFIG_STM32_FOC),y) -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif -endif - -ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) -CSRCS += stm32_foc_ihm16m1.c -endif - -ifeq ($(CONFIG_MATH_CORDIC),y) -CSRCS += stm32_cordic.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c deleted file mode 100644 index c2b993d18fe6c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c +++ /dev/null @@ -1,240 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 15 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN15_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 17, - 7, - 6 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN17_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 17, - 7, - 6 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN17_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c deleted file mode 100644 index 4c599539d004c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c deleted file mode 100644 index 9cddcb3b09346..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c deleted file mode 100644 index 5eabcf6079811..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM driver. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register the FOC device - must be before ADC setup */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_MATH_CORDIC - /* Initialize CORDIC and register the CORDIC driver. */ - - ret = stm32_cordic_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cordic_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_NUCLEO_G431RB_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - /* Initialize CAN socket interface */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c deleted file mode 100644 index 462f70b091a77..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A HIGH value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c deleted file mode 100644 index 6f777f22c6148..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_fdcan.h" -#include "nucleo-g431rb.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if !defined(CONFIG_STM32_FDCAN1) -# error "No CAN is enable. Please enable at least one CAN device" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ - - can = stm32_fdcaninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c deleted file mode 100644 index 72b03dc2324b0..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_fdcan.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ - - ret = stm32_fdcansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get FDCAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c deleted file mode 100644 index ce64c50083ba4..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "nucleo-g431rb.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(NUCLEOG431RB_PWMTIMER); - if (!pwm) - { - tmrerr("Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c deleted file mode 100644 index 43528165fb31c..0000000000000 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g431rb.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/CMakeLists.txt deleted file mode 100644 index 7fcedbbbecbf8..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig deleted file mode 100644 index cb1bf8ee517b2..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMAMUX1=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_LPUART1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig deleted file mode 100644 index 5e03072fbf5f6..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig deleted file mode 100644 index 2d0e3747829cb..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-g474re" -CONFIG_ARCH_BOARD_NUCLEO_G474RE=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32G4=y -CONFIG_ARCH_CHIP_STM32G474R=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARMV7M_LIBM=y -CONFIG_ARMV7M_MEMCPY=y -CONFIG_BOARD_LOOPSPERMSEC=0 -CONFIG_CDCACM=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_HARDFAULT_INFO=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEBUG_USB=y -CONFIG_DEBUG_USB_ERROR=y -CONFIG_DEBUG_USB_WARN=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBFS=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_DUALSPEED=y -CONFIG_USBDEV_ISOCHRONOUS=y -CONFIG_USBDEV_MAXPOWER=500 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/nucleo-g474re/include/board.h b/boards/arm/stm32/nucleo-g474re/include/board.h deleted file mode 100644 index bbc4cf8cf354b..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/include/board.h +++ /dev/null @@ -1,191 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#undef STM32_BOARD_XTAL /* Not installed by default */ - -#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ -#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ -#undef STM32_HSE_FREQUENCY /* Not installed by default */ -#undef STM32_LSE_FREQUENCY /* Not available on this board */ - -/* Main PLL Configuration. - * - * PLL source is HSI = 16MHz - * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 - * - * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) - * f(PLL_P) = f(VCO Clock) / PLLP - * f(PLL_Q) = f(VCO Clock) / PLLQ - * f(PLL_R) = f(VCO Clock) / PLLR - * - * Where: - * 8 <= PLLN <= 127 - * 1 <= PLLM <= 16 - * PLLP = 2 through 31 - * PLLQ = 2, 4, 6, or 8 - * PLLR = 2, 4, 6, or 8 - * - * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). - * 64MHz <= f(VCO Clock) <= 344MHz. - * - * Given the above: - * - * f(VCO Clock) = HSI x PLLN / PLLM - * = 16MHz x 85 / 4 - * = 340MHz - * - * PLLPCLK = f(VCO Clock) / PLLP - * = 340MHz / 10 - * = 34MHz - * (May be used for ADC) - * - * PLLQCLK = f(VCO Clock) / PLLQ - * = 340MHz / 2 - * = 170MHz - * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to - * 48MHz, may be used for USB, RNG.) - * - * PLLRCLK = f(VCO Clock) / PLLR - * = 340MHz / 2 - * = 170MHz - * (May be used for SYSCLK and most peripherals.) - */ - -#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI -#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ - RCC_PLLCFGR_PLLQEN | \ - RCC_PLLCFGR_PLLREN) - -#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) -#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) -#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) -#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 -#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 - -#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) -#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) -#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) -#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) - -/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (170MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (170MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The NucleoG474RE board has one user LED. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* LD2 (Green) */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs - * on the board. The following definitions describe how NuttX controls the - * LEDs: - * - * |--------------------|-------------------------|------------| - * | SYMBOL | Meaning | LED states | - * |--------------------|-------------------------|------------| - * | LED_STARTED | NuttX has been started | 0 0 0 0 | - * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | - * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | - * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | - * | LED_INIRQ | In an interrupt | No change | - * | LED_SIGNAL | In a signal handler | No change | - * | LED_ASSERTION | An assertion failed | No change | - * | LED_PANIC | The system has crashed | 0 B 0 0 | - * | LED_IDLE | STM32 is in sleep mode | Not used | - * |--------------------|-------------------------|------------| - * - * LED states legend: - * 0 = off - * 1 = on - * B = blink - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* Alternate function pin selections ****************************************/ - -/* LPUART1 (ST LINK V3E Virtual Console) */ -#define GPIO_LPUART1_TX GPIO_LPUART1_TX_1 /* PA2 */ -#define GPIO_LPUART1_RX GPIO_LPUART1_RX_1 /* PA3 */ -#define GPIO_LPUART1_CTS GPIO_LPUART1_CTS_1 /* PA6 */ -#define GPIO_LPUART1_RTS GPIO_LPUART1_RTS_1 /* PB1 */ - -/* USART3 Pins CN7 Pins 1 and 2 */ -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ -#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ - -/* Pin Multiplexing Disambiguation ******************************************/ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_G474RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32/nucleo-g474re/scripts/Make.defs deleted file mode 100644 index 977ae0d4707bb..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script b/boards/arm/stm32/nucleo-g474re/scripts/ld.script deleted file mode 100644 index 6ed340018bc45..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu b/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu deleted file mode 100644 index e35b09cec8937..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. The FLASH bootloader is located there and - * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k - * if dual bank mode), so our executable will begin at 0x0800:6000, leaving - * 488KiB. - * - * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: - * - * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. - * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. - * - * CCM SRAM (Routine Booster): - * - * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff - * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous - * with the SRAM1 and SRAM2. - * - * Because SRAM1 and SRAM2 are contiguous, they are treated as one region - * by this logic. - * - * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded - * from this linker script, to keep it reserved for special uses in code. - * REVISIT: Is this the correct way to handle CCM SRAM? - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt deleted file mode 100644 index 53f5643fc8bab..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt +++ /dev/null @@ -1,37 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-g474re/src/Make.defs b/boards/arm/stm32/nucleo-g474re/src/Make.defs deleted file mode 100644 index b27f9af351497..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -ASRCS = -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_USBDEV),y) - CSRCS += stm32_usbdev.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c deleted file mode 100644 index c06b2fb11b508..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c +++ /dev/null @@ -1,84 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-g474re.h" - -#if defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c b/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c deleted file mode 100644 index 8f134c1cd9efa..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "nucleo-g474re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_ARCH_LEDS) - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c b/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c deleted file mode 100644 index bc3c6aa900739..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "nucleo-g474re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#if defined(HAVE_LEDS) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - syslog(LOG_INFO, "Initialize CDCACM device\n"); - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c b/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c deleted file mode 100644 index 898d118a8e708..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "nucleo-g474re.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c deleted file mode 100644 index 2b7b61b153a2e..0000000000000 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-g474re.h" - -#if !defined(CONFIG_ARCH_LEDS) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * Initialize the user LEDs before use. Note: For this function to be - * available to user application logic, CONFIG_ARCH_LEDS must not be - * defined. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Allow user application logic to control LEDs one at a time. Note: For - * this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * led: Index to the LED, which may be one of the defines BOARD_LED1, - * BOARD_LED2, BOARD_LED3, or BOARD_LED4. - * ledon: true to turn the LED on, false to turn it off. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - switch (led) - { - case BOARD_LED1: - stm32_gpiowrite(GPIO_LED1, ledon); - break; - } -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Allow user application logic to control all LEDs in one function call. - * Note: For this function to be available to user application logic, - * CONFIG_ARCH_LEDS must not be defined. - * - * Parameters: - * ledset: Bitmask indicating the new state for all LEDs, where a set bit - * indicates LED on and a clear bit indicates LED off. To - * construct the bitmask, using a bitwise OR of the defines - * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or - * BOARD_LED4_BIT. - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/CMakeLists.txt deleted file mode 100644 index 5a90572fa08db..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig deleted file mode 100644 index a877414347662..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NX_DISABLE_16BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l152re" -CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32L1=y -CONFIG_ARCH_CHIP_STM32L152RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXDEMO=y -CONFIG_EXAMPLES_NXDEMO_BPP=16 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_EXTERNINIT=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_ILI9341=y -CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LCD_ILI9341_IFACE0_PORTRAIT=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NX_BLOCKING=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=81920 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig deleted file mode 100644 index a014bf12d2565..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="nucleo-l152re" -CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32L1=y -CONFIG_ARCH_CHIP_STM32L152RE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NSH_READLINE=y -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_MUTEX_UNSAFE=y -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=81920 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/nucleo-l152re/include/board.h b/boards/arm/stm32/nucleo-l152re/include/board.h deleted file mode 100644 index 1c9ff4c06a5bd..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/include/board.h +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 16 MHz RC oscillator - * - HSE high-speed external oscillator clock. 8 MHz from MCO output of - * ST-LINK. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. - * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, - * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) - * and 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSE -> 8MHz - * - PLL multiplier is 12 -> 96MHz PLL VCO clock output - * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output - * - * Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz - * - * USB/SDIO: - * If the USB or SDIO interface is used in the application, the PLL VCO - * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 - * MHz frequency. This is required to provide a 48 MHz clock to the USB or - * SDIO (SDIOCLK or USBCLK = PLLVCO/2). - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * 24 MHz when the product is in range 3 (1.2V). - * Output division to avoid exceeding 32 MHz as SYSCLK. - * The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#if 1 -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* PLL clocked by the HSE */ -#define STM32_HSEBYP_ENABLE 1 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -#define STM32_PLL_FREQUENCY (12*STM32_BOARD_XTAL) /* PLL VCO Frequency is 96MHz */ -#else -#define STM32_CFGR_PLLSRC 0 /* PLL clocked by the HSI RC */ -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* TODO: Timers */ - -/* LED definitions **********************************************************/ - -/* The Nucleo L152RE board has three LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2-1. - * LD3 PWR: red LED indicates that the board is powered. - * - * And one can be controlled by software: - * - * User LD2: green LED is a user LED connected to the I/O PA5 of the - * STM32L152RET6. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in - * any way. The following definition is used to access the LED. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD2 */ -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board - * the Nucleo L152RE. The following definitions describe how NuttX controls - * the LED: - * - * SYMBOL Meaning LED1 state - * ------------------ ----------------------- ---------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Button definitions *******************************************************/ - -/* The Nucleo L152RE supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PC13 of the STM32L152RET6. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32L152RET6. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART */ - -/* By default the USART2 is connected to STLINK Virtual COM Port: - * USART2_RX - PA3 - * USART2_TX - PA2 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ - -/* SPI1 */ - -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* I2C1 */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_40MHz) /* PB8 CN5 pin 10, D15 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_40MHz) /* PB9 CN5 pin 9, D14 */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_L152RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs deleted file mode 100644 index 2eb2354673a80..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-l152re/scripts/ld.script b/boards/arm/stm32/nucleo-l152re/scripts/ld.script deleted file mode 100644 index 51325adba9348..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32L152RET6 has 512Kb of FLASH beginning at address 0x0800:0000, - * 80Kb of SRAM, and 16Kb of EEPROM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 80K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt deleted file mode 100644 index c8bbc27e2fe41..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_LCD_ILI9341) - list(APPEND SRCS stm32_ili93418b.c) -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_spisd.c) -endif() - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/nucleo-l152re/src/Make.defs b/boards/arm/stm32/nucleo-l152re/src/Make.defs deleted file mode 100644 index 3eafd51d2e9c2..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_LCD_ILI9341),y) -CSRCS += stm32_ili93418b.c -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_spisd.c -endif - -ifeq ($(CONFIG_STM32_SPI),y) -CSRCS += stm32_spi.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c deleted file mode 100644 index 69c14c5f96f34..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c deleted file mode 100644 index f9b3cd5843394..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_i2c.h" - -#include "nucleo-l152re.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; -#ifdef CONFIG_STM32_I2C1 - struct i2c_master_s *i2c1; -#endif -#ifdef CONFIG_STM32_I2C2 - struct i2c_master_s *i2c2; -#endif - -#ifdef CONFIG_STM32_I2C1 - /* Get the I2C lower half instance */ - - i2c1 = stm32_i2cbus_initialize(1); - if (i2c1 == NULL) - { - i2cerr("ERROR: Initialize I2C1: %d\n", ret); - } - else - { - /* Register the I2C character driver */ - - ret = i2c_register(i2c1, 1); - if (ret < 0) - { - i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); - } - } -#endif - -#ifdef CONFIG_STM32_I2C2 - /* Get the I2C lower half instance */ - - i2c2 = stm32_i2cbus_initialize(2); - if (i2c2 == NULL) - { - i2cerr("ERROR: Initialize I2C2: %d\n", ret); - } - else - { - /* Register the I2C character driver */ - - ret = i2c_register(i2c2, 2); - if (ret < 0) - { - i2cerr("ERROR: Failed to register I2C2 device: %d\n", ret); - } - } -#endif - -#ifdef CONFIG_STM32_SPI - stm32_spiinitialize(); -#endif - -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(0, STM32_PROCFS_MOUNTPOINT, "procfs", 0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - - /* Initialize the MMC/SD SPI driver (SPI1 is used) */ - - ret = stm32_spisd_initialize(1, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c deleted file mode 100644 index 47366db118cd9..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button - * resources. After that, board_buttons() may be called to collect the - * current state of all buttons or board_button_irq() may be called to - * register button interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure the single button as an input. NOTE that EXTI interrupts are - * also configured for the pin. - */ - - stm32_configgpio(GPIO_BTN_USER); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit unsigned integer with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the USER button. A LOW value means that the key is - * pressed. - */ - - return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of the - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == BUTTON_USER) - { - ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c deleted file mode 100644 index 5d59d781d635f..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c +++ /dev/null @@ -1,268 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "nucleo-l152re.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Global driver instances */ - -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *g_spi1; -#endif -#ifdef CONFIG_STM32_SPI2 - struct spi_dev_s *g_spi2; -#endif -#ifdef CONFIG_STM32_SPI3 - struct spi_dev_s *g_spi3; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spiinitialize - * - * Description: - * Called to configure SPI chip select GPIO pins. - * - ****************************************************************************/ - -void weak_function stm32_spiinitialize(void) -{ - int ret; -#ifdef CONFIG_STM32_SPI1 - /* Initialize the SPI1 bus */ - - g_spi1 = stm32_spibus_initialize(1); - if (g_spi1 == NULL) - { - spierr("ERROR: Initialize SPI1: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI1 character driver */ - - ret = spi_register(g_spi1, 1); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI1 device: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_STM32_SPI2 - /* Initialize the SPI2 bus */ - - g_spi2 = stm32_spibus_initialize(2); - if (g_spi2 == NULL) - { - spierr("ERROR: Initialize SPI2: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI2 character driver */ - - ret = spi_register(g_spi2, 2); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI2 device: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_STM32_SPI3 - /* Initialize the SPI3 bus */ - - g_spi3 = stm32_spibus_initialize(3); - if (g_spi3 == NULL) - { - spierr("ERROR: Initialize SPI3: \n"); - } - -#ifdef CONFIG_SPI_DRIVER - /* Register the SPI3 character driver */ - - ret = spi_register(g_spi3, 3); - if (ret < 0) - { - spierr("ERROR: Failed to register SPI3 device: %d\n", ret); - } -#endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SPI1_CS, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} - -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c deleted file mode 100644 index 4ed85198d21e5..0000000000000 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "nucleo-l152re.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/odrive36/CMakeLists.txt b/boards/arm/stm32/odrive36/CMakeLists.txt deleted file mode 100644 index 430752bb2ce04..0000000000000 --- a/boards/arm/stm32/odrive36/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/odrive36/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/odrive36/configs/nsh/defconfig b/boards/arm/stm32/odrive36/configs/nsh/defconfig deleted file mode 100644 index ec8b2cd552759..0000000000000 --- a/boards/arm/stm32/odrive36/configs/nsh/defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="odrive36" -CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15272 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig deleted file mode 100644 index d56e316f5c53d..0000000000000 --- a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="odrive36" -CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=15272 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/odrive36/include/board.h b/boards/arm/stm32/odrive36/include/board.h deleted file mode 100644 index 87d431fa5c4d7..0000000000000 --- a/boards/arm/stm32/odrive36/include/board.h +++ /dev/null @@ -1,212 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif -#include "stm32_rcc.h" -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* DMA Channel/Stream Selections ********************************************/ - -/* ADC 1 */ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* Alternate function pin selections ****************************************/ - -/* ADC */ - -#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 -#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 -#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 -#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 - -#define GPIO_ADC2_IN10 GPIO_ADC2_IN10_0 -#define GPIO_ADC2_IN11 GPIO_ADC2_IN11_0 -#define GPIO_ADC2_IN12 GPIO_ADC2_IN13_0 - -#define GPIO_ADC3_IN12 GPIO_ADC3_IN12_0 -#define GPIO_ADC3_IN13 GPIO_ADC3_IN13_0 - -/* USART2: - * USART2_TX - PA2 - GPIO_3 - * USART2_RX - PA3 - GPIO_4 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) - -/* CAN: - * CAN_R - PB8 - * CAN_T - PB9 - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -/* SPI3 - connected to DRV8301 - * SPI3_SCK - PC10 - * SPI3_MISO - PC11 - * SPI3_MOSI - PC12 - */ - -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) - -/* USBDEV */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) - -/* Dual FOC configuration */ - -/* TIM1 configuration *******************************************************/ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH1 - PA8 - U high */ -#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_2|GPIO_SPEED_100MHz) /* TIM1 CH1N - PB13 - U low */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH2 - PA9 - V high */ -#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_100MHz) /* TIM1 CH2N - PB14 - V low */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH3 - PA10 - W high */ -#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_100MHz) /* TIM1 CH3N - PB15 - W low */ -#define GPIO_TIM1_CH4OUT 0 /* not used as output */ - -/* TIM8 configuration *******************************************************/ - -#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH1 - PC6 - U high */ -#define GPIO_TIM8_CH1NOUT (GPIO_TIM8_CH1N_2|GPIO_SPEED_100MHz) /* TIM8 CH1N - PA7 - U low */ -#define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH2 - PC7 - V high */ -#define GPIO_TIM8_CH2NOUT (GPIO_TIM8_CH2N_1|GPIO_SPEED_100MHz) /* TIM8 CH2N - PB0 - V low */ -#define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH3 - PC8 - W high */ -#define GPIO_TIM8_CH3NOUT (GPIO_TIM8_CH3N_1|GPIO_SPEED_100MHz) /* TIM8 CH3N - PB1 - W low */ -#define GPIO_TIM8_CH4OUT 0 /* not used as output */ - -/* QEN3 configuration *******************************************************/ - -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) /* TIM3 CH1IN - PB4 */ -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) /* TIM3 CH2IN - PB5 */ - -/* QEN4 configuration *******************************************************/ - -#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_1|GPIO_SPEED_50MHz) /* TIM4 CH1IN - PB6 */ -#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_1|GPIO_SPEED_50MHz) /* TIM4 CH2IN - PB7 */ - -#endif /* __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/odrive36/scripts/Make.defs b/boards/arm/stm32/odrive36/scripts/Make.defs deleted file mode 100644 index fc9a05f91d22d..0000000000000 --- a/boards/arm/stm32/odrive36/scripts/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/odrive36/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/odrive36/scripts/ld.script b/boards/arm/stm32/odrive36/scripts/ld.script deleted file mode 100644 index 7e28d6544342d..0000000000000 --- a/boards/arm/stm32/odrive36/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(.init_array .init_array.*)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/odrive36/src/CMakeLists.txt b/boards/arm/stm32/odrive36/src/CMakeLists.txt deleted file mode 100644 index fb8dbb343df0c..0000000000000 --- a/boards/arm/stm32/odrive36/src/CMakeLists.txt +++ /dev/null @@ -1,39 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/odrive36/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/odrive36/src/Make.defs b/boards/arm/stm32/odrive36/src/Make.defs deleted file mode 100644 index 4074cab81c508..0000000000000 --- a/boards/arm/stm32/odrive36/src/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/odrive36/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_STM32_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/odrive36/src/stm32_boot.c b/boards/arm/stm32/odrive36/src/stm32_boot.c deleted file mode 100644 index bb3bb54f71f1b..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_boot.c +++ /dev/null @@ -1,107 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "odrive.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_SEGGER_SYSVIEW - up_perf_init((void *)STM32_SYSCLK_FREQUENCY); -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/odrive36/src/stm32_bringup.c b/boards/arm/stm32/odrive36/src/stm32_bringup.c deleted file mode 100644 index ab2bb6f29b8df..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_bringup.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include -#include - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -# include "stm32_qencoder.h" -#endif - -#include "odrive.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the PROC filesystem: %d\n", - ret); - } -#endif /* CONFIG_FS_PROCFS */ - -#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) - /* Initialize CDCACM */ - - ret = cdcacm_initialize(0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); - } -#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ - -#if defined(CONFIG_STM32_TIM3_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver - TIM3 */ - - ret = board_qencoder_initialize(0, 3); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); - } - - /* Connect QE index pin */ - - ret = stm32_qe_index_init(3, GPIO_QE3_INDEX); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); - } -#endif - -#if defined(CONFIG_STM32_TIM4_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver - TIM4 */ - - ret = board_qencoder_initialize(1, 4); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); - } - - /* Connect QE index pin */ - - ret = stm32_qe_index_init(4, GPIO_QE4_INDEX); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_FOC - /* Initialize and register FOC devices */ - - ret = stm32_foc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/odrive36/src/stm32_foc.c b/boards/arm/stm32/odrive36/src/stm32_foc.c deleted file mode 100644 index 7107a31b61a55..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_foc.c +++ /dev/null @@ -1,962 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_foc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_foc.h" -#include "stm32_gpio.h" -#ifdef CONFIG_ADC -# include "stm32_adc.h" -#endif - -#include "odrive.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_ODRIVE_HW_VOLTAGE_56 -# error Tested only for ODrive 56V version -#endif - -/* Supported FOC instances */ - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -# define ODRIVE_FOC_FOC0 1 -#else -# define ODRIVE_FOC_FOC0 0 -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -# define ODRIVE_FOC_FOC1 1 -#else -# define ODRIVE_FOC_FOC1 0 -#endif - -#define ODRIVE_FOC_INST (ODRIVE_FOC_FOC0 + ODRIVE_FOC_FOC1) - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -# define ODRIVE32_FOC0_DEVPATH "/dev/foc0" -# define ODRIVE32_FOC0_INST (0) -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -# define ODRIVE32_FOC1_DEVPATH "/dev/foc1" -# define ODRIVE32_FOC1_INST (1) -#endif - -/* Must match upper-half configuration */ - -#if ODRIVE_FOC_INST != CONFIG_MOTOR_FOC_INST -# error Invalid configuration -#endif - -/* Only 2-shunt configuration supported by board */ - -#if CONFIG_MOTOR_FOC_SHUNTS != 2 -# error For now only 2-shunts configuration is supported -#endif - -/* Configuration specific for DRV8301: - * 1. PWM channels must have positive polarity - * 2. PWM complementary channels must have positive polarity - */ - -#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY -# error -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - -# if CONFIG_STM32_TIM1_CH1POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH2POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH3POL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH1NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH2NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM1_CH3NPOL != 0 -# error -# endif - -/* FOC0 uses ADC2 */ - -# ifndef CONFIG_STM32_FOC_FOC0_ADC2 -# error -# endif - -# if CONFIG_STM32_ADC2_RESOLUTION != 0 -# error -# endif - -#endif /* CONFIG_ODRIVE_FOC_FOC0 */ - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - -# if CONFIG_STM32_TIM8_CH1POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH2POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH3POL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH1NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH2NPOL != 0 -# error -# endif -# if CONFIG_STM32_TIM8_CH3NPOL != 0 -# error -# endif - -/* FOC1 uses ADC3 */ - -# ifndef CONFIG_STM32_FOC_FOC1_ADC3 -# error -# endif - -# if CONFIG_STM32_ADC3_RESOLUTION != 0 -# error -# endif - -#endif /* CONFIG_ODRIVE_FOC_FOC1 */ - -/* Aux ADC needs DMA enabled */ - -#ifdef CONFIG_ADC -# ifndef CONFIG_STM32_ADC1_DMA -# error -# endif -# ifndef CONFIG_STM32_ADC1_SCAN -# error -# endif -#endif - -/* TODO: */ - -#define PWM_DEADTIME (50) -#define PWM_DEADTIME_NS (320) - -/* Board parameters: - * Current shunt resistance = 0.0005 - * Current sense gain = (10/20/40/80) - * Vbus min = 12V - * Vbus max = 24V or 56V - * Iout max = 40A (no cooling for - * MOSFETs) - * IPHASE_RATIO = 1/(R_shunt*gain) - * ADC_REF_VOLTAGE = 3.3 - * ADC_VAL_MAX = 4095 - * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX - * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = 0.02014 (gain=80) - * VBUS_RATIO = 1/VBUS_gain = 11 or 19 - */ - -#define ADC_VOLT_REF 3300000 /* micro volt */ -#define ADC_VAL_MAX 4095 -#define R_SHUNT 500 /* micro ohm */ - -/* Center-aligned PWM duty cycle limits */ - -#define MAX_DUTY_B16 ftob16(0.95f) - -/* ADC configuration */ - -#define CURRENT_SAMPLE_TIME ADC_SMPR_3 -#define VBUS_SAMPLE_TIME ADC_SMPR_15 -#define TEMP_SAMPLE_TIME ADC_SMPR_15 - -#define ODRIVE_ADC_AUX (1) -#define ODRIVE_ADC_FOC0 (2) -#define ODRIVE_ADC_FOC1 (3) - -#ifdef CONFIG_ODRIVE_FOC_VBUS -# define ODRIVE_FOC_VBUS 1 -#else -# define ODRIVE_FOC_VBUS 0 -#endif -#ifdef CONFIG_ODRIVE_FOC_TEMP -# define ODRIVE_FOC_TEMP 3 -#else -# define ODRIVE_FOC_TEMP 0 -#endif - -#ifdef CONFIG_ADC -# define ODRIVE_ADC_AUX_DEVPATH "/dev/adc0" -# define ODRIVE_ADC_AUX_NCHAN (ODRIVE_FOC_VBUS + ODRIVE_FOC_TEMP) -#endif - -#define ADC1_INJECTED (0) -#define ADC1_REGULAR (0) -#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) - -#define ADC2_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#define ADC2_REGULAR (0) -#define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) - -#define ADC3_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#define ADC3_REGULAR (0) -#define ADC3_NCHANNELS (ADC3_INJECTED + ADC3_REGULAR) - -#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN -# error -#endif - -#if ADC2_INJECTED != CONFIG_STM32_ADC2_INJECTED_CHAN -# error -#endif - -#if ADC3_INJECTED != CONFIG_STM32_ADC3_INJECTED_CHAN -# error -#endif - -/* DRV8301 configuration */ - -#ifndef CONFIG_STM32_SPI3 -# error -#endif - -#define DRV8301_0_SPI (3) -#define DRV8301_1_SPI (3) - -#define DRV8301_FREQUENCY (500000) - -/* Qenco configuration */ - -#ifdef CONFIG_SENSORS_QENCODER -# ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -# error Invalid configuration -# endif -# ifndef CONFIG_STM32_QENCODER_INDEX_PIN -# error Invalid configuration -# endif -# ifdef CONFIG_STM32_TIM3_QE -# if CONFIG_STM32_TIM3_QEPSC != 0 -# error Invalid TIM3 QEPSC value -# endif -# endif -# ifdef CONFIG_STM32_TIM4_QE -# if CONFIG_STM32_TIM4_QEPSC != 0 -# error Invalid TIM4 QEPSC value -# endif -# endif -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev); -static int board_foc_shutdown(struct foc_dev_s *dev); -static int board_foc_calibration(struct foc_dev_s *dev, bool state); -static int board_foc_fault_clear(struct foc_dev_s *dev); -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); -static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, - foc_current_t *curr); -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info); -static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, - unsigned long arg); -#ifdef CONFIG_MOTOR_FOC_TRACE -static int board_foc_trace_init(struct foc_dev_s *dev); -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); -#endif - -static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, - xcpt_t isr, void *arg); -static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, - bool enable); -static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev); - -static int stm32_focdev_setup(int devno, int spino, - struct stm32_foc_board_s *board); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Board specific ops */ - -static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = -{ - .setup = board_foc_setup, - .shutdown = board_foc_shutdown, - .calibration = board_foc_calibration, - .fault_clear = board_foc_fault_clear, - .pwm_start = board_foc_pwm_start, - .current_get = board_foc_current_get, - .info_get = board_foc_info_get, - .ioctl = board_foc_ioctl, -#ifdef CONFIG_MOTOR_FOC_TRACE - .trace_init = board_foc_trace_init, - .trace = board_foc_trace -#endif -}; - -/* Board specific ADC configuration - * - * AUX (only VBUS used): - * VBUS - ADC1 - ADC1_IN6 (PA6) - * M0_TEMP - ADC1 - ADC1_IN15 (PC5) - * M1_TEMP - ADC1 - ADC1_IN4 (PA4) - * AUX_TEMP - ADC1 - ADC1_IN5 (PA5) - * - * FOC device 0: - * Phase 1 - ADC2 - ADC2_IN10 (PC0) - * Phase 2 - ADC2 - ADC2_IN11 (PC1) - * - * FOC device 1: - * Phase 1 - ADC3 - ADC3_IN13 (PC3) - * Phase 2 - ADC3 - ADC3_IN12 (PC2) - * - */ - -#ifdef CONFIG_ADC - -/* AUX ADC configuration */ - -static uint8_t g_adc_aux_chan[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - 6, -#endif -#ifdef ODRIVE_ADC_TEMP - 15, - 4, - 5 -#endif -}; - -static uint32_t g_adc_aux_pins[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - GPIO_ADC1_IN6, -#endif -#ifdef ODRIVE_ADC_TEMP - GPIO_ADC1_IN15, - GPIO_ADC1_IN4, - GPIO_ADC1_IN5 -#endif -}; - -static adc_channel_t g_adc_aux_stime[] = -{ -#ifdef CONFIG_ODRIVE_FOC_VBUS - { - .channel = 6, - .sample_time = VBUS_SAMPLE_TIME - }, -#endif -#ifdef ODRIVE_ADC_TEMP - { - .channel = 15, - .sample_time = TEMP_SAMPLE_TIME - }, - { - .channel = 4, - .sample_time = TEMP_SAMPLE_TIME - }, - { - .channel = 5, - .sample_time = TEMP_SAMPLE_TIME - } -#endif -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -/* Board specific ADC configuration for FOC device 0 */ - -static uint8_t g_adc_foc0_chan[] = -{ - 10, - 11 -}; - -static uint32_t g_adc_foc0_pins[] = -{ - GPIO_ADC2_IN10, - GPIO_ADC2_IN11, -}; - -static adc_channel_t g_adc_foc0_stime[] = -{ - { - .channel = 10, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 11, - .sample_time = CURRENT_SAMPLE_TIME - } -}; - -static struct stm32_foc_adc_s g_adc_foc0_cfg = -{ - .chan = g_adc_foc0_chan, - .pins = g_adc_foc0_pins, - .stime = g_adc_foc0_stime, - .nchan = ADC2_NCHANNELS, - .regch = ADC2_REGULAR, - .intf = ODRIVE_ADC_FOC0 -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -/* Board specific ADC configuration for FOC device 1 */ - -static uint8_t g_adc_foc1_chan[] = -{ - 13, - 12 -}; - -static uint32_t g_adc_foc1_pins[] = -{ - GPIO_ADC3_IN13, - GPIO_ADC3_IN12, -}; - -static adc_channel_t g_adc_foc1_stime[] = -{ - { - .channel = 13, - .sample_time = CURRENT_SAMPLE_TIME - }, - { - .channel = 12, - .sample_time = CURRENT_SAMPLE_TIME - } -}; - -static struct stm32_foc_adc_s g_adc_foc1_cfg = -{ - .chan = g_adc_foc1_chan, - .pins = g_adc_foc1_pins, - .stime = g_adc_foc1_stime, - .nchan = ADC3_NCHANNELS, - .regch = ADC3_REGULAR, - .intf = ODRIVE_ADC_FOC1 -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC0 -/* Board specific data - FOC 0 */ - -static struct stm32_foc_board_data_s g_stm32_foc0_board_data = -{ - .adc_cfg = &g_adc_foc0_cfg, - .pwm_dt = (PWM_DEADTIME), -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc0_board = -{ - .data = &g_stm32_foc0_board_data, - .ops = &g_stm32_foc_board_ops, -}; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 -/* Board specific data - FOC 1 */ - -static struct stm32_foc_board_data_s g_stm32_foc1_board_data = -{ - .adc_cfg = &g_adc_foc1_cfg, - .pwm_dt = (PWM_DEADTIME), -}; - -/* Board specific configuration */ - -static struct stm32_foc_board_s g_stm32_foc1_board = -{ - .data = &g_stm32_foc1_board_data, - .ops = &g_stm32_foc_board_ops, -}; -#endif - -/* DRV8301 board ops */ - -static struct drv8301_ops_s g_drv8301_board_ops = -{ - .fault_attach = stm32_foc_drv8301_fault_attach, - .gate_enable = stm32_foc_drv8301_gate_enable, - .fault_handle = stm32_foc_drv8301_fault_handle -}; - -/* Global data */ - -static mutex_t g_common_lock = NXMUTEX_INITIALIZER; -static bool g_fault_attached = false; -static bool g_gate_enabled = false; - -static struct foc_dev_s *g_foc_dev[2] = -{ - NULL, - NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_foc_setup - ****************************************************************************/ - -static int board_foc_setup(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->setup(dev->pwr); -} - -/**************************************************************************** - * Name: board_foc_shutdown - ****************************************************************************/ - -static int board_foc_shutdown(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->shutdown(dev->pwr); -} - -/**************************************************************************** - * Name: board_foc_calibration - ****************************************************************************/ - -static int board_foc_calibration(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->calibration(dev->pwr, state); -} - -/**************************************************************************** - * Name: board_foc_fault_clear - ****************************************************************************/ - -static int board_foc_fault_clear(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* TODO: clear DRV8301 faults */ - - return OK; -} - -/**************************************************************************** - * Name: board_foc_pwm_start - ****************************************************************************/ - -static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) -{ - DEBUGASSERT(dev); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_current_get - ****************************************************************************/ - -static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, - foc_current_t *curr) -{ - DEBUGASSERT(dev); - DEBUGASSERT(curr_raw); - DEBUGASSERT(curr); - - /* Get currents */ - - curr[1] = curr_raw[0]; - curr[2] = curr_raw[1]; - - /* From Kirchhoff's current law: ia = -(ib + ic) */ - - curr[0] = -(curr[1] + curr[2]); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_info_get - ****************************************************************************/ - -static int board_foc_info_get(struct foc_dev_s *dev, - struct foc_info_s *info) -{ - struct foc_get_boardcfg_s cfg; - - DEBUGASSERT(dev); - DEBUGASSERT(info); - - UNUSED(dev); - - /* PWM */ - - info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; - info->hw_cfg.pwm_max = MAX_DUTY_B16; - - /* Get power stage configuration */ - - board_foc_ioctl(dev, MTRIOC_GET_BOARDCFG, (unsigned long)&cfg); - - /* ADC Current */ - - info->hw_cfg.iphase_max = 40000; - - info->hw_cfg.iphase_scale = ((100000ul * (ADC_VOLT_REF / ADC_VAL_MAX)) / - (cfg.gain * R_SHUNT)); - - return OK; -} - -/**************************************************************************** - * Name: board_foc_ioctl - ****************************************************************************/ - -static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, unsigned long arg) -{ - DEBUGASSERT(dev); - DEBUGASSERT(dev->pwr); - - return dev->pwr->ops->ioctl(dev->pwr, cmd, arg); -} - -#ifdef CONFIG_MOTOR_FOC_TRACE -/**************************************************************************** - * Name: board_foc_trace_init - ****************************************************************************/ - -static int board_foc_trace_init(struct foc_dev_s *dev) -{ - DEBUGASSERT(dev); - - UNUSED(dev); - - /* Not supported */ - - return -1; -} - -/**************************************************************************** - * Name: board_foc_trace - ****************************************************************************/ - -static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) -{ - DEBUGASSERT(dev); - - UNUSED(dev); -} -#endif - -/**************************************************************************** - * Name: stm32_foc_drv8301_fault_attach - ****************************************************************************/ - -static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, - xcpt_t isr, void *arg) -{ - int ret = OK; - - nxmutex_lock(&g_common_lock); - - /* nFAULT is common for both FOC instances */ - - if (g_fault_attached != (bool) isr) - { - ret = stm32_gpiosetevent(GPIO_DRV8301_NFAULT, false, true, false, - isr, arg); - - g_fault_attached = (bool) isr; - } - - nxmutex_unlock(&g_common_lock); - - return ret; -} - -/**************************************************************************** - * Name: stm32_foc_drv8301_gate_enable - ****************************************************************************/ - -static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, - bool enable) -{ - /* ENGATE is common for both FOC instances */ - - nxmutex_lock(&g_common_lock); - - if (enable != g_gate_enabled) - { - stm32_gpiowrite(GPIO_DRV8301_ENGATE, enable); - - g_gate_enabled = enable; - } - - nxmutex_unlock(&g_common_lock); - - return OK; -} - -/**************************************************************************** - * Name: stm32_foc_drv8301_fault_handle - ****************************************************************************/ - -static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev) -{ - UNUSED(dev); - - /* Set fault state for both instances */ - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - g_foc_dev[0]->state.fault |= FOC_FAULT_BOARD; -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - g_foc_dev[1]->state.fault |= FOC_FAULT_BOARD; -#endif - - /* Disable gates for both instances */ - - stm32_gpiowrite(GPIO_DRV8301_ENGATE, false); -} - -/**************************************************************************** - * Name: stm32_focdev_setup - ****************************************************************************/ - -static int stm32_focdev_setup(int devno, int spino, - struct stm32_foc_board_s *board) -{ - struct drv8301_cfg_s drv8301_cfg; - struct drv8301_board_s drv8301_board; - struct spi_dev_s *spi = NULL; - struct foc_dev_s *foc = NULL; - int ret = OK; - char devpath[20]; - - /* Initialize arch specific FOC 0 lower-half */ - - foc = stm32_foc_initialize(devno, board); - if (foc == NULL) - { - ret = -errno; - mtrerr("Failed to initialize STM32 FOC: %d\n", ret); - goto errout; - } - - DEBUGASSERT(foc->lower); - - /* Get devpath */ - - snprintf(devpath, sizeof(devpath), "/dev/foc%d", devno); - - /* Get SPI device */ - - spi = stm32_spibus_initialize(spino); - if (spi == NULL) - { - ret = -errno; - goto errout; - } - - /* DRV8301 configuration */ - - drv8301_cfg.freq = DRV8301_FREQUENCY; - drv8301_cfg.gate_curr = DRV8301_GATECURR_1p7; - drv8301_cfg.gain = DRV8301_GAIN_80; - drv8301_cfg.pwm_mode = DRV8301_PWM_6IN; - drv8301_cfg.oc_adj = DRV8301_OCADJ_DEFAULT; - - /* DRV8301 board data */ - - drv8301_board.spi = spi; - drv8301_board.ops = &g_drv8301_board_ops; - drv8301_board.cfg = &drv8301_cfg; - drv8301_board.devno = devno; - - /* Register DRV8301 device */ - - ret = drv8301_register(devpath, foc, &drv8301_board); - if (ret < 0) - { - mtrerr("Failed to register drv8301 device: %d\n", ret); - goto errout; - } - -errout: - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_foc_setup - * - * Description: - * Setup FOC devices - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_foc_setup(void) -{ - int ret = OK; - - /* Configure common EN_GATE */ - - stm32_configgpio(GPIO_DRV8301_ENGATE); - -#ifdef CONFIG_ODRIVE_FOC_FOC0 - ret = stm32_focdev_setup(0, DRV8301_0_SPI, &g_stm32_foc0_board); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_focdev_setup 0 failed: %d\n", ret); - goto errout; - } -#endif - -#ifdef CONFIG_ODRIVE_FOC_FOC1 - ret = stm32_focdev_setup(1, DRV8301_1_SPI, &g_stm32_foc1_board); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_focdev_setup 1 failed: %d\n", ret); - goto errout; - } -#endif - -errout: - return ret; -} - -#ifdef CONFIG_ADC -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc = NULL; - struct stm32_adc_dev_s *stm32_adc = NULL; - struct adc_sample_time_s stime; - int i = 0; - int ret = OK; - - /* Configure pins */ - - for (i = 0; i < ODRIVE_ADC_AUX_NCHAN; i += 1) - { - stm32_configgpio(g_adc_aux_pins[i]); - } - - /* Initialize ADC */ - - adc = stm32_adcinitialize(ODRIVE_ADC_AUX, g_adc_aux_chan, - ODRIVE_ADC_AUX_NCHAN); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface %d\n", ODRIVE_ADC_AUX); - ret = -ENODEV; - goto errout; - } - - /* Register ADC */ - - ret = adc_register(ODRIVE_ADC_AUX_DEVPATH, adc); - if (ret < 0) - { - aerr("ERROR: adc_register %s failed: %d\n", - ODRIVE_ADC_AUX_DEVPATH, ret); - goto errout; - } - - /* Get lower-half ADC */ - - stm32_adc = (struct stm32_adc_dev_s *)adc->ad_priv; - DEBUGASSERT(stm32_adc); - - /* Configure ADC sample time */ - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ODRIVE_ADC_AUX_NCHAN; - stime.channel = g_adc_aux_stime; - - STM32_ADC_SAMPLETIME_SET(stm32_adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(stm32_adc); - - ret = OK; - -errout: - return ret; -} -#endif diff --git a/boards/arm/stm32/odrive36/src/stm32_spi.c b/boards/arm/stm32/odrive36/src/stm32_spi.c deleted file mode 100644 index dd3c358b0706e..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_spi.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "odrive.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f4discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_MOTOR_FOC -# ifdef CONFIG_ODRIVE_FOC_FOC0 - stm32_configgpio(GPIO_GATEDRV0_CS); -# endif -# ifdef CONFIG_ODRIVE_FOC_FOC1 - stm32_configgpio(GPIO_GATEDRV1_CS); -# endif -#endif /* CONFIG_MOTOR_FOC */ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_MOTOR_FOC -# ifdef CONFIG_ODRIVE_FOC_FOC0 - if (devid == SPIDEV_MOTOR(0)) - { - stm32_gpiowrite(GPIO_GATEDRV0_CS, !selected); - } -# endif - -# ifdef CONFIG_ODRIVE_FOC_FOC1 - if (devid == SPIDEV_MOTOR(1)) - { - stm32_gpiowrite(GPIO_GATEDRV1_CS, !selected); - } -# endif -#endif /* CONFIG_MOTOR_FOC */ -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/odrive36/src/stm32_usb.c b/boards/arm/stm32/odrive36/src/stm32_usb.c deleted file mode 100644 index 6b622e0768b5a..0000000000000 --- a/boards/arm/stm32/odrive36/src/stm32_usb.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "odrive.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt deleted file mode 100644 index 33d4a70518187..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig deleted file mode 100644 index 76a1fb22c4c37..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BMP180=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_BMP180=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig deleted file mode 100644 index e8b7e412e0a28..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DAC=y -CONFIG_EXAMPLES_DAC=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig deleted file mode 100644 index 9a68e4e14850f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_DISCOVER=y -CONFIG_EXAMPLES_DISCOVER_DHCPC=y -CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80101 -CONFIG_EXAMPLES_DISCOVER_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="discover_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig deleted file mode 100644 index 68fcf5a41382b..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_INA219=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_INA219=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig deleted file mode 100644 index 705fc73e15577..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NET_ETHERNET is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_NET=y -CONFIG_DEBUG_NET_ERROR=y -CONFIG_DEBUG_NET_INFO=y -CONFIG_DEBUG_NET_WARN=y -CONFIG_DEBUG_WIRELESS=y -CONFIG_DEBUG_WIRELESS_ERROR=y -CONFIG_DEBUG_WIRELESS_INFO=y -CONFIG_DEBUG_WIRELESS_WARN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_IEEE802154_NETDEV=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_BUFSIZE=128 -CONFIG_IOB_NBUFFERS=32 -CONFIG_IOB_NCHAINS=16 -CONFIG_LINE_MAX=64 -CONFIG_MAC802154_NTXDESC=32 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDEV_IFINDEX=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_STATISTICS=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_6LOWPAN=y -CONFIG_NET_6LOWPAN_COMPRESSION_THRESHOLD=500 -CONFIG_NET_6LOWPAN_EXTENDEDADDR=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_AUTOCONF=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_ROUTER=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_PROMISCUOUS=y -CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_SYSTEM_SYSTEM=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig deleted file mode 100644 index aa23ce824c460..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_WIRELESS=y -CONFIG_DEBUG_WIRELESS_ERROR=y -CONFIG_DEBUG_WIRELESS_INFO=y -CONFIG_DEBUG_WIRELESS_WARN=y -CONFIG_DRIVERS_IEEE802154=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE802154_I8SAK=y -CONFIG_IEEE802154_MAC=y -CONFIG_IEEE802154_MACDEV=y -CONFIG_IEEE802154_MRF24J40=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_WIRELESS=y -CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig deleted file mode 100644 index f099771caefd3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80101 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig deleted file mode 100644 index ec0a10d31c543..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig deleted file mode 100644 index a81d22650165a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 -CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80185 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_LIBRARY=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_READLINE=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig deleted file mode 100644 index e98d6d69fa97e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TIMER=y -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig deleted file mode 100644 index 6105ef196c890..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig deleted file mode 100644 index 1a98f84122a37..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-e407" -CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="webserver_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_DISCOVER=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-e407/include/board.h b/boards/arm/stm32/olimex-stm32-e407/include/board.h deleted file mode 100644 index 2ea3adb4e42b0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/include/board.h +++ /dev/null @@ -1,280 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Olimex-STM32-E407 board features a 12MHz crystal and - * a 32kHz RTC backup crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output - * voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for : Enabled - * USB OTG FS, - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 12MHz - * LSE - 32.768 kHz - * STM32F407ZGT6 - too 168Mhz - */ - -#define STM32_BOARD_XTAL 12000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - * - * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 - * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-E405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-E405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART1 */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ - -/* USART2 */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ - -/* USART3 */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) /* PB6 */ -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) /* PB7 */ - -/* SPI1 */ - -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ - -/* Ethernet *****************************************************************/ - -#if defined(CONFIG_STM32_ETHMAC) -/* RMII interface to the LAN8710 PHY (works with LAN8720 driver) */ - -# ifndef CONFIG_STM32_RMII -# error CONFIG_STM32_RMII must be defined -# endif - -/* Clocking is provided by an external 50Mhz XTAL */ - -# ifndef CONFIG_STM32_RMII_EXTCLK -# error CONFIG_STM32_RMII_EXTCLK must be defined -# endif - -/* Pin disambiguation */ - -# define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) /* PA3 */ -# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) /* PG13 */ -# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* PG14 */ -# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ - -#endif - -/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs deleted file mode 100644 index 4d7247871dc24..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZE),y) -LDSCRIPT = f407ze.ld -else ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZG),y) -LDSCRIPT = f407zg.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt deleted file mode 100644 index 152d38216dde5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt +++ /dev/null @@ -1,77 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_CAN) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_IEEE802154_MRF24J40) - list(APPEND SRCS stm32_mrf24j40.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32F407ZE) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407ze.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407zg.ld") -endif() diff --git a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs b/boards/arm/stm32/olimex-stm32-e407/src/Make.defs deleted file mode 100644 index e5b1f17edc3de..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-e407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_CAN),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_DAC),y) -CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_IEEE802154_MRF24J40),y) -CSRCS += stm32_mrf24j40.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c deleted file mode 100644 index f97001b1243da..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, - * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, - * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, - * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - adbg("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - adbg("adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c deleted file mode 100644 index 89766c7191e4c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c deleted file mode 100644 index 9c52967acfcdd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_ccm.h" -#include "stm32.h" -#include "stm32_i2c.h" - -#include "olimex-stm32-e407.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c deleted file mode 100644 index 5636dad261832..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-e407.h" - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_SENSORS_INA219 -#include "stm32_ina219.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 -/* #define HAVE_I2CTOOL 1 */ - -/* Can't support USB host or device features if USB OTG HS is not enabled */ - -#ifndef CONFIG_STM32_OTGHS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# undef CONFIG_CAN -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef CONFIG_CAN - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_INA219 - /* Configure and initialize the INA219 sensor */ - - ret = board_ina219_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ina219initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_TIMER) - /* Initialize the timer, at this moment it's only Timer 1,2,3 */ - - #if defined(CONFIG_STM32_TIM1) - stm32_timer_driver_setup("/dev/timer1", 1); - #endif - #if defined(CONFIG_STM32_TIM2) - stm32_timer_driver_setup("/dev/timer2", 2); - #endif - #if defined(CONFIG_STM32_TIM3) - stm32_timer_driver_setup("/dev/timer3", 3); - #endif -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - /* Configure MRF24J40 wireless */ - - ret = stm32_mrf24j40_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed:" - " %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c deleted file mode 100644 index 8964bd3c7b4a7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is - * indexed by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c deleted file mode 100644 index 468129ff98d1f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - candbg("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - candbg("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c deleted file mode 100644 index b98658b4eb0cb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Acutronics Robotics All rights reserved. - * SPDX-FileContributor: Juan Flores - * SPDX-FileContributor: Juha Niskanen - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "stm32_dac.h" -#include "olimex-stm32-e407.h" - -#include - -#if defined(CONFIG_DAC) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct dac_dev_s *g_dac; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dac_setup - * - * Description: - * Initialize and register the DAC0 of the microcontroller. - * - * Input parameters: - * devpath - The full path to the driver to register. E.g., "/dev/dac0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_dac_setup(void) -{ - static bool initialized = false; - - if (!initialized) - { - int ret; - - g_dac = stm32_dacinitialize(1); - if (g_dac == NULL) - { - aerr("ERROR: Failed to get DAC interface\n"); - return -ENODEV; - } - - /* Register the DAC driver at "/dev/dac0" */ - - ret = dac_register("/dev/dac0", g_dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c deleted file mode 100644 index 7659f5432a767..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_exti.h" -#include "stm32_spi.h" - -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_IEEE802154_MRF24J40 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_priv_s -{ - struct mrf24j40_lower_s dev; - xcpt_t handler; - void *arg; - uint32_t intcfg; - uint8_t spidev; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MRF24J40 driver from differences in GPIO interrupt handling - * varying boards and MCUs. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg); -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state); -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MRF24J40 - * driver. This structure provides information about the configuration - * of the MRF24J40 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_priv_s g_mrf24j40_mb1_priv = -{ - .dev.attach = stm32_attach_irq, - .dev.enable = stm32_enable_irq, - .handler = NULL, - .arg = NULL, - .intcfg = GPIO_MRF24J40_INT, - .spidev = 1, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the MRF24J40 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO - * interrupt - * irq_enable - Enable or disable the GPIO interrupt - */ - -static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, - xcpt_t handler, void *arg) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - DEBUGASSERT(priv != NULL); - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, - bool state) -{ - struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); - - wlinfo("state:%d\n", (int)state); - - /* Attach and enable, or detach and disable */ - - if (state) - { - stm32_gpiosetevent(priv->intcfg, false, true, true, - priv->handler, priv->arg); - } - else - { - stm32_gpiosetevent(priv->intcfg, false, false, false, - NULL, NULL); - } -} - -/**************************************************************************** - * Name: stm32_mrf24j40_devsetup - * - * Description: - * Initialize one the MRF24J40 device in one mikroBUS slot - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) -{ - struct ieee802154_radio_s *radio; - MACHANDLE mac; - struct spi_dev_s *spi; - int ret; - - /* Configure the interrupt pin */ - - stm32_configgpio(priv->intcfg); - - /* Initialize the SPI bus and get an instance of the SPI interface */ - - spi = stm32_spibus_initialize(priv->spidev); - if (spi == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Initialize and register the SPI MRF24J40 device */ - - radio = mrf24j40_init(spi, &priv->dev); - if (radio == NULL) - { - wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); - return -ENODEV; - } - - /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ - - mac = mac802154_create(radio); - if (mac == NULL) - { - wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); - return -ENODEV; - } - -#ifdef CONFIG_IEEE802154_NETDEV - /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN - * network interface by wrapping the MAC interface instance in a - * network device driver via mac802154dev_register(). - */ - - ret = mac802154netdev_register(mac); - if (ret < 0) - { - wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", - 0, ret); - return ret; - } -#endif - -#ifdef CONFIG_IEEE802154_MACDEV - /* If want to call these APIs from userspace, you have to wrap the MAC - * interface in a character device viamac802154dev_register(). - */ - - ret = mac802154dev_register(mac, 0); - if (ret < 0) - { - wlerr("ERROR: " - "Failed to register the MAC character driver /dev/ieee%d: %d\n", - 0, ret); - return ret; - } -#endif - - UNUSED(ret); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mrf24j40_initialize - * - * Description: - * Initialize the MRF24J40 device. - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_mrf24j40_initialize(void) -{ - int ret; - - wlinfo("Configuring MRF24J40\n"); - - ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); - if (ret < 0) - { - wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); - } - - UNUSED(ret); - return OK; -} -#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c deleted file mode 100644 index 8f81e1556a2ff..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c +++ /dev/null @@ -1,303 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Olimex-STM32-E407 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_LCD_ST7567 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_LCD_PCD8544 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_WL_NRF24L01 - stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - stm32_configgpio(GPIO_MRF24J40_CS); /* MRF24J40 chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif - -#ifdef CONFIG_IEEE802154_MRF24J40 - if (devid == SPIDEV_IEEE802154(0)) - { - stm32_gpiowrite(GPIO_MRF24J40_CS, !selected); - } -#endif - -#if defined(CONFIG_IEEE802154_XBEE) - if (devid == SPIDEV_IEEE802154(0)) - { - stm32_gpiowrite(GPIO_XBEE_CS, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_CD, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c deleted file mode 100644 index 5bc17c864d089..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c deleted file mode 100644 index 4df415385ef59..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c +++ /dev/null @@ -1,329 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-e407.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO -# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor - * for device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uvdbg("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, andi - * the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c deleted file mode 100644 index d9e198ee1993f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-e407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt deleted file mode 100644 index 58cb6b3682885..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig deleted file mode 100644 index a3ba7928726f2..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h405" -CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_CAN=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG2=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-h405/include/board.h b/boards/arm/stm32/olimex-stm32-h405/include/board.h deleted file mode 100644 index 81bdf2420020d..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/include/board.h +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(12) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(360) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-H405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-H405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ -#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs deleted file mode 100644 index ecd20a669ce6a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script b/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script deleted file mode 100644 index 37a944a3efbba..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt deleted file mode 100644 index 0fb338eadb597..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs b/boards/arm/stm32/olimex-stm32-h405/src/Make.defs deleted file mode 100644 index 82df67a1c2ddd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h405/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c deleted file mode 100644 index f741f3255f9f7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; -/* , 2, 3, - * 4, 5, 6, - * 7, 8, 9, - * 10, 11, 12, - * 13, 15 - * }; - */ - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1_0 -}; -/* , GPIO_ADC1_IN2_0, GPIO_ADC1_IN3_0, - * GPIO_ADC1_IN4_0, GPIO_ADC1_IN5_0, GPIO_ADC1_IN6_0, - * GPIO_ADC1_IN7_0, GPIO_ADC1_IN8_0, GPIO_ADC1_IN9_0, - * GPIO_ADC1_IN10_0, GPIO_ADC1_IN11_0, GPIO_ADC1_IN12_0, - * GPIO_ADC1_IN13_0, GPIO_ADC1_IN15_0 - * }; - */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c deleted file mode 100644 index 7dc946d460e4e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c deleted file mode 100644 index f7b9a5410e369..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-h405.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) -# undef CONFIG_CAN -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c deleted file mode 100644 index 5a2e348ea2e84..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c deleted file mode 100644 index 64bbe3f5b0cfe..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c deleted file mode 100644 index ce10acef66425..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-h405.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c deleted file mode 100644 index 8b80592954273..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-h405.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt deleted file mode 100644 index 37624d8016fb5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig deleted file mode 100644 index a7d1a43050305..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_EXCHANGE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h407" -CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig deleted file mode 100644 index 2a561e5dad30c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_EXCHANGE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-h407" -CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-h407/include/board.h b/boards/arm/stm32/olimex-stm32-h407/include/board.h deleted file mode 100644 index e585d6a451dd5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/include/board.h +++ /dev/null @@ -1,287 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Olimex-STM32-H407 board features a 12MHz crystal and - * a 32kHz RTC backup crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output - * voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, - * SDIO and RNG clock : Enabled - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 12MHz - * LSE - 32.768 kHz - * STM32F407ZGT6 - too 168Mhz - */ - -#define STM32_BOARD_XTAL 12000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 12) * 360 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - * - * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 - * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status - * LED in any way. - * The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED_STATUS 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED_STATUS_BIT (1 << BOARD_LED_STATUS) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of - * the Olimex STM32-H405. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED_STATUS on */ -#define LED_HEAPALLOCATE 1 /* no change */ -#define LED_IRQSENABLED 2 /* no change */ -#define LED_STACKCREATED 3 /* no change */ -#define LED_INIRQ 4 /* no change */ -#define LED_SIGNAL 5 /* no change */ -#define LED_ASSERTION 6 /* LED_STATUS off */ -#define LED_PANIC 7 /* LED_STATUS blinking */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-H405 supports one buttons: */ - -#define BUTTON_BUT 0 -#define NUM_BUTTONS 1 - -#define BUTTON_BUT_BIT (1 << BUTTON_BUT) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#if 0 -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ -#endif - -/* USART2: */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) -#define GPIO_USART2_CTS GPIO_USART2_CTS_1 -#define GPIO_USART2_RTS GPIO_USART2_RTS_1 - -/* USART6: (UEXT connector) */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) - -/* GPIO_USART6_CTS and GPIO_USART6_RTS aren't used for UEXT */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ -#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs deleted file mode 100644 index 6dae53fb984eb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script b/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script deleted file mode 100644 index 2d0c8e0704f54..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407ZGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt deleted file mode 100644 index 4f687f840f77a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt +++ /dev/null @@ -1,65 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs b/boards/arm/stm32/olimex-stm32-h407/src/Make.defs deleted file mode 100644 index 9e3959c58c9d8..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs +++ /dev/null @@ -1,67 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c deleted file mode 100644 index 6ec856172e30f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c +++ /dev/null @@ -1,165 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1//14 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. - * - * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 1 -}; - -/* Configurations of pins used byte each ADC channels - * - * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, - * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, - * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, - * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; - */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN1 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c deleted file mode 100644 index 8b8236d5ea945..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED_STATUS GPIO for output */ - - stm32_configgpio(GPIO_LED_STATUS); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == LED_STARTED) - { - stm32_gpiowrite(GPIO_LED_STATUS, false); - } - - if (led == LED_ASSERTION || led == LED_PANIC) - { - stm32_gpiowrite(GPIO_LED_STATUS, true); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c deleted file mode 100644 index a2f2c02ed66f9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "olimex-stm32-h407.h" -#include "stm32_ccm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - * Presumably either CONFIG_USBDEV is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c deleted file mode 100644 index 7a4e99655bdab..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c +++ /dev/null @@ -1,168 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-h407.h" - -/* Conditional logic in olimex-stm32-h407.h will determine if certain - * features are supported. - * Tests for these features need to be made after including - * olimex-stm32-h407.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y: - * Called from board_late_initialize(). - * - * Otherwise, bad news: Never called - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize MMC/SD driver: %d\n", - ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. - * stm32_usbhost_initialize() starts a thread will monitor for USB - * connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize USB host: %d\n", - ret); - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to start USB monitor: %d\n", - ret); - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - syslog(LOG_ERR, - "ERROR: Failed to instantiate the RTC lower-half driver\n"); - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind/register the RTC driver: %d\n", - ret); - } - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c deleted file mode 100644 index f8eefa4d76fa2..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_BUT -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_BUT])) - { - ret |= BUTTON_BUT_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c deleted file mode 100644 index c9cc0fc267886..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c deleted file mode 100644 index 7752b2a054d29..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c deleted file mode 100644 index 2da446dbe0791..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32_otghs.h" -#include "olimex-stm32-h407.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F407_USBHOST_PRIO -# define CONFIG_STM32F407_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F407_USBHOST_STACKSIZE -# define CONFIG_STM32F407_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_VBUS); - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO, - CONFIG_STM32H407_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c deleted file mode 100644 index 7f7b316204499..0000000000000 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "olimex-stm32-h407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED_STATUS -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED_STATUS); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt deleted file mode 100644 index 714fc64c28c14..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig deleted file mode 100644 index 92e3f709d9e78..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p107" -CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DRIPADDR=0xc0a80201 -CONFIG_NETINIT_IPADDR=0xc0a80232 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p107/include/board.h b/boards/arm/stm32/olimex-stm32-p107/include/board.h deleted file mode 100644 index 2af99acd922b2..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/include/board.h +++ /dev/null @@ -1,145 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. From above, we already have PLL3 input - * frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs deleted file mode 100644 index 340d9862478fd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script b/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script deleted file mode 100644 index a0144f22e74c8..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu b/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu deleted file mode 100644 index 9a2251caf1a65..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Don't know if this is correct. Just 256K-48K (not testet) */ -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt deleted file mode 100644 index 0e5286c799dbe..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt +++ /dev/null @@ -1,35 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ENCX24J600) - list(APPEND SRCS stm32_encx24j600.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs b/boards/arm/stm32/olimex-stm32-p107/src/Make.defs deleted file mode 100644 index d7aa1806f7391..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs +++ /dev/null @@ -1,37 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p107/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ENCX24J600),y) -CSRCS += stm32_encx24j600.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c deleted file mode 100644 index 729ccbe7e16eb..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "arm_internal.h" -#include "olimex-stm32-p107.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. - * This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c deleted file mode 100644 index 1836835c4bcc5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c deleted file mode 100644 index 62ae40b65edd0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "olimex-stm32-p107.h" - -#if defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Olimex stm32-p107 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* Configure ENCX24J600 SPI1 CS (also RESET and interrupt pins) */ - -#if defined(CONFIG_ENCX24J600) && defined(CONFIG_STM32_SPI3) - stm32_configgpio(GPIO_ENCX24J600_CS); - stm32_configgpio(GPIO_ENCX24J600_INTR); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENCX24J600_CS, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt deleted file mode 100644 index e80a16fed32e0..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig deleted file mode 100644 index ed329af28cdb3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p207" -CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207ZE=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_DRIPADDR=0xa0000001 -CONFIG_NETINIT_IPADDR=0xa0000002 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG2=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x18 -CONFIG_STM32_PHYSR_100HD=0x8 -CONFIG_STM32_PHYSR_10FD=0x14 -CONFIG_STM32_PHYSR_10HD=0x4 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x1c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST=y diff --git a/boards/arm/stm32/olimex-stm32-p207/include/board.h b/boards/arm/stm32/olimex-stm32-p207/include/board.h deleted file mode 100644 index 6a632373c9bc5..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/include/board.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN1 BOARD_LED1 -#define BOARD_LED_YELLOW BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_GREEN2 BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the Olimex STM32-P207. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-P207 supports seven buttons: */ - -#define BUTTON_TAMPER 0 -#define BUTTON_WKUP 1 -#define BUTTON_RIGHT 2 -#define BUTTON_UP 3 -#define BUTTON_LEFT 4 -#define BUTTON_DOWN 5 -#define BUTTON_CENTER 6 - -#define NUM_BUTTONS 7 - -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) -#define BUTTON_RIGHT_BIT (1 << BUTTON_RIGHT) -#define BUTTON_UP_BIT (1 << BUTTON_UP) -#define BUTTON_LEFT_BIT (1 << BUTTON_LEFT) -#define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) -#define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ - -/* CAN: */ -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* Ethernet: */ - -/* - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - NC (not connected) - * - PA0 is ETH_MII_CRS - NC - * - PA3 is ETH_MII_COL - NC - * - PB10 is ETH_MII_RX_ER - NC - * - PB0 is ETH_MII_RXD2 - NC - * - PH7 is ETH_MII_RXD3 - NC - * - PC3 is ETH_MII_TX_CLK - NC - * - PC2 is ETH_MII_TXD2 - NC - * - PB8 is ETH_MII_TXD3 - NC - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs deleted file mode 100644 index 9aaebcbad7a64..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script b/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script deleted file mode 100644 index d8e4a95fc739c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt deleted file mode 100644 index 98fcae67692dc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs b/boards/arm/stm32/olimex-stm32-p207/src/Make.defs deleted file mode 100644 index 42ceed74368d7..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p207/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c deleted file mode 100644 index 8224185440092..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P207 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10_0 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c deleted file mode 100644 index 7455e3582f3c9..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define LED_STARTED_BITS (BOARD_LED1_BIT) -#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) -#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) -#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) -#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) -#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_PANIC_BITS (BOARD_LED4_BIT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const unsigned int g_ledbits[8] = -{ - LED_STARTED_BITS, - LED_HEAPALLOCATE_BITS, - LED_IRQSENABLED_BITS, - LED_STACKCREATED_BITS, - LED_INIRQ_BITS, - LED_SIGNAL_BITS, - LED_ASSERTION_BITS, - LED_PANIC_BITS -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | - BOARD_LED3_BIT | BOARD_LED4_BIT); - led_setbits(g_ledbits[led]); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_clrbits(g_ledbits[led]); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c deleted file mode 100644 index 3ce6df06ea461..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c +++ /dev/null @@ -1,205 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-p207.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device if USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_STM32_USBHOST -# undef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c deleted file mode 100644 index fbf2d1236ba66..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_TAMPER, - GPIO_BTN_WKUP, - GPIO_BTN_RIGHT, - GPIO_BTN_UP, - GPIO_BTN_LEFT, - GPIO_BTN_DOWN, - GPIO_BTN_CENTER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) - { - ret |= BUTTON_TAMPER_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_WKUP])) - { - ret |= BUTTON_WKUP_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_RIGHT])) - { - ret |= BUTTON_RIGHT_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_UP])) - { - ret |= BUTTON_UP_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_LEFT])) - { - ret |= BUTTON_LEFT_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_DOWN])) - { - ret |= BUTTON_DOWN_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_CENTER])) - { - ret |= BUTTON_CENTER_BIT; - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c deleted file mode 100644 index b2bf59dacf7ef..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c deleted file mode 100644 index 0217d0bdfd1c3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c +++ /dev/null @@ -1,313 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-p207.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB host Mass Storage Class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c deleted file mode 100644 index 044ff84794de1..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-p207.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt deleted file mode 100644 index 9932d6545d588..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig deleted file mode 100644 index f9ead32d95bbd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_CS4344=y -CONFIG_AUDIO_EXCLUDE_TONE=y -CONFIG_AUDIO_EXCLUDE_VOLUME=y -CONFIG_AUDIO_I2S=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_I2S3=y -CONFIG_STM32_I2S3_TX=y -CONFIG_STM32_I2S_MCK=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_DMA=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig deleted file mode 100644 index 2ffe4347fa1da..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_DHTXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_DHTXX=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FREERUN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig deleted file mode 100644 index c9560ec454115..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs deleted file mode 100644 index b8256a1439968..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# NXFLAT module definitions - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig deleted file mode 100644 index d7b726a5612fc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_ELF_STACKSIZE=4096 -CONFIG_EXAMPLES_ELF=y -CONFIG_EXAMPLES_ELF_DEVPATH="/dev/sda" -CONFIG_EXAMPLES_ELF_FSREMOVEABLE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="elf_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PATH_INITIAL="/mnt/vfat" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=4 -CONFIG_START_MONTH=8 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs deleted file mode 100644 index 03291ccbb7842..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# NXFLAT module definitions - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig deleted file mode 100644 index d03474e354acd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/sda" -CONFIG_EXAMPLES_MODULE_FSREMOVEABLE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="module_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_MODULE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=8 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs deleted file mode 100644 index e933d297972bd..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT1 = memory.ld -LDSCRIPT2 = kernel-space.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig deleted file mode 100644 index c7ce54486b294..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig deleted file mode 100644 index 854cda731db49..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=64 -CONFIG_MODULE=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=393216 -CONFIG_RAM_START=0x20400000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_MONTH=6 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig deleted file mode 100644 index d59e71b70d949..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ /dev/null @@ -1,82 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_STM32_AUTONEG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_KS8721=y -CONFIG_EXAMPLES_MQTTC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HTS221_DEBUG=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0xc0a80101 -CONFIG_NETINIT_DRIPADDR=0xc0a80101 -CONFIG_NETINIT_IPADDR=0xc0a801e1 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_MQTTC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_NOTIFIER=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_HTS221=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_ETH100MBPS=y -CONFIG_STM32_ETHFD=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NETDB=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TELNET_CLIENT=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig deleted file mode 100644 index 068f384397b42..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=32 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig deleted file mode 100644 index c5f244513af7e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimex-stm32-p407" -CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407ZG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_I2C_RESET=y -CONFIG_I2S=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_IFLOWCONTROL_LOWER_WATERMARK=25 -CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK=75 -CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SPI=y -CONFIG_START_DAY=26 -CONFIG_START_MONTH=5 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USART6=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_ZMODEM=y -CONFIG_SYSTEM_ZMODEM_DEVNAME="/dev/ttyS1" -CONFIG_SYSTEM_ZMODEM_IFLOW=y -CONFIG_SYSTEM_ZMODEM_MOUNTPOINT="/mnt" -CONFIG_SYSTEM_ZMODEM_OFLOW=y -CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 -CONFIG_USART3_BAUD=9600 -CONFIG_USART3_IFLOWCONTROL=y -CONFIG_USART3_OFLOWCONTROL=y -CONFIG_USART3_RXBUFSIZE=512 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/olimex-stm32-p407/include/board.h b/boards/arm/stm32/olimex-stm32-p407/include/board.h deleted file mode 100644 index 92a26895aadca..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/include/board.h +++ /dev/null @@ -1,453 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN1 BOARD_LED1 -#define BOARD_LED_YELLOW BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_GREEN2 BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the Olimex STM32-P407. The following definitions describe how - * NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The Olimex STM32-P407 supports seven buttons: */ - -#define BUTTON_TAMPER 0 -#define BUTTON_WKUP 1 - -#ifdef CONFIG_INPUT_DJOYSTICK -# define NUM_BUTTONS 2 -#else -# define JOYSTICK_RIGHT 2 -# define JOYSTICK_UP 3 -# define JOYSTICK_LEFT 4 -# define JOYSTICK_DOWN 5 -# define JOYSTICK_CENTER 6 - -# define NUM_BUTTONS 7 -#endif - -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) - -#ifndef CONFIG_INPUT_DJOYSTICK -# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) -# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) -# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) -# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) -# define JOYSTICK_CENTER_BIT (1 << JOYSTICK_CENTER) -#endif - -/* Alternate function pin selections ****************************************/ - -/* USART3: */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ -#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ - -/* UEXT USART3: This will redefine the above macros if enabled. */ - -#ifdef CONFIG_STM32_OLIMEXP407_UEXT_USART3 -# undef GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) -# undef GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) -# undef GPIO_USART3_CTS GPIO_USART3_CTS_2 -# undef GPIO_USART3_RTS GPIO_USART3_RTS_2 - -# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) /* PC11 */ -# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) /* PC10 */ -#endif - -/* USART6: */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) /* PG9 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ - -/* microSD Connector: - * - * ----------------- ----------------- ------------------------ - * SD/MMC CONNECTOR BOARD GPIO CONFIGURATION(s - * PIN SIGNAL SIGNAL (no remapping) - * --- ------------- ----------------- ------------------------- - * 1 DAT2/RES SD_D2/USART3_TX/ PC10 GPIO_SDIO_D2 - * SPI3_SCK - * 2 CD/DAT3/CS SD_D3/USART3_RX/ PC11 GPIO_SDIO_D3 - * SPI3_MISO - * 3 CMD/DI SD_CMD PD2 GPIO_SDIO_CMD - * 4 VDD N/A N/A - * 5 CLK/SCLK SD_CLK/SPI3_MOSI PC12 GPIO_SDIO_CK - * 6 VSS N/A N/A - * 7 DAT0/D0 SD_D0/DCMI_D2 PC8 GPIO_SDIO_D0 - * 8 DAT1/RES SD_D1/DCMI_D3 PC9 GPIO_SDIO_D1 - * --- ------------- ----------------- ------------------------- - * - * NOTES: - * 1. DAT4, DAT4, DAT6, and DAT7 not connected. - * 2. There are no alternative pin selections. - * 3. There is no card detect (CD) GPIO input so we will not - * sense if there is a card in the SD slot or not. This will - * make usage very awkward. - */ - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - NC (not connected) - * - PA0 is ETH_MII_CRS - NC - * - PA3 is ETH_MII_COL - NC - * - PB10 is ETH_MII_RX_ER - NC - * - PB0 is ETH_MII_RXD2 - NC - * - PH7 is ETH_MII_RXD3 - NC - * - PC3 is ETH_MII_TX_CLK - NC - * - PC2 is ETH_MII_TXD2 - NC - * - PB8 is ETH_MII_TXD3 - NC - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* USART6 - * - * DMAMAP_USART6_RX_1 = Channel 5, Stream1 - * DMAMAP_USART6_RX_2 = Channel 5, Stream2 - * DMAMAP_USART6_TX_1 = Channel 5, Stream6 - * DMAMAP_USART6_TX_2 = Channel 5, Stream7 - */ - -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 -#define DMAMAP_USART6_TX DMAMAP_USART6_TX_1 - -/* DHTxx pin configuration */ - -#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9) -#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN) -#define GPIO_DHTXX_PIN_INPUT (GPIO_INPUT|GPIO_FLOAT|GPIO_DHTXX_PIN) - -#define BOARD_DHTXX_GPIO_INPUT GPIO_DHTXX_PIN_INPUT -#define BOARD_DHTXX_GPIO_OUTPUT GPIO_DHTXX_PIN_OUTPUT -#define BOARD_DHTXX_FRTIMER 1 /* Free-run timer 1 */ - -/* SPI3 - As present in the UEXT header */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 - -/* I2S3 - CS4344 configuration uses I2S3 */ - -#define GPIO_I2S3_SD GPIO_I2S3_SD_1 -#define GPIO_I2S3_CK GPIO_I2S3_CK_1 -#define GPIO_I2S3_WS GPIO_I2S3_WS_2 -#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 - -#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 - -/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ - -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* FSMC SRAM */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile deleted file mode 100644 index 4590512f13460..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c deleted file mode 100644 index 9741858be5840..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs deleted file mode 100644 index c617c730ec81f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld deleted file mode 100644 index 75ab5f6cdf4a3..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld deleted file mode 100644 index 38a91fff9864f..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) - -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld deleted file mode 100644 index f877525caa1cc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 8Kb of SRAM. (See boards/stm32f4discovery/scripts/kernel-space.ld). - * Allowing additional memory permitis configuring debug instrumentation to - * be added to the kernel space without overflowing the partition. This could - * just as easily be set to 256Kb or even 512Kb. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000 (it cannot be positioned at 0x0800000 because vectors power-up - * reset vectors are places at the beginning of that range). If you change - * this address, don't forget to change the CONFIG_NUTTX_USERSPACE - * configuration setting to match and to modify the check in kernel/userspace.c. - * - * With 112Kb of SRAM a 64Kb user heap would seem possible but it is not in - * the current organization of SRAM memory (that could be changed with a - * little effort). The current ordering of SRAM is: (1) kernel .bss/.data, - * (2) user .bss/.data, (3) kernel heap (determined by CONFIG_MM_KERNEL_HEAPSIZE), - * and (4) the user heap. The maximum size of the user space heap is then - * limited to 32Kb beginning at address 0x20008000. - * - * Both of these alignment limitations could be reduced by using multiple - * regions to map the FLASH/SDRAM range or perhaps with some clever use of - * subregions or with multiple MPU regions per memory region. - * - * NOTE: The MPU is used in a mode where mappings are not required for - * kernel addresses and, hence, there are not alignment issues for those - * case. Only the user address spaces suffer from alignment requirements. - * However, in order to exploit this fact, we would still need to change - * the ordering of memory regions in SRAM. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x2000 0000: Kernel .data region. Typical size: 0.1KB - * ------ ---- Kernel .bss region. Typical size: 1.8KB - * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------ ---- Padded to 8KB - * 0x2000 2000: User .data region. Size is variable. - * ------ ---- User .bss region Size is variable. - * 0x2000 4000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. - * 0x2000 8000: Beginning of 32Kb user heap. - * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. - * 0x2001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K - usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K - xsram (rwx) : ORIGIN = 0x2000a000, LENGTH = 80K -} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld b/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld deleted file mode 100644 index c0c286e10c953..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt deleted file mode 100644 index f10df30fa1f73..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt +++ /dev/null @@ -1,61 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_sram.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_AUDIO_CS4344) - list(APPEND SRCS stm32_cs4344.c) -endif() - -if(CONFIG_INPUT_DJOYSTICK) - list(APPEND SRCS stm32_djoystick.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs b/boards/arm/stm32/olimex-stm32-p407/src/Make.defs deleted file mode 100644 index 8d0d261b5fb06..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-p407/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) - CSRCS += stm32_sram.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) - CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_ADC),y) - CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) - CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_AUDIO_CS4344),y) - CSRCS += stm32_cs4344.c -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) - CSRCS += stm32_djoystick.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c deleted file mode 100644 index 37fddf81d0e38..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 - * ADC123_IN10 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN10 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c deleted file mode 100644 index a77daaf0ea9ee..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define LED_STARTED_BITS (BOARD_LED1_BIT) -#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) -#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) -#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) -#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) -#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) -#define LED_PANIC_BITS (BOARD_LED4_BIT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const unsigned int g_ledbits[8] = -{ - LED_STARTED_BITS, - LED_HEAPALLOCATE_BITS, - LED_IRQSENABLED_BITS, - LED_STACKCREATED_BITS, - LED_INIRQ_BITS, - LED_SIGNAL_BITS, - LED_ASSERTION_BITS, - LED_PANIC_BITS -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | - BOARD_LED3_BIT | BOARD_LED4_BIT); - led_setbits(g_ledbits[led]); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_clrbits(g_ledbits[led]); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c deleted file mode 100644 index 77a521816a5cc..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "olimex-stm32-p407.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_STM32_FSMC - /* If the FSMC is enabled, then enable SRAM access */ - - stm32_stram_configure(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration - * and 2) disabled, and 3) the weak function stm32_usb_configure() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - stm32_usb_configure(); -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure on-board BUTTONs if BUTTON support has been selected. */ - -#ifdef CONFIG_ARCH_BUTTONS - board_button_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ - defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization here if so configured */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c deleted file mode 100644 index af02950de4527..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_MODULE -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_SENSORS_DHTXX -#include "stm32_dhtxx.h" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef HAVE_MODSYMS -extern const struct symtab_s MODSYMS_SYMTAB_ARRAY[]; -extern const int MODSYMS_NSYMBOLS_VAR; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef HAVE_MODSYMS - /* Install the module symbol table */ - - libelf_setsymtab(MODSYMS_SYMTAB_ARRAY, MODSYMS_NSYMBOLS_VAR); -#endif - -#ifdef HAVE_MMCSD - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(MMCSD_SLOTNO); - if (!sdio) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SDIO slot %d\n", - MMCSD_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(MMCSD_MINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - /* Then let's guess and say that there is a card in the slot. The Olimex - * STM32 P407 does not support a GPIO to detect if there is a card in - * the slot so we are reduced to guessing. - */ - - sdio_mediachange(sdio, true); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_setup() starts a thread - * will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_setup(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_DHTXX - ret = board_dhtxx_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dhtxx_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_CS4344 - /* Configure CS4344 audio */ - - ret = stm32_cs4344_initialize(1); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - ret = stm32_djoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c deleted file mode 100644 index a17716582e138..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c +++ /dev/null @@ -1,188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" - -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_TAMPER, - GPIO_BTN_WKUP, - - /* The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should - * be used by the discrete joystick driver. - */ - -#ifndef CONFIG_INPUT_DJOYSTICK - GPIO_JOY_RIGHT, - GPIO_JOY_UP, - GPIO_JOY_LEFT, - GPIO_JOY_DOWN, - GPIO_JOY_CENTER -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - /* Check that state of each key */ - - if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) - { - ret |= BUTTON_TAMPER_BIT; - } - - if (stm32_gpioread(g_buttons[BUTTON_WKUP])) - { - ret |= BUTTON_WKUP_BIT; - } - -#ifndef CONFIG_INPUT_DJOYSTICK - if (stm32_gpioread(g_buttons[JOYSTICK_RIGHT])) - { - ret |= JOYSTICK_RIGHT_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_UP])) - { - ret |= JOYSTICK_UP_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_LEFT])) - { - ret |= JOYSTICK_LEFT_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_DOWN])) - { - ret |= JOYSTICK_DOWN_BIT; - } - - if (stm32_gpioread(g_buttons[JOYSTICK_CENTER])) - { - ret |= JOYSTICK_CENTER_BIT; - } -#endif - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c deleted file mode 100644 index 71bc50e3bc67e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_can.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c deleted file mode 100644 index 4f96e0bff419e..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t - djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-P407 joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialize - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c deleted file mode 100644 index 75b6ec8f9723c..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "olimex-stm32-p407.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the olimex - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - stm32_configgpio(GPIO_ST7735_CS); -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a call to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_LCD_ST7735 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_ST7735_CS, !selected); - } -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - -#ifdef CONFIG_LCD_ST7735 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_ST7735_AO, !cmd); - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c deleted file mode 100644 index a21739968a7c6..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c +++ /dev/null @@ -1,330 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "olimex-stm32-p407.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_OLIMEXP407_USBHOST_PRIO -# define CONFIG_OLIMEXP407_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_OLIMEXP407_USBHOST_STACKSIZE -# define CONFIG_OLIMEXP407_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_usb_configure very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_setup - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_setup(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO, - CONFIG_OLIMEXP407_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c deleted file mode 100644 index 2a7ceec92a30a..0000000000000 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include "stm32.h" -#include "olimex-stm32-p407.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/CMakeLists.txt deleted file mode 100644 index bf93e02b885aa..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig deleted file mode 100644 index 95cf7656244e4..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_RESET=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_NSH_NESTDEPTH=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig deleted file mode 100644 index 8a01242f25bbf..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ /dev/null @@ -1,132 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_CDCACM_NRDREQS=2 -CONFIG_CDCACM_NWRREQS=2 -CONFIG_CDCACM_RXBUFSIZE=96 -CONFIG_CDCACM_TXBUFSIZE=96 -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MMCSD=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_BKP=y -CONFIG_STM32_CRC=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 -CONFIG_USART2_RXBUFSIZE=32 -CONFIG_USART2_TXBUFSIZE=32 -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_SCSI_STACKSIZE=340 -CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig deleted file mode 100644 index fbbcff77f4c10..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ /dev/null @@ -1,113 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FAT_MAXFNAME=12 -CONFIG_FILE_STREAM=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_NAMED_SEMAPHORES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MMCSD=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_BKP=y -CONFIG_STM32_CRC=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_I2C2=y -CONFIG_STM32_I2C_DUTY16_9=y -CONFIG_STM32_I2C_DYNTIMEO=y -CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 -CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 -CONFIG_USART2_RXBUFSIZE=32 -CONFIG_USART2_TXBUFSIZE=32 -CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig deleted file mode 100644 index 7687414c781bf..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=40 -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_CODECS_BUFSIZE=0 -CONFIG_NSH_FILEIOSIZE=128 -CONFIG_NSH_NESTDEPTH=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=758 -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig deleted file mode 100644 index 35eb903db23cd..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="olimexino-stm32" -CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103RB=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_INTERRUPTSTACK=340 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_EXTID=y -CONFIG_CAN_LOOPBACK=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_CAN=y -CONFIG_FDCLONE_DISABLE=y -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=300 -CONFIG_INIT_ENTRYPOINT="can_main" -CONFIG_INIT_STACKSIZE=880 -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_SMALL=y -CONFIG_NAME_MAX=8 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_PTHREAD_STACK_DEFAULT=464 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKSTACKSIZE=758 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKSTACKSIZE=768 -CONFIG_STACK_COLORATION=y -CONFIG_START_YEAR=2014 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_REMAP1=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_FLOWCONTROL_BROKEN=y -CONFIG_STM32_FORCEPOWER=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PARTIAL_REMAP=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_PARTIAL_REMAP=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_USART1_RXBUFSIZE=32 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32/olimexino-stm32/include/board.h b/boards/arm/stm32/olimexino-stm32/include/board.h deleted file mode 100644 index 219e6256517b7..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/include/board.h +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* Buttons ******************************************************************/ - -#define BUTTON_BOOT0_BIT (0) -#define BUTTON_BOOT0_MASK (1< flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu deleted file mode 100644 index 5cb7d690bfac1..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Don't know if this is correct. Just 256K-48K (not tested) */ -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt deleted file mode 100644 index 9457b7258b78a..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_leds.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/olimexino-stm32/src/Make.defs b/boards/arm/stm32/olimexino-stm32/src/Make.defs deleted file mode 100644 index 65205d7152800..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/Make.defs +++ /dev/null @@ -1,49 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimexino-stm32/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_leds.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c b/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c deleted file mode 100644 index b4d93ced9dc22..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifdef CONFIG_USBDEV -# include "stm32_usbdev.h" -#endif - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: vbus_handler - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) -static int vbus_handler(int irq, void *context, void *arg) -{ - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - stm32_led_initialize(); -#endif - -#ifdef CONFIG_ARCH_BUTTONS - /* Configure on-board buttons. */ - - board_button_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = OK; - -#ifdef CONFIG_USBMSC -#if !defined(CONFIG_NSH_BUILTIN_APPS) && !defined(CONFIG_SYSTEM_USBMSC) - ret = board_usbmsc_initialize(0); -#endif -#endif - -#if !defined(CONFIG_NSH_BUILTIN_APPS) && defined(CONFIG_USBDEV_COMPOSITE) - ret = board_composite_initialize(0); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - -#if defined(CONFIG_USBDEV) - stm32_usb_set_pwr_callback(vbus_handler); -#endif -} -#endif diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c b/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c deleted file mode 100644 index 026ef07e68ef3..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "olimexino-stm32.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(BUTTON_BOOT0N); - return 1; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. - * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - return stm32_gpioread(BUTTON_BOOT0N) ? 0 : BUTTON_BOOT0_MASK; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id == IRQBUTTON) - { - ret = stm32_gpiosetevent(BUTTON_BOOT0N, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c b/boards/arm/stm32/olimexino-stm32/src/stm32_can.c deleted file mode 100644 index 64164af8b235a..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#include "olimexino-stm32.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c deleted file mode 100644 index dbc418009f57f..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c +++ /dev/null @@ -1,448 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/* There is nothing to do here if SPI support is not selected. */ - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* No SPI? Then no USB MSC device in composite */ - -#ifndef CONFIG_STM32_SPI -# undef CONFIG_USBMSC_COMPOSITE -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 -# undef OLIMEXINO_STM32_MMCSDSLOTNO -# define OLIMEXINO_STM32_MMCSDSLOTNO 0 -# undef OLIMEXINO_STM32_MMCSDSPIPORTNO -# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. This is just an - * application specific wrapper aboutn usbmsc_unitialize() that is called - * form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - DEBUGASSERT(g_mschandle != NULL); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[0]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[0].classobject = cdcacm_classobject; - dev[0].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[0].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[0].devinfo.ninterfaces; - strbase += dev[0].devinfo.nstrings; - - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[1]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[1].classobject = board_mscclassobject; - dev[1].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[1].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; - dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; - - /* Count up the base numbers */ - - ifnobase += dev[1].devinfo.ninterfaces; - strbase += dev[1].devinfo.nstrings; - - return composite_initialize(composite_getdevdescs(), dev, 2); -} -#endif - -/**************************************************************************** - * Name: board_composite1_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 1. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite1_connect(int port) -{ - /* REVISIT: This configuration currently fails. stm32_epallocpma() fails - * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte - * buffers, two required for EP0, leaving only buffers for 5 additional - * endpoints. - */ - -#if 0 - struct composite_devdesc_s dev[2]; - int strbase = COMPOSITE_NSTRIDS; - int ifnobase = 0; - int epno; - int i; - - for (i = 0, epno = 1; i < 2; i++) - { - /* Ask the cdcacm driver to fill in the constants we didn't know here */ - - cdcacm_get_composite_devdesc(&dev[i]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[i].classobject = cdcacm_classobject; - dev[i].uninitialize = cdcacm_uninitialize; - - dev[i].minor = i; /* The minor interface number */ - - /* Interfaces */ - - dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - - /* Strings */ - - dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; - - ifnobase += dev[i].devinfo.ninterfaces; - strbase += dev[i].devinfo.nstrings; - } - - return composite_initialize(composite_getdevdescs(), dev, 2); -#else - return NULL; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - /* If system/composite is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - - struct spi_dev_s *spi; - int ret; - - /* First, get an instance of the SPI interface */ - - syslog(LOG_INFO, "Initializing SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - /* Now bind the SPI interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=0 slot=%d\n", - OLIMEXINO_STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(0, OLIMEXINO_STM32_MMCSDSLOTNO, spi); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port %d to MMC/SD minor=0 slot=%d %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO, OLIMEXINO_STM32_MMCSDSLOTNO, - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { -#ifdef CONFIG_USBMSC_COMPOSITE - return board_composite0_connect(port); -#else - return NULL; -#endif - } - else if (configid == 1) - { - return board_composite1_connect(port); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c b/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c deleted file mode 100644 index f0a2df6beffd9..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c +++ /dev/null @@ -1,183 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Dump GPIO registers */ - -#ifdef CONFIG_DEBUG_LEDS_INFO -# define led_dumpgpio(m) stm32_dumpgpio(GPIO_LED_GREEN, m) -#else -# define led_dumpgpio(m) -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -static bool g_initialized = false; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize/board_userled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -uint32_t stm32_led_initialize(void) -#else -uint32_t board_userled_initialize(void) -#endif -{ - /* Configure all LED GPIO lines */ - - led_dumpgpio("board_*led_initialize() Entry)"); - - stm32_configgpio(GPIO_LED_YELLOW); - stm32_configgpio(GPIO_LED_GREEN); - - led_dumpgpio("board_*led_initialize() Exit"); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -#ifndef CONFIG_ARCH_LEDS -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED_GREEN) - { - stm32_gpiowrite(GPIO_LED_GREEN, !ledon); - } - else if (led == BOARD_LED_YELLOW) - { - stm32_gpiowrite(GPIO_LED_YELLOW, !ledon); - } -} -#endif - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -#ifndef CONFIG_ARCH_LEDS -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_LED_YELLOW_BIT) == 0); - stm32_gpiowrite(GPIO_LED_YELLOW, (ledset & BOARD_LED_YELLOW_BIT) == 0); -} -#endif - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_on(int led) -{ - switch (led) - { - default: - case LED_STARTED: - case LED_HEAPALLOCATE: - case LED_IRQSENABLED: - stm32_gpiowrite(GPIO_LED_GREEN, false); - stm32_gpiowrite(GPIO_LED_YELLOW, false); - break; - - case LED_STACKCREATED: - stm32_gpiowrite(GPIO_LED_GREEN, true); - stm32_gpiowrite(GPIO_LED_YELLOW, false); - g_initialized = true; - break; - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - stm32_gpiowrite(GPIO_LED_YELLOW, true); - break; - - case LED_IDLE : /* IDLE */ - stm32_gpiowrite(GPIO_LED_GREEN, false); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_off(int led) -{ - switch (led) - { - default: - case LED_STARTED: - case LED_HEAPALLOCATE: - case LED_IRQSENABLED: - case LED_STACKCREATED: - stm32_gpiowrite(GPIO_LED_GREEN, false); - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - stm32_gpiowrite(GPIO_LED_YELLOW, false); - break; - - case LED_IDLE: /* IDLE */ - stm32_gpiowrite(GPIO_LED_GREEN, g_initialized); - break; - } -} -#endif diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c b/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c deleted file mode 100644 index 43053e5ccbe0d..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include "chip.h" -#include "stm32.h" -#include "olimexino-stm32.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* Setup CS */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(USER_CSN); -#endif - -#ifdef CONFIG_STM32_SPI2 - stm32_configgpio(MMCSD_CSN); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - if (devid == SPIDEV_USER(0)) - { - stm32_gpiowrite(USER_CSN, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -#if defined(CONFIG_MMCSD) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(MMCSD_CSN, !selected); - } -#endif -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - /* No switch on SD card socket so assume it is here */ - - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c b/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c deleted file mode 100644 index da1a423330fde..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_set_pwr_callback() - * - * Description: - * Input Parameters: - * pwr_changed_handler: An interrupt handler that will be called on VBUS - * power state changes. - * - ****************************************************************************/ - -void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler) -{ - stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, - pwr_changed_handler, NULL); -} - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUPN); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can - * be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUPN, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c b/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c deleted file mode 100644 index 8af999fdb60fb..0000000000000 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "olimexino-stm32.h" - -/* There is nothing to do here if SPI support is not selected. */ - -#ifdef CONFIG_STM32_SPI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 -# undef OLIMEXINO_STM32_MMCSDSLOTNO -# define OLIMEXINO_STM32_MMCSDSLOTNO 0 -# undef OLIMEXINO_STM32_MMCSDSPIPORTNO -# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - - struct spi_dev_s *spi; - int ret; - - /* First, get an instance of the SPI interface */ - - syslog(LOG_INFO, "Initializing SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO); - - /* Now bind the SPI interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=%d slot=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1, OLIMEXINO_STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, - OLIMEXINO_STM32_MMCSDSLOTNO, spi); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port %d to MMC/SD minor=%d slot=%d %d\n", - OLIMEXINO_STM32_MMCSDSPIPORTNO, CONFIG_SYSTEM_USBMSC_DEVMINOR1, - OLIMEXINO_STM32_MMCSDSLOTNO, ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); - - return OK; -} - -#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32/omnibusf4/CMakeLists.txt b/boards/arm/stm32/omnibusf4/CMakeLists.txt deleted file mode 100644 index bf326c7306af0..0000000000000 --- a/boards/arm/stm32/omnibusf4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig deleted file mode 100644 index ad1678e330e08..0000000000000 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ /dev/null @@ -1,123 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="omnibusf4" -CONFIG_ARCH_BOARD_OMNIBUSF4=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F405RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_IOCTL=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_URANDOM=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_EXAMPLES_LEDS=y -CONFIG_EXAMPLES_LEDS_LEDSET=0x1 -CONFIG_EXAMPLES_LEDS_STACKSIZE=512 -CONFIG_EXAMPLES_PWM=y -CONFIG_EXAMPLES_SERIALRX=y -CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_NCHAINS=8 -CONFIG_LIBC_HOSTNAME="omnibusf4" -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_M25P_SPIFREQUENCY=75000000 -CONFIG_MMCSD=y -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_MPU60X0_EXTI=y -CONFIG_MTD=y -CONFIG_MTD_M25P=y -CONFIG_MTD_SECT512=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=2 -CONFIG_NSH_PROMPT_STRING="omnibusf4> " -CONFIG_NSH_READLINE=y -CONFIG_PIPES=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MPU60X0=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMDATARAM=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_TIM10=y -CONFIG_STM32_TIM12=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH3OUT=y -CONFIG_STM32_TIM2_CH4OUT=y -CONFIG_STM32_TIM2_CHANNEL3=y -CONFIG_STM32_TIM2_CHANNEL4=y -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CH4OUT=y -CONFIG_STM32_TIM3_CHANNEL3=y -CONFIG_STM32_TIM3_CHANNEL4=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM5=y -CONFIG_STM32_TIM8=y -CONFIG_STM32_TIM9=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART3=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_ZMODEM=y -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_DMA=y -CONFIG_USBDEV_DUALSPEED=y -CONFIG_USBDEV_MAXPOWER=500 -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y -CONFIG_VIDEO_MAX7456=y -CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32/omnibusf4/include/board.h b/boards/arm/stm32/omnibusf4/include/board.h deleted file mode 100644 index 89ac84283a104..0000000000000 --- a/boards/arm/stm32/omnibusf4/include/board.h +++ /dev/null @@ -1,262 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The OMNIBUSF4 board uses a single 8MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator - * output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for - * USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* Pin configurations *******************************************************/ - -#define BOARD_NLEDS 2 /* One literal LED, one beeper */ -#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5) -#define GPIO_BEEPER1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTB|GPIO_PIN4) - -/* USART1: */ - -#if 0 -#define INVERTER_PIN_USART1 PC0 /* DYS F4 Pro, Omnibus F4 AIO 1st Gen only */ -#endif -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ - -/* USART2: - * - * TODO: Do OMNIBUSF4 targets use USART2? - */ - -/* USART3: */ - -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ - -/* USART4: */ - -/* USART6: */ - -#if 0 -#define INVERTER_PIN_UART6 PC8 /* Omnibus F4 V3 and later, EXUAVF4PRO */ -#endif -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - motor outputs, etc. are on these pins: */ - -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S1_OUT PB0 */ -#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz) /* S2_OUT PB1 */ -#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) /* S3_OUT PA3 */ -#define GPIO_TIM2_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S4_OUT PA2 */ - -/* SPI1 : - * - * MPU6000 6-axis motion sensor (accelerometer + gyroscope), or - * MPU6500 6-Axis MEMS MotionTracking Device with DMP - * - * MPU6000 interrupts - * #define USE_GYRO_EXTI - * #define GYRO_1_EXTI_PIN PC4 - * #define USE_MPU_DATA_READY_SIGNAL - * - * #define GYRO_1_ALIGN CW270_DEG - * #define ACC_1_ALIGN CW270_DEG - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ -#if 0 -#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_2|GPIO_SPEED_50MHz) /* PA4 */ -#endif -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 /* 2:0:3 */ -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 /* 2:3:3 */ - -/* SPI2 : - * - * Used for MMC/SD on OMNIBUSF4SD. - */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PB14 */ -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PB15 */ -#define GPIO_SPI2_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX /* 1:3:0 */ -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX /* 1:4:0 */ - -#define GPIO_MMCSD_NSS GPIO_SPI2_NSS -#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ - GPIO_PORTB | GPIO_PIN7) /* PB7 SD_DET */ - -/* SPI3 : - * - * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 - * (? BF code says "PB3"). - * define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4 - * - * Barometer and/or MAX7456, depending on the target. - * (OMNIBUSF4BASE targets appear to have a cyrf6936 device.) - */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PC11 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PC12 */ -#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_1|GPIO_SPEED_50MHz) /* PA15 */ /* TODO: doesn't work like a chip select */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ - -#if 0 -/* I2C : */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#endif - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/omnibusf4/kernel/Makefile b/boards/arm/stm32/omnibusf4/kernel/Makefile deleted file mode 100644 index 75b08bc56a65b..0000000000000 --- a/boards/arm/stm32/omnibusf4/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c deleted file mode 100644 index 4f26f3b6fa7b2..0000000000000 --- a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/omnibusf4/scripts/Make.defs b/boards/arm/stm32/omnibusf4/scripts/Make.defs deleted file mode 100644 index fb493131e67b4..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld b/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld deleted file mode 100644 index 05813d380150b..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/scripts/ld.script b/boards/arm/stm32/omnibusf4/scripts/ld.script deleted file mode 100644 index a4e200f91e90e..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -EXTERN(_vectors) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/scripts/memory.ld b/boards/arm/stm32/omnibusf4/scripts/memory.ld deleted file mode 100644 index ff462c1e469af..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/omnibusf4/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/omnibusf4/scripts/user-space.ld b/boards/arm/stm32/omnibusf4/scripts/user-space.ld deleted file mode 100644 index 83c52fe4f9f96..0000000000000 --- a/boards/arm/stm32/omnibusf4/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32/omnibusf4/src/CMakeLists.txt deleted file mode 100644 index 9be173575b5ee..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt +++ /dev/null @@ -1,83 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c) - -if(CONFIG_SENSORS_MPU60X0) - list(APPEND SRCS stm32_mpu6000.c) -endif() - -if(CONFIG_VIDEO_MAX7456) - list(APPEND SRCS stm32_max7456.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_NETDEVICES) - list(APPEND SRCS stm32_netinit.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_BOARDCTL_IOCTL) - list(APPEND SRCS stm32_ioctl.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/omnibusf4/src/Make.defs b/boards/arm/stm32/omnibusf4/src/Make.defs deleted file mode 100644 index 6fa1d9b08b85a..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/Make.defs +++ /dev/null @@ -1,84 +0,0 @@ -############################################################################ -# boards/arm/stm32/omnibusf4/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c - -ifeq ($(CONFIG_SENSORS_MPU60X0),y) -CSRCS += stm32_mpu6000.c -endif - -ifeq ($(CONFIG_VIDEO_MAX7456),y) -CSRCS += stm32_max7456.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) -CSRCS += stm32_ioctl.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/omnibusf4/src/stm32_boot.c b/boards/arm/stm32/omnibusf4/src/stm32_boot.c deleted file mode 100644 index 651df187d8134..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_boot.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "omnibusf4.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the - * 1) OTG FS controller is in the configuration and - * 2) disabled, and - * 3) the weak function stm32_usbinitialize() has been brought into the - * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef HAVE_NETMONITOR - /* Configure board resources to support networking. */ - - if (stm32_netinitialize) - { - stm32_netinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef HAVE_CCM_HEAP - /* Initialize CCM allocator */ - - ccm_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32/omnibusf4/src/stm32_bringup.c deleted file mode 100644 index bbda6f831f851..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c +++ /dev/null @@ -1,292 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32_romfs.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#include "omnibusf4.h" - -/* Conditional logic in omnibusf4.h will determine if certain features - * are supported. Tests for these features need to be made after including - * omnibusf4.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_INITIALIZE=y : - * Called from board_initialize(). - * - * CONFIG_BOARD_INITIALIZE=n && CONFIG_BOARDCTL=y : - * Called from the NSH library - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - uerr("ERROR: Failed to start USB monitor: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - /* Our MMC/SD port is on SPI2. */ - - ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - -#ifdef CONFIG_PWM - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MPU60X0 - /* Initialize the MPU6000 device. */ - - ret = stm32_mpu6000_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mpu6000_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_MAX7456 - /* Initialize the MAX7456 OSD device. */ - - ret = stm32_max7456_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_max7456_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; - } - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - /* Initialize and mount ROMFS. */ - - ret = stm32_romfs_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#if defined(CONFIG_RNDIS) - /* Set up a MAC address for the RNDIS device. */ - - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - - return ret; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_idle.c b/boards/arm/stm32/omnibusf4/src/stm32_idle.c deleted file mode 100644 index a21bc28cff65b..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_idle.c +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c b/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c deleted file mode 100644 index 2d6e436022ad2..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - /* TODO: media change callback */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int port, int minor) -{ - struct spi_dev_s *spi; - int rv; - - stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ - - mcinfo("INFO: Initializing mmcsd port %d minor %d SD_DET %x\n", - port, minor, stm32_gpioread(GPIO_MMCSD_NCD)); - - spi = stm32_spibus_initialize(port); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", port); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, minor, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - port, minor); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c b/boards/arm/stm32/omnibusf4/src/stm32_netinit.c deleted file mode 100644 index 459c12b540ffb..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_netinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pm.c b/boards/arm/stm32/omnibusf4/src/stm32_pm.c deleted file mode 100644 index 1192f27edccda..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "omnibusf4.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pm_buttons(); -#endif - - /* Initialize the LED PM */ - - stm32_led_pminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32/omnibusf4/src/stm32_pwm.c deleted file mode 100644 index 110d82016bbb3..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "omnibusf4.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * - * Initialize PWM and register Omnibus F4's TIM2 and TIM3 PWM devices: - * - * TIM3 CH3 PB0 S1_OUT - * TIM3 CH4 PB1 S2_OUT - * TIM2 CH4 PA3 S3_OUT - * TIM2 CH3 PA2 S4_OUT - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - int npwm = 0; /* hardware device enumerator */ - const char *ppwm = NULL; /* pointer to PWM device name */ - struct pwm_lowerhalf_s *pwm = NULL; /* lower-half driver handle */ - - /* Initialize TIM2 and TIM3. - * - * Ihe underlying STM32 driver "knows" there are up to four channels - * available for each timer device, so we don't have to do anything - * special here to export the two channels each that we're - * interested in. The user will want to avoid the channels that - * aren't connected to anything, however, or risk death by boredom - * from resulting non-response. - */ - - for (npwm = 2; npwm <= 3; npwm++) - { - pwm = stm32_pwminitialize(npwm); - - /* If we can't get the lower-half handle, skip and keep going. */ - - if (!pwm) - { - continue; - } - - /* Translate the peripheral number to a device name. */ - - switch (npwm) - { - case 2: - ppwm = "/dev/pwm2"; - break; - - case 3: - ppwm = "/dev/pwm3"; - break; - - /* Skip missing names. */ - - default: - continue; - } - - pwm_register(ppwm, pwm); - } - - return 0; -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_reset.c b/boards/arm/stm32/omnibusf4/src/stm32_reset.c deleted file mode 100644 index 9ce6cdc4963ca..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_reset.c +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32_dfumode.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int board_reset(int mode) -{ - if (mode == 0) - { - /* Normal reset */ - - up_systemreset(); - } - else - { - /* DFU reset */ - - stm32_dfumode(); - } -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32/omnibusf4/src/stm32_romfs.h deleted file mode 100644 index a626fd2ac2731..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c deleted file mode 100644 index 3111816d8ef3c..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_spi.c b/boards/arm/stm32/omnibusf4/src/stm32_spi.c deleted file mode 100644 index 525a8781df7ba..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_spi.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "omnibusf4.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the omnibusf4 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_CS_MPU6000); - stm32_configgpio(GPIO_EXTI_MPU6000); -#endif -#ifdef CONFIG_STM32_SPI3 - stm32_configgpio(GPIO_CS_MAX7456); -#endif -#if defined(CONFIG_MMCSD_SPI) - stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: CS is active-low. */ - - stm32_gpiowrite(GPIO_CS_MPU6000, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: NSS is active-low. */ - - stm32_gpiowrite(GPIO_MMCSD_NSS, selected ? 0 : 1); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - /* Note: SD_DET is pulled high when there's no SD card present. */ - - return stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* Note: MAX7456 CS is active-low. */ - - stm32_gpiowrite(GPIO_CS_MAX7456, selected ? 0 : 1); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_timer.c b/boards/arm/stm32/omnibusf4/src/stm32_timer.c deleted file mode 100644 index 0d6e5b1b5d371..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_timer.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "omnibusf4.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_uid.c b/boards/arm/stm32/omnibusf4/src/stm32_uid.c deleted file mode 100644 index 892821fa4536f..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usb.c b/boards/arm/stm32/omnibusf4/src/stm32_usb.c deleted file mode 100644 index 94f60081162c0..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_usb.c +++ /dev/null @@ -1,338 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "omnibusf4.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_OMNIBUSF4_USBHOST_PRIO -# define CONFIG_OMNIBUSF4_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_OMNIBUSF4_USBHOST_STACKSIZE -# define CONFIG_OMNIBUSF4_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Omnibusf4 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_OMNIBUSF4_USBHOST_PRIO, - CONFIG_OMNIBUSF4_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c b/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c deleted file mode 100644 index b3c093ab6a166..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c b/boards/arm/stm32/omnibusf4/src/stm32_userleds.c deleted file mode 100644 index 2d624f27610fe..0000000000000 --- a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "omnibusf4.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, - GPIO_BEEPER1 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) - { - stm32_configgpio(g_ledcfg[wled]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) - { - stm32_gpiowrite(g_ledcfg[wled], - (ledset & (1 << wled)) == 0 ? 1 : 0); - } -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/CMakeLists.txt b/boards/arm/stm32/photon/CMakeLists.txt deleted file mode 100644 index 2bb4205c977cb..0000000000000 --- a/boards/arm/stm32/photon/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/photon/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig deleted file mode 100644 index 7291e7e2ddea9..0000000000000 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ADBD_AUTHENTICATION=y -CONFIG_ADBD_AUTH_PUBKEY=y -CONFIG_ADBD_DEVICE_ID="serialno" -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_LOGCAT_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEV_URANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="adbd_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=2048 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32/photon/configs/nsh/defconfig deleted file mode 100644 index e1c4b317d0a28..0000000000000 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig deleted file mode 100644 index bc62471ce2024..0000000000000 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=8192 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RGBLED_INVERT=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWM_MULTICHAN=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CH3OUT=y -CONFIG_STM32_TIM2_CH4OUT=y -CONFIG_STM32_TIM2_CHANNEL2=y -CONFIG_STM32_TIM2_CHANNEL3=y -CONFIG_STM32_TIM2_CHANNEL4=y -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32/photon/configs/usbnsh/defconfig deleted file mode 100644 index 7349032a1c81d..0000000000000 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/photon/configs/wlan-perf/defconfig b/boards/arm/stm32/photon/configs/wlan-perf/defconfig deleted file mode 100644 index c4d498634d86b..0000000000000 --- a/boards/arm/stm32/photon/configs/wlan-perf/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DFU_BASE=0x8020000 -CONFIG_DFU_BINARY=y -CONFIG_DFU_PID=0xd006 -CONFIG_DFU_VID=0x2b04 -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=32 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PHOTON_WLAN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32/photon/configs/wlan/defconfig deleted file mode 100644 index ac6ceaea97fd8..0000000000000 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ /dev/null @@ -1,100 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_IEEE80211_BROADCOM_FWFILES is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="photon" -CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F205RG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DFU_BASE=0x8020000 -CONFIG_DFU_BINARY=y -CONFIG_DFU_PID=0xd006 -CONFIG_DFU_VID=0x2b04 -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IEEE80211_BROADCOM_BCM43362=y -CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 -CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=16 -CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y -CONFIG_MM_REGIONS=2 -CONFIG_NDEBUG=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1518 -CONFIG_NET_GUARDSIZE=32 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_PKT=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PHOTON_DFU_BOOTLOADER=y -CONFIG_PHOTON_IWDG=y -CONFIG_PHOTON_WDG_THREAD=y -CONFIG_PHOTON_WLAN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SDIO_BLOCKSETUP=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA2=y -CONFIG_STM32_IWDG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_BUFFER=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_CONSOLE=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSLOG_INTBUFFER=y -CONFIG_SYSLOG_PROCESSID=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32/photon/include/board.h b/boards/arm/stm32/photon/include/board.h deleted file mode 100644 index 6c5ac34d01c1e..0000000000000 --- a/boards/arm/stm32/photon/include/board.h +++ /dev/null @@ -1,311 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The Particle photon board features a single 26MHz crystal. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) - * PLLM : 26 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG HS : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 26MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 26000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (26,000,000 / 26) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* USB OTG HS definitions ***************************************************/ - -/* Do not enable external PHY clock or OTG_HS module will not work */ - -#undef BOARD_ENABLE_USBOTG_HSULPI - -/* LED definitions **********************************************************/ - -/* LEDs - * - * A single LED is available driven by PA13. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ---------------------------- ------ - * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ - */ - -#define LED_STARTED 0 /* NuttX has been started OFF */ -#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ -#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ -#define LED_STACKCREATED 1 /* Idle stack created ON */ -#define LED_INIRQ 2 /* In an interrupt N/C */ -#define LED_SIGNAL 2 /* In a signal handler N/C */ -#define LED_ASSERTION 2 /* An assertion failed N/C */ -#define LED_PANIC 3 /* The system has crashed FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* Thus if LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) - -/* RGB LED - * - * R = TIM2 CH2 on PA1 | G = TIM2 CH3 on PA2 | B = TIM4 CH4 on PA3 - * - * Note: Pin boards: GPIO_TIM2_CH2OUT ; GPIO_TIM2_CH3OUT ; GPIO_TIM2_CH4OUT - */ - -#define RGBLED_RPWMTIMER 2 -#define RGBLED_RPWMCHANNEL 2 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 3 -#define RGBLED_BPWMTIMER 2 -#define RGBLED_BPWMCHANNEL 4 - -/* Button definitions *******************************************************/ - -#define BOARD_BUTTON1 0 -#define NUM_BUTTONS 1 -#define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) - -/* Alternate function pin selections ****************************************/ - -/* UART1 */ - -#ifdef CONFIG_STM32_USART1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) -#endif - -/* SPI1 */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ - -/* SPI3 */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) /* PB4 */ -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) /* PB5 */ -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) /* PB3 */ - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* OTG HS */ - -#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 -#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 - -/* SDIO definitions *********************************************************/ - -/* Note that slower clocking is required when DMA is disabled in order - * to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. - * - * These values have not been tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -#endif /* __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/photon/scripts/Make.defs b/boards/arm/stm32/photon/scripts/Make.defs deleted file mode 100644 index 12f4622680f7f..0000000000000 --- a/boards/arm/stm32/photon/scripts/Make.defs +++ /dev/null @@ -1,68 +0,0 @@ -############################################################################ -# boards/arm/stm32/photon/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) -LDSCRIPT = photon_dfu.ld -else -LDSCRIPT = photon_jtag.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -# See http://dfu-util.sourceforge.net/ - -DFUSUFFIX = dfu-suffix -DFUUTIL = dfu-util - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -ifeq ($(CONFIG_DFU_BINARY),y) - -define FLASH - $(Q) echo "DFUSUFFIX: $(1).dfu" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(1) $(1).dfu - $(Q) $(DFUSUFFIX) -v $(subst 0x,,$(CONFIG_DFU_VID)) -p $(subst 0x,,$(CONFIG_DFU_PID)) -a $(1).dfu - $(Q) $(DFUUTIL) -d $(CONFIG_DFU_VID):$(CONFIG_DFU_PID) -a 0 -s $(CONFIG_DFU_BASE) -D $(1).dfu -endef - -else - -define FLASH - $(Q) $(ECHO) "Photon firmware upload through JTAG is not supported" -endef - -endif diff --git a/boards/arm/stm32/photon/src/CMakeLists.txt b/boards/arm/stm32/photon/src/CMakeLists.txt deleted file mode 100644 index e6e55c00a003c..0000000000000 --- a/boards/arm/stm32/photon/src/CMakeLists.txt +++ /dev/null @@ -1,68 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/photon/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_PHOTON_DFU_BOOTLOADER) - list(APPEND SRCS dfu_signature.c) -endif() - -if(CONFIG_INPUT_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_PHOTON_WDG) - list(APPEND SRCS stm32_wdt.c) -endif() - -if(CONFIG_PHOTON_WLAN) - list(APPEND SRCS stm32_wlan.c) - list(APPEND SRCS stm32_wlan_firmware.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_PHOTON_DFU_BOOTLOADER) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/photon_dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/photon_jtag.ld") -endif() diff --git a/boards/arm/stm32/photon/src/Make.defs b/boards/arm/stm32/photon/src/Make.defs deleted file mode 100644 index 6edf5dce2d9a9..0000000000000 --- a/boards/arm/stm32/photon/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/photon/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) -CSRCS += dfu_signature.c -endif - -ifeq ($(CONFIG_INPUT_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_PHOTON_WDG),y) -CSRCS += stm32_wdt.c -endif - -ifeq ($(CONFIG_PHOTON_WLAN),y) -CSRCS += stm32_wlan.c -CSRCS += stm32_wlan_firmware.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/photon/src/stm32_autoleds.c b/boards/arm/stm32/photon/src/stm32_autoleds.c deleted file mode 100644 index f78cd9a89a0af..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_autoleds.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* LEDs - * - * A single LED is available driven by PA13. - * - * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_autoleds.c. The LEDs are used to encode - * OS-related events as follows: - * - * ------------------- ----------------------- ------ - * SYMBOL Meaning LED - * ------------------- ----------------------- ------ - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt N/C - * LED_SIGNAL In a signal handler N/C - * LED_ASSERTION An assertion failed N/C - * LED_PANIC The system has crashed FLASH - * - * Thus is LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If LED is flashing at approximately - * 2Hz, then a fatal error has been detected and the system has halted. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "photon.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure Photon LED gpio as output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1 || led == 3) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 3) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_boot.c b/boards/arm/stm32/photon/src/stm32_boot.c deleted file mode 100644 index 631df3142d6a5..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_boot.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "arm_internal.h" -#include "photon.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the - * 1) OTG HS controller is in the configuration and - * 2) disabled, and - * 3) the weak function stm32_usbinitialize() has been brought into - * the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board initialization */ - - stm32_bringup(); -} -#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32/photon/src/stm32_bringup.c b/boards/arm/stm32/photon/src/stm32_bringup.c deleted file mode 100644 index 5096dad8d0b5b..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_bringup.c +++ /dev/null @@ -1,167 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include - -#include "photon.h" -#include "stm32_wdg.h" - -#ifdef CONFIG_USBADB -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * This function initializes and configures all on-board features - * appropriate for the selected configuration. - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#ifdef CONFIG_STM32_IWDG - /* Initialize the watchdog timer */ - - stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); -#endif - -#ifdef CONFIG_PHOTON_WDG - /* Start WDG kicker thread */ - - ret = photon_watchdog_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to start watchdog thread: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PHOTON_WLAN - /* Initialize wlan driver and hardware */ - - ret = photon_wlan_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_USBDEV_COMPOSITE - -#ifndef CONFIG_BOARDCTL_USBDEVCTRL - ret = board_composite_initialize(0); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to initialize composite: %d\n", ret); - return ret; - } - - if (board_composite_connect(0, 0) == NULL) - { - syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); - return ret; - } -#endif /* !CONFIG_BOARDCTL_USBDEVCTRL */ -#else -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif -#endif /* CONFIG_USBDEV_COMPOSITE */ - return ret; -} diff --git a/boards/arm/stm32/photon/src/stm32_buttons.c b/boards/arm/stm32/photon/src/stm32_buttons.c deleted file mode 100644 index 9288ec789f6a9..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_buttons.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include "photon.h" - -#include "stm32_gpio.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - /* Configure Photon button gpio as input */ - - stm32_configgpio(GPIO_BUTTON1); - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - /* Check the state of the only button */ - - if (stm32_gpioread(GPIO_BUTTON1)) - { - return BOARD_BUTTON1_BIT; - } - - return 0; -} - -/**************************************************************************** - * Name: board_button_irq - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - if (id != BOARD_BUTTON1) - { - /* Invalid button id */ - - return -EINVAL; - } - - /* Configure interrupt on falling edge only */ - - return stm32_gpiosetevent(GPIO_BUTTON1, false, true, false, - irqhandler, arg); -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/boards/arm/stm32/photon/src/stm32_composite.c b/boards/arm/stm32/photon/src/stm32_composite.c deleted file mode 100644 index f0eec287904cf..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_composite.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - /* Change "dev" array size to add more composite devs */ - - struct composite_devdesc_s dev[1]; - int ifnobase = 0; - int strbase = (COMPOSITE_NSTRIDS) - 1; - - int dev_idx = 0; - -#ifdef CONFIG_USBADB - /* Configure the ADB USB device */ - - /* Ask the adb driver to fill in the constants we didn't - * know here. - */ - - usbdev_adb_get_composite_devdesc(&dev[dev_idx]); - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBADB_EP_BULKIN_IDX] = 1; - dev[dev_idx].devinfo.epno[USBADB_EP_BULKOUT_IDX] = 2; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - - /* Add other composite devices here */ - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { - return board_composite0_connect(port); - } - - return NULL; -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/photon/src/stm32_rgbled.c b/boards/arm/stm32/photon/src/stm32_rgbled.c deleted file mode 100644 index c43f21b604ba1..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_rgbled.c +++ /dev/null @@ -1,169 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "photon.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL2 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM2_CHANNEL4 -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct file file; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - ledr->ops->setup(ledr); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - ledg->ops->setup(ledg); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - ledb->ops->setup(ledb); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - ret = file_open(&file, "/dev/rgbled0", O_WRONLY); - if (ret < 0) - { - lederr("ERROR: open failed: %d\n", ret); - return ret; - } - - /* Initialize led off */ - - file_write(&file, "#000000", 8); - file_close(&file); - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/photon/src/stm32_spi.c b/boards/arm/stm32/photon/src/stm32_spi.c deleted file mode 100644 index 618331bb43dd2..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_spi.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "photon.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 - * STM32 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - switch (devid) - { - default: - break; - } - - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - /* To be provided */ - - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/photon/src/stm32_usb.c b/boards/arm/stm32/photon/src/stm32_usb.c deleted file mode 100644 index d8f5862485465..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_usb.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "photon.h" -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the Photon board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. - * This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif diff --git a/boards/arm/stm32/photon/src/stm32_userleds.c b/boards/arm/stm32/photon/src/stm32_userleds.c deleted file mode 100644 index 1d78b7ecd2ab6..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_userleds.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include "photon.h" - -#include "stm32_gpio.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure Photon LED gpio as output */ - - stm32_configgpio(GPIO_LED1); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_wlan.c b/boards/arm/stm32/photon/src/stm32_wlan.c deleted file mode 100644 index 2c0edcbca37d5..0000000000000 --- a/boards/arm/stm32/photon/src/stm32_wlan.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "stm32_gpio.h" -#include "stm32_sdio.h" - -#include "photon.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: bcmf_board_reset - ****************************************************************************/ - -void bcmf_board_reset(int minor, bool reset) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); -} - -/**************************************************************************** - * Name: bcmf_board_power - ****************************************************************************/ - -void bcmf_board_power(int minor, bool power) -{ - /* Power signal is not used on Photon board */ -} - -/**************************************************************************** - * Name: bcmf_board_initialize - ****************************************************************************/ - -void bcmf_board_initialize(int minor) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure reset pin */ - - stm32_configgpio(GPIO_WLAN0_RESET); - - /* Put wlan chip in reset state */ - - bcmf_board_reset(minor, true); -} - -/**************************************************************************** - * Name: bcmf_board_setup_oob_irq - ****************************************************************************/ - -void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) -{ - if (minor != SDIO_WLAN0_MINOR) - { - return; - } - - /* Configure SDIO card in-band interrupt callback */ - - if (g_sdio_dev != NULL) - { - sdio_set_sdio_card_isr(g_sdio_dev, func, arg); - } -} - -/**************************************************************************** - * Name: bcmf_board_etheraddr - ****************************************************************************/ - -bool bcmf_board_etheraddr(struct ether_addr *ethaddr) -{ - return false; -} - -/**************************************************************************** - * Name: photon_wlan_initialize - ****************************************************************************/ - -int photon_wlan_initialize() -{ - int ret; - - /* Initialize sdio interface */ - - wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); - - if (!g_sdio_dev) - { - wlerr("ERROR: Failed to initialize SDIO with slot %d\n", - SDIO_WLAN0_SLOTNO); - return ERROR; - } - - /* Bind the SDIO interface to the bcmf driver */ - - ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); - - if (ret != OK) - { - wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); - - /* FIXME deinitialize sdio device */ - - return ERROR; - } - - return OK; -} diff --git a/boards/arm/stm32/shenzhou/CMakeLists.txt b/boards/arm/stm32/shenzhou/CMakeLists.txt deleted file mode 100644 index afc3a6116339b..0000000000000 --- a/boards/arm/stm32/shenzhou/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32/shenzhou/configs/nsh/defconfig deleted file mode 100644 index 6458d6ddcb1a5..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SPICLOCK=12500000 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MMCSDSPIPORTNO=1 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig deleted file mode 100644 index b26d3effac213..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ADS7843E_SPIDEV=3 -CONFIG_ADS7843E_SWAPXY=y -CONFIG_ADS7843E_THRESHX=39 -CONFIG_ADS7843E_THRESHY=51 -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_ETH0_PHY_DM9161=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INPUT=y -CONFIG_INPUT_ADS7843E=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_SSD1289=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_LISTENERSTACK=1596 -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 -CONFIG_NXWM_NXTERM_STACKSIZE=1596 -CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=101 -CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2012 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_REMAP=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=1596 -CONFIG_SYSTEM_TELNETD_STACKSIZE=1596 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig deleted file mode 100644 index 9bd6be420efbe..0000000000000 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ /dev/null @@ -1,89 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="shenzhou" -CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DM9161=y -CONFIG_EXAMPLES_THTTPD=y -CONFIG_EXAMPLES_THTTPD_DRIPADDR=0xc0a80001 -CONFIG_EXAMPLES_THTTPD_NOMAC=y -CONFIG_FS_NXFFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="thttp_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MTD=y -CONFIG_MTD_W25=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETINIT_IPADDR=0xc0a80032 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_THTTPD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=768 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFLAT=y -CONFIG_PIPES=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_BKP=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=17 -CONFIG_STM32_PHYSR_100FD=0x8000 -CONFIG_STM32_PHYSR_100HD=0x4000 -CONFIG_STM32_PHYSR_10FD=0x2000 -CONFIG_STM32_PHYSR_10HD=0x1000 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0xf000 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_THTTPD_CGI_BYTECOUNT=20000 -CONFIG_THTTPD_CGI_PRIORITY=50 -CONFIG_THTTPD_CGI_STACKSIZE=1024 -CONFIG_THTTPD_IOBUFFERSIZE=1024 -CONFIG_THTTPD_IPADDR=0xc0a80032 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/shenzhou/include/board.h b/boards/arm/stm32/shenzhou/include/board.h deleted file mode 100644 index 394f305ee9868..0000000000000 --- a/boards/arm/stm32/shenzhou/include/board.h +++ /dev/null @@ -1,463 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* PLL output is 72MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ -#define STM32_PLL_FREQUENCY (72000000) - -/* SYCLLK and HCLK are the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* MCO output driven by PLL3. - * From above, we already have PLL3 input frequency as: - * - * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz - */ - -#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) -# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ -# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_KEY1 0 /* Name printed on board */ -#define BUTTON_KEY2 1 -#define BUTTON_KEY3 2 -#define BUTTON_KEY4 3 -#define NUM_BUTTONS 4 - -#define BUTTON_USERKEY2 BUTTON_KEY1 /* Names in schematic */ -#define BUTTON_USERKEY BUTTON_KEY2 -#define BUTTON_TAMPER BUTTON_KEY3 -#define BUTTON_WAKEUP BUTTON_KEY4 - -#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) -#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) -#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) -#define BUTTON_KEY4_BIT (1 << BUTTON_KEY4) - -#define BUTTON_USERKEY2_BIT BUTTON_KEY1_BIT -#define BUTTON_USERKEY_BIT BUTTON_KEY2_BIT -#define BUTTON_TAMPER_BIT BUTTON_KEY3_BIT -#define BUTTON_WAKEUP_BIT BUTTON_KEY4_BIT - -/* Relays */ - -#define NUM_RELAYS 2 - -/* Pin selections ***********************************************************/ - -/* Ethernet - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of - * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is - * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in RMII - * 48 PB11 MII_TX_EN Ethernet PHY mode. - * 51 PB12 MII_TXD0 Ethernet PHY - * 52 PB13 MII_TXD1 Ethernet PHY - * 16 PC1 MII_MDC Ethernet PHY - * 34 PC5 MII_INT Ethernet PHY - * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP - * - * The board desdign can support a 50MHz external clock to drive the PHY - * (U9). However, on my board, U9 is not present. - * - * 67 PA8 MCO DM9161AEP - */ - -#ifdef CONFIG_STM32_ETHMAC -# ifndef CONFIG_STM32_ETH_REMAP -# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" -# endif -# ifndef CONFIG_STM32_RMII -# error "STM32 Ethernet requires CONFIG_STM32_RMII" -# endif -# ifndef CONFIG_STM32_RMII_MCO -# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" -# endif -#endif - -/* USB - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USB_VBUS MINI-USB-AB. JP3 - * 69 PA10 USB_ID MINI-USB-AB. JP5 - * 70 PA11 USB_DM MINI-USB-AB - * 71 PA12 USB_DP MINI-USB-AB - * 95 PB8 USB_PWR Drives USB VBUS - */ - -/* UARTS/USARTS - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP - * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP - * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 - * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) - */ - -#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) -# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" -#endif - -#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) -# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" -#endif - -/* SPI - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. - * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), - * the NRF24L01 2.4G wireless module. - * Requires CONFIG_STM32_SPI3_REMAP. - */ - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) -# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" -#endif - -#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) -# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" -#endif - -/* DAC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 29 PA4 DAC_OUT1 To CON5(CN14) - * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 - */ - -/* ADC - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) - * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) - * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 - */ - -/* CAN - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 91 PB5 CAN2_RX Requires CONFIG_STM32_CAN2_REMAP. - * 92 PB6 CAN2_TX Requires CONFIG_STM32_CAN2_REMAP. See also JP11 - * 81 PD0 CAN1_RX Requires CONFIG_STM32_CAN1_REMAP2. - * 82 PD1 CAN1_TX Requires CONFIG_STM32_CAN1_REMAP2. - */ - -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP2) -# error "CONFIG_STM32_CAN1 requires CONFIG_STM32_CAN1_REMAP2" -#endif - -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_REMAP) -# error "CONFIG_STM32_CAN2 requires CONFIG_STM32_CAN2_REMAP" -#endif - -/* I2C - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 92 PB6 I2C1_SCL Requires !CONFIG_STM32_I2C1_REMAP - * 93 PB7 I2C1_SDA - */ - -#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) -# error "CONFIG_STM32_I2C1 must not have CONFIG_STM32_I2C1_REMAP" -#endif - -/* I2S - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 51 PB12 I2S_WS GPIO_I2S2_WS. Audio DAC - * 52 PB13 I2S_CK GPIO_I2S2_CK. Audio DAC - * 54 PB15 I2S_DIN ??? Audio DAC data in. - * 63 PC6 I2S_MCK GPIO_I2S2_MCK. Audio DAC. Active low: Pulled high - */ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the Shenzhou board. - * Because of the various rotations, clearing the display in the normal way - * by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm32_lcdclear(uint16_t color); - -/**************************************************************************** - * Relay control functions - * - * Description: - * Non-standard functions for relay control from the Shenzhou board. - * - * NOTE: These must match the prototypes in include/nuttx/arch.h - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_RELAYS -void up_relaysinit(void); -void relays_setstat(int relays, bool stat); -bool relays_getstat(int relays); -void relays_setstats(uint32_t relays_stat); -uint32_t relays_getstats(void); -void relays_onoff(int relays, uint32_t mdelay); -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); -void relays_resetmode(int relays); -void relays_powermode(int relays); -void relays_resetmodes(uint32_t relays_stat); -void relays_powermodes(uint32_t relays_stat); -#endif - -/**************************************************************************** - * Chip ID functions - * - * Description: - * Non-standard functions to obtain chip ID information. - * - ****************************************************************************/ - -const char *stm32_getchipid(void); -const char *stm32_getchipid_string(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* SPI3 */ - -#define GPIO_SPI3_NSS GPIO_ADJUST_MODE(GPIO_SPI3_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_SCK GPIO_ADJUST_MODE(GPIO_SPI3_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_MISO GPIO_ADJUST_MODE(GPIO_SPI3_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI3_MOSI GPIO_ADJUST_MODE(GPIO_SPI3_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/shenzhou/scripts/Make.defs b/boards/arm/stm32/shenzhou/scripts/Make.defs deleted file mode 100644 index 920c3f3fc2511..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/Make.defs +++ /dev/null @@ -1,53 +0,0 @@ -############################################################################ -# boards/arm/stm32/shenzhou/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -# Pick the linker script - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -MKNXFLAT = mknxflat -LDNXFLAT = ldnxflat - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections - -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script b/boards/arm/stm32/shenzhou/scripts/ld.script deleted file mode 100644 index 92929e25eb28c..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/ld.script +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and - * 64K of SRAM beginning at address 0x2000:0000. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32/shenzhou/scripts/ld.script.dfu deleted file mode 100644 index 63eb3ea049173..0000000000000 --- a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and - * 64K of SRAM beginning at address 0x2000:0000. Here we assume that the - * STMicro DFU bootloader is being used. In that case, the correct load .text - * load address is 0x08003000 (leaving 208K). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/shenzhou/src/CMakeLists.txt b/boards/arm/stm32/shenzhou/src/CMakeLists.txt deleted file mode 100644 index fe1037ab0f8d4..0000000000000 --- a/boards/arm/stm32/shenzhou/src/CMakeLists.txt +++ /dev/null @@ -1,73 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_RELAYS) - list(APPEND SRCS stm32_relays.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -# NOTE: SSD1289 is not supported on the board - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -else() - list(APPEND SRCS stm32_ili93xx.c) -endif() - -if(CONFIG_INPUT_ADS7843E) - list(APPEND SRCS stm32_touchscreen.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/shenzhou/src/Make.defs b/boards/arm/stm32/shenzhou/src/Make.defs deleted file mode 100644 index 86db238f76e14..0000000000000 --- a/boards/arm/stm32/shenzhou/src/Make.defs +++ /dev/null @@ -1,75 +0,0 @@ -############################################################################ -# boards/arm/stm32/shenzhou/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_RELAYS),y) -CSRCS += stm32_relays.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_MTD_W25),y) -CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -# NOTE: SSD1289 is not supported on the board - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -else -CSRCS += stm32_ili93xx.c -endif - -ifeq ($(CONFIG_INPUT_ADS7843E),y) -CSRCS += stm32_touchscreen.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/shenzhou/src/stm32_adc.c b/boards/arm/stm32/shenzhou/src/stm32_adc.c deleted file mode 100644 index 95cd3ac7accfa..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_adc.c +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "shenzhou.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. - * The only internal signal for ADC testing is the potentiometer input: - * - * ADC1_IN10(PC0) Potentiometer - * - * External signals are also available on CON5 CN14: - * - * ADC_IN8 (PB0) CON5 CN14 Pin2 - * ADC_IN9 (PB1) CON5 CN14 Pin1 - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 10 -}; - -/* {10, 8, 9}; */ - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN10 -}; - -/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32/shenzhou/src/stm32_autoleds.c deleted file mode 100644 index cae0688a9f3f9..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define SHENZHOU_LED1 (1 << 0) -#define SHENZHOU_LED2 (1 << 1) -#define SHENZHOU_LED3 (1 << 2) -#define SHENZHOU_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((SHENZHOU_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((SHENZHOU_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((SHENZHOU_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((SHENZHOU_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((SHENZHOU_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((clrbits & SHENZHOU_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & SHENZHOU_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & SHENZHOU_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & SHENZHOU_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - /* All LEDs are pulled up and, hence, active low */ - - if ((setbits & SHENZHOU_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((setbits & SHENZHOU_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((setbits & SHENZHOU_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((setbits & SHENZHOU_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: up_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void up_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_boot.c b/boards/arm/stm32/shenzhou/src/stm32_boot.c deleted file mode 100644 index b4aa743dcb07b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_boot.c +++ /dev/null @@ -1,270 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_W25 1 - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* Only one slot */ - -#ifndef CONFIG_STM32_SPI1 -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO -# error "Only one MMC/SD slot: Slot 0" -# endif - -/* Verify configured SPI port number */ - -# if defined(CONFIG_NSH_MMCSDSPIPORTNO) && CONFIG_NSH_MMCSDSPIPORTNO != STM32_MMCSDSPIPORTNO -# error "Only one MMC/SD port: SPI1" -# endif -#endif - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return; - } -#endif - -#ifdef HAVE_MMCSD - /* Initialize the SPI-based MMC/SD slot */ - - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", - STM32_MMCSDSLOTNO, ret); - return; - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. - * stm32_usbhost_initialize() starts a thread will monitor - * for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_INPUT_ADS7843E - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/shenzhou/src/stm32_buttons.c b/boards/arm/stm32/shenzhou/src/stm32_buttons.c deleted file mode 100644 index 0081e708c365b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_buttons.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "shenzhou.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Shenzhou button. This array is indexed by - * the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USERKEY2, GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_can.c b/boards/arm/stm32/shenzhou/src/stm32_can.c deleted file mode 100644 index 8a32d419a42ea..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_can.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "shenzhou.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_chipid.c b/boards/arm/stm32/shenzhou/src/stm32_chipid.c deleted file mode 100644 index 8ad2d692034be..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_chipid.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_chipid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -const char *stm32_getchipid(void) -{ - static char cpuid[12]; - int i; - - for (i = 0; i < 12; i++) - { - cpuid[i] = getreg8(0x1ffff7e8 + i); - } - - return cpuid; -} - -const char *stm32_getchipid_string(void) -{ - static char cpuid[27]; - int c; - int i; - - for (i = 0, c = 0; i < 12; i++) - { - snprintf(&cpuid[c], sizeof(cpuid) - c, - "%02X", getreg8(0x1ffff7e8 + 11 - i)); - c += 2; - if (i % 4 == 3) - { - cpuid[c++] = '-'; - } - } - - cpuid[26] = '\0'; - return cpuid; -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c deleted file mode 100644 index 283527e5d118b..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSPIPORTNO 1 /* Port is SPI1 */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -#ifndef CONFIG_STM32_SPI1 -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if MMC/SD driver support is not selected */ - -#ifndef CONFIG_MMCSD -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SPI1=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct spi_dev_s *spi; - int ret; - - /* Get the SPI port */ - - finfo("Initializing SPI port %d\n", STM32_MMCSDSPIPORTNO); - - spi = stm32_spibus_initialize(STM32_MMCSDSPIPORTNO); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port %d\n", - STM32_MMCSDSPIPORTNO); - return -ENODEV; - } - - finfo("Successfully initialized SPI port %d\n", STM32_MMCSDSPIPORTNO); - - /* Bind the SPI port to the slot */ - - finfo("Binding SPI port %d to MMC/SD slot %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); - - ret = mmcsd_spislotinitialize(minor, STM32_MMCSDSLOTNO, spi); - if (ret < 0) - { - ferr("ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO, ret); - return ret; - } - - finfo("Successfully bound SPI port %d to MMC/SD slot %d\n", - STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); -#endif - return OK; -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_relays.c b/boards/arm/stm32/shenzhou/src/stm32_relays.c deleted file mode 100644 index fab227889369d..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_relays.c +++ /dev/null @@ -1,274 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_relays.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "shenzhou.h" - -#ifdef CONFIG_ARCH_RELAYS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RELAYS_MIN_RESET_TIME 5 -#define RELAYS_RESET_MTIME 5 -#define RELAYS_POWER_MTIME 50 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_relays_stat = 0; -static bool g_relays_init = false; - -static const uint16_t g_relays[NUM_RELAYS] = -{ - GPIO_RELAYS_R00 -#ifdef GPIO_RELAYS_R01 - , GPIO_RELAYS_R01 -#endif -#ifdef GPIO_RELAYS_R02 - , GPIO_RELAYS_R02 -#endif -#ifdef GPIO_RELAYS_R03 - , GPIO_RELAYS_R03 -#endif -#ifdef GPIO_RELAYS_R04 - , GPIO_RELAYS_R04 -#endif -#ifdef GPIO_RELAYS_R05 - , GPIO_RELAYS_R05 -#endif -#ifdef GPIO_RELAYS_R06 - , GPIO_RELAYS_R06 -#endif -#ifdef GPIO_RELAYS_R07 - , GPIO_RELAYS_R07 -#endif -#ifdef GPIO_RELAYS_R08 - , GPIO_RELAYS_R08 -#endif -#ifdef GPIO_RELAYS_R09 - , GPIO_RELAYS_R09 -#endif -#ifdef GPIO_RELAYS_R10 - , GPIO_RELAYS_R10 -#endif -#ifdef GPIO_RELAYS_R11 - , GPIO_RELAYS_R11 -#endif -#ifdef GPIO_RELAYS_R12 - , GPIO_RELAYS_R12 -#endif -#ifdef GPIO_RELAYS_R13 - , GPIO_RELAYS_R13 -#endif -#ifdef GPIO_RELAYS_R14 - , GPIO_RELAYS_R14 -#endif -#ifdef GPIO_RELAYS_R15 - , GPIO_RELAYS_R15 -#endif -#ifdef GPIO_RELAYS_R16 - , GPIO_RELAYS_R16 -#endif -#ifdef GPIO_RELAYS_R17 - , GPIO_RELAYS_R17 -#endif -#ifdef GPIO_RELAYS_R18 - , GPIO_RELAYS_R18 -#endif -#ifdef GPIO_RELAYS_R19 - , GPIO_RELAYS_R19 -#endif -#ifdef GPIO_RELAYS_R20 - , GPIO_RELAYS_R20 -#endif -#ifdef GPIO_RELAYS_R21 - , GPIO_RELAYS_R21 -#endif -#ifdef GPIO_RELAYS_R22 - , GPIO_RELAYS_R22 -#endif -#ifdef GPIO_RELAYS_R23 - , GPIO_RELAYS_R23 -#endif -#ifdef GPIO_RELAYS_R24 - , GPIO_RELAYS_R24 -#endif -#ifdef GPIO_RELAYS_R25 - , GPIO_RELAYS_R25 -#endif -#ifdef GPIO_RELAYS_R26 - , GPIO_RELAYS_R26 -#endif -#ifdef GPIO_RELAYS_R27 - , GPIO_RELAYS_R27 -#endif -#ifdef GPIO_RELAYS_R28 - , GPIO_RELAYS_R28 -#endif -#ifdef GPIO_RELAYS_R29 - , GPIO_RELAYS_R29 -#endif -#ifdef GPIO_RELAYS_R30 - , GPIO_RELAYS_R30 -#endif -#ifdef GPIO_RELAYS_R31 - , GPIO_RELAYS_R31 -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void up_relaysinit(void) -{ - int i; - - if (g_relays_init) - { - return; - } - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_RELAYS; i++) - { - stm32_configgpio(g_relays[i]); - stm32_gpiowrite(g_relays[i], false); - } - - g_relays_init = true; -} - -void relays_setstat(int relays, bool stat) -{ - if ((unsigned)relays < NUM_RELAYS) - { - stm32_gpiowrite(g_relays[relays], stat); - if (!stat) - { - g_relays_stat &= ~(1 << relays); - } - else - { - g_relays_stat |= (1 << relays); - } - } -} - -bool relays_getstat(int relays) -{ - if ((unsigned)relays < NUM_RELAYS) - { - return (g_relays_stat & (1 << relays)) != 0; - } - - return false; -} - -void relays_setstats(uint32_t relays_stat) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_setstat(i, (relays_stat & (1 << i)) != 0); - } -} - -uint32_t relays_getstats(void) -{ - return (uint32_t)g_relays_stat; -} - -void relays_onoff(int relays, uint32_t mdelay) -{ - if ((unsigned)relays < NUM_RELAYS) - { - if (mdelay > 0) - { - if (relays_getstat(relays)) - { - relays_setstat(relays, false); - nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); - } - - relays_setstat(relays, true); - nxsched_usleep(mdelay * 100 * 1000); - relays_setstat(relays, false); - } - } -} - -void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) -{ - int i; - - for (i = 0; i < NUM_RELAYS; i++) - { - relays_onoff(i, mdelay); - } -} - -void relays_resetmode(int relays) -{ - relays_onoff(relays, RELAYS_RESET_MTIME); -} - -void relays_powermode(int relays) -{ - relays_onoff(relays, RELAYS_POWER_MTIME); -} - -void relays_resetmodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_RESET_MTIME); -} - -void relays_powermodes(uint32_t relays_stat) -{ - relays_onoffs(relays_stat, RELAYS_POWER_MTIME); -} - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_spi.c b/boards/arm/stm32/shenzhou/src/stm32_spi.c deleted file mode 100644 index 43629080b141c..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_spi.c +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "shenzhou.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Shenzhou board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_SD_CS); /* SD card chip select */ - stm32_configgpio(GPIO_SD_CD); /* SD card detect */ - stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ -#endif - - /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ - -#ifdef CONFIG_STM32_SPI3 - stm32_configgpio(GPIO_TP_CS); /* Touchscreen chip select */ - stm32_configgpio(GPIO_LCDDF_CS); /* Data flash chip select (on the LCD module) */ - stm32_configgpio(GPIO_LCDSD_CS); /* SD chip select (on the LCD module) */ - stm32_configgpio(GPIO_WIRELESS_CS); /* Wireless chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). - * All other methods (including stm32_spibus_initialize()) are provided by - * common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI1 connects to the SD CARD and to the SPI FLASH */ - - if (devid == SPIDEV_MMCSD(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_SD_CS, !selected); - } - else if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - /* The card detect pin is pulled up so that we detect the presence of a - * card by see a low value on the input pin. - */ - - if (stm32_gpioread(GPIO_SD_CD)) - { - return 0; - } - - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - /* SPI3 connects to TFT LCD (for touchscreen and SD) and the RF24L01 2.4G - * wireless module. - */ - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_TP_CS, !selected); - } - else if (devid == SPIDEV_MMCSD(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCDDF_CS, !selected); - } - else if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_LCDSD_CS, !selected); - } - else if (devid == SPIDEV_WIRELESS(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_WIRELESS_CS, !selected); - } -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c deleted file mode 100644 index c8b22220d7420..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c +++ /dev/null @@ -1,597 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#undef CONFIG_LCD_FASTCONFIG -#define CONFIG_LCD_FASTCONFIG 1 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of this driver */ - -struct stm32_lower_s -{ - struct ssd1289_lcd_s dev; /* This is externally visible the driver state */ - struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ - bool output; /* True: Configured for output */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helpers */ - -#ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(struct stm32_lower_s *priv, - const char *msg); -#else -# define stm32_lcdshow(p,m) -#endif - -static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data); -#ifndef CONFIG_LCD_NOGETRUN -static inline uint16_t stm32_rddata(struct stm32_lower_s *priv); -#endif - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_LCD_NOGETRUN -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -/* Initialization */ - -#ifndef CONFIG_LCD_NOGETRUN -static void stm32_lcdinput(struct stm32_lower_s *priv); -#endif -static void stm32_lcdoutput(struct stm32_lower_s *priv); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* TFT LCD - * - * -- ---- -------------- --------------------------------------------------- - * PN NAME SIGNAL NOTES - * -- ---- -------------- --------------------------------------------------- - * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) - * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and - * to the W25X16 SPI FLASH - * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) - * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) - * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) - * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) - * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) - * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) - * 58 PD11 SD_CS Active low: Pulled high - * (See also TFT LCD CN13, pin 32) - * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) - * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). - * Schematic is wrong LCD_WR is PB14. - * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) - * 97 PE0 DB00 To TFT LCD (CN13, pin 3) - * 98 PE1 DB01 To TFT LCD (CN13, pin 4) - * 1 PE2 DB02 To TFT LCD (CN13, pin 5) - * 2 PE3 DB03 To TFT LCD (CN13, pin 6) - * 3 PE4 DB04 To TFT LCD (CN13, pin 7) - * 4 PE5 DB05 To TFT LCD (CN13, pin 8) - * 5 PE6 DB06 To TFT LCD (CN13, pin 9) - * 38 PE7 DB07 To TFT LCD (CN13, pin 10) - * 39 PE8 DB08 To TFT LCD (CN13, pin 11) - * 40 PE9 DB09 To TFT LCD (CN13, pin 12) - * 41 PE10 DB10 To TFT LCD (CN13, pin 13) - * 42 PE11 DB11 To TFT LCD (CN13, pin 16) - * 43 PE12 DB12 To TFT LCD (CN13, pin 15) - * 44 PE13 DB13 To TFT LCD (CN13, pin 16) - * 45 PE14 DB14 To TFT LCD (CN13, pin 17) - * 46 PE15 DB15 To TFT LCD (CN13, pin 18) - * - * NOTE: - * The backlight signl NC_BL (CN13, pin 24) is pulled high and not under - * software control - * - * On LCD module: - * -- -------------- -------------------------------------------------------- - * PN SIGNAL NOTES - * -- -------------- -------------------------------------------------------- - * 3 DB01 To LCD DB1 - * 4 DB00 To LCD DB0 - * 5 DB03 To LCD DB3 - * 6 DB02 To LCD DB2 - * 7 DB05 To LCD DB5 - * 8 DB04 To LCD DB4 - * 9 DB07 To LCD DB7 - * 10 DB06 To LCD DB6 - * 11 DB09 To LCD DB9 - * 12 DB08 To LCD DB8 - * 13 DB11 To LCD DB11 - * 14 DB10 To LCD DB10 - * 15 DB13 To LCD DB13 - * 16 DB12 To LCD DB12 - * 17 DB15 To LCD DB15 - * 18 DB14 To LCD DB14 - * 19 RS To LCD RS - * 20 /LCD_CS To LCD CS - * 21 /RD To LCD RD - * 22 /WR To LCD WR - * 23 BL_EN (Not referenced) - * 24 /RESET - * 25 /INT To Touch IC /INT - * 26 MISO To Touch IC DOUT; To AT45DB161B SO; To SD card DAT0 - * 27 LE To 74HC573 that controls LCD 8-bit/16-bit mode - * 28 MOSI To Touch IC DIN; To AT45DB161B SI; To SD card CMD - * 29 /DF_CS To AT45DB161B Data Flash /CS - * 30 SCLK To Touch IC DCLK; To AT45DB161B SCK; To SD card CLK - * 31 /SD_CS To SD card /CS - * 31 /TP_CS To Touch IC CS - */ - -/* LCD GPIO configurations */ - -#ifndef CONFIG_LCD_FASTCONFIG -static const uint32_t g_lcdout[16] = -{ - GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, - GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, - GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, - GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, - GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, - GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, - GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, - GPIO_LCD_D14OUT, GPIO_LCD_D15OUT -}; - -static const uint32_t g_lcdin[16] = -{ - GPIO_LCD_D0IN, GPIO_LCD_D1IN, - GPIO_LCD_D2IN, GPIO_LCD_D3IN, - GPIO_LCD_D4IN, GPIO_LCD_D5IN, - GPIO_LCD_D6IN, GPIO_LCD_D7IN, - GPIO_LCD_D8IN, GPIO_LCD_D9IN, - GPIO_LCD_D10IN, GPIO_LCD_D11IN, - GPIO_LCD_D12IN, GPIO_LCD_D13IN, - GPIO_LCD_D14IN, GPIO_LCD_D15IN -}; -#endif - -static const uint32_t g_lcdconfig[] = -{ - GPIO_LCD_RS, GPIO_LCD_CS, - GPIO_LCD_RD, GPIO_LCD_WR, - GPIO_LCD_LE, -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/* Driver state structure (only supports one LCD) */ - -static struct stm32_lower_s g_lcdlower = -{ - { - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_LCD_NOGETRUN - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight - }, - .drvr = NULL, - .output = false -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_lcdshow - * - * Description: - * Show the state of the interface - * - ****************************************************************************/ - -#ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(struct stm32_lower_s *priv, - const char *msg) -{ - _info("%s:\n", msg); - _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", - getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), - getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); - _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); - if (priv->output) - { - _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); - } - else - { - _info(" INPUT: %08x\n", getreg32(LCD_IDR)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_wrdata - * - * Description: - * Latch data on D0-D15 and toggle the WR line. - * - ****************************************************************************/ - -static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data) -{ - /* Make sure D0-D15 are configured as outputs */ - - stm32_lcdoutput(priv); - - /* Latch the 16-bit LCD data and toggle the WR line */ - - putreg32(1, LCD_WR_CLEAR); - putreg32((uint32_t)data, LCD_ODR); - - /* Total WR pulse with should be 50ns wide. */ - - putreg32(1, LCD_WR_SET); -} - -/**************************************************************************** - * Name: stm32_rddata - * - * Description: - * Latch data on D0-D15 and toggle the WR line. - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static inline uint16_t stm32_rddata(struct stm32_lower_s *priv) -{ - uint16_t regval; - - /* Make sure D0-D15 are configured as inputs */ - - stm32_lcdinput(priv); - - /* Toggle the RD line to latch the 16-bit LCD data */ - - putreg32(1, LCD_RD_CLEAR); - - /* Data should appear 250ns after RD. - * Total RD pulse width should be 500nS - */ - - __asm__ __volatile__(" nop\n nop\n nop\n nop\n"); - regval = (uint16_t)getreg32(LCD_IDR); - putreg32(1, LCD_RD_SET); - return regval; -} -#endif - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Select the LCD by setting the LCD_CS low */ - - putreg32(1, LCD_CS_CLEAR); -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* De-select the LCD by setting the LCD_CS high */ - - putreg32(1, LCD_CS_SET); -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Clear the RS signal to select the index address */ - - putreg32(1, LCD_RS_CLEAR); - - /* And write the index */ - - stm32_wrdata(priv, (uint16_t)index); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Set the RS signal to select the data address */ - - putreg32(1, LCD_RS_SET); - - /* Read and return the data */ - - return stm32_rddata(priv); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; - - /* Set the RS signal to select the data address */ - - putreg32(1, LCD_RS_SET); - - /* And write the data */ - - stm32_wrdata(priv, data); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - /* There is no software control over the backlight */ -} - -/**************************************************************************** - * Name: stm32_lcdinput - * - * Description: - * Config data lines for input operations. - * - ****************************************************************************/ - -#ifndef CONFIG_LCD_NOGETRUN -static void stm32_lcdinput(struct stm32_lower_s *priv) -{ -#ifndef CONFIG_LCD_FASTCONFIG - int i; -#endif - - /* Check if we are already configured for input */ - - if (priv->output) - { - /* Configure GPIO data lines as inputs */ - -#ifdef CONFIG_LCD_FASTCONFIG - putreg32(LCD_INPUT, LCD_CRL); - putreg32(LCD_INPUT, LCD_CRH); -#else - for (i = 0; i < 16; i++) - { - stm32_configgpio(g_lcdin[i]); - } -#endif - - /* No longer configured for output */ - - priv->output = false; - } -} -#endif - -/**************************************************************************** - * Name: stm32_lcdoutput - * - * Description: - * Config data lines for output operations. - * - ****************************************************************************/ - -static void stm32_lcdoutput(struct stm32_lower_s *priv) -{ -#ifndef CONFIG_LCD_FASTCONFIG - int i; -#endif - - /* Check if we are already configured for output */ - - if (!priv->output) - { - /* Configure GPIO data lines as outputs */ - -#ifdef CONFIG_LCD_FASTCONFIG - putreg32(LCD_OUTPUT, LCD_CRL); - putreg32(LCD_OUTPUT, LCD_CRH); -#else - for (i = 0; i < 16; i++) - { - stm32_configgpio(g_lcdout[i]); - } -#endif - - /* Now we are configured for output */ - - priv->output = true; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - struct stm32_lower_s *priv = &g_lcdlower; - int i; - - /* Only initialize the driver once */ - - if (!priv->drvr) - { - lcdinfo("Initializing\n"); - - /* Configure GPIO pins */ - - stm32_lcdoutput(priv); - for (i = 0; i < NLCD_CONFIG; i++) - { - stm32_configgpio(g_lcdconfig[i]); - } - - /* Configure and enable the LCD */ - - priv->drvr = ssd1289_lcdinitialize(&priv->dev); - if (!priv->drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - priv->drvr->setpower(priv->drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - struct stm32_lower_s *priv = &g_lcdlower; - DEBUGASSERT(lcddev == 0); - return priv->drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - struct stm32_lower_s *priv = &g_lcdlower; - - /* Turn the display off */ - - priv->drvr->setpower(priv->drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c deleted file mode 100644 index 537e004b629c5..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c +++ /dev/null @@ -1,276 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_touchscreen.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_ADS7843E -#ifndef CONFIG_INPUT -# error "Touchscreen support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_SPI3 -# error "Touchscreen support requires CONFIG_STM32_SPI3" -#endif - -#ifndef CONFIG_ADS7843E_FREQUENCY -# define CONFIG_ADS7843E_FREQUENCY 500000 -#endif - -#ifndef CONFIG_ADS7843E_SPIDEV -# define CONFIG_ADS7843E_SPIDEV 3 -#endif - -#if CONFIG_ADS7843E_SPIDEV != 3 -# error "CONFIG_ADS7843E_SPIDEV must be three" -#endif - -#ifndef CONFIG_ADS7843E_DEVMINOR -# define CONFIG_ADS7843E_DEVMINOR 0 -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_config_s -{ - struct ads7843e_config_s dev; - xcpt_t handler; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the ADS7843E driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - * pendown - Return the state of the pen down GPIO input - */ - -static int tsc_attach(struct ads7843e_config_s *state, xcpt_t isr); -static void tsc_enable(struct ads7843e_config_s *state, bool enable); -static void tsc_clear(struct ads7843e_config_s *state); -static bool tsc_busy(struct ads7843e_config_s *state); -static bool tsc_pendown(struct ads7843e_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the ADS7843E - * driver. This structure provides information about the configuration - * of the ADS7843E and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_config_s g_tscinfo = -{ - { - .frequency = CONFIG_ADS7843E_FREQUENCY, - .attach = tsc_attach, - .enable = tsc_enable, - .clear = tsc_clear, - .busy = tsc_busy, - .pendown = tsc_pendown, - }, - .handler = NULL, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the ADS7843E driver from differences in GPIO - * interrupt handling by varying boards and MCUs. If possible, - * interrupts should be configured on both rising and falling edges - * so that contact and loss-of-contact events can be detected. - * - * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - * pendown - Return the state of the pen down GPIO input - */ - -static int tsc_attach(struct ads7843e_config_s *state, xcpt_t handler) -{ - struct stm32_config_s *priv = (struct stm32_config_s *)state; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - return OK; -} - -static void tsc_enable(struct ads7843e_config_s *state, bool enable) -{ - struct stm32_config_s *priv = (struct stm32_config_s *)state; - - /* The caller should not attempt to enable interrupts if the handler - * has not yet been 'attached' - */ - - DEBUGASSERT(priv->handler || !enable); - - /* Attach and enable, or detach and disable */ - - iinfo("enable:%d\n", enable); - if (enable) - { - stm32_gpiosetevent(GPIO_TP_INT, true, true, false, - priv->handler, NULL); - } - else - { - stm32_gpiosetevent(GPIO_TP_INT, false, false, false, - NULL, NULL); - } -} - -static void tsc_clear(struct ads7843e_config_s *state) -{ - /* Does nothing */ -} - -static bool tsc_busy(struct ads7843e_config_s *state) -{ - /* Hmmm... The ADS7843E BUSY pin is not brought out on the Shenzhou board. - * We will most certainly have to revisit this. There is this cryptic - * statement in the XPT2046 spec: "No DCLK delay required with dedicated - * serial port." - * - * The busy state is used by the ADS7843E driver to control the delay - * between sending the command, then reading the returned data. - */ - - return false; -} - -static bool tsc_pendown(struct ads7843e_config_s *state) -{ - /* XPT2046 uses an an internal pullup resistor. The PENIRQ output goes low - * due to the current path through the touch screen to ground, which - * initiates an interrupt to the processor via TP_INT. - */ - - bool pendown = !stm32_gpioread(GPIO_TP_INT); - iinfo("pendown:%d\n", pendown); - return pendown; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ - struct spi_dev_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Configure and enable the ADS7843E interrupt pin as an input. */ - - stm32_configgpio(GPIO_TP_INT); - - /* Get an instance of the SPI interface */ - - dev = stm32_spibus_initialize(CONFIG_ADS7843E_SPIDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize SPI bus %d\n", - CONFIG_ADS7843E_SPIDEV); - return -ENODEV; - } - - /* Initialize and register the SPI touschscreen device */ - - ret = ads7843e_register(dev, &g_tscinfo.dev, - CONFIG_ADS7843E_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to initialize SPI bus %d\n", - CONFIG_ADS7843E_SPIDEV); - - /* up_spiuninitialize(dev); */ - - return -ENODEV; - } - - return OK; -} - -#endif /* CONFIG_INPUT_ADS7843E */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_usb.c b/boards/arm/stm32/shenzhou/src/stm32_usb.c deleted file mode 100644 index 6660fca6bf810..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "shenzhou.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return -ENOSYS; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c deleted file mode 100644 index 4e9f496f1320a..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/shenzhou/src/stm32_userleds.c b/boards/arm/stm32/shenzhou/src/stm32_userleds.c deleted file mode 100644 index 52d3107e2fa91..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "shenzhou.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_w25.c b/boards/arm/stm32/shenzhou/src/stm32_w25.c deleted file mode 100644 index 861d79a855098..0000000000000 --- a/boards/arm/stm32/shenzhou/src/stm32_w25.c +++ /dev/null @@ -1,145 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include - -# include "stm32_spi.h" -#endif - -#include "shenzhou.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and NXFFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) -# warning "Can't support both FAT and NXFFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#ifdef CONFIG_FS_NXFFS - char devname[12]; -#endif - int ret; - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - ferr("ERROR: Failed to initialize SPI port 2\n"); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); - return -ENODEV; - } - -#ifndef CONFIG_FS_NXFFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", -ret); - return ret; - } - - /* Mount the file system at /mnt/w25 */ - - snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); - ret = nx_mount(NULL, devname, "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif -#endif - - return OK; -} diff --git a/boards/arm/stm32/shenzhou/tools/oocd.sh b/boards/arm/stm32/shenzhou/tools/oocd.sh deleted file mode 100755 index 136a792c6f9ef..0000000000000 --- a/boards/arm/stm32/shenzhou/tools/oocd.sh +++ /dev/null @@ -1,90 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -unset DEBUG - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - DEBUG=-d3 - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/shenzhou/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="${DEBUG} -s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/CMakeLists.txt deleted file mode 100644 index 7bbea8e4a973f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig deleted file mode 100644 index 1e7956808cc67..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_COMPOSITE_CONFIGSTR="system/composite" -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" -CONFIG_COMPOSITE_SERIALSTR="12345" -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="conn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_COMPOSITE=y -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig deleted file mode 100644 index 268aee418cc55..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_FAT_LCNAMES=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig deleted file mode 100644 index 760f1b8b5cfd7..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,109 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=2 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_MTD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXTK_BORDERCOLOR1=0xd69a -CONFIG_NXTK_BORDERCOLOR2=0xad55 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig deleted file mode 100644 index b75dbf44445e1..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nx_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig deleted file mode 100644 index 2421726a6d08a..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NXTERM=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxterm_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=256 -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=29 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2012 -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig deleted file mode 100644 index 4df26c1ffef14..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ /dev/null @@ -1,94 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set -# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set -# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_CUSTOM_PMINIT=y -CONFIG_ARCH_IDLE_CUSTOM=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf -CONFIG_EXAMPLES_NXHELLO_FONTID=6 -CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_EXAMPLES_NX_COLOR1=0xaedc -CONFIG_EXAMPLES_NX_COLOR2=0xe7ff -CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 -CONFIG_EXAMPLES_NX_FONTID=0 -CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_MAXCONTRAST=100 -CONFIG_LCD_MAXPOWER=100 -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_RPORTRAIT=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXFONT_SANS28X37B=y -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PM=y -CONFIG_PM_BUTTONS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_FREQUENCY=16384 -CONFIG_RTC_HIRES=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM3210E_LCD=y -CONFIG_STM3210E_LCD_BACKLIGHT=y -CONFIG_STM3210E_LCD_PWM=y -CONFIG_STM3210E_R61580_DISABLE=y -CONFIG_STM32_BKP=y -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig deleted file mode 100644 index 3a83a3e914e07..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_INIT_ENTRYPOINT="msconn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=30 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_BULKINREQLEN=256 -CONFIG_USBMSC_BULKOUTREQLEN=256 -CONFIG_USBMSC_EPBULKIN=5 -CONFIG_USBMSC_NRDREQS=2 -CONFIG_USBMSC_NWRREQS=2 -CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" -CONFIG_USBMSC_REMOVABLE=y -CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig deleted file mode 100644 index 3177d178960b6..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3210e-eval" -CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103ZE=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_INIT_ENTRYPOINT="usbserial_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_PL2303=y -CONFIG_PL2303_PRODUCTSTR="USBdev Serial" -CONFIG_PL2303_RXBUFSIZE=512 -CONFIG_PL2303_TXBUFSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=23 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2009 -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm3210e-eval/include/board.h b/boards/arm/stm32/stm3210e-eval/include/board.h deleted file mode 100644 index 6f3c44144929d..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/include/board.h +++ /dev/null @@ -1,402 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/* Logic in arch/arm/src and boards/ may need to include these file prior to - * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be - * included here because board.h is used in other contexts where the STM32 - * internal header files are not available. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* SRAM definitions *********************************************************/ - -/* The 8 Mbit SRAM is provided on the PT3 board using the FSMC_NE3 chip - * select. - */ - -/* This is the Bank1 SRAM3 address: */ - -#define BOARD_SRAM_BASE 0x68000000 /* Bank2 SRAM3 base address */ -#define BOARD_SRAM_SIZE (1*1024*1024) /* 8-Mbit = 1-Mbyte */ - -/* LED definitions **********************************************************/ - -/* The STM3210E-EVAL board has 4 LEDs that we will encode as: */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* The STM3210E-EVAL supports several buttons - * - * Reset -- Connected to NRST - * Wakeup -- Connected to PA.0 - * Tamper -- Connected to PC.13 - * Key -- Connected to PG.8 - * - * And a Joystick - * - * Joystick center -- Connected to PG.7 - * Joystick down -- Connected to PD.3 - * Joystick left -- Connected to PG.14 - * Joystick right -- Connected to PG.13 - * Joystick up -- Connected to PG.15 - * - * The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should be - * used by the discrete joystick driver. - */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_KEY 2 - -#ifdef CONFIG_INPUT_DJOYSTICK -# define NUM_BUTTONS 3 -#else -# define JOYSTICK_SEL 3 -# define JOYSTICK_DOWN 4 -# define JOYSTICK_LEFT 5 -# define JOYSTICK_RIGHT 6 -# define JOYSTICK_UP 7 - -# define NUM_BUTTONS 8 -#endif - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_KEY_BIT (1 << BUTTON_KEY) - -#ifndef CONFIG_INPUT_DJOYSTICK -# define JOYSTICK_SEL_BIT (1 << JOYSTICK_SEL) -# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) -# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) -# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) -# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3210e_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3210e_lcdclear(uint16_t color); -#endif - -/**************************************************************************** - * Name: stm32_lm75initialize - * - * Description: - * Initialize and register the LM-75 Temperature Sensor driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/temp0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) -int stm32_lm75initialize(const char *devpath); -#endif - -/**************************************************************************** - * Name: stm32_lm75attach - * - * Description: - * Attach the LM-75 interrupt handler - * - * Input Parameters: - * irqhandler - the LM-75 interrupt handler - * arg - The argument that will accompany the interrupt - * - * Returned Value: - * Zero (OK) returned on success; a negated errno value is returned on - * failure. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) -int stm32_lm75attach(xcpt_t irqhandler, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* SDIO */ - -#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) -#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* FSMC NPS pins (used by board srcs) */ - -#define GPIO_NPS_A0 GPIO_ADJUST_MODE(GPIO_NPS_A0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A1 GPIO_ADJUST_MODE(GPIO_NPS_A1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A10 GPIO_ADJUST_MODE(GPIO_NPS_A10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A11 GPIO_ADJUST_MODE(GPIO_NPS_A11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A12 GPIO_ADJUST_MODE(GPIO_NPS_A12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A13 GPIO_ADJUST_MODE(GPIO_NPS_A13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A14 GPIO_ADJUST_MODE(GPIO_NPS_A14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A15 GPIO_ADJUST_MODE(GPIO_NPS_A15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A2 GPIO_ADJUST_MODE(GPIO_NPS_A2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A3 GPIO_ADJUST_MODE(GPIO_NPS_A3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A4 GPIO_ADJUST_MODE(GPIO_NPS_A4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A5 GPIO_ADJUST_MODE(GPIO_NPS_A5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A6 GPIO_ADJUST_MODE(GPIO_NPS_A6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A7 GPIO_ADJUST_MODE(GPIO_NPS_A7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A8 GPIO_ADJUST_MODE(GPIO_NPS_A8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_A9 GPIO_ADJUST_MODE(GPIO_NPS_A9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) -#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NBL0 GPIO_ADJUST_MODE(GPIO_NPS_NBL0_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NBL1 GPIO_ADJUST_MODE(GPIO_NPS_NBL1_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE2 GPIO_ADJUST_MODE(GPIO_NPS_NE2_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE3 GPIO_ADJUST_MODE(GPIO_NPS_NE3_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NE4 GPIO_ADJUST_MODE(GPIO_NPS_NE4_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) -#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32/stm3210e-eval/scripts/Make.defs deleted file mode 100644 index 7087042362d61..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3210e-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script b/boards/arm/stm32/stm3210e-eval/scripts/ld.script deleted file mode 100644 index afebfee8ace82..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu deleted file mode 100644 index 24bf37b6b6be4..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * STM3210E-EVAL's DFU bootloader is being used. In that case, the correct - * load .text load address is 0x08003000 (leaving 464Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 464K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt deleted file mode 100644 index b870c533c1ce4..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt +++ /dev/null @@ -1,70 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_extcontext.c stm32_extmem.c - stm32_selectnor.c) - list(APPEND SRCS stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c) - list(APPEND SRCS stm32_selectlcd.c stm32_deselectlcd.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) - - if(CONFIG_PM_BUTTONS) - list(APPEND SRCS stm32_pmbuttons.c) - endif() -endif() - -if(CONFIG_INPUT_DJOYSTICK) - list(APPEND SRCS stm32_djoystick.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3210e-eval/src/Make.defs b/boards/arm/stm32/stm3210e-eval/src/Make.defs deleted file mode 100644 index 9815a6acb2d43..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/Make.defs +++ /dev/null @@ -1,71 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3210e-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_extcontext.c stm32_extmem.c stm32_selectnor.c -CSRCS += stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c -CSRCS += stm32_selectlcd.c stm32_deselectlcd.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) -CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c - -ifeq ($(CONFIG_PM_BUTTONS),y) -CSRCS += stm32_pmbuttons.c -endif -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) -CSRCS += stm32_djoystick.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c deleted file mode 100644 index fc374d2a837c3..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel: Variable Resistor */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 14 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN14 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c deleted file mode 100644 index e4a1125248afe..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* If the FSMC and external RAM are selected, then enable SRAM access */ - -#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) - stm32_selectsram(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c deleted file mode 100644 index 3a6d49c8f43ac..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c +++ /dev/null @@ -1,317 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* PORT and SLOT number probably depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# define NSH_HAVEUSBDEV 1 -# define NSH_HAVEMMCSD 1 -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#else - -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -# undef NSH_HAVEUSBDEV -# undef NSH_HAVEMMCSD -#endif - -/* Can't support USB features if USB is not enabled */ - -#ifndef CONFIG_USBDEV -# undef NSH_HAVEUSBDEV -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef NSH_HAVEMMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef NSH_HAVEMMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 1\n"); - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 1\n"); - - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); - return -ENODEV; - } - - syslog(LOG_INFO, - "Successfully bound SPI port 0 to the SPI FLASH driver\n"); -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - - /* Create the SPI FLASH MTD instance */ - - /* The M25Pxx is not a give media to implement a file system.. - * its block sizes are too large - */ - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef NSH_HAVEMMCSD - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_NSH_MMCSDMINOR); - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the STM3210E-EVAL board supports a GPIO - * to detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the simulated framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - /* Initialize and register the joystick driver */ - - ret = stm32_djoy_initialization(); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the joystick driver: %d\n", ret); - return ret; - } - - syslog(LOG_INFO, "Successfully registered the joystick driver\n"); -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c deleted file mode 100644 index c60b60a4d50d7..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_KEY, - - /* The Joystick is treated like the other buttons unless - * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should - * be used by the discrete joystick driver. - */ - -#ifndef CONFIG_INPUT_DJOYSTICK - GPIO_JOY_SEL, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_UP -#endif -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c b/boards/arm/stm32/stm3210e-eval/src/stm32_can.c deleted file mode 100644 index 9ef1ed802793e..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c +++ /dev/null @@ -1,95 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F103ZE supports only CAN1 */ - -#define CAN_PORT 1 - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#ifdef CONFIG_STM32_CAN1 - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c deleted file mode 100644 index b955808ef1ba0..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ /dev/null @@ -1,450 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* No SDIO? Then no USB MSC device in composite */ - -#ifndef CONFIG_STM32_SDIO -# undef CONFIG_USBMSC_COMPOSITE -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application- specific wrapper about usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - DEBUGASSERT(g_mschandle != NULL); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite0_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *board_composite0_connect(int port) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[0]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[0].classobject = cdcacm_classobject; - dev[0].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[0].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[0].devinfo.ninterfaces; - strbase += dev[0].devinfo.nstrings; - - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[1]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[1].classobject = board_mscclassobject; - dev[1].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[1].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; - dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; - - /* Count up the base numbers */ - - ifnobase += dev[1].devinfo.ninterfaces; - strbase += dev[1].devinfo.nstrings; - - return composite_initialize(composite_getdevdescs(), dev, 2); -} -#endif - -/**************************************************************************** - * Name: board_composite1_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 1. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite1_connect(int port) -{ - /* REVISIT: This configuration currently fails. stm32_epallocpma() fails - * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte - * buffers, two required for EP0, leaving only buffers for 5 additional - * endpoints. - */ - -#if 0 - struct composite_devdesc_s dev[2]; - int strbase = COMPOSITE_NSTRIDS; - int ifnobase = 0; - int epno; - int i; - - for (i = 0, epno = 1; i < 2; i++) - { - /* Ask the cdcacm driver to fill in the constants we didn't know here */ - - cdcacm_get_composite_devdesc(&dev[i]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[i].classobject = cdcacm_classobject; - dev[i].uninitialize = cdcacm_uninitialize; - - dev[i].minor = i; /* The minor interface number */ - - /* Interfaces */ - - dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - - /* Strings */ - - dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; - dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; - - ifnobase += dev[i].devinfo.ninterfaces; - strbase += dev[i].devinfo.nstrings; - } - - return composite_initialize(composite_getdevdescs(), dev, 2); -#else - return NULL; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - /* If system/composite is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - * - * NOTE: CONFIG_NSH_BUILTIN_APPS is not a fool-proof indication that NSH - * was built. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=0\n"); - - ret = mmcsd_slotinitialize(0, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the STM3210E-EVAL board supports a GPIO to detect if - * there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { -#ifdef CONFIG_USBMSC_COMPOSITE - return board_composite0_connect(port); -#else - return NULL; -#endif - } - else if (configid == 1) - { - return board_composite1_connect(port); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c deleted file mode 100644 index 4b10bfee096ea..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c deleted file mode 100644 index 42bed7c9f852e..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable NOR FLASH - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0x000030d2, STM32_FSMC_BCR3); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR3); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c deleted file mode 100644 index acd4aa605df31..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t -djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t -djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialization - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialization(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c deleted file mode 100644 index e40b69a09856b..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c +++ /dev/null @@ -1,137 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* It would be much more efficient to brute force these all into the - * the appropriate registers. Just a little tricky. - */ - -/* GPIO configurations common to SRAM and NOR Flash */ - -const uint16_t g_commonconfig[NCOMMON_CONFIG] = -{ - /* A0... A18 */ - - GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3, - GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7, - GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11, - GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15, - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, - GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, - GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, - GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, - - /* NOE, NWE */ - - GPIO_NPS_NOE, GPIO_NPS_NWE -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c deleted file mode 100644 index 6420bf627a4e7..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c +++ /dev/null @@ -1,437 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" -#include "stm32_rtc.h" - -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode - * (which corresponds to STM32 stop mode). If this alarm expires, - * the logic in this file will wakeup from PM_STANDBY mode and - * transition to PM_SLEEP mode (STM32 standby mode). - */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 15 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/* Values for the RTC Alarm to reset from the PM_SLEEP mode (STM32 - * standby mode). If CONFIG_PM_SLEEP_WAKEUP is defined in the - * configuration, then the logic in this file will program the RTC - * alarm to wakeup the processor after an a delay. - * - * This feature might be useful, for example, in a system that needs to - * use minimal power but awake up to perform some task at periodic - * intervals. - */ - -#ifdef CONFIG_PM_SLEEP_WAKEUP - -# ifndef CONFIG_RTC_ALARM -# error "CONFIG_RTC_ALARM should be enabled to use CONFIG_PM_SLEEP_WAKEUP" -# endif - -/* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC - * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 - * awakens from PM_SLEEP mode. - */ - -# ifndef CONFIG_PM_SLEEP_WAKEUP_SEC -# define CONFIG_PM_SLEEP_WAKEUP_SEC 10 -# endif - -# ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC -# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static volatile bool g_alarmwakeup; /* Wakeup Alarm indicator */ -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_alarmcb - * - * Description: - * RTC alarm callback - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void) -{ - /* Note that we were awaken by an alarm */ - - g_alarmwakeup = true; -} -#endif - -/**************************************************************************** - * Name: stm32_alarm_exti - * - * Description: - * RTC alarm EXTI interrupt service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static int stm32_alarm_exti(int irq, void *context, void *arg) -{ - stm32_alarmcb(); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_exti_cancel - * - * Description: - * Disable the ALARM EXTI interrupt - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_exti_cancel(void) -{ - stm32_exti_alarm(false, false, false, NULL, NULL); -} -#endif - -/**************************************************************************** - * Name: stm32_rtc_alarm - * - * Description: - * Set the alarm - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti) -{ - struct timespec alarmtime; - int ret; - - /* Configure to receive RTC Alarm EXTI interrupt */ - - if (exti) - { - /* TODO: Make sure that that is no pending EXTI interrupt */ - - stm32_exti_alarm(true, true, true, stm32_alarm_exti, NULL); - } - - /* Configure the RTC alarm to Auto Wake the system */ - - up_rtc_gettime(&alarmtime); - - alarmtime.tv_sec += tv_sec; - alarmtime.tv_nsec += tv_nsec; - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - - if (alarmtime.tv_nsec >= NSEC_PER_SEC) - { - /* Carry to the seconds */ - - alarmtime.tv_sec++; - alarmtime.tv_nsec -= NSEC_PER_SEC; - } - - /* Set the alarm */ - - g_alarmwakeup = false; - ret = stm32_rtc_setalarm(&alarmtime, stm32_alarmcb); - if (ret < 0) - { - serr("ERROR: Warning: The alarm is already set\n"); - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - int ret; - - /* The following is logic that is done after the wake-up from PM_STANDBY - * state. It decides whether to go back to the PM_NORMAL or to the deeper - * power-saving mode PM_SLEEP: If the alarm expired with no "normal" - * wake-up event, then PM_SLEEP is entered. - * - * Logically, this code belongs at the end of the PM_STANDBY case below, - * does not work in the position for some unknown reason. - */ - - if (oldstate == PM_STANDBY) - { - /* Were we awakened by the alarm? */ - -#ifdef CONFIG_RTC_ALARM - if (g_alarmwakeup) - { - /* Yes.. Go to SLEEP mode */ - - newstate = PM_SLEEP; - } - else -#endif - { - /* Resume normal operation */ - - newstate = PM_NORMAL; - } - } - else - { - /* Let the PM system decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - } - - /* Check for state changes */ - - if (newstate != oldstate) - { - _info("newstate= %d oldstate=%d\n", newstate, oldstate); - - sched_lock(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - /* If we just awakened from PM_STANDBY mode, then reconfigure - * clocking. - */ - - if (oldstate == PM_STANDBY) - { - /* Re-enable clocking */ - - stm32_clockenable(); - - /* The system timer was disabled while in PM_STANDBY or - * PM_SLEEP modes. But the RTC has still be running: Reset - * the system time the current RTC time. - */ - -#ifdef CONFIG_RTC - clock_synchronize(NULL); -#endif - } - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { - /* Set the alarm as an EXTI Line */ - -#ifdef CONFIG_RTC_ALARM - stm32_rtc_alarm(CONFIG_PM_ALARM_SEC, CONFIG_PM_ALARM_NSEC, true); -#endif - /* Wait 10ms */ - - up_mdelay(10); - - /* Enter the STM32 stop mode */ - - stm32_pmstop(false); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM - stm32_exti_cancel(); - ret = stm32_rtc_cancelalarm(); - if (ret < 0) - { - swarn("WARNING: Cancel alarm failed\n"); - } -#endif - - /* Note: See the additional PM_STANDBY related logic at the - * beginning of this function. That logic is executed after - * this point. - */ - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - /* Configure the RTC alarm to Auto Reset the system */ - -#ifdef CONFIG_PM_SLEEP_WAKEUP - stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, - CONFIG_PM_SLEEP_WAKEUP_NSEC, false); -#endif - /* Wait 10ms */ - - up_mdelay(10); - - /* Enter the STM32 standby mode */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - sched_unlock(); - } -} -#else -# define stm32_idlepm() -#endif /* CONFIG_PM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c deleted file mode 100644 index 9195f4a7c88e0..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1841 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs: - * - * 1. Ampire AM-240320LTNQW00H - * 2. Orise Tech SPFD5408B - * 3. RenesasSP R61580 - * - * The driver dynamically selects the LCD based on the reported LCD ID value. - * However, code size can be reduced by suppressing support for individual - * LCDs using: - * - * CONFIG_STM3210E_AM240320_DISABLE - * CONFIG_STM3210E_SPFD5408B_DISABLE - * CONFIG_STM3210E_R61580_DISABLE - * - * Omitting the above (or setting them to "n") enables support for the LCD. - * Setting any of the above to "y" will disable support for the - * corresponding LCD. - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Backlight */ - -#ifndef CONFIG_STM3210E_LCD_BACKLIGHT -# undef CONFIG_STM3210E_LCD_PWM -#endif - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# if !defined(CONFIG_STM32_TIM1) -# warning "CONFIG_STM3210E_LCD_PWM requires CONFIG_STM32_TIM1" -# undef CONFIG_STM3210E_LCD_PWM -# endif -# if defined(CONFIG_STM32_TIM1_FULL_REMAP) -# warning "PA8 cannot be configured as TIM1 CH1 with full remap" -# undef CONFIG_STM3210E_LCD_PWM -# endif -#endif - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# if CONFIG_LCD_MAXPOWER < 2 -# warning "A larger value of CONFIG_LCD_MAXPOWER is recommended" -# endif -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# undef CONFIG_LCD_MAXPOWER -# if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) -# define CONFIG_LCD_MAXPOWER 100 -# else -# define CONFIG_LCD_MAXPOWER 1 -# endif -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* PWM Frequency */ - -#ifndef CONFIG_STM3210E_LCD_PWMFREQUENCY -# define CONFIG_STM3210E_LCD_PWMFREQUENCY 100 -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_PORTRAIT) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif !defined(CONFIG_LCD_LANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* When reading 16-bit gram data, there may some shifts in the returned data - * and/or there may be some colors in the incorrect posisions: - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * Red and green appear to be swapped on read-back as well - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * - AM240320: Unknown -- assume colors are correct for now. - */ - -#define SPFD5408B_RDSHIFT 5 - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#ifdef CONFIG_LCD_LANDSCAPE -# define STM3210E_XRES 320 -# define STM3210E_YRES 240 -#else -# define STM3210E_XRES 240 -# define STM3210E_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3210E_BPP 16 -#define STM3210E_COLORFMT FB_FMT_RGB16_565 - -/* STM3210E-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 4 of NOR/SRAM Bank 1~4 */ - -#define STM3210E_LCDBASE ((uint32_t)(0x60000000 | 0x0c000000)) -#define LCD ((struct lcd_regs_s *) STM3210E_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define SPFD5408B_ID 0x5408 -#define R61580_ID 0x1580 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_SPFD5408B, - LCD_TYPE_R61580, - LCD_TYPE_AM240320 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3210e_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) - uint32_t reload; -#endif - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3210e_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3210e_readreg(uint8_t regaddr); -static inline void stm3210e_gramselect(void); -static inline void stm3210e_writegram(uint16_t rgbval); -static void stm3210e_readsetup(uint16_t *accum); -#ifndef CONFIG_STM3210E_AM240320_DISABLE -static void stm3210e_readnosetup(uint16_t *accum); -#endif -static uint16_t stm3210e_readshift(uint16_t *accum); -static uint16_t stm3210e_readnoshift(uint16_t *accum); -static void stm3210e_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3210e_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, - size_t npixels); -static int stm3210e_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, - size_t npixels); - -/* LCD Configuration */ - -static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3210e_getpower(struct lcd_dev_s *dev); -static int stm3210e_setpower(struct lcd_dev_s *dev, int power); -static int stm3210e_getcontrast(struct lcd_dev_s *dev); -static int stm3210e_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* LCD Power Management */ - -#ifdef CONFIG_PM -static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/* Initialization */ - -static inline void stm3210e_lcdinitialize(void); -#ifdef CONFIG_STM3210E_LCD_BACKLIGHT -static void stm3210e_backlight(void); -#else -# define stm3210e_backlight() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3210E_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3210E_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3210E_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3210E_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3210e_putrun, /* Put a run into LCD memory */ - .getrun = stm3210e_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3210E_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3210e_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3210e_getvideoinfo, - .getplaneinfo = stm3210e_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3210e_getpower, - .setpower = stm3210e_setpower, - .getcontrast = stm3210e_getcontrast, - .setcontrast = stm3210e_setcontrast, - }, -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_lcdcb = -{ - .notify = stm3210e_pm_notify, - .prepare = stm3210e_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3210e_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3210e_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3210e_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3210e_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3210e_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3210e_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3210e_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3210e_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3210e_readsetup / stm3210e_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * - AM240320: Unknown -- assuming no shift in the return data - * - ****************************************************************************/ - -/* Used for SPFD5408B and R61580 */ - -#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) -static void stm3210e_readsetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} -#endif - -/* Used only for AM240320 */ - -#ifndef CONFIG_STM3210E_AM240320_DISABLE -static void stm3210e_readnosetup(uint16_t *accum) -{ -} -#endif - -/**************************************************************************** - * Name: stm3210e_readshift / stm3210e_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly - * shifting the data and possibly swapping red and green components. - * - * - SPFD5408B: There appears to be a 5-bit shift in the returned data. - * Red and green appear to be swapped on read-back as well - * - R61580: There is a 16-bit (1 pixel) shift in the returned data. - * All colors in the normal order - * - AM240320: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -/* This version is used only for the SPFD5408B. It shifts the data by - * 5-bits and swaps red and green - */ - -#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE -static uint16_t stm3210e_readshift(uint16_t *accum) -{ - uint16_t red; - uint16_t green; - uint16_t blue; - - /* Read the value (GRAM register already selected) */ - - uint16_t next = LCD->value; - - /* Return previous bits 0-10 as bits 6-15 and next data bits 11-15 as - * bits 0-5 - * - * xxxx xPPP PPPP PPPP - * NNNN Nxxx xxxx xxxx - * - * Assuming that SPFD5408B_RDSHIFT == 5 - */ - - uint16_t value = *accum << SPFD5408B_RDSHIFT | - next >> (16 - SPFD5408B_RDSHIFT); - - /* Save the value for the next time we are called */ - - *accum = next; - - /* Tear the RGB655 apart. Swap read and green */ - - red = (value << (11 - 5)) & 0xf800; /* Move bits 5-9 to 11-15 */ - green = (value >> (10 - 5)) & 0x07e0; /* Move bits 10-15 to bits 5-10 */ - blue = value & 0x001f; /* Blue is in the right place */ - - /* And put the RGB565 back together */ - - value = red | green | blue; - - /* This is weird... If blue is zero, then red+green values are off by 0x20. - * Except that both 0x0000 and 0x0020 can map to 0x0000. Need to revisit - * this!!!!!!!!!!! I might be misinterpreting some of the data that I - * have. - */ - -#if 0 /* REVISIT */ - if (value != 0 && blue == 0) - { - value += 0x20; - } -#endif - - return value; -} -#endif - -/* This version is used for the R61580 and for the AM240320. It neither - * shifts nor swaps colors. - */ - -#if !defined(CONFIG_STM3210E_R61580_DISABLE) || !defined(CONFIG_STM3210E_AM240320_DISABLE) -static uint16_t stm3210e_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} -#endif - -/**************************************************************************** - * Name: stm3210e_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3210e_setcursor(uint16_t col, uint16_t row) -{ - stm3210e_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3210e_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3210e_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The lcd device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3210e_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, - size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Which edge of the display is the "top?" Here the - * edge with the simplest conversion is used. - */ - - col = (STM3210E_XRES - 1) - col; - - /* Set the cursor position */ - - stm3210e_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3210e_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position (auto-decrements to the next - * column) - */ - - stm3210e_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. (Swap row and column. This is done implicitly). */ - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - stm3210e_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. (Swap row and column. This is done implicitly). - * Which edge of the display is the "top"? - */ - - col = (STM3210E_XRES - 1) - col; - row = (STM3210E_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - stm3210e_writegram(*src++); - - /* Decrement to next column */ - - col--; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The lcd device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3210e_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, - size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type */ - - switch (g_lcddev.type) - { -#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE - case LCD_TYPE_SPFD5408B: - readsetup = stm3210e_readsetup; - readgram = stm3210e_readshift; - break; -#endif - -#ifndef CONFIG_STM3210E_R61580_DISABLE - case LCD_TYPE_R61580: - readsetup = stm3210e_readsetup; - readgram = stm3210e_readnoshift; - break; -#endif - -#ifndef CONFIG_STM3210E_AM240320_DISABLE - case LCD_TYPE_AM240320: - readsetup = stm3210e_readnosetup; - readgram = stm3210e_readnoshift; - break; -#endif - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Which edge of the display is the "top?" Here the - * edge with the simplest conversion is used. - */ - - col = (STM3210E_XRES - 1) - col; - - /* Set the cursor position */ - - stm3210e_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3210e_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position (autoincrements to the next - * row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates (Swap row and column. This is done implicitly). */ - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. (Swap row and column. This is done implicitly). - * Which edge of the display is the "top"? - */ - - col = (STM3210E_XRES - 1) - col; - row = (STM3210E_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3210e_setcursor(row, col); - stm3210e_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col--; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getpower - * - * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_getpower(struct lcd_dev_s *dev) -{ - ginfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3210e_poweroff - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_poweroff(void) -{ - /* Turn the display off */ - - stm3210e_writereg(LCD_REG_7, 0); - - /* Disable timer 1 clocking */ - -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) -# if defined(CONFIG_STM3210E_LCD_PWM) - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); -# endif - - /* Configure the PA8 pin as an output */ - - stm32_configgpio(GPIO_LCD_BACKLIGHT); - - /* Turn the backlight off */ - - stm32_gpiowrite(GPIO_LCD_BACKLIGHT, false); -#endif - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3210e_setpower - * - * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: - * full on). On backlit LCDs, this setting may correspond to the backlight - * setting. - * - ****************************************************************************/ - -static int stm3210e_setpower(struct lcd_dev_s *dev, int power) -{ - ginfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { -#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) - uint32_t frac; - uint32_t duty; - - /* If we are coming up from the power off state, then re-configure - * the timer - */ - - if (g_lcddev.power == 0) - { - stm3210e_backlight(); - } - - /* Make sure that the power value is within range */ - - if (power > CONFIG_LCD_MAXPOWER) - { - power = CONFIG_LCD_MAXPOWER; - } - - /* Calculate the new backlight duty. It is a faction of the timer1 - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - frac = (power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#else - /* Turn the backlight on */ - - stm32_gpiowrite(GPIO_LCD_BACKLIGHT, true); -#endif - /* Then turn the display on */ - -#ifndef CONFIG_STM3210E_AM240320_DISABLE -# if !defined (CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) - stm3210e_writereg(LCD_REG_7, - g_lcddev.type == LCD_TYPE_AM240320 ? - 0x0173 : 0x0112); -# else - stm3210e_writereg(LCD_REG_7, 0x0173); -# endif -#else - stm3210e_writereg(LCD_REG_7, 0x0112); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3210e_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3210e_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3210e_getcontrast(struct lcd_dev_s *dev) -{ - ginfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3210e_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3210e_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - ginfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3210e_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * None - The driver already agreed to transition to the low power - * consumption state when when it returned OK to the prepare() call. - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ -#ifdef CONFIG_STM3210E_LCD_PWM - uint32_t frac; - uint32_t duty; -#endif - - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LCD operation */ - -#ifdef CONFIG_STM3210E_LCD_PWM - frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Reduce LCD light */ - -#ifdef CONFIG_STM3210E_LCD_PWM - frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; - duty = (g_lcddev.reload * frac) >> 16; - if (duty > 0) - { - duty--; - } - - /* Reduce the LCD backlight to 50% of the MAXPOWER */ - - duty >>= 1; - putreg16((uint16_t)duty, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Turn display backlight off */ - -#ifdef CONFIG_STM3210E_LCD_PWM - putreg16(0, STM32_TIM1_CCR1); -#endif - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Turn off LCD */ - - if (g_lcddev.type == LCD_TYPE_AM240320) - { - /* Display off sequence */ - - stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ - up_mdelay(10); /* Wait for 2 frame scan */ - stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ - - /* Power off sequence */ - - stm3210e_writereg(LCD_REG_30, 0x09); /* VCOM stop */ - stm3210e_writereg(LCD_REG_27, 0x0e); /* VS/VDH turn off */ - stm3210e_writereg(LCD_REG_24, 0xc0); /* CP1, CP2, CP3 turn off */ - up_mdelay(10); /* wait 10 ms */ - - stm3210e_writereg(LCD_REG_24, 0x00); /* VR1 / VR2 off */ - stm3210e_writereg(LCD_REG_28, 0x30); /* Step up circuit operating current stop */ - up_mdelay(10); - - stm3210e_poweroff(); - stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ - up_mdelay(10); /* Wait for 2 frame scan */ - - stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ - } - else - { - stm3210e_poweroff(); - } - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: stm3210e_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - * Input Parameters: - * - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state data at - * the end of the structure. - * - * pmstate - Identifies the new PM state - * - * Returned Value: - * Zero - (OK) means the event was successfully processed and that the - * driver is prepared for the PM state change. - * - * Non-zero - means that the driver is not prepared to perform the tasks - * needed achieve this power setting and will cause the state - * change to be aborted. NOTE: The prepare() method will also - * be called when reverting from lower back to higher power - * consumption modes (say because another driver refused a - * lower power state change). Drivers are not permitted to - * return non-zero values when reverting back to higher power - * consumption modes! - * - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LCD driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm3210e_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3210e_lcdinitialize(void) -{ - uint16_t id; - - /* Check if the LCD is Orise Tech SPFD5408B Controller (or the compatible - * RenesasSP R61580). - */ - - id = stm3210e_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the SPFD5408B */ - -#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) - if (id == SPFD5408B_ID) - { - /* Set the LCD type for the SPFD5408B */ - - g_lcddev.type = LCD_TYPE_SPFD5408B; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ - stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - - /* Power On sequence */ - - stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3210e_writereg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_16, 0x12b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_18, 0x01bd); /* External reference voltage= Vci */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ - stm3210e_writereg(LCD_REG_41, 0x000e); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3210e_writereg(LCD_REG_33, 0x013f); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (SPFD5408B) */ - - stm3210e_writereg(LCD_REG_48, 0x0b0d); - stm3210e_writereg(LCD_REG_49, 0x1923); - stm3210e_writereg(LCD_REG_50, 0x1c26); - stm3210e_writereg(LCD_REG_51, 0x261c); - stm3210e_writereg(LCD_REG_52, 0x2419); - stm3210e_writereg(LCD_REG_53, 0x0d0b); - stm3210e_writereg(LCD_REG_54, 0x1006); - stm3210e_writereg(LCD_REG_55, 0x0610); - stm3210e_writereg(LCD_REG_56, 0x0706); - stm3210e_writereg(LCD_REG_57, 0x0304); - stm3210e_writereg(LCD_REG_58, 0x0e05); - stm3210e_writereg(LCD_REG_59, 0x0e01); - stm3210e_writereg(LCD_REG_60, 0x010e); - stm3210e_writereg(LCD_REG_61, 0x050e); - stm3210e_writereg(LCD_REG_62, 0x0403); - stm3210e_writereg(LCD_REG_63, 0x0607); - - /* Set GRAM area */ - - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ - - /* Partial Display Control */ - - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x0000); - stm3210e_writereg(LCD_REG_131, 0x0000); - stm3210e_writereg(LCD_REG_132, 0x0000); - stm3210e_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3210e_writereg(LCD_REG_144, 0x0010); - stm3210e_writereg(LCD_REG_146, 0x0000); - stm3210e_writereg(LCD_REG_147, 0x0003); - stm3210e_writereg(LCD_REG_149, 0x0110); - stm3210e_writereg(LCD_REG_151, 0x0000); - stm3210e_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR=1 - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3210e_writereg(LCD_REG_3, 0x1018); - stm3210e_writereg(LCD_REG_7, 0); /* Display OFF */ - } - else -#endif - - /* Check if the ID is for the almost compatible R61580 */ - -#if !defined(CONFIG_STM3210E_R61580_DISABLE) - if (id == R61580_ID) - { - /* Set the LCD type for the R61580 */ - - g_lcddev.type = LCD_TYPE_R61580; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - up_mdelay(100); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_0, 0x0000); - stm3210e_writereg(LCD_REG_164, 0x0001); - up_mdelay(100); - stm3210e_writereg(LCD_REG_96, 0xa700); - stm3210e_writereg(LCD_REG_8, 0x0808); - - /* Gamma Setting */ - - stm3210e_writereg(LCD_REG_48, 0x0203); - stm3210e_writereg(LCD_REG_49, 0x080f); - stm3210e_writereg(LCD_REG_50, 0x0401); - stm3210e_writereg(LCD_REG_51, 0x050b); - stm3210e_writereg(LCD_REG_52, 0x3330); - stm3210e_writereg(LCD_REG_53, 0x0b05); - stm3210e_writereg(LCD_REG_54, 0x0005); - stm3210e_writereg(LCD_REG_55, 0x0f08); - stm3210e_writereg(LCD_REG_56, 0x0302); - stm3210e_writereg(LCD_REG_57, 0x3033); - - /* Power Setting */ - - stm3210e_writereg(LCD_REG_144, 0x0018); /* 80Hz */ - stm3210e_writereg(LCD_REG_16, 0x0530); /* BT, AP */ - stm3210e_writereg(LCD_REG_17, 0x0237); /* DC1,DC0,VC */ - stm3210e_writereg(LCD_REG_18, 0x01bf); - stm3210e_writereg(LCD_REG_19, 0x1000); /* VCOM */ - up_mdelay(200); - - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ - stm3210e_writereg(LCD_REG_2, 0x0200); - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_9, 0x0001); - stm3210e_writereg(LCD_REG_10, 0x0008); - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ - stm3210e_writereg(LCD_REG_13, 0xd000); - stm3210e_writereg(LCD_REG_14, 0x0030); - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ - stm3210e_writereg(LCD_REG_32, 0x0000); /* H Start */ - stm3210e_writereg(LCD_REG_33, 0x0000); /* V Start */ - stm3210e_writereg(LCD_REG_41, 0x002e); - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x005f); - stm3210e_writereg(LCD_REG_147, 0x0701); - - stm3210e_writereg(LCD_REG_7, 0x0000); /* Display OFF */ - } - else -#endif - { -#ifndef CONFIG_STM3210E_AM240320_DISABLE - /* Set the LCD type for the AM240320 */ - - g_lcddev.type = LCD_TYPE_AM240320; - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3210e_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - stm3210e_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3210e_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3210e_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3210e_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3210e_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve */ - - stm3210e_writereg(LCD_REG_48, 0x0006); - stm3210e_writereg(LCD_REG_49, 0x0101); - stm3210e_writereg(LCD_REG_50, 0x0003); - stm3210e_writereg(LCD_REG_53, 0x0106); - stm3210e_writereg(LCD_REG_54, 0x0b02); - stm3210e_writereg(LCD_REG_55, 0x0302); - stm3210e_writereg(LCD_REG_56, 0x0707); - stm3210e_writereg(LCD_REG_57, 0x0007); - stm3210e_writereg(LCD_REG_60, 0x0600); - stm3210e_writereg(LCD_REG_61, 0x020b); - - /* Set GRAM area */ - - stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3210e_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3210e_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3210e_writereg(LCD_REG_128, 0x0000); - stm3210e_writereg(LCD_REG_129, 0x0000); - stm3210e_writereg(LCD_REG_130, 0x0000); - stm3210e_writereg(LCD_REG_131, 0x0000); - stm3210e_writereg(LCD_REG_132, 0x0000); - stm3210e_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3210e_writereg(LCD_REG_144, 0x0010); - stm3210e_writereg(LCD_REG_146, 0x0000); - stm3210e_writereg(LCD_REG_147, 0x0003); - stm3210e_writereg(LCD_REG_149, 0x0110); - stm3210e_writereg(LCD_REG_151, 0x0000); - stm3210e_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3210e_writereg(LCD_REG_3, 0x1018); - stm3210e_writereg(LCD_REG_7, 0); /* Display off */ -#else - lcderr("ERROR: Unsupported LCD type\n"); -#endif - } -} - -/**************************************************************************** - * Name: stm3210e_backlight - * - * Description: - * The LCD backlight is driven from PA8 which must be configured as TIM1 - * CH1. TIM1 must then be configured to output a clock on PA8; the duty - * of the clock determineds the backlight level. - * - ****************************************************************************/ - -#ifdef CONFIG_STM3210E_LCD_BACKLIGHT -static void stm3210e_backlight(void) -{ -#ifdef CONFIG_STM3210E_LCD_PWM - uint32_t prescaler; - uint32_t reload; - uint32_t timclk; - uint16_t bdtr; - uint16_t ccmr; - uint16_t ccer; - uint16_t cr2; - - /* Calculate the TIM1 prescaler value */ - - prescaler = (STM32_PCLK2_FREQUENCY / CONFIG_STM3210E_LCD_PWMFREQUENCY + - 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - /* Calculate the TIM1 reload value */ - - timclk = STM32_PCLK2_FREQUENCY / prescaler; - reload = timclk / CONFIG_STM3210E_LCD_PWMFREQUENCY; - - if (reload < 1) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - - g_lcddev.reload = reload; - - /* Configure PA8 as TIM1 CH1 output */ - - stm32_configgpio(GPIO_TIM1_CH1OUT); - - /* Enabled timer 1 clocking */ - - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - - /* Reset timer 1 */ - - modifyreg32(STM32_RCC_APB2RSTR, 0, RCC_APB2RSTR_TIM1RST); - modifyreg32(STM32_RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM1_CR1); - - /* Set the Autoreload value */ - - putreg16(reload - 1, STM32_TIM1_ARR); - - /* Set the Prescaler value */ - - putreg16(prescaler - 1, STM32_TIM1_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM1_EGR); - - /* Reset the Repetition Counter value */ - - putreg16(0, STM32_TIM1_RCR); - - /* Set the main output enable (MOE) bit and clear the OSSI and OSSR - * bits in the BDTR register. - */ - - bdtr = getreg16(STM32_TIM1_BDTR); - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - bdtr |= ATIM_BDTR_MOE; - putreg16(bdtr, STM32_TIM1_BDTR); - - /* Disable the Channel 1 */ - - ccer = getreg16(STM32_TIM1_CCER); - ccer &= ~ATIM_CCER_CC1E; - putreg16(ccer, STM32_TIM1_CCER); - - /* Get the TIM1 CR2 register value */ - - cr2 = getreg16(STM32_TIM1_CR2); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM1_CCMR1); - ccmr &= ATIM_CCMR1_OC1M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT); - ccmr |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - - /* Set the power to the minimum value */ - - g_lcddev.power = 0; - putreg16(0, STM32_TIM1_CCR1); - - /* Select the output polarity level == LOW and enable */ - - ccer |= (ATIM_CCER_CC1E); - - /* Reset the Output N Polarity level */ - - ccer &= ~(ATIM_CCER_CC1NP | ATIM_CCER_CC1NE); - - /* Reset the Output Compare and Output Compare N IDLE State */ - - cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N); - - /* Write the timer configuration */ - - putreg16(cr2, STM32_TIM1_CR2); - putreg16(ccmr, STM32_TIM1_CCMR1); - putreg16(ccer, STM32_TIM1_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM1_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer */ - - ccer |= ATIM_CR1_CEN; - putreg16(ccer, STM32_TIM1_CR1); - - /* Dump timer1 registers */ - - lcdinfo("APB2ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB2ENR)); - lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR1)); - lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR2)); - lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SMCR)); - lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM1_DIER)); - lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SR)); - lcdinfo("BDTR: %04" PRIx32 "\n", getreg32(STM32_TIM1_BDTR)); - lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR1)); - lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR2)); - lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCER)); - lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM1_CNT)); - lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM1_PSC)); - lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM1_ARR)); - lcdinfo("RCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_RCR)); - lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR1)); - lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR2)); - lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR3)); - lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR4)); - lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM1_DMAR)); -#endif -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ -#ifdef CONFIG_PM - int ret; -#endif - - ginfo("Initializing\n"); - - /* Register to receive power management callbacks */ - -#ifdef CONFIG_PM - ret = pm_register(&g_lcdcb); - if (ret != OK) - { - lcderr("ERROR: pm_register failed: %d\n", ret); - } -#endif - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3210e_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3210e_lcdclear(0); - - /* Turn the backlight off */ - - stm3210e_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. This - * allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3210e_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3210e_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3210e_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3210e_setcursor(0, STM3210E_XRES - 1); - stm3210e_gramselect(); - for (i = 0; i < STM3210E_XRES * STM3210E_YRES; i++) - { - LCD->value = color; - } -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c deleted file mode 100644 index 56d005a627cd3..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c +++ /dev/null @@ -1,372 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED State Controls */ - -static inline void led_clrbits(unsigned int clrbits); -static inline void led_setbits(unsigned int setbits); -static void led_setonoff(unsigned int bits); - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_clrbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_setbits - * - * Description: - * Set all LEDs to the bit encoded state - * - ****************************************************************************/ - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Name: led_setonoff - * - * Description: - * Set/clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: stm32_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c b/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c deleted file mode 100644 index 867ea413b5c35..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm3210e-eval.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pmbuttons(); -#endif - - /* Initialize the LED PM */ - - stm32_ledpminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c deleted file mode 100644 index 20fd76a4af25f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c +++ /dev/null @@ -1,181 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" -#include "stm3210e-eval.h" - -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_BUTTONS -# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" -#endif - -#define BUTTON_MIN 0 -#ifdef CONFIG_INPUT_DJOYSTICK -# define BUTTON_MAX 2 -#else -# define BUTTON_MAX 7 -#endif - -#ifndef CONFIG_PM_BUTTONS_MIN -# define CONFIG_PM_BUTTONS_MIN BUTTON_MIN -#endif -#ifndef CONFIG_PM_BUTTONS_MAX -# define CONFIG_PM_BUTTONS_MAX BUTTON_MAX -#endif - -#if CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX -# error "CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX" -#endif - -#if CONFIG_PM_BUTTONS_MAX > BUTTON_MAX -# error "CONFIG_PM_BUTTONS_MAX > BUTTON_MAX" -#endif - -#ifndef CONFIG_ARCH_IRQBUTTONS -# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_PM_IRQBUTTONS_MIN -# define CONFIG_PM_IRQBUTTONS_MIN CONFIG_PM_BUTTONS_MIN -#endif - -#ifndef CONFIG_PM_IRQBUTTONS_MAX -# define CONFIG_PM_IRQBUTTONS_MAX CONFIG_PM_BUTTONS_MAX -#endif - -#if CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX -# error "CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX" -#endif - -#if CONFIG_PM_IRQBUTTONS_MAX > 7 -# error "CONFIG_PM_IRQBUTTONS_MAX > 7" -#endif - -#ifndef CONFIG_PM_BUTTON_ACTIVITY -# define CONFIG_PM_BUTTON_ACTIVITY 10 -#endif - -/* Miscellaneous Definitions ************************************************/ - -#define MIN_BUTTON MIN(CONFIG_PM_BUTTONS_MIN, CONFIG_PM_IRQBUTTONS_MIN) -#define MAX_BUTTON MAX(CONFIG_PM_BUTTONS_MAX, CONFIG_PM_IRQBUTTONS_MAX) - -#define NUM_PMBUTTONS (MAX_BUTTON - MIN_BUTTON + 1) -#define BUTTON_INDEX(b) ((b)-MIN_BUTTON) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -/**************************************************************************** - * Name: button_handler - * - * Description: - * Handle a button wake-up interrupt - * - ****************************************************************************/ - -static int button_handler(int irq, void *context, void *arg) -{ - /* At this point the MCU should have already awakened. The state - * change will be handled in the IDLE loop when the system is re-awakened - * The button interrupt handler should be totally ignorant of the PM - * activities and should report button activity as if nothing - * special happened. - */ - - pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); - return 0; -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmbuttons - * - * Description: - * Configure all the buttons of the STM3210e-eval board as EXTI, - * so any button is able to wakeup the MCU from the PM_STANDBY mode - * - ****************************************************************************/ - -void stm32_pmbuttons(void) -{ -#ifdef CONFIG_ARCH_IRQBUTTONS - int ret; - int i; -#endif - - /* Initialize the button GPIOs */ - - board_button_initialize(); - -#ifdef CONFIG_ARCH_IRQBUTTONS - for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) - { - ret = board_button_irq(i, button_handler, (void *)i); - if (ret < 0) - { - serr("ERROR: board_button_irq failed: %d\n", ret); - } - } -#endif -} - -#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c deleted file mode 100644 index d128d108edd35..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* GPIO configurations unique to the LCD */ - -static const uint16_t g_lcdconfig[] = -{ - /* NE4 */ - - GPIO_NPS_NE4 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint16_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank4 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN, STM32_FSMC_BCR4); - - /* Bank4 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); - - putreg32(0xffffffff, STM32_FSMC_BWTR4); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c deleted file mode 100644 index 3569e423e7c53..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3210e-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and - * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of - * SRAM, respectively. - * - * Pin Usage (per schematic) - * FLASH SRAM NAND LCD - * D[0..15] [0..15] [0..15] [0..7] [0..15] - * A[0..23] [0..22] [0..18] [16,17] [0] - * FSMC_NBL0 PE0 OUT ~BLE --- --- --- - * FSMC_NBL1 PE1 OUT ~BHE --- --- --- - * FSMC_NE2 PG9 OUT --- ~E --- --- - * FSMC_NE3 PG10 OUT ~CE --- --- --- - * FSMC_NE4 PG12 OUT --- --- --- ~CS - * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL - * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD - * FSMC_NWAIT PD6 IN --- R~B --- --- - * FSMC_INT2 PG6* IN --- --- R~B --- - * - * *JP7 will switch to PD6 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint16_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(3) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_MWID16 | - FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c deleted file mode 100644 index 61a21c6674ab2..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c +++ /dev/null @@ -1,146 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI1 - /* Configure the SPI-based FLASH CS GPIO */ - - stm32_configgpio(GPIO_FLASH_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - if (devid == SPIDEV_FLASH(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_FLASH_CS, !selected); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c deleted file mode 100644 index ba8518ef085f2..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3210e-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the STM3210E-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup: PB.14 */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. Alternatively, if no pull-up GPIO the following EXTERN can be - * redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c deleted file mode 100644 index 6abb8c388fe2f..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32.h" - -/* There is nothing to do here if SDIO support is not selected. */ - -#ifdef CONFIG_STM32_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/* SLOT number(s) could depend on the board configuration */ - -#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL -# undef STM32_MMCSDSLOTNO -# define STM32_MMCSDSLOTNO 0 -#else -/* Add configuration for new STM32 boards here */ - -# error "Unrecognized STM32 board" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void); - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - struct sdio_dev_s *sdio; - int ret; - - /* First, get an instance of the SDIO interface */ - - syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - STM32_MMCSDSLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", - CONFIG_SYSTEM_USBMSC_DEVMINOR1); - - ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - return ret; - } - - syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); - - /* Then let's guess and say that there is a card in the slot. - * I need to check to see if the STM3210E-EVAL board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - -#endif /* CONFIG_NSH_BUILTIN_APPS */ - - return OK; -} - -#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh b/boards/arm/stm32/stm3210e-eval/tools/oocd.sh deleted file mode 100755 index 66a7cca63d08a..0000000000000 --- a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/CMakeLists.txt deleted file mode 100644 index 70278d3238c1b..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig deleted file mode 100644 index 4e5992c98af68..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DHCPD=y -CONFIG_EXAMPLES_DHCPD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="dhcpd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_DHCPD=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig deleted file mode 100644 index 29550b5cd4246..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nettest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NET=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig deleted file mode 100644 index b1df69ce5e01d..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig deleted file mode 100644 index 57d9b07abc807..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig deleted file mode 100644 index 068d4c090decd..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_BACKGROUND_IMAGE="" -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig deleted file mode 100644 index 43b76f0b4da57..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3220g-eval" -CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F2=y -CONFIG_ARCH_CHIP_STM32F207IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=10926 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NSH_LIBRARY=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2012 -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3220g-eval/include/board.h b/boards/arm/stm32/stm3220g-eval/include/board.h deleted file mode 100644 index 86ebef53bb08b..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/include/board.h +++ /dev/null @@ -1,552 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four clock sources are available on STM3220G-EVAL evaluation board for - * STM32F207IGH6 and RTC embedded: - * - * X1, 25 MHz crystal for ethernet PHY with socket. - * It can be removed when clock is provided by MCO pin of the MCU - * X2, 26 MHz crystal for USB OTG HS PHY - * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller - * (It can be removed from socket when internal RC clock is used.) - * - * This is the "standard" configuration as set up by - * arch/arm/src/stm32f40xx_rcc.c: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL - * configuration - * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 240 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 240 - * = 240,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 240,000,000 / 2 = 120,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 240,000,000 / 5 = 48,000,000 - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) - -#define STM32_SYSCLK_FREQUENCY 120000000ul - -/* AHB clock (HCLK) is SYSCLK (120MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)= 16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* Ethernet *****************************************************************/ - -/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ - -#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) - -# if !defined(CONFIG_STM32_MII) -# warning "CONFIG_STM32_MII required for Ethernet" -# elif !defined(CONFIG_STM32_MII_MCO1) -# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" -# else - - /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ - -# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE -# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE - -# endif -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3220G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3220G-EVAL supports three buttons: */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_USER 2 - -#define NUM_BUTTONS 3 - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* UART3: - * - * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) - * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX - */ - -#ifdef CONFIG_STM32_USART3 -# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) -# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) -#endif - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - * - PH2 is ETH_MII_CRS - * - PH3 is ETH_MII_COL - * - PI10 is ETH_MII_RX_ER - * - PH6 is ETH_MII_RXD2 - * - PH7 is ETH_MII_RXD3 - * - PC3 is ETH_MII_TX_CLK - * - PC2 is ETH_MII_TXD2 - * - PB8 is ETH_MII_TXD3 - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM3220G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using the following: - * - * If FSMC is not used: - * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT - * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, - * pin 33 -- not available unless you bridge SB14. - * - * TIM1 CH1OUT: PE9 FSMC_D6 - * Daughterboard Extension Connector, CN2, pin 24 - * - * TIM1_CH2OUT: PE11 FSMC_D8 - * Daughterboard Extension Connector, CN2, pin 26 - * - * TIM1_CH3OUT: PE13 FSMC_D10 - * Daughterboard Extension Connector, CN2, pin 28 - * - * TIM1_CH4OUT: PE14 FSMC_D11 - * Daughterboard Extension Connector, CN2, pin 29 - * - * If OTG FS is not used - * - * TIM1_CH3OUT: PA10 OTG_FS_ID - * Daughterboard Extension Connector, CN3, pin 14 - * - * TIM1_CH4OUT: PA11 OTG_FS_DM - * Daughterboard Extension Connector, CN3, pin 11 - * - * If DMCI is not used - * - * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC - * Daughterboard Extension Connector, CN4, pin 4 - * - * TIM8_CH2OUT: PI6 DCMI_D6 & MC - * Daughterboard Extension Connector, CN4, pin 3 - * - * TIM8_CH3OUT: PI7 DCMI_D7 & MC - * Daughterboard Extension Connector, CN4, pin 2 - * - * If SDIO is not used - * - * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC - * Daughterboard Extension Connector, CN3, pin 18 - * - * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) - * Daughterboard Extension Connector, CN3, pin 17 - * - * Others - * - * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) - */ - -#if !defined(CONFIG_STM32_FSMC) -# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) -#elif !defined(CONFIG_STM32_OTGFS) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -#if !defined(CONFIG_STM32_DCMI) -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) -#else -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) -# if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) -# endif -#endif - -#if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -/* CAN - * - * Connector 10 (CN10) - * is DB-9 male connector that can be used with CAN1 or CAN2. - * - * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver - * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver - * - * CAN signals are then available on CN10 pins: - * - * CN10 Pin 7 = CANH - * CN10 Pin 2 = CANL - * - * Mapping to STM32 GPIO pins: - * - * PD0 = FSMC_D2 & CAN1_RX - * PD1 = FSMC_D3 & CAN1_TX - * PB13 = ULPI_D6 & CAN2_TX - * PB5 = ULPI_D7 & CAN2_RX - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) - -/* I2C. - * Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are - * available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* FSMC (LCD/SRAM) */ - -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3220g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3220g_lcdclear(uint16_t color); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs deleted file mode 100644 index f0aa8af0b8ece..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3220g-eval/scripts/ld.script b/boards/arm/stm32/stm3220g-eval/scripts/ld.script deleted file mode 100644 index 0133f9415af2a..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/ld.script +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F207IGH6U has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 128Kb of SRAM. SRAM is split up into two blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt deleted file mode 100644 index 7f0321dd1b8b0..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt +++ /dev/null @@ -1,69 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_FSMC) - list( - APPEND - SRCS - stm32_lcd.c - stm32_selectlcd.c - stm32_deselectlcd.c - stm32_selectsram.c - stm32_deselectsram.c - stm32_extmem.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3220g-eval/src/Make.defs b/boards/arm/stm32/stm3220g-eval/src/Make.defs deleted file mode 100644 index e77785ac6fa58..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/Make.defs +++ /dev/null @@ -1,63 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c deleted file mode 100644 index d3bfcd0a171d3..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC3 -# warning "Channel information only available for ADC3" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The STM3220G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of - * STM32F207IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = -{ - 7 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC3_NCHANNELS] = -{ - GPIO_ADC3_IN7 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC3 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC3_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c deleted file mode 100644 index 2cd09b07a13c2..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c deleted file mode 100644 index a3693105506b6..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c +++ /dev/null @@ -1,368 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* MMCSD PORT and SLOT number probably depend on the board configuration */ - -#define HAVE_USBDEV 1 -#define HAVE_MMCSD 1 -#define HAVE_USBHOST 1 - -#if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -#endif - -#ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -#endif - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef HAVE_MMCSD -#endif - -#ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* If the FSMC is enabled, then enable SRAM access */ - -#ifdef CONFIG_STM32_FSMC - stm32_selectsram(); -#endif - - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) the weak function stm32_usbinitialize() has been brought into the - * build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - -#ifdef CONFIG_STM32_OTGFS - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); - return; - } - - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); - return; - } - -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - -#ifdef HAVE_MMCSD - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - return; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return; - } - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the STM3220G-EVAL board supports a GPIO to detect if - * there is a card in the slot. - */ - - sdio_mediachange(sdio, true); -#endif - - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - -#ifdef HAVE_USBHOST - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c deleted file mode 100644 index 8c177aa3ed484..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm3220g-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c b/boards/arm/stm32/stm3220g-eval/src/stm32_can.c deleted file mode 100644 index 0145c3b0a5180..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c deleted file mode 100644 index a6239db7ecf93..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c deleted file mode 100644 index 9c0696c984911..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable SRAM - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c deleted file mode 100644 index 1b61bc8e50235..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c deleted file mode 100644 index 2828d7eb76848..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs on the STM324xG_EVAL board: - * - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# define CONFIG_LCD_MAXPOWER 1 -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_LANDSCAPE) -# ifdef CONFIG_LCD_RLANDSCAPE -# error "Cannot define both landscape and any other orientations" -# endif -#elif !defined(CONFIG_LCD_RLANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# define STM3220G_XRES 320 -# define STM3220G_YRES 240 -#else -# define STM3220G_XRES 240 -# define STM3220G_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3220G_BPP 16 -#define STM3220G_COLORFMT FB_FMT_RGB16_565 - -/* STM3220G-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ - -#define STM3220G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) -#define LCD ((struct lcd_regs_s *)STM3220G_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define ILI9320_ID 0x9320 -#define ILI9321_ID 0x9321 -#define ILI9325_ID 0x9325 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_ILI9320, - LCD_TYPE_ILI9325 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3220g_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3220g_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3220g_readreg(uint8_t regaddr); -static inline void stm3220g_gramselect(void); -static inline void stm3220g_writegram(uint16_t rgbval); -static void stm3220g_readnosetup(uint16_t *accum); -static uint16_t stm3220g_readnoshift(uint16_t *accum); -static void stm3220g_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3220g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels); -static int stm3220g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels); - -/* LCD Configuration */ - -static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3220g_getpower(struct lcd_dev_s *dev); -static int stm3220g_setpower(struct lcd_dev_s *dev, int power); -static int stm3220g_getcontrast(struct lcd_dev_s *dev); -static int stm3220g_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* Initialization */ - -static inline void stm3220g_lcdinitialize(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3220G_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3220G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3220G_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3220G_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3220g_putrun, /* Put a run into LCD memory */ - .getrun = stm3220g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3220G_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3220g_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3220g_getvideoinfo, - .getplaneinfo = stm3220g_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3220g_getpower, - .setpower = stm3220g_setpower, - .getcontrast = stm3220g_getcontrast, - .setcontrast = stm3220g_setcontrast, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3220g_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3220g_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3220g_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3220g_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3220g_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3220g_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3220g_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3220g_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - ILI932x: Discard first dummy read; no shift in the return data - * - ****************************************************************************/ - -static void stm3220g_readnosetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. - * Possibly shifting the data and possibly swapping red and green - * components. - * - * - ILI932x: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -static uint16_t stm3220g_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} - -/**************************************************************************** - * Name: stm3220g_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3220g_setcursor(uint16_t col, uint16_t row) -{ - stm3220g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3220g_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3220g_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The LCD device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3220g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - /* Write the GRAM data, manually incrementing X */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(col, row); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - col = (STM3220G_XRES - 1) - col; - row = (STM3220G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3220g_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3220g_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position - * (auto-decrements to the next column) - */ - - stm3220g_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the - * bottom of the board). - */ - - col = (STM3220G_XRES - 1) - col; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3220G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - stm3220g_writegram(*src++); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The LCD device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3220g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type. - * Kind of silly with only one LCD type. - */ - - switch (g_lcddev.type) - { - case LCD_TYPE_ILI9320: - case LCD_TYPE_ILI9325: - readsetup = stm3220g_readnosetup; - readgram = stm3220g_readnoshift; - break; - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3220G-EVAL is used as the top. - */ - - col = (STM3220G_XRES - 1) - col; - row = (STM3220G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3220g_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3220g_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position - * (autoincrements to the next row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are - * at the bottom of the board). - */ - - col = (STM3220G_XRES - 1) - col; - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are - * at the bottom of the board). - */ - - row = (STM3220G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3220g_setcursor(row, col); - stm3220g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getpower - * - * Description: - * Get the LCD panel power status - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_getpower(struct lcd_dev_s *dev) -{ - lcdinfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3220g_poweroff - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_poweroff(void) -{ - /* Turn the display off */ - - stm3220g_writereg(LCD_REG_7, 0); - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3220g_setpower - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3220g_setpower(struct lcd_dev_s *dev, int power) -{ - lcdinfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - /* Then turn the display on */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) - stm3220g_writereg(LCD_REG_7, 0x0173); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3220g_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3220g_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3220g_getcontrast(struct lcd_dev_s *dev) -{ - lcdinfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3220g_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3220g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - lcdinfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3220g_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3220g_lcdinitialize(void) -{ - uint16_t id; - - /* Check LCD ID */ - - id = stm3220g_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) -#elif !defined(CONFIG_STM32_ILI9320_DISABLE) && defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID) -#else /* if defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE)) */ - if (id == ILI9325_ID) -#endif - { - /* Save the LCD type (not actually used at for anything important) */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) - if (id == ILI9325_ID) - { - g_lcddev.type = LCD_TYPE_ILI9325; - } - else -# endif - { - g_lcddev.type = LCD_TYPE_ILI9320; - stm3220g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - } -#else /* if !defined(CONFIG_STM32_ILI9325_DISABLE) */ - g_lcddev.type = LCD_TYPE_ILI9325; -#endif - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3220g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3220g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3220g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3220g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - - /* stm3220g_writereg(LCD_REG_3, 0x1018); - * Set GRAM write direction and BGR=1. - */ - - stm3220g_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3220g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3220g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3220g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3220g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3220g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3220g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3220g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3220g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3220g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3220g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3220g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3220g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3220g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3220g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3220g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (ILI9320/1) */ - -#if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif - { - stm3220g_writereg(LCD_REG_48, 0x0006); - stm3220g_writereg(LCD_REG_49, 0x0101); - stm3220g_writereg(LCD_REG_50, 0x0003); - stm3220g_writereg(LCD_REG_53, 0x0106); - stm3220g_writereg(LCD_REG_54, 0x0b02); - stm3220g_writereg(LCD_REG_55, 0x0302); - stm3220g_writereg(LCD_REG_56, 0x0707); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0600); - stm3220g_writereg(LCD_REG_61, 0x020b); - } -#endif - - /* Adjust the Gamma Curve (ILI9325) */ - -#if !defined(CONFIG_STM32_ILI9325_DISABLE) -# if !defined(CONFIG_STM32_ILI9320_DISABLE) - else -# endif - { - stm3220g_writereg(LCD_REG_48, 0x0007); - stm3220g_writereg(LCD_REG_49, 0x0302); - stm3220g_writereg(LCD_REG_50, 0x0105); - stm3220g_writereg(LCD_REG_53, 0x0206); - stm3220g_writereg(LCD_REG_54, 0x0808); - stm3220g_writereg(LCD_REG_55, 0x0206); - stm3220g_writereg(LCD_REG_56, 0x0504); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0105); - stm3220g_writereg(LCD_REG_61, 0x0808); - } -#endif - - /* Set GRAM area */ - - stm3220g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3220g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3220g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3220g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3220g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - - /* stm3220g_writereg(LCD_REG_96, 0xa700); - * Gate Scan Line(GS=1, scan direction is G320~G1) - */ - - stm3220g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3220g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3220g_writereg(LCD_REG_128, 0x0000); - stm3220g_writereg(LCD_REG_129, 0x0000); - stm3220g_writereg(LCD_REG_130, 0x0000); - stm3220g_writereg(LCD_REG_131, 0x0000); - stm3220g_writereg(LCD_REG_132, 0x0000); - stm3220g_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3220g_writereg(LCD_REG_144, 0x0010); - stm3220g_writereg(LCD_REG_146, 0x0000); - stm3220g_writereg(LCD_REG_147, 0x0003); - stm3220g_writereg(LCD_REG_149, 0x0110); - stm3220g_writereg(LCD_REG_151, 0x0000); - stm3220g_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3220g_writereg(LCD_REG_3, 0x1018); - stm3220g_writereg(LCD_REG_7, 0); /* Display off */ - } - else - { - lcderr("ERROR: Unsupported LCD type\n"); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3220g_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3220g_lcdclear(0); - - /* Turn the display off */ - - stm3220g_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3220g_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3220g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the stm3220g-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can - * be very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3220g_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3220g_setcursor(0, STM3220G_XRES - 1); - stm3220g_gramselect(); - for (i = 0; i < STM3220G_XRES * STM3220G_YRES; i++) - { - LCD->value = color; - } -} - -#endif /* !CONFIG_STM32_ILI9320_DISABLE || !CONFIG_STM32_ILI9325_DISABLE */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c b/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c deleted file mode 100644 index 546c8335f2d74..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM3220G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using variously unused pins on the - * board for PWM output (see board.h for details of pins). - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM3220G_EVAL_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c deleted file mode 100644 index 45603a50da54c..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 -#define LCD_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin Usage (per schematic) - * SRAM LCD - * D[0..15] [0..15] [0..15] - * A[0..25] [0..22] [0] RS - * FSMC_NBL0 PE0 OUT --- --- - * FSMC_NBL1 PE1 OUT --- --- - * FSMC_NE2 PG9 OUT --- --- - * FSMC_NE3 PG10 OUT --- ~CS - * FSMC_NE4 PG12 OUT --- --- - * FSMC_NWE PD5 OUT --- ~WR/SCL - * FSMC_NOE PD4 OUT --- ~RD - * FSMC_NWAIT PD6 IN --- --- - * FSMC_INT2 PG6* IN --- --- - * FSMC_INT3 - * FSMC_INTR - * FSMC_CD - * FSMC_CLK - * FSMC_NCE2 - * FSMC_NCE3 - * FSMC_NCE4_1 - * FSMC_NCE4_2 - * FSMC_NIORD - * FSMC_NIOWR - * FSMC_NL - * FSMC_NREG - */ - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* NOE, NWE, and NE3 */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank3 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank3 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c deleted file mode 100644 index 5c1553a1aa4f5..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM Timing */ - -#define SRAM_ADDRESS_SETUP_TIME 3 -#define SRAM_ADDRESS_HOLD_TIME 1 -#define SRAM_DATA_SETUP_TIME 6 -#define SRAM_BUS_TURNAROUND_DURATION 1 -#define SRAM_CLK_DIVISION 1 -#define SRAM_DATA_LATENCY 2 - -/* SRAM pin definitions */ - -#define SRAM_NADDRLINES 21 -#define SRAM_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIOs Configuration ****************************************************** - * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 - * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 - * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 - * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 - * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 - * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 - * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 - * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 - * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 - * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 - * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 - * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 - * PE15 <-> FSMC_D12 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint32_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC - * Bank NOR/SRAM2 base address (0x64000000) - * - * General transaction rules. The requested AHB transaction data size can - * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data - * width. Some simple transaction rules must be followed: - * - * Case 1: AHB transaction width and SRAM data width are equal - * There is no issue in this case. - * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller - * consecutive memory accesses in order to meet the external data width. - * Case 3: AHB transaction size is smaller than the memory size. - * SRAM supports the byte select feature. - * a) FSMC allows write transactions accessing the right data through its - * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire - * memory word and uses the needed byte only). The NBL[1:0] are always - * kept low during read transactions. - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ - stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration - * - * Bank enable : Not yet - * Data address mux : Disabled - * Memory Type : PSRAM - * Data bus width : 16-bits - * Flash access : Disabled - * Burst access mode : Disabled - * Polarity : Low - * Wrapped burst mode : Disabled - * Write timing : Before state - * Write enable : Yes - * Wait signal : Disabled - * Extended mode : Disabled - * Asynchronous wait : Disabled - * Write burst : Disabled - */ - - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN), STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | - FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | - FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | - FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | - FSMC_BTR_ACCMODA), - STM32_FSMC_BTR2); - - /* Bank1 NOR/SRAM timing register for write configuration, - * if extended mode is used - */ - - putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ - - /* Enable the bank */ - - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c deleted file mode 100644 index 5d99e643455bc..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c +++ /dev/null @@ -1,130 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c deleted file mode 100644 index 190e897501de7..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm3220g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C1 -# error "STMPE811 support requires CONFIG_STM32_I2C1" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 1 -#endif - -#if CONFIG_STMPE811_I2CDEV != 1 -# error "CONFIG_STMPE811_I2CDEV must be one" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and loss- - * of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. We will use it when EXTI interruptsare enabled */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c deleted file mode 100644 index 3252daf95d926..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm3220g-eval.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3220G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ -#ifdef HAVE_USB - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c b/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c deleted file mode 100644 index 9a69e756ae071..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3220g-eval.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh b/boards/arm/stm32/stm3220g-eval/tools/oocd.sh deleted file mode 100755 index 66a7cca63d08a..0000000000000 --- a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/env bash - -# Get command line parameters - -USAGE="USAGE: $0 [-dh] " -ADVICE="Try '$0 -h' for more information" - -while [ ! -z "$1" ]; do - case $1 in - -d ) - set -x - ;; - -h ) - echo "$0 is a tool for generation of proper version files for the NuttX build" - echo "" - echo $USAGE - echo "" - echo "Where:" - echo " -d" - echo " Enable script debug" - echo " -h" - echo " show this help message and exit" - echo " Use the OpenOCD 0.4.0" - echo " " - echo " The full path to the top-level NuttX directory" - exit 0 - ;; - * ) - break; - ;; - esac - shift -done - -TOPDIR=$1 -if [ -z "${TOPDIR}" ]; then - echo "Missing argument" - echo $USAGE - echo $ADVICE - exit 1 -fi - -# This script *probably* only works with the following versions of OpenOCD: - -# Local search directory and configurations - -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" -OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" - -OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" -OPENOCD_EXE=openocd.exe -OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" - -OPENOCD_TARGET="stm32.cfg" -OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" - -echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" - -# Verify that everything is what it claims it is and is located where it claims it is. - -if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then - echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then - echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" - exit 1 -fi -if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then - echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" - exit 1 -fi - -# Enable debug if so requested - -if [ "X$2" = "X-d" ]; then - OPENOCD_ARGS=$OPENOCD_ARGS" -d3" - set -x -fi - -# Okay... do it! - -echo "Starting OpenOCD" -"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & -echo "OpenOCD daemon started" -ps -ef | grep openocd -echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/CMakeLists.txt deleted file mode 100644 index 823f2be9fe84e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig deleted file mode 100644 index ef5bf8ed08713..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DHCPD=y -CONFIG_EXAMPLES_DHCPD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="dhcpd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_DHCPD=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig deleted file mode 100644 index b17d7f63105d1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISCOVER_DESCR="STM3240G-EVAL" -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_DISCOVER=y -CONFIG_EXAMPLES_DISCOVER_DHCPC=y -CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80201 -CONFIG_EXAMPLES_DISCOVER_NOMAC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="discover_main" -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig deleted file mode 100644 index 95c71a7752181..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_PDCURSES=y -CONFIG_FS_PROCFS=y -CONFIG_GRAPHICS_PDCURSES=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0x64000000 -CONFIG_HEAP2_SIZE=2097152 -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PDCURSES_FONT_6X9=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=9 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs deleted file mode 100644 index c8ecd22e21e7c..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs +++ /dev/null @@ -1,40 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld - -ARCHCXXFLAGS += -fpermissive -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig deleted file mode 100644 index 0e2ea7668494e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NXWM_NXTERM is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LIBC_USRWORK=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NUTTX_USERSPACE=0x08040000 -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXSTART_SERVERSTACK=1596 -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm3240g-eval/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig deleted file mode 100644 index 9a38a060c90f7..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_NETTEST_NOMAC=y -CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nettest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_NETLIB=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig deleted file mode 100644 index 1b212f135dc02..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig deleted file mode 100644 index 3c038271c3336..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_SDIO=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig deleted file mode 100644 index 52d25eaf5fa92..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_NXTERM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0x64000000 -CONFIG_HEAP2_SIZE=2097152 -CONFIG_HOST_WINDOWS=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxterm_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=256 -CONFIG_NXTK_BORDERCOLOR1=0xad55 -CONFIG_NXTK_BORDERCOLOR2=0x6b4d -CONFIG_NXTK_BORDERCOLOR3=0xdedb -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig deleted file mode 100644 index 416c842d4c472..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ /dev/null @@ -1,122 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_FSMC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_MULTIPLE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig deleted file mode 100644 index 24e0a378c3819..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 -CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 -CONFIG_EXAMPLES_TELNETD_NOMAC=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="telnetd_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NSH_LIBRARY=y -CONFIG_NUNGET_CHARS=0 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DFU=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig deleted file mode 100644 index 133e6f23b899c..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_EXAMPLES_NETTEST=y -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="webserver_main" -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MTD=y -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART3=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig deleted file mode 100644 index 353a903f228b1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm3240g-eval" -CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407IG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_XMLRPC=y -CONFIG_EXAMPLES_XMLRPC_DHCPC=y -CONFIG_EXAMPLES_XMLRPC_NOMAC=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_POLLED=y -CONFIG_INIT_ENTRYPOINT="xmlrpc_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT_ENTRIES=4 -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=650 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=196608 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART3_RXBUFSIZE=128 -CONFIG_USART3_SERIAL_CONSOLE=y -CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm3240g-eval/include/board.h b/boards/arm/stm32/stm3240g-eval/include/board.h deleted file mode 100644 index 895059dfce0ec..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/include/board.h +++ /dev/null @@ -1,603 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H -#define __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Logic in arch/arm/src and boards/ may need to include these file prior to - * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be - * included here because board.h is used in other contexts where the STM32 - * internal header files are not available. - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four clock sources are available on STM3240G-EVAL evaluation board for - * STM32F407IGH6 and RTC embedded: - * - * X1, 25 MHz crystal for Ethernet PHY with socket. - * It can be removed when clock is provided by MCO pin of the MCU - * X2, 26 MHz crystal for USB OTG HS PHY - * X3, 32 kHz crystal for embedded RTC - * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller - * (It can be removed from socket when internal RC clock is used.) - * - * This is the "standard" configuration as set up by - * arch/arm/src/stm32f40xx_rcc.c: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL - * configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 25MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8-11 are on APB2, others on APB1 - */ - -#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN -#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN -#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN -#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN - -#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN -#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN -#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN -#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN -#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* Ethernet *****************************************************************/ - -/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ - -#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) - -# if !defined(CONFIG_STM32_MII) -# warning "CONFIG_STM32_MII required for Ethernet" -# elif !defined(CONFIG_STM32_MII_MCO1) -# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" -# else - - /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ - -# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE -# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE - -# endif -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the STM3240G-EVAL. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM3240G-EVAL supports three buttons: */ - -#define BUTTON_WAKEUP 0 -#define BUTTON_TAMPER 1 -#define BUTTON_USER 2 - -#define NUM_BUTTONS 3 - -#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* SRAM definitions *********************************************************/ - -/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares - * the same I/Os with the CAN1 bus. Jumper settings: - * - * JP1: Connect PE4 to SRAM as A20 - * JP2: onnect PE3 to SRAM as A19 - * - * JP3 and JP10 must not be fitted for SRAM and LCD application. - * JP3 and JP10 select CAN1 or CAN2 if fitted; neither if not fitted. - */ - -#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) -# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) -# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM" -# endif -#endif - -/* This is the Bank1 SRAM2 address: */ - -#define BOARD_SRAM_BASE 0x64000000 -#define BOARD_SRAM_SIZE (2*1024*1024) - -/* Alternate function pin selections ****************************************/ - -/* UART3: - * - * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) - * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX - */ - -#define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) -#define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) - -/* Ethernet: - * - * - PA2 is ETH_MDIO - * - PC1 is ETH_MDC - * - PB5 is ETH_PPS_OUT - * - PH2 is ETH_MII_CRS - * - PH3 is ETH_MII_COL - * - PI10 is ETH_MII_RX_ER - * - PH6 is ETH_MII_RXD2 - * - PH7 is ETH_MII_RXD3 - * - PC3 is ETH_MII_TX_CLK - * - PC2 is ETH_MII_TXD2 - * - PB8 is ETH_MII_TXD3 - * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK - * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV - * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 - * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 - * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN - * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 - * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 - */ - -#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) - -/* PWM - * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using the following: - * - * If FSMC is not used: - * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT - * Daughterboard Extension Connector, CN3, pin 32 - * Motor Control Connector CN15, - * pin 33 -- not available unless you bridge SB14. - * - * TIM1 CH1OUT: PE9 FSMC_D6 - * Daughterboard Extension Connector, CN2, pin 24 - * - * TIM1_CH2OUT: PE11 FSMC_D8 - * Daughterboard Extension Connector, CN2, pin 26 - * - * TIM1_CH3OUT: PE13 FSMC_D10 - * Daughterboard Extension Connector, CN2, pin 28 - * - * TIM1_CH4OUT: PE14 FSMC_D11 - * Daughterboard Extension Connector, CN2, pin 29 - * - * If OTG FS is not used - * - * TIM1_CH3OUT: PA10 OTG_FS_ID - * Daughterboard Extension Connector, CN3, pin 14 - * - * TIM1_CH4OUT: PA11 OTG_FS_DM - * Daughterboard Extension Connector, CN3, pin 11 - * - * If DMCI is not used - * - * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC - * Daughterboard Extension Connector, CN4, pin 4 - * - * TIM8_CH2OUT: PI6 DCMI_D6 & MC - * Daughterboard Extension Connector, CN4, pin 3 - * - * TIM8_CH3OUT: PI7 DCMI_D7 & MC - * Daughterboard Extension Connector, CN4, pin 2 - * - * If SDIO is not used - * - * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC - * Daughterboard Extension Connector, CN3, pin 18 - * - * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) - * Daughterboard Extension Connector, CN3, pin 17 - * - * Others - * - * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) - */ - -#if !defined(CONFIG_STM32_FSMC) -# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) -#elif !defined(CONFIG_STM32_OTGFS) -# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) -# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -#if !defined(CONFIG_STM32_DCMI) -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) -#else -# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) -# if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) -# endif -#endif - -#if !defined(CONFIG_STM32_SDIO) -# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) -#endif - -/* CAN - * - * Connector 10 (CN10) - * is DB-9 male connector that can be used with CAN1 or CAN2. - * - * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver - * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver - * - * CAN signals are then available on CN10 pins: - * - * CN10 Pin 7 = CANH - * CN10 Pin 2 = CANL - * - * Mapping to STM32 GPIO pins: - * - * PD0 = FSMC_D2 & CAN1_RX - * PD1 = FSMC_D3 & CAN1_TX - * PB13 = ULPI_D6 & CAN2_TX - * PB5 = ULPI_D7 & CAN2_RX - */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) - -#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) - -/* I2C. - * Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are - * available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3240g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the STM3210E-EVAL board. - * Because of the various rotations, clearing the display in the normal - * way by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_FSMC -void stm3240g_lcdclear(uint16_t color); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/* ETH MII/RMII inputs and MDC/MDIO + MCO1 */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* FSMC SRAM/LCD */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm3240g-eval/kernel/Makefile b/boards/arm/stm32/stm3240g-eval/kernel/Makefile deleted file mode 100644 index 3aba5389f39f0..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c deleted file mode 100644 index f50a59be45218..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08040000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08040000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs deleted file mode 100644 index 091ebb2629a44..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld b/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld deleted file mode 100644 index 92d718a435cb1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/ld.script b/boards/arm/stm32/stm3240g-eval/scripts/ld.script deleted file mode 100644 index 250db269b1f74..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld b/boards/arm/stm32/stm3240g-eval/scripts/memory.ld deleted file mode 100644 index 7eeff47560d99..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 256Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256K - xflash (rx) : ORIGIN = 0x08080000, LENGTH = 512K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K - usram (rwx) : ORIGIN = 0x20001800, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002800, LENGTH = 102K -} diff --git a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld b/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld deleted file mode 100644 index 80a6572aa6493..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt deleted file mode 100644 index c8c5aa4f724e1..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt +++ /dev/null @@ -1,62 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c) - list(APPEND SRCS stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm3240g-eval/src/Make.defs b/boards/arm/stm32/stm3240g-eval/src/Make.defs deleted file mode 100644 index 04d1ecfdd0b22..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c -CSRCS += stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c deleted file mode 100644 index bfeaca3cf336d..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c +++ /dev/null @@ -1,157 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 3 ADC interfaces are supported */ - -#if STM32_NADC < 3 -# undef CONFIG_STM32_ADC3 -#endif - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) -#ifndef CONFIG_STM32_ADC3 -# warning "Channel information only available for ADC3" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The STM3240G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of - * STM32F407IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 - */ - -/* Identifying number of each ADC channel: Variable Resistor. */ - -#ifdef CONFIG_STM32_ADC3 -static const uint8_t g_chanlist[ADC3_NCHANNELS] = -{ - 7 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC3_NCHANNELS] = -{ - GPIO_ADC3_IN7 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC3 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC3_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c deleted file mode 100644 index fc90a9ad31930..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM3210E_LED1 (1 << 0) -#define STM3210E_LED2 (1 << 1) -#define STM3210E_LED3 (1 << 2) -#define STM3210E_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM3210E_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM3210E_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM3210E_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM3210E_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c deleted file mode 100644 index 4f59c13c407ec..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm3240g-eval.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) - * the weak function stm32_spidev_initialize() has been brought into the - * link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_FSMC - /* If the FSMC is enabled, then enable SRAM access */ - - stm32_selectsram(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought the weak function stm32_usbinitialize() has been brought into - * the build. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - stm32_led_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform the board initialization on the start-up thread. Some - * initializations may fail in this case due to the limited capability of - * the start-up thread. - */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c deleted file mode 100644 index 016041c919078..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c +++ /dev/null @@ -1,390 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -#endif - -#ifdef CONFIG_STM32_SDIO -# include -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_INPUT_STMPE811 -# include -#endif - -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* For now, don't build in any SPI1 support -- NSH is not using it */ - -#undef CONFIG_STM32_SPI1 - -/* Assume that we support everything until convinced otherwise */ - -#define HAVE_MMCSD 1 -#define HAVE_USBDEV 1 -#define HAVE_USBHOST 1 -#define HAVE_RTC_DRIVER 1 - -/* Can't support MMC/SD features if mountpoints are disabled or if SDIO - * support is not enabled. - */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) -# undef HAVE_MMCSD -#endif - -/* Default MMC/SD minor number */ - -#ifdef HAVE_MMCSD -# ifndef CONFIG_NSH_MMCSDMINOR -# define CONFIG_NSH_MMCSDMINOR 0 -# endif - -/* Default MMC/SD SLOT number */ - -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 -# error "Only one MMC/SD slot" -# undef CONFIG_NSH_MMCSDSLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO 0 -# endif -#endif - -/* Can't support USB host or device features if USB OTG FS is not enabled */ - -#ifndef CONFIG_STM32_OTGFS -# undef HAVE_USBDEV -# undef HAVE_USBHOST -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Can't support USB host is USB host is not enabled */ - -#ifndef CONFIG_USBHOST -# undef HAVE_USBHOST -#endif - -/* Check if we can support the RTC driver */ - -#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) -# undef HAVE_RTC_DRIVER -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - _err("ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#ifdef HAVE_I2CTOOL -static void stm32_i2ctool(void) -{ -#ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); -#endif -#ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); -#endif -#ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif -#ifdef CONFIG_STM32_SPI1 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; -#endif -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; -#endif - int ret; - - /* Register I2C drivers on behalf of the I2C tool */ - - stm32_i2ctool(); - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - syslog(LOG_ERR, - "ERROR: Failed to instantiate the RTC lower-half driver\n"); - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to bind/register the RTC driver: %d\n", - ret); - } - } -#endif - - /* Configure SPI-based devices */ - -#ifdef CONFIG_STM32_SPI1 - /* Get the SPI port */ - - spi = stm32_spibus_initialize(1); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); - } - else - { - /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ - - mtd = m25p_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SPI port 0 to SPI FLASH driver\n"); - } - } - -#warning "Now what are we going to do with this SPI FLASH driver?" -#endif - -#ifdef HAVE_MMCSD - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); - if (!sdio) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SDIO slot %d\n", - CONFIG_NSH_MMCSDSLOTNO); - } - else - { - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", - ret); - } - - /* Then let's guess and say that there is a card in the slot. I need - * to check to see if the STM3240G-EVAL board supports a GPIO to - * detect if there is a card in the slot. - */ - - sdio_mediachange(sdio, true); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread that will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the simulated framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen. - * WARNING: stm32_tsc_setup() cannot be called from the IDLE thread. - */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c b/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c deleted file mode 100644 index 66f45af683705..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c +++ /dev/null @@ -1,164 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm3240g-eval.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. - * The exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - if (i == BUTTON_WAKEUP) - { - released = !released; - } - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c b/boards/arm/stm32/stm3240g-eval/src/stm32_can.c deleted file mode 100644 index 53e357df19c8e..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c deleted file mode 100644 index dc9cee810b60a..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectlcd - * - * Description: - * Disable the LCD - * - ****************************************************************************/ - -void stm32_deselectlcd(void) -{ - /* Restore registers to their power up settings */ - - putreg32(0xffffffff, STM32_FSMC_BCR4); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(0x0fffffff, STM32_FSMC_BTR4); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c deleted file mode 100644 index 6f8840bedfb60..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_deselectsram - * - * Description: - * Disable SRAM - * - ****************************************************************************/ - -void stm32_deselectsram(void) -{ - /* Restore registers to their power up settings */ - - putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); - - /* Disable AHB clocking to the FSMC */ - - stm32_fsmc_disable(); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c deleted file mode 100644 index dd6d6b4163f87..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c deleted file mode 100644 index 8ab6c22e6addb..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ /dev/null @@ -1,1188 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This driver supports the following LCDs on the STM324xG_EVAL board: - * - * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR - * AM-240320D5TOQW01H (LCD_ILI9325) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the - * AM-240320L8TNQW00H(LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the - * AM-240320D5TOQW01H(LCD_ILI9325) - */ - -/* Check contrast selection */ - -#if !defined(CONFIG_LCD_MAXCONTRAST) -# define CONFIG_LCD_MAXCONTRAST 1 -#endif - -/* Check power setting */ - -#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 -# define CONFIG_LCD_MAXPOWER 1 -#endif - -#if CONFIG_LCD_MAXPOWER > 255 -# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" -#endif - -/* Check orientation */ - -#if defined(CONFIG_LCD_PORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) -# error "Cannot define both portrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_RPORTRAIT) -# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# error "Cannot define both rportrait and any other orientations" -# endif -#elif defined(CONFIG_LCD_LANDSCAPE) -# ifdef CONFIG_LCD_RLANDSCAPE -# error "Cannot define both landscape and any other orientations" -# endif -#elif !defined(CONFIG_LCD_RLANDSCAPE) -# define CONFIG_LCD_LANDSCAPE 1 -#endif - -/* Display/Color Properties *************************************************/ - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) -# define STM3240G_XRES 320 -# define STM3240G_YRES 240 -#else -# define STM3240G_XRES 240 -# define STM3240G_YRES 320 -#endif - -/* Color depth and format */ - -#define STM3240G_BPP 16 -#define STM3240G_COLORFMT FB_FMT_RGB16_565 - -/* STM3240G-EVAL LCD Hardware Definitions ***********************************/ - -/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ - -#define STM3240G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) -#define LCD ((struct lcd_regs_s *)STM3240G_LCDBASE) - -#define LCD_REG_0 0x00 -#define LCD_REG_1 0x01 -#define LCD_REG_2 0x02 -#define LCD_REG_3 0x03 -#define LCD_REG_4 0x04 -#define LCD_REG_5 0x05 -#define LCD_REG_6 0x06 -#define LCD_REG_7 0x07 -#define LCD_REG_8 0x08 -#define LCD_REG_9 0x09 -#define LCD_REG_10 0x0a -#define LCD_REG_12 0x0c -#define LCD_REG_13 0x0d -#define LCD_REG_14 0x0e -#define LCD_REG_15 0x0f -#define LCD_REG_16 0x10 -#define LCD_REG_17 0x11 -#define LCD_REG_18 0x12 -#define LCD_REG_19 0x13 -#define LCD_REG_20 0x14 -#define LCD_REG_21 0x15 -#define LCD_REG_22 0x16 -#define LCD_REG_23 0x17 -#define LCD_REG_24 0x18 -#define LCD_REG_25 0x19 -#define LCD_REG_26 0x1a -#define LCD_REG_27 0x1b -#define LCD_REG_28 0x1c -#define LCD_REG_29 0x1d -#define LCD_REG_30 0x1e -#define LCD_REG_31 0x1f -#define LCD_REG_32 0x20 -#define LCD_REG_33 0x21 -#define LCD_REG_34 0x22 -#define LCD_REG_36 0x24 -#define LCD_REG_37 0x25 -#define LCD_REG_40 0x28 -#define LCD_REG_41 0x29 -#define LCD_REG_43 0x2b -#define LCD_REG_45 0x2d -#define LCD_REG_48 0x30 -#define LCD_REG_49 0x31 -#define LCD_REG_50 0x32 -#define LCD_REG_51 0x33 -#define LCD_REG_52 0x34 -#define LCD_REG_53 0x35 -#define LCD_REG_54 0x36 -#define LCD_REG_55 0x37 -#define LCD_REG_56 0x38 -#define LCD_REG_57 0x39 -#define LCD_REG_58 0x3a -#define LCD_REG_59 0x3b -#define LCD_REG_60 0x3c -#define LCD_REG_61 0x3d -#define LCD_REG_62 0x3e -#define LCD_REG_63 0x3f -#define LCD_REG_64 0x40 -#define LCD_REG_65 0x41 -#define LCD_REG_66 0x42 -#define LCD_REG_67 0x43 -#define LCD_REG_68 0x44 -#define LCD_REG_69 0x45 -#define LCD_REG_70 0x46 -#define LCD_REG_71 0x47 -#define LCD_REG_72 0x48 -#define LCD_REG_73 0x49 -#define LCD_REG_74 0x4a -#define LCD_REG_75 0x4b -#define LCD_REG_76 0x4c -#define LCD_REG_77 0x4d -#define LCD_REG_78 0x4e -#define LCD_REG_79 0x4f -#define LCD_REG_80 0x50 -#define LCD_REG_81 0x51 -#define LCD_REG_82 0x52 -#define LCD_REG_83 0x53 -#define LCD_REG_96 0x60 -#define LCD_REG_97 0x61 -#define LCD_REG_106 0x6a -#define LCD_REG_118 0x76 -#define LCD_REG_128 0x80 -#define LCD_REG_129 0x81 -#define LCD_REG_130 0x82 -#define LCD_REG_131 0x83 -#define LCD_REG_132 0x84 -#define LCD_REG_133 0x85 -#define LCD_REG_134 0x86 -#define LCD_REG_135 0x87 -#define LCD_REG_136 0x88 -#define LCD_REG_137 0x89 -#define LCD_REG_139 0x8b -#define LCD_REG_140 0x8c -#define LCD_REG_141 0x8d -#define LCD_REG_143 0x8f -#define LCD_REG_144 0x90 -#define LCD_REG_145 0x91 -#define LCD_REG_146 0x92 -#define LCD_REG_147 0x93 -#define LCD_REG_148 0x94 -#define LCD_REG_149 0x95 -#define LCD_REG_150 0x96 -#define LCD_REG_151 0x97 -#define LCD_REG_152 0x98 -#define LCD_REG_153 0x99 -#define LCD_REG_154 0x9a -#define LCD_REG_157 0x9d -#define LCD_REG_164 0xa4 -#define LCD_REG_192 0xc0 -#define LCD_REG_193 0xc1 -#define LCD_REG_229 0xe5 - -/* LCD IDs */ - -#define ILI9320_ID 0x9320 -#define ILI9321_ID 0x9321 -#define ILI9325_ID 0x9325 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* LCD type */ - -enum lcd_type_e -{ - LCD_TYPE_UNKNOWN = 0, - LCD_TYPE_ILI9320, - LCD_TYPE_ILI9325 -}; - -/* This structure describes the LCD registers */ - -struct lcd_regs_s -{ - volatile uint16_t address; - volatile uint16_t value; -}; - -/* This structure describes the state of this driver */ - -struct stm3240g_dev_s -{ - /* Publicly visible device structure */ - - struct lcd_dev_s dev; - - /* Private LCD-specific information follows */ - - uint8_t type; /* LCD type. See enum lcd_type_e */ - uint8_t power; /* Current power setting */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm3240g_writereg(uint8_t regaddr, uint16_t regval); -static uint16_t stm3240g_readreg(uint8_t regaddr); -static inline void stm3240g_gramselect(void); -static inline void stm3240g_writegram(uint16_t rgbval); -static void stm3240g_readnosetup(uint16_t *accum); -static uint16_t stm3240g_readnoshift(uint16_t *accum); -static void stm3240g_setcursor(uint16_t col, uint16_t row); - -/* LCD Data Transfer Methods */ - -static int stm3240g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels); -static int stm3240g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels); - -/* LCD Configuration */ - -static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo); -static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo); - -/* LCD RGB Mapping */ - -#ifdef CONFIG_FB_CMAP -# error "RGB color mapping not supported by this driver" -#endif - -/* Cursor Controls */ - -#ifdef CONFIG_FB_HWCURSOR -# error "Cursor control not supported by this driver" -#endif - -/* LCD Specific Controls */ - -static int stm3240g_getpower(struct lcd_dev_s *dev); -static int stm3240g_setpower(struct lcd_dev_s *dev, int power); -static int stm3240g_getcontrast(struct lcd_dev_s *dev); -static int stm3240g_setcontrast(struct lcd_dev_s *dev, - unsigned int contrast); - -/* Initialization */ - -static inline void stm3240g_lcdinitialize(void); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is working memory allocated by the LCD driver for each LCD device - * and for each color plane. This memory will hold one raster line of data. - * The size of the allocated run buffer must therefore be at least - * (bpp * xres / 8). Actual alignment of the buffer must conform to the - * bitwidth of the underlying pixel type. - * - * If there are multiple planes, they may share the same working buffer - * because different planes will not be operate on concurrently. However, - * if there are multiple LCD devices, they must each have unique run buffers. - */ - -static uint16_t g_runbuffer[STM3240G_XRES]; - -/* This structure describes the overall LCD video controller */ - -static const struct fb_videoinfo_s g_videoinfo = -{ - .fmt = STM3240G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ - .xres = STM3240G_XRES, /* Horizontal resolution in pixel columns */ - .yres = STM3240G_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ -}; - -/* This is the standard, NuttX Plane information object */ - -static const struct lcd_planeinfo_s g_planeinfo = -{ - .putrun = stm3240g_putrun, /* Put a run into LCD memory */ - .getrun = stm3240g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3240G_BPP, /* Bits-per-pixel */ -}; - -/* This is the standard, NuttX LCD driver object */ - -static struct stm3240g_dev_s g_lcddev = -{ - .dev = - { - /* LCD Configuration */ - - .getvideoinfo = stm3240g_getvideoinfo, - .getplaneinfo = stm3240g_getplaneinfo, - - /* LCD RGB Mapping -- Not supported */ - - /* Cursor Controls -- Not supported */ - - /* LCD Specific Controls */ - - .getpower = stm3240g_getpower, - .setpower = stm3240g_setpower, - .getcontrast = stm3240g_getcontrast, - .setcontrast = stm3240g_setcontrast, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm3240g_writereg - * - * Description: - * Write to an LCD register - * - ****************************************************************************/ - -static void stm3240g_writereg(uint8_t regaddr, uint16_t regval) -{ - /* Write the register address then write the register value */ - - LCD->address = regaddr; - LCD->value = regval; -} - -/**************************************************************************** - * Name: stm3240g_readreg - * - * Description: - * Read from an LCD register - * - ****************************************************************************/ - -static uint16_t stm3240g_readreg(uint8_t regaddr) -{ - /* Write the register address then read the register value */ - - LCD->address = regaddr; - return LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_gramselect - * - * Description: - * Setup to read or write multiple pixels to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3240g_gramselect(void) -{ - LCD->address = LCD_REG_34; -} - -/**************************************************************************** - * Name: stm3240g_writegram - * - * Description: - * Write one pixel to the GRAM memory - * - ****************************************************************************/ - -static inline void stm3240g_writegram(uint16_t rgbval) -{ - /* Write the value (GRAM register already selected) */ - - LCD->value = rgbval; -} - -/**************************************************************************** - * Name: stm3240g_readnosetup - * - * Description: - * Prime the operation by reading one pixel from the GRAM memory if - * necessary for this LCD type. When reading 16-bit gram data, there may - * be some shifts in the returned data: - * - * - ILI932x: Discard first dummy read; no shift in the return data - * - ****************************************************************************/ - -static void stm3240g_readnosetup(uint16_t *accum) -{ - /* Read-ahead one pixel */ - - *accum = LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_readnoshift - * - * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly - * shifting the data and possibly swapping red and green components. - * - * - ILI932x: Unknown -- assuming colors are in the color order - * - ****************************************************************************/ - -static uint16_t stm3240g_readnoshift(uint16_t *accum) -{ - /* Read the value (GRAM register already selected) */ - - return LCD->value; -} - -/**************************************************************************** - * Name: stm3240g_setcursor - * - * Description: - * Set the cursor position. In landscape mode, the "column" is actually - * the physical Y position and the "row" is the physical X position. - * - ****************************************************************************/ - -static void stm3240g_setcursor(uint16_t col, uint16_t row) -{ - stm3240g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ - stm3240g_writereg(LCD_REG_33, col); /* GRAM vertical address */ -} - -/**************************************************************************** - * Name: stm3240g_putrun - * - * Description: - * This method can be used to write a partial raster line to the LCD: - * - * dev - The lcd device - * row - Starting row to write to (range: 0 <= row < yres) - * col - Starting column to write to (range: 0 <= col <= xres-npixels) - * buffer - The buffer containing the run to be written to the LCD - * npixels - The number of pixels to write to the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3240g_putrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - const uint8_t *buffer, size_t npixels) -{ - const uint16_t *src = (const uint16_t *)buffer; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Write the run to GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - /* Write the GRAM data, manually incrementing X */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(col, row); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - col = (STM3240G_XRES - 1) - col; - row = (STM3240G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3240g_setcursor(col, row); - - /* Then write the GRAM data, auto-decrementing X */ - - stm3240g_gramselect(); - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position - * (auto-decrements to the next column) - */ - - stm3240g_writegram(*src++); - } -#elif defined(CONFIG_LCD_PORTRAIT) - - /* Convert coordinates. - * In this configuration, the top of the display is to the left of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - col = (STM3240G_XRES - 1) - col; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3240G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - stm3240g_writegram(*src++); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getrun - * - * Description: - * This method can be used to read a partial raster line from the LCD: - * - * dev - The lcd device - * row - Starting row to read from (range: 0 <= row < yres) - * col - Starting column to read read (range: 0 <= col <= xres-npixels) - * buffer - The buffer in which to return the run read from the LCD - * npixels - The number of pixels to read from the LCD - * (range: 0 < npixels <= xres-col) - * - ****************************************************************************/ - -static int stm3240g_getrun(struct lcd_dev_s *dev, - fb_coord_t row, fb_coord_t col, - uint8_t *buffer, size_t npixels) -{ - uint16_t *dest = (uint16_t *)buffer; - void (*readsetup)(uint16_t *accum); - uint16_t (*readgram)(uint16_t *accum); - uint16_t accum; - int i; - - /* Buffer must be provided and aligned to a 16-bit address boundary */ - - lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); - DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - - /* Configure according to the LCD type. - * Kind of silly with only one LCD type. - */ - - switch (g_lcddev.type) - { - case LCD_TYPE_ILI9320: - case LCD_TYPE_ILI9325: - readsetup = stm3240g_readnosetup; - readgram = stm3240g_readnoshift; - break; - - default: /* Shouldn't happen */ - return -ENOSYS; - } - - /* Read the run from GRAM. */ - -#ifdef CONFIG_LCD_LANDSCAPE - /* Convert coordinates -- Here the edge away from the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col++; - } -#elif defined(CONFIG_LCD_RLANDSCAPE) - /* Convert coordinates -- Here the edge next to the row of buttons on - * the STM3240G-EVAL is used as the top. - */ - - col = (STM3240G_XRES - 1) - col; - row = (STM3240G_YRES - 1) - row; - - /* Set the cursor position */ - - stm3240g_setcursor(col, row); - - /* Then read the GRAM data, auto-decrementing Y */ - - stm3240g_gramselect(); - - /* Prime the pump for unaligned read data */ - - readsetup(&accum); - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position - * (autoincrements to the next row) - */ - - *dest++ = readgram(&accum); - } -#elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. - * In this configuration, the top of the display is to the left of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - col = (STM3240G_XRES - 1) - col; - - /* Then read the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Read the next pixel from this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Increment to next column */ - - col--; - } -#else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. - * In this configuration, the top of the display is to the right of the - * buttons (if the board is held so that the buttons are at the bottom of - * the board). - */ - - row = (STM3240G_YRES - 1) - row; - - /* Then write the GRAM data, manually incrementing Y (which is col) */ - - for (i = 0; i < npixels; i++) - { - /* Write the next pixel to this position */ - - stm3240g_setcursor(row, col); - stm3240g_gramselect(); - readsetup(&accum); - *dest++ = readgram(&accum); - - /* Decrement to next column */ - - col++; - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getvideoinfo - * - * Description: - * Get information about the LCD video controller configuration. - * - ****************************************************************************/ - -static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, - struct fb_videoinfo_s *vinfo) -{ - DEBUGASSERT(dev && vinfo); - lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, - g_videoinfo.yres, g_videoinfo.nplanes); - memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getplaneinfo - * - * Description: - * Get information about the configuration of each LCD color plane. - * - ****************************************************************************/ - -static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, - unsigned int planeno, - struct lcd_planeinfo_s *pinfo) -{ - DEBUGASSERT(dev && pinfo && planeno == 0); - lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); - memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); - pinfo->dev = dev; - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getpower - * - * Description: - * Get the LCD panel power status - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_getpower(struct lcd_dev_s *dev) -{ - lcdinfo("power: %d\n", 0); - return g_lcddev.power; -} - -/**************************************************************************** - * Name: stm3240g_poweroff - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_poweroff(void) -{ - /* Turn the display off */ - - stm3240g_writereg(LCD_REG_7, 0); - - /* Remember the power off state */ - - g_lcddev.power = 0; - return OK; -} - -/**************************************************************************** - * Name: stm3240g_setpower - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, - * this setting may correspond to the backlight setting. - * - ****************************************************************************/ - -static int stm3240g_setpower(struct lcd_dev_s *dev, int power) -{ - lcdinfo("power: %d\n", power); - DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - /* Then turn the display on */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) - stm3240g_writereg(LCD_REG_7, 0x0173); -#endif - g_lcddev.power = power; - } - else - { - /* Turn the display off */ - - stm3240g_poweroff(); - } - - return OK; -} - -/**************************************************************************** - * Name: stm3240g_getcontrast - * - * Description: - * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3240g_getcontrast(struct lcd_dev_s *dev) -{ - lcdinfo("Not implemented\n"); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3240g_setcontrast - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) -{ - lcdinfo("contrast: %d\n", contrast); - return -ENOSYS; -} - -/**************************************************************************** - * Name: stm3240g_lcdinitialize - * - * Description: - * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). - * - ****************************************************************************/ - -static inline void stm3240g_lcdinitialize(void) -{ - uint16_t id; - - /* Check LCD ID */ - - id = stm3240g_readreg(LCD_REG_0); - lcdinfo("LCD ID: %04x\n", id); - - /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) -#elif !defined(CONFIG_STM3240G_ILI9320_DISABLE) && defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9320_ID || id == ILI9321_ID) -#else /* if defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE)) */ - if (id == ILI9325_ID) -#endif - { - /* Save the LCD type - * (not actually used at for anything important) - */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (id == ILI9325_ID) - { - g_lcddev.type = LCD_TYPE_ILI9325; - } - else -# endif - { - g_lcddev.type = LCD_TYPE_ILI9320; - stm3240g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ - } -#else /* if !defined(CONFIG_STM3240G_ILI9325_DISABLE) */ - g_lcddev.type = LCD_TYPE_ILI9325; -#endif - lcdinfo("LCD type: %d\n", g_lcddev.type); - - /* Start Initial Sequence */ - - stm3240g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ - stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ - stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ - stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - - /* stm3240g_writereg(LCD_REG_3, 0x1018); - * Set GRAM write direction and BGR=1. - */ - - stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */ - stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ - stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ - stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ - stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ - stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ - stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ - - /* Power On sequence */ - - stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ - stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ - stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ - up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ - - stm3240g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ - stm3240g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ - stm3240g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ - up_mdelay(50); - - stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ - stm3240g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ - - /* Adjust the Gamma Curve (ILI9320/1) */ - -#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif - { - stm3240g_writereg(LCD_REG_48, 0x0006); - stm3240g_writereg(LCD_REG_49, 0x0101); - stm3240g_writereg(LCD_REG_50, 0x0003); - stm3240g_writereg(LCD_REG_53, 0x0106); - stm3240g_writereg(LCD_REG_54, 0x0b02); - stm3240g_writereg(LCD_REG_55, 0x0302); - stm3240g_writereg(LCD_REG_56, 0x0707); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0600); - stm3240g_writereg(LCD_REG_61, 0x020b); - } -#endif - - /* Adjust the Gamma Curve (ILI9325) */ - -#if !defined(CONFIG_STM3240G_ILI9325_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) - else -# endif - { - stm3240g_writereg(LCD_REG_48, 0x0007); - stm3240g_writereg(LCD_REG_49, 0x0302); - stm3240g_writereg(LCD_REG_50, 0x0105); - stm3240g_writereg(LCD_REG_53, 0x0206); - stm3240g_writereg(LCD_REG_54, 0x0808); - stm3240g_writereg(LCD_REG_55, 0x0206); - stm3240g_writereg(LCD_REG_56, 0x0504); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0105); - stm3240g_writereg(LCD_REG_61, 0x0808); - } -#endif - - /* Set GRAM area */ - - stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ - stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ - stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ - stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ - stm3240g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - - /* stm3240g_writereg(LCD_REG_96, 0xa700); - * Gate Scan Line(GS=1, scan direction is G320~G1) - */ - - stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ - stm3240g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ - - /* Partial Display Control */ - - stm3240g_writereg(LCD_REG_128, 0x0000); - stm3240g_writereg(LCD_REG_129, 0x0000); - stm3240g_writereg(LCD_REG_130, 0x0000); - stm3240g_writereg(LCD_REG_131, 0x0000); - stm3240g_writereg(LCD_REG_132, 0x0000); - stm3240g_writereg(LCD_REG_133, 0x0000); - - /* Panel Control */ - - stm3240g_writereg(LCD_REG_144, 0x0010); - stm3240g_writereg(LCD_REG_146, 0x0000); - stm3240g_writereg(LCD_REG_147, 0x0003); - stm3240g_writereg(LCD_REG_149, 0x0110); - stm3240g_writereg(LCD_REG_151, 0x0000); - stm3240g_writereg(LCD_REG_152, 0x0000); - - /* Set GRAM write direction and BGR = 1 - * - * I/D=01 (Horizontal : increment, Vertical : decrement) - * AM=1 (address is updated in vertical writing direction) - */ - - stm3240g_writereg(LCD_REG_3, 0x1018); - stm3240g_writereg(LCD_REG_7, 0); /* Display off */ - } - else - { - lcderr("ERROR: Unsupported LCD type\n"); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, - * but with the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable LCD */ - - up_mdelay(50); - stm3240g_lcdinitialize(); - - /* Clear the display (setting it to the color 0=black) */ - - stm3240g_lcdclear(0); - - /* Turn the display off */ - - stm3240g_poweroff(); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return &g_lcddev.dev; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - stm3240g_poweroff(); - stm32_deselectlcd(); -} - -/**************************************************************************** - * Name: stm3240g_lcdclear - * - * Description: - * This is a non-standard LCD interface just for the stm3240g-EVAL board. - * Because of the various rotations, clearing the display in the normal way - * by writing a sequences of runs that covers the entire display can be - * very slow. Here the display is cleared by simply setting all GRAM - * memory to the specified color. - * - ****************************************************************************/ - -void stm3240g_lcdclear(uint16_t color) -{ - uint32_t i = 0; - - stm3240g_setcursor(0, STM3240G_XRES - 1); - stm3240g_gramselect(); - for (i = 0; i < STM3240G_XRES * STM3240G_YRES; i++) - { - LCD->value = color; - } -} - -#endif /* !CONFIG_STM3240G_ILI9320_DISABLE || !CONFIG_STM3240G_ILI9325_DISABLE */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c b/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c deleted file mode 100644 index 2d4e6393779f2..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM3240G-Eval has no real on-board PWM devices, but the board can be - * configured to output a pulse train using variously unused pins on the - * board for PWM output (see board.h for details of pins). - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM3240G_EVAL_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c deleted file mode 100644 index c3c854d032088..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c +++ /dev/null @@ -1,155 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 -#define LCD_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin Usage (per schematic) - * SRAM LCD - * D[0..15] [0..15] [0..15] - * A[0..25] [0..22] [0] RS - * FSMC_NBL0 PE0 OUT --- --- - * FSMC_NBL1 PE1 OUT --- --- - * FSMC_NE2 PG9 OUT --- --- - * FSMC_NE3 PG10 OUT --- ~CS - * FSMC_NE4 PG12 OUT --- --- - * FSMC_NWE PD5 OUT --- ~WR/SCL - * FSMC_NOE PD4 OUT --- ~RD - * FSMC_NWAIT PD6 IN --- --- - * FSMC_INT2 PG6* IN --- --- - * FSMC_INT3 - * FSMC_INTR - * FSMC_CD - * FSMC_CLK - * FSMC_NCE2 - * FSMC_NCE3 - * FSMC_NCE4_1 - * FSMC_NCE4_2 - * FSMC_NIORD - * FSMC_NIOWR - * FSMC_NL - * FSMC_NREG - */ - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* NOE, NWE, and NE3 */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank3 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); - - /* Bank3 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); - - putreg32(0xffffffff, STM32_FSMC_BWTR3); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c deleted file mode 100644 index 7ffe0a673f738..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c +++ /dev/null @@ -1,186 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_FSMC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -/* SRAM Timing */ - -#define SRAM_ADDRESS_SETUP_TIME 3 -#define SRAM_ADDRESS_HOLD_TIME 1 -#define SRAM_DATA_SETUP_TIME 6 -#define SRAM_BUS_TURNAROUND_DURATION 1 -#define SRAM_CLK_DIVISION 1 -#define SRAM_DATA_LATENCY 2 - -/* SRAM pin definitions */ - -#define SRAM_NADDRLINES 21 -#define SRAM_NDATALINES 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIOs Configuration ****************************************************** - * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 - * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 - * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 - * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 - * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 - * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 - * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 - * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 - * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 - * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 - * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 - * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 - * PE15 <-> FSMC_D12 - */ - -/* GPIO configurations unique to SRAM */ - -static const uint32_t g_sramconfig[] = -{ - /* NE3, NBL0, NBL1, */ - - GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 -}; -#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_selectsram - * - * Description: - * Initialize to access external SRAM. SRAM will be visible at the FSMC - * Bank NOR/SRAM2 base address (0x64000000) - * - * General transaction rules. The requested AHB transaction data size can - * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data - * width. Some simple transaction rules must be followed: - * - * Case 1: AHB transaction width and SRAM data width are equal - * There is no issue in this case. - * Case 2: AHB transaction size is greater than the memory size - * In this case, the FSMC splits the AHB transaction into smaller - * consecutive memory accesses in order to meet the external data width. - * Case 3: AHB transaction size is smaller than the memory size. - * SRAM supports the byte select feature. - * a) FSMC allows write transactions accessing the right data through its - * byte lanes (NBL[1:0]) - * b) Read transactions are allowed (the controller reads the entire - * memory word and uses the needed byte only). The NBL[1:0] are always - * kept low during read transactions. - * - ****************************************************************************/ - -void stm32_selectsram(void) -{ - /* Configure new GPIO pins */ - - stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ - stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration - * - * Bank enable : Not yet - * Data address mux : Disabled - * Memory Type : PSRAM - * Data bus width : 16-bits - * Flash access : Disabled - * Burst access mode : Disabled - * Polarity : Low - * Wrapped burst mode : Disabled - * Write timing : Before state - * Write enable : Yes - * Wait signal : Disabled - * Extended mode : Disabled - * Asynchronous wait : Disabled - * Write burst : Disabled - */ - - putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | - FSMC_BCR_WREN), STM32_FSMC_BCR2); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | - FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | - FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | - FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | - FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | - FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | - FSMC_BTR_ACCMODA), - STM32_FSMC_BTR2); - - /* Bank1 NOR/SRAM timing register for write configuration, - * if extended mode is used - */ - - putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ - - /* Enable the bank */ - - putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); -} - -#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c deleted file mode 100644 index c2ca8d2be6b16..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 - * logic. To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return SPI_STATUS_PRESENT; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c deleted file mode 100644 index 87334017a2f77..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm3240g-eval.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C1 -# error "STMPE811 support requires CONFIG_STM32_I2C1" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 1 -#endif - -#if CONFIG_STMPE811_I2CDEV != 1 -# error "CONFIG_STMPE811_I2CDEV must be one" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. - * They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and - * loss-of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. - * We will use it when EXTI interruptsare enabled - */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c deleted file mode 100644 index e09730cee8fa4..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c +++ /dev/null @@ -1,304 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm3240g-eval.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_USBHOST_DEFPRIO -# define CONFIG_USBHOST_DEFPRIO 50 -#endif - -#ifndef CONFIG_USBHOST_STACKSIZE -# ifdef CONFIG_USBHOST_HUB -# define CONFIG_USBHOST_STACKSIZE 1536 -# else -# define CONFIG_USBHOST_STACKSIZE 1024 -# endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM3240G-EVAL board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, - CONFIG_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c b/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c deleted file mode 100644 index 61299ea969ecd..0000000000000 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm3240g-eval.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32_tiny/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/CMakeLists.txt deleted file mode 100644 index 6b35bfde309f2..0000000000000 --- a/boards/arm/stm32/stm32_tiny/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig deleted file mode 100644 index ff2c3f8694598..0000000000000 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32_tiny" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig deleted file mode 100644 index 627a8111f2051..0000000000000 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32_tiny" -CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/stm32_tiny/include/board.h b/boards/arm/stm32/stm32_tiny/include/board.h deleted file mode 100644 index 26354257da2e5..0000000000000 --- a/boards/arm/stm32/stm32_tiny/include/board.h +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H -#define __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* The board has only one controllable LED */ -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* NRF24L01 Driver **********************************************************/ - -/* NRF24L01 chip enable: PB.1 */ - -#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) - -/* NRF24L01 IRQ line: PA.0 */ - -#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE -#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI2 */ - -#define GPIO_SPI2_NSS GPIO_ADJUST_MODE(GPIO_SPI2_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_SCK GPIO_ADJUST_MODE(GPIO_SPI2_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_MISO GPIO_ADJUST_MODE(GPIO_SPI2_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI2_MOSI GPIO_ADJUST_MODE(GPIO_SPI2_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -#endif /* __ARCH_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32_tiny/scripts/Make.defs b/boards/arm/stm32/stm32_tiny/scripts/Make.defs deleted file mode 100644 index 3093bfc93eed8..0000000000000 --- a/boards/arm/stm32/stm32_tiny/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32_tiny/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32_tiny/scripts/ld.script b/boards/arm/stm32/stm32_tiny/scripts/ld.script deleted file mode 100644 index 4ce9e558389d1..0000000000000 --- a/boards/arm/stm32/stm32_tiny/scripts/ld.script +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt deleted file mode 100644 index c73b5cfb5bddf..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c) - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32_tiny/src/Make.defs b/boards/arm/stm32/stm32_tiny/src/Make.defs deleted file mode 100644 index a8268fc340102..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/Make.defs +++ /dev/null @@ -1,33 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32_tiny/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32/stm32_tiny/src/stm32_boot.c deleted file mode 100644 index 978fee88af4d1..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c +++ /dev/null @@ -1,129 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32_tiny.h" - -#ifdef CONFIG_WL_NRF24L01 -#include "stm32_nrf24l01.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = OK; - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_WL_NRF24L01) - /* Initialize the NRF24L01 wireless module */ - - ret = board_nrf24l01_initialize(2); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize failed: %d\n", ret); - } -#endif -} -#endif diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c b/boards/arm/stm32/stm32_tiny/src/stm32_leds.c deleted file mode 100644 index 96ed9bf54df39..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED, v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, - * we simply turn it on when the board boots - */ - - set_led(true); - break; - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c b/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c deleted file mode 100644 index 3a4f9982399d0..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM32 Tiny board provides a LED on GPIO line B5. - */ - -#ifdef CONFIG_PWM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32TINY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c b/boards/arm/stm32/stm32_tiny/src/stm32_spi.c deleted file mode 100644 index ff9d37e515ab3..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32_tiny.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_STM32_SPI2 -# ifdef CONFIG_WL_NRF24L01 - /* Configure the SPI-based NRF24L01 chip select GPIO */ - - spiinfo("Configure GPIO for SPI2/CS\n"); - stm32_configgpio(GPIO_NRF24L01_CS); -# endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted"); - - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - break; -#endif - default: - break; - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - switch (devid) - { -#ifdef CONFIG_WL_NRF24L01 - case SPIDEV_WIRELESS(0): - status |= SPI_STATUS_PRESENT; - break; -#endif - default: - break; - } - - return status; -} - -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c b/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c deleted file mode 100644 index 34a13f0c6fc68..0000000000000 --- a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_tiny.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - uinfo("called\n"); - - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined - * to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/CMakeLists.txt deleted file mode 100644 index 9daf994ef1404..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig deleted file mode 100644 index 00e362af8bce3..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 -CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 -CONFIG_EXAMPLES_MOUNT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig deleted file mode 100644 index 7c9318d5a8d2e..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ /dev/null @@ -1,90 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -# CONFIG_STM32_AUTONEG is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_MOUNT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="butterfly2" -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NET=y -CONFIG_NETINIT_DRIPADDR=0x0a010101 -CONFIG_NETINIT_IPADDR=0x0a010163 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_ETH_PKTSIZE=1500 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOCAL=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PL2303=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ETH100MBPS=y -CONFIG_STM32_ETHFD=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_ETH_REMAP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_MII=y -CONFIG_STM32_MII_EXTCLK=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig deleted file mode 100644 index a75cab61efdc9..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_MOUNT=y -CONFIG_EXAMPLES_USBSERIAL=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PL2303=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig deleted file mode 100644 index 00e362af8bce3..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32butterfly2" -CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_HIDKBD=y -CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 -CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 -CONFIG_EXAMPLES_MOUNT=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBC_STRERROR_SHORT=y -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_MOTD=y -CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_TABCOMPLETION=y -CONFIG_RR_INTERVAL=100 -CONFIG_SCHED_CPULOAD_SYSCLK=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_YEAR=1970 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_REMAP=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSLOG_TIMESTAMP=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_VI=y -CONFIG_TESTING_RAMTEST=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBHOST_HIDKBD=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32butterfly2/include/board.h b/boards/arm/stm32/stm32butterfly2/include/board.h deleted file mode 100644 index 47811ad89f006..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/include/board.h +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - 8 MHz RC factory-trimmed - * LSI - 40 KHz RC (30-60KHz, uncalibrated) - * HSE - On-board crystal frequency is 14.7456MHz - * LSE - LSE is not connected - */ - -#define STM32_BOARD_XTAL 14745600ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000u -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 0 - -/* PLL output is 71.8848MHz */ - -#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d4 -#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx12 -#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d4 -#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx65 -#define STM32_PLL_FREQUENCY 71884800ul - -/* SYSCLK and HCLK adre the PLL frequency */ - -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* USB clock output is 47.9232MHz */ - -#define STM32_CFGR_OTGFSPRE RCC_CFGR_OTGFSPREd3 - -/* APB2 clock (PCLK2) is HCLK */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY - -#define STM32APB_TIM1_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (35.9424MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* There are four LEDs on stm32butterfly2 board that can be controlled by - * software. - * All pulled high and van be illuminated by driving the output low. - * - * LED1 PB0 - * LED2 PB1 - * LED3 PC4 - * LED4 PC5 - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In thath case, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - */ - -#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF ON OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF ON */ -#define LED_INIRQ 5 /* In an interrupt N/C N/C N/C GLOW */ -#define LED_SIGNAL 6 /* In a signal handler N/C N/C N/C GLOW */ -#define LED_ASSERTION 7 /* An assertion failed N/C N/C N/C GLOW */ -#define LED_PANIC 8 /* The system has crashed N/C N/C N/C FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* After booting, LED1-3 are not longer used by the system and can be used - * for other purposes by the application (Of course, all LEDs are available - * to the application if CONFIG_ARCH_LEDS is not defined. - */ - -/* ADC configuration. Right now only ADC12_IN10 is supported - * (potentiometer) - */ - -#ifdef CONFIG_STM32_ADC2 -# error "CONFIG_STM32_ADC2 is not supported" -#endif - -/* SPI configuration. Only SPI1 is supported */ - -#ifdef CONFIG_STM32_SPI2 -# error "CONFIG_STM32_SPI2 is not supported" -#endif - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM GPIO_ADJUST_MODE(GPIO_OTGFS_DM_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_DP GPIO_ADJUST_MODE(GPIO_OTGFS_DP_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_ID GPIO_ADJUST_MODE(GPIO_OTGFS_ID_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_SOF GPIO_ADJUST_MODE(GPIO_OTGFS_SOF_0, GPIO_MODE_50MHz) -#define GPIO_OTGFS_VBUS GPIO_OTGFS_VBUS_0 - -#endif /* __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32/stm32butterfly2/scripts/Make.defs deleted file mode 100644 index 8fe66cdd72fe3..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32butterfly2/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = dfu.ld -else - LDSCRIPT = flash.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld b/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld deleted file mode 100644 index 5901e67a90948..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/dfu.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld b/boards/arm/stm32/stm32butterfly2/scripts/flash.ld deleted file mode 100644 index 57edf7919bc13..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt deleted file mode 100644 index 6e3faeea1a225..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_leds.c) - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_SPI1) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_USBHOST) - list(APPEND SRCS stm32_usbhost.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32/stm32butterfly2/src/Make.defs b/boards/arm/stm32/stm32butterfly2/src/Make.defs deleted file mode 100644 index 04fda674517e8..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/Make.defs +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32butterfly2/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_leds.c - -ifeq ($(CONFIG_STM32_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SPI1),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -CSRCS += stm32_usbhost.c -endif - -ifeq ($(CONFIG_USBDEV),y) -CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c deleted file mode 100644 index 1c15f9556a900..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c +++ /dev/null @@ -1,78 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "stm32_adc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - uint8_t channel[1] = - { - 10 - }; - - struct adc_dev_s *adc; - int rv; - - if (initialized) - { - return OK; - } - - ainfo("INFO: Initializing ADC12_IN10\n"); - stm32_configgpio(GPIO_ADC12_IN10_0); - if ((adc = stm32_adcinitialize(1, channel, 1)) == NULL) - { - aerr("ERROR: Failed to get adc interface\n"); - return -ENODEV; - } - - if ((rv = adc_register("/dev/adc0", adc)) < 0) - { - aerr("ERROR: adc_register failed: %d\n", rv); - return rv; - } - - initialized = true; - ainfo("INFO: ADC12_IN10 initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c deleted file mode 100644 index de6bf256cf4de..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "stm32_butterfly2.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * Initializes low level pins for the drivers. - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - stm32_led_initialize(); - stm32_spidev_initialize(); - stm32_usb_initialize(); -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret = 0; - -#ifdef CONFIG_MMCSD - ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_USBHOST - ret = stm32_usbhost_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c deleted file mode 100644 index 9de138b47b015..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "stm32_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NUM_BUTTONS 5 - -#define GPIO_JOY_O (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN7) -#define GPIO_JOY_U (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN8) -#define GPIO_JOY_D (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN9) -#define GPIO_JOY_R (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN10) -#define GPIO_JOY_L (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ - GPIO_PORTC | GPIO_PIN11) - -/**************************************************************************** - * Private Declarations - ****************************************************************************/ - -static const uint32_t buttons[NUM_BUTTONS] = -{ - GPIO_JOY_O, GPIO_JOY_U, GPIO_JOY_D, GPIO_JOY_R, GPIO_JOY_L -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * Initializes gpio pins for joystick buttons - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - for (i = 0; i != NUM_BUTTONS; ++i) - { - stm32_configgpio(buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * Reads keys - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t rv = 0; - int i; - - for (i = 0; i != NUM_BUTTONS; ++i) - { - if (stm32_gpioread(buttons[i]) == 0) - { - rv |= 1 << i; - } - } - - return rv; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c deleted file mode 100644 index c2d1d4b4f2682..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c +++ /dev/null @@ -1,257 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#define GPIO_LED1 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define GPIO_LED2 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) -#define GPIO_LED3 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN4) -#define GPIO_LED4 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ - GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Identifies led state */ - -enum led_state -{ - LED_ON = false, - LED_OFF = true -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_state - * - * Description: - * Sets pack of leds to given state - ****************************************************************************/ - -static void led_state(enum led_state state, unsigned int leds) -{ - if (leds & BOARD_LED1_BIT) - { - stm32_gpiowrite(GPIO_LED1, state); - } - - if (leds & BOARD_LED2_BIT) - { - stm32_gpiowrite(GPIO_LED2, state); - } - - if (leds & BOARD_LED3_BIT) - { - stm32_gpiowrite(GPIO_LED3, state); - } - - if (leds & BOARD_LED4_BIT) - { - stm32_gpiowrite(GPIO_LED4, state); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - * - * Description: - * Initializes low level gpio pins for board LEDS - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Name: board_autoled_on - * - * Description: - * Drives board leds when specific RTOS state led occurs. - * - * Input Parameters: - * led - This is actually RTOS state not led number of anything like that - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case LED_STARTED: - led_state(LED_OFF, BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED1_BIT); - break; - - case LED_HEAPALLOCATE: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED2_BIT); - break; - - case LED_IRQSENABLED: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); - led_state(LED_ON, BOARD_LED3_BIT); - break; - - case LED_STACKCREATED: - led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT); - led_state(LED_ON, BOARD_LED4_BIT); - break; - - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - led_state(LED_ON, BOARD_LED4_BIT); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - * - * Description: - * Drives board leds when specific RTOS state led ends - * - * Input Parameters: - * led - This is actually RTOS state not led number of anything like that - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_STARTED: - led_state(LED_OFF, BOARD_LED1_BIT); - break; - - case LED_HEAPALLOCATE: - led_state(LED_OFF, BOARD_LED2_BIT); - break; - - case LED_IRQSENABLED: - led_state(LED_OFF, BOARD_LED3_BIT); - break; - - case LED_STACKCREATED: - case LED_INIRQ: - case LED_SIGNAL: - case LED_ASSERTION: - case LED_PANIC: - led_state(LED_OFF, BOARD_LED4_BIT); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_userled_initialize - * - * Description: - * This function should initialize leds for user use, but on RTOS start we - * initialize every led for use by RTOS and at end, when RTOS is fully - * booted up, we give control of these specific leds for user. So that's - * why this function is empty. - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Already initialized by stm32_led_initialize. */ - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - * - * Description: - * Sets led to ledon state. - * - * Input Parameters: - * led - Led to be set, indexed from 0 - * ledon - new state for the led. - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - unsigned int ledbit; - -#ifndef CONFIG_ARCH_LEDS - if (led == BOARD_LED4) - { - return; - } -#endif - - ledbit = 1 << led; - led_state(ledon, ledbit); -} - -/**************************************************************************** - * Name: board_userled_all - * - * Description: - * Sets whole ledset to given state. - * - * Input Parameters: - * ledset - Led bits to be set on or off - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ -#ifdef CONFIG_ARCH_LEDS - led_state(LED_ON, ledset & ~BOARD_LED4_BIT); - led_state(LED_OFF, ~(ledset | BOARD_LED4_BIT)); -#else - led_state(LED_ON, ledset); - led_state(LED_OFF, ~ledset); -#endif -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c deleted file mode 100644 index 50b5bc9ea60a5..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_butterfly2.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_SPI1 -# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" -#endif - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ -static const int SD_SLOT_NO = 0; /* There is only one SD slot */ - -/* Media changed callback */ - -static spi_mediachange_t g_chmediaclbk; - -/* Argument for media changed callback */ - -static void *g_chmediaarg; - -/* Semafor to inform stm32_cd_thread that card was inserted or pulled out */ - -static sem_t g_cdsem = SEM_INITIALIZER(0); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cd_thread - * - * Description: - * Working thread to call mediachanged function when card is inserted or - * pulled out. - ****************************************************************************/ - -static void *stm32_cd_thread(void *arg) -{ - spiinfo("INFO: Running card detect thread\n"); - while (1) - { - nxsem_wait(&g_cdsem); - spiinfo("INFO: Card has been inserted, initializing\n"); - - if (g_chmediaclbk) - { - /* Card doesn't seem to initialize properly without letting it to - * rest for a millisecond or so. - */ - - nxsched_usleep(1 * 1000); - g_chmediaclbk(g_chmediaarg); - } - } - - return NULL; -} - -/**************************************************************************** - * Name: stm32_cd - * - * Description: - * Card detect interrupt handler. - ****************************************************************************/ - -static int stm32_cd(int irq, void *context, void *arg) -{ - static const int debounce_time = 100; /* [ms] */ - static uint32_t now = 0; - static uint32_t prev = 0; - struct timespec tp; - - clock_systime_timespec(&tp); - now = tp.tv_sec * 1000 + tp.tv_nsec / 1000000; - - /* When inserting card, card detect plate might bounce causing this - * interrupt to be called many time on single card insert/deinsert. Thus - * we are allowing only one interrupt every 100ms. - */ - - if (now - debounce_time > prev) - { - prev = now; - nxsem_post(&g_cdsem); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi1 device\n"); - g_chmediaclbk = callback; - g_chmediaarg = arg; - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int minor) -{ - struct spi_dev_s *spi; - struct sched_param schparam; - pthread_attr_t pattr; - int rv; - - spiinfo("INFO: Initializing mmcsd card\n"); - if ((spi = stm32_spibus_initialize(SD_SPI_PORT)) == NULL) - { - ferr("failed to initialize SPI port %d\n", SD_SPI_PORT); - return -ENODEV; - } - - if ((rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi)) < 0) - { - ferr("failed to bind SPI port %d to SD slot %d\n", SD_SPI_PORT, - SD_SLOT_NO); - return rv; - } - - stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); - - pthread_attr_init(&pattr); -#ifdef CONFIG_DEBUG_FS - pthread_attr_setstacksize(&pattr, 1024); -#else - pthread_attr_setstacksize(&pattr, 256); -#endif - - schparam.sched_priority = 50; - pthread_attr_setschedparam(&pattr, &schparam); - pthread_create(NULL, &pattr, stm32_cd_thread, NULL); - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c deleted file mode 100644 index 9044b910a783a..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c +++ /dev/null @@ -1,98 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "stm32_butterfly2.h" -#include "stm32_gpio.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins. - * - * Note: - * Here only CS pins are configured as SPI pins are configured by driver - * itself. - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - spiinfo("INFO: Initializing spi gpio pins\n"); - - stm32_configgpio(GPIO_SD_CS); - stm32_configgpio(GPIO_SD_CD); -} - -/**************************************************************************** - * Name: stm32_spi1select - * - * Description: - * Function asserts given devid based on select - ****************************************************************************/ - -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool select) -{ - spiinfo("INFO: Selecting spi dev: %" PRId32 ", state: %d\n", - devid, select); - - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SD_CS, !select); - } -} - -/**************************************************************************** - * Name: stm32_spi1status - * - * Description: - * Return status of devid - ****************************************************************************/ - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - spiinfo("INFO: Requesting info from spi dev: %" PRId32 "\n", devid); - - if (devid == SPIDEV_MMCSD(0)) - { - if (stm32_gpioread(GPIO_SD_CD) == 0) - { - return SPI_STATUS_PRESENT; - } - } - - return 0; -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c deleted file mode 100644 index 56ebf480d7491..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32_gpio.h" - -#include -#include "stm32_butterfly2.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_initialize - * - * Description: - * Initializes USB pins - ****************************************************************************/ - -void stm32_usb_initialize(void) -{ - uinfo("INFO: Initializing usb otgfs gpio pins\n"); - - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c deleted file mode 100644 index 8bdb6fce116c9..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_OTGFS -# error "CONFIG_USBDEV requires CONFIG_STM32_OTGFS to be enabled" -#endif - -#ifdef CONFIG_USBHOST -# error "CONFIG_USBDEV cannot be set alongside CONFIG_USBHOST" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - * TODO: - * - Well... implement those features like clock shutdown. - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("INFO: usb %s", resume ? "resumed" : "suspended"); -} diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c deleted file mode 100644 index 7d5c6a160e4ae..0000000000000 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32_butterfly2.h" -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_OTGFS -# error "CONFIG_USBHOST requires CONFIG_STM32_OTGFS to be enabled" -#endif - -#ifdef CONFIG_USBDEV -# error "CONFIG_USBHOST cannot be set alongside CONFIG_USBDEV" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct usbhost_connection_s *g_usbconn; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_detect - * - * Description: - * Wait for USB devices to be connected. - ****************************************************************************/ - -static void *usbhost_detect(void *arg) -{ - struct usbhost_hubport_s *hport; - - uinfo("INFO: Starting usb detect thread\n"); - - for (; ; ) - { - CONN_WAIT(g_usbconn, &hport); - - if (hport->connected) - { - CONN_ENUMERATE(g_usbconn, hport); - } - } - - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Initializes USB host functionality. - ****************************************************************************/ - -int stm32_usbhost_initialize(void) -{ - int rv; - -#ifdef CONFIG_USBHOST_MSC - uinfo("INFO: Initializing USB MSC class\n"); - - if ((rv = usbhost_msc_initialize()) < 0) - { - uerr("ERROR: Failed to register mass storage class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_CDACM - uinfo("INFO: Initializing CDCACM usb class\n"); - - if ((rv = usbhost_cdacm_initialize()) < 0) - { - uerr("ERROR: Failed to register CDC/ACM serial class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - uinfo("INFO: Initializing HID Keyboard usb class\n"); - - if ((rv = usbhost_kbdinit()) < 0) - { - uerr("ERROR: Failed to register the KBD class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - uinfo("INFO: Initializing HID Mouse usb class\n"); - - if ((rv = usbhost_mouse_init()) < 0) - { - uerr("ERROR: Failed to register the mouse class: %d\n", rv); - } -#endif - -#ifdef CONFIG_USBHOST_HUB - uinfo("INFO: Initializing USB HUB class\n"); - - if ((rv = usbhost_hub_initialize()) < 0) - { - uerr("ERROR: Failed to register hub class: %d\n", rv); - } -#endif - - if ((g_usbconn = stm32_otgfshost_initialize(0))) - { - pthread_attr_t pattr; - struct sched_param schparam; - - pthread_attr_init(&pattr); - pthread_attr_setstacksize(&pattr, 2048); - - schparam.sched_priority = 50; - pthread_attr_setschedparam(&pattr, &schparam); - - return pthread_create(NULL, &pattr, usbhost_detect, NULL); - } - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. - * - * The application uses this field to control power to this port, and the - * core clears this bit on an overcurrent condition. - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - ****************************************************************************/ - -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); -} diff --git a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt deleted file mode 100644 index d4b2e558d3015..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig deleted file mode 100644 index 60d0b587290f7..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ /dev/null @@ -1,78 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_BINFMT_DISABLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ADBD_DEVICE_ID="test" -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FILE_STREAM=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="adbd_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DFU=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=8 -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig deleted file mode 100644 index 8204b158b8cc1..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_APDS9960=y -CONFIG_FILE_STREAM=y -CONFIG_I2C_DRIVER=y -CONFIG_IDLETHREAD_STACKSIZE=512 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PTHREAD_STACK_MIN=512 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=3072 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_APDS9960=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig deleted file mode 100644 index f6aca5546d964..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_TONE=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_ONESHOT=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig deleted file mode 100644 index cb630b8a5c346..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig deleted file mode 100644 index 8609d8332fb4f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN_ERRORS=y -CONFIG_CAN_EXTID=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_NMSGS=4 -CONFIG_EXAMPLES_CAN_WRITE=y -CONFIG_HOST_MACOS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN_TSEG1=13 -CONFIG_STM32_CAN_TSEG2=2 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig deleted file mode 100644 index 625735d4b99ac..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="hello_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_LINE_MAX=80 -CONFIG_MM_SMALL=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_NOEXT_VECTORS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig deleted file mode 100644 index 07ad100354746..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 -CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_ST7567=y -CONFIG_LINE_MAX=80 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXTK_BORDERWIDTH=1 -CONFIG_NX_BLOCKING=y -CONFIG_NX_WRITEONLY=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig deleted file mode 100644 index e648a558cc3c7..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FILE_STREAM=y -CONFIG_I2C=y -CONFIG_I2CTOOL_DEFFREQ=100000 -CONFIG_I2CTOOL_MAXBUS=1 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD_BACKPACK=y -CONFIG_LCD_LCD1602=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_SLCD=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig deleted file mode 100644 index 226a3fc04215e..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CAN=y -CONFIG_CANUTILS_CANLIB=y -CONFIG_CAN_MCP2515=y -CONFIG_CAN_TXREADY=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_CAN=y -CONFIG_EXAMPLES_CAN_READ=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_MCP2515_PHASESEG1=3 -CONFIG_MCP2515_PROPSEG=1 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig deleted file mode 100644 index c5b2ce959c997..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_EXAMPLES_NRF24L01TERM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig deleted file mode 100644 index 6cce4dd24af19..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig deleted file mode 100644 index 88305a3a2464a..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig deleted file mode 100644 index 82ebe0e454faf..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CL_MFRC522=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_CONTACTLESS=y -CONFIG_EXAMPLES_RFID_READUID=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig deleted file mode 100644 index 0aa109abc0034..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM4_CH4OUT=y -CONFIG_STM32_TIM4_CHANNEL=4 -CONFIG_STM32_TIM4_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig deleted file mode 100644 index d281ac189e745..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_I2C=y -CONFIG_I2C_DRIVER=y -CONFIG_I2C_RESET=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM_TOOLCHAIN=y -CONFIG_LINE_MAX=80 -CONFIG_LTO_FULL=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_DS18B20=y -CONFIG_SENSORS_DS18B20_POLL=y -CONFIG_SENSORS_HYT271=y -CONFIG_SENSORS_HYT271_POLL=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C2=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART2_1WIREDRIVER=y -CONFIG_STM32_USART_SINGLEWIRE=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_SENSORTEST=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig deleted file mode 100644 index a10002a0e1a9f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_CAT is not set -# CONFIG_NSH_DISABLE_CD is not set -# CONFIG_NSH_DISABLE_CP is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_MKDIR is not set -# CONFIG_NSH_DISABLE_MOUNT is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_PWD is not set -# CONFIG_NSH_DISABLE_RM is not set -# CONFIG_NSH_DISABLE_SLEEP is not set -# CONFIG_NSH_DISABLE_TEST is not set -# CONFIG_NSH_DISABLE_UMOUNT is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_SSD1306_I2C=y -CONFIG_LCD_UG2864HSWEG01=y -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig deleted file mode 100644 index d355792be1a69..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DEV_CONSOLE is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USB=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV_TRACE=y -CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig deleted file mode 100644 index a95bf5abb4c02..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_LEDS=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USERLED=y -CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig deleted file mode 100644 index baa759d2c7451..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f103-minimum" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LINE_MAX=80 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=1024 -CONFIG_RAM_SIZE=20480 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_VEML6070=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=7 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f103-minimum/include/board.h b/boards/arm/stm32/stm32f103-minimum/include/board.h deleted file mode 100644 index 36ed8ae7f6979..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/include/board.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is - * 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers 1 and 8 will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* BUTTON definitions *******************************************************/ - -#define NUM_BUTTONS 2 - -#define BUTTON_USER1 0 -#define BUTTON_USER2 1 -#define BUTTON_USER1_BIT (1 << BUTTON_USER1) -#define BUTTON_USER2_BIT (1 << BUTTON_USER2) - -/* LED definitions **********************************************************/ - -/* Define how many LEDs this board has (needed by userleds) */ - -#define BOARD_NLEDS 1 - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED2 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 off */ -#define LED_SIGNAL 5 /* LED2 on */ -#define LED_ASSERTION 6 /* LED1 + LED2 */ -#define LED_PANIC 7 /* LED1 / LED2 blinking */ - -/* PWM - * - * The STM32F103-Minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM3 CH3 on PB0. - * - * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not - * remap pin. - */ - -/* RGB LED - * - * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 - * - * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT - */ - -#define RGBLED_RPWMTIMER 1 -#define RGBLED_RPWMCHANNEL 1 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 2 -#define RGBLED_BPWMTIMER 4 -#define RGBLED_BPWMCHANNEL 4 - -/* Tone Driver **************************************************************/ - -#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */ -#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */ -#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */ -#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */ - -/* NRF24L01 Driver **********************************************************/ - -/* Chip enable: PB.1 */ - -#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) - -/* IRQ line: PA.0 */ - -#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE -#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ - -/* HCSR04 driver */ - -/* Pins config to use with HC-SR04 sensor */ - -#define GPIO_HCSR04_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) -#define GPIO_HCSR04_TRIG (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1) - -#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT -#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG -#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ - -/* Pin for APDS-9960 sensor */ - -#define GPIO_APDS9960_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT - -/* ZERO CROSS pin definition */ - -#define BOARD_ZEROCROSS_GPIO \ - (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* USART2 */ - -#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART2_RX GPIO_USART2_RX_0 -#define GPIO_USART2_CTS GPIO_USART2_CTS_0 -#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) -#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* I2C1 */ - -#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) - -/* I2C2 */ - -#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) -#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) - -/* CAN1 */ - -#define GPIO_CAN1_RX GPIO_CAN1_RX_0 -#define GPIO_CAN1_TX GPIO_ADJUST_MODE(GPIO_CAN1_TX_0, GPIO_MODE_50MHz) - -/* USB */ - -#define GPIO_USB_DM GPIO_USB_DM_0 -#define GPIO_USB_DP GPIO_USB_DP_0 - -/* TIM1 */ - -#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 -#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 -#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 -#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 -#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 -#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 -#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) - -/* TIM2 */ - -#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 -#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 -#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 -#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 -#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) - -/* TIM3 */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 -#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 -#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 -#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 -#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) - -/* TIM4 */ - -#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_0 -#define GPIO_TIM4_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH1OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_0 -#define GPIO_TIM4_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH2OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH3IN GPIO_TIM4_CH3IN_0 -#define GPIO_TIM4_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH3OUT_0, GPIO_MODE_50MHz) -#define GPIO_TIM4_CH4IN GPIO_TIM4_CH4IN_0 -#define GPIO_TIM4_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH4OUT_0, GPIO_MODE_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs deleted file mode 100644 index 6d4f1b4b8c916..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f103-minimum/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script deleted file mode 100644 index 38b17fb89158d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - * - * NOTE: While the STM32F103C8T6 states that the part has 64Kb of FLASH, - * all parts that I have seen do, in fact, have 128Kb of FLASH. That - * additional 64Kb of FLASH can be utilized by simply change the LENGTH - * of the flash region from 64K to 128K. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = LOADADDR(.data); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu deleted file mode 100644 index e9a9a6b75d242..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and - * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the - * STM32duino bootloader is being used. In that case, the correct load .text - * address is 0x0800:2000 (leaving 56Kb). - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08002000, LENGTH = 120K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt deleted file mode 100644 index 06607962aed7e..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt +++ /dev/null @@ -1,120 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SENSORS_HYT271) - list(APPEND SRCS stm32_hyt271.c) -endif() - -if(CONFIG_SENSORS_DS18B20) - list(APPEND SRCS stm32_ds18b20.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_MTD_AT24XX) - if(CONFIG_STM32_I2C1) - list(APPEND SRCS stm32_at24.c) - endif() -endif() - -if(CONFIG_CAN_MCP2515) - list(APPEND SRCS stm32_mcp2515.c) -endif() - -if(CONFIG_LCD_MAX7219) - list(APPEND SRCS stm32_max7219.c) -endif() - -if(CONFIG_INPUT_NUNCHUCK) - list(APPEND SRCS stm32_nunchuck.c) -endif() - -if(CONFIG_LCD_SSD1306_I2C) - list(APPEND SRCS stm32_lcd_ssd1306.c) -endif() - -if(CONFIG_LCD_ST7567) - list(APPEND SRCS stm32_lcd_st7567.c) -endif() - -if(CONFIG_LCD_PCD8544) - list(APPEND SRCS stm32_pcd8544.c) -endif() - -if(CONFIG_USBDEV) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock.c) - endif() -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f103-minimum/src/Make.defs b/boards/arm/stm32/stm32f103-minimum/src/Make.defs deleted file mode 100644 index a0fc84fc4eefb..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/Make.defs +++ /dev/null @@ -1,122 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f103-minimum/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SENSORS_HYT271),y) - CSRCS += stm32_hyt271.c -endif - -ifeq ($(CONFIG_SENSORS_DS18B20),y) - CSRCS += stm32_ds18b20.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_MMCSD),y) - CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_MTD_W25),y) - CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_MTD_AT24XX),y) -ifeq ($(CONFIG_STM32_I2C1),y) -CSRCS += stm32_at24.c -endif -endif - -ifeq ($(CONFIG_CAN_MCP2515),y) - CSRCS += stm32_mcp2515.c -endif - -ifeq ($(CONFIG_LCD_MAX7219),y) - CSRCS += stm32_max7219.c -endif - -ifeq ($(CONFIG_INPUT_NUNCHUCK),y) - CSRCS += stm32_nunchuck.c -endif - -ifeq ($(CONFIG_LCD_SSD1306_I2C),y) -CSRCS += stm32_lcd_ssd1306.c -endif - -ifeq ($(CONFIG_LCD_ST7567),y) - CSRCS += stm32_lcd_st7567.c -endif - -ifeq ($(CONFIG_LCD_PCD8544),y) - CSRCS += stm32_pcd8544.c -endif - -ifeq ($(CONFIG_USBDEV),y) - CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c deleted file mode 100644 index 2da9c070aff19..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "stm32_adc.h" -#include "stm32f103_minimum.h" - -#ifdef CONFIG_ADC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Up to 2 ADC interfaces are supported */ - -#if STM32_NADC < 2 -# undef CONFIG_STM32_ADC2 -#endif - -#if STM32_NADC < 1 -# undef CONFIG_STM32_ADC1 -#endif - -#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) -#ifndef CONFIG_STM32_ADC1 -# warning "Channel information only available for ADC1" -#endif - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 1 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel to be used with Variable Resistor - * (Pontentiometer) - */ - -#ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = -{ - 0 -}; /* ADC12_IN0 */ - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC12_IN0 -}; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ -#ifdef CONFIG_STM32_ADC1 - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ -#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c deleted file mode 100644 index 0204fcfa0de6f..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c +++ /dev/null @@ -1,135 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32f103_minimum.h" - -#ifdef HAVE_AT24 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_at24_automount - * - * Description: - * Initialize and configure the AT24 serial EEPROM - * - ****************************************************************************/ - -int stm32_at24_automount(int minor) -{ - struct i2c_master_s *i2c; - struct mtd_dev_s *mtd; - static bool initialized = false; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* No.. Get the I2C bus driver */ - - finfo("Initialize I2C%d\n", AT24_I2C_BUS); - i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); - if (!i2c) - { - ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); - return -ENODEV; - } - - /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ - - finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); - mtd = at24c_initialize(i2c); - if (!mtd) - { - ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", - AT24_I2C_BUS); - return -ENODEV; - } - -#if defined(CONFIG_STM32F103MINIMUM_AT24_FTL) - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", AT24_MINOR); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } - -#elif defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) - /* Initialize to provide NXFFS on the MTD interface */ - - finfo("Initialize the NXFFS file system\n"); - ret = nxffs_initialize(mtd); - if (ret < 0) - { - ferr("ERROR: NXFFS initialization failed: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/at24 */ - - finfo("Mount the NXFFS file system at /dev/at24\n"); - ret = nx_mount(NULL, "/mnt/at24", "nxffs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); - return ret; - } -#endif - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* HAVE_AT24 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c deleted file mode 100644 index 5a352af6e54cd..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED1, !v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - - /* As the board provides only one soft controllable LED, we simply - * turn it on when the board boots. - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c deleted file mode 100644 index 0f4f0c9e0a520..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif - - /* Initialize USB is - * 1) USBDEV is selected, - * 2) the USB controller is not disabled, and - * 3) the weak function stm32_usbinitialize() has been brought - * into the build. - */ - -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() - * will be called immediately after up_initialize() is called and just - * before the initial application is started. This additional - * initialization phase may be used, for example, to initialize - * board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c deleted file mode 100644 index 518bffcec4a06..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c +++ /dev/null @@ -1,603 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#include "stm32f103_minimum.h" - -/* Conditional logic in stm32f103_minimum.h will determine if certain - * features are supported. Tests for these features need to be made after - * including stm32f103_minimum.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_LEDS_APA102 -#include "stm32_apa102.h" -#endif - -#ifdef CONFIG_WS2812 -#include "stm32_ws2812.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -#ifdef CONFIG_SENSORS_VEML6070 -#include "stm32_veml6070.h" -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK -#include "stm32_nunchuck.h" -#endif - -#ifdef CONFIG_AUDIO_TONE -#include "stm32_tone.h" -#endif - -#ifdef CONFIG_SENSORS_LM75 -#include "stm32_lm75.h" -#endif - -#ifdef CONFIG_WL_NRF24L01 -#include "stm32_nrf24l01.h" -#endif - -#ifdef CONFIG_SENSORS_HCSR04 -#include "stm32_hcsr04.h" -#endif - -#ifdef CONFIG_SENSORS_APDS9960 -#include "stm32_apds9960.h" -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS -#include "stm32_zerocross.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_HYT271 -# define HAVE_SENSORS_DEVICE -#endif - -#ifdef CONFIG_SENSORS_DS18B20 -# define HAVE_SENSORS_DEVICE -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_USBADB -#include -#endif - -#ifdef CONFIG_I2C_DRIVER -#include -#include "stm32_i2c.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Checking needed by W25 Flash */ - -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/* Checking needed by MMC/SDCard */ - -#ifdef CONFIG_NSH_MMCSDMINOR -# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR -#else -# define MMCSD_MINOR 0 -#endif - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ -#ifdef CONFIG_I2C_DRIVER -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef HAVE_SENSORS_DEVICE -static int g_sensor_devno; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef CONFIG_ONESHOT - struct oneshot_lowerhalf_s *os = NULL; -#endif - int ret = OK; - -#ifdef CONFIG_DEV_GPIO - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_I2C_DRIVER - /* Register I2C drivers on behalf of the I2C tool */ - #ifdef CONFIG_STM32_I2C1 - stm32_i2c_register(1); - #endif - #ifdef CONFIG_STM32_I2C2 - stm32_i2c_register(2); - #endif - #ifdef CONFIG_STM32_I2C3 - stm32_i2c_register(3); - #endif -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS - /* Configure the zero-crossing driver */ - - ret = board_zerocross_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize Zero-Cross, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD - ret = stm32_mmcsd_initialize(MMCSD_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef HAVE_AT24 - /* Initialize the AT24 driver */ - - ret = stm32_at24_automount(AT24_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_at24_automount() failed: %d\n", ret); - return ret; - } -#endif /* HAVE_AT24 */ - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_AUDIO_TONE - /* Configure and initialize the tone generator. */ - - ret = board_tone_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_tone_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LEDS_APA102 - /* Configure and initialize the APA102 LED Strip. */ - - ret = board_apa102_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apa102_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_WS2812 - /* Configure and initialize the WS2812 LEDs. */ - - ret = board_ws2812_initialize(0, WS2812_SPI, WS2812_NLEDS); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_HYT271 - /* Configure and initialize the HYT271 sensors */ - - ret = stm32_hyt271initialize(g_sensor_devno); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_hyt271initialize() failed: %d\n", ret); - } - else - { - g_sensor_devno += ret; - } -#endif - -#ifdef CONFIG_SENSORS_DS18B20 - /* Configure and initialize the DS18B20 sensors */ - - ret = stm32_ds18b20initialize(g_sensor_devno); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ds18b20initialize() failed: %d\n", ret); - } - else - { - g_sensor_devno += ret; - } -#endif - -#ifdef CONFIG_LM75_I2C - /* Configure and initialize the LM75 sensor */ - - ret = board_lm75_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_HCSR04 - /* Configure and initialize the HC-SR04 distance sensor */ - - ret = board_hcsr04_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: board_max6675_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN_MCP2515 - /* Configure and initialize the MCP2515 CAN device */ - - ret = stm32_mcp2515initialize("/dev/can0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ONESHOT - os = oneshot_initialize(1, 10); - if (os) - { - ret = oneshot_register("/dev/oneshot", os); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK - /* Register the Nunchuck driver */ - - ret = board_nunchuck_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nunchuck_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, - CONFIG_STM32F103MINIMUM_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_APDS9960 - /* Register the APDS-9960 gesture sensor */ - - ret = board_apds9960_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_SENSORS_VEML6070 - /* Register the UV-A light sensor */ - - ret = board_veml6070_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_veml6070_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_WL_NRF24L01) - /* Initialize the NRF24L01 wireless module */ - - ret = board_nrf24l01_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_SOCKET - /* Initialize CAN socket interface */ - - /* STM32F103C8 may not have enough Flash for SocketCAN; use a part with - * more Flash (e.g. STM32F103CB). - */ - - ret = stm32_cansock_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c deleted file mode 100644 index 44fa04b7acef9..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER1, GPIO_BTN_USER2 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c deleted file mode 100644 index 4d0d37d09c690..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32.h" -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ - struct can_dev_s *can; - int ret; - - can = stm32_caninitialize(1); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c deleted file mode 100644 index 47da3f32fb9df..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c +++ /dev/null @@ -1,59 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32_can.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_cansock_setup - * - * Description: - * Initialize CAN socket interface - * - ****************************************************************************/ - -int stm32_cansock_setup(void) -{ - int ret; - - /* Call stm32_cansockinitialize() to register the CAN network device */ - - ret = stm32_cansockinitialize(1); - if (ret < 0) - { - canerr("ERROR: Failed to get CAN interface %d\n", ret); - return ret; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c deleted file mode 100644 index 5806b9579bd4d..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif /* BOARD_NGPIOIN > 0 */ -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif /* BOARD_NGPIOOUT > 0 */ -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif /* BOARD_NGPIOINT > 0 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif /* BOARD_NGPIOIN > 0 */ - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif /* BOARD_NGPIOOUT > 0 */ - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif /* BOARD_NGPIOINT > 0 */ - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT > 0 -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - #if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif /* BOARD_NGPIOINT > 0 */ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif /* BOARD_NGPIOIN > 0*/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif /* BOARD_NGPIOOUT > 0 */ - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif /* BOARD_NGPIOINT > 0 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c deleted file mode 100644 index adff376b27902..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f103_minimum.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - ret = board_ssd1306_initialize(OLED_I2C_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c deleted file mode 100644 index 79dc5aa1120c2..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" -#include "stm32f103_minimum.h" - -#ifdef CONFIG_NX_LCDDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LCD_SPI_PORTNO 1 /* On SPI1 */ - -#ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct spi_dev_s *g_spidev; -struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); - - if (!g_spidev) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - g_lcddev = max7219_initialize(g_spidev, lcddev); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); - } - else - { - lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); - - return g_lcddev; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} - -#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c deleted file mode 100644 index 71ba958c1551e..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32_spi.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ - defined(CONFIG_CAN_MCP2515) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_mcp2515config_s -{ - /* Configuration structure as seen by the MCP2515 driver */ - - struct mcp2515_config_s config; - - /* Additional private definitions only known to this driver */ - - struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ - mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ - void *arg; /* Argument to pass to the interrupt handler */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the MCP2515 driver from differences in GPIO interrupt handling - * by varying boards and MCUs. - * - * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt - */ - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the MCP2515 - * driver. This structure provides information about the configuration - * of the MCP2515 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -static struct stm32_mcp2515config_s g_mcp2515config = -{ - .config = - { - .spi = NULL, - .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .devid = 0, - .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ - .nfilters = 6, -#ifdef MCP2515_LOOPBACK - .loopback = false; -#endif - .attach = mcp2515_attach, - }, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* This is the MCP2515 Interrupt handler */ - -int mcp2515_interrupt(int irq, void *context, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Verify that we have a handler attached */ - - if (priv->handler) - { - /* Yes.. forward with interrupt along with its argument */ - - priv->handler(&priv->config, priv->arg); - } - - return OK; -} - -static int mcp2515_attach(struct mcp2515_config_s *state, - mcp2515_handler_t handler, void *arg) -{ - struct stm32_mcp2515config_s *priv = - (struct stm32_mcp2515config_s *)state; - irqstate_t flags; - - caninfo("Saving handler %p\n", handler); - - flags = enter_critical_section(); - - priv->handler = handler; - priv->arg = arg; - - /* Configure the interrupt for falling edge */ - - stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, - mcp2515_interrupt, priv); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mcp2515initialize - * - * Description: - * Initialize and register the MCP2515 RFID driver. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/rfid0" - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int stm32_mcp2515initialize(const char *devpath) -{ - struct spi_dev_s *spi; - struct can_dev_s *can; - struct mcp2515_can_s *mcp2515; - int ret; - - /* Check if we are already initialized */ - - if (!g_mcp2515config.handle) - { - sninfo("Initializing\n"); - - /* Configure the MCP2515 interrupt pin as an input */ - - stm32_configgpio(GPIO_MCP2515_IRQ); - - spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); - - if (!spi) - { - return -ENODEV; - } - - /* Save the SPI instance in the mcp2515_config_s structure */ - - g_mcp2515config.config.spi = spi; - - /* Instantiate the MCP2515 CAN Driver */ - - mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); - if (mcp2515 == NULL) - { - canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); - return -ENODEV; - } - - /* Save the opaque structure */ - - g_mcp2515config.handle = mcp2515; - - /* Initialize the CAN Device with the MCP2515 operations */ - - can = mcp2515_initialize(mcp2515); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register(devpath, can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - } - - return OK; -} - -#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c deleted file mode 100644 index 96c77106410db..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32f103_minimum.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_SPI1 -# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" -#endif - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Private Definitions - ****************************************************************************/ - -static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ -static const int SD_SLOT_NO = 0; /* There is only one SD slot */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* NOTE: We are using a SDCard adapter/module without Card Detect pin! - * Then we don't need to Card Detect callback here. - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - spiinfo("INFO: Registering spi1 device\n"); - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int minor) -{ - struct spi_dev_s *spi; - int rv; - - mcinfo("INFO: Initializing mmcsd card\n"); - - spi = stm32_spibus_initialize(SD_SPI_PORT); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - SD_SPI_PORT, SD_SLOT_NO); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c deleted file mode 100644 index fb7dc02e793eb..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f103-minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connect to CN5 just for this purpose: - * - * PB0 ADC12_IN8/TIM3_CH3 - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F103MINIMUM_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c deleted file mode 100644 index 40e3e2659b8c0..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ -#ifdef CONFIG_STM32_DFU - /* TODO handle reboot to bootloader */ - -#endif - - up_systemreset(); - return 0; -} - diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c deleted file mode 100644 index 3ba2dc47d783c..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_RGBLED -#endif - -#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c deleted file mode 100644 index 4cb79126a6d63..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c +++ /dev/null @@ -1,285 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 - * board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_CAN_MCP2515 - stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_LCD_ST7567 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_LCD_PCD8544 - stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ -#endif - -#ifdef CONFIG_WL_NRF24L01 - stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#if defined(CONFIG_CAN_MCP2515) - if (devid == SPIDEV_CANBUS(0)) - { - stm32_gpiowrite(GPIO_MCP2515_CS, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_WL_NRF24L01 - if (devid == SPIDEV_WIRELESS(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ -#ifdef CONFIG_LCD_ST7567 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#ifdef CONFIG_LCD_PCD8544 - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_CD, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c deleted file mode 100644 index 9cf25efa67ce3..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called to setup USB-related GPIO pins for the STM32F103 Minimum board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* USB Soft Connect Pullup */ - - stm32_configgpio(GPIO_USB_PULLUP); -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. Alternatively, if no pull-up GPIO the following EXTERN - * can be redefined to be NULL. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c deleted file mode 100644 index 3ab090b7c655c..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c deleted file mode 100644 index 7ae565c5719b7..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f103_minimum.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c deleted file mode 100644 index 3303c6eabbf4b..0000000000000 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c +++ /dev/null @@ -1,279 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" - -#include "stm32f103_minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the watchdog - * timer - */ - -#define W25_SPI_PORT 1 - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/* Can't support both FAT and SMARTFS */ - -#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_SMARTFS) -# warning "Can't support both FAT and SMARTFS -- using FAT" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ - int ret; -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; - struct mtd_geometry_s geo; -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F103MINIMUM_FLASH_PART_NAMES; -#endif - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(W25_SPI_PORT); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - W25_SPI_PORT); - return -ENODEV; - } - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" - "W25 FLASH driver\n", W25_SPI_PORT); - return -ENODEV; - } - -#ifndef CONFIG_FS_SMARTFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide SMARTFS on the MTD interface */ - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - -#ifdef CONFIG_STM32F103MINIMUM_FLASH_PART - { - int partno; - int partsize; - int partoffset; - int partszbytes; - int erasesize; - const char *partstring = CONFIG_STM32F103MINIMUM_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partref[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - /* Get the Flash erase size */ - - erasesize = geo.erasesize; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - partszbytes = (partsize << 10); /* partsize is defined in KB */ - - /* Check if partition size is bigger then erase block */ - - if (partszbytes < erasesize) - { - syslog(LOG_ERR, - "ERROR: Partition size is lesser than erasesize!\n"); - return -1; - } - - /* Check if partition size is multiple of erase block */ - - if ((partszbytes % erasesize) != 0) - { - syslog(LOG_ERR, - "ERROR: Partition size isn't multiple of erasesize!\n"); - return -1; - } - - mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); - partoffset += partszbytes / erasesize; - -#ifdef CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partref, sizeof(partref), "p%d", partno); - smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, - mtd_part, partref); -#endif - } - - /* Set the partition name */ - -#if defined(CONFIG_MTD_PARTITION_NAMES) - if (!mtd_part) - { - syslog(LOG_ERR, "Error: failed to create partition %s\n", - partname); - return -1; - } - - mtd_setpartitionname(mtd_part, partname); - - /* Now skip to next name. We don't need to split the string here - * because the MTD partition logic will only display names up to - * the comma, thus allowing us to use a single static name - * in the code. - */ - - while (*partname != ',' && *partname != '\0') - { - /* Skip to next ',' */ - - partname++; - } - - if (*partname == ',') - { - partname++; - } -#endif - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_STM32F103MINIMUM_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_STM32F103MINIMUM_FLASH_PART */ -#endif /* CONFIG_FS_SMARTFS */ -#endif /* HAVE_W25 */ - - return OK; -} diff --git a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/CMakeLists.txt deleted file mode 100644 index 1d87be10fd0f0..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig deleted file mode 100644 index 374b8bdc590c1..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ /dev/null @@ -1,128 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_SYSTEM_DD is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_DRIVERS_SMPS=y -CONFIG_EXAMPLES_SMPS=y -CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" -CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 -CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 -CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBDSP=y -CONFIG_LIBM=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_ECHO=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_FREE=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HELP=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y -CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STDIO_BUFFER_SIZE=128 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_INJECTED_CHAN=2 -CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_ADC1_TRG2=y -CONFIG_STM32_HRTIM_ADC=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DEADTIME=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMA=y -CONFIG_STM32_HRTIM_TIMA_DT=y -CONFIG_STM32_HRTIM_TIMA_PWM=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMA_PWM_CH2=y -CONFIG_STM32_HRTIM_TIMB=y -CONFIG_STM32_HRTIM_TIMB_DT=y -CONFIG_STM32_HRTIM_TIMB_PWM=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y -CONFIG_STM32_HRTIM_TIMB_PWM_CH2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig deleted file mode 100644 index 9ed9e4d15f3db..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MQUEUE=y -CONFIG_DISABLE_POSIX_TIMERS=y -CONFIG_DISABLE_PTHREAD=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FDCLONE_STDIO=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NAME_MAX=16 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_BASENAME=y -CONFIG_NSH_DISABLE_CAT=y -CONFIG_NSH_DISABLE_CD=y -CONFIG_NSH_DISABLE_CMP=y -CONFIG_NSH_DISABLE_CP=y -CONFIG_NSH_DISABLE_DF=y -CONFIG_NSH_DISABLE_DIRNAME=y -CONFIG_NSH_DISABLE_EXEC=y -CONFIG_NSH_DISABLE_EXIT=y -CONFIG_NSH_DISABLE_GET=y -CONFIG_NSH_DISABLE_HEXDUMP=y -CONFIG_NSH_DISABLE_KILL=y -CONFIG_NSH_DISABLE_LOSETUP=y -CONFIG_NSH_DISABLE_LS=y -CONFIG_NSH_DISABLE_MKDIR=y -CONFIG_NSH_DISABLE_MKRD=y -CONFIG_NSH_DISABLE_MOUNT=y -CONFIG_NSH_DISABLE_MV=y -CONFIG_NSH_DISABLE_PUT=y -CONFIG_NSH_DISABLE_PWD=y -CONFIG_NSH_DISABLE_RM=y -CONFIG_NSH_DISABLE_RMDIR=y -CONFIG_NSH_DISABLE_SET=y -CONFIG_NSH_DISABLE_SLEEP=y -CONFIG_NSH_DISABLE_SOURCE=y -CONFIG_NSH_DISABLE_TEST=y -CONFIG_NSH_DISABLE_TIME=y -CONFIG_NSH_DISABLE_UMOUNT=y -CONFIG_NSH_DISABLE_UNAME=y -CONFIG_NSH_DISABLE_UNSET=y -CONFIG_NSH_DISABLE_USLEEP=y -CONFIG_NSH_DISABLE_WGET=y -CONFIG_NSH_DISABLE_XD=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_READLINE=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig deleted file mode 100644 index 08b072eda47fa..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ /dev/null @@ -1,98 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_DMESG is not set -# CONFIG_NSH_DISABLE_ECHO is not set -# CONFIG_NSH_DISABLE_ENV is not set -# CONFIG_NSH_DISABLE_EXPORT is not set -# CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LS is not set -# CONFIG_NSH_DISABLE_PRINTF is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_TRUNCATE is not set -# CONFIG_NSH_DISABLE_UPTIME is not set -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f334-disco" -CONFIG_ARCH_BOARD_STM32F334_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F334C8=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_TOOLCHAIN_BUILDROOT=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_COMP=y -CONFIG_DAC=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DRIVERS_POWERLED=y -CONFIG_EXAMPLES_POWERLED=y -CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT=100 -CONFIG_EXAMPLES_POWERLED_DEVPATH="/dev/powerled0" -CONFIG_FDCLONE_STDIO=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1024 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBM=y -CONFIG_NAME_MAX=16 -CONFIG_NSH_ARGCAT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=256 -CONFIG_NSH_MAXARGUMENTS=16 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_PREALLOC_TIMERS=2 -CONFIG_PTHREAD_STACK_DEFAULT=1024 -CONFIG_PTHREAD_STACK_MIN=1024 -CONFIG_RAM_SIZE=12288 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_COMP4=y -CONFIG_STM32_DAC1=y -CONFIG_STM32_DAC1CH1=y -CONFIG_STM32_DAC1CH1_DMA=y -CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE=5 -CONFIG_STM32_DAC1CH1_DMA_EXTERNAL=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_HRTIM1=y -CONFIG_STM32_HRTIM_BURST=y -CONFIG_STM32_HRTIM_CLK_FROM_PLL=y -CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y -CONFIG_STM32_HRTIM_DMA=y -CONFIG_STM32_HRTIM_EEV2=y -CONFIG_STM32_HRTIM_EVENTS=y -CONFIG_STM32_HRTIM_PWM=y -CONFIG_STM32_HRTIM_TIMC=y -CONFIG_STM32_HRTIM_TIMC_BURST=y -CONFIG_STM32_HRTIM_TIMC_BURST_CH1=y -CONFIG_STM32_HRTIM_TIMC_DMA=y -CONFIG_STM32_HRTIM_TIMC_PWM=y -CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f334-disco/include/board.h b/boards/arm/stm32/stm32f334-disco/include/board.h deleted file mode 100644 index b1b39e94d8f7c..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/include/board.h +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f334-disco. The following definitions describe how NuttX - * controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F334-DISCO supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user button connected to the I/O PA0 of the STM32F334R8. - * B2 RESET: push button connected to NRST is used to RESET the - * STM32F334R8. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) - -/* I2C */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) - -/* SPI */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* TIM */ - -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) - -#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) - -/* USART */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_50MHz) /* PB4 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_50MHz) /* PB3 */ - -/* Board configuration for powerled example: - * - Set HRTIM TIMC output 1 (PB12) on PERIOD. - * - Reset HRTIM TIMC output 1 on HRTIM EEV2. - * - HRTIM EEV2 is connected to COMP4 output which works as current limit. - * - COMP4 inverting input is connected to DAC1CH1 output. - * - COMP4 non-inverting input (PB1) is connected to current sense - * resistor (1 Ohm). - * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used - * to provide slope compensation. - */ - -#if defined(CONFIG_EXAMPLES_POWERLED) - -/* Comparators configuration ************************************************/ - -#define COMP4_INM COMP_INMSEL_DAC1CH1 - -/* HRTIM configuration ******************************************************/ - -#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMC_MODE HRTIM_MODE_CONT -#define HRTIM_TIMC_DMA (HRTIM_DMA_REP|HRTIM_DMA_CMP1|HRTIM_DMA_CMP2| \ - HRTIM_DMA_CMP3|HRTIM_DMA_CMP4) -#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER -#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_EXTEVNT2 -#define HRTIM_TIMC_CH1_IDLE_STATE HRTIM_IDLE_INACTIVE - -#define HRTIM_EEV_SAMPLING HRTIM_EEV_SAMPLING_d1 -#define HRTIM_EEV2_SRC HRTIM_EEV_SRC_ANALOG -#define HRTIM_EEV2_FILTER HRTIM_EEV_DISABLE -#define HRTIM_EEV2_POL HRTIM_EEV_POL_HIGH -#define HRTIM_EEV2_SEN HRTIM_EEV_SEN_LEVEL -#define HRTIM_EEV2_MODE HRTIM_EEV_MODE_FAST - -#define HRTIM_BURST_CLOCK HRTIM_BURST_CLOCK_HRTIM -#define HRTIM_BURST_PRESCALER HRTIM_BURST_PRESCALER_1 -#define HRTIM_BURST_TRIGGERS 0 - -/* DMA channels *************************************************************/ - -/* DAC */ - -#define DAC1CH1_DMA_CHAN DMACHAN_HRTIM1_C - -#endif /* CONFIG_EXAMPLES_POWERLED */ - -/* Board configuration for SMPS example: - * PA8 - HRTIM_CHA1 - * PA9 - HRTIM_CHA2 - * PA10 - HRTIM_CHB1 - * PA11 - HRTIM_CHB2 - * VIN - ADC Channel 2 (PA1) - * VOUT - ADC Channel 4 (PA3) - */ - -#if defined(CONFIG_EXAMPLES_SMPS) - -/* HRTIM configuration ******************************************************/ - -/* Timer A configuration - Buck operations */ - -#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMA_MODE HRTIM_MODE_CONT -#define HRTIM_TIMA_UPDATE 0 -#define HRTIM_TIMA_RESET 0 - -#define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMA_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMA_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMA_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMA_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMA_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMA_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMA_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMA_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMA_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -/* Timer B configuration - Boost operations */ - -#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_1 -#define HRTIM_TIMB_MODE HRTIM_MODE_CONT -#define HRTIM_TIMB_UPDATE 0 -#define HRTIM_TIMB_RESET 0 - -#define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_NONE -#define HRTIM_TIMB_CH2_SET HRTIM_OUT_SET_NONE -#define HRTIM_TIMB_CH2_RST HRTIM_OUT_RST_NONE - -#define HRTIM_TIMB_DT_FSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMB_DT_RSLOCK HRTIM_DT_LOCK -#define HRTIM_TIMB_DT_FVLOCK HRTIM_DT_RW -#define HRTIM_TIMB_DT_RVLOCK HRTIM_DT_RW -#define HRTIM_TIMB_DT_FSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMB_DT_RSIGN HRTIM_DT_SIGN_POSITIVE -#define HRTIM_TIMB_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 - -#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4 - -/* DMA channels *************************************************************/ - -#endif /* CONFIG_EXAMPLES_SMPS */ - -/* HRTIM1 */ - -#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 -#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 -#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 -#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 -#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 -#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 -#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 -#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 -#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 -#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 -#define GPIO_HRTIM1_EEV1 GPIO_HRTIM1_EEV1_0 -#define GPIO_HRTIM1_EEV2 GPIO_HRTIM1_EEV2_0 -#define GPIO_HRTIM1_EEV3 GPIO_HRTIM1_EEV3_0 -#define GPIO_HRTIM1_FLT1 GPIO_HRTIM1_FLT1_0 -#define GPIO_HRTIM1_FLT2 GPIO_HRTIM1_FLT2_0 -#define GPIO_HRTIM1_FLT3 GPIO_HRTIM1_FLT3_0 -#define GPIO_HRTIM1_FLT4 GPIO_HRTIM1_FLT4_0 -#define GPIO_HRTIM1_FLT5 GPIO_HRTIM1_FLT5_0 - -/* COMP */ - -#define GPIO_COMP2_INP GPIO_COMP2_INP_0 -#define GPIO_COMP4_INP GPIO_COMP4_INP_0 -#define GPIO_COMP6_INP GPIO_COMP6_INP_0 - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -#endif /* __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs deleted file mode 100644 index 3312eb4725896..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f334-disco/scripts/ld.script b/boards/arm/stm32/stm32f334-disco/scripts/ld.script deleted file mode 100644 index 4a28638fbc2ae..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/ld.script +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F334C8 has 64Kb of FLASH beginning at address 0x0800:0000, - * 12Kb of SRAM and 4Kb of CCM SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt deleted file mode 100644 index b3e02b012c827..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_DRIVERS_POWERLED) - list(APPEND SRCS stm32_powerled.c) -endif() - -if(CONFIG_DRIVERS_SMPS) - list(APPEND SRCS stm32_smps.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f334-disco/src/Make.defs b/boards/arm/stm32/stm32f334-disco/src/Make.defs deleted file mode 100644 index df8d1b44b3755..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/Make.defs +++ /dev/null @@ -1,57 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_SPI),y) -CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_DRIVERS_POWERLED),y) -CSRCS += stm32_powerled.c -endif - -ifeq ($(CONFIG_DRIVERS_SMPS),y) -CSRCS += stm32_smps.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c b/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c deleted file mode 100644 index 9d40e86bd6cca..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2) */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC2) -# if defined(DEV1_PORT) -# define DEV2_PORT 2 -# else -# define DEV1_PORT 2 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 3 -#define ADC2_NCHANNELS 3 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 2, - 11 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC1_IN1_0, /* PA0/A0 */ - GPIO_ADC1_IN2_0, /* PA1/A1 */ - GPIO_ADC1_IN11_0, /* PB0/A3 */ -}; - -#elif DEV1_PORT == 2 - -#define DEV1_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[3] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 2 - -#define DEV2_NCHANNELS ADC2_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[1] = -{ - 1, - 6, - 7 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC2_IN1_0, /* PA4/A2 */ - GPIO_ADC2_IN7_0, /* PC1/A4 */ - GPIO_ADC2_IN6_0, /* PC0/A5 */ -}; - -#endif /* DEV2_PORT == 2 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c deleted file mode 100644 index 3cc43c8ee0a23..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f334-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == BOARD_LED1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c deleted file mode 100644 index 5aacb0f9f1109..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c +++ /dev/null @@ -1,194 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f334-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#undef HAVE_LEDS -#undef HAVE_DAC - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) -# define HAVE_LEDS 1 -#endif - -#if defined(CONFIG_DAC) -# define HAVE_DAC1 1 -# define HAVE_DAC2 1 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - int ret; - -#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS) -#ifdef HAVE_LEDS - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - return; - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DAC - /* Initialize DAC and register the DAC driver. */ - - ret = stm32_dac_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_COMP - /* Initialize COMP and register the COMP driver. */ - - ret = stm32_comp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_OPAMP - /* Initialize OPAMP and register the OPAMP driver. */ - - ret = stm32_opamp_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_HRTIM - /* Initialize HRTIM and register the HRTIM driver. */ - - ret = stm32_hrtim_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_hrtim_setup failed: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_DRIVERS_POWERLED - /* Initialize powerled and register the powerled driver */ - - ret = stm32_powerled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_powerled_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DRIVERS_SMPS - /* Initialize smps and register the smps driver */ - - ret = stm32_smps_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); -} -#endif diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c b/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c deleted file mode 100644 index d1f45f0ab7ab2..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ - defined(CONFIG_STM32_COMP4) || \ - defined(CONFIG_STM32_COMP6)) - -#ifdef CONFIG_STM32_COMP2 -# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP4 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) -# error "Currently only one COMP device supported" -# endif -#elif CONFIG_STM32_COMP6 -# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) -# error "Currently only one COMP device supported" -# endif -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_comp_setup - * - * Description: - * Initialize COMP - * - ****************************************************************************/ - -int stm32_comp_setup(void) -{ - static bool initialized = false; - struct comp_dev_s *comp = NULL; - int ret; - - if (!initialized) - { - /* Get the comparator interface */ - -#ifdef CONFIG_STM32_COMP2 - comp = stm32_compinitialize(2); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 2); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP4 - comp = stm32_compinitialize(4); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 4); - return -ENODEV; - } -#endif - -#ifdef CONFIG_STM32_COMP6 - comp = stm32_compinitialize(6); - if (comp == NULL) - { - aerr("ERROR: Failed to get COMP%d interface\n", 6); - return -ENODEV; - } -#endif - - /* Register the comparator character driver at /dev/comp0 */ - - ret = comp_register("/dev/comp0", comp); - if (ret < 0) - { - aerr("ERROR: comp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || - * CONFIG_STM32_COMP2 - * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c b/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c deleted file mode 100644 index 381aa7549c39f..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_hrtim.h" - -#if defined(CONFIG_STM32_HRTIM) && defined(CONFIG_STM32_HRTIM1) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_hrtim_setup - * - * Description: - * Initialize HRTIM driver - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_hrtim_setup(void) -{ - static bool initialized = false; - struct hrtim_dev_s *hrtim = NULL; - int ret; - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - tmrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Register the HRTIM character driver at /dev/hrtim0 */ - - ret = hrtim_register("/dev/hrtim0", hrtim); - if (ret < 0) - { - tmrerr("ERROR: hrtim_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c b/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c deleted file mode 100644 index 67ba3ad9f6783..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_opamp_setup - * - * Description: - * Initialize OPAMP - * - ****************************************************************************/ - -int stm32_opamp_setup(void) -{ - static bool initialized = false; - struct opamp_dev_s *opamp = NULL; - int ret; - - if (!initialized) - { - /* Get the OPAMP interface */ - -#ifdef CONFIG_STM32_OPAMP2 - opamp = stm32_opampinitialize(2); - if (opamp == NULL) - { - aerr("ERROR: Failed to get OPAMP%d interface\n", 2); - return -ENODEV; - } -#endif - - /* Register the OPAMP character driver at /dev/opamp0 */ - - ret = opamp_register("/dev/opamp0", opamp); - if (ret < 0) - { - aerr("ERROR: opamp_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c deleted file mode 100644 index 8c42a9c23cba9..0000000000000 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c +++ /dev/null @@ -1,1143 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_smps.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_hrtim.h" -#include "stm32_adc.h" - -#include - -#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) - -#ifndef CONFIG_LIBDSP -# error CONFIG_LIBDSP is required -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) -# error "SMPS example requires HRTIM1 support" -#endif - -#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) -# error "SMPS example requires ADC1 support" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* ADC1 channels used in this example */ - -#define ADC1_NCHANNELS 2 - -/* ADC1 injected channels numeration */ - -#define V_IN_ADC_INJ_CHANNEL 0 -#define V_OUT_ADC_INJ_CHANNEL 1 - -/* Voltage reference for ADC */ - -#define ADC_REF_VOLTAGE ((float)3.3) - -/* ADC resolution */ - -#define ADC_VAL_MAX 4095 - -/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ - -#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) - -/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ - -#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) - -/* Some absolute limits */ - -#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 -#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 -#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 - -#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA -# error "Output current limit great than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV -# error "Output voltage limit greater than absolute limit!" -#endif -#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV -# error "Input voltage limit greater than absolute limit!" -#endif - -/* Maximum output voltage for boost converter in float */ - -#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) - -/* Current limit table dimension */ - -#define SMPS_CURRENT_LIMIT_TAB_DIM 15 - -/* At this time only PID controller implemented */ - -#define SMPS_CONTROLLER_PID 1 - -/* Converter's finite accuracy */ - -#define SMPS_VOLTAGE_ACCURACY ((float)0.01) - -/* Buck-boost mode threshold */ - -#define SMPS_BUCKBOOST_RANGE ((float)0.5) - -/* PID controller configuration */ - -#define PID_KP ((float)1.0) -#define PID_KI ((float)0.1) -#define PID_KD ((float)0.0) - -/* Converter frequencies: - * - TIMA_PWM_FREQ - buck converter 250kHz - * - TIMB_PWM_FREQ - boost converter 250kHz - */ - -#define TIMA_PWM_FREQ 250000 -#define TIMB_PWM_FREQ 250000 - -/* Deadtime configuration */ - -#define DT_RISING 0x0A0 -#define DT_FALLING 0x0A0 - -/* Helper macros */ - -#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ - HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1|HRTIM_OUT_TIMA_CH2| \ - HRTIM_OUT_TIMB_CH1|HRTIM_OUT_TIMB_CH2, state); - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Current converter mode */ - -enum converter_mode_e -{ - CONVERTER_MODE_INIT, /* Initial mode */ - CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ - CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ - CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ -}; - -/* SMPS lower drivers structure */ - -struct smps_lower_dev_s -{ - struct hrtim_dev_s *hrtim; /* PWM generation */ - struct stm32_adc_dev_s *adc; /* input and output voltage sense */ - struct comp_dev_s *comp; /* not used in this demo - only as reference */ - struct dac_dev_s *dac; /* not used in this demo - only as reference */ - struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ -}; - -/* Private data for smps */ - -struct smps_priv_s -{ - uint8_t conv_mode; /* Converter mode */ - uint16_t v_in_raw; /* Voltage input RAW value */ - uint16_t v_out_raw; /* Voltage output RAW value */ - float v_in; /* Voltage input real value in V */ - float v_out; /* Voltage output real value in V */ - bool running; /* Running flag */ - pid_controller_f32_t pid; /* PID controller */ - float *c_limit_tab; /* Current limit tab */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev); -static int smps_shutdown(struct smps_dev_s *dev); -static int smps_start(struct smps_dev_s *dev); -static int smps_stop(struct smps_dev_s *dev); -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param); -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits); -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state); -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); -static int smps_fault_get(struct smps_dev_s *dev, - uint8_t *fault); -static int smps_fault_clean(struct smps_dev_s *dev, - uint8_t fault); -static int smps_ioctl(struct smps_dev_s *dev, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct smps_lower_dev_s g_smps_lower; -struct smps_priv_s g_smps_priv; -struct smps_s g_smps; - -struct smps_ops_s g_smps_ops = -{ - .setup = smps_setup, - .shutdown = smps_shutdown, - .start = smps_start, - .stop = smps_stop, - .params_set = smps_params_set, - .mode_set = smps_mode_set, - .limits_set = smps_limits_set, - .fault_set = smps_fault_set, - .state_get = smps_state_get, - .fault_get = smps_fault_get, - .fault_clean = smps_fault_clean, - .ioctl = smps_ioctl -}; - -struct smps_dev_s g_smps_dev = -{ - .ops = &g_smps_ops, - .priv = &g_smps, - .lower = NULL -}; - -/* ADC configuration: - * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) - * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) - * - * ADC channels configured in injected mode. - * - * Transistors configuration in buck mode: - * - T5 - ON - * - T12 - OFF - * - T4 and T11 - buck operation - * Transistors configuration in boost mode: - * - T4 - ON - * - T11 - OFF - * - T5 and T12 - boost operation - * Transistors configuration in buck-boost mode: - * - T4, T11 - buck operation - * - T5 and T12 - boost operation - * - * HRTIM outputs configuration: - * - T4 -> PA8 -> HRTIM_CHA1 - * - T5 -> PA11 -> HRTIM_CHB2 - * - T11 -> PA9 -> HRTIM_CHA2 - * - T12 -> PA10 -> HRTIM_CHB1 - * - */ - -/* ADC channel list */ - -static const uint8_t g_adc1chan[ADC1_NCHANNELS] = -{ - 2, - 4 -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_adc1pins[ADC1_NCHANNELS] = -{ - GPIO_ADC1_IN2_0, /* PA1 - V_IN */ - GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int smps_shutdown(struct smps_dev_s *dev) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - - /* Stop smps if running */ - - if (priv->running == true) - { - smps_stop(dev); - } - - /* Reset smps structure */ - - memset(smps, 0, sizeof(struct smps_s)); - - return OK; -} - -/**************************************************************************** - * Name: smps_setup - * - * Description: - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -static int smps_setup(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct hrtim_dev_s *hrtim = NULL; - struct stm32_adc_dev_s *adc = NULL; - struct smps_priv_s *priv; - struct adc_channel_s channels[ADC1_NCHANNELS]; - struct adc_sample_time_s stime; - int ret = OK; - int i = 0; - - /* Initialize smps structure */ - - smps->opmode = SMPS_OPMODE_INIT; - smps->state.state = SMPS_STATE_INIT; - smps->priv = &g_smps_priv; - - /* Check lower half drivers */ - - hrtim = lower->hrtim; - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get hrtim "); - ret = ERROR; - goto errout; - } - - adc = lower->adc; - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC lower level interface"); - ret = ERROR; - goto errout; - } - - /* Update ADC sample time */ - - for (i = 0; i < ADC1_NCHANNELS; i += 1) - { - channels[i].sample_time = ADC_SMPR_61p5; - channels[i].channel = g_adc1chan[i]; - } - - memset(&stime, 0, sizeof(struct adc_sample_time_s)); - - stime.channels_nbr = ADC1_NCHANNELS; - stime.channel = channels; - - STM32_ADC_SAMPLETIME_SET(adc, &stime); - STM32_ADC_SAMPLETIME_WRITE(adc); - - /* TODO: create current limit table */ - - UNUSED(priv); - -errout: - return ret; -} - -static int smps_start(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - volatile uint64_t per = 0; - uint64_t fclk = 0; - int ret = OK; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Reset SMPS private structure */ - - memset(priv, 0, sizeof(struct smps_priv_s)); - -#ifdef SMPS_CONTROLLER_PID - /* Initialize PID controller */ - - pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); - - /* Set PID controller saturation */ - - pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); - - /* Reset PI integral if saturated */ - - pi_ireset_enable(&priv->pid, true); -#endif - - /* Get TIMA period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA); - per = fclk / TIMA_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve tima pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMA_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMA period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, (uint16_t)per); - - /* Get TIMB period value for given frequency */ - - fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMB); - per = fclk / TIMB_PWM_FREQ; - if (per > HRTIM_PER_MAX) - { - pwrerr("ERROR: Can not achieve timb pwm " - "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", - (uint32_t)TIMB_PWM_FREQ, fclk); - ret = -EINVAL; - goto errout; - } - - /* Set TIMB period value */ - - HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMB, (uint16_t)per); - - /* ADC trigger on TIMA CMP4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP4, 10000); - - /* Configure TIMER A and TIMER B deadtime mode - * - * NOTE: In deadtime mode we have to configure output 1 only - * (SETx1, RSTx1), output 2 configuration is not significant. - */ - - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING, - DT_RISING); - HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING, - DT_FALLING); - - /* Set T4 and T12 to a low state. - * Deadtime mode force T11 and T5 to a high state. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_PER); - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_PER); - - /* Set running flag */ - - priv->running = true; - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); - - /* Enable ADC JEOS interrupts */ - - STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); - - /* Enable ADC12 interrupts */ - - up_enable_irq(STM32_IRQ_ADC12); - - /* Start injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, true); - -errout: - return ret; -} - -static int smps_stop(struct smps_dev_s *dev) -{ - struct smps_lower_dev_s *lower = dev->lower; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct hrtim_dev_s *hrtim = lower->hrtim; - struct stm32_adc_dev_s *adc = lower->adc; - - /* Disable HRTIM outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - /* Stop injected conversion */ - - STM32_ADC_INJ_STARTCONV(adc, false); - - /* Disable ADC JEOS interrupts */ - - STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); - - /* Disable ADC12 interrupts */ - - up_disable_irq(STM32_IRQ_ADC12); - - /* Reset running flag */ - - priv->running = false; - - return OK; -} - -static int smps_params_set(struct smps_dev_s *dev, - struct smps_params_s *param) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only output voltage */ - - smps->param.v_out = param->v_out; - - /* REVISIT: use current and power parameters ? */ - - if (param->i_out > 0) - { - pwrwarn("WARNING: Output current parameters not used in this demo\n"); - } - - if (param->p_out > 0) - { - pwrwarn("WARNING: Output power parameters not used in this demo\n"); - } - - return ret; -} - -static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Only constant voltage mode supported */ - - if (mode == SMPS_OPMODE_CV) - { - smps->opmode = mode; - } - else - { - pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); - ret = ERROR; - goto errout; - } - -errout: - return ret; -} - -static int smps_limits_set(struct smps_dev_s *dev, - struct smps_limits_s *limits) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - int ret = OK; - - /* Some assertions */ - - if (limits->v_out <= 0) - { - pwrerr("ERROR: Output voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_in <= 0) - { - pwrerr("ERROR: Input voltage limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->i_out <= 0) - { - pwrerr("ERROR: Output current limit must be set!\n"); - ret = ERROR; - goto errout; - } - - if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) - { - limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output voltage limiit > SMPS absolute output voltage " - "limit. Set output voltage limit to %.2f.\n", - limits->v_out); - } - - if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) - { - limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS input voltage limiit > SMPS absolute input voltage " - "limit. Set input voltage limit to %.2f.\n", - limits->v_in); - } - - if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) - { - limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; - pwrwarn("WARNING: " - "SMPS output current limiit > SMPS absolute output current " - "limit. Set output current limit to %.2f.\n", - limits->i_out); - } - - /* Set output voltage limit */ - - smps->limits.v_out = limits->v_out; - - /* Set input voltage limit */ - - smps->limits.v_in = limits->v_in; - - /* Set current limit */ - - smps->limits.i_out = limits->i_out; - - /* Lock limits */ - - smps->limits.lock = true; - -errout: - return ret; -} - -static int smps_state_get(struct smps_dev_s *dev, - struct smps_state_s *state) -{ - struct smps_s *smps = (struct smps_s *)dev->priv; - - /* Copy locally stored feedbacks data to status structure */ - - smps->state.fb.v_in = g_smps_priv.v_in; - smps->state.fb.v_out = g_smps_priv.v_out; - - /* Return state structure to caller */ - - memcpy(state, &smps->state, sizeof(struct smps_state_s)); - - return OK; -} - -static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) -{ - return OK; -} - -static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) -{ - return OK; -} - -static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) -{ - return OK; -} - -/**************************************************************************** - * Name: smps_controller - ****************************************************************************/ - -static float smps_controller(struct smps_priv_s *priv, float err) -{ - float out = 0.0; - -#ifdef SMPS_CONTROLLER_PID - out = pid_controller(&priv->pid, err); -#else -# error "At this time only PID controller implemented" -#endif - - return out; -} - -/**************************************************************************** - * Name: smps_duty_set - ****************************************************************************/ - -static void smps_duty_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - float out) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - uint8_t mode = priv->conv_mode; - uint16_t cmp = 0; - float duty = 0.0; - uint16_t per = 0; - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - /* Do nothing */ - - break; - } - - case CONVERTER_MODE_BUCK: - { - if (out >= priv->v_in) out = priv->v_in; - if (out < 0.0) out = 0.0; - - duty = out / priv->v_in; - -#warning TODO: current limit in buck mode - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - cmp = (uint16_t)(per * duty); - - if (cmp > per - 30) cmp = per - 30; - - /* Set T4 duty cycle. T11 is complementary to T4 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BOOST: - { - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T12 duty cycle. T5 is complementary to T12 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Buck converter is set to fixed duty cycle (80%). - * Now we need set boost converter - */ - - per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); - - if (out < priv->v_in) out = priv->v_in; - if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; - - duty = 1.0 - priv->v_in / out; - -#warning TODO: current limit in buck boost mode - - cmp = (uint16_t)(per * duty); - - /* Set T12 duty cycle. T5 is complementary to T12 */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } -} - -/**************************************************************************** - * Name: smps_conv_mode_set - * - * Description: - * Change converter mode (buck/boost/buck-boost). - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void smps_conv_mode_set(struct smps_priv_s *priv, - struct smps_lower_dev_s *lower, - uint8_t mode) -{ - struct hrtim_dev_s *hrtim = lower->hrtim; - - /* Disable all outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); - - switch (mode) - { - case CONVERTER_MODE_INIT: - { - break; - } - - case CONVERTER_MODE_BUCK: - { - /* Set T12 low (T5 high) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_NONE); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_PER); - - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BOOST: - { - /* Set T4 high (T11 low) on the next PER */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_NONE); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_CMP1); - - break; - } - - case CONVERTER_MODE_BUCKBOOST: - { - /* Set T4 to a high state on PER and reset on CMP1. - * T11 is complementary to T4. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set T12 to a high state on PER and reset on CMP1. - * T5 is complementary to T12. - */ - - HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_SET_PER); - HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, - HRTIM_OUT_RST_CMP1); - - /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ - - HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, - 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, - HRTIM_TIMER_TIMA))); - - break; - } - - default: - { - pwrerr("ERROR: Unknown converter mode %d!\n", mode); - break; - } - } - - /* Set mode in private data */ - - priv->conv_mode = mode; - - /* Enable outputs */ - - HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); -} - -/**************************************************************************** - * Name: adc12_handler - ****************************************************************************/ - -static void adc12_handler(void) -{ - struct smps_dev_s *dev = &g_smps_dev; - struct smps_s *smps = (struct smps_s *)dev->priv; - struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; - struct smps_lower_dev_s *lower = dev->lower; - struct stm32_adc_dev_s *adc = lower->adc; - uint32_t pending; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - float err; - float out; - uint8_t mode; - - pending = STM32_ADC_INT_GET(adc); - - if (pending & ADC_INT_JEOC && priv->running == true) - { - /* Get raw ADC values */ - - priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); - priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); - - /* Convert raw values to real values */ - - priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; - priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; - - /* According to measured voltages we set converter - * in appropriate mode - */ - - if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage greater than input voltage - set - * boost converter - */ - - mode = CONVERTER_MODE_BOOST; - } - - else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) - { - /* Desired output voltage lower than input voltage - set - * buck converter - */ - - mode = CONVERTER_MODE_BUCK; - } - - else - { - /* Desired output voltage close to input voltage - set - * buck-boost converter - */ - - mode = CONVERTER_MODE_BUCKBOOST; - } - - /* Configure converter to the new mode if needed */ - - if (priv->conv_mode != mode) - { - smps_conv_mode_set(priv, lower, mode); - } - - /* Get regulator error */ - - err = smps->param.v_out - priv->v_out; - - if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) - { - /* PID controller */ - - out = smps_controller(priv, err); - - /* Update duty cycle */ - - smps_duty_set(priv, lower, out); - } - } - - /* Clear pending */ - - STM32_ADC_INT_ACK(adc, pending); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_smps_setup - * - * Description: - * Initialize SMPS driver. - * - * Returned Value: - * 0 on success, a negated errno value on failure - * - ****************************************************************************/ - -int stm32_smps_setup(void) -{ - struct smps_lower_dev_s *lower = &g_smps_lower; - struct smps_dev_s *smps = &g_smps_dev; - struct hrtim_dev_s *hrtim = NULL; - struct adc_dev_s *adc = NULL; - static bool initialized = false; - int ret = OK; - int i; - - /* Initialize only once */ - - if (!initialized) - { - /* Get the HRTIM interface */ - - hrtim = stm32_hrtiminitialize(); - if (hrtim == NULL) - { - pwrerr("ERROR: Failed to get HRTIM1 interface\n"); - return -ENODEV; - } - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1pins[i]); - } - - /* Get the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); - if (adc == NULL) - { - pwrerr("ERROR: Failed to get ADC %d interface\n", 1); - return -ENODEV; - } - - /* Initialize SMPS lower driver interfaces */ - - lower->hrtim = hrtim; - lower->adc = adc->ad_priv; - lower->comp = NULL; - lower->dac = NULL; - lower->opamp = NULL; - - /* Attach ADC12 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); - if (ret < 0) - { - pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC12 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Setup ADC hardware */ - - adc->ad_ops->ao_setup(adc); - - /* We do not need register character drivers for SMPS lower - * peripherals. All control should be done via SMPS character - * driver. - */ - - ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); - if (ret < 0) - { - pwrerr("ERROR: smps_register failed: %d\n", ret); - return ret; - } - - initialized = true; - } - -errout: - return ret; -} - -#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/CMakeLists.txt deleted file mode 100644 index b5910c678d95d..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig deleted file mode 100644 index 8fd33f99d8cd1..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f3discovery" -CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=40960 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig deleted file mode 100644 index 72cd5cdaeb7e0..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f3discovery" -CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F3=y -CONFIG_ARCH_CHIP_STM32F303VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=6522 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=40960 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USB=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32f3discovery/include/board.h b/boards/arm/stm32/stm32f3discovery/include/board.h deleted file mode 100644 index 2761c0cfb059d..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/include/board.h +++ /dev/null @@ -1,275 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* HSI - Internal 8 MHz RC Oscillator - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ - -#define STM32_HSI_FREQUENCY 8000000ul -#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL source is HSE/1, - * PLL multiplier is 9: - * PLL frequency is 8MHz (XTAL) x 9 = 72MHz - */ - -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 -#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (72MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (72MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ - -/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ - -/* Timers driven from APB2 will be PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* APB1 timers 2-7 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* USB divider -- Divide PLL clock by 1.5 */ - -#define STM32_CFGR_USBPRE 0 - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 PWR: red LED indicates that the board is powered. - * LD2 COM: LD2 default status is red. LD2 turns to green to indicate that - * communications are in progress between the PC and the - * ST-LINK/V2. - * - * And eight can be controlled by software: - * - * User LEDs connected to the I/O of the STM32F303VCT6. - * User LD3: red LED is a user LED connected to the PE9 I/O. - * User LD4: blue LED is a user LED connected to the PE8 I/O. - * User LD5: orange LED is a user LED connected to the PE10 I/O. - * User LD6: green LED is a user LED connected to the PE15 I/O. - * User LD7: green LED is a user LED connected to the PE11 I/O. - * User LD8: orange LED is a user LED connected to the PE14 I/O. - * User LD9: blue LED is a user LED connected to the PE12 I/O. - * User LD10: red LED is a user LED connected to the PE13 I/O. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_LED3 2 /* User LD5 */ -#define BOARD_LED4 3 /* User LD6 */ -#define BOARD_LED5 4 /* User LD7 */ -#define BOARD_LED6 5 /* User LD8 */ -#define BOARD_LED7 6 /* User LD9 */ -#define BOARD_LED8 7 /* User LD10 */ -#define BOARD_NLEDS 8 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) -#define BOARD_LED5_BIT (1 << BOARD_LED5) -#define BOARD_LED6_BIT (1 << BOARD_LED6) -#define BOARD_LED7_BIT (1 << BOARD_LED7) -#define BOARD_LED8_BIT (1 << BOARD_LED8) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on - * board the stm32f3discovery. - * The following definitions describe how NuttX controls the LEDs: - * - * SYMBOL Meaning LED state - * Initially all LEDs are OFF - * ------------------- ----------------------- ------------- ------------ - * LED_STARTED NuttX has been started LD3 ON - * LED_HEAPALLOCATE Heap has been allocated LD4 ON - * LED_IRQSENABLED Interrupts enabled LD4 ON - * LED_STACKCREATED Idle stack created LD6 ON - * LED_INIRQ In an interrupt LD7 should glow - * LED_SIGNAL In a signal handler LD8 might glow - * LED_ASSERTION An assertion failed LD9 ON while handling - * the assertion - * LED_PANIC The system has crashed LD10 Blinking at 2Hz - * LED_IDLE STM32 is in sleep mode (Optional, not used) - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 1 -#define LED_IRQSENABLED 2 -#define LED_STACKCREATED 3 -#define LED_INIRQ 4 -#define LED_SIGNAL 5 -#define LED_ASSERTION 6 -#define LED_PANIC 7 - -/* Button definitions *******************************************************/ - -/* The STM32F3Discovery supports two buttons; only one button is controllable - * by software: - * - * B1 USER: - * user and wake-up button connected to the I/O PA0 of the - * STM32F303VCT6. - * B2 RESET: - * pushbutton connected to NRST is used to RESET the STM32F303VCT6. - */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART - * - * USART1: Hardwired to embedded STLinkV2 hardware debugger - * RX (PC5) - * TX (PC4) - * - * USART2: - * Connect to an external UART<->RS232 transceiver for use as console. - * RX (PA3) - * TX (PA2) - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) -#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) - -/* SPI - * - * SPI1: Hardwired to ST L3GD20 MEMS device - * MISO (PA6) - * MSOI (PA7) - * SCK (PA5) - */ - -#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 -#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 -#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 - -/* I2C - * - * I2C1: Accessible via expansion headers - * SCL (PA15) - * SDA (PA14) - * SMBA (PB5) - * - * I2C2: Accessible via expansion headers - * SCL (PA9) - * SDA (PA10) - * SMBA (PB12) - */ - -#ifdef CONFIG_STM32_I2C1 -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) -#endif - -#ifdef CONFIG_STM32_I2C2 -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#endif - -/* USB */ - -#define GPIO_USB_DM (GPIO_USB_DM_0|GPIO_SPEED_50MHz) -#define GPIO_USB_DP (GPIO_USB_DP_0|GPIO_SPEED_50MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs deleted file mode 100644 index f4a90c1997c83..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f3discovery/scripts/ld.script b/boards/arm/stm32/stm32f3discovery/scripts/ld.script deleted file mode 100644 index eef4269081028..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/ld.script +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F303VCT has 256Kb of FLASH beginning at address 0x0800:0000 and - * 40Kb of SRAM. - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt deleted file mode 100644 index a5f1196b8266a..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt +++ /dev/null @@ -1,45 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f3discovery/src/Make.defs b/boards/arm/stm32/stm32f3discovery/src/Make.defs deleted file mode 100644 index 5ab0f6b49b4dd..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_USB),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c deleted file mode 100644 index fd2d12653cbcc..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,108 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, - GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_onoff - ****************************************************************************/ - -void board_autoled_onoff(int led, bool state) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], state); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - board_autoled_onoff(led, true); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - board_autoled_onoff(led, false); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c deleted file mode 100644 index fe33571227438..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f3discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB if the 1) USB device controller is in the configuration - * and 2) disabled, and 3) the weak function stm32_usbinitialize() has - * been brought into the build. Presumably either CONFIG_USBDEV is also - * selected. - */ - -#ifdef CONFIG_STM32_USB - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c b/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c deleted file mode 100644 index b0fc88f9be70b..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_USBDEV 1 -#define HAVE_USBMONITOR 1 - -/* Can't support USB device features if the STM32 USB peripheral is not - * enabled. - */ - -#ifndef CONFIG_STM32_USB -# undef HAVE_USBDEV -#endif - -/* Can't support USB device is USB device is not enabled */ - -#ifndef CONFIG_USBDEV -# undef HAVE_USBDEV -#endif - -/* Check if we should enable the USB monitor before starting NSH */ - -#ifndef CONFIG_USBMONITOR -# undef HAVE_USBMONITOR -#endif - -#ifndef HAVE_USBDEV -# undef CONFIG_USBDEV_TRACE -#endif - -#ifndef HAVE_USBHOST -# undef CONFIG_USBHOST_TRACE -#endif - -#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) -# undef HAVE_USBMONITOR -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32F3DISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c b/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c deleted file mode 100644 index ba6a750784797..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f3discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c b/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c deleted file mode 100644 index d929dcfd8ce89..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f3discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f3discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. This pin is used - * by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c deleted file mode 100644 index b5a17433a8794..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f3discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ - stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ - stm32_configgpio(GPIO_MEMS_INT2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - stm32_gpiowrite(GPIO_MEMS_CS, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c deleted file mode 100644 index 375d66d3408e4..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifdef CONFIG_STM32_USB - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_USB is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F3Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* Does the STM32 F3 have an external soft pull-up? */ -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this - * method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - return OK; -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("Resume: %d\n", resume); -} - -#endif /* CONFIG_STM32_USB */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c b/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c deleted file mode 100644 index 38ff516b8cb31..0000000000000 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f3discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, - GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED1-8 GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt deleted file mode 100644 index 0c3a3b0299f94..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig deleted file mode 100644 index 6389be0013f70..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_ADC1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig deleted file mode 100644 index f82b09d2f9091..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BMP280_I2C_ADDR_77=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BMP280=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_BMP280=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig deleted file mode 100644 index 51c16c29654b4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_PWM=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH1OUT=y -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig deleted file mode 100644 index de8ac9fa46eaa..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_HCSR04=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FREERUN=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig deleted file mode 100644 index cf6d3abb7978b..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_SLCD=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_BACKPACK=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig deleted file mode 100644 index 347ce193ef3ce..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2CTOOL_MAXBUS=1 -CONFIG_I2CTOOL_MINBUS=1 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_LM75=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_I2CTOOL=y -CONFIG_SYSTEM_LM75=y -CONFIG_SYSTEM_LM75_CELSIUS=y -CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp0" -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig deleted file mode 100644 index 2e2272e87d58d..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NX_DISABLE_1BPP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAX7219=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig deleted file mode 100644 index 9d8225dcdd8c7..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CL_MFRC522=y -CONFIG_DRIVERS_CONTACTLESS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_RFID_READUID=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig deleted file mode 100644 index c65f62a46b3d6..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set -# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_EXAMPLES_MODBUSMASTER=y -CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_MASTER=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MB_RTU_MASTER=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_BAUD=38400 -CONFIG_USART2_PARITY=2 -CONFIG_USART2_RS485=y -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig deleted file mode 100644 index 7067c5a9386f0..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_ASCII_ENABLED is not set -# CONFIG_MB_TCP_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_EXAMPLES_MODBUS=y -CONFIG_EXAMPLES_MODBUS_PORT=1 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_SLAVE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_BAUD=38400 -CONFIG_USART2_PARITY=2 -CONFIG_USART2_RS485=y -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig deleted file mode 100644 index 7df3e220a81dc..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig deleted file mode 100644 index 0f5de2d968ed2..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_QENCODER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_QENCODER=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_QE=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig deleted file mode 100644 index e5bc3efabcaf4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig deleted file mode 100644 index 4620407de0458..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig deleted file mode 100644 index c006b542eab46..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_FB=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_DD12864WO4A=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig deleted file mode 100644 index 9f84d79196068..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SYSTEM_TELNETD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_TELNETD=y -CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xC0A80101 -CONFIG_EXAMPLES_TELNETD_IPADDR=0xC0A80102 -CONFIG_FS_PROCFS=y -CONFIG_FS_TMPFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MEMFD_ERROR=y -CONFIG_LINE_MAX=64 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETINIT_DRIPADDR=0xC0A80101 -CONFIG_NETINIT_IPADDR=0xC0A80102 -CONFIG_NETINIT_NETMASK=0xFFFFFF00 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig deleted file mode 100644 index e3f070a97e28e..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_SDIO=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBMSC=y -CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig deleted file mode 100644 index d22a6dc62bec4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig deleted file mode 100644 index 26a52a6e1af7c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f401rc-rs485" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F401RC_RS485=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F401RC=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" -CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" -CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=3 -CONFIG_EXAMPLES_WS2812=y -CONFIG_EXAMPLES_WS2812_DEFAULT_DEV="/dev/leddrv0" -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=98304 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2014 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USBDEV=y -CONFIG_WS2812=y -CONFIG_WS2812_FREQUENCY=9000000 -CONFIG_WS2812_LED_COUNT=10 diff --git a/boards/arm/stm32/stm32f401rc-rs485/include/board.h b/boards/arm/stm32/stm32f401rc-rs485/include/board.h deleted file mode 100644 index 537c0650e1f76..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/include/board.h +++ /dev/null @@ -1,470 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F401RC-RS485 uses an external 32kHz crystal (X2) to enable HSE - * clock. - * - * System Clock source : PLL (HSI) - * SYSCLK(Hz) : 84000000 Determined by PLL - * configuration - * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 16 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - not installed - * LSE - not installed - */ - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_BOARD_USEHSI 1 - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. - * Some possible solutions include: - * - * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 - * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 - * - * We will configure like this - * - * PLL source is HSI - * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN - * = (16,000,000 / 16) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 4 = 84,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 336,000,000 / 7 = 48,000,000 - * - * REVISIT: Trimming of the HSI is not yet supported. - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 84000000ul - -/* AHB clock (HCLK) is SYSCLK (84MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) - -/* Timers driven from APB2 will be twice PCLK2 */ - -/* REVISIT */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in - * the future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART2: - * RXD: PA3 CN4 pin 20 - * TXD: PA2 CN4 pin 18 - */ - -#ifdef CONFIG_USART2_RS485 - /* Lets use for RS485 */ - -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ - - /* RS485 DIR pin: PA1 */ - -# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) - -#endif - -/* USART6: - * RXD: PC7 CN2 pin 15 - * TXD: PC6 CN2 pin 17 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - * - * The STM32F401RC-RS485 has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM3 CH1 on PA6. - */ - -#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) - -/* Quadrature Encoder - * - * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. - */ - -#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 -#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_1 - -/* HCSR04 driver */ - -/* Pins config to use with HC-SR04 sensor */ - -#define GPIO_HCSR04_INT (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN1) -#define GPIO_HCSR04_TRIG (GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN0) - -#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT -#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG -#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* MAX7219 */ - -#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) - -/* MFRC522 */ - -#define GPIO_RFID_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) - -/* MAX31855 */ - -#define GPIO_MAX31855_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) - -/* MAX6675 */ - -#define GPIO_MAX6675_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) -/* LEDs - * - * The STM32F401RC-RS485 boards provide 4 blue user LEDs. LD1, LD2, LD3 - * and LD4 that are connected to MCU I/O pins PC0, PC1, PC2 and PC3. - * - When the I/O is HIGH value, the LED is on. - * - When the I/O is LOW, the LED is off. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD1 0 -#define BOARD_LD2 1 -#define BOARD_LD3 2 -#define BOARD_LD4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LD1) -#define BOARD_LED2_BIT (1 << BOARD_LD2) -#define BOARD_LED3_BIT (1 << BOARD_LD3) -#define BOARD_LED4_BIT (1 << BOARD_LD4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related - * events as follows when the red LED (PE24) is available: - * - * SYMBOL Meaning LD2 - * ------------------- ----------------------- ----------- - * LED_STARTED NuttX has been started OFF - * LED_HEAPALLOCATE Heap has been allocated OFF - * LED_IRQSENABLED Interrupts enabled OFF - * LED_STACKCREATED Idle stack created ON - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed Blinking - * LED_IDLE MCU is in sleep mode Not used - * - * Thus if LD2, NuttX has successfully booted and is, apparently, running - * normally. If LD2 is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 1 - -/* Buttons - * The STM32F401RC-RS485 has 3 user buttons: SW3, SW4, and SW5. - * They are connected to PB13, PB14, and PB15 respectively. - */ - -#define BUTTON_SW3 0 -#define BUTTON_SW4 1 -#define BUTTON_SW5 2 -#define NUM_BUTTONS 3 - -#define BUTTON_SW3_BIT (1 << BUTTON_SW3) -#define BUTTON_SW4_BIT (1 << BUTTON_SW4) -#define BUTTON_SW5_BIT (1 << BUTTON_SW5) - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) - -/* Stepper Motor - DRV8266 */ - -#define GPIO_DIR (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7) -#define GPIO_STEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4) -#define GPIO_SLEEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) - -#define GPIO_M1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0) -#define GPIO_M2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) -#define GPIO_M3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) - -#define GPIO_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs b/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs deleted file mode 100644 index ac4d63351981c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32F401RC),y) -LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) - -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script b/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script deleted file mode 100644 index 855e00562cec4..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script +++ /dev/null @@ -1,109 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F401RC has 256Kb of FLASH beginning at address 0x0800:0000 and - * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, - * FLASH memory is aliased to address 0x0000:0000 where the code expects to - * begin execution by jumping to the entry point in the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - /* The STM32F401RC has 128Kb of SRAM beginning at the following address */ - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt deleted file mode 100644 index bf67263f69295..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt +++ /dev/null @@ -1,86 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_USERLED) - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_STM32_CONFIG_I2C_EE_24XXEEPROM) - list(APPEND SRCS stm32_at24.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_DEV_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_VIDEO_FB) - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_lcd_ssd1306.c) - endif() - if(CONFIG_LCD_ST7735) - list(APPEND SRCS stm32_lcd_st7735.c) - endif() -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32F401RC) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") -endif() diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs deleted file mode 100644 index 122740343adba..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs +++ /dev/null @@ -1,86 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_VIDEO_FB),y) - ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_lcd_ssd1306.c - endif - ifeq ($(CONFIG_LCD_ST7735),y) - CSRCS += stm32_lcd_st7735.c - endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_USERLED),y) -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_I2C_EE_24XX),y) -CSRCS += stm32_at24.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_DEV_GPIO),y) -CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) -CSRCS += stm32_hx711.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c deleted file mode 100644 index a8a60d7a591aa..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_STM32_ADC1 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The number of ADC channels in the conversion list */ - -#define ADC1_NCHANNELS 2 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Identifying number of each ADC channel. */ - -/* There are two trimpots on the board connected to ADC1_IN0 and ADC1_IN4 */ - -static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = -{ - 0, 4 -}; - -/* Configurations of pins used byte each ADC channels */ - -static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = -{ - GPIO_ADC\1_IN\2_0, - GPIO_ADC\1_IN\2_0 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - struct adc_dev_s *adc; - int ret; - int i; - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < ADC1_NCHANNELS; i++) - { - stm32_configgpio(g_adc1_pinlist[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register failed: %d\n", ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c deleted file mode 100644 index 4d37aa0c64f5d..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define AT24_I2C_BUS 1 /* EEPROM chip is configured to use I2C1 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_at24_init - * - * Description: - * Initialize and configure the AT24 serial EEPROM - * - ****************************************************************************/ - -int stm32_at24_init(char *path) -{ - struct i2c_master_s *i2c; - static bool initialized = false; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* No.. Get the I2C bus driver */ - - finfo("Initialize I2C%d\n", AT24_I2C_BUS); - i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); - if (!i2c) - { - ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); - return -ENODEV; - } - - /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ - - finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); - ret = ee24xx_initialize(i2c, 0x50, path, EEPROM_AT24CM02, false); - if (ret < 0) - { - ferr("ERROR: Failed to bind I2C%d to the AT24 EEPROM driver\n", - AT24_I2C_BUS); - return -ENODEV; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c deleted file mode 100644 index dd989cc1f1488..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c +++ /dev/null @@ -1,83 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#include - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LD2 GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c deleted file mode 100644 index e4a5038168bbe..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include - -#include "arm_internal.h" -#include "stm32f401rc-rs485.h" - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif - - /* Configure SPI chip selects if - * 1) SPI is not disabled, and - * 2) the weak function stm32_spidev_initialize() has been brought into - * the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - stm32_spidev_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c deleted file mode 100644 index eaf5642cb8a2b..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c +++ /dev/null @@ -1,404 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include -#include - -#include - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "stm32f401rc-rs485.h" - -#include - -#ifdef CONFIG_SENSORS_LM75 -#include "stm32_lm75.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#ifdef CONFIG_SENSORS_HCSR04 -#include "stm32_hcsr04.h" -#endif - -#ifdef CONFIG_LCD_MAX7219 -#include "stm32_max7219_matrix.h" -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#ifdef CONFIG_STEPPER_DRV8825 -#include "stm32_drv8266.h" -#endif - -#ifdef CONFIG_SENSORS_BMP280 -#include "stm32_bmp280.h" -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_WS2812 -#include "stm32_ws2812.h" -#endif - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_SENSORS_MAX31855 -#include "stm32_max31855.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef CONFIG_SENSORS_MAX31855 - /* Register device 0 on spi channel 1 */ - - ret = board_max31855_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: stm32_max31855initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: stm32_max6675initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_I2C_EE_24XX - ret = stm32_at24_init("/dev/eeprom"); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize EEPROM HX24LCXXB: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_LM75_I2C - /* Configure and initialize the LM75 sensor */ - - ret = board_lm75_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) - /* Initialize ADC and register the ADC driver. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_MAX7219 - /* Configure and initialize the MAX7219 driver */ - - ret = board_max7219_matrix_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, \ - "ERROR: board_max7219_matrix_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD driver: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, STM32F401RCRS485_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - -#ifdef CONFIG_SENSORS_HCSR04 - /* Configure and initialize the HC-SR04 distance sensor */ - - ret = board_hcsr04_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STEPPER_DRV8825 - /* Configure and initialize the drv8825 driver */ - - ret = board_drv8825_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_drv8825_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP280 - /* Initialize the BMP280 pressure sensor. */ - - ret = board_bmp280_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP280, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_WS2812) && defined(CONFIG_WS2812_LED_COUNT) - /* Configure and initialize the WS2812 LEDs. */ - - ret = board_ws2812_initialize(0, WS2812_SPI, CONFIG_WS2812_LED_COUNT); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - /* Initialize GPIO driver */ - - ret = stm32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c deleted file mode 100644 index f8ac4d7ec25f1..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F401RC RS485 button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c deleted file mode 100644 index fddefc25ae830..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c +++ /dev/null @@ -1,343 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOIN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; -#endif - -#if BOARD_NGPIOIN > 0 -/* This array maps the GPIO pins used as INPUT */ - -static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = -{ - GPIO_IN1, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; -#endif - -#if BOARD_NGPIOOUT -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_INT1, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -#if BOARD_NGPIOIN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); - return OK; -} -#endif - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); - return OK; -} - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); - return OK; -} -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); - return OK; -} - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers for use with /apps/examples/gpio - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - int pincount = 0; - -#if BOARD_NGPIOIN > 0 - for (i = 0; i < BOARD_NGPIOIN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register(&g_gpin[i].gpio, pincount); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpioinputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpiooutputs[i], 0); - stm32_configgpio(g_gpiooutputs[i]); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpiointinputs[i]); - - pincount++; - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c deleted file mode 100644 index 929558c3b1c02..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c deleted file mode 100644 index f4fe30a4acc60..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#include "stm32_ssd1306.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - int ret; - - /* Initialize the RESET and DC pins */ - - stm32_configgpio(GPIO_LCD_RESET); - stm32_configgpio(GPIO_LCD_DC); - - /* Reset the OLED display */ - - stm32_gpiowrite(GPIO_LCD_RESET, 0); - up_mdelay(1); - stm32_gpiowrite(GPIO_LCD_RESET, 1); - up_mdelay(120); - - ret = board_ssd1306_initialize(OLED_SPI_PORT); - if (ret < 0) - { - lcderr("ERROR: Failed to initialize SSD1306\n"); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int devno) -{ - return board_ssd1306_getdev(); -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c deleted file mode 100644 index 885152e7b3312..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f401rc-rs485.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM3 CH1. - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F401RCRS485_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F401RCRS485_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c deleted file mode 100644 index 7f140d6ee42ae..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c deleted file mode 100644 index e7e4de294213c..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c deleted file mode 100644 index ead5b4fcfcaea..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f401rc-rs485 - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - stm32_configgpio(GPIO_LCD_CS); /* LCD chip select */ -#endif - -#ifdef CONFIG_LCD_MAX7219 - stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ -#endif - -#ifdef CONFIG_CL_MFRC522 - stm32_configgpio(GPIO_RFID_CS); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX31855) - stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX66755) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - #if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_LCD_CS, !selected); - } - #endif - - #ifdef CONFIG_LCD_MAX7219 - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } - #endif - - #if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_RFID_CS, !selected); - } - #endif - - #if defined(CONFIG_SENSORS_MAX31855) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX31855_CS, !selected); - } - #endif - - #if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } - #endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(GPIO_LCD_DC, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c deleted file mode 100644 index 317d1358bc63f..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include "stm32_otgfs.h" -#include "stm32_gpio.h" -#include "stm32f401rc-rs485.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" -# undef HAVE_USB -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usb_configure - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the Olimex STM32 P407 board. - * - ****************************************************************************/ - -void stm32_usb_configure(void) -{ -#ifdef CONFIG_STM32_OTGFS - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* We don´t have the OTG FS VBUS sensing GPIO */ -#endif -} - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c deleted file mode 100644 index d5d633d8996be..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_mmcsd_initialize(port, CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c deleted file mode 100644 index b0b46ca4075e0..0000000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f401rc-rs485.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt deleted file mode 100644 index cc4e51625293c..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig b/boards/arm/stm32/stm32f411-minimum/Kconfig deleted file mode 100644 index 43f2f0018b8a8..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/Kconfig +++ /dev/null @@ -1,86 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_STM32F411_MINIMUM - -config STM32F411MINIMUM_USBHOST_STACKSIZE - int "USB host waiter stack size" - default 1024 - depends on USBHOST - -config STM32F411MINIMUM_USBHOST_PRIO - int "USB host waiter task priority" - default 100 - depends on USBHOST - -config STM32F411MINIMUM_FLASH - bool "MTD driver for external 8Mbyte W25Q64FV FLASH on SPI1" - default n - select MTD - select MTD_W25 - select MTD_SMART - select FS_SMARTFS - select STM32_SPI1 - select MTD_BYTE_WRITE - ---help--- - Configures an MTD device for use with the onboard flash - -config STM32F411MINIMUM_FLASH_MINOR - int "Minor number for the FLASH /dev/smart entry" - default 0 - depends on STM32F411MINIMUM_FLASH - ---help--- - Sets the minor number for the FLASH MTD /dev entry - -menuconfig STM32F411MINIMUM_HX711 - bool "Enable hx711 scale sensor" - default n - select ADC_HX711 - -if STM32F411MINIMUM_HX711 - -choice - prompt "Select GPIO port for clock pin" - default STM32F411MINIMUM_HX711_CLK_PORTA - -config STM32F411MINIMUM_HX711_CLK_PORTA - bool "Port A" -config STM32F411MINIMUM_HX711_CLK_PORTB - bool "Port B" - -endchoice # Select GPIO port for clock pin - -config STM32F411MINIMUM_HX711_CLK_PIN - int "Select GPIO pin number for clock pin" - default 1 - range 0 15 - -choice - prompt "Select GPIO port for data pin" - default STM32F411MINIMUM_HX711_DATA_PORTA - -config STM32F411MINIMUM_HX711_DATA_PORTA - bool "Port A" -config STM32F411MINIMUM_HX711_DATA_PORTB - bool "Port B" - -endchoice # Select GPIO port for data pin - -config STM32F411MINIMUM_HX711_DATA_PIN - int "Select GPIO pin number for data pin" - default 2 - range 0 15 - -endif # STM32F411MINIMUM_HX711 - -menuconfig STM32F411MINIMUM_GPIO - select DEV_GPIO - bool "enable gpio subsystem" - -if STM32F411MINIMUM_GPIO -source "boards/arm/stm32/stm32f411-minimum/Kconfig.gpio" -endif - -endif diff --git a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig deleted file mode 100644 index 815e19ca8b04b..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_COMPOSITE=y -CONFIG_COMPOSITE_IAD=y -CONFIG_COMPOSITE_PRODUCTID=0x2022 -CONFIG_COMPOSITE_VENDORID=0x03eb -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_OTG_ID_GPIO_DISABLE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_CDCACM=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig deleted file mode 100644 index 4f5c7bc0cdbe1..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig deleted file mode 100644 index d2c984c4aeee8..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PWM=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig deleted file mode 100644 index f1273c7d5650f..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=6 -CONFIG_START_YEAR=2020 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_CHMODE=0 -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_CHMODE=0 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_CHMODE=0 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_TIM4=y -CONFIG_STM32_TIM4_CH4OUT=y -CONFIG_STM32_TIM4_CHANNEL=4 -CONFIG_STM32_TIM4_CHMODE=0 -CONFIG_STM32_TIM4_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig deleted file mode 100644 index 5ca14bc662afa..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig deleted file mode 100644 index d489172e6a3a7..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411-minimum" -CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411CE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_OTG_ID_GPIO_DISABLE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_STM32F411MINIMUM_FLASH=y -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_FLASH_PREFETCH=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" -CONFIG_TASK_NAME_SIZE=15 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_BUSPOWERED=y -CONFIG_USBMSC=y diff --git a/boards/arm/stm32/stm32f411-minimum/include/board.h b/boards/arm/stm32/stm32f411-minimum/include/board.h deleted file mode 100644 index 5d353b961ca77..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/include/board.h +++ /dev/null @@ -1,363 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL config - * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 4 (STM32_PLLCFG_PLLM) - * PLLN : 192 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 25 MHz Crystal - * LSE - 32 KHz Crystal - */ - -#define STM32_BOARD_XTAL 25000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_LSE_FREQUENCY 32768 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 - * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 - * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 - * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 - * - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the USB - * clock = 48MHz - * - * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (25,000,000 / 25) * 192 - * = 192,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 192,000,000 / 2 = 96,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 96,000,000 / 2 = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM4 CH2 on PD13. - */ -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) //PA8 -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) //PA1 -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) //PB0 -#define GPIO_TIM4_CH4OUT (GPIO_TIM4_CH4OUT_1|GPIO_SPEED_50MHz) //PB9 - -/* RGB LED - * - * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 - * - * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT - */ - -#define RGBLED_RPWMTIMER 1 -#define RGBLED_RPWMCHANNEL 1 -#define RGBLED_GPWMTIMER 2 -#define RGBLED_GPWMCHANNEL 2 -#define RGBLED_BPWMTIMER 4 -#define RGBLED_BPWMCHANNEL 4 - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. - */ - -/* The board has only one controllable LED */ - -#define LED_STARTED 0 /* No LEDs */ -#define LED_HEAPALLOCATE 1 /* LED1 on */ -#define LED_IRQSENABLED 2 /* LED1 on */ -#define LED_STACKCREATED 3 /* LED1 on */ -#define LED_INIRQ 4 /* LED1 on */ -#define LED_SIGNAL 5 /* LED1 on */ -#define LED_ASSERTION 6 /* LED1 on */ -#define LED_PANIC 7 /* LED1 blinking */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_NLEDS 1 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PA0 of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define BUTTON_EXTERNAL 1 //External user button connected to PA1 -#define NUM_BUTTONS 2 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) -#define BUTTON_EXTERNAL_BIT (1 << BUTTON_EXTERNAL) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs deleted file mode 100644 index 3a41209051dfc..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411-minimum/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = stm32f411ce.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt deleted file mode 100644 index 67ae6a038bb8a..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -endif() - -if(CONFIG_USERLED) - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_MTD_W25) - list(APPEND SRCS stm32_w25.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_USBDEV_COMPOSITE) - list(APPEND SRCS stm32_composite.c) -endif() - -if(CONFIG_STM32F411MINIMUM_GPIO) - list(APPEND SRCS stm32_gpio.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32f411ce.ld") diff --git a/boards/arm/stm32/stm32f411-minimum/src/Make.defs b/boards/arm/stm32/stm32f411-minimum/src/Make.defs deleted file mode 100644 index a221a572f16d4..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/Make.defs +++ /dev/null @@ -1,77 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411-minimum/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -endif - -ifeq ($(CONFIG_USERLED),y) - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_RGBLED),y) - CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) - CSRCS += stm32_hx711.c -endif - -ifeq ($(CONFIG_SPI),y) - CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32F411MINIMUM_GPIO),y) - CSRCS += stm32_gpio.c -endif - -ifeq ($(CONFIG_MTD_W25),y) - CSRCS += stm32_w25.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) - CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) - CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c deleted file mode 100644 index 9846714e8d892..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void set_led(bool v) -{ - ledinfo("Turn LED %s\n", v? "on":"off"); - stm32_gpiowrite(GPIO_LED1, !v); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LED1); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - ledinfo("board_autoled_on(%d)\n", led); - - switch (led) - { - case LED_STARTED: - case LED_HEAPALLOCATE: - /* As the board provides only one soft controllable LED, we simply - * turn it on when the board boots. - */ - - set_led(true); - break; - - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(true); - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - - /* For panic state, the LED is blinking */ - - set_led(false); - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c deleted file mode 100644 index c37c11bf046ca..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c deleted file mode 100644 index e81aad31989ab..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c +++ /dev/null @@ -1,187 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Checking needed by W25 Flash */ - -#define HAVE_W25 1 - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_W25 -#endif - -/* Default W25 minor number */ - -#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) -# define CONFIG_NSH_W25MINOR 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure and initialize the RGB LED. */ - - ret = stm32_rgbled_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO - ret = stm32_gpio_initialize(); - if (ret != OK) - { - gerr("ERROR: Failed to initialize gpio: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_W25 - /* Initialize and register the W25 FLASH file system. */ - - ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", - CONFIG_NSH_W25MINOR, ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c deleted file mode 100644 index ff1867283277c..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER, GPIO_BTN_EXTERNAL -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c deleted file mode 100644 index 78bd6f5a5b8cd..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c +++ /dev/null @@ -1,278 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/smart0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/smart0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/smart0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application specific wrapper for usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - if (g_mschandle) - { - usbmsc_uninitialize(g_mschandle); - } - - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - /* Here we are composing the configuration of the usb composite device. - * - * The standard is to use one CDC/ACM and one USB mass storage device. - */ - - if (configid == 0) - { - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - int dev_idx = 0; - -#ifdef CONFIG_USBMSC_COMPOSITE - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[dev_idx].classobject = board_mscclassobject; - dev[dev_idx].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 3; - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 3; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - dev_idx++; -#endif - -#ifdef CONFIG_CDCACM_COMPOSITE - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[dev_idx].classobject = cdcacm_classobject; - dev[dev_idx].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 2; - dev_idx++; -#endif - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); - } - else - { - return NULL; - } -} - -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c deleted file mode 100644 index 754e624d61a77..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c +++ /dev/null @@ -1,741 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct stm32gpint_dev_s -{ - struct stm32gpio_dev_s stm32gpio; - pin_interrupt_t callback; -}; - -struct stm32gpio_info_s -{ - uint32_t pin; - const char *pinname; /* Holds pin name like gpio_a0, gpio_custom_name */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value); -#endif - -#if BOARD_NGPIO_OUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -#endif - -#if BOARD_NGPIO_INT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static const struct gpio_operations_s gpin_ops = -{ - .go_read = gpin_read, - .go_write = NULL, - .go_attach = NULL, - .go_enable = NULL, -}; - -static struct stm32gpio_dev_s g_gpin[BOARD_NGPIO_IN]; -static const struct stm32gpio_info_s g_gpio_inputs[BOARD_NGPIO_IN] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_IN - { .pin = GPIO_A0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_IN - { .pin = GPIO_A1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_IN - { .pin = GPIO_A2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_IN - { .pin = GPIO_A3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_IN - { .pin = GPIO_A4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_IN - { .pin = GPIO_A5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_IN - { .pin = GPIO_A6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_IN - { .pin = GPIO_A7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_IN - { .pin = GPIO_A8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_IN - { .pin = GPIO_A9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_IN - { .pin = GPIO_A10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_IN - { .pin = GPIO_A11_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_IN - { .pin = GPIO_A12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_IN - { .pin = GPIO_A15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_IN - { .pin = GPIO_B0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_IN - { .pin = GPIO_B1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_IN - { .pin = GPIO_B2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_IN - { .pin = GPIO_B3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_IN - { .pin = GPIO_B4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_IN - { .pin = GPIO_B5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_IN - { .pin = GPIO_B6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_IN - { .pin = GPIO_B7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_IN - { .pin = GPIO_B8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_IN - { .pin = GPIO_B9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_IN - { .pin = GPIO_B10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_IN - { .pin = GPIO_B12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_IN - { .pin = GPIO_B13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_IN - { .pin = GPIO_B14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_IN - { .pin = GPIO_B15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_IN - { .pin = GPIO_C13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_IN - { .pin = GPIO_C14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_IN - { .pin = GPIO_C15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_IN > 0 */ - -#if BOARD_NGPIO_OUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, -}; - -static struct stm32gpio_dev_s g_gpout[BOARD_NGPIO_OUT]; -static const struct stm32gpio_info_s g_gpio_outputs[BOARD_NGPIO_OUT] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_OUT - { .pin = GPIO_A0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_OUT - { .pin = GPIO_A1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_OUT - { .pin = GPIO_A2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_OUT - { .pin = GPIO_A3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_OUT - { .pin = GPIO_A4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_OUT - { .pin = GPIO_A5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_OUT - { .pin = GPIO_A6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_OUT - { .pin = GPIO_A7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_OUT - { .pin = GPIO_A8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_OUT - { .pin = GPIO_A9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_OUT - { .pin = GPIO_A10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_OUT - { .pin = GPIO_A11_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_OUT - { .pin = GPIO_A12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_OUT - { .pin = GPIO_A15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_OUT - { .pin = GPIO_B0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_OUT - { .pin = GPIO_B1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_OUT - { .pin = GPIO_B2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_OUT - { .pin = GPIO_B3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_OUT - { .pin = GPIO_B4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_OUT - { .pin = GPIO_B5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_OUT - { .pin = GPIO_B6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_OUT - { .pin = GPIO_B7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_OUT - { .pin = GPIO_B8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_OUT - { .pin = GPIO_B9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_OUT - { .pin = GPIO_B10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_OUT - { .pin = GPIO_B12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_OUT - { .pin = GPIO_B13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_OUT - { .pin = GPIO_B14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_OUT - { .pin = GPIO_B15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_OUT - { .pin = GPIO_C13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_OUT - { .pin = GPIO_C14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_OUT - { .pin = GPIO_C15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_OUT > 0 */ - -#if BOARD_NGPIO_INT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, -}; - -static struct stm32gpint_dev_s g_gpint[BOARD_NGPIO_INT]; -static const struct stm32gpio_info_s g_gpio_int_inputs[BOARD_NGPIO_INT] = -{ -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_INT - { .pin = GPIO_A0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_INT - { .pin = GPIO_A1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_INT - { .pin = GPIO_A2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_INT - { .pin = GPIO_A3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_INT - { .pin = GPIO_A4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_INT - { .pin = GPIO_A5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_INT - { .pin = GPIO_A6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_INT - { .pin = GPIO_A7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_INT - { .pin = GPIO_A8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_INT - { .pin = GPIO_A9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_INT - { .pin = GPIO_A10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_INT - { .pin = GPIO_A11_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_INT - { .pin = GPIO_A12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_INT - { .pin = GPIO_A15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_INT - { .pin = GPIO_B0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_INT - { .pin = GPIO_B1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_INT - { .pin = GPIO_B2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_INT - { .pin = GPIO_B3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_INT - { .pin = GPIO_B4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_INT - { .pin = GPIO_B5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_INT - { .pin = GPIO_B6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_INT - { .pin = GPIO_B7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_INT - { .pin = GPIO_B8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_INT - { .pin = GPIO_B9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_INT - { .pin = GPIO_B10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_INT - { .pin = GPIO_B12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_INT - { .pin = GPIO_B13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_INT - { .pin = GPIO_B14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_INT - { .pin = GPIO_B15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_INT - { .pin = GPIO_C13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_INT - { .pin = GPIO_C14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, -#endif - -#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_INT - { .pin = GPIO_C15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, -#endif -}; -#endif /* BOARD_NGPIO_INT > 0 */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpin_read - ****************************************************************************/ - -#if BOARD_NGPIO_IN > 0 -static int gpin_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_IN); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpio_inputs[stm32gpio->id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpout_read - ****************************************************************************/ - -#if BOARD_NGPIO_OUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL && value != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); - gpioinfo("Reading...\n"); - - *value = stm32_gpioread(g_gpio_outputs[stm32gpio->id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpout_write - ****************************************************************************/ - -#if BOARD_NGPIO_OUT > 0 -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct stm32gpio_dev_s *stm32gpio = - (struct stm32gpio_dev_s *)dev; - - DEBUGASSERT(stm32gpio != NULL); - DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); - gpioinfo("Writing %d\n", (int)value); - - stm32_gpiowrite(g_gpio_outputs[stm32gpio->id].pin, value); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_read - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - DEBUGASSERT(stm32gpint != NULL && value != NULL); - DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIO_INT); - gpioinfo("Reading int pin...\n"); - - *value = stm32_gpioread(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32gpio_interrupt - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int stm32gpio_interrupt(int irq, void *context, void *arg) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)arg; - - DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); - - stm32gpint->callback(&stm32gpint->stm32gpio.gpio, - stm32gpint->stm32gpio.id); - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_attach - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, false, - false, false, NULL, NULL); - - gpioinfo("Attach %p\n", callback); - stm32gpint->callback = callback; - return OK; -} -#endif - -/**************************************************************************** - * Name: gpint_enable - ****************************************************************************/ - -#if BOARD_NGPIO_INT > 0 -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct stm32gpint_dev_s *stm32gpint = - (struct stm32gpint_dev_s *)dev; - - if (enable) - { - if (stm32gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, - true, false, false, stm32gpio_interrupt, - &g_gpint[stm32gpint->stm32gpio.id]); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, - false, false, false, NULL, NULL); - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpio_initialize - * - * Description: - * Initialize GPIO drivers - * - ****************************************************************************/ - -int stm32_gpio_initialize(void) -{ - int i; - -#if BOARD_NGPIO_IN > 0 - for (i = 0; i < BOARD_NGPIO_IN; i++) - { - /* Setup and register the GPIO pin */ - - g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; - g_gpin[i].gpio.gp_ops = &gpin_ops; - g_gpin[i].id = i; - gpio_pin_register_byname(&g_gpin[i].gpio, g_gpio_inputs[i].pinname); - - /* Configure the pin that will be used as input */ - - stm32_configgpio(g_gpio_inputs[i].pin); - } -#endif - -#if BOARD_NGPIO_OUT > 0 - for (i = 0; i < BOARD_NGPIO_OUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register_byname(&g_gpout[i].gpio, g_gpio_outputs[i].pinname); - - /* Configure the pin that will be used as output */ - - stm32_gpiowrite(g_gpio_outputs[i].pin, 0); - stm32_configgpio(g_gpio_outputs[i].pin); - } -#endif - -#if BOARD_NGPIO_INT > 0 - for (i = 0; i < BOARD_NGPIO_INT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].stm32gpio.id = i; - gpio_pin_register_byname(&g_gpint[i].stm32gpio.gpio, - g_gpio_int_inputs[i].pinname); - - /* Configure the pin that will be used as interrupt input */ - - stm32_configgpio(g_gpio_int_inputs[i].pin); - } -#endif - - return 0; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c deleted file mode 100644 index ce88a74bcbf18..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c deleted file mode 100644 index 6f7354477ca86..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f411-minimum has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connect to CN5 just for this purpose: - * - * PB0 ADC12_IN8/TIM3_CH3 - * - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F411MINIMUM_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F411MINIMUM_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c deleted file mode 100644 index faaa9e4871b94..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c +++ /dev/null @@ -1,185 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_RGBLED -#endif - -#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL -# undef HAVE_PWM -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Initial for support of a connected RGB LED using PWM. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, - RGBLED_BPWMCHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c deleted file mode 100644 index 890f8cc3db280..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c +++ /dev/null @@ -1,175 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins - * for the WeAct Studio MiniF4 board. - * - ****************************************************************************/ - -void stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#ifdef CONFIG_MTD_W25 - stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ -#endif - -#ifdef CONFIG_MMCSD_SPI - stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2select and stm32_spi1/2status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_SDCARD_CS, !selected); - } -#endif - -#ifdef CONFIG_MTD_W25 - stm32_gpiowrite(FLASH_SPI1_CS, !selected); -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_MMCSD_SPI - if (devid == SPIDEV_MMCSD(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, - bool cmd) -{ - return -ENODEV; -} -#endif -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c deleted file mode 100644 index 08afc617c0cf9..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c +++ /dev/null @@ -1,329 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f411-minimum.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411MINIMUM_USBHOST_PRIO -# define CONFIG_STM32F411MINIMUM_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE -# define CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB-related GPIO pins for the WeAct Studio MiniF4 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. No GPIO configuration is - * required - * This board has no connections for VBUS, Power On, or Overcurrent - * GPIOs - */ -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. This function will start a thread that will monitor for - * device connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411MINIMUM_USBHOST_PRIO, - CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a charge - * pump or, if 5 V are available on the application board, a basic power - * switch, must be added externally to drive the 5 V VBUS line. The - * external charge pump can be driven by any GPIO output. When the - * application decides to power on VBUS using the chosen GPIO, it must - * also set the port power bit in the host port control and status - * register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, and the - * core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent condition - * is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, - * etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c deleted file mode 100644 index 19084231667d2..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_w25initialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c deleted file mode 100644 index 3abebf3e77c49..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411-minimum.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c deleted file mode 100644 index 17427b4e92684..0000000000000 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c +++ /dev/null @@ -1,156 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_STM32_SPI1 -# include -# include -# include -# include -#endif - -#include "stm32_spi.h" - -#include "stm32f411-minimum.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the watchdog - * timer - */ - -#define W25_SPI_PORT 1 - -/* Configuration ************************************************************/ - -/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ - -#define HAVE_W25 1 -#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) -# undef HAVE_W25 -#endif - -/* Can't support W25 features if mountpoints are disabled */ - -#if defined(CONFIG_DISABLE_MOUNTPOINT) -# undef HAVE_W25 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_w25initialize - * - * Description: - * Initialize and register the W25 FLASH file system. - * - ****************************************************************************/ - -int stm32_w25initialize(int minor) -{ - int ret; -#ifdef HAVE_W25 - struct spi_dev_s *spi; - struct mtd_dev_s *mtd; - struct mtd_geometry_s geo; -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F411MINIMUM_FLASH_PART_NAMES; -#endif - - /* Get the SPI port */ - - spi = stm32_spibus_initialize(W25_SPI_PORT); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", - W25_SPI_PORT); - return -ENODEV; - } - - /* Raise SPI frequency from default 400kHz to something usable - * SPI1 uses PCLK2 of 96MHz with DIV2 = 48Mbps max - * W25Q64 requires more dummy clocks above 26MHz - */ - - SPI_SETFREQUENCY(spi, 24000000); - - /* Now bind the SPI interface to the W25 SPI FLASH driver */ - - mtd = w25_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" - "W25 FLASH driver\n", W25_SPI_PORT); - return -ENODEV; - } - -#ifndef CONFIG_FS_SMARTFS - /* Register the MTD driver */ - - char path[32]; - snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); - ret = register_mtddriver(path, mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to register the MTD driver %s, ret %d\n", - path, ret); - return ret; - } -#else - /* Initialize to provide SMARTFS on the MTD interface */ - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F411MINIMUM_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_FS_SMARTFS */ -#endif /* HAVE_W25 */ - - return OK; -} diff --git a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt deleted file mode 100644 index 884177caaef25..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig deleted file mode 100644 index db7826a6b94f1..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32_SYSCFG is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f411e-disco" -CONFIG_ARCH_BOARD_STM32F411E_DISCO=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F411VE=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=8499 -CONFIG_BUILTIN=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=131072 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=14 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2014 -CONFIG_STM32_FLASH_CONFIG_E=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f411e-disco/include/board.h b/boards/arm/stm32/stm32f411e-disco/include/board.h deleted file mode 100644 index 903bf73d31712..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/include/board.h +++ /dev/null @@ -1,358 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL - * configuration - * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 4 (STM32_PLLCFG_PLLM) - * PLLN : 192 (STM32_PLLCFG_PLLN) - * PLLP : 4 (STM32_PLLCFG_PLLP) - * PLLQ : 8 (STM32_PLLCFG_PPQ) - * Flash Latency(WS) : 3 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - 8 MHz Crystal - * LSE - not installed - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL - -/* Main PLL Configuration. - * - * Formulae: - * - * VCO input frequency = PLL input clock frequency / PLLM, - * 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, - * 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, - * PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, - * 2 <= PLLQ <= 15 - * - * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the - * USB clock= 48MHz. - * - * PLLQ = 8 PLLP = 4 PLLN=192 PLLM=4 - * - * We will configure like this - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 4) * 192 - * = 384,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 384,000,000 / 4 = 96,000,000 - * USB OTG FS and SDIO Clock - * = PLL_VCO / PLLQ - * = 384,000,000 / 8 = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) - -#define STM32_SYSCLK_FREQUENCY 96000000ul - -/* AHB clock (HCLK) is SYSCLK (96MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -/* REVISIT */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (48MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -/* REVISIT */ - -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz - */ - -/* REVISIT */ - -#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz - * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz - */ - -/* REVISIT */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future is we set aside more DMA channels/streams. - * - * SDIO DMA - *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA - *   DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* Need to VERIFY fwb */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 - */ - -#if 1 -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ -#else -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ -#endif - -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ - -#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ -#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 - -/* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ - -/* UART RX DMA configurations */ - -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 - -/* I2C - * - * The optional _GPIO configurations allow the I2C driver to manually - * reset the bus to clear stuck slaves. They match the pin configuration, - * but are normally-high GPIOs. - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) -#define GPIO_I2C1_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) - -#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) -#define GPIO_I2C2_SCL_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) -#define GPIO_I2C2_SDA_GPIO \ - (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) - -/* SPI - * - * There are sensors on SPI1, and SPI2 is connected to the FRAM. - */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) - -/* LEDs - * - * The STM32F411E Discovery board has four user leds - * LD3 connected to PD13. - * LD4 connected to PD12. - * LD5 connected to PD14. - * LD6 connected to PD15. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LD3 0 -#define BOARD_LD4 1 -#define BOARD_LD5 2 -#define BOARD_LD6 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LD3_BIT (1 << BOARD_LD3) -#define BOARD_LD4_BIT (1 << BOARD_LD4) -#define BOARD_LD5_BIT (1 << BOARD_LD5) -#define BOARD_LD6_BIT (1 << BOARD_LD6) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board. - * The following definitions describe how NuttX controls - * the LEDs: - * - * SYMBOL Meaning LED - * ------------------- ---------------------------- -------------------- - */ - -#define LED_STARTED 0 /* NuttX has been started None */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON(1), OFF(2) */ -#define LED_IRQSENABLED 2 /* Interrupts enabled OFF(1), ON(2) */ -#define LED_STACKCREATED 3 /* Idle stack created ON(1), ON(2) */ -#define LED_INIRQ 4 /* In an interrupt (no change) */ -#define LED_SIGNAL 5 /* In a signal handler (no change) */ -#define LED_ASSERTION 6 /* An assertion failed ON(3) */ -#define LED_PANIC 7 /* The system has crashed FLASH(1,2) */ -#define LED_IDLE 8 /* idle loop FLASH(4) */ - -/* Buttons - * - * B1 USER: the user button is connected to the I/O PA0 of the STM32 - * microcontroller. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* USB OTG FS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs deleted file mode 100644 index 606d070f68d40..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411e-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = f411ve.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt deleted file mode 100644 index 9f3433d0cc824..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt +++ /dev/null @@ -1,31 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c) - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f411ve.ld") diff --git a/boards/arm/stm32/stm32f411e-disco/src/Make.defs b/boards/arm/stm32/stm32f411e-disco/src/Make.defs deleted file mode 100644 index cff6ead802f11..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f411e-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += stm32_autoleds.c -else - CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c deleted file mode 100644 index 07237023ba414..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,134 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f411e-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED GPIO for output */ - - stm32_configgpio(GPIO_LD3); - stm32_configgpio(GPIO_LD4); - stm32_configgpio(GPIO_LD5); - stm32_configgpio(GPIO_LD6); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - switch (led) - { - case LED_HEAPALLOCATE: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, false); - } - break; - - case LED_IRQSENABLED: - { - stm32_gpiowrite(GPIO_LD3, false); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_STACKCREATED: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_ASSERTION: - { - stm32_gpiowrite(GPIO_LD5, true); - } - break; - - case LED_PANIC: - { - stm32_gpiowrite(GPIO_LD3, true); - stm32_gpiowrite(GPIO_LD4, true); - } - break; - - case LED_IDLE: - { - stm32_gpiowrite(GPIO_LD6, true); - } - break; - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - switch (led) - { - case LED_PANIC: - { - stm32_gpiowrite(GPIO_LD3, false); - stm32_gpiowrite(GPIO_LD4, false); - } - break; - - case LED_IDLE: - { - stm32_gpiowrite(GPIO_LD6, false); - } - break; - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c deleted file mode 100644 index 9aecad9bdee43..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f411e-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the - * weak function stm32_spidev_initialize() has been brought into the link. - */ - - stm32_spidev_initialize(); -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the OTG FS controller is in the configuration. - * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. - */ - - stm32_usbinitialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c deleted file mode 100644 index fe85d312f3e6b..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "stm32.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32f411e-disco.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) - /* Initialize USB host operation. stm32_usbhost_initialize() starts - * a thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - ferr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c deleted file mode 100644 index ef990dc549be1..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f411e-disco.h" - -#if defined(CONFIG_ARCH_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) -# error "The NuttX Buttons Driver depends on IRQ support to work!\n" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns - * an 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, - arg); - } - - return ret; -} -#endif - -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c deleted file mode 100644 index 83372a115e995..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +++ /dev/null @@ -1,353 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. - * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. - * SPDX-FileContributor: Gregory Nutt - * SPDX-FileContributor: Brian Webb - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f411e-disco.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO -# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F411 board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, - CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c deleted file mode 100644 index a4b0a2bf7745a..0000000000000 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32f411e-disco.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static const uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LD3, - GPIO_LD4, - GPIO_LD5, - GPIO_LD6, -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_configgpio(g_ledcfg[i]); - } - - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - int i; - - /* Configure LED GPIOs for output */ - - for (i = 0; i < BOARD_NLEDS; i++) - { - stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); - } -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt deleted file mode 100644 index 7e51cbd70df83..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig deleted file mode 100644 index 1addeb2e1b8d0..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_CCMEXCLUDE is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ADC=y -CONFIG_ANALOG=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=3 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC3=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_ADC=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig deleted file mode 100644 index aa691be350b72..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FBOVERLAY=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY_BLIT=y -CONFIG_FB_SYNC=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=7774208 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=128 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MAXARGUMENTS=17 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y -CONFIG_VIDEO_FB_SPLASHSCREEN=y -CONFIG_VIDEO_FB_SPLASHSCREEN_BPP16=y -CONFIG_VIDEO_FB_SPLASHSCREEN_DISP_TIME=2 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig deleted file mode 100644 index cccc4378d2312..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MTD_CONFIG=y -CONFIG_MTD_CONFIG_RAM_CONSOLIDATE=y -CONFIG_MTD_PARTITION=y -CONFIG_MTD_PARTITION_NAMES=y -CONFIG_MTD_SMART_SECTOR_SIZE=512 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PLATFORM_CONFIGDATA=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMARTFS_MULTI_ROOT_DIRS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_FLASH=y -CONFIG_STM32F429I_DISCO_FLASH_PART=y -CONFIG_STM32F429I_DISCO_RAMMTD=y -CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RNG=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig deleted file mode 100644 index a98b7de6841a9..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FBOVERLAY=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY_BLIT=y -CONFIG_FB_SYNC=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=7774208 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=128 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_MAXARGUMENTS=17 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig deleted file mode 100644 index 82332b7e9fe95..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_LIBC_FLOATINGPOINT is not set -# CONFIG_NSH_DISABLE_MW is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INTERRUPTSTACK=4096 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIB_GDBSTUB=y -CONFIG_LIB_GDBSTUB_DEBUG=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_GDBSTUB=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig deleted file mode 100644 index 816e761186400..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_NOOPT=y -CONFIG_HAVE_CXX=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_HIGHPRI=y -CONFIG_STM32_ADC1=y -CONFIG_STM32_ADC1_DMA=y -CONFIG_STM32_ADC1_DMA_CFG=1 -CONFIG_STM32_ADC1_EXTSEL=y -CONFIG_STM32_ADC1_INJECTED_CHAN=1 -CONFIG_STM32_ADC_LL_OPS=y -CONFIG_STM32_ADC_NOIRQ=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWM_LL_OPS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_READLINE=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig deleted file mode 100644 index a0308040c9199..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NX=y -CONFIG_EXAMPLES_NX_BPP=16 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_ILI9341=y -CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NX_BLOCKING=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y -CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig deleted file mode 100644 index 36849b2e3e81e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ /dev/null @@ -1,83 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_LV_BUILD_EXAMPLES is not set -# CONFIG_STM32_FB_CMAP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_LVGLDEMO=y -CONFIG_EXAMPLES_TOUCHSCREEN=y -CONFIG_FB_OVERLAY=y -CONFIG_FS_PROCFS=y -CONFIG_GRAPHICS_LVGL=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8081408 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LV_USE_CLIB_MALLOC=y -CONFIG_LV_USE_CLIB_SPRINTF=y -CONFIG_LV_USE_CLIB_STRING=y -CONFIG_LV_USE_DEMO_WIDGETS=y -CONFIG_LV_USE_LOG=y -CONFIG_LV_USE_NUTTX=y -CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2017 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI5=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig deleted file mode 100644 index 37383ba2e6239..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig deleted file mode 100644 index 4daefe0a7476f..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FB_CMAP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEV_LOOP=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=16 -CONFIG_EXAMPLES_NXHELLO_SERVERPRIO=110 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NX_BLOCKING=y -CONFIG_NX_WRITEONLY=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=214688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=7 -CONFIG_START_MONTH=2 -CONFIG_START_YEAR=2019 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_DMA2D=y -CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 -CONFIG_STM32_DMA2D_FB_SIZE=307200 -CONFIG_STM32_DMA2D_LAYER_PPLINE=240 -CONFIG_STM32_DMA2D_NLAYERS=2 -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD076A000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig deleted file mode 100644 index 1db71182f3112..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ /dev/null @@ -1,111 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -# CONFIG_STM32_LTDC_L2 is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FB_OVERLAY=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xd0000000 -CONFIG_HEAP2_SIZE=8081408 -CONFIG_INIT_ENTRYPOINT="nxwm_main" -CONFIG_INPUT=y -CONFIG_INPUT_STMPE811=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTERM=y -CONFIG_NXTERM_CACHESIZE=32 -CONFIG_NXTERM_CURSORCHAR=95 -CONFIG_NXTERM_MXCHARS=325 -CONFIG_NXTERM_NXKBDIN=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NXWIDGETS=y -CONFIG_NXWIDGETS_BPP=16 -CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y -CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y -CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb -CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 -CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e -CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 -CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf -CONFIG_NXWIDGETS_SIZEOFCHAR=1 -CONFIG_NXWM=y -CONFIG_NXWM_CALIBRATION_AVERAGE=y -CONFIG_NXWM_CALIBRATION_MESSAGES=y -CONFIG_NXWM_CALIBRATION_NSAMPLES=2 -CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y -CONFIG_NXWM_HEXCALCULATOR_FONTID=5 -CONFIG_NXWM_KEYBOARD=y -CONFIG_NXWM_TASKBAR_LEFT=y -CONFIG_NXWM_TASKBAR_VSPACING=4 -CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=15 -CONFIG_START_MONTH=11 -CONFIG_STM32F429I_DISCO_ILI9341=y -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_I2C3=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LTDC=y -CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 -CONFIG_STM32_LTDC_FB_SIZE=307200 -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STMPE811_ACTIVELOW=y -CONFIG_STMPE811_EDGE=y -CONFIG_STMPE811_THRESHX=39 -CONFIG_STMPE811_THRESHY=51 -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig deleted file mode 100644 index f948552f17c6d..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARDCTL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRVR_MKRD=y -CONFIG_FRAME_POINTER=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYNAME="ofloader" -CONFIG_INIT_ENTRYPOINT="ofloader_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_REGIONS=3 -CONFIG_MTD=y -CONFIG_MTD_PROGMEM=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FLASH_CONFIG_I=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_OFLOADER=y -CONFIG_SYSTEM_OFLOADER_BUFFERSIZE=4096 -CONFIG_SYSTEM_OFLOADER_DEBUG=y -CONFIG_SYSTEM_OFLOADER_TABLE="/dev/flash,0x08000000,0x20000" -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig deleted file mode 100644 index c9e0881603240..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_INSTRUMENT_ALL=y -CONFIG_ARCH_INTERRUPTSTACK=4096 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_STACK_RECORD=32 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig deleted file mode 100644 index a7293527dc2c6..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig +++ /dev/null @@ -1,67 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DRIVERS_NOTERAM is not set -# CONFIG_SERIAL_RTT_CONSOLE is not set -# CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_NOTE=y -CONFIG_DRIVERS_NOTE_TASKNAME_BUFSIZE=0 -CONFIG_EXAMPLES_NOTEPRINTF=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_DUMP=y -CONFIG_SCHED_INSTRUMENTATION_HEAP=y -CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y -CONFIG_SCHED_INSTRUMENTATION_SWITCH=y -CONFIG_SCHED_INSTRUMENTATION_WDOG=y -CONFIG_SEGGER_SYSVIEW=y -CONFIG_SERIAL_RTT0=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_RTT=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_SYSTEM=y -CONFIG_TASK_NAME_SIZE=16 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig deleted file mode 100644 index 0e37eddf1ab99..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_STM32_FLASH_PREFETCH is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig deleted file mode 100644 index 1c20aa029a01a..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f429i-disco" -CONFIG_ARCH_BOARD_STM32F429I_DISCO=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F429Z=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEV_LOOP=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP2_BASE=0xD0000000 -CONFIG_HEAP2_SIZE=8388608 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=3 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32_EXTERNAL_RAM=y -CONFIG_STM32_FMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGHS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_TESTING_RAMTEST=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f429i-disco/include/board.h b/boards/arm/stm32/stm32f429i-disco/include/board.h deleted file mode 100644 index 2bb3b57f0cf6e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/include/board.h +++ /dev/null @@ -1,540 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* DO NOT include STM32 internal header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F429I-DISCO board features a single 8MHz crystal. - * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 180000000 Determined by PLL - * configuration - * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_NLEDS 2 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f429i-disco. - * The following definitions describe how NuttX controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F429I-DISCO supports one button: */ - -#define BUTTON_USER 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* USART1: - * - * The STM32F429I-DISCO has no on-board serial devices, but the console is - * brought out to PA9 (TX) and PA10 (RX) for connection to an external serial - * device. - */ - -#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) - -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) - -/* CAN: */ - -#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) -#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) - -/* PWM - * - * The STM32F429I-DISCO has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ -#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ -#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ -#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ -#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ -#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ - -/* I2C - There is a STMPE811 TouchPanel on I2C3 using these pins: */ - -#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) - -/* SPI - There is a MEMS device on SPI5 using these pins: */ - -#define GPIO_SPI5_MISO (GPIO_SPI5_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI5_MOSI (GPIO_SPI5_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI5_SCK (GPIO_SPI5_SCK_1|GPIO_SPEED_50MHz) - -/* SPI - External SPI flash may be connected on SPI4: */ - -#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz) - -/* FMC - SDRAM */ - -#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz) - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -#ifdef CONFIG_STM32_LTDC -# ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - -/* LCD - * - * The STM32F429I-DISCO board contains an onboard TFT LCD connected to the - * LTDC interface of the uC. - * The LCD is 240x320 pixels. - * Define the parameters of the LCD and the interface here. - */ - -/* Panel configuration - * - * LCD Panel is Saef Technology Limited (SF-TC240T-9229A2-T) with integrated - * Ilitek ILI9341 LCD Single Chip Driver (240RGBx320) - * - * PLLSAI settings - * PLLSAIN : 192 - * PLLSAIR : 4 - * PLLSAIQ : 7 - * PLLSAIDIVR : 8 - * - * Timings - * Horizontal Front Porch : 10 (STM32_LTDC_HFP) - * Horizontal Back Porch : 20 (STM32_LTDC_HBP) - * Vertical Front Porch : 4 (STM32_LTDC_VFP) - * Vertical Back Porch : 2 (STM32_LTDC_VBP) - * - * Horizontal Sync : 10 (STM32_LTDC_HSYNC) - * Vertical Sync : 4 (STM32_LTDC_VSYNC) - * - * Active Width : 240 (STM32_LTDC_ACTIVEW) - * Active Height : 320 (STM32_LTDC_ACTIVEH) - */ - -/* LTDC PLL configuration - * - * PLLSAI_VCO = STM32_HSE_FREQUENCY / PLLM - * = 8000000ul / 8 - * = 1,000,000 - * - * PLL LCD clock output - * = PLLSAI_VCO * PLLSAIN / PLLSAIR / PLLSAIDIVR - * = 1,000,000 * 192 / 4 /8 - * = 6,000,000 - */ - -/* Defined panel settings */ - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ - defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define BOARD_LTDC_WIDTH 320 -# define BOARD_LTDC_HEIGHT 240 -#else -# define BOARD_LTDC_WIDTH 240 -# define BOARD_LTDC_HEIGHT 320 -#endif - -#define BOARD_LTDC_OUTPUT_BPP 16 -#define BOARD_LTDC_HFP 10 -#define BOARD_LTDC_HBP 20 -#define BOARD_LTDC_VFP 4 -#define BOARD_LTDC_VBP 2 -#define BOARD_LTDC_HSYNC 10 -#define BOARD_LTDC_VSYNC 2 - -#define BOARD_LTDC_PLLSAIN 192 -#define BOARD_LTDC_PLLSAIR 4 -#define BOARD_LTDC_PLLSAIQ 7 - -/* Division factor for LCD clock */ - -#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 - -/* Pixel Clock Polarity */ - -#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ - -/* Data Enable Polarity */ - -#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ - -/* Vertical Sync Polarity */ - -#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ - -/* Horizontal Sync Polarity */ - -#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ - -/* GPIO pinset */ - -#define GPIO_LTDC_PINS 18 /* 18-bit display */ - -#define GPIO_LTDC_R2 (GPIO_LTDC_R2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R3 (GPIO_LTDC_R3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R4 (GPIO_LTDC_R4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R5 (GPIO_LTDC_R5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R6 (GPIO_LTDC_R6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_R7 (GPIO_LTDC_R7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_G2 (GPIO_LTDC_G2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G3 (GPIO_LTDC_G3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G4 (GPIO_LTDC_G4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G5 (GPIO_LTDC_G5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G6 (GPIO_LTDC_G6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_G7 (GPIO_LTDC_G7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_B2 (GPIO_LTDC_B2_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B3 (GPIO_LTDC_B3_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B4 (GPIO_LTDC_B4_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B5 (GPIO_LTDC_B5_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B6 (GPIO_LTDC_B6_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_B7 (GPIO_LTDC_B7_1|GPIO_SPEED_100MHz) - -#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_1 -#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_1 -#define GPIO_LTDC_DE (GPIO_LTDC_DE_1|GPIO_SPEED_100MHz) -#define GPIO_LTDC_CLK GPIO_LTDC_CLK_1 - -#else -/* Custom LCD display configuration */ - -# define BOARD_LTDC_WIDTH ??? -# define BOARD_LTDC_HEIGHT ??? - -#define BOARD_LTDC_HFP ??? -#define BOARD_LTDC_HBP ??? -#define BOARD_LTDC_VFP ??? -#define BOARD_LTDC_VBP ??? -#define BOARD_LTDC_HSYNC ??? -#define BOARD_LTDC_VSYNC ??? - -#define BOARD_LTDC_PLLSAIN ??? -#define BOARD_LTDC_PLLSAIR ??? -#define BOARD_LTDC_PLLSAIQ ??? - -/* Division factor for LCD clock */ - -#define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? - -/* Pixel Clock Polarity */ - -#define BOARD_LTDC_GCR_PCPOL ??? - -/* Data Enable Polarity */ - -#define BOARD_LTDC_GCR_DEPOL ??? - -/* Vertical Sync Polarity */ - -#define BOARD_LTDC_GCR_VSPOL ??? - -/* Horizontal Sync Polarity */ - -#define BOARD_LTDC_GCR_HSPOL ??? - -/* GPIO pinset */ - -#define GPIO_LTDC_PINS ??? - -#define GPIO_LTDC_R2 ??? -#define GPIO_LTDC_R3 ??? -#define GPIO_LTDC_R4 ??? -#define GPIO_LTDC_R5 ??? -#define GPIO_LTDC_R6 ??? -#define GPIO_LTDC_R7 ??? - -#define GPIO_LTDC_G2 ??? -#define GPIO_LTDC_G3 ??? -#define GPIO_LTDC_G4 ??? -#define GPIO_LTDC_G5 ??? -#define GPIO_LTDC_G6 ??? -#define GPIO_LTDC_G7 ??? - -#define GPIO_LTDC_B2 ??? -#define GPIO_LTDC_B3 ??? -#define GPIO_LTDC_B4 ??? -#define GPIO_LTDC_B5 ??? -#define GPIO_LTDC_B6 ??? -#define GPIO_LTDC_B7 ??? - -#define GPIO_LTDC_VSYNC ??? -#define GPIO_LTDC_HSYNC ??? -#define GPIO_LTDC_DE ??? -#define GPIO_LTDC_CLK ??? - -#endif /* Custom LCD display */ - -/* Configure PLLSAI */ - -#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) -#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) -#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) - -#endif /* CONFIG_STM32_LTDC */ - -/* L3GD20 MEMS */ - -#define GPIO_L3GD20_DREADY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) -#define L3GD20_IRQ (2 + STM32_IRQ_EXTI0) - -#define BOARD_L3GD20_GPIO_DREADY GPIO_L3GD20_DREADY -#define BOARD_L3GD20_IRQ L3GD20_IRQ - -#define GPIO_LIS3DSH_EXT0 \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 - -/* DMA **********************************************************************/ - -#define ADC1_DMA_CHAN DMAMAP_ADC1_1 - -/* USB OTG FS / OTG HS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 -#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* FMC SDRAM pins (referenced by board src) */ - -#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz) -#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz) - -/* USB OTGHSFS (HS in FS mode) */ - -#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs deleted file mode 100644 index a88280f56b3af..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f429i-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_SYSTEM_OFLOADER),y) -LDSCRIPT = ofloader.ld -else -LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld deleted file mode 100644 index db9d9db676a05..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script b/boards/arm/stm32/stm32f429i-disco/scripts/ld.script deleted file mode 100644 index f6fde30fd1e85..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script +++ /dev/null @@ -1,133 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of SRAM beginning at address 0x2002:0000 - * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld b/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld deleted file mode 100644 index 95ece2dbfe8a4..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and - * 256Kb of SRAM. SRAM is split up into four blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of SRAM beginning at address 0x2002:0000 - * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x20000 0000: Kernel .data region. Typical size: 0.1KB - * ------- ---- Kernel .bss region. Typical size: 1.8KB - * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------- ---- Padded to 4KB - * 0x20000 1000: User .data region. Size is variable. - * ------- ---- User .bss region Size is variable. - * 0x20000 2000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE. - * ------- ---- Beginning of user heap. Can vary with other settings. - * 0x20001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K - usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K - xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K -} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld deleted file mode 100644 index 3ee80c42f4651..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - *(.userspace) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt deleted file mode 100644 index fa9314f019bff..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_extmem.c) -endif() - -if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_INPUT_STMPE811) - list(APPEND SRCS stm32_stmpe811.c) -endif() - -if(CONFIG_STM32F429I_DISCO_ILI9341) - list(APPEND SRCS stm32_ili93414ws.c) -endif() - -if(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE - AND CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - AND CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32F429I_DISCO_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32/stm32f429i-disco/src/Make.defs b/boards/arm/stm32/stm32f429i-disco/src/Make.defs deleted file mode 100644 index 5b7dd1fcbd2fd..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/Make.defs +++ /dev/null @@ -1,82 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f429i-disco/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CSRCS += stm32_extmem.c -endif - -ifeq ($(CONFIG_STM32_OTGHS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_INPUT_STMPE811),y) -CSRCS += stm32_stmpe811.c -endif - -ifeq ($(CONFIG_STM32F429I_DISCO_ILI9341),y) -CSRCS += stm32_ili93414ws.c -endif - -ifeq ($(and \ - $(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE), \ - $(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE), \ - $(CONFIG_STM32_LTDC)),) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_ADC),y) -CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32F429I_DISCO_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c deleted file mode 100644 index 45b62589d27a9..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c +++ /dev/null @@ -1,237 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32.h" - -#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* 1 or 2 ADC devices (DEV1, DEV2). - * ADC1 and ADC3 supported for now. - */ - -#if defined(CONFIG_STM32_ADC1) -# define DEV1_PORT 1 -#endif - -#if defined(CONFIG_STM32_ADC3) -# if defined(DEV1_PORT) -# define DEV2_PORT 3 -# else -# define DEV1_PORT 3 -# endif -#endif - -/* The number of ADC channels in the conversion list */ - -/* TODO DMA */ - -#define ADC1_NCHANNELS 2 -#define ADC3_NCHANNELS 1 - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* DEV 1 */ - -#if DEV1_PORT == 1 - -#define DEV1_NCHANNELS ADC1_NCHANNELS - -/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ - -static const uint8_t g_chanlist1[2] = -{ - 5, - 13, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[2] = -{ - GPIO_ADC1_IN5_0, /* PA5 */ - GPIO_ADC1_IN13_0, /* PC3 */ -}; - -#elif DEV1_PORT == 3 - -#define DEV1_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist1[1] = -{ - 4, -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist1[1] = -{ - GPIO_ADC3_IN4_0, /* PF6 */ -}; - -#endif /* DEV1_PORT == 1 */ - -#ifdef DEV2_PORT - -/* DEV 2 */ - -#if DEV2_PORT == 3 - -#define DEV2_NCHANNELS ADC3_NCHANNELS - -/* Identifying number of each ADC channel */ - -static const uint8_t g_chanlist2[3] = -{ - 8, - 9, - 10 -}; - -/* Configurations of pins used by each ADC channel */ - -static const uint32_t g_pinlist2[3] = -{ - GPIO_ADC3_IN8_0, /* PD11/A3 */ - GPIO_ADC3_IN9_0, /* PD12/A4 */ - GPIO_ADC3_IN10_0, /* PD13/A5 */ -}; - -#endif /* DEV2_PORT == 3 */ -#endif /* DEV2_PORT */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_adc_setup - * - * Description: - * Initialize ADC and register the ADC driver. - * - ****************************************************************************/ - -int stm32_adc_setup(void) -{ - static bool initialized = false; - struct adc_dev_s *adc; - int ret; - int i; - - /* Check if we have already initialized */ - - if (!initialized) - { - /* DEV1 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc0" */ - - ret = adc_register("/dev/adc0", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); - return ret; - } - -#ifdef DEV2_PORT - /* DEV2 */ - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV2_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist2[i]); - } - - /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - - adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); - if (adc == NULL) - { - aerr("ERROR: Failed to get ADC interface 2\n"); - return -ENODEV; - } - - /* Register the ADC driver at "/dev/adc1" */ - - ret = adc_register("/dev/adc1", adc); - if (ret < 0) - { - aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); - return ret; - } -#endif - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c deleted file mode 100644 index cdc48319a0246..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM32F4_LED1 (1 << 0) -#define STM32F4_LED2 (1 << 1) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c deleted file mode 100644 index deabbc588b52a..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32f429i-disco.h" -#include "stm32_ccm.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ - defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ - defined(CONFIG_STM32_SPI5) - - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the 1) OTG HS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif - -#ifdef CONFIG_STM32_FMC - stm32_sdram_initialize(); -#endif - -#ifdef HAVE_CCM_HEAP - /* Initialize CCM allocator */ - - ccm_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c deleted file mode 100644 index a00da867c599b..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c +++ /dev/null @@ -1,429 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_STM32_SPI4 -# include -#endif - -#if defined(CONFIG_MTD_SST25XX) || defined(CONFIG_MTD_PROGMEM) -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR -#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 -#endif - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART -#ifdef CONFIG_PLATFORM_CONFIGDATA -# include -#endif -#endif - -#ifdef CONFIG_STM32_OTGHS -# include "stm32_usbhost.h" -#endif - -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_INPUT_BUTTONS_LOWER -# include -#endif - -#ifdef CONFIG_SENSORS_L3GD20 -#include "stm32_l3gd20.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#if defined(CONFIG_STM32_SPI4) - struct spi_dev_s *spi; -#endif -#if defined(CONFIG_MTD) - struct mtd_dev_s *mtd; -#if defined (CONFIG_MTD_SST25XX) - struct mtd_geometry_s geo; -#endif -#endif -#if defined(CONFIG_MTD_PARTITION_NAMES) - const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; -#endif - int ret; - -#ifdef HAVE_PROC - /* mount the proc filesystem */ - - ret = nx_mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to mount the PROC filesystem: %d\n", ret); - return ret; - } -#endif - - /* Configure SPI-based devices */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PROGMEM) - mtd = progmem_initialize(); - if (mtd == NULL) - { - syslog(LOG_ERR, "ERROR: progmem_initialize\n"); - } - - ret = register_mtddriver("/dev/flash", mtd, 0, mtd); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: register_mtddriver() failed: %d\n", ret); - } - -#endif - -#ifdef CONFIG_STM32_SPI4 - /* Get the SPI port */ - - syslog(LOG_INFO, "Initializing SPI port 4\n"); - - spi = stm32_spibus_initialize(4); - if (!spi) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); - return -ENODEV; - } - - syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); - - /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This - * is a FLASH device that has been added external to the board (i.e. - * the board does not ship from STM with any on-board FLASH. - */ - -#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) - syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); - - mtd = sst25xx_initialize(spi); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH" - " driver\n"); - } - else - { - syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH" - " driver\n"); - - /* Get the geometry of the FLASH device */ - - ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, - (unsigned long)((uintptr_t)&geo)); - if (ret < 0) - { - ferr("ERROR: mtd->ioctl failed: %d\n", ret); - return ret; - } - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART - { - int partno; - int partsize; - int partoffset; - int partszbytes; - int erasesize; - const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; - const char *ptr; - struct mtd_dev_s *mtd_part; - char partref[16]; - - /* Now create a partition on the FLASH device */ - - partno = 0; - ptr = partstring; - partoffset = 0; - - /* Get the Flash erase size */ - - erasesize = geo.erasesize; - - while (*ptr != '\0') - { - /* Get the partition size */ - - partsize = atoi(ptr); - partszbytes = (partsize << 10); /* partsize is defined in KB */ - - /* Check if partition size is bigger then erase block */ - - if (partszbytes < erasesize) - { - ferr("ERROR: Partition size is lesser than erasesize!\n"); - return -1; - } - - /* Check if partition size is multiple of erase block */ - - if ((partszbytes % erasesize) != 0) - { - ferr("ERROR: Partition size is not multiple of" - " erasesize!\n"); - return -1; - } - - mtd_part = mtd_partition(mtd, partoffset, - partszbytes / erasesize); - partoffset += partszbytes / erasesize; - -#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART - /* Test if this is the config partition */ - - if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) - { - /* Register the partition as the config device */ - - mtdconfig_register(mtd_part); - } - else -#endif - { - /* Now initialize a SMART Flash block device and bind it - * to the MTD device. - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - snprintf(partref, sizeof(partref), "p%d", partno); - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, - mtd_part, partref); -#endif - } - -#if defined(CONFIG_MTD_PARTITION_NAMES) - /* Set the partition name */ - - if (mtd_part == NULL) - { - ferr("ERROR: failed to create partition %s\n", partname); - return -1; - } - - mtd_setpartitionname(mtd_part, partname); - - /* Now skip to next name. We don't need to split the string - * here because the MTD partition logic will only display names - * up to the comma, thus allowing us to use a single static - * name in the code. - */ - - while (*partname != ',' && *partname != '\0') - { - /* Skip to next ',' */ - - partname++; - } - - if (*partname == ',') - { - partname++; - } -#endif - - /* Update the pointer to point to the next size in the list */ - - while ((*ptr >= '0') && (*ptr <= '9')) - { - ptr++; - } - - if (*ptr == ',') - { - ptr++; - } - - /* Increment the part number */ - - partno++; - } - } -#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - - /* Configure the device with no partition support */ - - smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); - -#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ - } - -#endif /* CONFIG_MTD */ -#endif /* CONFIG_STM32_SPI4 */ - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) - /* Create a RAM MTD device if configured */ - - { - uint8_t *start = - kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd = rammtd_initialize(start, - CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); - mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); - - /* Now initialize a SMART Flash block device and bind it to the MTD - * device - */ - -#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) - smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); -#endif - } - -#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ - -#ifdef CONFIG_INPUT_STMPE811 - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_L3GD20 - ret = board_l3gd20_initialize(0, 5); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor:" - " %d\n", ret); - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC - /* Initialize ADC and register the ADC device. */ - - ret = stm32_adc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c deleted file mode 100644 index 314d14da7c97d..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c +++ /dev/null @@ -1,150 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32f429i-disco.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c deleted file mode 100644 index 68464531cc54e..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c deleted file mode 100644 index c74f2bb1ce9de..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c +++ /dev/null @@ -1,178 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FMC -#warning "FMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -#error "Required GPIO ports not enabled" -#endif - -#define STM32_SDRAM_CLKEN FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2 - -#define STM32_SDRAM_PALL FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2 - -#define STM32_SDRAM_REFRESH FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\ - FMC_SDCMR_NRFS(4) - -#define STM32_SDRAM_MODEREG FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\ - FMC_SDCMR_MDR_BURST_LENGTH_2 | \ - FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\ - FMC_SDCMR_MDR_CAS_LATENCY_3 |\ - FMC_SDCMR_MDR_WBL_SINGLE - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_sdram_config[] = -{ - /* 16 data lines */ - - GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, - GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, - GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, - GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, - - /* 12 address lines */ - - GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, - GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, - GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, - - /* control lines */ - - GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0, - GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, - GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS, -}; - -#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdram_initialize - * - * Description: - * Called from stm32_bringup to initialize external SDRAM access. - * - ****************************************************************************/ - -void stm32_sdram_initialize(void) -{ - uint32_t val; - int i; - volatile int count; - - /* Enable GPIOs as FMC / memory pins */ - - for (i = 0; i < NUM_SDRAM_GPIOS; i++) - { - stm32_configgpio(g_sdram_config[i]); - } - - /* Enable AHB clocking to the FMC */ - - stm32_fmc_enable(); - - /* Configure and enable the SDRAM bank1 - * - * FMC clock = 180MHz/2 = 90MHz - * 90MHz = 11,11 ns - * All timings from the datasheet for Speedgrade -7 (=7ns) - */ - - val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ - FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ - FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */ - FMC_SDCR_NBANKS_4 | /* 4 internal banks */ - FMC_SDCR_WIDTH_16 | /* width = 16 bits */ - FMC_SDCR_ROWS_12 | /* numrows = 12 */ - FMC_SDCR_COLS_8; /* numcols = 8 bits */ - stm32_fmc_sdram_set_control(1, val); - stm32_fmc_sdram_set_control(2, val); - - val = FMC_SDTR_TRCD(3) | /* tRCD min = 15ns */ - FMC_SDTR_TRP(3) | /* tRP min = 15ns */ - FMC_SDTR_TWR(3) | /* tWR = 2CLK */ - FMC_SDTR_TRC(8) | /* tRC min = 63ns */ - FMC_SDTR_TRAS(5) | /* tRAS min = 42ns */ - FMC_SDTR_TXSR(8) | /* tXSR min = 70ns */ - FMC_SDTR_TMRD(3); /* tMRD = 2CLK */ - stm32_fmc_sdram_set_timing(2, val); - - /* SDRAM Initialization sequence */ - - stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */ - for (count = 0; count < 10000; count++); /* Delay */ - stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */ - stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */ - stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */ - - /* Set refresh count - * - * FMC_CLK = 90MHz - * Refresh_Rate = 7.81us - * Counter = (FMC_CLK * Refresh_Rate) - 20 - */ - - stm32_fmc_sdram_set_refresh_rate(683); - - /* Disable write protection */ - - /* stm32_fmc_sdram_write_protect(2, false); */ -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c deleted file mode 100644 index 1a40a0bb80329..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c +++ /dev/null @@ -1,535 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" - -#include "stm32_pwm.h" -#include "stm32_adc.h" -#include "stm32_dma.h" - -#include -#ifdef CONFIG_STM32F429I_DISCO_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -#ifndef CONFIG_ARCH_FPU -# warning Set CONFIG_ARCH_FPU for hardware FPU support -#endif - -#ifdef CONFIG_STM32_ADC1_DMA -# if defined(CONFIG_STM32_TIM1_PWM) -# define HIGHPRI_HAVE_TIM1 -# endif -# if (CONFIG_STM32_ADC1_DMA_CFG != 1) -# error ADC1 DMA must be configured in Circular Mode -# endif -# if !defined(HIGHPRI_HAVE_TIM1) -# error "Needs TIM1 to trigger ADC DMA" -# endif -#endif - -#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) -# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 1) -# error Max 1 injected channels supported for now -# else -# define HIGHPRI_HAVE_INJECTED -# endif -#endif - -#ifdef HIGHPRI_HAVE_INJECTED -# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN -#else -# define INJ_NCHANNELS (0) -#endif - -#ifndef CONFIG_STM32_ADC1_DMA -# define REG_NCHANNELS (1) -#else -# define REG_NCHANNELS (1) -#endif - -#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) - -#define DEV1_PORT (1) -#define DEV1_NCHANNELS ADC1_NCHANNELS -#define ADC_REF_VOLTAGE (3.3f) -#define ADC_VAL_MAX (4095) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* High priority example private data */ - -struct highpri_s -{ - struct stm32_adc_dev_s *adc1; -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm; -#endif - volatile uint32_t cntr1; - volatile uint32_t cntr2; - volatile uint8_t current; - uint16_t r_val[REG_NCHANNELS]; - float r_volt[REG_NCHANNELS]; -#ifdef HIGHPRI_HAVE_INJECTED - uint16_t j_val[INJ_NCHANNELS]; - float j_volt[INJ_NCHANNELS]; -#endif - bool lock; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ADC channel list */ - -static const uint8_t g_chanlist1[DEV1_NCHANNELS] = -{ - 5, -#if INJ_NCHANNELS > 0 - 13, -#endif -}; - -/* Configurations of pins used by ADC channel */ - -static const uint32_t g_pinlist1[DEV1_NCHANNELS] = -{ - GPIO_ADC1_IN5_0, /* PA5 */ -#if INJ_NCHANNELS > 0 - GPIO_ADC1_IN13_0, /* PC3 */ -#endif -}; - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: adc12_handler - * - * Description: - * This is the handler for the high speed ADC interrupt. - * - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) -void adc_handler(void) -{ - struct stm32_adc_dev_s *adc = g_highpri.adc1; - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint32_t pending; -#ifdef HIGHPRI_HAVE_INJECTED - int i = 0; -#endif - - /* Get pending ADC1 interrupts */ - - pending = STM32_ADC_INT_GET(adc); - - if (g_highpri.lock == true) - { - goto irq_out; - } - -#ifndef CONFIG_STM32_ADC1_DMA - /* Regular channel end of conversion */ - - if (pending & ADC_ISR_EOC) - { - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - /* Get regular data */ - - g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); - - /* Do some floating point operations */ - - g_highpri.r_volt[g_highpri.current] = - (float)g_highpri.r_val[g_highpri.current] * ref / bit; - - if (g_highpri.current >= REG_NCHANNELS - 1) - { - g_highpri.current = 0; - } - else - { - g_highpri.current += 1; - } - } -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Injected channel end of sequence */ - - if (pending & ADC_ISR_JEOC) - { - /* Increase injected sequence counter */ - - g_highpri.cntr2 += 1; - - /* Get injected channels */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); - } - - /* Do some floating point operations */ - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; - } - } -#endif - -irq_out: - - /* Clear ADC pending interrupts */ - - STM32_ADC_INT_ACK(adc, pending); -} -#endif - -/**************************************************************************** - * Name: dma2s0_handler - * - * Description: - * This is the handler for the high speed ADC interrupt using DMA transfer. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_ADC1_DMA -void dma2s0_handler(void) -{ - float ref = ADC_REF_VOLTAGE; - float bit = ADC_VAL_MAX; - uint8_t pending; - int i; - - pending = stm32_dma_intget(DMA2, DMA_STREAM0); - - if (g_highpri.lock == true) - { - goto irq_out; - } - - /* Increase regular sequence counter */ - - g_highpri.cntr1 += 1; - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - /* Do some floating point operations */ - - g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; - } - -irq_out: - - /* Clear DMA pending interrupts */ - - stm32_dma_intack(DMA2, DMA_STREAM0, pending); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ -#ifdef HIGHPRI_HAVE_TIM1 - struct stm32_pwm_dev_s *pwm1; -#endif - struct adc_dev_s *adc1; - struct highpri_s *highpri; - int ret; - int i; - - highpri = &g_highpri; - - /* Initialize highpri structure */ - - memset(highpri, 0, sizeof(struct highpri_s)); - - printf("\nhighpri_main: Started\n"); - - /* Configure the pins as analog inputs for the selected channels */ - - for (i = 0; i < DEV1_NCHANNELS; i++) - { - stm32_configgpio(g_pinlist1[i]); - } - - /* Initialize ADC driver */ - - adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); - if (adc1 == NULL) - { - aerr("ERROR: Failed to get ADC interface 1\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; - -#ifdef HIGHPRI_HAVE_TIM1 - /* Initialize TIM1 */ - - pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); - if (pwm1 == NULL) - { - printf("ERROR: Failed to get PWM1 interface\n"); - ret = EXIT_FAILURE; - goto errout; - } - - highpri->pwm = pwm1; - - /* Setup PWM device */ - - PWM_SETUP(pwm1); - - /* Set timer frequency */ - - PWM_FREQ_UPDATE(pwm1, 1000); - - /* Set CCR1 */ - - PWM_CCR_UPDATE(pwm1, 1, 0x0f00); - - /* Enable TIM1 OUT1 */ - - PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); - -#ifdef CONFIG_DEBUG_PWM_INFO - /* Print debug */ - - PWM_DUMP_REGS(pwm1); -#endif - -#endif /* HIGHPRI_HAVE_TIM1 */ - -#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) - /* Attach ADC ram vector if no DMA or injected channels support */ - - ret = arm_ramvec_attach(STM32_IRQ_ADC, adc_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the ADC interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_ADC, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_ADC); -#endif - -#ifdef CONFIG_STM32_ADC1_DMA - /* Attach DMA2 STREAM0 ram vector if DMA */ - - ret = arm_ramvec_attach(STM32_IRQ_DMA2S0, dma2s0_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - /* Set the priority of the DMA2 STREAM0 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_DMA2S0, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - ret = EXIT_FAILURE; - goto errout; - } - - up_enable_irq(STM32_IRQ_DMA2S0); -#endif - - /* Setup ADC hardware */ - - adc1->ad_ops->ao_setup(adc1); - - /* Configure regular channels trigger to T1CC1 */ - - STM32_ADC_EXTCFG_SET(highpri->adc1, - ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); - -#ifndef CONFIG_STM32_ADC1_DMA - /* Enable ADC regular conversion interrupts if no DMA */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); -#else - /* Note: ADC and DMA must be reset after overrun occurs. - * For this example we assume that overrun will not occur. - * This is true only if DMA and ADC trigger are properly configured. - * DMA configuration must be done before ADC trigger starts! - */ - - /* Register ADC buffer for DMA transfer */ - - STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Enable ADC injected channels end of conversion interrupts */ - - STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC); -#endif - -#ifdef HIGHPRI_HAVE_TIM1 - /* Enable timer counter after ADC and DMA configuration */ - - PWM_TIM_ENABLE(pwm1, true); -#endif - - while (1) - { -#ifndef CONFIG_STM32_ADC1_DMA - /* Software trigger for regular sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); - - nxsched_usleep(100); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Software trigger for injected sequence */ - - adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); - - nxsched_usleep(100); -#endif - /* Lock global data */ - - g_highpri.lock = true; - -#ifndef CONFIG_STM32_ADC1_DMA - printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, - g_highpri.r_volt[g_highpri.current]); -#else - printf("%" PRId32 " ", g_highpri.cntr1); - - for (i = 0; i < REG_NCHANNELS; i += 1) - { - printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); - } - - printf("\n"); -#endif - -#ifdef HIGHPRI_HAVE_INJECTED - /* Print data from injected channels */ - - printf("%" PRId32 " ", g_highpri.cntr2); - - for (i = 0; i < INJ_NCHANNELS; i += 1) - { - printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); - } - - printf("\n"); -#endif - /* Unlock global data */ - - g_highpri.lock = false; - - nxsched_sleep(1); - } - -errout: - return ret; -} - -#endif /* CONFIG_STM32F429I_DISCO_HIGHPRI */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c deleted file mode 100644 index 2daac96d2b727..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ -#ifdef CONFIG_RTC_ALARM - struct timespec alarmtime; -#endif - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: stm32_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) -static void stm32_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c deleted file mode 100644 index 07dd27571ebc6..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c +++ /dev/null @@ -1,576 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32f429i-disco.h" -#include "stm32_ltdc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE -# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE -#else -# define ILI9341_LCD_DEVICE 0 -#endif - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - -/* Display settings */ - -/* Pixel Format Set (COLMOD) - * - * Note! RGB interface settings (DPI) is unimportant for the MCU interface - * mode but set the register to the defined state equal to the MCU interface - * pixel format. - * - * 16 Bit MCU: 01100101 / h65 - * - * DPI: 6 (RGB18-666 RGB interface) - * DBI: 5 (RGB16-565 MCU interface, not used set to default) - */ - -#define STM32_ILI9341_PIXSET_PARAM (ILI9341_PIXEL_FORMAT_SET_DPI(6) | \ - ILI9341_PIXEL_FORMAT_SET_DBI(5)) - -/* DE Mode RCM = 2, Sync Mode RCM = 3 - * Interface Mode Control - * - * EPL: 0 High enable for RGB interface - * DPL: 1 data fetched at the falling time - * HSPL: 0 Low level sync clock - * VSPL: 0 Low level sync clock - * RCM: 2 (DE Mode) - * ByPass_Mode: 1 (Memory) - */ - -#define STM32_ILI9341_IFMODE_PARAM (ILI9341_INTERFACE_CONTROL_DPL | \ - ILI9341_INTERFACE_CONTROL_RCM(2) | \ - ILI9341_INTERFACE_CONTROL_BPASS) - -/* Interface control (IFCTL) - * - * Parameter 1: 0x0001 - * MY_EOR: 0 - * MX_EOR: 0 - * MV_EOR: 0 - * BGR_EOR: 0 - * WEMODE: 1 Reset column and page if data transfer exceeds - */ - -#define STM32_ILI9341_IFCTL_PARAM1 (ILI9341_INTERFACE_CONTROL_WEMODE) - -/* Parameter 2: 0x0000 - * - * EPF: 0 65k color format for RGB interface - * MDT: 0 Display data transfer mode - * - */ -#define STM32_ILI9341_IFCTL_PARAM2 (ILI9341_INTERFACE_CONTROL_MDT(0) | \ - ILI9341_INTERFACE_CONTROL_EPF(0)) - -/* Parameter 3: 0x0000/0x0020 - * - * ENDIAN: 0 Big endian - * DM: 1 RGB Interface Mode - * RM: 1 RGB interface - * RIM: 0 18-bit 1 transfer/pixel RGB interface mode - * - */ -#define STM32_ILI9341_IFCTL_PARAM3 (ILI9341_INTERFACE_CONTROL_RM | \ - ILI9341_INTERFACE_CONTROL_DM(1)) - -/* Memory access control (MADCTL) */ - -/* Landscape: 00100000 / 00101000 / h28 - * - * MY: 0 - * MX: 0 - * MV: 1 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_LANDSCAPE_MY 0 -#define ILI9341_MADCTL_LANDSCAPE_MX 0 -#define ILI9341_MADCTL_LANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV -#define ILI9341_MADCTL_LANDSCAPE_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_LANDSCAPE_BGR 0 -#else -# define ILI9341_MADCTL_LANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_LANDSCAPE_MH 0 - -#define ILI9341_MADCTL_LANDSCAPE_PARAM1 (ILI9341_MADCTL_LANDSCAPE_MY | \ - ILI9341_MADCTL_LANDSCAPE_MX | \ - ILI9341_MADCTL_LANDSCAPE_MV | \ - ILI9341_MADCTL_LANDSCAPE_ML | \ - ILI9341_MADCTL_LANDSCAPE_BGR | \ - ILI9341_MADCTL_LANDSCAPE_MH) - -/* Portrait: 00000000 / 00001000 / h08 - * - * MY: 0 - * MX: 0 - * MV: 0 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_PORTRAIT_MY 0 -#define ILI9341_MADCTL_PORTRAIT_MX ILI9341_MEMORY_ACCESS_CONTROL_MX -#define ILI9341_MADCTL_PORTRAIT_MV 0 -#define ILI9341_MADCTL_PORTRAIT_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_PORTRAIT_BGR 0 -#else -# define ILI9341_MADCTL_PORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_PORTRAIT_MH 0 - -#define ILI9341_MADCTL_PORTRAIT_PARAM1 (ILI9341_MADCTL_PORTRAIT_MY | \ - ILI9341_MADCTL_PORTRAIT_MX | \ - ILI9341_MADCTL_PORTRAIT_MV | \ - ILI9341_MADCTL_PORTRAIT_ML | \ - ILI9341_MADCTL_PORTRAIT_BGR | \ - ILI9341_MADCTL_PORTRAIT_MH) - -/* RLandscape: 01100000 / 01101000 / h68 - * - * MY: 0 - * MX: 1 - * MV: 1 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - */ - -#define ILI9341_MADCTL_RLANDSCAPE_MY 0 -#define ILI9341_MADCTL_RLANDSCAPE_MX ILI9341_MEMORY_ACCESS_CONTROL_MX -#define ILI9341_MADCTL_RLANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV -#define ILI9341_MADCTL_RLANDSCAPE_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_RLANDSCAPE_BGR 0 -#else -# define ILI9341_MADCTL_RLANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_RLANDSCAPE_MH 0 - -#define ILI9341_MADCTL_RLANDSCAPE_PARAM1 \ - (ILI9341_MADCTL_RLANDSCAPE_MY | \ - ILI9341_MADCTL_RLANDSCAPE_MX | \ - ILI9341_MADCTL_RLANDSCAPE_MV | \ - ILI9341_MADCTL_RLANDSCAPE_ML | \ - ILI9341_MADCTL_RLANDSCAPE_BGR | \ - ILI9341_MADCTL_RLANDSCAPE_MH) - -/* RPortrait: 11000000 / 11001000 / hc8 - * - * MY: 1 - * MX: 1 - * MV: 0 - * ML: 0 - * BGR: 0/1 Depending on endian mode of the mcu? - * MH: 0 - * - */ - -#define ILI9341_MADCTL_RPORTRAIT_MY ILI9341_MEMORY_ACCESS_CONTROL_MY -#define ILI9341_MADCTL_RPORTRAIT_MX 0 -#define ILI9341_MADCTL_RPORTRAIT_MV 0 -#define ILI9341_MADCTL_RPORTRAIT_ML 0 -#ifdef CONFIG_ENDIAN_BIG -# define ILI9341_MADCTL_RPORTRAIT_BGR 0 -#else -# define ILI9341_MADCTL_RPORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR -#endif -#define ILI9341_MADCTL_RPORTRAIT_MH 0 - -#define ILI9341_MADCTL_RPORTRAIT_PARAM1 (ILI9341_MADCTL_RPORTRAIT_MY | \ - ILI9341_MADCTL_RPORTRAIT_MX | \ - ILI9341_MADCTL_RPORTRAIT_MV | \ - ILI9341_MADCTL_RPORTRAIT_ML | \ - ILI9341_MADCTL_RPORTRAIT_BGR | \ - ILI9341_MADCTL_RPORTRAIT_MH) - -/* Set the display orientation */ - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 -# warning "ILI9341 doesn't support full landscape with RGB interface" -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_PORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 -# warning "ILI9341 doesn't support full landscape with RGB interface" -#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RPORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 -#else -# error "display orientation not defined" -#endif - -#define ILI9341_XRES BOARD_LTDC_WIDTH -#define ILI9341_YRES BOARD_LTDC_HEIGHT -#endif /* CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE -struct lcd_dev_s *g_lcd = NULL; -#endif - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE -struct ili9341_lcd_s *g_ltdc = NULL; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE -/**************************************************************************** - * Name: stm32_ili9341_initialize - * - * Description: - * Initialize the ili9341 LCD controller to the RGB interface mode. - * - ****************************************************************************/ - -static int stm32_ili9341_initialize(void) -{ - struct ili9341_lcd_s *lcd = g_ltdc; - - lcd = stm32_ili93414ws_initialize(); - - if (lcd == NULL) - { - return ENODEV; - } - - /* Select spi device */ - - lcdinfo("Initialize ili9341 lcd driver\n"); - lcd->select(lcd); - -#ifdef CONFIG_DEBUG_LCD_INFO - /* Read display identification */ - - uint8_t param; - lcd->sendcmd(lcd, ILI9341_READ_ID1); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules manufacturer ID: %d\n", param); - - lcd->sendcmd(lcd, ILI9341_READ_ID2); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules driver version ID: %d\n", param); - - lcd->sendcmd(lcd, ILI9341_READ_ID3); - lcd->recvparam(lcd, ¶m); - lcdinfo("ili9341 LCD driver: LCD modules driver ID: %d\n", param); -#endif - - /* Reset the lcd display to the default state */ - - lcdinfo("ili9341 LCD driver: Software Reset\n"); - lcd->sendcmd(lcd, ILI9341_SOFTWARE_RESET); - up_mdelay(5); - - lcdinfo("ili9341 LCD driver: set Memory Access Control %08x\n", - STM32_ILI9341_MADCTL_PARAM); - lcd->sendcmd(lcd, ILI9341_MEMORY_ACCESS_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_MADCTL_PARAM); - - /* Pixel Format */ - - lcdinfo("ili9341 LCD driver: Set Pixel Format: %02x\n", - STM32_ILI9341_PIXSET_PARAM); - lcd->sendcmd(lcd, ILI9341_PIXEL_FORMAT_SET); - lcd->sendparam(lcd, STM32_ILI9341_PIXSET_PARAM); - - /* Select column */ - - lcdinfo("ili9341 LCD driver: Set Column Address\n"); - lcd->sendcmd(lcd, ILI9341_COLUMN_ADDRESS_SET); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, (ILI9341_XRES >> 8)); - lcd->sendparam(lcd, (ILI9341_XRES & 0xff)); - - /* Select page */ - - lcdinfo("ili9341 LCD driver: Set Page Address\n"); - lcd->sendcmd(lcd, ILI9341_PAGE_ADDRESS_SET); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, 0); - lcd->sendparam(lcd, (ILI9341_YRES >> 8)); - lcd->sendparam(lcd, (ILI9341_YRES & 0xff)); - - /* RGB Interface signal control */ - - lcdinfo("ili9341 LCD driver: Set RGB Interface signal control: %02x\n", - STM32_ILI9341_IFMODE_PARAM); - lcd->sendcmd(lcd, ILI9341_RGB_SIGNAL_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_IFMODE_PARAM); - - /* Interface control */ - - lcdinfo("ili9341 LCD driver: Set Interface control: %d:%d:%d\n", - STM32_ILI9341_IFCTL_PARAM1, - STM32_ILI9341_IFCTL_PARAM2, - STM32_ILI9341_IFCTL_PARAM3); - - lcd->sendcmd(lcd, ILI9341_INTERFACE_CONTROL); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM1); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM2); - lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM3); - - /* Sleep out set to the end */ - - lcdinfo("ili9341 LCD driver: Sleep Out\n"); - lcd->sendcmd(lcd, ILI9341_SLEEP_OUT); - up_mdelay(5); /* 120? */ - - /* Display on */ - - lcdinfo("ili9341 LCD driver: Display On\n"); - lcd->sendcmd(lcd, ILI9341_DISPLAY_ON); - - /* Deselect spi device */ - - lcd->deselect(lcd); - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD Device. - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Set display off */ - - g_lcd->setpower(g_lcd, 0); - - g_lcd = NULL; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a reference to the LCD object for the specified LCD Device. - * This allows support for multiple LCD devices. - * - * Input Parameters: - * lcddev - Number of the LDC Device. - * - * Returned Value: - * Reference to the LCD object if exist otherwise NULL - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - if (lcddev == ILI9341_LCD_DEVICE) - { - return g_lcd; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is - * fully initialized, display memory cleared, and the LCD ready to use, but - * with the power setting at 0 (full off). - * - * Input Parameters: - * - * Returned Value: - * On success - Ok - * On error - Error Code - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* check if always initialized */ - - if (!g_lcd) - { - /* Initialize the sub driver structure */ - - struct ili9341_lcd_s *dev = stm32_ili93414ws_initialize(); - - /* Initialize public lcd driver structure */ - - if (dev) - { - /* Get a reference to valid lcd driver structure to avoid repeated - * initialization of the LCD Device. Also enables uninitializing of - * the LCD Device. - */ - - g_lcd = ili9341_initialize(dev, ILI9341_LCD_DEVICE); - if (g_lcd) - { - return OK; - } - } - - return -ENODEV; - } - - return OK; -} -#endif /* CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE */ - -#ifdef CONFIG_STM32_LTDC -/**************************************************************************** - * Name: up_fbinitialize - * - * Description: - * Initialize the framebuffer video hardware associated with the display. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * - * Returned Value: - * Zero is returned on success; a negated errno value is returned on any - * failure. - * - ****************************************************************************/ - -int up_fbinitialize(int display) -{ - static bool initialized = false; - int ret = OK; - - if (!initialized) - { -#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE - /* Initialize the ili9341 LCD controller */ - - ret = stm32_ili9341_initialize(); - if (ret >= OK) - { - ret = stm32_ltdcinitialize(); - } - -#else - /* Custom LCD display with RGB interface */ - - ret = stm32_ltdcinitialize(); -#endif - - initialized = (ret >= OK); - } - - return ret; -} - -/**************************************************************************** - * Name: up_fbgetvplane - * - * Description: - * Return a a reference to the framebuffer object for the specified video - * plane of the specified plane. - * Many OSDs support multiple planes of video. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * vplane - Identifies the plane being queried. - * - * Returned Value: - * A non-NULL pointer to the frame buffer access structure is returned on - * success; NULL is returned on any failure. - * - ****************************************************************************/ - -struct fb_vtable_s *up_fbgetvplane(int display, int vplane) -{ - return stm32_ltdcgetvplane(vplane); -} - -/**************************************************************************** - * Name: up_fbuninitialize - * - * Description: - * Uninitialize the framebuffer support for the specified display. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_fbuninitialize(int display) -{ - stm32_ltdcuninitialize(); -} -#endif /* CONFIG_STM32_LTDC */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c deleted file mode 100644 index 9ce1aab6c4229..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f429i-disco.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM Timer */ - -#define STM32F429IDISCO_PWMTIMER 1 - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F429IDISCO_PWMTIMER); - if (!pwm) - { - tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - tmrerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c deleted file mode 100644 index 940f4af472ae5..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) ||\ - defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI5 -struct spi_dev_s *g_spidev5 = NULL; -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f429i-disco - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI5 - stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ - stm32_configgpio(GPIO_CS_LCD); /* LCD chip select */ - stm32_configgpio(GPIO_LCD_DC); /* LCD Data/Command select */ - stm32_configgpio(GPIO_LCD_ENABLE); /* LCD enable select */ -#endif -#if defined(CONFIG_STM32_SPI4) && defined(CONFIG_MTD_SST25XX) - stm32_configgpio(GPIO_CS_SST25); /* SST25 FLASH chip select */ -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ -#if defined(CONFIG_MTD_SST25XX) - if (devid == SPIDEV_FLASH(0)) - { - stm32_gpiowrite(GPIO_CS_SST25, !selected); - } -#endif -} - -uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#if defined(CONFIG_STM32F429I_DISCO_ILI9341) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_CS_LCD, !selected); - } - else -#endif - - { - stm32_gpiowrite(GPIO_CS_MEMS, !selected); - } -} - -uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI4 -int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI5 -int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_STM32F429I_DISCO_ILI9341) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(GPIO_LCD_DC, !cmd); - - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#endif /* CONFIG_SPI_CMDDATA */ - -/**************************************************************************** - * Name: stm32_spi5initialize - * - * Description: - * Initialize the selected SPI port. - * As long as the method stm32_spibus_initialize recognized the initialized - * state of the spi device by the spi enable flag of the cr1 register, it - * isn't safe to disable the spi device outside of the nuttx spi interface - * structure. But this has to be done as long as the nuttx spi interface - * doesn't support bidirectional data transfer for multiple devices share - * one spi bus. This wrapper does nothing else than store the initialized - * state of the spi device after the first initializing and should be used - * by each driver who shares the spi5 bus. - * - * Input Parameters: - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI5 -struct spi_dev_s *stm32_spi5initialize(void) -{ - if (!g_spidev5) - { - g_spidev5 = stm32_spibus_initialize(5); - } - - return g_spidev5; -} -#endif -#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c deleted file mode 100644 index 9179d51fc3fb0..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c +++ /dev/null @@ -1,337 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32.h" -#include "stm32f429i-disco.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifdef CONFIG_INPUT_STMPE811 -#ifndef CONFIG_INPUT -# error "STMPE811 support requires CONFIG_INPUT" -#endif - -#ifndef CONFIG_STM32_I2C3 -# error "STMPE811 support requires CONFIG_STM32_I2C3" -#endif - -#ifndef CONFIG_STMPE811_I2C -# error "Only the STMPE811 I2C interface is supported" -#endif - -#ifdef CONFIG_STMPE811_SPI -# error "Only the STMPE811 SPI interface is supported" -#endif - -#ifndef CONFIG_STMPE811_FREQUENCY -# define CONFIG_STMPE811_FREQUENCY 100000 -#endif - -#ifndef CONFIG_STMPE811_I2CDEV -# define CONFIG_STMPE811_I2CDEV 3 -#endif - -#if CONFIG_STMPE811_I2CDEV != 3 -# error "CONFIG_STMPE811_I2CDEV must be three" -#endif - -#ifndef CONFIG_STMPE811_DEVMINOR -# define CONFIG_STMPE811_DEVMINOR 0 -#endif - -/* Board definitions ********************************************************/ - -/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both - * connected to the STM32 via I2C1. They share a common interrupt line: PI2. - * - * STMPE811 U24, I2C address 0x41 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- TouchScreen_Y- LCD Connector XL - * X- TouchScreen_X- LCD Connector XR - * Y+ TouchScreen_Y+ LCD Connector XD - * X+ TouchScreen_X+ LCD Connector XU - * IN3 EXP_IO9 - * IN2 EXP_IO10 - * IN1 EXP_IO11 - * IN0 EXP_IO12 - * - * STMPE811 U29, I2C address 0x44 (7-bit) - * ------ ---- ---------------- -------------------------------------------- - * STPE11 PIN BOARD SIGNAL BOARD CONNECTION - * ------ ---- ---------------- -------------------------------------------- - * Y- EXP_IO1 - * X- EXP_IO2 - * Y+ EXP_IO3 - * X+ EXP_IO4 - * IN3 EXP_IO5 - * IN2 EXP_IO6 - * IN1 EXP_IO7 - * IN0 EXP_IO8 - */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_stmpe811config_s -{ - /* Configuration structure as seen by the STMPE811 driver */ - - struct stmpe811_config_s config; - - /* Additional private definitions only known to this driver */ - - STMPE811_HANDLE handle; /* The STMPE811 driver handle */ - xcpt_t handler; /* The STMPE811 interrupt handler */ - void *arg; /* Interrupt handler argument */ -}; - -/**************************************************************************** - * Static Function Prototypes - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks - * to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs.* so that contact and loss- - * of-contact events can be detected. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg); -static void stmpe811_enable(struct stmpe811_config_s *state, - bool enable); -static void stmpe811_clear(struct stmpe811_config_s *state); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* A reference to a structure of this type must be passed to the STMPE811 - * driver. This structure provides information about the configuration - * of the STMPE811 and provides some board-specific hooks. - * - * Memory for this structure is provided by the caller. It is not copied - * by the driver and is presumed to persist while the driver is active. The - * memory must be writable because, under certain circumstances, the driver - * may modify frequency or X plate resistance values. - */ - -#ifndef CONFIG_STMPE811_TSC_DISABLE -static struct stm32_stmpe811config_s g_stmpe811config = -{ - .config = - { -#ifdef CONFIG_STMPE811_I2C - .address = STMPE811_ADDR1, -#endif - .frequency = CONFIG_STMPE811_FREQUENCY, - -#ifdef CONFIG_STMPE811_MULTIPLE - .irq = STM32_IRQ_EXTI2, -#endif - .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), - .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, - - .attach = stmpe811_attach, - .enable = stmpe811_enable, - .clear = stmpe811_clear, - }, - .handler = NULL, - .arg = NULL, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* IRQ/GPIO access callbacks. These operations all hidden behind - * callbacks to isolate the STMPE811 driver from differences in GPIO - * interrupt handling by varying boards and MCUs. - * - * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt - * enable - Enable or disable the GPIO interrupt - * clear - Acknowledge/clear any pending GPIO interrupt - */ - -static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, - void *arg) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - - iinfo("Saving handler %p\n", isr); - DEBUGASSERT(priv); - - /* Just save the handler. We will use it when EXTI interruptsare enabled */ - - priv->handler = isr; - priv->arg = arg; - return OK; -} - -static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) -{ - struct stm32_stmpe811config_s *priv = - (struct stm32_stmpe811config_s *)state; - irqstate_t flags; - - /* Attach and enable, or detach and disable. Enabling and disabling GPIO - * interrupts is a multi-step process so the safest thing is to keep - * interrupts disabled during the reconfiguration. - */ - - flags = enter_critical_section(); - if (enable) - { - /* Configure the EXTI interrupt using the SAVED handler */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, - priv->handler, priv->arg); - } - else - { - /* Configure the EXTI interrupt with a NULL handler to disable it */ - - stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, - NULL, NULL); - } - - leave_critical_section(flags); -} - -static void stmpe811_clear(struct stmpe811_config_s *state) -{ - /* Does nothing */ -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tsc_setup - * - * Description: - * This function is called by board-bringup logic to configure the - * touchscreen device. This function will register the driver as - * /dev/inputN where N is the minor device number. - * - * Input Parameters: - * minor - The input device minor number - * - * Returned Value: - * Zero is returned on success. Otherwise, a negated errno value is - * returned to indicate the nature of the failure. - * - ****************************************************************************/ - -int stm32_tsc_setup(int minor) -{ -#ifndef CONFIG_STMPE811_TSC_DISABLE - struct i2c_master_s *dev; - int ret; - - iinfo("minor %d\n", minor); - DEBUGASSERT(minor == 0); - - /* Check if we are already initialized */ - - if (!g_stmpe811config.handle) - { - iinfo("Initializing\n"); - - /* Configure the STMPE811 interrupt pin as an input */ - - stm32_configgpio(GPIO_IO_EXPANDER); - - /* Get an instance of the I2C interface */ - - dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); - if (!dev) - { - ierr("ERROR: Failed to initialize I2C bus %d\n", - CONFIG_STMPE811_I2CDEV); - return -ENODEV; - } - - /* Instantiate the STMPE811 driver */ - - g_stmpe811config.handle = - stmpe811_instantiate(dev, - (struct stmpe811_config_s *)&g_stmpe811config); - if (!g_stmpe811config.handle) - { - ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); - return -ENODEV; - } - - /* Initialize and register the I2C touchscreen device */ - - ret = stmpe811_register(g_stmpe811config.handle, - CONFIG_STMPE811_DEVMINOR); - if (ret < 0) - { - ierr("ERROR: Failed to register STMPE driver: %d\n", ret); - - /* stm32_i2cbus_uninitialize(dev); */ - - return -ENODEV; - } - } - - return OK; -#else - return -ENOSYS; -#endif -} - -#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c deleted file mode 100644 index 3178d70af9ec4..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otghs.h" -#include "stm32f429i-disco.h" - -#ifdef CONFIG_STM32_OTGHS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F429IDISCO_USBHOST_PRIO -# define CONFIG_STM32F429IDISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGHS - stm32_configgpio(GPIO_OTGHS_VBUS); - stm32_configgpio(GPIO_OTGHS_PWRON); - stm32_configgpio(GPIO_OTGHS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otghshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F429IDISCO_USBHOST_PRIO, - CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGHS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c deleted file mode 100644 index b3d122eb03906..0000000000000 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c +++ /dev/null @@ -1,211 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f429i-disco.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_ledpminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_ledpminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/CMakeLists.txt deleted file mode 100644 index 290b7c62f75f6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt +++ /dev/null @@ -1,30 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) - -if(NOT CONFIG_BUILD_FLAT) - add_subdirectory(kernel) - set_property( - GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld - ${CMAKE_CURRENT_LIST_DIR}/scripts/user-space.ld) -endif() diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig deleted file mode 100644 index 165220b6cbe92..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_SHELL_SERVICE=y -CONFIG_ADBD_USB_SERVER=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_URANDOM=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LIBUV=y -CONFIG_LINE_MAX=128 -CONFIG_MMCSD=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_CHILD_STATUS=y -CONFIG_SCHED_HAVE_PARENT=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2020 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_ADBD=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBADB=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig deleted file mode 100644 index f30298ce9ae06..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ /dev/null @@ -1,74 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_AUDIO=y -CONFIG_AUDIO_CS43L22=y -CONFIG_AUDIO_CUSTOM_DEV_PATH=y -CONFIG_AUDIO_EXCLUDE_TONE=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_AUDIO=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_I2C_DRIVER=y -CONFIG_I2C_POLLED=y -CONFIG_I2C_RESET=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_I2S3=y -CONFIG_STM32_I2S3_TX=y -CONFIG_STM32_I2S_MCK=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_OTGFS_SOFINTR=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USBHOST=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NXPLAYER=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_USBHOST_ISOC_DISABLE=y -CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig deleted file mode 100644 index 4220e68169f23..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig +++ /dev/null @@ -1,66 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_APDS9960=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_FB_STACKSIZE=16000 -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_LARGEFILE=y -CONFIG_FS_PROCFS=y -CONFIG_GAMES_BRICKMATCH=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_APA102=y -CONFIG_LCD_APA102_FREQUENCY=10000000 -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_APDS9960=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_DMA1=y -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig deleted file mode 100644 index 2922985e15590..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CANUTILS_LIBDRONECAN=y -CONFIG_CAN_EXTID=y -CONFIG_EXAMPLES_DRONECAN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_CAN1=y -CONFIG_STM32_CAN1_BAUD=500000 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig deleted file mode 100644 index 4eb4037db8123..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig +++ /dev/null @@ -1,99 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_COMPOSITE_IAD=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=128 -CONFIG_MMCSD=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_MACADDR_1=0xdeadcafe -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NFS=y -CONFIG_NFS_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_FILE_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/nfs/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_RNDIS_COMPOSITE=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_COMPOSITE=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBDEV_COMPOSITE=y -CONFIG_USBMSC=y -CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig deleted file mode 100644 index 53f1a03f82066..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_SYSTEM_DD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CXX_EXCEPTION=y -CONFIG_CXX_STANDARD="c++17" -CONFIG_DRVR_MKRD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_NONE=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBCXXTOOLCHAIN=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig deleted file mode 100644 index 6da12af7d4289..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ALLOW_GPL_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_HAVE_CXX=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="cxxtest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=2 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TESTING_CXXTEST=y -CONFIG_UCLIBCXX=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig deleted file mode 100644 index 41930cc1dae8e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_ELF_STACKSIZE=4096 -CONFIG_EXAMPLES_ELF=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="elf_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_MM_REGIONS=2 -CONFIG_PATH_INITIAL="/mnt/romfs" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig deleted file mode 100644 index 6659ea3bcc4e7..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_DRIPADDR=0xc0a80001 -CONFIG_NETINIT_IPADDR=0xc0a80010 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=16 -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=16 -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_W5500=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig deleted file mode 100644 index 4f103fa26f4b4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ /dev/null @@ -1,88 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NET_IPv4 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETINIT_IPv6NETMASK_8=0xff80 -CONFIG_NETINIT_NOMAC=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_SOLINGER=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32F4DISBB=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_USART6_RXBUFSIZE=64 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs b/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs deleted file mode 100644 index 8905673c9792d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs +++ /dev/null @@ -1,42 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT1 = memory.ld -LDSCRIPT2 = kernel-space.ld - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig deleted file mode 100644 index 12fbc10e64f28..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARM_MPU=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILD_PROTECTED=y -CONFIG_CONSOLE_SYSLOG=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DISABLE_ENVIRON=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="ostest_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_KERNEL_HEAPSIZE=16384 -CONFIG_MM_REGIONS=2 -CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=22 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2013 -CONFIG_STM32_CCMEXCLUDE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_TESTING_OSTEST=y -CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 -CONFIG_TESTING_OSTEST_STACKSIZE=2048 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig deleted file mode 100644 index fe6437b339e90..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD_BACKPACK=y -CONFIG_LCD_LCD1602=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig deleted file mode 100644 index fdb159aa6f946..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_LWL_CONSOLE=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig deleted file mode 100644 index aa01c29c274c6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MAX31855=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MAX31855=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig deleted file mode 100644 index 120398ee50c63..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DISABLE_OS_API is not set -# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set -# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set -# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set -# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set -# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set -# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set -# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set -# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set -# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_BASENAME is not set -# CONFIG_NSH_DISABLE_CMP is not set -# CONFIG_NSH_DISABLE_DF is not set -# CONFIG_NSH_DISABLE_DIRNAME is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_ITEF is not set -# CONFIG_NSH_DISABLE_LOOPS is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_SEMICOLON is not set -# CONFIG_NSH_DISABLE_TIME is not set -# CONFIG_NSH_DISABLE_UNAME is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_NX_DISABLE_1BPP is not set -# CONFIG_NX_WRITEONLY is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_EXAMPLES_NXHELLO=y -CONFIG_EXAMPLES_NXHELLO_BPP=1 -CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 -CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_MAX7219=y -CONFIG_LCD_NOGETRUN=y -CONFIG_MAX7219_NHORIZONTALBLKS=4 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NX=y -CONFIG_NXFONT_MONO5X8=y -CONFIG_NXSTART_SERVERSTACK=1536 -CONFIG_NX_BLOCKING=y -CONFIG_NX_MXCLIENTMSGS=32 -CONFIG_PREALLOC_MQ_MSGS=16 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=21 -CONFIG_START_MONTH=4 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig deleted file mode 100644 index 4a3511f054699..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ /dev/null @@ -1,70 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_STM32_CCMEXCLUDE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CODECS_HASH_MD5=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MM_REGIONS=2 -CONFIG_NETUTILS_CODECS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=30 -CONFIG_SCHED_WAITPID=y -CONFIG_SENDFILE_BUFSIZE=1024 -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig deleted file mode 100644 index a0b33e071f609..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MB_TCP_ENABLED is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MW is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_MODBUS=y -CONFIG_EXAMPLES_MODBUS_PORT=1 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INDUSTRY_MODBUS=y -CONFIG_INDUSTRY_MODBUS_SLAVE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_BAUD=38400 -CONFIG_USART1_PARITY=2 -CONFIG_USART1_RS485=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig deleted file mode 100644 index baae91a957c31..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MODULE=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig deleted file mode 100644 index 012456083ba42..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_KEYBOARD=y -CONFIG_EXAMPLES_KEYBOARD_DEVPATH="/dev/keypad0" -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_I2C=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_MPR121_KEYPAD=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_I2C1=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig deleted file mode 100644 index d5d4a081473f5..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEBUG_ERROR is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_SENSORS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_QENCODER=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_MT6816=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig deleted file mode 100644 index 20094fe529c66..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ /dev/null @@ -1,91 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_MMCSD_MMCSUPPORT is not set -# CONFIG_MMCSD_SPI is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_LAN8720=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 -CONFIG_MMCSD_SDIO=y -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_SOLINGER=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32F4DISBB=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PHYADDR=0 -CONFIG_STM32_PHYSR=31 -CONFIG_STM32_PHYSR_100FD=0x0018 -CONFIG_STM32_PHYSR_100HD=0x0008 -CONFIG_STM32_PHYSR_10FD=0x0014 -CONFIG_STM32_PHYSR_10HD=0x0004 -CONFIG_STM32_PHYSR_ALTCONFIG=y -CONFIG_STM32_PHYSR_ALTMODE=0x001c -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_SDIO=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART6_RXBUFSIZE=64 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig deleted file mode 100644 index 0b5d259baa585..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig deleted file mode 100644 index 0e98105330cd2..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set -# CONFIG_NXFONTS_DISABLE_16BPP is not set -# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set -# CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_NX_PACKEDMSFIRST is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_EXAMPLES_NXLINES=y -CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 -CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 -CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 -CONFIG_EXAMPLES_NXLINES_BPP=16 -CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb -CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nxlines_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_MAXCONTRAST=1 -CONFIG_LCD_MAXPOWER=255 -CONFIG_LCD_SSD1289=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LIBRARY=y -CONFIG_NSH_READLINE=y -CONFIG_NX=y -CONFIG_NXFONT_SANS22X29B=y -CONFIG_NXFONT_SANS23X27=y -CONFIG_NXTK_BORDERCOLOR1=0x5cb7 -CONFIG_NXTK_BORDERCOLOR2=0x21c9 -CONFIG_NXTK_BORDERCOLOR3=0xffdf -CONFIG_NX_BLOCKING=y -CONFIG_NX_KBD=y -CONFIG_NX_XYINPUT_MOUSE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_FSMC=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig deleted file mode 100644 index 33c24e9c6302e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig +++ /dev/null @@ -1,61 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_MKRD=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=2048 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_NXSCOPE=y -CONFIG_EXAMPLES_NXSCOPE_CDCACM=y -CONFIG_EXAMPLES_NXSCOPE_SERIAL_PATH="/dev/ttyACM0" -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nxscope_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_INTELHEX_BINARY=y -CONFIG_LOGGING_NXSCOPE=y -CONFIG_LOGGING_NXSCOPE_ACKFRAMES=y -CONFIG_LOGGING_NXSCOPE_DIVIDER=y -CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y -CONFIG_MM_REGIONS=2 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_READLINE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig deleted file mode 100644 index b1c252b5e6c3b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ARCH_LEDS is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_CUSTOM_PMINIT=y -CONFIG_ARCH_IDLE_CUSTOM=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PM=y -CONFIG_PM_BUTTONS=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_ALARM=y -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig deleted file mode 100644 index 245906de64f0f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BINFMT_CONSTRUCTORS=y -CONFIG_BOARDCTL=y -CONFIG_BOARDCTL_APP_SYMTAB=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_CONSOLE_SYSLOG=y -CONFIG_ELF=y -CONFIG_EXAMPLES_POSIXSPAWN=y -CONFIG_EXECFUNCS_HAVE_SYMTAB=y -CONFIG_EXECFUNCS_NSYMBOLS_VAR="g_spawn_nexports" -CONFIG_EXECFUNCS_SYMTAB_ARRAY="g_spawn_exports" -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="posix_spawn_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_MM_REGIONS=2 -CONFIG_PATH_INITIAL="/mnt/romfs" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_START_DAY=26 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig deleted file mode 100644 index 0da7f887e4182..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_PTYTEST=y -CONFIG_EXAMPLES_PTYTEST_POLL=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PSEUDOTERM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SERIAL_TERMIOS=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_STM32_USART3=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig deleted file mode 100644 index 57b1645f4fa6b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_RGBLED=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="rgbled_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_PWM_NCHANNELS=3 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RGBLED=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_TIM2=y -CONFIG_STM32_TIM2_CH2OUT=y -CONFIG_STM32_TIM2_CHANNEL=2 -CONFIG_STM32_TIM2_PWM=y -CONFIG_STM32_TIM3=y -CONFIG_STM32_TIM3_CH3OUT=y -CONFIG_STM32_TIM3_CHANNEL=3 -CONFIG_STM32_TIM3_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig deleted file mode 100644 index 0130b48eb6a11..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ /dev/null @@ -1,92 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=128 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 -CONFIG_NETINIT_DHCPC=y -CONFIG_NETINIT_DRIPADDR=0x0 -CONFIG_NETINIT_MACADDR_1=0xdeadcafe -CONFIG_NETINIT_NETMASK=0x0 -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_LOOPBACK=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NFS=y -CONFIG_NFS_STATISTICS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_FILE_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/nfs/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RNDIS=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_START_DAY=13 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2014 -CONFIG_STM32_DMA2=y -CONFIG_STM32_DMACAPABLE=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig deleted file mode 100644 index e6b0d17a5dbfc..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_ASSERTIONS_FILENAME is not set -# CONFIG_NDEBUG is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_KEYBOARD=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_SBUTTON=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig deleted file mode 100644 index 61fa2cab6f9e3..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_SCHED_SPORADIC=y -CONFIG_SCHED_SPORADIC_MAXREPL=5 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2021 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART6=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART6_RXBUFSIZE=128 -CONFIG_USART6_SERIAL_CONSOLE=y -CONFIG_USART6_TXBUFSIZE=128 -CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig deleted file mode 100644 index 01904582935ec..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_ST7567=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig deleted file mode 100644 index 96ae4a22989bf..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_EXAMPLES_FB=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LCD_PORTRAIT=y -CONFIG_LCD_ST7789=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NXFONTS_DISABLE_1BPP=y -CONFIG_NXFONTS_DISABLE_24BPP=y -CONFIG_NXFONTS_DISABLE_2BPP=y -CONFIG_NXFONTS_DISABLE_32BPP=y -CONFIG_NXFONTS_DISABLE_4BPP=y -CONFIG_NXFONTS_DISABLE_8BPP=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig deleted file mode 100644 index 35821863695b4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CXX_LOCALIZATION=y -CONFIG_CXX_WCHAR=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_EXAMPLES_HELLOXX=y -CONFIG_HAVE_CXX=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBCXX=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_LOCALE=y -CONFIG_LIBC_LOCALTIME=y -CONFIG_LIBC_MAX_EXITFUNS=4 -CONFIG_LIBM=y -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=2 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2012 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TLS_NELEM=16 -CONFIG_TLS_TASK_NELEM=8 -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig deleted file mode 100644 index 660319b4b17d6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_FAT_LCNAMES=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_IFUPDOWN=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSLOG_CHAR=y -CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_USBMSC=y -CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 -CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/ram0" -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USBDEV=y -CONFIG_USBMSC=y -CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig deleted file mode 100644 index 2b1efa580e7c6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_DEV_CONSOLE is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_USBDEVCTRL=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CDCACM=y -CONFIG_CDCACM_CONSOLE=y -CONFIG_CDCACM_RXBUFSIZE=256 -CONFIG_CDCACM_TXBUFSIZE=256 -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAMLOG=y -CONFIG_RAMLOG_BUFSIZE=4096 -CONFIG_RAMLOG_SYSLOG=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=27 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_OTGFS=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig deleted file mode 100644 index 3179db663c279..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ /dev/null @@ -1,102 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_MMCSD_HAVE_CARDDETECT is not set -# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set -# CONFIG_NET_ARP is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_SPI_CALLBACK is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_CODECS_HASH_MD5=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_HARDFAULT_ALERT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m -CONFIG_EXAMPLES_WEBSERVER=y -CONFIG_FAT_LFN=y -CONFIG_FS_FAT=y -CONFIG_FS_FATTIME=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HEAP_COLORATION=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_ENVPATH=y -CONFIG_LIBC_EXECFUNCS=y -CONFIG_LINE_MAX=64 -CONFIG_MMCSD=y -CONFIG_MM_IOB=y -CONFIG_MM_REGIONS=2 -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETINIT_NETLOCAL=y -CONFIG_NETUTILS_CODECS=y -CONFIG_NETUTILS_FTPC=y -CONFIG_NETUTILS_HTTPD_DIRLIST=y -CONFIG_NETUTILS_HTTPD_SENDFILE=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NETUTILS_WEBSERVER=y -CONFIG_NET_USRSOCK=y -CONFIG_NET_USRSOCK_PREALLOC_CONNS=16 -CONFIG_NET_USRSOCK_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_PATH_INITIAL="/mnt/sd0/bin" -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_READLINE_CMD_HISTORY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORKPRIORITY=30 -CONFIG_SCHED_WAITPID=y -CONFIG_SENDFILE_BUFSIZE=1024 -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=22 -CONFIG_START_MONTH=10 -CONFIG_START_YEAR=2019 -CONFIG_STM32_DMA1=y -CONFIG_STM32_DMA2=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI2=y -CONFIG_STM32_SPI2_DMA=y -CONFIG_STM32_SPI3=y -CONFIG_STM32_SPI3_DMA=y -CONFIG_STM32_USART2=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_NTPC=y -CONFIG_TESTING_OSTEST=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 -CONFIG_WIRELESS_GS2200M=y -CONFIG_WL_GS2200M=y -CONFIG_WL_GS2200M_DISABLE_DHCPC=y -CONFIG_WL_GS2200M_SPI_FREQUENCY=10000000 diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig deleted file mode 100644 index fb9fdbfc6b712..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ARCH_FPU is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32f4discovery" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F4=y -CONFIG_ARCH_CHIP_STM32F407VG=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 -CONFIG_MM_REGIONS=2 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM=y -CONFIG_RAM_SIZE=114688 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_XEN1210=y -CONFIG_START_DAY=17 -CONFIG_START_MONTH=8 -CONFIG_START_YEAR=2016 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_TIM1=y -CONFIG_STM32_TIM1_CH1OUT=y -CONFIG_STM32_TIM1_PWM=y -CONFIG_STM32_USART2=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART2_RXBUFSIZE=128 -CONFIG_USART2_SERIAL_CONSOLE=y -CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32f4discovery/include/board.h b/boards/arm/stm32/stm32f4discovery/include/board.h deleted file mode 100644 index 0287bd8a0fda8..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/include/board.h +++ /dev/null @@ -1,650 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -# include -#endif - -/* Do not include STM32-specific header files here */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* The STM32F4 Discovery board features a single 8MHz crystal. - * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. - * - * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL - * configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed - * SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock - */ - -/* HSI - 16 MHz RC factory-trimmed - * LSI - 32 KHz RC - * HSE - On-board crystal frequency is 8MHz - * LSE - 32.768 kHz - */ - -#define STM32_BOARD_XTAL 8000000ul - -#define STM32_HSI_FREQUENCY 16000000ul -#define STM32_LSI_FREQUENCY 32000 -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_LSE_FREQUENCY 32768 - -/* Main PLL Configuration. - * - * PLL source is HSE - * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN - * = (8,000,000 / 8) * 336 - * = 336,000,000 - * SYSCLK = PLL_VCO / PLLP - * = 336,000,000 / 2 = 168,000,000 - * USB OTG FS, SDIO and RNG Clock - * = PLL_VCO / PLLQ - * = 48,000,000 - */ - -#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) -#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) -#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 -#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) - -#define STM32_SYSCLK_FREQUENCY 168000000ul - -/* AHB clock (HCLK) is SYSCLK (168MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) - -/* Timers driven from APB1 will be twice PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) - -/* Timers driven from APB2 will be twice PCLK2 */ - -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* SDIO dividers. Note that slower clocking is required when DMA is disabled - * in order to avoid RX overrun/TX underrun errors due to delayed responses - * to service FIFOs in interrupt driven mode. These values have not been - * tuned!!! - * - * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz - */ - -#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz - * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz - */ - -#ifdef CONFIG_SDIO_DMA -# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) -#else -# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) -#endif - -/* LED definitions **********************************************************/ - -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs - * in any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -#define BOARD_LED_GREEN BOARD_LED1 -#define BOARD_LED_ORANGE BOARD_LED2 -#define BOARD_LED_RED BOARD_LED3 -#define BOARD_LED_BLUE BOARD_LED4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on - * board the stm32f4discovery. The following definitions describe how NuttX - * controls the LEDs: - */ - -#define LED_STARTED 0 /* LED1 */ -#define LED_HEAPALLOCATE 1 /* LED2 */ -#define LED_IRQSENABLED 2 /* LED1 + LED2 */ -#define LED_STACKCREATED 3 /* LED3 */ -#define LED_INIRQ 4 /* LED1 + LED3 */ -#define LED_SIGNAL 5 /* LED2 + LED3 */ -#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ -#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ - -/* Button definitions *******************************************************/ - -/* The STM32F4 Discovery supports one button: */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate function pin selections ****************************************/ - -/* CAN */ - -#ifndef CONFIG_STM32_FSMC -# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) -# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) -#endif - -#ifndef CONFIG_STM32_ETHMAC -# define GPIO_CAN2_RX (GPIO_CAN2_RX_1|GPIO_SPEED_50MHz) -# define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) -#endif - -/* USART1 */ - -#ifdef CONFIG_USART1_RS485 - /* Lets use for RS485 on pins: PB6 and PB7 */ - -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) - - /* RS485 DIR pin: PA15 */ - -# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ - GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN15) - -#endif - -/* USART2: - * - * The STM32F4 Discovery has no on-board serial devices, but the console is - * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial - * device. - * - * These pins selections, however, conflict with pin usage on the - * STM32F4DIS-BB. - */ - -#ifndef CONFIG_STM32F4DISBB -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3, P1 pin 13 */ -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2, P1 pin 14 */ -# define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0, P1 pin 11 */ -# define GPIO_USART2_RTS GPIO_USART2_RTS_1 /* PA1, P1 pin 12 (conflict with USER button) */ -#endif - -/* USART3: - * - * Used in pseudoterm configuration and also with the BT860 HCI UART. - * RTS/CTS Flow control support is needed by the HCI UART. - * - * There are conflicts with the STM32F4DIS-BB Ethernet in this configuration - * when Ethernet is enabled: - * - * PB-11 conflicts with Ethernet TXEN - * PB-13 conflicts with Ethernet TXD1 - * - * UART3 TXD and RXD are available on CON4 PD8 and PD8 of the STM32F4DIS-BB, - * respectively, but not CTS or RTS. For now we assume that Ethernet is not - * enabled if USART3 is used in a configuration with the STM32F4DIS-BB. - */ - -#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10, P1 pin 34 (also MP45DT02 CLK_IN) */ -#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11, P1 pin 35 */ -#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13, P1 pin 37 */ -#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14, P1 pin 38 */ - -/* USART6: - * - * The STM32F4DIS-BB base board provides RS-232 drivers and a DB9 connector - * for USART6. This is the preferred serial console for use with the - * STM32F4DIS-BB. - * - * NOTE: CTS and RTS are not brought out to the RS-232 connector on the - * baseboard. - */ - -#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 (also I2S3_MCK and P2 pin 48) */ -#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 (also P2 pin 47) */ - -/* PWM - * - * The STM32F4 Discovery has no real on-board PWM devices, but the board - * can be configured to output a pulse train using TIM4 CH2 on PD13. - */ - -#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) - -/* Capture - * - * The STM32F4 Discovery has no real on-board pwm capture devices, but the - * board can be configured to capture pwm using TIM3 CH2 PB5. - */ - -#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) - -/* RGB LED - * - * R = TIM1 CH1 on PE9 | G = TIM2 CH2 on PA1 | B = TIM3 CH3 on PB0 - */ - -#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) -#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) - -/* SPI - There is a MEMS device on SPI1 using these pins: */ - -#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) - -/* SPI DMA -- As used for I2S DMA transfer with the audio configuration */ - -#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 -#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 - -/* SPI2 - Test MAX31855 on SPI2 PB10 = SCK, PB14 = MISO */ - -#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_50MHz) - -/* SPI2 DMA -- As used for MMC/SD SPI */ - -#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX -#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX - -/* SPI3 DMA -- As used for I2S DMA transfer with the audio configuration */ - -#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) -#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) - -#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 -#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 - -/* I2S3 - CS43L22 configuration uses I2S3 */ - -#define GPIO_I2S3_SD GPIO_I2S3_SD_2 -#define GPIO_I2S3_CK GPIO_I2S3_CK_2 -#define GPIO_I2S3_WS GPIO_I2S3_WS_1 - -#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 -#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 - -/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and - * I2C1_SDA are available on the following pins: - * - * - PB6 is I2C1_SCL - * - PB9 is I2C1_SDA - */ - -#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) -#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) - -/* Timer Inputs/Outputs */ - -#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) -#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) - -#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) -#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) - -/* Ethernet *****************************************************************/ - -#if defined(CONFIG_STM32F4DISBB) && defined(CONFIG_STM32_ETHMAC) - /* RMII interface to the LAN8720 PHY */ - -# ifndef CONFIG_STM32_RMII -# error CONFIG_STM32_RMII must be defined -# endif - - /* Clocking is provided by an external 25Mhz XTAL */ - -# ifndef CONFIG_STM32_RMII_EXTCLK -# error CONFIG_STM32_RMII_EXTCLK must be defined -# endif - - /* Pin disambiguation */ - -# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) -# define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) - -#endif - -#ifdef CONFIG_MMCSD_SPI -#define GPIO_MMCSD_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ - GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) - -#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ - GPIO_PORTC | GPIO_PIN1) -#endif - -/* DMA Channel/Stream Selections ********************************************/ - -/* Stream selections are arbitrary for now but might become important in the - * future if we set aside more DMA channels/streams. - * - * SDIO DMA - * DMAMAP_SDIO_1 = Channel 4, Stream 3 - * DMAMAP_SDIO_2 = Channel 4, Stream 6 - */ - -#define DMAMAP_SDIO DMAMAP_SDIO_1 - -/* ZERO CROSS pin definition */ - -#define BOARD_ZEROCROSS_GPIO \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN0) - -/* Pin for APDS-9960 sensor */ - -#define GPIO_APDS9960_INT \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT - -/* IRQ Pin for MPR121 Capacitive Keypad */ - -#define GPIO_MPR121_INT \ - (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0) - -#define BOARD_MPR121_GPIO_INT GPIO_MPR121_INT - -/* Pin for Magnetic Encoder MT6816 */ - -#define GPIO_CS_MT6816 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) - -/* LIS3DSH */ - -#define GPIO_LIS3DSH_EXT0 \ - (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) - -#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 - -/* XEN1210 magnetic sensor */ - -#define GPIO_XEN1210_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN5) - -#define GPIO_CS_XEN1210 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) - -#define BOARD_XEN1210_GPIO_INT GPIO_XEN1210_INT - -#define BOARD_SBUTTON_GPIO_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ - GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN0) - -/* Define what timer to use as XEN1210 CLK (will use channel 1) */ - -#define BOARD_XEN1210_PWMTIMER 1 - -/* Keyboard Matrix Configuration */ - -/* Define keyboard matrix row pins (outputs) */ - -#define GPIO_KMATRIX_ROW0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN7) -#define GPIO_KMATRIX_ROW1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN8) -#define GPIO_KMATRIX_ROW2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) -#define GPIO_KMATRIX_ROW3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN10) - -/* Row pins as inputs with pull-up for early diagnostics */ - -#define GPIO_KMATRIX_ROW0_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN7) -#define GPIO_KMATRIX_ROW1_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN8) -#define GPIO_KMATRIX_ROW2_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN9) -#define GPIO_KMATRIX_ROW3_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN10) - -/* Define keyboard matrix column pins (inputs) */ - -#define GPIO_KMATRIX_COL0 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN11) -#define GPIO_KMATRIX_COL1 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN13) -#define GPIO_KMATRIX_COL2 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ - GPIO_PORTE|GPIO_PIN14) - -/* Column pins as outputs for diagnostics only */ - -#define GPIO_KMATRIX_COL0_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) -#define GPIO_KMATRIX_COL1_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) -#define GPIO_KMATRIX_COL2_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) - -/* Board-level KMATRIX pin definitions */ - -#define BOARD_KMATRIX_ROW0 GPIO_KMATRIX_ROW0 -#define BOARD_KMATRIX_ROW1 GPIO_KMATRIX_ROW1 -#define BOARD_KMATRIX_ROW2 GPIO_KMATRIX_ROW2 -#define BOARD_KMATRIX_ROW3 GPIO_KMATRIX_ROW3 - -#define BOARD_KMATRIX_ROW0_IN GPIO_KMATRIX_ROW0_IN -#define BOARD_KMATRIX_ROW1_IN GPIO_KMATRIX_ROW1_IN -#define BOARD_KMATRIX_ROW2_IN GPIO_KMATRIX_ROW2_IN -#define BOARD_KMATRIX_ROW3_IN GPIO_KMATRIX_ROW3_IN - -#define BOARD_KMATRIX_COL0 GPIO_KMATRIX_COL0 -#define BOARD_KMATRIX_COL1 GPIO_KMATRIX_COL1 -#define BOARD_KMATRIX_COL2 GPIO_KMATRIX_COL2 - -#define BOARD_KMATRIX_COL0_OUT GPIO_KMATRIX_COL0_OUT -#define BOARD_KMATRIX_COL1_OUT GPIO_KMATRIX_COL1_OUT -#define BOARD_KMATRIX_COL2_OUT GPIO_KMATRIX_COL2_OUT - -#ifdef CONFIG_INPUT_KMATRIX -int board_kmatrix_diag(int loops, int delay_ms); -#endif - -/* Keyboard Matrix I2C Configuration */ - -#define CONFIG_STM32_KMATRIX_I2C_BUS 1 /* I2C1 */ -#define CONFIG_STM32_KMATRIX_I2C_ADDR 0x20 /* MCP23X08/PCA9538 address */ -#define CONFIG_STM32_KMATRIX_I2C_FREQ 400000 /* 400 kHz */ - -/* MCO and ETH inputs (referenced by arch/eth driver) */ - -#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) - -/* SDIO */ - -#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) -#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) - -/* USB OTG FS / OTG HS */ - -#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) -#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) -#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) - -/* DAC */ - -#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 -#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 - -/* I2S3 MCK (referenced by audio driver) */ - -#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 - -/* FSMC SRAM/LCD pins */ - -#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) -#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt deleted file mode 100644 index 9691ef0269262..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -target_sources(nuttx_user PRIVATE stm32_userspace.c) diff --git a/boards/arm/stm32/stm32f4discovery/kernel/Makefile b/boards/arm/stm32/stm32f4discovery/kernel/Makefile deleted file mode 100644 index 1edb33f89baad..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/Makefile +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/kernel/Makefile -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) -USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = stm32_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - @echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - @echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_MOTOROLA_SREC),y) - @echo "CP: nuttx_user.srec" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - @echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - -$(TOPDIR)$(DELIM)User.map: nuttx_user.elf - @echo "MK: User.map" - $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map - $(Q) $(CROSSDEV)size nuttx_user.elf - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c deleted file mode 100644 index ee6b7fab075d0..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -#if CONFIG_NUTTX_USERSPACE != 0x08020000 -# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct userspace_data_s g_userspace_data = -{ - .us_heap = &g_mmheap, -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - /* User data memory structure */ - - .us_data = &g_userspace_data, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* User-space work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs deleted file mode 100644 index 109235fb9cd97..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld b/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld deleted file mode 100644 index b9bf5bf4bbb9d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/ld.script b/boards/arm/stm32/stm32f4discovery/scripts/ld.script deleted file mode 100644 index 25abe6a015057..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/ld.script +++ /dev/null @@ -1,126 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/ld.script - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112Kb of SRAM beginning at address 0x2000:0000 - * 2) 16Kb of SRAM beginning at address 0x2001:c000 - * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address - * range. - */ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K -} - -OUTPUT_ARCH(arm) -ENTRY(_stext) -EXTERN(_vectors) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : ALIGN(4) { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : ALIGN(4) { - *(.ARM.extab*) - } > flash - - .ARM.exidx : ALIGN(4) { - __exidx_start = ABSOLUTE(.); - *(.ARM.exidx*) - __exidx_end = ABSOLUTE(.); - } > flash - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - .data : ALIGN(4) { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : ALIGN(4) { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld b/boards/arm/stm32/stm32f4discovery/scripts/memory.ld deleted file mode 100644 index d82501ffb65f7..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld +++ /dev/null @@ -1,88 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/memory.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and - * 192Kb of SRAM. SRAM is split up into three blocks: - * - * 1) 112KB of SRAM beginning at address 0x2000:0000 - * 2) 16KB of SRAM beginning at address 0x2001:c000 - * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 - * - * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 - * where the code expects to begin execution by jumping to the entry point in - * the 0x0800:0000 address range. - * - * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of - * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which - * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld). Allowing the - * additional does permit addition debug instrumentation to be added to the - * kernel space without overflowing the partition. - * - * Alignment of the user space FLASH partition is also a critical factor: - * The user space FLASH partition will be spanned with a single region of - * size 2**n bytes. The alignment of the user-space region must be the same. - * As a consequence, as the user-space increases in size, the alignment - * requirement also increases. - * - * This alignment requirement means that the largest user space FLASH region - * you can have will be 512KB at it would have to be positioned at - * 0x08800000. If you change this address, don't forget to change the - * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify - * the check in kernel/userspace.c. - * - * For the same reasons, the maximum size of the SRAM mapping is limited to - * 4KB. Both of these alignment limitations could be reduced by using - * multiple regions to map the FLASH/SDRAM range or perhaps with some - * clever use of subregions. - * - * A detailed memory map for the 112KB SRAM region is as follows: - * - * 0x2000 0000: Kernel .data region. Typical size: 0.1KB - * ------ ---- Kernel .bss region. Typical size: 1.8KB - * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is - * determined by CONFIG_IDLETHREAD_STACKSIZE and - * adjustments for alignment. Typical is 1KB. - * ------ ---- Padded to 8KB - * 0x2000 2000: User .data region. Size is variable. - * ------ ---- User .bss region Size is variable. - * 0x2000 4000: Beginning of kernel heap. Size determined by - * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. - * 0x2000 8000: Beginning of 32Kb user heap. - * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. - * 0x2001 c000: End+1 of CPU RAM - */ - -MEMORY -{ - /* 1024Kb FLASH */ - - kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K - uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K - xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* 112Kb of contiguous SRAM */ - - ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K - usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K - xsram (rwx) : ORIGIN = 0x20008000, LENGTH = 80K -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld b/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld deleted file mode 100644 index 5e246bc28338f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/user-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -/* Make sure that the critical memory management functions are in user-space. - * the user heap memory manager will reside in user-space but be usable both - * by kernel- and user-space code - */ - -EXTERN(umm_initialize) -EXTERN(umm_addregion) - -EXTERN(malloc) -EXTERN(realloc) -EXTERN(zalloc) -EXTERN(free) - -OUTPUT_ARCH(arm) -SECTIONS -{ - .userspace : { - KEEP(*(.userspace)) - } > uflash - - .text : { - _stext = ABSOLUTE(.); - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > uflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > uflash - - .ARM.extab : { - *(.ARM.extab*) - } > uflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > uflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > usram AT > uflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > usram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt deleted file mode 100644 index e56c3f35a7d26..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt +++ /dev/null @@ -1,234 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_AUDIO_CS43L22) - list(APPEND SRCS stm32_cs43l22.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usb.c) -endif() - -if(CONFIG_LCD_ST7567) - list(APPEND SRCS stm32_st7567.c) -endif() - -if(CONFIG_ENC28J60) - list(APPEND SRCS stm32_enc28j60.c) -endif() - -if(CONFIG_LPWAN_SX127X) - list(APPEND SRCS stm32_sx127x.c) -endif() - -if(CONFIG_LCD_MAX7219) - list(APPEND SRCS stm32_max7219.c) -endif() - -if(CONFIG_LCD_ST7032) - list(APPEND SRCS stm32_st7032.c) -endif() - -if(CONFIG_PCA9635PW) - list(APPEND SRCS stm32_pca9635.c) -endif() - -if(CONFIG_STM32_SDIO) - list(APPEND SRCS stm32_sdio.c) -endif() - -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_ethernet.c) -endif() - -if(CONFIG_LEDS_MAX7219) - list(APPEND SRCS stm32_max7219_leds.c) -endif() - -if(CONFIG_RGBLED) - list(APPEND SRCS stm32_rgbled.c) -endif() - -if(CONFIG_RTC_DS1307) - list(APPEND SRCS stm32_ds1307.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pm.c) -endif() - -if(CONFIG_PM_BUTTONS) - list(APPEND SRCS stm32_pmbuttons.c) -endif() - -if(CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_extmem.c) - - if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) - endif() -endif() - -if(CONFIG_LCD_SSD1351) - list(APPEND SRCS stm32_ssd1351.c) -endif() - -if(CONFIG_LCD_UG2864AMBAG01) - list(APPEND SRCS stm32_ug2864ambag01.c) -endif() - -if(CONFIG_LCD_UG2864HSWEG01) - list(APPEND SRCS stm32_ug2864hsweg01.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_timer.c) -endif() - -if(CONFIG_STM32_HCIUART) - if(CONFIG_BLUETOOTH_UART) - list(APPEND SRCS stm32_hciuart.c) - endif() -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_UNIQUEID) - list(APPEND SRCS stm32_uid.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(NOT CONFIG_STM32_ETHMAC) - if(CONFIG_NETDEVICES) - list(APPEND SRCS stm32_netinit.c) - endif() -endif() - -if(CONFIG_MMCSD_SPI) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_WL_GS2200M) - list(APPEND SRCS stm32_gs2200m.c) -endif() - -if(CONFIG_LCD_ST7789) - list(APPEND SRCS stm32_st7789.c) -endif() - -if(CONFIG_ADC_HX711) - list(APPEND SRCS stm32_hx711.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -# Set linker script based on build type -if(CONFIG_BUILD_PROTECTED) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/memory.ld" - "${NUTTX_BOARD_DIR}/scripts/kernel-space.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") -endif() - -# TODO:move this to appropriate arch/toolchain level -set_property( - GLOBAL APPEND - PROPERTY COMPILE_OPTIONS $<$:-fno-strict-aliasing - -fomit-frame-pointer>) - -# TODO: see where to put pic flags set_property(TARGET nuttx APPEND PROPERTY -# NUTTX_COMPILE_OPTIONS $<$>:-fpic -msingle-pic-base -# -mpic-register=r10>) - -# ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y) ARCHCFLAGS += -nostdlib -# -ffreestanding ARCHCXXFLAGS += -nostdlib -ffreestanding else ARCHCFLAGS += -# -funwind-tables ARCHCXXFLAGS += -fno-rtti -funwind-tables ifneq -# ($(CONFIG_DEBUG_NOOPT),y) ARCHOPTIMIZATION += -fno-strength-reduce endif endif - -if(CONFIG_UNWINDER_ARM) - set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_COMPILE_OPTIONS -funwind-tables) - set_property(GLOBAL APPEND PROPERTY COMPILE_OPTIONS -fno-strength-reduce) -endif() - -# TODO: nxflat NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = -# $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -# -no-check-sections LDNXFLATFLAGS = -e main -s 2048 - -# Loadable module definitions - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_MODULE_COMPILE_OPTIONS -mlong-calls) -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_MODULE_LINK_OPTIONS -r -e module_initialize -T - ${NUTTX_DIR}/libs/libc/elf/gnu-elf.ld) - -# ELF module definitions - -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_APP_COMPILE_OPTIONS -mlong-calls) -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_ELF_APP_LINK_OPTIONS -r -e main - -T${NUTTX_BOARD_DIR}/scripts/gnu-elf.ld) diff --git a/boards/arm/stm32/stm32f4discovery/src/Make.defs b/boards/arm/stm32/stm32f4discovery/src/Make.defs deleted file mode 100644 index d4a14a5c9f11b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/Make.defs +++ /dev/null @@ -1,195 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_AUDIO_CS43L22),y) -CSRCS += stm32_cs43l22.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) -CSRCS += stm32_usb.c -endif - -ifeq ($(CONFIG_LCD_ST7567),y) -CSRCS += stm32_st7567.c -endif - -ifeq ($(CONFIG_ENC28J60),y) -CSRCS += stm32_enc28j60.c -endif - -ifeq ($(CONFIG_NET_W5500),y) -CSRCS += stm32_w5500.c -endif - -ifeq ($(CONFIG_LPWAN_SX127X),y) -CSRCS += stm32_sx127x.c -endif - -ifeq ($(CONFIG_LCD_MAX7219),y) -CSRCS += stm32_max7219.c -endif - -ifeq ($(CONFIG_LCD_ST7032),y) -CSRCS += stm32_st7032.c -endif - -ifeq ($(CONFIG_PCA9635PW),y) -CSRCS += stm32_pca9635.c -endif - -ifeq ($(CONFIG_STM32_SDIO),y) -CSRCS += stm32_sdio.c -endif - -ifeq ($(CONFIG_STM32_ETHMAC),y) -CSRCS += stm32_ethernet.c -endif - -ifeq ($(CONFIG_LEDS_MAX7219),y) -CSRCS += stm32_max7219_leds.c -endif - -ifeq ($(CONFIG_RGBLED),y) -CSRCS += stm32_rgbled.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_CAPTURE),y) -CSRCS += stm32_capture.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CSRCS += stm32_pm.c -endif - -ifeq ($(CONFIG_PM_BUTTONS),y) -CSRCS += stm32_pmbuttons.c -endif - -ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CSRCS += stm32_idle.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CSRCS += stm32_extmem.c - -ifeq ($(CONFIG_LCD_SSD1289),y) -CSRCS += stm32_ssd1289.c -endif -endif - -ifeq ($(CONFIG_LCD_APA102),y) -CSRCS += stm32_apa102.c -endif - -ifeq ($(CONFIG_LCD_SSD1351),y) -CSRCS += stm32_ssd1351.c -endif - -ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) -CSRCS += stm32_ug2864ambag01.c -endif - -ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) -CSRCS += stm32_ug2864hsweg01.c -endif - -ifeq ($(CONFIG_TIMER),y) -CSRCS += stm32_timer.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -ifeq ($(CONFIG_BLUETOOTH_UART),y) -CSRCS += stm32_hciuart.c -endif -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) -CSRCS += stm32_uid.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifneq ($(CONFIG_STM32_ETHMAC),y) -ifeq ($(CONFIG_NETDEVICES),y) -CSRCS += stm32_netinit.c -endif -endif - -ifeq ($(CONFIG_MMCSD_SPI),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_WL_GS2200M),y) -CSRCS += stm32_gs2200m.c -endif - -ifeq ($(CONFIG_LCD_ST7789),y) -CSRCS += stm32_st7789.c -endif - -ifeq ($(CONFIG_INPUT_DJOYSTICK),y) - CSRCS += stm32_djoystick.c -endif - -ifeq ($(CONFIG_USBDEV_COMPOSITE),y) - CSRCS += stm32_composite.c -endif - -ifeq ($(CONFIG_ADC_HX711),y) -CSRCS += stm32_hx711.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c deleted file mode 100644 index 2f886258095fa..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c +++ /dev/null @@ -1,232 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The following definitions map the encoded LED setting to GPIO settings */ - -#define STM32F4_LED1 (1 << 0) -#define STM32F4_LED2 (1 << 1) -#define STM32F4_LED3 (1 << 2) -#define STM32F4_LED4 (1 << 3) - -#define ON_SETBITS_SHIFT (0) -#define ON_CLRBITS_SHIFT (4) -#define OFF_SETBITS_SHIFT (8) -#define OFF_CLRBITS_SHIFT (12) - -#define ON_BITS(v) ((v) & 0xff) -#define OFF_BITS(v) (((v) >> 8) & 0x0ff) -#define SETBITS(b) ((b) & 0x0f) -#define CLRBITS(b) (((b) >> 4) & 0x0f) - -#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) -#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) -#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) -#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) - -#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) -#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) -#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED3) << ON_SETBITS_SHIFT) -#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED4) << ON_CLRBITS_SHIFT) -#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) -#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_INIRQ_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) -#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) - -#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) -#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) - -#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) -#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -#define LED_PANIC_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) -#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) -#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) -#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const uint16_t g_ledbits[8] = -{ - (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), - - (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), - - (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), - - (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), - - (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), - - (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), - - (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), - - (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline void led_clrbits(unsigned int clrbits) -{ - if ((clrbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & STM32F4_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & STM32F4_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -static inline void led_setbits(unsigned int setbits) -{ - if ((setbits & STM32F4_LED1) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((setbits & STM32F4_LED2) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((setbits & STM32F4_LED3) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((setbits & STM32F4_LED4) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -static void led_setonoff(unsigned int bits) -{ - led_clrbits(CLRBITS(bits)); - led_setbits(SETBITS(bits)); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - led_setonoff(ON_BITS(g_ledbits[led])); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - led_setonoff(OFF_BITS(g_ledbits[led])); -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c deleted file mode 100644 index b99a443e08df1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "itm.h" - -#include "stm32.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - -#ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32_usbinitialize() has been - * brought into the build. Presumably either CONFIG_USBDEV or - * CONFIG_USBHOST is also selected. - */ - - if (stm32_usbinitialize) - { - stm32_usbinitialize(); - } -#endif - -#ifdef HAVE_NETMONITOR - /* Configure board resources to support networking. */ - - if (stm32_netinitialize) - { - stm32_netinitialize(); - } -#endif - -#ifdef CONFIG_ARCH_LEDS - /* Configure on-board LEDs if LED support has been selected. */ - - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c deleted file mode 100644 index a5dae40aba65f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c +++ /dev/null @@ -1,703 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#ifdef CONFIG_USBMONITOR -# include -#endif - -#include "stm32.h" -#include "stm32_romfs.h" - -#ifdef CONFIG_STM32_OTGFS -# include "stm32_usbhost.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#ifdef CONFIG_RNDIS -# include -#endif - -#ifdef CONFIG_SENSORS_APDS9960 -#include "stm32_apds9960.h" -#endif - -#ifdef CONFIG_SENSORS_MT6816 -#include "stm32_mt6816.h" -#endif - -#ifdef CONFIG_INPUT_MPR121_KEYPAD -#include "stm32_mpr121.h" -#endif - -#ifdef CONFIG_CL_MFRC522 -#include "stm32_mfrc522.h" -#endif - -#include "stm32f4discovery.h" - -/* Conditional logic in stm32f4discovery.h will determine if certain features - * are supported. Tests for these features need to be made after including - * stm32f4discovery.h. - */ - -#ifdef HAVE_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -/* The following are includes from board-common logic */ - -#ifdef CONFIG_SENSORS_BMP180 -#include "stm32_bmp180.h" -#endif - -#ifdef CONFIG_RTC_DS1307 -#include "stm32_ds1307.h" -#endif - -#ifdef CONFIG_SENSORS_MS56XX -#include "stm32_ms5611.h" -#endif - -#ifdef CONFIG_SENSORS_MAX6675 -#include "stm32_max6675.h" -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK -#include "stm32_nunchuck.h" -#endif - -#ifdef CONFIG_INPUT_SBUTTON -#include "board_sbutton.h" -#endif - -#ifdef CONFIG_INPUT_KMATRIX -#include "stm32_kmatrix_gpio.h" -#endif - -#ifdef CONFIG_INPUT_KMATRIX_I2C -#include "stm32_kmatrix_i2c.h" -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS -#include "stm32_zerocross.h" -#endif - -#ifdef CONFIG_SENSORS_QENCODER -#include "board_qencoder.h" -#endif - -#ifdef CONFIG_SENSORS_BH1750FVI -#include "stm32_bh1750.h" -#endif - -#ifdef CONFIG_LIS3DSH -#include "stm32_lis3dsh.h" -#endif - -#ifdef CONFIG_LCD_BACKPACK -#include "stm32_lcd_backpack.h" -#endif - -#ifdef CONFIG_SENSORS_MAX31855 -#include "stm32_max31855.h" -#endif - -#ifdef CONFIG_SENSORS_MLX90614 -#include "stm32_mlx90614.h" -#endif - -#ifdef CONFIG_SENSORS_XEN1210 -#include "stm32_xen1210.h" -#endif - -#ifdef CONFIG_USBADB -# include -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2c_register - * - * Description: - * Register one I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2c_register(int bus) -{ - struct i2c_master_s *i2c; - int ret; - - i2c = stm32_i2cbus_initialize(bus); - if (i2c == NULL) - { - syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); - } - else - { - ret = i2c_register(i2c, bus); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", - bus, ret); - stm32_i2cbus_uninitialize(i2c); - } - } -} -#endif - -/**************************************************************************** - * Name: stm32_i2ctool - * - * Description: - * Register I2C drivers for the I2C tool. - * - ****************************************************************************/ - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) -static void stm32_i2ctool(void) -{ - stm32_i2c_register(1); -#if 0 - stm32_i2c_register(1); - stm32_i2c_register(2); -#endif -} -#else -# define stm32_i2ctool() -#endif - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ -#ifdef HAVE_RTC_DRIVER - struct rtc_lowerhalf_s *lower; -#endif - int ret = OK; - -#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) - stm32_i2ctool(); -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Initialize the BMP180 pressure sensor. */ - - ret = board_bmp180_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_MS56XX - /* Initialize the MS5611 pressure sensor. */ - - ret = board_ms5611_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize MS5611, error %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_SENSORS_BH1750FVI - ret = board_bh1750_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_bh1750initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_ZEROCROSS - /* Configure the zero-crossing driver */ - - board_zerocross_initialize(0); -#endif - -#ifdef CONFIG_SENSORS_MT6816 - /* Initialize MT6816 as /dev/qe0 on SPI1 */ - - ret = board_mt6816_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_mt6816_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LEDS_MAX7219 - ret = stm32_max7219init("/dev/numdisp0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: max7219_leds_register failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_MPR121_KEYPAD - /* Initialize MPR121 using I2C1 bus to /dev/keypad0 */ - - ret = board_mpr121_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_mpr121_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_ST7032 - ret = stm32_st7032init("/dev/slcd0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: st7032_register failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_RGBLED - /* Configure the RGB LED driver */ - - stm32_rgbled_setup(); -#endif - -#if defined(CONFIG_PCA9635PW) - /* Initialize the PCA9635 chip */ - - ret = stm32_pca9635_initialize(); - if (ret < 0) - { - serr("ERROR: stm32_pca9635_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LCD_BACKPACK - /* slcd:0, i2c:1, rows=2, cols=16 */ - - ret = board_lcd_backpack_init(0, 1, 2, 16); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_SDIO - /* Initialize the SDIO block driver */ - - ret = stm32_sdio_initialize(); - if (ret != OK) - { - ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_MMCSD_SPI - /* Initialize the MMC/SD SPI driver (SPI2 is used) */ - - ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", - CONFIG_NSH_MMCSDMINOR, ret); - } -#endif - -#ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32_usbhost_initialize() starts a - * thread will monitor for USB connection and disconnection events. - */ - - ret = stm32_usbhost_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to initialize USB host: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_USBMONITOR - /* Start the USB Monitor */ - - ret = usbmonitor_start(); - if (ret != OK) - { - uerr("ERROR: Failed to start USB monitor: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - /* Initialize TIMER and register the TIMER device. */ - - ret = stm32_timer_driver_setup("/dev/timer0", CONFIG_STM32F4DISCO_TIMER); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAPTURE - /* Initialize Capture and register the Capture driver. */ - - ret = stm32_capture_setup("/dev/capture0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_capture_setup failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_DJOYSTICK - ret = stm32_djoy_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_KMATRIX - /* Initialize and register the keyboard matrix driver */ - - ret = board_kmatrix_initialize(CONFIG_INPUT_KMATRIX_DEVPATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_kmatrix_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_KMATRIX_I2C - /* Initialize and register the keyboard matrix driver via I2C expander */ - - ret = board_kmatrix_i2c_initialize("/dev/kbd0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_kmatrix_i2c_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_INPUT_NUNCHUCK - /* Register the Nunchuck driver */ - - ret = board_nunchuck_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MLX90614 - ret = board_mlx90614_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize MLX90614, error %d\n", ret); - return ret; - } -#endif - -#if defined(CONFIG_STM32_QE) && defined(CONFIG_SENSORS_QENCODER) - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32F4DISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - return ret; - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_SBUTTON - /* Register the Single Button Dual Action driver */ - - ret = board_sbutton_initialize(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_sbtn_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_APDS9960 - /* Register the APDS-9960 gesture sensor */ - - ret = board_apds9960_initialize(0, 1); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", - ret); - } -#endif - -#ifdef CONFIG_RTC_DS1307 - ret = board_ds1307_initialize(1); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize DS1307 RTC driver: %d\n", ret); - return ret; - } -#endif - -#ifdef HAVE_RTC_DRIVER - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (!lower) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - return -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - return ret; - } - } -#endif - -#ifdef HAVE_CS43L22 - /* Configure CS43L22 audio */ - - ret = stm32_cs43l22_initialize(1); - if (ret != OK) - { - serr("Failed to initialize CS43L22 audio: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX31855 - /* Register device 0 on spi channel 2 */ - - ret = board_max31855_initialize(0, 2); - if (ret < 0) - { - serr("ERROR: stm32_max31855initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MAX6675 - ret = board_max6675_initialize(0, 2); - if (ret < 0) - { - serr("ERROR: stm32_max6675initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_STM32_ROMFS - ret = stm32_romfs_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_SENSORS_XEN1210 - ret = board_xen1210_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: xen1210_archinitialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_LIS3DSH - /* Create a lis3dsh driver instance fitting the chip built into - * stm32f4discovery - */ - - ret = board_lis3dsh_initialize(0, 1); - if (ret < 0) - { - serr("ERROR: Failed to initialize LIS3DSH driver: %d\n", ret); - } -#endif - -#ifdef HAVE_HCIUART - ret = hciuart_dev_initialize(); - if (ret < 0) - { - serr("ERROR: Failed to initialize HCI UART driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) - uint8_t mac[6]; - mac[0] = 0xa0; /* TODO */ - mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; - mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; - mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; - mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; - mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; - usbdev_rndis_initialize(mac); -#endif - -#ifdef CONFIG_WL_GS2200M - ret = stm32_gs2200m_initialize("/dev/gs2200m", 3); - if (ret < 0) - { - serr("ERROR: Failed to initialize GS2200M: %d\n", ret); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - ret = stm32_lpwaninitialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver:" - " %d\n", ret); - } -#endif /* CONFIG_LPWAN_SX127X */ - -#ifdef CONFIG_USBADB - usbdev_adb_initialize(); -#endif - -#ifdef CONFIG_CL_MFRC522 - ret = stm32_mfrc522initialize("/dev/rfid0"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ADC_HX711 - ret = stm32_hx711_initialize(); - if (ret != OK) - { - aerr("ERROR: Failed to initialize hx711: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c b/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c deleted file mode 100644 index 8e2150389e12d..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F4 Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c b/boards/arm/stm32/stm32f4discovery/src/stm32_can.c deleted file mode 100644 index b919bdc52ee70..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c deleted file mode 100644 index 12531a29de342..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c +++ /dev/null @@ -1,349 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_composite.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_otgfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define COMPOSITE0_DEV (3) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void *g_mschandle; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_mscclassobject - * - * Description: - * If the mass storage class driver is part of composite device, then - * its instantiation and configuration is a multi-step, board-specific, - * process (See comments for usbmsc_configure below). In this case, - * board-specific logic must provide board_mscclassobject(). - * - * board_mscclassobject() is called from the composite driver. It must - * encapsulate the instantiation and configuration of the mass storage - * class and the return the mass storage device's class driver instance - * to the composite driver. - * - * Input Parameters: - * classdev - The location to return the mass storage class' device - * instance. - * - * Returned Value: - * 0 on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static int board_mscclassobject(int minor, - struct usbdev_devinfo_s *devinfo, - struct usbdevclass_driver_s **classdev) -{ - int ret; - - DEBUGASSERT(g_mschandle == NULL); - - /* Configure the mass storage device */ - - uinfo("Configuring with NLUNS=1\n"); - ret = usbmsc_configure(1, &g_mschandle); - if (ret < 0) - { - uerr("ERROR: usbmsc_configure failed: %d\n", -ret); - return ret; - } - - uinfo("MSC handle=%p\n", g_mschandle); - - /* Bind the LUN(s) */ - - uinfo("Bind LUN=0 to /dev/mmcsd0\n"); - ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); - if (ret < 0) - { - uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", - ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - return ret; - } - - /* Get the mass storage device's class object */ - - ret = usbmsc_classobject(g_mschandle, devinfo, classdev); - if (ret < 0) - { - uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); - usbmsc_uninitialize(g_mschandle); - g_mschandle = NULL; - } - - return ret; -} -#endif - -/**************************************************************************** - * Name: board_mscuninitialize - * - * Description: - * Un-initialize the USB storage class driver. - * This is just an application specific wrapper for usbmsc_unitialize() - * that is called form the composite device logic. - * - * Input Parameters: - * classdev - The class driver instance previously given to the composite - * driver by board_mscclassobject(). - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBMSC_COMPOSITE -static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) -{ - if (g_mschandle) - { - usbmsc_uninitialize(g_mschandle); - } - - g_mschandle = NULL; -} -#endif - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port for - * configuration 0. - * - * Input Parameters: - * port - The USB device port. - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -static void *board_composite0_connect(int port) -{ - struct composite_devdesc_s dev[COMPOSITE0_DEV]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; - int dev_idx = 0; - int epin = 1; - int epout = 1; - -#ifdef CONFIG_RNDIS_COMPOSITE - /* Configure the RNDIS USB device */ - - /* Ask the rndis driver to fill in the constants we didn't - * know here. - */ - - usbdev_rndis_get_composite_devdesc(&dev[dev_idx]); - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; - dev[dev_idx].minor = 0; - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - -#ifdef CONFIG_USBMSC_COMPOSITE - /* Configure the mass storage device device */ - - /* Ask the usbmsc driver to fill in the constants we didn't - * know here. - */ - - usbmsc_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the USBMSC class */ - - dev[dev_idx].classobject = board_mscclassobject; - dev[dev_idx].uninitialize = board_mscuninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - -#ifdef CONFIG_CDCACM_COMPOSITE - /* Configure the CDC/ACM device */ - - /* Ask the cdcacm driver to fill in the constants we didn't - * know here. - */ - - cdcacm_get_composite_devdesc(&dev[dev_idx]); - - /* Overwrite and correct some values... */ - - /* The callback functions for the CDC/ACM class */ - - dev[dev_idx].classobject = cdcacm_classobject; - dev[dev_idx].uninitialize = cdcacm_uninitialize; - - /* Interfaces */ - - dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[dev_idx].minor = 0; /* The minor interface number */ - - /* Strings */ - - dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ - - /* Endpoints */ - - dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++; - dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++; - - /* Count up the base numbers */ - - ifnobase += dev[dev_idx].devinfo.ninterfaces; - strbase += dev[dev_idx].devinfo.nstrings; - - dev_idx += 1; -#endif - - /* Sanity checks */ - - DEBUGASSERT(epin < STM32_NENDPOINTS); - DEBUGASSERT(epout < STM32_NENDPOINTS); - - return composite_initialize(composite_getdevdescs(), dev, dev_idx); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_composite_initialize - * - * Description: - * Perform architecture specific initialization of a composite USB device. - * - ****************************************************************************/ - -int board_composite_initialize(int port) -{ - return OK; -} - -/**************************************************************************** - * Name: board_composite_connect - * - * Description: - * Connect the USB composite device on the specified USB device port using - * the specified configuration. The interpretation of the configid is - * board specific. - * - * Input Parameters: - * port - The USB device port. - * configid - The USB composite configuration - * - * Returned Value: - * A non-NULL handle value is returned on success. NULL is returned on - * any failure. - * - ****************************************************************************/ - -void *board_composite_connect(int port, int configid) -{ - if (configid == 0) - { - return board_composite0_connect(port); - } - else - { - return NULL; - } -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c b/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c deleted file mode 100644 index dbbd33c9a4775..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c +++ /dev/null @@ -1,299 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_INPUT_DJOYSTICK - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of Joystick discretes 5-WAY */ - -#define DJOY_NGPIOS 5 - -/* Bitset of supported Joystick discretes */ - -#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ - DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower); -static djoy_buttonset_t - djoy_sample(const struct djoy_lowerhalf_s *lower); -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg); - -static void djoy_disable(void); -static int djoy_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each Olimex-P407 joystick "button." Index using - * DJOY_* definitions in include/nuttx/input/djoystick.h. - */ - -static const uint16_t g_joygpio[DJOY_NGPIOS] = -{ - GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER -}; - -/* Current interrupt handler and argument */ - -static djoy_interrupt_t g_djoyhandler; -static void *g_djoyarg; - -/* This is the discrete joystick lower half driver interface */ - -static const struct djoy_lowerhalf_s g_djoylower = -{ - .dl_supported = djoy_supported, - .dl_sample = djoy_sample, - .dl_enable = djoy_enable, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: djoy_supported - * - * Description: - * Return the set of buttons supported on the discrete joystick device - * - ****************************************************************************/ - -static djoy_buttonset_t - djoy_supported(const struct djoy_lowerhalf_s *lower) -{ - iinfo("Supported: %02x\n", DJOY_SUPPORTED); - return (djoy_buttonset_t)DJOY_SUPPORTED; -} - -/**************************************************************************** - * Name: djoy_sample - * - * Description: - * Return the current state of all discrete joystick buttons - * - ****************************************************************************/ - -static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) -{ - djoy_buttonset_t ret = 0; - int i; - - /* Read each joystick GPIO value */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - bool released = stm32_gpioread(g_joygpio[i]); - if (!released) - { - ret |= (1 << i); - } - } - - iinfo("Retuning: %02x\n", DJOY_SUPPORTED); - return ret; -} - -/**************************************************************************** - * Name: djoy_enable - * - * Description: - * Enable interrupts on the selected set of joystick buttons. And empty - * set will disable all interrupts. - * - ****************************************************************************/ - -static void djoy_enable(const struct djoy_lowerhalf_s *lower, - djoy_buttonset_t press, djoy_buttonset_t release, - djoy_interrupt_t handler, void *arg) -{ - irqstate_t flags; - djoy_buttonset_t either = press | release; - djoy_buttonset_t bit; - bool rising; - bool falling; - int i; - - /* Start with all interrupts disabled */ - - flags = enter_critical_section(); - djoy_disable(); - - iinfo("press: %02x release: %02x handler: %p arg: %p\n", - press, release, handler, arg); - - /* If no events are indicated or if no handler is provided, then this - * must really be a request to disable interrupts. - */ - - if (either && handler) - { - /* Save the new the handler and argument */ - - g_djoyhandler = handler; - g_djoyarg = arg; - - /* Check each GPIO. */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - /* Enable interrupts on each pin that has either a press or - * release event associated with it. - */ - - bit = (1 << i); - if ((either & bit) != 0) - { - /* Active low so a press corresponds to a falling edge and - * a release corresponds to a rising edge. - */ - - falling = ((press & bit) != 0); - rising = ((release & bit) != 0); - - iinfo("GPIO %d: rising: %d falling: %d\n", - i, rising, falling); - - stm32_gpiosetevent(g_joygpio[i], rising, falling, - true, djoy_interrupt, NULL); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: djoy_disable - * - * Description: - * Disable all joystick interrupts - * - ****************************************************************************/ - -static void djoy_disable(void) -{ - irqstate_t flags; - int i; - - /* Disable each joystick interrupt */ - - flags = enter_critical_section(); - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); - } - - leave_critical_section(flags); - - /* Nullify the handler and argument */ - - g_djoyhandler = NULL; - g_djoyarg = NULL; -} - -/**************************************************************************** - * Name: djoy_interrupt - * - * Description: - * Discrete joystick interrupt handler - * - ****************************************************************************/ - -static int djoy_interrupt(int irq, void *context, void *arg) -{ - DEBUGASSERT(g_djoyhandler); - if (g_djoyhandler) - { - g_djoyhandler(&g_djoylower, g_djoyarg); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_djoy_initialize - * - * Description: - * Initialize and register the discrete joystick driver - * - ****************************************************************************/ - -int stm32_djoy_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32_gpiosetevent(). - */ - - for (i = 0; i < DJOY_NGPIOS; i++) - { - stm32_configgpio(g_joygpio[i]); - } - - /* Make sure that all interrupts are disabled */ - - djoy_disable(); - - /* Register the joystick device as /dev/djoy0 */ - - return djoy_register("/dev/djoy0", &g_djoylower); -} - -#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c deleted file mode 100644 index 5e7994ce3d030..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* 2MBit SPI FLASH OR ENC28J60 - * - * -- ---- ------------ ----------------------------------------------------- - * PIN NAME SIGNAL NOTES - * -- ---- ------------ ----------------------------------------------------- - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_spi.h" - -#include "stm32f4discovery.h" - -#ifdef CONFIG_ENC28J60 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* ENC28J60 - * - * --- ------ -------------- ------------------------------------------------ - * PIN NAME SIGNAL NOTES - * --- ------ -------------- ------------------------------------------------ - * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, - * 10Mbit ENC28J60, SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, - * 10Mbit EN28J60 Reset - * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt - */ - -/* ENC28J60 is on SPI1 */ - -#ifndef CONFIG_STM32_SPI1 -# error "Need CONFIG_STM32_SPI1 in the configuration" -#endif - -/* SPI Assumptions **********************************************************/ - -#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ -#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_lower_s -{ - const struct enc_lower_s lower; /* Low-level MCU interface */ - xcpt_t handler; /* ENC28J60 interrupt handler */ - void *arg; /* Argument that accompanies the interrupt */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg); -static void up_enable(const struct enc_lower_s *lower); -static void up_disable(const struct enc_lower_s *lower); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The - * following structure provides an MCU-independent mechanixm for controlling - * the ENC28J60 GPIO interrupt. - */ - -static struct stm32_lower_s g_enclower = -{ - .lower = - { - .attach = up_attach, - .enable = up_enable, - .disable = up_disable - }, - .handler = NULL, - .arg = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: struct enc_lower_s methods - ****************************************************************************/ - -static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, - void *arg) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - /* Just save the handler for use when the interrupt is enabled */ - - priv->handler = handler; - priv->arg = arg; - return OK; -} - -static void up_enable(const struct enc_lower_s *lower) -{ - struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; - - DEBUGASSERT(priv->handler); - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - priv->handler, priv->arg); -} - -/* REVISIT: Since the interrupt is completely torn down, not just disabled, - * in interrupt requests that occurs while the interrupt is disabled will be - * lost. - */ - -static void up_disable(const struct enc_lower_s *lower) -{ - stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, - NULL, NULL); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -void arm_netinitialize(void) -{ - struct spi_dev_s *spi; - int ret; - - /* Assumptions: - * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in - * boot-up. - */ - - spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); - if (!spi) - { - nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO); - return; - } - - /* Take ENC28J60 out of reset (active low) */ - - stm32_gpiowrite(GPIO_ENC28J60_RESET, true); - - /* Bind the SPI port to the ENC28J60 driver */ - - ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); - if (ret < 0) - { - nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); - return; - } - - ninfo("Bound SPI port %d to ENC28J60 device %d\n", - ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); -} - -#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c deleted file mode 100644 index 49bb57a9d9553..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# warning "FSMC is not enabled" -#endif - -#if STM32_NGPIO_PORTS < 6 -# error "Required GPIO ports not enabled" -#endif - -#define STM32_FSMC_NADDRCONFIGS 26 -#define STM32_FSMC_NDATACONFIGS 16 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* GPIO configurations common to most external memories */ - -static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = -{ - GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, - GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, - GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, - GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, - GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, - GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, - GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, - GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, - GPIO_FSMC_A24, GPIO_FSMC_A25 -}; - -static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = -{ - GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, - GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, - GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, - GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, - GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, - GPIO_FSMC_D15 -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for external memory usage - * - ****************************************************************************/ - -void stm32_extmemgpios(const uint32_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Name: stm32_extmemaddr - * - * Description: - * Initialize address line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemaddr(int naddrs) -{ - stm32_extmemgpios(g_addressconfig, naddrs); -} - -/**************************************************************************** - * Name: stm32_extmemdata - * - * Description: - * Initialize data line GPIOs for external memory access - * - ****************************************************************************/ - -void stm32_extmemdata(int ndata) -{ - stm32_extmemgpios(g_dataconfig, ndata); -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c b/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c deleted file mode 100644 index 30ab88b32e4df..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value); -static int stm32_hx711_data_read(unsigned char minor); -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct hx711_lower_s g_lower = -{ - .data_read = stm32_hx711_data_read, - .clock_set = stm32_hx711_clock_set, - .data_irq = stm32_hx711_data_irq, - .cleanup = NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int stm32_hx711_clock_set(unsigned char minor, int value) -{ - UNUSED(minor); - - stm32_gpiowrite(HX711_CLK_PIN, value); - return OK; -} - -static int stm32_hx711_data_read(unsigned char minor) -{ - UNUSED(minor); - - return stm32_gpioread(HX711_DATA_PIN); -} - -static int stm32_hx711_data_irq(unsigned char minor, - xcpt_t handler, void *arg) -{ - UNUSED(minor); - - return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int stm32_hx711_initialize(void) -{ - int ret; - - stm32_configgpio(HX711_DATA_PIN); - stm32_configgpio(HX711_CLK_PIN); - - ret = hx711_register(0, &g_lower); - if (ret != 0) - { - aerr("ERROR: Failed to register hx711 device: %d\n", ret); - return -1; - } - - return OK; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c deleted file mode 100644 index f4b5bf5bbb847..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_idle.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32_rcc.h" -#include "stm32_exti.h" - -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Does the board support an IDLE LED to indicate that the board is in the - * IDLE state? - */ - -#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) -# define BEGIN_IDLE() board_autoled_on(LED_IDLE) -# define END_IDLE() board_autoled_off(LED_IDLE) -#else -# define BEGIN_IDLE() -# define END_IDLE() -#endif - -/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ - -#ifndef CONFIG_PM_ALARM_SEC -# define CONFIG_PM_ALARM_SEC 3 -#endif - -#ifndef CONFIG_PM_ALARM_NSEC -# define CONFIG_PM_ALARM_NSEC 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void); -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_idlepm - * - * Description: - * Perform IDLE state power management. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void stm32_idlepm(void) -{ - static enum pm_state_e oldstate = PM_NORMAL; - enum pm_state_e newstate; - irqstate_t flags; - int ret; - - /* Decide, which power saving level can be obtained */ - - newstate = pm_checkstate(PM_IDLE_DOMAIN); - - /* Check for state changes */ - - if (newstate != oldstate) - { - sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); - - flags = enter_critical_section(); - - /* Force the global state change */ - - ret = pm_changestate(PM_IDLE_DOMAIN, newstate); - if (ret < 0) - { - /* The new state change failed, revert to the preceding state */ - - pm_changestate(PM_IDLE_DOMAIN, oldstate); - - /* No state change... */ - - goto errout; - } - - /* Then perform board-specific, state-dependent logic here */ - - switch (newstate) - { - case PM_NORMAL: - { - } - break; - - case PM_IDLE: - { - } - break; - - case PM_STANDBY: - { -#ifdef CONFIG_RTC_ALARM - /* Disable RTC Alarm interrupt */ - -#warning "missing logic" - - /* Configure the RTC alarm to Auto Wake the system */ - -#warning "missing logic" - - /* The tv_nsec value must not exceed 1,000,000,000. That - * would be an invalid time. - */ - -#warning "missing logic" - - /* Set the alarm */ - -#warning "missing logic" -#endif - /* Call the STM32 stop mode */ - - stm32_pmstop(true); - - /* We have been re-awakened by some even: A button press? - * An alarm? Cancel any pending alarm and resume the normal - * operation. - */ - -#ifdef CONFIG_RTC_ALARM -#warning "missing logic" -#endif - /* Resume normal operation */ - - pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); - newstate = PM_NORMAL; - } - break; - - case PM_SLEEP: - { - /* We should not return from standby mode. The only way out - * of standby is via the reset path. - */ - - stm32_pmstandby(); - } - break; - - default: - break; - } - - /* Save the new state */ - - oldstate = newstate; - -errout: - leave_critical_section(flags); - } -} -#else -# define stm32_idlepm() -#endif - -/**************************************************************************** - * Name: up_alarmcb - * - * Description: - * RTC alarm service routine - * - ****************************************************************************/ - -#if 0 /* Not used */ -static void up_alarmcb(void) -{ - /* This alarm occurs because there wasn't any EXTI interrupt during the - * PM_STANDBY period. So just go to sleep. - */ - - pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - - /* Perform IDLE mode power management */ - - BEGIN_IDLE(); - stm32_idlepm(); - END_IDLE(); -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c b/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c deleted file mode 100644 index 6c4905055d75c..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_NX_LCDDRIVER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LCD_SPI_PORTNO 1 /* On SPI1 */ - -#ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct spi_dev_s *g_spidev; -struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); - - if (g_spidev == NULL) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - g_lcddev = max7219_initialize(g_spidev, lcddev); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); - } - else - { - lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); - - return g_lcddev; - } - - return NULL; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* TO-FIX */ -} - -#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c b/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c deleted file mode 100644 index 980b52d497b62..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spi1register - * - * Description: - * Registers media change callback - ****************************************************************************/ - -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg) -{ - /* TODO: media change callback */ - - return OK; -} - -/**************************************************************************** - * Name: stm32_mmcsd_initialize - * - * Description: - * Initialize SPI-based SD card and card detect thread. - ****************************************************************************/ - -int stm32_mmcsd_initialize(int port, int minor) -{ - struct spi_dev_s *spi; - int rv; - - stm32_configgpio(GPIO_MMCSD_NCD); /* Assign SD_DET */ - stm32_configgpio(GPIO_MMCSD_NSS); /* Assign CS */ - stm32_gpiowrite(GPIO_MMCSD_NSS, 1); /* Ensure the CS is inactive */ - - mcinfo("INFO: Initializing mmcsd port %d minor %d\n", - port, minor); - - spi = stm32_spibus_initialize(port); - if (spi == NULL) - { - mcerr("ERROR: Failed to initialize SPI port %d\n", port); - return -ENODEV; - } - - rv = mmcsd_spislotinitialize(minor, minor, spi); - if (rv < 0) - { - mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", - port, minor); - return rv; - } - - spiinfo("INFO: mmcsd card has been initialized successfully\n"); - return OK; -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c b/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c deleted file mode 100644 index f6a8f0af711c1..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm_netinitialize - ****************************************************************************/ - -#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) -void arm_netinitialize(void) -{ -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c deleted file mode 100644 index d9ac5804f38b8..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c +++ /dev/null @@ -1,75 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "arm_internal.h" -#include "stm32_pm.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pminitialize - * - * Description: - * This function is called by MCU-specific logic at power-on reset in - * order to provide one-time initialization the power management subsystem. - * This function must be called *very* early in the initialization sequence - * *before* any other device drivers are initialized (since they may - * attempt to register with the power management subsystem). - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void arm_pminitialize(void) -{ - /* Initialize the NuttX power management subsystem proper */ - - pm_initialize(); - -#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - /* Initialize the buttons to wake up the system from low power modes */ - - stm32_pm_buttons(); -#endif - - /* Initialize the LED PM */ - - stm32_led_pminitialize(); -} - -#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c deleted file mode 100644 index 2d67dc8dd9c3b..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "nvic.h" -#include "stm32_pwr.h" -#include "stm32_pm.h" -#include "stm32f4discovery.h" - -#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_BUTTONS -# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_ARCH_IRQBUTTONS -# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" -#endif - -#ifndef CONFIG_PM_BUTTON_ACTIVITY -# define CONFIG_PM_BUTTON_ACTIVITY 10 -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, void *context, void *arg); -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: button_handler - * - * Description: - * Handle a button wake-up interrupt - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -static int button_handler(int irq, void *context, void *arg) -{ - /* At this point the MCU should have already awakened. The state - * change will be handled in the IDLE loop when the system is re-awakened - * The button interrupt handler should be totally ignorant of the PM - * activities and should report button activity as if nothing - * special happened. - */ - - pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); - return OK; -} -#endif /* CONFIG_ARCH_IRQBUTTONS */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pm_buttons - * - * Description: - * Configure the user button of the STM32f4discovery board as EXTI, - * so it is able to wakeup the MCU from the PM_STANDBY mode - * - ****************************************************************************/ - -void stm32_pm_buttons(void) -{ - /* Initialize the button GPIOs */ - - board_button_initialize(); - -#ifdef CONFIG_ARCH_IRQBUTTONS - board_button_irq(0, button_handler, NULL); -#endif -} - -#endif /* CONFIG_PM && CONFIG_ARCH_IDLE_CUSTOM && CONFIG_PM_BUTTONS)*/ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c deleted file mode 100644 index 089b3a8c74d68..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c +++ /dev/null @@ -1,125 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32f4discovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. This pin is used by - * FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if !defined(CONFIG_STM32_TIM4_CHANNEL) || CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); - if (!pwm) - { - aerr("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c deleted file mode 100644 index 9edc36b2a3017..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c deleted file mode 100644 index 983d11293bcab..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c +++ /dev/null @@ -1,173 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32f4discovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_RGBLED 1 - -#ifndef CONFIG_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM3 -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM1_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM2_PWM -# undef HAVE_RGBLED -#endif - -#ifndef CONFIG_STM32_TIM3_PWM -# undef HAVE_RGBLED -#endif - -#ifdef HAVE_RGBLED - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rgbled_setup - * - * Description: - * Configure the RGB LED. - * - ****************************************************************************/ - -int stm32_rgbled_setup(void) -{ - static bool initialized = false; - struct pwm_lowerhalf_s *ledr; - struct pwm_lowerhalf_s *ledg; - struct pwm_lowerhalf_s *ledb; - struct pwm_info_s info; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledr = stm32_pwminitialize(1); - if (!ledr) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); - return -ENODEV; - } - - /* Define frequency and duty cycle */ - - info.frequency = 100; - info.channels[0].duty = 0; - - /* Initialize LED R */ - - ledr->ops->setup(ledr); - ledr->ops->start(ledr, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledg = stm32_pwminitialize(2); - if (!ledg) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - ledb = stm32_pwminitialize(3); - if (!ledb) - { - lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); - - /* Register the RGB LED diver at "/dev/rgbled0" */ - - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, - 1, CONFIG_STM32_TIM2_CHANNEL, - CONFIG_STM32_TIM3_CHANNEL); - if (ret < 0) - { - lederr("ERROR: rgbled_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#else -# error "HAVE_RGBLED is undefined" -#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h deleted file mode 100644 index 8e47a501f46d4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c deleted file mode 100644 index 7f56897a821c6..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c - * This file provides contents of an optional ROMFS volume, mounted at boot. - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c deleted file mode 100644 index 9a604e0817c5e..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef HAVE_SDIO - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Card detections requires card support and a card detection GPIO */ - -#define HAVE_NCD 1 -#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) -# undef HAVE_NCD -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct sdio_dev_s *g_sdio_dev; -#ifdef HAVE_NCD -static bool g_sd_inserted; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ncd_interrupt - * - * Description: - * Card detect interrupt handler. - * - ****************************************************************************/ - -#ifdef HAVE_NCD -static int stm32_ncd_interrupt(int irq, void *context, void *arg) -{ - bool present; - - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) - { - sdio_mediachange(g_sdio_dev, present); - g_sd_inserted = present; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdio_initialize - * - * Description: - * Initialize SDIO-based MMC/SD card support - * - ****************************************************************************/ - -int stm32_sdio_initialize(void) -{ - int ret; - -#ifdef HAVE_NCD - /* Configure the card detect GPIO */ - - stm32_configgpio(GPIO_SDIO_NCD); - - /* Register an interrupt handler for the card detect pin */ - - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, - stm32_ncd_interrupt, NULL); -#endif - - /* Mount the SDIO-based MMC/SD block driver */ - - /* First, get an instance of the SDIO interface */ - - finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); - - g_sdio_dev = sdio_initialize(SDIO_SLOTNO); - if (!g_sdio_dev) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); - return -ENODEV; - } - - /* Now bind the SDIO interface to the MMC/SD driver */ - - finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); - - ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); - if (ret != OK) - { - ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); - return ret; - } - - finfo("Successfully bound SDIO to the MMC/SD driver\n"); - -#ifdef HAVE_NCD - /* Use SD card detect pin to check if a card is g_sd_inserted */ - - g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); - finfo("Card detect : %d\n", g_sd_inserted); - - sdio_mediachange(g_sdio_dev, g_sd_inserted); -#else - /* Assume that the SD card is inserted. What choice do we have? */ - - sdio_mediachange(g_sdio_dev, true); -#endif - - return OK; -} - -#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c deleted file mode 100644 index a1026359b9485..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c +++ /dev/null @@ -1,376 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" - -#include "stm32f4discovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32f4discovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_ENC28J60 - stm32_configgpio(GPIO_ENC28J60_CS); - stm32_configgpio(GPIO_ENC28J60_RESET); - stm32_configgpio(GPIO_ENC28J60_INTR); -#endif - -#ifdef CONFIG_NET_W5500 - stm32_configgpio(GPIO_W5500_CS); - stm32_configgpio(GPIO_W5500_RESET); - stm32_configgpio(GPIO_W5500_INTR); -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_LIS3MDL) - stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) - stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ -#endif - -#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MT6816) - stm32_configgpio(GPIO_CS_MT6816); -#endif - -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX31855) - stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ -#endif -#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) - stm32_configgpio(GPIO_MAX7219_CS); /* MAX7219 chip select */ -#endif -#ifdef CONFIG_LPWAN_SX127X - stm32_configgpio(GPIO_SX127X_CS); /* SX127x chip select */ -#endif - -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7567) - stm32_configgpio(STM32_LCD_CS); /* ST7567/ST7789 chip select */ -#endif -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX6675) - stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ -#endif -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ -# if defined(CONFIG_LCD_UG2864AMBAG01) - stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) - stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ -# endif -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use - * this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board - * is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#ifdef CONFIG_ENC28J60 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); - } -#endif - -#ifdef CONFIG_NET_W5500 - if (devid == SPIDEV_ETHERNET(0)) - { - /* Set the GPIO low to select and high to de-select */ - - stm32_gpiowrite(GPIO_W5500_CS, !selected); - } -#endif - -#ifdef CONFIG_LPWAN_SX127X - if (devid == SPIDEV_LPWAN(0)) - { - stm32_gpiowrite(GPIO_SX127X_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(STM32_LCD_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_MAX7219_CS, !selected); - } -#endif - -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_OLED_CS, !selected); - } -#endif - -#if defined (CONFIG_SENSORS_LIS3MDL) - if (devid == SPIDEV_ACCELEROMETER(0)) - { - stm32_gpiowrite(GPIO_CS_MEMS, !selected); - } -#endif - -#if defined (CONFIG_SENSORS_MT6816) - if (devid == SPIDEV_MAG_ENCODER(0)) - { - stm32_gpiowrite(GPIO_CS_MT6816, !selected); - } -#endif - -#if defined(CONFIG_CL_MFRC522) - if (devid == SPIDEV_CONTACTLESS(0)) - { - stm32_gpiowrite(GPIO_CS_MFRC522, !selected); - } -#endif -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t status = 0; - -#ifdef CONFIG_LPWAN_SX127X - if (devid == SPIDEV_LPWAN(0)) - { - status |= SPI_STATUS_PRESENT; - } -#endif - - return status; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_SENSORS_MAX31855) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX31855_CS, !selected); - } -#endif - -#if defined(CONFIG_SENSORS_MAX6675) - if (devid == SPIDEV_TEMPERATURE(0)) - { - stm32_gpiowrite(GPIO_MAX6675_CS, !selected); - } -#endif - -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - stm32_gpiowrite(GPIO_MMCSD_NSS, !selected); - } -#endif -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - uint8_t ret = 0; -#if defined(CONFIG_MMCSD_SPI) - if (devid == SPIDEV_MMCSD(0)) - { - /* Note: SD_DET is pulled high when there's no SD card present. */ - - ret = stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; - } -#endif - - return ret; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected) -{ - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : - "de-assert"); - -#if defined(CONFIG_WL_GS2200M) - if (devid == SPIDEV_WIRELESS(0)) - { - stm32_gpiowrite(GPIO_GS2200M_CS, !selected); - } -#endif -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) - if (devid == SPIDEV_DISPLAY(0)) - { - /* This is the Data/Command control pad which determines whether the - * data bits are data or a command. - */ - - stm32_gpiowrite(STM32_LCD_RS, !cmd); - - return OK; - } -#endif - -#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ - defined(CONFIG_LCD_SSD1351) - if (devid == SPIDEV_DISPLAY(0)) - { - /* "This is the Data/Command control pad which determines whether the - * data bits are data or a command. - * - * A0 = "H": the inputs at D0 to D7 are treated as display data. - * A0 = "L": the inputs at D0 to D7 are transferred to the command - * registers." - */ - -# if defined(CONFIG_LCD_UG2864AMBAG01) - stm32_gpiowrite(GPIO_OLED_A0, !cmd); -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) - stm32_gpiowrite(GPIO_OLED_DC, !cmd); -# endif - return OK; - } -#endif - - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c deleted file mode 100644 index 9f51dc3545f9f..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c +++ /dev/null @@ -1,390 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* STM32F4Discovery LCD Hardware Definitions ********************************/ - -/* LCD /CS is CE1 == NOR/SRAM Bank 1 - * - * Bank 1 = 0x60000000 | 0x00000000 - * Bank 2 = 0x60000000 | 0x04000000 - * Bank 3 = 0x60000000 | 0x08000000 - * Bank 4 = 0x60000000 | 0x0c000000 - * - * FSMC address bit 16 is used to distinguish command and data. - * FSMC address bits 0-24 correspond to ARM address bits 1-25. - */ - -#define STM32_LCDBASE ((uintptr_t)(0x60000000 | 0x00000000)) -#define LCD_INDEX (STM32_LCDBASE) -#define LCD_DATA (STM32_LCDBASE + 0x00020000) - -/* SRAM pin definitions */ - -#define LCD_NADDRLINES 1 /* A16 */ -#define LCD_NDATALINES 16 /* D0-15 */ - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* LCD pin mapping - * MAPPING TO STM32 F4: - * - * ---------------- ------------- ---------------------------------- - * STM32 FUNCTION LCD PIN STM32F4Discovery PIN - * ---------------- ------------- ---------------------------------- - * FSMC_D0 D0 pin 4 PD14 P1 pin 46 Conflict (Note 1) - * FSMC_D1 D1 pin 3 PD15 P1 pin 47 Conflict (Note 2) - * FSMC_D2 D2 pin 6 PD0 P2 pin 36 Free I/O - * FSMC_D3 D3 pin 5 PD1 P2 pin 33 Free I/O - * FSMC_D4 D4 pin 8 PE7 P1 pin 25 Free I/O - * FSMC_D5 D5 pin 7 PE8 P1 pin 26 Free I/O - * FSMC_D6 D6 pin 10 PE9 P1 pin 27 Free I/O - * FSMC_D7 D7 pin 9 PE10 P1 pin 28 Free I/O - * FSMC_D8 D8 pin 12 PE11 P1 pin 29 Free I/O - * FSMC_D9 D9 pin 11 PE12 P1 pin 30 Free I/O - * FSMC_D10 D10 pin 14 PE13 P1 pin 31 Free I/O - * FSMC_D11 D11 pin 13 PE14 P1 pin 32 Free I/O - * FSMC_D12 D12 pin 16 PE15 P1 pin 33 Free I/O - * FSMC_D13 D13 pin 15 PD8 P1 pin 40 Free I/O - * FSMC_D14 D14 pin 18 PD9 P1 pin 41 Free I/O - * FSMC_D15 D15 pin 17 PD10 P1 pin 42 Free I/O - * FSMC_A16 RS pin 19 PD11 P1 pin 27 Free I/O - * FSMC_NE1 ~CS pin 10 PD7 P2 pin 27 Free I/O - * FSMC_NWE ~WR pin 22 PD5 P2 pin 29 Conflict (Note 3) - * FSMC_NOE ~RD pin 21 PD4 P2 pin 32 Conflict (Note 4) - * PC6 RESET pin 24 PC6 P2 pin 47 Free I/O - * ---------------- ------------- ---------------------------------- - * - * 1 Used for the RED LED - * 2 Used for the BLUE LED - * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to - * use for the parallel interface if PC0 is held high (or floating). - * PC0 enables the STMPS2141STR IC power switch that drives the OTG FS - * host VBUS. - * 4 Also the reset pin for the CS43L22 audio Codec. - */ - -#define GPIO_LCD_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6) - -/* GPIO configurations unique to the LCD */ - -static const uint32_t g_lcdconfig[] = -{ - /* PC6(RESET), FSMC_A16, FSMC_NOE, FSMC_NWE, and FSMC_NE1 */ - - GPIO_LCD_RESET, GPIO_FSMC_A16, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE1 -}; -#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) - -/* This is the driver state structure - * (there is no retained state information) - */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ -#warning "Missing logic" -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize to the LCD - * - ****************************************************************************/ - -void stm32_selectlcd(void) -{ - /* Configure GPIO pins */ - - stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ - stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Color LCD configuration (LCD configured as follow): - * - * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. - * - Extended Mode = Disable "FSMC_BCR_EXTMOD" - * - Memory Type = SRAM "FSMC_BCR_SRAM" - * - Data Width = 16bit "FSMC_BCR_MWID16" - * - Write Operation = Enable "FSMC_BCR_WREN" - * - Asynchronous Wait = Disable - */ - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | - FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with - * the power setting at 0 (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Reset the LCD (active low) */ - - stm32_gpiowrite(GPIO_LCD_RESET, false); - up_mdelay(5); - stm32_gpiowrite(GPIO_LCD_RESET, true); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Clear the display (setting it to the color 0=black) */ - -#if 0 /* Already done in the driver */ - ssd1289_clear(g_ssd1289drvr, 0); -#endif - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c deleted file mode 100644 index 6fc6f5a3b9c59..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32_spi.h" - -#include "stm32f4discovery.h" - -#ifdef CONFIG_LCD_SSD1351 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The pin configurations here require that SPI1 is selected */ - -#ifndef CONFIG_STM32_SPI1 -# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" -#endif - -#ifndef CONFIG_SSD1351_SPI4WIRE -# error "The configuration requires the SPI 4-wire interface" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_graphics_setup - * - * Description: - * Called by NX initialization logic to configure the OLED. - * - ****************************************************************************/ - -struct lcd_dev_s *board_graphics_setup(unsigned int devno) -{ - struct spi_dev_s *spi; - struct lcd_dev_s *dev; - - /* Configure the OLED GPIOs. This initial configuration is RESET low, - * putting the OLED into reset state. - */ - - stm32_configgpio(GPIO_OLED_RESET); - - /* Wait a bit then release the OLED from the reset state */ - - up_mdelay(20); - stm32_gpiowrite(GPIO_OLED_RESET, true); - - /* Get the SPI1 port interface */ - - spi = stm32_spibus_initialize(1); - if (spi == NULL) - { - lcderr("ERROR: Failed to initialize SPI port 1\n"); - } - else - { - /* Bind the SPI port to the OLED */ - - dev = ssd1351_initialize(spi, devno); - if (dev == NULL) - { - lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); - } - else - { - lcdinfo("Bound SPI port 1 to OLED %d\n", devno); - - /* And turn the OLED on */ - - dev->setpower(dev, LCD_FULL_ON); - return dev; - } - } - - return NULL; -} - -#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c deleted file mode 100644 index e9f274bfbcaab..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_timer.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -#include "stm32_tim.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_TIMER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_driver_setup - * - * Description: - * Configure the timer driver. - * - * Input Parameters: - * devpath - The full path to the timer device. - * This should be of the form /dev/timer0 - * timer - The timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_driver_setup(const char *devpath, int timer) -{ - return stm32_timer_initialize(devpath, timer); -} - -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c b/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c deleted file mode 100644 index 32f51da6faaed..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include "stm32_uid.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - stm32_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c deleted file mode 100644 index b8f70554c4899..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c +++ /dev/null @@ -1,340 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usb.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_otgfs.h" -#include "stm32f4discovery.h" - -#ifdef CONFIG_STM32_OTGFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) -# define HAVE_USB 1 -#else -# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" -# undef HAVE_USB -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO -# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 -#endif - -#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE -# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static struct usbhost_connection_s *g_usbconn; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: usbhost_waiter - * - * Description: - * Wait for USB devices to be connected. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -static int usbhost_waiter(int argc, char *argv[]) -{ - struct usbhost_hubport_s *hport; - - uinfo("Running\n"); - for (; ; ) - { - /* Wait for the device to change state */ - - DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); - uinfo("%s\n", hport->connected ? "connected" : "disconnected"); - - /* Did we just become connected? */ - - if (hport->connected) - { - /* Yes.. enumerate the newly connected device */ - - CONN_ENUMERATE(g_usbconn, hport); - } - } - - /* Keep the compiler from complaining */ - - return 0; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbinitialize - * - * Description: - * Called from stm32_usbinitialize very early in initialization to setup - * USB-related GPIO pins for the STM32F4Discovery board. - * - ****************************************************************************/ - -void stm32_usbinitialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - - /* Configure the OTG FS VBUS sensing GPIO, - * Power On, and Overcurrent GPIOs - */ - -#ifdef CONFIG_STM32_OTGFS - stm32_configgpio(GPIO_OTGFS_VBUS); - stm32_configgpio(GPIO_OTGFS_PWRON); - stm32_configgpio(GPIO_OTGFS_OVER); -#endif -} - -/**************************************************************************** - * Name: stm32_usbhost_initialize - * - * Description: - * Called at application startup time to initialize the USB host - * functionality. - * This function will start a thread that will monitor for device - * connection/disconnection events. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_usbhost_initialize(void) -{ - int ret; - - /* First, register all of the class drivers needed to support the drivers - * that we care about: - */ - - uinfo("Register class drivers\n"); - -#ifdef CONFIG_USBHOST_HUB - /* Initialize USB hub class support */ - - ret = usbhost_hub_initialize(); - if (ret < 0) - { - uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_MSC - /* Register the USB mass storage class class */ - - ret = usbhost_msc_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the mass storage class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_CDCACM - /* Register the CDC/ACM serial class */ - - ret = usbhost_cdcacm_initialize(); - if (ret != OK) - { - uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); - } -#endif - -#ifdef CONFIG_USBHOST_HIDKBD - /* Initialize the HID keyboard class */ - - ret = usbhost_kbdinit(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID keyboard class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_HIDMOUSE - /* Initialize the HID mouse class */ - - ret = usbhost_mouse_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the HID mouse class\n"); - } -#endif - -#ifdef CONFIG_USBHOST_XBOXCONTROLLER - /* Initialize the HID mouse class */ - - ret = usbhost_xboxcontroller_init(); - if (ret != OK) - { - uerr("ERROR: Failed to register the XBox Controller class\n"); - } -#endif - - /* Then get an instance of the USB host interface */ - - uinfo("Initialize USB host\n"); - g_usbconn = stm32_otgfshost_initialize(0); - if (g_usbconn) - { - /* Start a thread to handle device connection. */ - - uinfo("Start usbhost_waiter\n"); - - ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, - CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, - usbhost_waiter, NULL); - return ret < 0 ? -ENOEXEC : OK; - } - - return -ENODEV; -} -#endif - -/**************************************************************************** - * Name: stm32_usbhost_vbusdrive - * - * Description: - * Enable/disable driving of VBUS 5V output. This function must be - * provided be each platform that implements the STM32 OTG FS host - * interface - * - * "On-chip 5 V VBUS generation is not supported. For this reason, a - * charge pump or, if 5 V are available on the application board, a - * basic power switch, must be added externally to drive the 5 V VBUS - * line. The external charge pump can be driven by any GPIO output. - * When the application decides to power on VBUS using the chosen GPIO, - * it must also set the port power bit in the host port control and - * status register (PPWR bit in OTG_FS_HPRT). - * - * "The application uses this field to control power to this port, - * and the core clears this bit on an overcurrent condition." - * - * Input Parameters: - * iface - For future growth to handle multiple USB host interface. - * Should be zero. - * enable - true: enable VBUS power; false: disable VBUS power - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -void stm32_usbhost_vbusdrive(int iface, bool enable) -{ - DEBUGASSERT(iface == 0); - - if (enable) - { - /* Enable the Power Switch by driving the enable pin low */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, false); - } - else - { - /* Disable the Power Switch by driving the enable pin high */ - - stm32_gpiowrite(GPIO_OTGFS_PWRON, true); - } -} -#endif - -/**************************************************************************** - * Name: stm32_setup_overcurrent - * - * Description: - * Setup to receive an interrupt-level callback if an overcurrent - * condition is detected. - * - * Input Parameters: - * handler - New overcurrent interrupt handler - * arg - The argument provided for the interrupt handler - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise, a negated errno value - * is returned to indicate the nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_USBHOST -int stm32_setup_overcurrent(xcpt_t handler, void *arg) -{ - return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV - * driver is used. This function is called whenever the USB enters or - * leaves suspend mode. This is an opportunity for the board logic to - * shutdown clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -#ifdef CONFIG_USBDEV -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} -#endif - -#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c deleted file mode 100644 index d4afdc4e95ebf..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c +++ /dev/null @@ -1,71 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization of the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#ifndef CONFIG_NSH_BUILTIN_APPS - return stm32_mmcsd_initialize(2, CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c b/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c deleted file mode 100644 index c2fc1756428d4..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32f4discovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This array maps an LED number to GPIO pin configuration */ - -static uint32_t g_ledcfg[BOARD_NLEDS] = -{ - GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* LED Power Management */ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_PM -static struct pm_callback_s g_ledscb = -{ - .notify = led_pm_notify, - .prepare = led_pm_prepare, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_pm_notify - * - * Description: - * Notify the driver of new power state. This callback is called after - * all drivers have had the opportunity to prepare for the new power state. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static void led_pm_notify(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - switch (pmstate) - { - case PM_NORMAL: - { - /* Restore normal LEDs operation */ - } - break; - - case PM_IDLE: - { - /* Entering IDLE mode - Turn leds off */ - } - break; - - case PM_STANDBY: - { - /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } - break; - - case PM_SLEEP: - { - /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } - break; - - default: - { - /* Should not get here */ - } - break; - } -} -#endif - -/**************************************************************************** - * Name: led_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a warning - * that the system is about to enter into a new power state. The driver - * should begin whatever operations that may be required to enter power - * state. The driver may abort the state change mode by returning a - * non-zero value from the callback function. - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int led_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - /* No preparation to change power modes is required by the LEDs driver. - * We always accept the state change by returning OK. - */ - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-4 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - if ((unsigned)led < BOARD_NLEDS) - { - stm32_gpiowrite(g_ledcfg[led], ledon); - } -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); - stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); - stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); - stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); -} - -/**************************************************************************** - * Name: stm32_led_pminitialize - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_led_pminitialize(void) -{ - /* Register to receive power management callbacks */ - - int ret = pm_register(&g_ledscb); - if (ret != OK) - { - board_autoled_on(LED_ASSERTION); - } -} -#endif /* CONFIG_PM */ - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt deleted file mode 100644 index bde3559ad0c87..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig deleted file mode 100644 index 7348760dcdcd8..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -# CONFIG_SERIAL is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32ldiscovery" -CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32L1=y -CONFIG_ARCH_CHIP_STM32L152RB=y -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_BUILTIN=y -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_ENABLE_ALL_SIGNALS=y -CONFIG_EXAMPLES_CHRONO=y -CONFIG_EXAMPLES_SLCD=y -CONFIG_FILE_STREAM=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LIBC_SLCDCODEC=y -CONFIG_LWL_CONSOLE=y -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=16384 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_RTC_DATETIME=y -CONFIG_SCHED_WAITPID=y -CONFIG_SLCD=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_LCD=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig deleted file mode 100644 index c486a692f0f5b..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_HEXDUMP is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32ldiscovery" -CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32L1=y -CONFIG_ARCH_CHIP_STM32L152RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2796 -CONFIG_DEFAULT_SMALL=y -CONFIG_DISABLE_MOUNTPOINT=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=1536 -CONFIG_INTELHEX_BINARY=y -CONFIG_MM_SMALL=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_FILEIOSIZE=64 -CONFIG_NUNGET_CHARS=0 -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PTHREAD_STACK_DEFAULT=1536 -CONFIG_RAM_SIZE=16384 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=19 -CONFIG_START_MONTH=5 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_SW_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_BAUD=57600 -CONFIG_USART1_RXBUFSIZE=64 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=64 diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32/stm32ldiscovery/include/board.h deleted file mode 100644 index a36765cc66e2a..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ /dev/null @@ -1,307 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Four different clock sources can be used to drive the system clock - * (SYSCLK): - * - * - HSI high-speed internal oscillator clock - * Generated from an internal 16 MHz RC oscillator - * - HSE high-speed external oscillator clock - * Normally driven by an external crystal (X3). However, this crystal is - * not fitted on the STM32L-Discovery board. - * - PLL clock - * - MSI multispeed internal oscillator clock - * The MSI clock signal is generated from an internal RC oscillator. - * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, - * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and - * 4.194 MHz. - * - * The devices have the following two secondary clock sources - * - LSI low-speed internal RC clock - * Drives the watchdog and RTC. Approximately 37KHz - * - LSE low-speed external oscillator clock - * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. - */ - -#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ - -#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ -#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL -#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ -#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ -#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ - -/* PLL Configuration - * - * - PLL source is HSI -> 16MHz input (nominal) - * - PLL multiplier is 6 -> 96MHz PLL VCO clock output (for USB) - * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output - * - * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz - * - * USB/SDIO: - * If the USB or SDIO interface is used in the application, the PLL VCO - * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 - * MHz frequency. This is required to provide a 48 MHz clock to the USB or - * SDIO (SDIOCLK or USBCLK = PLLVCO/2). - * SYSCLK - * The system clock is derived from the PLL VCO divided by the output - * division factor. - * Limitations: - * 96 MHz as PLLVCO when the product is in range 1 (1.8V), - * 48 MHz as PLLVCO when the product is in range 2 (1.5V), - * 24 MHz when the product is in range 3 (1.2V). - * Output division to avoid exceeding 32 MHz as SYSCLK. - * The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - */ - -#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ -#ifdef CONFIG_STM32_USB -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ -# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ -# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ -#else -# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ -# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ -# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ -#endif - -/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO - * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). - */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32_USB -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequency is 96MHz/PLLDIV = 32MHz */ -#else -# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequency is 64MHz/PLLDIV = 32MHz */ -#endif - -/* AHB clock (HCLK) is SYSCLK (32MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY -#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB2 timers 9, 10, and 11 will receive PCLK2. */ - -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) - -/* APB1 clock (PCLK1) is HCLK (32MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* APB1 timers 2-7 will receive PCLK1 */ - -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) - -/* LED definitions **********************************************************/ - -/* The STM32L-Discovery board has four LEDs. Two of these are controlled by - * logic on the board and are not available for software control: - * - * LD1 COM: LD2 default status is red. LD2 turns to green to indicate - * that communications are in progress between the PC and the - * ST-LINK/V2. - * LD2 PWR: Red LED indicates that the board is powered. - * - * And two LEDs can be controlled by software: - * - * User LD3: Green LED is a user LED connected to the I/O PB7 of the - * STM32L152 MCU. - * User LD4: Blue LED is a user LED connected to the I/O PB6 of the - * STM32L152 MCU. - * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in - * any way. The following definitions are used to access individual LEDs. - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 /* User LD3 */ -#define BOARD_LED2 1 /* User LD4 */ -#define BOARD_NLEDS 2 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) - -/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -#define LED_STARTED 0 -#define LED_HEAPALLOCATE 0 -#define LED_IRQSENABLED 0 -#define LED_STACKCREATED 1 -#define LED_INIRQ 2 -#define LED_SIGNAL 2 -#define LED_ASSERTION 2 -#define LED_PANIC 3 - -/* Button definitions *******************************************************/ - -/* The STM32L-Discovery supports two buttons; only one button is controllable - * by software: - * - * B1 USER: user and wake-up button connected to the I/O PA0 of the - * STM32L152. - * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152. - */ - -#define BUTTON_USER 0 -#define NUM_BUTTONS 1 - -#define BUTTON_USER_BIT (1 << BUTTON_USER) - -/* Alternate Pin Functions **************************************************/ - -/* The STM32L-Discovery has no on-board RS-232 driver. Further, there - * are no USART pins that do not conflict with the on board resources, in - * particular, the LCD. Most USART pins are available if the LCD is enabled; - * USART2 may be used if either the LCD or the on-board LEDs are disabled. - * - * PA9 USART1_TX LCD glass COM1 P2, pin 22 - * PA10 USART1_RX LCD glass COM2 P2, pin 21 - * PB6 USART1_TX LED Blue P2, pin 8 - * PB7 USART1_RX LED Green P2, pin 7 - * - * PA2 USART2_TX LCD SEG1 P1, pin 17 - * PA3 USART2_RX LCD SEG2 P1, pin 18 - * - * PB10 USART3_TX LCD SEG6 P1, pin 22 - * PB11 USART3_RX LCD SEG7 P1, pin 23 - * PC10 USART3_TX LCD SEG22 P2, pin 15 - * PC11 USART3_RX LCD SEG23 P2, pin 14 - */ - -#if !defined(CONFIG_STM32_LCD) -/* Select PA9 and PA10 if the LCD is not enabled */ - -# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_40MHz) /* PA10 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_40MHz) /* PA9 */ - -/* This there are no other options for USART1 on this part */ - -# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ -# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ - -/* Arbitrarily select PB10 and PB11 */ - -# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_40MHz) /* PB11 */ -# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_40MHz) /* PB10 */ - -#elif !defined(CONFIG_ARCH_LEDS) - -/* Select PB6 and PB7 if the LEDs are not enabled */ - -# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_40MHz) /* PB7 */ -# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_40MHz) /* PB6 */ - -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_slcd_initialize - * - * Description: - * Initialize the STM32L-Discovery LCD hardware and register the character - * driver as /dev/slcd0. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_LCD -int stm32_slcd_initialize(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs deleted file mode 100644 index d9b35b396fa5c..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32ldiscovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_ARCH_CHIP_STM32L152RB),y) - LDSCRIPT = stm32l152rb.ld -else ifeq ($(CONFIG_ARCH_CHIP_STM32L152RC),y) - LDSCRIPT = stm32l152rc.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt deleted file mode 100644 index feae2b53ca12f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +++ /dev/null @@ -1,51 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) - -if(CONFIG_ARCH_LEDS) - list(APPEND SRCS stm32_autoleds.c) -else() - list(APPEND SRCS stm32_userleds.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_STM32_LCD) - list(APPEND SRCS stm32_lcd.c) -endif() - -if(CONFIG_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_ARCH_CHIP_STM32L152RB) - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32l152rb.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32l152rc.ld") -endif() diff --git a/boards/arm/stm32/stm32ldiscovery/src/Make.defs b/boards/arm/stm32/stm32ldiscovery/src/Make.defs deleted file mode 100644 index 0a07db0a932e5..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/Make.defs +++ /dev/null @@ -1,47 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32ldiscovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c - -ifeq ($(CONFIG_ARCH_LEDS),y) -CSRCS += stm32_autoleds.c -else -CSRCS += stm32_userleds.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_STM32_LCD),y) -CSRCS += stm32_lcd.c -endif - -ifeq ($(CONFIG_PWM),y) -CSRCS += stm32_pwm.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c deleted file mode 100644 index e251d0f2ead09..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c +++ /dev/null @@ -1,124 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#ifdef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on - * board the STM32L-Discovery. The following definitions describe how NuttX - * controls the LEDs: - * - * SYMBOL Meaning LED state - * LED1 LED2 - * ------------------- ----------------------- -------- -------- - * LED_STARTED NuttX has been started OFF OFF - * LED_HEAPALLOCATE Heap has been allocated OFF OFF - * LED_IRQSENABLED Interrupts enabled OFF OFF - * LED_STACKCREATED Idle stack created ON OFF - * LED_INIRQ In an interrupt No change - * LED_SIGNAL In a signal handler No change - * LED_ASSERTION An assertion failed No change - * LED_PANIC The system has crashed OFF Blinking - * LED_IDLE STM32 is in sleep mode Not used - */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_autoled_initialize - ****************************************************************************/ - -void board_autoled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - bool led1on = false; - bool led2on = false; - - switch (led) - { - case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ - break; - - case 1: /* LED_STACKCREATED */ - led1on = true; - break; - - default: - case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ - return; - - case 3: /* LED_PANIC */ - led2on = true; - break; - } - - stm32_gpiowrite(GPIO_LED1, led1on); - stm32_gpiowrite(GPIO_LED2, led2on); -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led != 2) - { - stm32_gpiowrite(GPIO_LED1, false); - stm32_gpiowrite(GPIO_LED2, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c deleted file mode 100644 index 701fdbd303cc7..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32ldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c deleted file mode 100644 index be3ff1616ed44..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c +++ /dev/null @@ -1,140 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include - -#include "stm32ldiscovery.h" - -#ifdef CONFIG_SENSORS_QENCODER -# include "board_qencoder.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) -#ifdef CONFIG_USERLED_LOWER - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#else - /* Enable USER LED support for some other purpose */ - - board_userled_initialize(); -#endif /* CONFIG_USERLED_LOWER */ -#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#ifdef CONFIG_STM32_LCD - /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ - - ret = stm32_slcd_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_PWM - /* Initialize PWM and register the PWM device. */ - - ret = stm32_pwm_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_QENCODER - /* Initialize and register the qencoder driver */ - - ret = board_qencoder_initialize(0, CONFIG_STM32LDISCO_QETIMER); - if (ret != OK) - { - syslog(LOG_ERR, - "ERROR: Failed to register the qencoder: %d\n", - ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c deleted file mode 100644 index 15071e1fe4083..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32_gpio.h" -#include "stm32ldiscovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM32F3Discovery button. This array is indexed - * by the BUTTON_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_BTN_USER -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for all pins. - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed. */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c deleted file mode 100644 index ff4119682da8f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ /dev/null @@ -1,1599 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* References: - * - Based on the NuttX LCD1602 driver. - * - "STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced - * ARM-based 32-bit MCUs", STMicroelectronics, RM0038 - * - "STM32L1 discovery kits: STM32L-DISCOVERY and 32L152CDISCOVERY," - * STMicroelectronics, UM1079 - * - STM32L-Discovery Firmware Pack V1.0.2 (for character encoding) - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_rcc.h" -#include "hardware/stm32_lcd.h" - -#include "stm32ldiscovery.h" - -#ifdef CONFIG_STM32_LCD - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Define CONFIG_DEBUG_LCD_INFO to enable detailed LCD debug output. */ - -#ifndef CONFIG_LIBC_SLCDCODEC -# error "This SLCD driver requires CONFIG_LIBC_SLCDCODEC" -#endif - -/* LCD **********************************************************************/ - -/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28. The STM32L- - * Discovery has an LCD 24 segments, 4 commons. See stm32ldiscovery.h for - * the pin mapping. - */ - -/* Macro to convert an LCD register offset and bit number into a bit-band - * address: - */ - -#define SLCD_OFFSET (STM32_LCD_BASE - STM32_PERIPH_BASE) -#define SLCD_BBADDR(o,b) (STM32_PERIPHBB_BASE + ((SLCD_OFFSET + (o)) << 5) + ((b) << 2)) - -/* Some useful bit-band addresses */ - -#define SLCD_CR_LCDEN_BB SLCD_BBADDR(STM32_LCD_CR_OFFSET,0) -#define SLCD_SR_UDR_BB SLCD_BBADDR(STM32_LCD_SR_OFFSET,2) - -/* LCD characteristics */ - -#define SLCD_NROWS 1 -#define SLCD_NCHARS 6 -#define SLCD_MAXCONTRAST 7 - -/* An ASCII character may need to be decorated with a colon or decimal - * point - */ - -#define SLCD_DP 0x01 -#define SLCD_COLON 0x02 -#define SLCD_NBARS 4 - -/* Macros used for set/reset the LCD bar */ - -#define SLCD_BAR0_ON g_slcdstate.bar[1] |= 8 -#define SLCD_BAR0_OFF g_slcdstate.bar[1] &= ~8 -#define SLCD_BAR1_ON g_slcdstate.bar[0] |= 8 -#define SLCD_BAR1_OFF g_slcdstate.bar[0] &= ~8 -#define SLCD_BAR2_ON g_slcdstate.bar[1] |= 2 -#define SLCD_BAR2_OFF g_slcdstate.bar[1] &= ~2 -#define SLCD_BAR3_ON g_slcdstate.bar[0] |= 2 -#define SLCD_BAR3_OFF g_slcdstate.bar[0] &= ~2 - -/* These definitions support the logic of slcd_writemem() - * - * ---------- ----- ----- ----- ----- ------- - * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT - * - * ---------- ----- ----- ----- ----- ------- - * LCD SEG0 1N 1P 1D 1E Bit 0 - * LCD SEG1 1DP 1COL 1C 1M Bit 1 - * LCD SEG2 2N 2P 2D 2E Bit 2 - * LCD SEG3 2DP 2COL 2C 2M Bit 7 - * LCD SEG4 3N 3P 3D 3E Bit 8 - * LCD SEG5 3DP 3COL 3C 3M Bit 9 - * LCD SEG6 4N 4P 4D 4E Bit 10 - * LCD SEG7 4DP 4COL 4C 4M Bit 11 - * LCD SEG8 5N 5P 5D 5E Bit 12 - * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 - * LCD SEG10 6N 6P 6D 6E Bit 14 - * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 - * LCD SEG12 6J 6K 6A 6B Bit 16 - * LCD SEG13 6H 6Q 6F 6G Bit 17 - * LCD SEG14 5J 5K 5A 5B Bit 18 - * LCD SEG15 5H 5Q 5F 5G Bit 19 - * LCD SEG16 4J 4K 4A 4B Bit 20 - * LCD SEG17 4H 4Q 4F 4G Bit 21 - * LCD SEG18 3J 3K 3A 3B Bit 24 - * LCD SEG19 3H 3Q 3F 3G Bit 25 - * LCD SEG20 2J 2K 2A 2B Bit 26 - * LCD SEG21 2H 2Q 2F 2G Bit 27 - * LCD SEG22 1J 1K 1A 1B Bit 28 - * LCD SEG23 1H 1Q 1F 1G Bit 29 - * ---------- ----- ----- ----- ----- -------- - - * ---------------- ------ ------ ------ ------- ------- -------------------- - * LCD CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS - * SIGNAL 3210 3210 3210 3210 32 10 32 10 - * --------- ------ ------ ------ ------ -- --- -- --- -------------------- - * LCD SEG0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG1 0 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG3 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG4 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG5 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG6 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG7 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG8 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG9 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG10 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG11 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG12 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG13 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ - * 0xfffcbfff - * LCD SEG14 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG15 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ - * 0xfff3efff - * LCD SEG16 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG17 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff - * LCD SEG18 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG19 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff - * LCD SEG20 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG21 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b - * LCD SEG22 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * LCD SEG23 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc - * --------- ------ ------ ------ ------- ------- --------------------------- - */ - -/* SLCD_CHAR1_MASK COM0-3 0xcffffffc ..11 .... .... .... .... .... .... ..11 - */ - -#define SLCD_CHAR1_MASK0 0xcffffffc -#define SLCD_CHAR1_MASK1 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_MASK2 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_MASK3 SLCD_CHAR1_MASK0 -#define SLCD_CHAR1_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 26) | \ - ((uint32_t)(s) & 0x03) -#define SLCD_CHAR1_UPDATE1(s) SLCD_CHAR1_UPDATE0(s) -#define SLCD_CHAR1_UPDATE2(s) SLCD_CHAR1_UPDATE0(s) -#define SLCD_CHAR1_UPDATE3(s) SLCD_CHAR1_UPDATE0(s) - -/* SLCD_CHAR2_MASK COM0-3 0xf3ffff03 .... 22.. .... .... .... .... 2... .2.. - */ - -#define SLCD_CHAR2_MASK0 0xf3ffff7b -#define SLCD_CHAR2_MASK1 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_MASK2 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_MASK3 SLCD_CHAR2_MASK0 -#define SLCD_CHAR2_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 24) | \ - (((uint32_t)(s) & 0x02) << 6) | \ - (((uint32_t)(s) & 0x01) << 2) -#define SLCD_CHAR2_UPDATE1(s) SLCD_CHAR2_UPDATE0(s) -#define SLCD_CHAR2_UPDATE2(s) SLCD_CHAR2_UPDATE0(s) -#define SLCD_CHAR2_UPDATE3(s) SLCD_CHAR2_UPDATE0(s) - -/* SLCD_CHAR3_MASK COM0-3 0xfcfffcff .... ..33 .... .... .... ..33 .... .... - */ - -#define SLCD_CHAR3_MASK0 0xfcfffcff -#define SLCD_CHAR3_MASK1 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_MASK2 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_MASK3 SLCD_CHAR3_MASK0 -#define SLCD_CHAR3_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 22) | \ - (((uint32_t)(s) & 0x03) << 8) -#define SLCD_CHAR3_UPDATE1(s) SLCD_CHAR3_UPDATE0(s) -#define SLCD_CHAR3_UPDATE2(s) SLCD_CHAR3_UPDATE0(s) -#define SLCD_CHAR3_UPDATE3(s) SLCD_CHAR3_UPDATE0(s) - -/* SLCD_CHAR4_MASK COM0-3 0xffcff3ff .... .... ..44 .... .... 44.. .... .... - */ - -#define SLCD_CHAR4_MASK0 0xffcff3ff -#define SLCD_CHAR4_MASK1 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_MASK2 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_MASK3 SLCD_CHAR4_MASK0 -#define SLCD_CHAR4_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 18) | \ - (((uint32_t)(s) & 0x03) << 10) -#define SLCD_CHAR4_UPDATE1(s) SLCD_CHAR4_UPDATE0(s) -#define SLCD_CHAR4_UPDATE2(s) SLCD_CHAR4_UPDATE0(s) -#define SLCD_CHAR4_UPDATE3(s) SLCD_CHAR4_UPDATE0(s) - -/* SLCD_CHAR5_MASK COM0-1 0xfff3cfff .... .... .... 55.. ..55 .... .... .... - * COM2-3 0xfff3efff .... .... .... 55.. ...5 .... .... .... - */ - -#define SLCD_CHAR5_MASK0 0xfff3cfff -#define SLCD_CHAR5_MASK1 SLCD_CHAR5_MASK0 -#define SLCD_CHAR5_MASK2 0xfff3efff -#define SLCD_CHAR5_MASK3 SLCD_CHAR5_MASK2 -#define SLCD_CHAR5_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 16) | \ - (((uint32_t)(s) & 0x03) << 12) -#define SLCD_CHAR5_UPDATE1(s) SLCD_CHAR5_UPDATE0(s) -#define SLCD_CHAR5_UPDATE2(s) (((uint32_t)(s) & 0x0c) << 16) | \ - (((uint32_t)(s) & 0x01) << 12) -#define SLCD_CHAR5_UPDATE3(s) SLCD_CHAR5_UPDATE2(s) - -/* SLCD_CHAR6_MASK COM0-1 0xfffc3fff .... .... .... ..66 66.. .... .... .... - * COM2-3 0xfffc3fff .... .... .... ..66 .6.. .... .... .... - */ - -#define SLCD_CHAR6_MASK0 0xfffc3fff -#define SLCD_CHAR6_MASK1 SLCD_CHAR6_MASK0 -#define SLCD_CHAR6_MASK2 0xfffcbfff -#define SLCD_CHAR6_MASK3 SLCD_CHAR6_MASK2 -#define SLCD_CHAR6_UPDATE0(s) (((uint32_t)(s) & 0x04) << 15) | \ - (((uint32_t)(s) & 0x08) << 13) | \ - (((uint32_t)(s) & 0x03) << 14) -#define SLCD_CHAR6_UPDATE1(s) SLCD_CHAR6_UPDATE0(s) -#define SLCD_CHAR6_UPDATE2(s) (((uint32_t)(s) & 0x04) << 15) | \ - (((uint32_t)(s) & 0x08) << 13) | \ - (((uint32_t)(s) & 0x03) << 14) -#define SLCD_CHAR6_UPDATE3(s) SLCD_CHAR6_UPDATE2(s) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Global SLCD state */ - -struct stm32_slcdstate_s -{ - bool initialized; /* True: Completed initialization sequence */ - uint8_t curpos; /* The current cursor position */ - uint8_t buffer[SLCD_NCHARS]; /* SLCD ASCII content */ - uint8_t options[SLCD_NCHARS]; /* With colon or decimal point decoration */ - uint8_t bar[2]; /* Controls the bars on the far right of the SLCD */ -}; - -/**************************************************************************** - * Private Function Protototypes - ****************************************************************************/ - -/* Debug */ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpstate(const char *msg); -static void slcd_dumpslcd(const char *msg); -#else -# define slcd_dumpstate(msg) -# define slcd_dumpslcd(msg) -#endif - -/* Internal utilities */ - -static void slcd_clear(void); -static uint8_t slcd_getcontrast(void); -static int slcd_setcontrast(uint8_t contrast); -static void slcd_writebar(void); -static inline uint16_t slcd_mapch(uint8_t ch); -static inline void slcd_writemem(uint16_t segset, int curpos); -static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options); -static void slcd_appendch(uint8_t ch, uint8_t options); -static void slcd_action(enum slcdcode_e code, uint8_t count); - -/* Character driver methods */ - -static ssize_t slcd_read(struct file *, char *, size_t); -static ssize_t slcd_write(struct file *, const char *, size_t); -static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg); -static int slcd_poll(struct file *filep, struct pollfd *fds, - bool setup); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the driver state structure (there is no retained state - * information) - */ - -static const struct file_operations g_slcdops = -{ - NULL, /* open */ - NULL, /* close */ - slcd_read, /* read */ - slcd_write, /* write */ - NULL, /* seek */ - slcd_ioctl, /* ioctl */ - NULL, /* mmap */ - NULL, /* truncate */ - slcd_poll /* poll */ -}; - -/* LCD state data */ - -static struct stm32_slcdstate_s g_slcdstate; - -/* LCD Mapping - * - * A - * --------- _ - * |\ |J /| |_| COL - * F| H | K |B - * | \ | / | _ - * --G-- --M-+ |_| COL - * | /| \ | - * E| Q | N |C - * | / |P \| _ - * --------- |_| DP - * D - * - * LCD character 16-bit-encoding: - * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } - */ - -#warning "Encodings for all punctuation are incomplete" - -/* Space and ASCII punctuation: 0x20-0x2f */ - -static const uint16_t g_slcdpunct1[ASCII_0 - ASCII_SPACE] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* ! " # $ % & ' */ - 0x0000, 0x0000, 0xa0dd, 0x0000, 0x0000, 0xa000, 0x0000, 0x00c0 /* () * + , - . / */ -}; - -/* ASCII numerals 0-9: 0x30-0x39 */ - -static const uint16_t g_slcdnummap[ASCII_COLON - ASCII_0] = -{ - 0x5f00, 0x4200, 0xf500, 0x6700, 0xea00, 0xaf00, 0xbf00, 0x4600, /* 0-7 */ - 0xff00, 0xef00 /* 8-9 */ -}; - -/* ASCII punctuation: 0x3a-0x40 */ - -static const uint16_t g_slcdpunct2[ASCII_A - ASCII_COLON] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* : ; < = > ? @ */ -}; - -/* Upper case letters A-Z: 0x41-0x5a. Also lower case letters a-z: - * 0x61-0x7a - */ - -static const uint16_t g_slcdalphamap[ASCII_LBRACKET - ASCII_A] = -{ - 0xfe00, 0x6714, 0x1d00, 0x4714, 0x9d00, 0x9c00, 0x3f00, 0xfa00, /* A-H */ - 0x0014, 0x5300, 0x9841, 0x1900, 0x5a48, 0x5a09, 0x5f00, 0xfc00, /* I-P */ - 0x5f01, 0xfc01, 0xaf00, 0x0414, 0x5b00, 0x18c0, 0x5a81, 0x00c9, /* Q-X */ - 0x0058, 0x05c0 /* y-Z */ -}; - -/* ASCII punctuation: 0x5b-0x60 */ - -static const uint16_t g_slcdpunct3[ASCII_a - ASCII_LBRACKET] = -{ - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* [ \ ] ^ _ */ -}; - -/* ASCII punctuation: 0x7b-0x7e */ - -static const uint16_t g_slcdpunct4[ASCII_DEL - ASCII_LBRACE] = -{ - 0x0000, 0x0000, 0x0000, 0x0000 /* { | } ~ */ -}; - -/* All GPIOs that need to be configured for the STM32L-Discovery LCD */ - -static uint32_t g_slcdgpio[BOARD_SLCD_NGPIOS] = -{ - BOARD_SLCD_COM0, BOARD_SLCD_COM1, BOARD_SLCD_COM2, BOARD_SLCD_COM3, - - BOARD_SLCD_SEG0, BOARD_SLCD_SEG1, BOARD_SLCD_SEG2, BOARD_SLCD_SEG3, - BOARD_SLCD_SEG4, BOARD_SLCD_SEG5, BOARD_SLCD_SEG6, BOARD_SLCD_SEG7, - BOARD_SLCD_SEG8, BOARD_SLCD_SEG9, BOARD_SLCD_SEG10, BOARD_SLCD_SEG11, - BOARD_SLCD_SEG12, BOARD_SLCD_SEG13, BOARD_SLCD_SEG14, BOARD_SLCD_SEG15, - BOARD_SLCD_SEG16, BOARD_SLCD_SEG17, BOARD_SLCD_SEG18, BOARD_SLCD_SEG19, - BOARD_SLCD_SEG20, BOARD_SLCD_SEG21, BOARD_SLCD_SEG22, BOARD_SLCD_SEG23 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: slcd_dumpstate - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpstate(const char *msg) -{ - lcdinfo("%s:\n", msg); - lcdinfo(" curpos: %d\n", - g_slcdstate.curpos); - lcdinfo(" Display: [%c%c%c%c%c%c]\n", - g_slcdstate.buffer[0], g_slcdstate.buffer[1], - g_slcdstate.buffer[2], g_slcdstate.buffer[3], - g_slcdstate.buffer[4], g_slcdstate.buffer[5]); - lcdinfo(" Options: [%d%d%d%d%d%d]\n", - g_slcdstate.options[0], g_slcdstate.options[1], - g_slcdstate.options[2], g_slcdstate.options[3], - g_slcdstate.options[4], g_slcdstate.options[5]); - lcdinfo(" Bar: %02x %02x\n", - g_slcdstate.bar[0], g_slcdstate.bar[1]); -} -#endif - -/**************************************************************************** - * Name: slcd_dumpslcd - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_LCD_INFO -static void slcd_dumpslcd(const char *msg) -{ - lcdinfo("%s:\n", msg); - lcdinfo(" CR: %08x FCR: %08x SR: %08x CLR: %08x\n", - getreg32(STM32_LCD_CR), getreg32(STM32_LCD_FCR), - getreg32(STM32_LCD_SR), getreg32(STM32_LCD_CLR)); - lcdinfo(" RAM0L: %08x RAM1L: %08x RAM2L: %08x RAM3L: %08x\n", - getreg32(STM32_LCD_RAM0L), getreg32(STM32_LCD_RAM1L), - getreg32(STM32_LCD_RAM2L), getreg32(STM32_LCD_RAM3L)); -} -#endif - -/**************************************************************************** - * Name: slcd_clear - ****************************************************************************/ - -static void slcd_clear(void) -{ - uint32_t regaddr; - - linfo("Clearing\n"); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Write all zerios in to the LCD RAM */ - - for (regaddr = STM32_LCD_RAML(0); regaddr <= STM32_LCD_RAMH(7); regaddr++) - { - putreg32(0, regaddr); - } - - /* Set all buffered data to undecorated spaces and home the cursor */ - - memset(g_slcdstate.buffer, ' ', SLCD_NCHARS); - memset(g_slcdstate.options, 0, SLCD_NCHARS); - g_slcdstate.curpos = 0; - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); -} - -/**************************************************************************** - * Name: slcd_getcontrast - ****************************************************************************/ - -static uint8_t slcd_getcontrast(void) -{ - return (getreg32(STM32_LCD_FCR) & LCD_FCR_CC_MASK) >> LCD_FCR_CC_SHIFT; -} - -/**************************************************************************** - * Name: slcd_setcontrast - ****************************************************************************/ - -static int slcd_setcontrast(uint8_t contrast) -{ - uint32_t regval; - int ret = OK; - - /* Make sure that the contrast setting is within range */ - - if (contrast > 7) - { - contrast = 7; - ret = -ERANGE; - } - - regval = getreg32(STM32_LCD_FCR); - regval &= ~LCD_FCR_CC_MASK; - regval |= contrast << LCD_FCR_CC_SHIFT; - putreg32(regval, STM32_LCD_FCR); - - lcdinfo("contrast: %" PRId32 " FCR: %08x\n", - getreg32(STM32_LCD_FCR), contrast); - - return ret; -} - -/**************************************************************************** - * Name: slcd_writebar - ****************************************************************************/ - -static void slcd_writebar(void) -{ - uint32_t regval; - - lcdinfo("bar: %02x %02x\n", g_slcdstate.bar[0], g_slcdstate.bar[1]); - slcd_dumpslcd("BEFORE WRITE"); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Update the BAR */ - - regval = getreg32(STM32_LCD_RAM2L); - regval &= 0xffff5fff; - regval |= (uint32_t)(g_slcdstate.bar[0] << 12); - putreg32(regval, STM32_LCD_RAM2L); - - regval = getreg32(STM32_LCD_RAM3L); - regval &= 0xffff5fff; - regval |= (uint32_t)(g_slcdstate.bar[1] << 12); - putreg32(regval, STM32_LCD_RAM3L); - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); - slcd_dumpslcd("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_mapch - ****************************************************************************/ - -static inline uint16_t slcd_mapch(uint8_t ch) -{ - /* ASCII control characters, the forward delete character, period, colon, - * and all 8-bit ASCII character have already been handled prior to this - * function. - */ - - /* Return spaces all control characters (this should not happen) */ - - if (ch < ASCII_SPACE) - { - return 0x0000; - } - - /* Handle space and the first block of punctuation */ - - if (ch < ASCII_0) - { - return g_slcdpunct1[(int)ch - ASCII_SPACE]; - } - - /* Handle numbers */ - - else if (ch < ASCII_COLON) - { - return g_slcdnummap[(int)ch - ASCII_0]; - } - - /* Handle the next block of punctuation */ - - else if (ch < ASCII_A) - { - return g_slcdpunct2[(int)ch - ASCII_COLON]; - } - - /* Handle upper case letters */ - - else if (ch < ASCII_LBRACKET) - { - return g_slcdalphamap[(int)ch - ASCII_A]; - } - - /* Handle the next block of punctuation */ - - else if (ch < ASCII_a) - { - return g_slcdpunct3[(int)ch - ASCII_LBRACKET]; - } - - /* Handle lower case letters (by mapping them to upper case */ - - else if (ch < ASCII_LBRACE) - { - return g_slcdalphamap[(int)ch - ASCII_a]; - } - - /* Handle the final block of punctuation */ - - else if (ch < ASCII_DEL) - { - return g_slcdpunct4[(int)ch - ASCII_LBRACE]; - } - - /* Ignore 8-bit ASCII and DEL (this should not happen) */ - - return 0x0000; -} - -/**************************************************************************** - * Name: slcd_writemem - ****************************************************************************/ - -static inline void slcd_writemem(uint16_t segset, int curpos) -{ - uint8_t segments[4]; - uint32_t ram0; - uint32_t ram1; - uint32_t ram2; - uint32_t ram3; - int i; - int j; - - lcdinfo("segset: %04x curpos: %d\n", segset, curpos); - slcd_dumpslcd("BEFORE WRITE"); - - /* Isolate the least significant bits - * - * LCD character 16-bit-encoding: - * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } - * - * segments[0] = { E , D , P , N } - * segments[1] = { M , C , COL , DP } - * segments[2] = { B , A , K , J } - * segments[3] = { G , F , Q , H } - */ - - for (i = 12, j = 0; j < 4; i -= 4, j++) - { - segments[j] = (segset >> i) & 0x0f; - } - - lcdinfo("segments: %02x %02x %02x %02x\n", - segments[0], segments[1], segments[2], segments[3]); - - /* Make sure that any previous transfer is complete. The firmware sets - * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the - * end of the update. During this time the LCD_RAM is write protected. - */ - - while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); - - /* Now update the SLCD memory for the character at this cursor position by - * decoding the bit-mapped value - */ - - ram0 = getreg32(STM32_LCD_RAM0L); - ram1 = getreg32(STM32_LCD_RAM1L); - ram2 = getreg32(STM32_LCD_RAM2L); - ram3 = getreg32(STM32_LCD_RAM3L); - - switch (curpos) - { - case 0: - ram0 &= SLCD_CHAR1_MASK0; - ram0 |= SLCD_CHAR1_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR1_MASK1; - ram1 |= SLCD_CHAR1_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR1_MASK2; - ram2 |= SLCD_CHAR1_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR1_MASK3; - ram3 |= SLCD_CHAR1_UPDATE3(segments[3]); - break; - - case 1: - ram0 &= SLCD_CHAR2_MASK0; - ram0 |= SLCD_CHAR2_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR2_MASK1; - ram1 |= SLCD_CHAR2_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR2_MASK2; - ram2 |= SLCD_CHAR2_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR2_MASK3; - ram3 |= SLCD_CHAR2_UPDATE3(segments[3]); - break; - - case 2: - ram0 &= SLCD_CHAR3_MASK0; - ram0 |= SLCD_CHAR3_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR3_MASK1; - ram1 |= SLCD_CHAR3_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR3_MASK2; - ram2 |= SLCD_CHAR3_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR3_MASK3; - ram3 |= SLCD_CHAR3_UPDATE3(segments[3]); - break; - - case 3: - ram0 &= SLCD_CHAR4_MASK0; - ram0 |= SLCD_CHAR4_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR4_MASK1; - ram1 |= SLCD_CHAR4_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR4_MASK2; - ram2 |= SLCD_CHAR4_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR4_MASK3; - ram3 |= SLCD_CHAR4_UPDATE3(segments[3]); - break; - - case 4: - ram0 &= SLCD_CHAR5_MASK0; - ram0 |= SLCD_CHAR5_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR5_MASK1; - ram1 |= SLCD_CHAR5_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR5_MASK2; - ram2 |= SLCD_CHAR5_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR5_MASK3; - ram3 |= SLCD_CHAR5_UPDATE3(segments[3]); - break; - - case 5: - ram0 &= SLCD_CHAR6_MASK0; - ram0 |= SLCD_CHAR6_UPDATE0(segments[0]); - - ram1 &= SLCD_CHAR6_MASK1; - ram1 |= SLCD_CHAR6_UPDATE1(segments[1]); - - ram2 &= SLCD_CHAR6_MASK2; - ram2 |= SLCD_CHAR6_UPDATE2(segments[2]); - - ram3 &= SLCD_CHAR6_MASK3; - ram3 |= SLCD_CHAR6_UPDATE3(segments[3]); - break; - - default: - return; - } - - putreg32(ram0, STM32_LCD_RAM0L); - putreg32(ram1, STM32_LCD_RAM1L); - putreg32(ram2, STM32_LCD_RAM2L); - putreg32(ram3, STM32_LCD_RAM3L); - - /* Set the UDR bit to transfer the updated data to the second level - * buffer. - */ - - putreg32(1, SLCD_SR_UDR_BB); - slcd_dumpslcd("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_writech - ****************************************************************************/ - -static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options) -{ - uint16_t segset; - - /* Map the character code to a 16-bit encoded value */ - - segset = slcd_mapch(ch); - - /* Check if the character should be decorated with a decimal point or - * colon - */ - - if ((options & SLCD_DP) != 0) - { - segset |= 0x0002; - } - else if ((options & SLCD_COLON) != 0) - { - segset |= 0x0020; - } - - lcdinfo("ch: [%c] options: %02x segset: %04x\n", ch, options, segset); - - /* Decode the value and write it to the SLCD segment memory */ - - slcd_writemem(segset, curpos); - - /* Save these values in the state structure */ - - g_slcdstate.buffer[curpos] = ch; - g_slcdstate.options[curpos] = options; - - slcd_dumpstate("AFTER WRITE"); -} - -/**************************************************************************** - * Name: slcd_appendch - ****************************************************************************/ - -static void slcd_appendch(uint8_t ch, uint8_t options) -{ - lcdinfo("ch: [%c] options: %02x\n", ch, options); - - /* Write the character at the current cursor position */ - - slcd_writech(ch, g_slcdstate.curpos, options); - if (g_slcdstate.curpos < (SLCD_NCHARS - 1)) - { - g_slcdstate.curpos++; - } - - slcd_dumpstate("AFTER APPEND"); -} - -/**************************************************************************** - * Name: slcd_action - ****************************************************************************/ - -static void slcd_action(enum slcdcode_e code, uint8_t count) -{ - lcdinfo("Action: %d count: %d\n", code, count); - slcd_dumpstate("BEFORE ACTION"); - - switch (code) - { - /* Erasure */ - - case SLCDCODE_BACKDEL: /* Backspace (backward delete) N characters */ - { - int tmp; - - /* If we are at the home position or if the count is zero, then - * ignore the action - */ - - if (g_slcdstate.curpos < 1 || count < 1) - { - break; - } - - /* Otherwise, BACKDEL is like moving the cursor back N characters - * then doing a forward deletion. Decrement the cursor position - * and fall through. - */ - - tmp = (int)g_slcdstate.curpos - count; - if (tmp < 0) - { - tmp = 0; - count = g_slcdstate.curpos; - } - - /* Save the updated cursor positions */ - - g_slcdstate.curpos = tmp; - } - - case SLCDCODE_FWDDEL: /* DELete (forward delete) N characters moving text */ - if (count > 0) - { - int nchars; - int nmove; - int i; - - /* How many characters are to the right of the cursor position - * (including the one at the cursor position)? Then get the - * number of characters to move. - */ - - nchars = SLCD_NCHARS - g_slcdstate.curpos; - nmove = MIN(nchars, count) - 1; - - /* Move all characters after the current cursor position left - * by 'nmove' characters - */ - - for (i = g_slcdstate.curpos + nmove; i < SLCD_NCHARS - 1; i++) - { - slcd_writech(g_slcdstate.buffer[i - nmove], i, - g_slcdstate.options[i - nmove]); - } - - /* Erase the last 'nmove' characters on the display */ - - for (i = SLCD_NCHARS - nmove; i < SLCD_NCHARS; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - case SLCDCODE_ERASE: /* Erase N characters from the cursor position */ - if (count > 0) - { - int last; - int i; - - /* Get the last position to clear and make sure that the last - * position is on the SLCD. - */ - - last = g_slcdstate.curpos + count - 1; - if (last >= SLCD_NCHARS) - { - last = SLCD_NCHARS - 1; - } - - /* Erase N characters after the current cursor position left by - * one - */ - - for (i = g_slcdstate.curpos; i < last; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - case SLCDCODE_CLEAR: /* Home the cursor and erase the entire display */ - { - /* This is like HOME followed by ERASEEOL. Home the cursor and - * fall through. - */ - - g_slcdstate.curpos = 0; - } - - case SLCDCODE_ERASEEOL: /* Erase from the cursor position to the end of line */ - { - int i; - - /* Erase characters after the current cursor position to the end - * of the line - */ - - for (i = g_slcdstate.curpos; i < SLCD_NCHARS; i++) - { - slcd_writech(' ', i, 0); - } - } - break; - - /* Cursor movement */ - - case SLCDCODE_HOME: /* Cursor home */ - { - g_slcdstate.curpos = 0; - } - break; - - case SLCDCODE_END: /* Cursor end */ - { - g_slcdstate.curpos = SLCD_NCHARS - 1; - } - break; - - case SLCDCODE_LEFT: /* Cursor left by N characters */ - { - int tmp = (int)g_slcdstate.curpos - count; - - /* Don't permit movement past the beginning of the SLCD */ - - if (tmp < 0) - { - tmp = 0; - } - - /* Save the new cursor position */ - - g_slcdstate.curpos = (uint8_t)tmp; - } - break; - - case SLCDCODE_RIGHT: /* Cursor right by N characters */ - { - int tmp = (int)g_slcdstate.curpos + count; - - /* Don't permit movement past the end of the SLCD */ - - if (tmp >= SLCD_NCHARS) - { - tmp = SLCD_NCHARS - 1; - } - - /* Save the new cursor position */ - - g_slcdstate.curpos = (uint8_t)tmp; - } - break; - - case SLCDCODE_UP: /* Cursor up by N lines */ - case SLCDCODE_DOWN: /* Cursor down by N lines */ - case SLCDCODE_PAGEUP: /* Cursor up by N pages */ - case SLCDCODE_PAGEDOWN: /* Cursor down by N pages */ - break; /* Not supportable on this SLCD */ - - /* Blinking */ - - case SLCDCODE_BLINKSTART: /* Start blinking with current cursor position */ - case SLCDCODE_BLINKEND: /* End blinking after the current cursor position */ - case SLCDCODE_BLINKOFF: /* Turn blinking off */ - break; /* Not implemented */ - - /* These are actually unreportable errors */ - - default: - case SLCDCODE_NORMAL: /* Not a special keycode */ - break; - } - - slcd_dumpstate("AFTER ACTION"); -} - -/**************************************************************************** - * Name: slcd_read - ****************************************************************************/ - -static ssize_t slcd_read(struct file *filep, char *buffer, - size_t len) -{ - int ret = 0; - int i; - - /* Try to read the entire display. Notice that the seek offset - * (filep->f_pos) is ignored. It probably should be taken into account - * and also updated after each read and write. - */ - - for (i = 0; i < SLCD_NCHARS && ret < len; i++) - { - /* Return the character */ - - *buffer++ = g_slcdstate.buffer[i]; - ret++; - - /* Check if the character is decorated with a following period or - * colon - */ - - if (ret < len && g_slcdstate.buffer[i] != 0) - { - if ((g_slcdstate.buffer[i] & SLCD_DP) != 0) - { - *buffer++ = '.'; - ret++; - } - else if ((g_slcdstate.buffer[i] & SLCD_COLON) != 0) - { - *buffer++ = ':'; - ret++; - } - } - } - - slcd_dumpstate("READ"); - return ret; -} - -/**************************************************************************** - * Name: slcd_write - ****************************************************************************/ - -static ssize_t slcd_write(struct file *filep, - const char *buffer, size_t len) -{ - struct lib_meminstream_s instream; - struct slcdstate_s state; - enum slcdret_e result; - uint8_t ch; - uint8_t count; - uint8_t prev = ' '; - bool valid = false; - - /* Initialize the stream for use with the SLCD CODEC */ - - lib_meminstream(&instream, buffer, len); - - /* Prime the pump. This is messy, but necessary to handle decoration on a - * character based on any following period or colon. - */ - - memset(&state, 0, sizeof(struct slcdstate_s)); - result = slcd_decode(&instream.common, &state, &prev, &count); - - lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", - result, prev, count); - - switch (result) - { - case SLCDRET_CHAR: - valid = true; - break; - - case SLCDRET_SPEC: - { - slcd_action((enum slcdcode_e)prev, count); - prev = ' '; - } - break; - - case SLCDRET_EOF: - return 0; - } - - /* Now decode and process every byte in the input buffer */ - - while ((result = slcd_decode(&instream.common, - &state, &ch, &count)) != SLCDRET_EOF) - { - lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", - result, ch, count); - - if (result == SLCDRET_CHAR) /* A normal character was returned */ - { - /* Check for ASCII control characters */ - - if (ch < ASCII_SPACE) - { - /* All are ignored except for backspace and carriage return */ - - if (ch == ASCII_BS) - { - /* If there is a pending character, then output it now - * before performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the backward deletion */ - - slcd_action(SLCDCODE_BACKDEL, 1); - } - else if (ch == ASCII_CR) - { - /* If there is a pending character, then output it now - * before performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the carriage return */ - - slcd_action(SLCDCODE_HOME, 0); - } - } - - /* Handle characters decoreated with a period or a colon */ - - else if (ch == '.') - { - /* Write the previous character with the decimal point - * appended - */ - - slcd_appendch(prev, SLCD_DP); - prev = ' '; - valid = false; - } - else if (ch == ':') - { - /* Write the previous character with the colon appended */ - - slcd_appendch(prev, SLCD_COLON); - prev = ' '; - valid = false; - } - - /* Handle ASCII_DEL */ - - else if (ch == ASCII_DEL) - { - /* If there is a pending character, then output it now before - * performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the forward deletion */ - - slcd_action(SLCDCODE_FWDDEL, 1); - } - - /* The rest of the 7-bit ASCII characters are fair game */ - - else if (ch < 128) - { - /* Write the previous character if it valid */ - - if (valid) - { - slcd_appendch(prev, 0); - } - - /* There is now a valid output character */ - - prev = ch; - valid = true; - } - } - else /* (result == SLCDRET_SPEC) */ /* A special SLCD action was returned */ - { - /* If there is a pending character, then output it now before - * performing the action. - */ - - if (valid) - { - slcd_appendch(prev, 0); - prev = ' '; - valid = false; - } - - /* Then perform the action */ - - slcd_action((enum slcdcode_e)ch, count); - } - } - - /* Handle any unfinished output */ - - if (valid) - { - slcd_appendch(prev, 0); - } - - /* Assume that the entire input buffer was processed */ - - return (ssize_t)len; -} - -/**************************************************************************** - * Name: slcd_poll - ****************************************************************************/ - -static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - switch (cmd) - { - /* SLCDIOC_GETATTRIBUTES: Get the attributes of the SLCD - * - * argument: Pointer to struct slcd_attributes_s in which values - * will be returned - */ - - case SLCDIOC_GETATTRIBUTES: - { - struct slcd_attributes_s *attr = - (struct slcd_attributes_s *)((uintptr_t)arg); - - lcdinfo("SLCDIOC_GETATTRIBUTES:\n"); - - if (!attr) - { - return -EINVAL; - } - - attr->nrows = SLCD_NROWS; - attr->ncolumns = SLCD_NCHARS; - attr->nbars = SLCD_NBARS; - attr->maxcontrast = SLCD_MAXCONTRAST; - attr->maxbrightness = 0; - } - break; - - /* SLCDIOC_CURPOS: Get the SLCD cursor positioni (rows x characters) - * - * argument: Pointer to struct slcd_curpos_s in which values will be - * returned - */ - - case SLCDIOC_CURPOS: - { - struct slcd_curpos_s *curpos = - (struct slcd_curpos_s *)((uintptr_t)arg); - - lcdinfo("SLCDIOC_CURPOS: row=0 column=%d\n", g_slcdstate.curpos); - - if (!curpos) - { - return -EINVAL; - } - - curpos->row = 0; - curpos->column = g_slcdstate.curpos; - } - break; - - /* SLCDIOC_SETBAR: Set bars on a bar display - * - * argument: 32-bit bitset, with each bit corresponding to one bar. - */ - - case SLCDIOC_SETBAR: - { - lcdinfo("SLCDIOC_SETBAR: arg=0x%02lx\n", arg); - - /* Format the bar */ - - g_slcdstate.bar[0] = 0; - g_slcdstate.bar[1] = 0; - - if ((arg & 1) != 0) - { - SLCD_BAR0_ON; - } - - if ((arg & 2) != 0) - { - SLCD_BAR1_ON; - } - - if ((arg & 4) != 0) - { - SLCD_BAR2_ON; - } - - if ((arg & 8) != 0) - { - SLCD_BAR3_ON; - } - - /* Write the bar to SLCD memory */ - - slcd_writebar(); - } - break; - - /* SLCDIOC_GETCONTRAST: Get the current contrast setting - * - * argument: Pointer type int that will receive the current contrast - * setting - */ - - case SLCDIOC_GETCONTRAST: - { - int *contrast = (int *)((uintptr_t)arg); - if (!contrast) - { - return -EINVAL; - } - - *contrast = (int)slcd_getcontrast(); - lcdinfo("SLCDIOC_GETCONTRAST: contrast=%d\n", *contrast); - } - break; - - /* SLCDIOC_SETCONTRAST: Set the contrast to a new value - * - * argument: The new contrast value - */ - - case SLCDIOC_SETCONTRAST: - { - lcdinfo("SLCDIOC_SETCONTRAST: arg=%ld\n", arg); - - if (arg > SLCD_MAXCONTRAST) - { - return -ERANGE; - } - - return slcd_setcontrast((uint8_t)arg); - } - break; - - case SLCDIOC_GETBRIGHTNESS: /* Get the current brightness setting */ - case SLCDIOC_SETBRIGHTNESS: /* Set the brightness to a new value */ - default: - return -ENOTTY; - } - - return OK; -} - -/**************************************************************************** - * Name: slcd_poll - ****************************************************************************/ - -static int slcd_poll(struct file *filep, struct pollfd *fds, - bool setup) -{ - if (setup) - { - /* Data is always available to be read / Data can always be written */ - - poll_notify(&fds, 1, POLLIN | POLLOUT); - } - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_slcd_initialize - * - * Description: - * Initialize the STM32L-Discovery LCD hardware and register the character - * driver as /dev/slcd0. - * - ****************************************************************************/ - -int stm32_slcd_initialize(void) -{ - uint32_t regval; - int ret = OK; - int i; - - /* Only initialize the driver once. */ - - if (!g_slcdstate.initialized) - { - lcdinfo("Initializing\n"); - - /* Configure LCD GPIO pins */ - - for (i = 0; i < BOARD_SLCD_NGPIOS; i++) - { - stm32_configgpio(g_slcdgpio[i]); - } - - /* Enable the External Low-Speed (LSE) oscillator and select it as the - * LCD clock source. - * - * NOTE: LCD clocking should already be enabled in the RCC APB1ENR - * register. - */ - - stm32_rcc_enablelse(); - - lcdinfo("APB1ENR: %08" PRIx32 " CSR: %08" PRIx32 "\n", - getreg32(STM32_RCC_APB1ENR), getreg32(STM32_RCC_CSR)); - - /* Set the LCD prescaler and divider values */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~(LCD_FCR_DIV_MASK | LCD_FCR_PS_MASK); - regval |= (LCD_FCR_PS_DIV1 | LCD_FCR_DIV(31)); - putreg32(regval, STM32_LCD_FCR); - - /* Wait for the FCRSF flag to be set */ - - lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); - - /* Set the duty (1/4), bias (1/3), and the internal voltage source - * (VSEL=0) - */ - - regval = getreg32(STM32_LCD_CR); - regval &= ~(LCD_CR_BIAS_MASK | LCD_CR_DUTY_MASK | LCD_CR_VSEL); - regval |= (LCD_CR_DUTY_1TO4 | LCD_CR_BIAS_1TO3); - putreg32(regval, STM32_LCD_CR); - - /* SEG[31:28] are multiplexed with SEG[43:40] */ - - regval |= LCD_CR_MUX_SEG; - putreg32(regval, STM32_LCD_CR); - - /* Set the contrast to the mean value */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~LCD_FCR_CC_MASK; - regval |= LCD_FCR_CC_VLCD(4); - putreg32(regval, STM32_LCD_FCR); - - /* No dead time */ - - regval &= ~LCD_FCR_DEAD_MASK; - putreg32(regval, STM32_LCD_FCR); - - /* Set the pulse-on duration to 4/ck_ps */ - - regval &= ~LCD_FCR_PON_MASK; - regval |= LCD_FCR_PON(4); - putreg32(regval, STM32_LCD_FCR); - - /* Wait Until the LCD FCR register is synchronized */ - - lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); - - /* Enable LCD peripheral */ - - putreg32(1, SLCD_CR_LCDEN_BB); - - /* Wait Until the LCD is enabled and the LCD booster is ready */ - - lcdinfo("Wait for LCD_SR_ENS and LCD_SR_RDY, " - "CR: %08" PRIx32 " SR: %08" PRIx32 "\n", - getreg32(STM32_LCD_CR), getreg32(STM32_LCD_SR)); - - while ((getreg32(STM32_LCD_SR) & (LCD_SR_ENS | LCD_SR_RDY)) != - (LCD_SR_ENS | LCD_SR_RDY)); - - /* Disable blinking */ - - regval = getreg32(STM32_LCD_FCR); - regval &= ~(LCD_FCR_BLINKF_MASK | LCD_FCR_BLINK_MASK); - regval |= (LCD_FCR_BLINK_DISABLE | LCD_FCR_BLINKF_DIV32); - putreg32(regval, STM32_LCD_FCR); - - slcd_dumpslcd("AFTER INITIALIZATION"); - - /* Register the LCD device driver */ - - ret = register_driver("/dev/slcd0", &g_slcdops, 0644, &g_slcdstate); - g_slcdstate.initialized = true; - - /* Then clear the display */ - - slcd_clear(); - slcd_dumpstate("AFTER INITIALIZATION"); - } - - return ret; -} - -#endif /* CONFIG_STM32_LCD */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c deleted file mode 100644 index 3857da41ec48f..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_pwm.h" -#include "stm32ldiscovery.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* PWM - * - * The stm32ldiscovery has no real on-board PWM devices, but the board can - * be configured to output a pulse train using TIM4 CH2. - * This pin is used by FSMC is connected to CN5 just for this purpose: - * - * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) - * - * FSMC must be disabled in this case! - */ - -#define HAVE_PWM 1 - -#ifndef CONFIG_PWM -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4 -# undef HAVE_PWM -#endif - -#ifndef CONFIG_STM32_TIM4_PWM -# undef HAVE_PWM -#endif - -#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL -# undef HAVE_PWM -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pwm_setup - * - * Description: - * Initialize PWM and register the PWM device. - * - ****************************************************************************/ - -int stm32_pwm_setup(void) -{ -#ifdef HAVE_PWM - static bool initialized = false; - struct pwm_lowerhalf_s *pwm; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* Call stm32_pwminitialize() to get an instance of the PWM interface */ - - pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); - if (!pwm) - { - _err("ERROR: Failed to get the STM32 PWM lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - aerr("ERROR: pwm_register failed: %d\n", ret); - return ret; - } - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -#else - return -ENODEV; -#endif -} diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c deleted file mode 100644 index 7263febe7ea70..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c +++ /dev/null @@ -1,182 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the stm32ldiscovery - * board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ -#ifdef CONFIG_STM32_SPI1 - stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ - stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ - stm32_configgpio(GPIO_MEMS_INT2); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - - stm32_gpiowrite(GPIO_MEMS_CS, !selected); -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return -ENODEV; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c deleted file mode 100644 index 362209fa5999b..0000000000000 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" -#include "stm32.h" -#include "stm32ldiscovery.h" - -#ifndef CONFIG_ARCH_LEDS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_userled_initialize - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Configure LED1-2 GPIOs for output */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - return BOARD_NLEDS; -} - -/**************************************************************************** - * Name: board_userled - ****************************************************************************/ - -void board_userled(int led, bool ledon) -{ - uint32_t ledcfg; - - if (led == BOARD_LED1) - { - ledcfg = GPIO_LED1; - } - else if (led == BOARD_LED2) - { - ledcfg = GPIO_LED2; - } - else - { - return; - } - - stm32_gpiowrite(ledcfg, ledon); -} - -/**************************************************************************** - * Name: board_userled_all - ****************************************************************************/ - -void board_userled_all(uint32_t ledset) -{ - bool ledon; - - ledon = ((ledset & BOARD_LED1_BIT) != 0); - stm32_gpiowrite(GPIO_LED1, ledon); - - ledon = ((ledset & BOARD_LED2_BIT) != 0); - stm32_gpiowrite(GPIO_LED2, ledon); -} - -#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt deleted file mode 100644 index 0b290a9db7311..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig deleted file mode 100644 index fc5c0296bf715..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ /dev/null @@ -1,58 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_DISABLE_ENVIRON is not set -# CONFIG_DISABLE_POSIX_TIMERS is not set -# CONFIG_NSH_DISABLEBG is not set -# CONFIG_NSH_DISABLESCRIPT is not set -# CONFIG_NSH_DISABLE_EXEC is not set -# CONFIG_NSH_DISABLE_EXIT is not set -# CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_IFCONFIG is not set -# CONFIG_NSH_DISABLE_LOSETUP is not set -# CONFIG_NSH_DISABLE_MKRD is not set -# CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PUT is not set -# CONFIG_NSH_DISABLE_WGET is not set -# CONFIG_NSH_DISABLE_XD is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="stm32vldiscovery" -CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F100RB=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=2398 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEFAULT_SMALL=y -CONFIG_IDLETHREAD_STACKSIZE=128 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=768 -CONFIG_INTELHEX_BINARY=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_PTHREAD_STACK_DEFAULT=128 -CONFIG_PTHREAD_STACK_MIN=128 -CONFIG_RAM_SIZE=8192 -CONFIG_RAM_START=0x20000000 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STDIO_BUFFER_SIZE=0 -CONFIG_STM32_BKP=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_RTC=y -CONFIG_STM32_USART1=y -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_RXBUFSIZE=128 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_USART1_TXBUFSIZE=128 diff --git a/boards/arm/stm32/stm32vldiscovery/include/board.h b/boards/arm/stm32/stm32vldiscovery/include/board.h deleted file mode 100644 index 2d6b6419de449..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/include/board.h +++ /dev/null @@ -1,142 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* On-board crystal frequency is 8MHz (HSE) */ - -#define STM32_BOARD_XTAL 8000000ul - -/* PLL source is HSE / 1, - * PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz - */ - -#define STM32_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1d1 -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC -#define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx3 -#define STM32_PLL_FREQUENCY (3 * STM32_BOARD_XTAL) - -/* Use the PLL and set the SYSCLK source to be the PLL */ - -#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL -#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* AHB clock (HCLK) is SYSCLK (24MHz) */ - -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY - -/* APB2 clock (PCLK2) is HCLK (24MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK -#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB2 timers (1, 15-17) will receive PCLK2. */ - -#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY - -/* APB1 clock (PCLK1) is HCLK (24MHz) */ - -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK -#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY - -/* APB1 timers (2-7, 12-14) will receive PCLK1. */ - -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM12_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM13_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM14_CLKIN STM32_PCLK1_FREQUENCY - -/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx - * otherwise frequency is 2xAPBx. - * Note: TIM1,15-17 are on APB2, others on APB1 - */ - -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY - -/* LED definitions **********************************************************/ - -/* It is assumed that a generic board has 1 LED. Thus only two different - * states can be shown. Statuses defined as "1" will light the LED, the - * ones defined as "0" will turn the LED off. - */ - -#define LED_STARTED 1 -#define LED_HEAPALLOCATE 1 -#define LED_IRQSENABLED 1 -#define LED_STACKCREATED 1 -#define LED_INIRQ 1 -#define LED_SIGNAL 1 -#define LED_ASSERTION 0 -#define LED_PANIC 0 - -/* Button definitions *******************************************************/ - -/* It is assumed that a generic board has 1 button. */ - -#define BUTTON_0 0 - -#define NUM_BUTTONS 1 - -#define BUTTON_0_BIT (1 << BUTTON_0) - -/* Alternate function pin selections ****************************************/ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -#endif /* __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs deleted file mode 100644 index aba039baff4c1..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32vldiscovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = stm32vldiscovery.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt deleted file mode 100644 index ee0a0879fcae5..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c) - -target_sources(board PRIVATE ${SRCS}) - -set_property(GLOBAL PROPERTY LD_SCRIPT - "${NUTTX_BOARD_DIR}/scripts/stm32vldiscovery.ld") diff --git a/boards/arm/stm32/stm32vldiscovery/src/Make.defs b/boards/arm/stm32/stm32vldiscovery/src/Make.defs deleted file mode 100644 index 9eef1f9e16dac..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/Make.defs +++ /dev/null @@ -1,29 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32vldiscovery/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c deleted file mode 100644 index cbdbe7788a83a..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "arm_internal.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - stm32_led_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c deleted file mode 100644 index bf078df319d9b..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifdef CONFIG_FS_PROCFS -# include -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_USERLED -# include -#endif - -#include "stm32.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_INPUT_BUTTONS - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_USERLED - /* Register the LED driver */ - - ret = userled_lower_initialize("/dev/userleds"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - - return ret; -} diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c deleted file mode 100644 index e5e62a4fa3428..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32vldiscovery.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - stm32_configgpio(GPIO_BTN_0); /* Configure the GPIO pins as inputs. */ - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - - ret = (stm32_gpioread(GPIO_BTN_0) == false ? 1 : 0); - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - if (id == 0) - { - ret = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c deleted file mode 100644 index 0bb0c88732a86..0000000000000 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c +++ /dev/null @@ -1,79 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32vldiscovery.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void stm32_led_initialize(void) -{ - stm32_configgpio(GPIO_LED1); /* Configure LED1 GPIO for output */ -} - -/**************************************************************************** - * Name: board_autoled_on - ****************************************************************************/ - -void board_autoled_on(int led) -{ - if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, true); - } -} - -/**************************************************************************** - * Name: board_autoled_off - ****************************************************************************/ - -void board_autoled_off(int led) -{ - if (led == 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } -} - -#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt deleted file mode 100644 index 4fc77f37f5d26..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig deleted file mode 100644 index 431ff572a077f..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_FT80X=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_FT80X=y -CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=24 -CONFIG_START_MONTH=2 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_SPI1=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig deleted file mode 100644 index 4b412ea8f066e..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F103VC=y -CONFIG_ARCH_HIPRI_INTERRUPT=y -CONFIG_ARCH_RAMVECTORS=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="highpri_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=22 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2013 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_TIM6=y -CONFIG_STM32_USART1=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y -CONFIG_VIEWTOOL_HIGHPRI=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig deleted file mode 100644 index c71355f280664..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" -CONFIG_NET=y -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDB_DNSSERVER_NOADDR=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_DHCPC=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NETUTILS_TFTPC=y -CONFIG_NETUTILS_WEBCLIENT=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_NET_ICMPv6_SOCKET=y -CONFIG_NET_IPv6=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_ROUTE=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=23 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING6=y -CONFIG_SYSTEM_PING=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig deleted file mode 100644 index 1f9679122ed30..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_WINDOWS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=192 -CONFIG_SCHED_HPWORKSTACKSIZE=1024 -CONFIG_START_DAY=21 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2009 -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig deleted file mode 100644 index f9a2ca62b57af..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="arm" -CONFIG_ARCH_BOARD="viewtool-stm32f107" -CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" -CONFIG_ARCH_CHIP_STM32F1=y -CONFIG_ARCH_CHIP_STM32F107VC=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=5483 -CONFIG_BUILTIN=y -CONFIG_ETH0_PHY_DP83848C=y -CONFIG_EXAMPLES_TCPBLASTER=y -CONFIG_FS_PROCFS=y -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=50 -CONFIG_IOB_NCHAINS=12 -CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" -CONFIG_LIBM=y -CONFIG_NET=y -CONFIG_NETINIT_NOMAC=y -CONFIG_NETINIT_THREAD=y -CONFIG_NETUTILS_TELNETD=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_MAX_LISTENPORTS=40 -CONFIG_NET_ROUTE=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_STATISTICS=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_PREALLOC_CONNS=40 -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RAM_SIZE=65536 -CONFIG_RAM_START=0x20000000 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_LPWORKPRIORITY=120 -CONFIG_START_DAY=23 -CONFIG_STM32_ETHMAC=y -CONFIG_STM32_JTAG_FULL_ENABLE=y -CONFIG_STM32_PHYSR=16 -CONFIG_STM32_PHYSR_100MBPS=0x0000 -CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 -CONFIG_STM32_PHYSR_MODE=0x0004 -CONFIG_STM32_PHYSR_SPEED=0x0002 -CONFIG_STM32_PWR=y -CONFIG_STM32_RMII_EXTCLK=y -CONFIG_STM32_USART1=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board.h b/boards/arm/stm32/viewtool-stm32f107/include/board.h deleted file mode 100644 index 28494c647ccc1..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/include/board.h +++ /dev/null @@ -1,166 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H -#define __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ -# include -#endif - -/* Clocking *****************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) -# include -#else -# error Unrecognized STM32 chip -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* LED definitions **********************************************************/ - -/* There are four LEDs on the ViewTool STM32F103/F107 board that can be - * controlled by software: LED1 through LED4. All pulled high and can be - * illuminated by driving the output to low - * - * LED1 PA6 - * LED2 PA7 - * LED3 PB12 - * LED4 PB13 - */ - -/* LED index values for use with board_userled() */ - -#define BOARD_LED1 0 -#define BOARD_LED2 1 -#define BOARD_LED3 2 -#define BOARD_LED4 3 -#define BOARD_NLEDS 4 - -/* LED bits for use with board_userled_all() */ - -#define BOARD_LED1_BIT (1 << BOARD_LED1) -#define BOARD_LED2_BIT (1 << BOARD_LED2) -#define BOARD_LED3_BIT (1 << BOARD_LED3) -#define BOARD_LED4_BIT (1 << BOARD_LED4) - -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is - * defined. In that case, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode - * OS-related events as follows: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - */ -#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ -#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ -#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF OFF */ -#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON OFF */ -#define LED_INIRQ 4 /* In an interrupt N/C N/C N/C GLOW */ -#define LED_SIGNAL 4 /* In a signal handler N/C N/C N/C GLOW */ -#define LED_ASSERTION 4 /* An assertion failed N/C N/C N/C GLOW */ -#define LED_PANIC 4 /* The system has crashed N/C N/C N/C FLASH */ -#undef LED_IDLE /* MCU is in sleep mode Not used */ - -/* After booting, LED1-3 are not longer used by the system and can be used - * for other purposes by the application (Of course, all LEDs are available - * to the application if CONFIG_ARCH_LEDS is not defined. - */ - -/* Buttons ******************************************************************/ - -/* All pulled high and will be sensed low when depressed. - * - * SW2 PC11 Needs J42 closed - * SW3 PC12 Needs J43 closed - * SW4 PA0 Needs J44 closed - */ - -#define BUTTON_SW2 0 -#define BUTTON_SW3 1 -#define BUTTON_SW4 2 -#define NUM_BUTTONS 3 - -#define BUTTON_SW2_BIT (1 << BUTTON_SW2) -#define BUTTON_SW3_BIT (1 << BUTTON_SW3) -#define BUTTON_SW4_BIT (1 << BUTTON_SW4) - -/* Alternate function pin selections (auto-aliased for new pinmap) */ - -/* USART1 */ - -#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) -#define GPIO_USART1_RX GPIO_USART1_RX_0 - -/* SPI1 */ - -#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) -#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) - -/* MCO */ - -#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) - -/* Ethernet (MII/RMII) */ - -#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 -#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 -#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 -#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 -#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 -#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 -#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 -#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 -#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 -#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 -#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) -#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 -#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 -#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 -#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 -#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) -#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) - -/* TIM6 has no GPIO pins (basic timer) */ - -#endif /* __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs deleted file mode 100644 index 1aa5da98b3fde..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs +++ /dev/null @@ -1,46 +0,0 @@ -############################################################################ -# boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = dfu.ld -else - LDSCRIPT = flash.ld -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld b/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld deleted file mode 100644 index 8dda638806342..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld b/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld deleted file mode 100644 index 5cd741cedc89c..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld +++ /dev/null @@ -1,118 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K - sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > flash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > flash - - .ARM.extab : { - *(.ARM.extab*) - } > flash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > flash - __exidx_end = ABSOLUTE(.); - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } > flash - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } > flash - - _eronly = ABSOLUTE(.); - - /* The RAM vector table (if present) should lie at the beginning of SRAM */ - - .ram_vectors : { - *(.ram_vectors) - } > sram - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > sram AT > flash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt deleted file mode 100644 index c994fa4536ce5..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt +++ /dev/null @@ -1,79 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c) - -if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) -endif() - -if(CONFIG_MMCSD) - list(APPEND SRCS stm32_mmcsd.c) -endif() - -if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_usbdev.c) -else() - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() -endif() - -if(CONFIG_INPUT_ADS7843E) - list(APPEND SRCS stm32_ads7843e.c) -endif() - -if(CONFIG_LCD_SSD1289) - list(APPEND SRCS stm32_ssd1289.c) -endif() - -if(CONFIG_USBMSC) - list(APPEND SRCS stm32_usbmsc.c) -endif() - -if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) -endif() - -if(CONFIG_VIEWTOOL_HIGHPRI) - list(APPEND SRCS stm32_highpri.c) -endif() - -if(CONFIG_VIEWTOOL_FT80X_SPI1) - list(APPEND SRCS stm32_ft80x.c) -elseif(CONFIG_VIEWTOOL_FT80X_SPI2) - list(APPEND SRCS stm32_ft80x.c) -endif() - -if(CONFIG_VIEWTOOL_MAX3421E_SPI1) - list(APPEND SRCS stm32_max3421e.c) -elseif(CONFIG_VIEWTOOL_MAX3421E_SPI2) - list(APPEND SRCS stm32_max3421e.c) -endif() - -target_sources(board PRIVATE ${SRCS}) - -if(CONFIG_STM32_DFU) - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dfu.ld") -else() - set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") -endif() diff --git a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs b/boards/arm/stm32/viewtool-stm32f107/src/Make.defs deleted file mode 100644 index 260a9270b30a2..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs +++ /dev/null @@ -1,77 +0,0 @@ -############################################################################ -# boards/arm/stm32/viewtool-stm32f107/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c - -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can.c -endif - -ifeq ($(CONFIG_MMCSD),y) -CSRCS += stm32_mmcsd.c -endif - -ifeq ($(CONFIG_STM32_OTGFS),y) # F107 -CSRCS += stm32_usbdev.c -else -ifeq ($(CONFIG_STM32_USB),y) # F103 -CSRCS += stm32_usbdev.c -endif -endif - -ifeq ($(CONFIG_INPUT_ADS7843E),y) # F103 -CSRCS += stm32_ads7843e.c -endif - -ifeq ($(CONFIG_LCD_SSD1289),y) # F103 -CSRCS += stm32_ssd1289.c -endif - -ifeq ($(CONFIG_USBMSC),y) -CSRCS += stm32_usbmsc.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) -CSRCS += stm32_buttons.c -endif - -ifeq ($(CONFIG_VIEWTOOL_HIGHPRI),y) -CSRCS += stm32_highpri.c -endif - -ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI1),y) -CSRCS += stm32_ft80x.c -else ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI2),y) -CSRCS += stm32_ft80x.c -endif - -ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI1),y) -CSRCS += stm32_max3421e.c -else ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI2),y) -CSRCS += stm32_max3421e.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c deleted file mode 100644 index c7eada920982f..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "arm_internal.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void stm32_boardinitialize(void) -{ - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak - * function stm32_spidev_initialize() has been brought into the link. - */ - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - if (stm32_spidev_initialize) - { - stm32_spidev_initialize(); - } -#endif - - /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbdev_initialize() has been - * brought into the build. - */ - -#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBDEV) - if (stm32_usbdev_initialize) - { - stm32_usbdev_initialize(); - } -#endif - - /* Configure on-board LEDs (unconditionally). */ - - stm32_led_initialize(); -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - stm32_bringup(); -} -#endif diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c deleted file mode 100644 index c9cfd7c659111..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c +++ /dev/null @@ -1,202 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#ifdef CONFIG_RTC_DRIVER -# include -# include "stm32_rtc.h" -#endif - -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_SENSORS_MPL115A -#include "stm32_mpl115a.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Default MMC/SD SLOT number */ - -#ifdef HAVE_MMCSD -# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != VIEWTOOL_MMCSD_SLOTNO -# error "Only one MMC/SD slot: VIEWTOOL_MMCSD_SLOTNO" -# undef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO -# endif - -# ifndef CONFIG_NSH_MMCSDSLOTNO -# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO -# endif -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_driver_initialize - * - * Description: - * Initialize and register the RTC driver. - * - ****************************************************************************/ - -#ifdef HAVE_RTC_DRIVER -static int rtc_driver_initialize(void) -{ - struct rtc_lowerhalf_s *lower; - int ret; - - /* Instantiate the STM32 lower-half RTC driver */ - - lower = stm32_rtc_lowerhalf(); - if (lower == NULL) - { - serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); - ret = -ENOMEM; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - if (ret < 0) - { - serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); - } - } - - return ret; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - ****************************************************************************/ - -int stm32_bringup(void) -{ - int ret; - -#ifdef HAVE_RTC_DRIVER - ret = rtc_driver_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: rtc_driver_initialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - serr("ERROR: Failed to mount procfs at %s: %d\n", - STM32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef HAVE_MMCSD - ret = stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_sdinitialize failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_INPUT_ADS7843E - /* Initialize the touchscreen */ - - ret = stm32_tsc_setup(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_STM32_CAN_CHARDRIVER - /* Initialize CAN and register the CAN driver. */ - - ret = stm32_can_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_MPL115A - ret = board_mpl115a_initialize(0, 5); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_mpl115ainitialize failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) - ret = stm32_ft80x_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) - ret = stm32_max3421e_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); - } -#endif - - UNUSED(ret); - return OK; -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c deleted file mode 100644 index 38d6fbedecf79..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_ARCH_BUTTONS - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Pin configuration for each STM3210E-EVAL button. This array is indexed by - * the BUTTON_* and JOYSTICK_* definitions in board.h - */ - -static const uint32_t g_buttons[NUM_BUTTONS] = -{ - GPIO_SW2, GPIO_SW3, GPIO_SW4 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - int i; - - /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are - * configured for some pins but NOT used in this file - */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - stm32_configgpio(g_buttons[i]); - } - - return NUM_BUTTONS; -} - -/**************************************************************************** - * Name: board_buttons - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint32_t ret = 0; - int i; - - /* Check that state of each key */ - - for (i = 0; i < NUM_BUTTONS; i++) - { - /* A LOW value means that the key is pressed for most keys. The - * exception is the WAKEUP button. - */ - - bool released = stm32_gpioread(g_buttons[i]); - - /* Accumulate the set of depressed (not released) keys */ - - if (!released) - { - ret |= (1 << i); - } - } - - return ret; -} - -/**************************************************************************** - * Button support. - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. board_buttons() returns an - * 32-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning - * of each bit. - * - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See - * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of - * enumeration value. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret = -EINVAL; - - /* The following should be atomic */ - - if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) - { - ret = stm32_gpiosetevent(g_buttons[id], true, true, true, - irqhandler, arg); - } - - return ret; -} -#endif -#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c deleted file mode 100644 index ae2e41e792cf1..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c +++ /dev/null @@ -1,103 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_can.h" - -#ifdef CONFIG_CAN - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* The STM32F107VC supports CAN1 and CAN2 */ - -#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) -# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." -# undef CONFIG_STM32_CAN2 -#endif - -#ifdef CONFIG_STM32_CAN1 -# define CAN_PORT 1 -#else -# define CAN_PORT 2 -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_can_setup - * - * Description: - * Initialize CAN and register the CAN device - * - ****************************************************************************/ - -int stm32_can_setup(void) -{ -#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) - struct can_dev_s *can; - int ret; - - /* Call stm32_caninitialize() to get an instance of the CAN interface */ - - can = stm32_caninitialize(CAN_PORT); - if (can == NULL) - { - canerr("ERROR: Failed to get CAN interface\n"); - return -ENODEV; - } - - /* Register the CAN driver at "/dev/can0" */ - - ret = can_register("/dev/can0", can); - if (ret < 0) - { - canerr("ERROR: can_register failed: %d\n", ret); - return ret; - } - - return OK; -#else - return -ENODEV; -#endif -} - -#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c deleted file mode 100644 index b9d97434c7732..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c +++ /dev/null @@ -1,277 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "ram_vectors.h" -#include "stm32_tim.h" - -#include "viewtool_stm32f107.h" - -#include - -#ifdef CONFIG_VIEWTOOL_HIGHPRI - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_ARCH_CHIP_STM32F103VC -# warning This only only been verified with CONFIG_ARCH_CHIP_STM32F103VC -#endif - -#ifndef CONFIG_ARCH_HIPRI_INTERRUPT -# error CONFIG_ARCH_HIPRI_INTERRUPT is required -#endif - -#ifndef CONFIG_ARCH_RAMVECTORS -# error CONFIG_ARCH_RAMVECTORS is required -#endif - -#ifndef CONFIG_STM32_TIM6 -# error CONFIG_STM32_TIM6 is required -#endif - -#ifndef CONFIG_VIEWTOOL_TIM6_FREQUENCY -# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_APB1_TIM6_CLKIN -# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#endif - -#ifndef CONFIG_VIEWTOOL_TIM6_PERIOD -# warning CONFIG_VIEWTOOL_TIM6_PERIOD defaulting to 1MS -# define CONFIG_VIEWTOOL_TIM6_PERIOD (CONFIG_VIEWTOOL_TIM6_FREQUENCY / 1000) -#endif - -#ifndef CONFIG_ARCH_IRQPRIO -# error CONFIG_ARCH_IRQPRIO is required -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct highpri_s -{ - struct stm32_tim_dev_s *dev; /* TIM6 driver instance */ - volatile uint64_t basepri[16]; - volatile uint64_t handler; - volatile uint64_t thread; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct highpri_s g_highpri; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static inline_function bool is_nesting_interrupt(void) -{ - return up_interrupt_context(); -} - -/**************************************************************************** - * Name: tim6_handler - * - * Description: - * This is the handler for the high speed TIM6 interrupt. - * - ****************************************************************************/ - -void tim6_handler(void) -{ - uint8_t basepri; - int index; - - /* Acknowledge the timer interrupt */ - - STM32_TIM_ACKINT(g_highpri.dev, ATIM_SR_UIF); - - /* Increment the count associated with the current basepri */ - - basepri = getbasepri(); - index = ((basepri >> 4) & 15); - g_highpri.basepri[index]++; - - /* Check if we are in an interrupt handle */ - - if (is_nesting_interrupt()) - { - g_highpri.handler++; - } - else - { - g_highpri.thread++; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: highpri_main - * - * Description: - * Main entry point in into the high priority interrupt test. - * - ****************************************************************************/ - -int highpri_main(int argc, char *argv[]) -{ - struct stm32_tim_dev_s *dev; - uint64_t basepri[16]; - uint64_t handler; - uint64_t thread; - uint64_t total; - uint32_t seconds; - int prescaler; - int ret; - int i; - - printf("highpri_main: Started\n"); - - /* Configure basic timer TIM6 and enable interrupts */ - - dev = stm32_tim_init(6); - if (!dev) - { - fprintf(stderr, "highpri_main: ERROR: stm32_tim_init(6) failed\n"); - return EXIT_FAILURE; - } - - g_highpri.dev = dev; - - prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); - printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", - (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, - prescaler); - - STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); - printf("TIM6 period=%d cycles; interrupt rate=%d Hz\n", - CONFIG_VIEWTOOL_TIM6_PERIOD, - CONFIG_VIEWTOOL_TIM6_FREQUENCY / CONFIG_VIEWTOOL_TIM6_PERIOD); - - /* Attach TIM6 ram vector */ - - ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", - ret); - return EXIT_FAILURE; - } - - /* Set the priority of the TIM6 interrupt vector */ - - ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); - if (ret < 0) - { - fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", - ret); - return EXIT_FAILURE; - } - - /* Enable the timer interrupt at the NVIC and at TIM6 */ - - up_enable_irq(STM32_IRQ_TIM6); - STM32_TIM_ENABLEINT(dev, ATIM_DIER_UIE); - - /* Monitor interrupts */ - - seconds = 0; - for (; ; ) - { - /* Flush stdout and wait a bit */ - - fflush(stdout); - nxsched_sleep(1); - seconds++; - - /* Sample counts so that they are not volatile. Missing a count now - * and then is a normal consequence of this design. - */ - - for (i = 0; i < 16; i++) - { - basepri[i] = g_highpri.basepri[i]; - } - - handler = g_highpri.handler; - thread = g_highpri.thread; - - /* Then print out what is happening */ - - printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); - for (i = 0, total = 0; i < 16; i++) - { - total += basepri[i]; - } - - if (total > 0) - { - for (i = 0; i < 16; i++) - { - if (basepri[i] > 0) - { - printf(" basepri[%02x]: %lld (%d%%)\n", - i << 4, basepri[i], - (int)((100 * basepri[i] + (total / 2)) / total)); - } - } - } - - total = handler + thread; - if (total > 0) - { - printf(" Handler: %lld (%d%%)\n", - handler, (int)((100*handler + (total / 2)) / total)); - printf(" Thread: %lld (%d%%)\n\n", - thread, (int)((100*thread + (total / 2)) / total)); - } - } - - return EXIT_SUCCESS; -} - -#endif /* CONFIG_VIEWTOOL_HIGHPRI */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c deleted file mode 100644 index fb495d7e018e7..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c +++ /dev/null @@ -1,280 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_gpio.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: led_onbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_onbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, false); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, false); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, false); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, false); - } -} - -/**************************************************************************** - * Name: led_offbits - * - * Description: - * Clear all LEDs to the bit encoded state - * - ****************************************************************************/ - -static void led_offbits(unsigned int clrbits) -{ - if ((clrbits & BOARD_LED1_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED1, true); - } - - if ((clrbits & BOARD_LED2_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED2, true); - } - - if ((clrbits & BOARD_LED3_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED3, true); - } - - if ((clrbits & BOARD_LED4_BIT) != 0) - { - stm32_gpiowrite(GPIO_LED4, true); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_led_initialize - * - * Description: - * Configure LEDs. LEDs are left in the OFF state. - * - ****************************************************************************/ - -void stm32_led_initialize(void) -{ - /* Configure LED1-4 GPIOs for output. Initial state is OFF */ - - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); -} - -/**************************************************************************** - * Name: board_autoled_on - * - * Description: - * Select the "logical" ON state: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - * LED_STARTED 0 NuttX has been started ON OFF OFF OFF - * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF - * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF - * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF - * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW - * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW - * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW - * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH - * ED_IDLE MCU is in sleep mode Not used - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_on(int led) -{ - switch (led) - { - case 0: - led_offbits(BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED1_BIT); - break; - - case 1: - led_offbits(BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED2_BIT); - break; - - case 2: - led_offbits(BOARD_LED3_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED1_BIT | BOARD_LED2_BIT); - break; - - case 3: - led_offbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); - led_onbits(BOARD_LED3_BIT); - break; - - case 4: - stm32_gpiowrite(GPIO_LED4, false); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_autoled_off - * - * Description: - * Select the "logical" OFF state: - * - * SYMBOL Val Meaning LED state - * LED1 LED2 LED3 LED4 - * ----------------- --- ----------------------- ---- ---- ---- ---- - * LED_STARTED 0 NuttX has been started ON OFF OFF OFF - * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF - * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF - * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF - * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW - * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW - * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW - * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH - * ED_IDLE MCU is in sleep mode Not used - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_LEDS -void board_autoled_off(int led) -{ - switch (led) - { - case 0: - case 1: - case 2: - case 3: - break; - - case 4: - stm32_gpiowrite(GPIO_LED4, true); - break; - } -} -#endif - -/**************************************************************************** - * Name: board_userled_initialize, board_userled, and board_userled_all - * - * Description: - * These interfaces allow user control of the board LEDs. - * - * If CONFIG_ARCH_LEDS is defined, then NuttX will control both on-board - * LEDs up until the completion of boot. The it will continue to control - * LED2; LED1 is available for application use. - * - * If CONFIG_ARCH_LEDS is not defined, then both LEDs are available for - * application use. - * - ****************************************************************************/ - -uint32_t board_userled_initialize(void) -{ - /* Already initialized by stm32_led_initialize */ - - return BOARD_NLEDS; -} - -void board_userled(int led, bool ledon) -{ - uint32_t pinset; - - switch (led) - { - case BOARD_LED1: - pinset = GPIO_LED1; - break; - - case BOARD_LED2: - pinset = GPIO_LED2; - break; - - case BOARD_LED3: - pinset = GPIO_LED3; - break; - - case BOARD_LED4: -#ifndef CONFIG_ARCH_LEDS - pinset = GPIO_LED4; - break; -#endif - default: - return; - } - - stm32_gpiowrite(pinset, !ledon); -} - -void board_userled_all(uint32_t ledset) -{ -#ifdef CONFIG_ARCH_LEDS - led_onbits(ledset & ~BOARD_LED4_BIT); - led_offbits(~(ledset | BOARD_LED4_BIT)); -#else - led_onbits(ledset); - led_offbits(~ledset); -#endif -} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c deleted file mode 100644 index 7720b136bfd1d..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "stm32_sdio.h" -#include "viewtool_stm32f107.h" - -/* Only the STM32F103 supports the SDIO interface */ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#define HAVE_MMCSD 1 /* Assume that we have SD support */ -#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ - -/* Can't support MMC/SD features if the SDIO peripheral is disabled */ - -#ifndef CONFIG_STM32_SDIO -# undef HAVE_MMCSD -#endif - -/* Can't support MMC/SD features if mountpoints are disabled */ - -#ifdef CONFIG_DISABLE_MOUNTPOINT -# undef HAVE_MMCSD -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_sdinitialize - * - * Description: - * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n - * and CONFIG_STM32_SDIO=y - * - ****************************************************************************/ - -int stm32_sdinitialize(int minor) -{ -#ifdef HAVE_MMCSD - struct sdio_dev_s *sdio; - int ret; - - /* Configure the card-detect GPIO */ -#warning REVISIT: Missing logic - - /* First, get an instance of the SDIO interface */ - - sdio = sdio_initialize(STM32_MMCSDSLOTNO); - if (!sdio) - { - ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); - return -ENODEV; - } - - finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); - - /* Now bind the SDIO interface to the MMC/SD driver */ - - ret = mmcsd_slotinitialize(minor, sdio); - if (ret != OK) - { - ferr("ERROR:"); - ferr("Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - } - - finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", - STM32_MMCSDSLOTNO, minor); - - /* Then let's guess and say that there is a card in the slot. I need to - * check to see if the M3 Wildfire board supports a GPIO to detect if there - * is a card in the slot. - */ -#warning REVISIT: Need to read the current state of the card-detect pin -#warning REVISIT: Need to support interrupts from the card-detect pin - sdio_mediachange(sdio, true); -#endif - return OK; -} - -#endif /* CONFIG_ARCH_CHIP_STM32F103VC */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c deleted file mode 100644 index 317acedc80942..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c +++ /dev/null @@ -1,210 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "viewtool_stm32f107.h" - -#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spidev_initialize - * - * Description: - * Called to configure SPI chip select GPIO pins for the Viewtool - * stm32f103/107 board. - * - ****************************************************************************/ - -void weak_function stm32_spidev_initialize(void) -{ - /* NOTE: Clocking for SPIx was already provided in stm32_rcc.c. - * Configurations of SPI pins is performed in stm32_spi.c. - * Here, we only initialize chip select pins unique to the board - * architecture. - */ - -#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_INPUT_ADS7843E) - /* Configure the XPT2046 SPI2 CS pin as an output */ - - stm32_configgpio(GPIO_LCDTP_CS); -#endif - -#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_SENSORS_MPL115A) - /* Configure the MPL115A SPI3 CS pin as an output */ - - stm32_configgpio(GPIO_MPL115A_CS); -#endif - -#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) - /* Configure the FT80x CS pin as an input */ - - stm32_configgpio(GPIO_FT80X_CS); -#endif - -#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) - /* Configure the MAX3421E CS pin as an input */ - - stm32_configgpio(GPIO_MAX3421E_CS); -#endif -} - -/**************************************************************************** - * Name: stm32_spi1/2/3select and stm32_spi1/2/3status - * - * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status - * must be provided by board-specific logic. They are implementations of - * the select and status methods of the SPI interface defined by struct - * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions - * in your board-specific logic. These functions will perform chip - * selection and status operations using GPIOs in the way your board is - * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to - * bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_VIEWTOOL_FT80X_SPI1 - /* Select/de-select the FT80x */ - - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_FT80X_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI1 - /* Select/de-select the MAX3421E */ - - if (devid == SPIDEV_USBHOST(0)) - { - stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); - } - else -#endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } -} - -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); - -#ifdef CONFIG_INPUT_ADS7843E - /* Select/de-select the touchscreen */ - - if (devid == SPIDEV_TOUCHSCREEN(0)) - { - stm32_gpiowrite(GPIO_LCDTP_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_FT80X_SPI2 - /* Select/de-select the FT80x */ - - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_FT80X_CS, !selected); - } - else -#endif -#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI2 - /* Select/de-select the MAX3421E */ - - if (devid == SPIDEV_USBHOST(0)) - { - stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); - } - else -#endif - { - spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); - } -} - -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, - uint32_t devid, bool selected) -{ - spiinfo("devid: %d CS: %s\n", - (int)devid, selected ? "assert" : "de-assert"); -} - -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) -{ - return 0; -} -#endif - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3*/ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c deleted file mode 100644 index 527956b6f1dfe..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c +++ /dev/null @@ -1,568 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32.h" -#include "viewtool_stm32f107.h" - -#ifdef CONFIG_LCD_SSD1289 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_STM32_FSMC -# error "CONFIG_STM32_FSMC is required to use the LCD" -#endif - -/* Color depth and format */ - -#define LCD_BPP 16 -#define LCD_COLORFMT FB_FMT_RGB16_565 - -/* Display Resolution */ - -#if defined(CONFIG_LCD_LANDSCAPE) -# define LCD_XRES 320 -# define LCD_YRES 240 -#else -# define LCD_XRES 240 -# define LCD_YRES 320 -#endif - -#define LCD_BL_TIMER_PERIOD 8999 - -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip - * select signal - */ - -/* RS <==> A16 */ - -#define LCD_INDEX 0x60000000 /* RS = 0 */ -#define LCD_DATA 0x60020000 /* RS = 1 */ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Low Level LCD access */ - -static void stm32_select(struct ssd1289_lcd_s *dev); -static void stm32_deselect(struct ssd1289_lcd_s *dev); -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev); -#endif -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* LCD - * - * An LCD may be connected via J11. Only the STM32F103 supports the FSMC - * signals needed to drive the LCD. - * - * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, - * and (a) a XPT2046 touch screen controller. - * - * LCD Connector - * ------------- - * - * ------------------------- --------------------- --------------- - * Connector J11 GPIO CONFIGURATION(s) - * PIN SIGNAL LEGEND (F103 only) LCD Module - * --- --------- ----------- --------------------- --------------- - * 1 VDD_5 NC N/A 5V --- - * 2 GND GND N/A GND --- - * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D - * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D - * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D - * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D - * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D - * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D - * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D - * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D - * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D - * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D - * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D - * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D - * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D - * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D - * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D - * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D - * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D - * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D - * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D - * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D - * 23 PB1 LCD_RESET (GPIO) RESET HY32D - * 24 N/C NC N/A TE (unused?) - * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 - * (Drives LCD backlight) - * 26 GND BL_GND N/A BLGND CA6219 - * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 - * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 - * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 - * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 - * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 - * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 - * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- - * 34 GND GND N/A GND --- - * --- --------- ----------- --------------------- --------------- - * - * NOTES: - * 1) Only the F103 version of the board supports the FSMC - * 2) No remap - * 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately): - * - * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input - * (active LOW) - * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input - * So will chip enable to either LCD_CS or - * Flash_CS. - * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output - * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output - * - * Truth Table: - * 1E\ 1A0 1A1 1Y0 1Y1 - * --- --- --- --- --- - * HI N/A N/A HI HI - * LO LO LO LO HI - * LO HI LO HI LO - */ - -const uint16_t fsmc_gpios[] = -{ - /* A16... A23. REVISIT: only A16 is used by the LCD */ - - GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, - GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, - - /* D0... D15 */ - - GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, - GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, - GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, - GPIO_NPS_D15, - - /* NOE, NWE, and NE1 */ - - GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1 -}; - -#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) - -/* This is the driver state structure */ - -static struct ssd1289_lcd_s g_ssd1289 = -{ - .select = stm32_select, - .deselect = stm32_deselect, - .index = stm32_index, -#ifndef CONFIG_SSD1289_WRONLY - .read = stm32_read, -#endif - .write = stm32_write, - .backlight = stm32_backlight -}; - -/* The saved instance of the LCD driver */ - -static struct lcd_dev_s *g_ssd1289drvr; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_select - * - * Description: - * Select the LCD device - * - ****************************************************************************/ - -static void stm32_select(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_deselect - * - * Description: - * De-select the LCD device - * - ****************************************************************************/ - -static void stm32_deselect(struct ssd1289_lcd_s *dev) -{ - /* Does not apply to this hardware */ -} - -/**************************************************************************** - * Name: stm32_index - * - * Description: - * Set the index register - * - ****************************************************************************/ - -static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) -{ - putreg16((uint16_t)index, LCD_INDEX); -} - -/**************************************************************************** - * Name: stm32_read - * - * Description: - * Read LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -#ifndef CONFIG_SSD1289_WRONLY -static uint16_t stm32_read(struct ssd1289_lcd_s *dev) -{ - return getreg16(LCD_DATA); -} -#endif - -/**************************************************************************** - * Name: stm32_write - * - * Description: - * Write LCD data (GRAM data or register contents) - * - ****************************************************************************/ - -static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) -{ - putreg16((uint16_t)data, LCD_DATA); -} - -/**************************************************************************** - * Name: stm32_backlight - * - * Description: - * Enable/disable LCD panel power - * (0: full off - CONFIG_LCD_MAXPOWER: full on). - * Used here to set pwm duty on timer used for backlight. - * - ****************************************************************************/ - -static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) -{ - DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); - - /* Set new power level */ - - if (power > 0) - { - uint32_t duty; - - /* Calculate the new backlight duty. It is a fraction of the timer - * period based on the ration of the current power setting to the - * maximum power setting. - */ - - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * - (uint32_t)power) / CONFIG_LCD_MAXPOWER; - if (duty >= LCD_BL_TIMER_PERIOD) - { - duty = LCD_BL_TIMER_PERIOD - 1; - } - - putreg16((uint16_t)duty, STM32_TIM3_CCR2); - } - else - { - putreg16((uint16_t)0, STM32_TIM3_CCR2); - } -} - -static void init_lcd_backlight(void) -{ - uint16_t ccmr; - uint16_t ccer; - - /* Configure PB5 as TIM3 CH2 output */ - - stm32_configgpio(GPIO_TIM3_CH2OUT); - - /* Enable timer 3 clocking */ - - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - - /* Reset timer 3 */ - - modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); - modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); - - /* Reset the Counter Mode and set the clock division */ - - putreg16(0, STM32_TIM3_CR1); - - /* Set the Autoreload value */ - - putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); - - /* Set the Prescaler value */ - - putreg16(0, STM32_TIM3_PSC); - - /* Generate an update event to reload the Prescaler value immediately */ - - putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); - - /* Disable the Channel 2 */ - - ccer = getreg16(STM32_TIM3_CCER); - ccer &= ~ATIM_CCER_CC2E; - putreg16(ccer, STM32_TIM3_CCER); - - /* Select the Output Compare Mode Bits */ - - ccmr = getreg16(STM32_TIM3_CCMR1); - ccmr &= ATIM_CCMR1_OC2M_MASK; - ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); - - putreg16(0, STM32_TIM3_CCR2); - - /* Select the output polarity level == HIGH */ - - ccer &= ~ATIM_CCER_CC2P; - - /* Enable channel 2 */ - - ccer |= ATIM_CCER_CC2E; - - /* Write the timer configuration */ - - putreg16(ccmr, STM32_TIM3_CCMR1); - putreg16(ccer, STM32_TIM3_CCER); - - /* Set the auto preload enable bit */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - - /* Enable Backlight Timer !!!! */ - - modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); - - /* Dump timer3 registers */ - - lcdinfo("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR)); - lcdinfo("CR1: %04x\n", getreg32(STM32_TIM3_CR1)); - lcdinfo("CR2: %04x\n", getreg32(STM32_TIM3_CR2)); - lcdinfo("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR)); - lcdinfo("DIER: %04x\n", getreg32(STM32_TIM3_DIER)); - lcdinfo("SR: %04x\n", getreg32(STM32_TIM3_SR)); - lcdinfo("EGR: %04x\n", getreg32(STM32_TIM3_EGR)); - lcdinfo("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1)); - lcdinfo("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2)); - lcdinfo("CCER: %04x\n", getreg32(STM32_TIM3_CCER)); - lcdinfo("CNT: %04x\n", getreg32(STM32_TIM3_CNT)); - lcdinfo("PSC: %04x\n", getreg32(STM32_TIM3_PSC)); - lcdinfo("ARR: %04x\n", getreg32(STM32_TIM3_ARR)); - lcdinfo("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1)); - lcdinfo("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2)); - lcdinfo("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); - lcdinfo("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR)); -} - -/**************************************************************************** - * Name: stm32_selectlcd - * - * Description: - * Initialize the memory controller (FSMC) - * - ****************************************************************************/ - -static void stm32_selectlcd(void) -{ - /* Configure new GPIO state */ - - stm32_extmemgpios(fsmc_gpios, NGPIOS); - - /* Enable AHB clocking to the FSMC */ - - stm32_fsmc_enable(); - - /* Bank1 NOR/SRAM control register configuration */ - - putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); - - /* Bank1 NOR/SRAM timing register configuration */ - - putreg32( - FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | - FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | - FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | - FSMC_BTR_ACCMODA, - STM32_FSMC_BTR1); - - /* As ext mode is not active the write timing is ignored!! */ - - putreg32(0xffffffff, STM32_FSMC_BWTR1); - - /* Enable the bank by setting the MBKEN bit */ - - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, - STM32_FSMC_BCR1); - - /* Configure the LCD RESET pin. - * Initial value will take the LCD out of reset - */ - - stm32_configgpio(GPIO_LCD_RESET); -} - -/**************************************************************************** - * Name: stm32_extmemgpios - * - * Description: - * Initialize GPIOs for NOR or SRAM - * - ****************************************************************************/ - -static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) -{ - int i; - - /* Configure GPIOs */ - - for (i = 0; i < ngpios; i++) - { - stm32_configgpio(gpios[i]); - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_lcd_initialize - * - * Description: - * Initialize the LCD video hardware. - * The initial state of the LCD is fully initialized, display memory - * cleared, and the LCD ready to use, but with the power setting at 0 - * (full off). - * - ****************************************************************************/ - -int board_lcd_initialize(void) -{ - /* Only initialize the driver once */ - - if (!g_ssd1289drvr) - { - lcdinfo("Initializing\n"); - - /* Initialize the backlight */ - - init_lcd_backlight(); - - /* Configure GPIO pins and configure the FSMC to support the LCD */ - - stm32_selectlcd(); - - /* Configure and enable the LCD */ - - up_mdelay(50); - g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); - if (!g_ssd1289drvr) - { - lcderr("ERROR: ssd1289_lcdinitialize failed\n"); - return -ENODEV; - } - } - - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); - return OK; -} - -/**************************************************************************** - * Name: board_lcd_getdev - * - * Description: - * Return a a reference to the LCD object for the specified LCD. - * This allows support for multiple LCD devices. - * - ****************************************************************************/ - -struct lcd_dev_s *board_lcd_getdev(int lcddev) -{ - DEBUGASSERT(lcddev == 0); - return g_ssd1289drvr; -} - -/**************************************************************************** - * Name: board_lcd_uninitialize - * - * Description: - * Uninitialize the LCD support - * - ****************************************************************************/ - -void board_lcd_uninitialize(void) -{ - /* Turn the display off */ - - g_ssd1289drvr->setpower(g_ssd1289drvr, 0); -} - -#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c deleted file mode 100644 index c0d3001b33921..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32_otgfs.h" -#include "viewtool_stm32f107.h" - -#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_USB) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_usbdev_initialize - * - * Description: - * Called from stm32_boardinitialize very early in initialization to setup - * USB related GPIO pins for the Viewtool STM32F107 board. - * - ****************************************************************************/ - -void stm32_usbdev_initialize(void) -{ - /* The OTG FS has an internal soft pull-up. - * No GPIO configuration is required - */ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC - stm32_configgpio(GPIO_USB_PULLUP); -#endif -} - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional - * description of this method. Alternatively, if no pull-up GPIO the - * following EXTERN can be redefined to be NULL. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_CHIP_STM32F103VC -int stm32_usbpullup(struct usbdev_s *dev, bool enable) -{ - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); - stm32_gpiowrite(GPIO_USB_PULLUP, !enable); - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume) -{ - uinfo("resume: %d\n", resume); -} - -#endif /* CONFIG_STM32_OTGFS || CONFIG_STM32_USB*/ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c deleted file mode 100644 index 015af8a323d69..0000000000000 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "stm32.h" -#include "viewtool_stm32f107.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 -# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 VIEWTOOL_MMCSD_SLOTNO -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_usbmsc_initialize - * - * Description: - * Perform architecture specific initialization as needed to establish - * the mass storage device that will be exported by the USB MSC device. - * - ****************************************************************************/ - -int board_usbmsc_initialize(int port) -{ - /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initialized. - * In this case, there is nothing further to be done here. - */ - -#if defined(HAVE_MMCSD) && !defined(CONFIG_NSH_BUILTIN_APPS) - return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); -#else - return OK; -#endif -} diff --git a/boards/arm/stm32f1/cloudctrl/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt new file mode 100644 index 0000000000000..63062e3011b14 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/cloudctrl/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/cloudctrl/Kconfig b/boards/arm/stm32f1/cloudctrl/Kconfig similarity index 100% rename from boards/arm/stm32/cloudctrl/Kconfig rename to boards/arm/stm32f1/cloudctrl/Kconfig diff --git a/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig new file mode 100644 index 0000000000000..35a72832e26fc --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="cloudctrl" +CONFIG_ARCH_BOARD_CLOUDCTRL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=1 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYINIT=y +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/cloudctrl/include/board.h b/boards/arm/stm32f1/cloudctrl/include/board.h new file mode 100644 index 0000000000000..df0ae697667cd --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/include/board.h @@ -0,0 +1,409 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. From above, we already have PLL3 input + * frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_KEY1 0 /* Name printed on board */ +#define BUTTON_KEY2 1 +#define BUTTON_KEY3 2 +#define NUM_BUTTONS 3 + +#define BUTTON_USERKEY BUTTON_KEY1 /* Names in schematic */ +#define BUTTON_TAMPER BUTTON_KEY2 +#define BUTTON_WAKEUP BUTTON_KEY3 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) +#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) + +#define BUTTON_USERKEY_BIT BUTTON_KEY1_BIT +#define BUTTON_TAMPER_BIT BUTTON_KEY2_BIT +#define BUTTON_WAKEUP_BIT BUTTON_KEY3_BIT + +/* Relays */ + +#define NUM_RELAYS 2 + +/* Pin selections ***********************************************************/ + +/* Ethernet + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in + * 48 PB11 MII_TX_EN Ethernet PHY RMII mode. + * 51 PB12 MII_TXD0 Ethernet PHY + * 52 PB13 MII_TXD1 Ethernet PHY + * 16 PC1 MII_MDC Ethernet PHY + * 34 PC5 MII_INT Ethernet PHY + * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * + * 67 PA8 MCO DM9161AEP + */ + +#ifdef CONFIG_STM32_ETHMAC +# ifndef CONFIG_STM32_ETH_REMAP +# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" +# endif +# ifndef CONFIG_STM32_RMII +# error "STM32 Ethernet requires CONFIG_STM32_RMII" +# endif +# ifndef CONFIG_STM32_RMII_MCO +# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" +# endif +#endif + +/* USB + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USB_VBUS MINI-USB-AB. JP3 + * 69 PA10 USB_ID MINI-USB-AB. JP5 + * 70 PA11 USB_DM MINI-USB-AB + * 71 PA12 USB_DP MINI-USB-AB + * 95 PB8 USB_PWR Drives USB VBUS + */ + +/* UARTS/USARTS + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 + * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) + */ + +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) +# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" +#endif + +#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) +# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" +#endif + +/* SPI + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" +#endif + +#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) +# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" +#endif + +/* DAC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 29 PA4 DAC_OUT1 To CON5(CN14) + * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 + */ + +/* ADC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) + * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) + * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm32_lcdclear(uint16_t color); + +/**************************************************************************** + * Relay control functions + * + * Description: + * Non-standard functions for relay control from the Shenzhou board. + * + * NOTE: These must match the prototypes in include/nuttx/arch.h + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_RELAYS +void up_relaysinit(void); +void relays_setstat(int relays, bool stat); +bool relays_getstat(int relays); +void relays_setstats(uint32_t relays_stat); +uint32_t relays_getstats(void); +void relays_onoff(int relays, uint32_t mdelay); +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); +void relays_resetmode(int relays); +void relays_powermode(int relays); +void relays_resetmodes(uint32_t relays_stat); +void relays_powermodes(uint32_t relays_stat); +#endif + +/**************************************************************************** + * Chip ID functions + * + * Description: + * Non-standard functions to obtain chip ID information. + * + ****************************************************************************/ + +const char *stm32_getchipid(void); +const char *stm32_getchipid_string(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_CLOUDCTRL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/cloudctrl/scripts/Make.defs b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs new file mode 100644 index 0000000000000..806f4f368af06 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32f1/cloudctrl/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = cloudctrl-dfu.ld +else + LDSCRIPT = cloudctrl.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld index f65e582ac706f..962101f605053 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld index 1d6e63c1ec9ce..edbb31f7bf732 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt new file mode 100644 index 0000000000000..323760288c281 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt @@ -0,0 +1,67 @@ +# ############################################################################## +# boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_chipid.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_RELAYS) + list(APPEND SRCS stm32_relays.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_PHYINIT) + list(APPEND SRCS stm32_phyinit.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/cloudctrl-dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/cloudctrl.ld") +endif() diff --git a/boards/arm/stm32f1/cloudctrl/src/Make.defs b/boards/arm/stm32f1/cloudctrl/src/Make.defs new file mode 100644 index 0000000000000..acb393d7f7e6c --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f1/cloudctrl/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_chipid.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_RELAYS),y) +CSRCS += stm32_relays.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_PHYINIT),y) +CSRCS += stm32_phyinit.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/cloudctrl/src/cloudctrl.h b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h similarity index 99% rename from boards/arm/stm32/cloudctrl/src/cloudctrl.h rename to boards/arm/stm32f1/cloudctrl/src/cloudctrl.h index 58d98fabb4c98..00d0411160c75 100644 --- a/boards/arm/stm32/cloudctrl/src/cloudctrl.h +++ b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/cloudctrl.h + * boards/arm/stm32f1/cloudctrl/src/cloudctrl.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c new file mode 100644 index 0000000000000..dff3cb52e9833 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "cloudctrl.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. The only internal signal for ADC + * testing is the potentiometer input: + * + * ADC1_IN10(PC0) Potentiometer + * + * External signals are also available on CON5 CN14: + * + * ADC_IN8 (PB0) CON5 CN14 Pin2 + * ADC_IN9 (PB1) CON5 CN14 Pin1 + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 /* {10, 8, 9}; */ +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ba9fe2732c09f --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define CLOUDCTRL_LED1 (1 << 0) +#define CLOUDCTRL_LED2 (1 << 1) +#define CLOUDCTRL_LED3 (1 << 2) +#define CLOUDCTRL_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((CLOUDCTRL_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((CLOUDCTRL_LED2|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2|CLOUDCTRL_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((CLOUDCTRL_LED1|CLOUDCTRL_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((CLOUDCTRL_LED3|CLOUDCTRL_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((CLOUDCTRL_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((CLOUDCTRL_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((CLOUDCTRL_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((CLOUDCTRL_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((CLOUDCTRL_LED3) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((CLOUDCTRL_LED3) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((clrbits & CLOUDCTRL_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & CLOUDCTRL_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & CLOUDCTRL_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & CLOUDCTRL_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((setbits & CLOUDCTRL_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & CLOUDCTRL_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & CLOUDCTRL_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((setbits & CLOUDCTRL_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c new file mode 100644 index 0000000000000..20d17470a6d55 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c @@ -0,0 +1,200 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + + /* Initialize and register the W25 FLASH file system. */ + +#ifdef HAVE_W25 + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + +#ifdef HAVE_USBHOST + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + return; + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c new file mode 100644 index 0000000000000..06b2467a8b292 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "cloudctrl.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each cloudctrl button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c new file mode 100644 index 0000000000000..8abfb93176da9 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +const char *stm32_getchipid(void) +{ + static char cpuid[12]; + int i; + + for (i = 0; i < 12; i++) + { + cpuid[i] = getreg8(0x1ffff7e8 + i); + } + + return cpuid; +} + +const char *stm32_getchipid_string(void) +{ + static char cpuid[27]; + int c; + int i; + + for (i = 0, c = 0; i < 12; i++) + { + snprintf(&cpuid[c], sizeof(cpuid) - c, + "%02X", getreg8(0x1ffff7e8 + 11 - i)); + c += 2; + if (i % 4 == 3) + { + cpuid[c++] = '-'; + } + } + + cpuid[26] = '\0'; + return cpuid; +} diff --git a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c similarity index 97% rename from boards/arm/stm32/cloudctrl/src/stm32_phyinit.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c index 26b01ab9810f5..95382ef1a2235 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_phyinit.c + * boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c new file mode 100644 index 0000000000000..e86a2345942c7 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c @@ -0,0 +1,274 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_relays.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "cloudctrl.h" + +#ifdef CONFIG_ARCH_RELAYS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RELAYS_MIN_RESET_TIME 5 +#define RELAYS_RESET_MTIME 5 +#define RELAYS_POWER_MTIME 50 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_relays_stat = 0; +static bool g_relays_init = false; + +static const uint16_t g_relays[NUM_RELAYS] = +{ + GPIO_RELAYS_R00 +#ifdef GPIO_RELAYS_R01 + , GPIO_RELAYS_R01 +#endif +#ifdef GPIO_RELAYS_R02 + , GPIO_RELAYS_R02 +#endif +#ifdef GPIO_RELAYS_R03 + , GPIO_RELAYS_R03 +#endif +#ifdef GPIO_RELAYS_R04 + , GPIO_RELAYS_R04 +#endif +#ifdef GPIO_RELAYS_R05 + , GPIO_RELAYS_R05 +#endif +#ifdef GPIO_RELAYS_R06 + , GPIO_RELAYS_R06 +#endif +#ifdef GPIO_RELAYS_R07 + , GPIO_RELAYS_R07 +#endif +#ifdef GPIO_RELAYS_R08 + , GPIO_RELAYS_R08 +#endif +#ifdef GPIO_RELAYS_R09 + , GPIO_RELAYS_R09 +#endif +#ifdef GPIO_RELAYS_R10 + , GPIO_RELAYS_R10 +#endif +#ifdef GPIO_RELAYS_R11 + , GPIO_RELAYS_R11 +#endif +#ifdef GPIO_RELAYS_R12 + , GPIO_RELAYS_R12 +#endif +#ifdef GPIO_RELAYS_R13 + , GPIO_RELAYS_R13 +#endif +#ifdef GPIO_RELAYS_R14 + , GPIO_RELAYS_R14 +#endif +#ifdef GPIO_RELAYS_R15 + , GPIO_RELAYS_R15 +#endif +#ifdef GPIO_RELAYS_R16 + , GPIO_RELAYS_R16 +#endif +#ifdef GPIO_RELAYS_R17 + , GPIO_RELAYS_R17 +#endif +#ifdef GPIO_RELAYS_R18 + , GPIO_RELAYS_R18 +#endif +#ifdef GPIO_RELAYS_R19 + , GPIO_RELAYS_R19 +#endif +#ifdef GPIO_RELAYS_R20 + , GPIO_RELAYS_R20 +#endif +#ifdef GPIO_RELAYS_R21 + , GPIO_RELAYS_R21 +#endif +#ifdef GPIO_RELAYS_R22 + , GPIO_RELAYS_R22 +#endif +#ifdef GPIO_RELAYS_R23 + , GPIO_RELAYS_R23 +#endif +#ifdef GPIO_RELAYS_R24 + , GPIO_RELAYS_R24 +#endif +#ifdef GPIO_RELAYS_R25 + , GPIO_RELAYS_R25 +#endif +#ifdef GPIO_RELAYS_R26 + , GPIO_RELAYS_R26 +#endif +#ifdef GPIO_RELAYS_R27 + , GPIO_RELAYS_R27 +#endif +#ifdef GPIO_RELAYS_R28 + , GPIO_RELAYS_R28 +#endif +#ifdef GPIO_RELAYS_R29 + , GPIO_RELAYS_R29 +#endif +#ifdef GPIO_RELAYS_R30 + , GPIO_RELAYS_R30 +#endif +#ifdef GPIO_RELAYS_R31 + , GPIO_RELAYS_R31 +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_relaysinit(void) +{ + int i; + + if (g_relays_init) + { + return; + } + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_RELAYS; i++) + { + stm32_configgpio(g_relays[i]); + stm32_gpiowrite(g_relays[i], false); + } + + g_relays_init = true; +} + +void relays_setstat(int relays, bool stat) +{ + if ((unsigned)relays < NUM_RELAYS) + { + stm32_gpiowrite(g_relays[relays], stat); + if (!stat) + { + g_relays_stat &= ~(1 << relays); + } + else + { + g_relays_stat |= (1 << relays); + } + } +} + +bool relays_getstat(int relays) +{ + if ((unsigned)relays < NUM_RELAYS) + { + return (g_relays_stat & (1 << relays)) != 0; + } + + return false; +} + +void relays_setstats(uint32_t relays_stat) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_setstat(i, (relays_stat & (1 << i)) != 0); + } +} + +uint32_t relays_getstats(void) +{ + return (uint32_t)g_relays_stat; +} + +void relays_onoff(int relays, uint32_t mdelay) +{ + if ((unsigned)relays < NUM_RELAYS) + { + if (mdelay > 0) + { + if (relays_getstat(relays)) + { + relays_setstat(relays, false); + nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); + } + + relays_setstat(relays, true); + nxsched_usleep(mdelay * 100 * 1000); + relays_setstat(relays, false); + } + } +} + +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_onoff(i, mdelay); + } +} + +void relays_resetmode(int relays) +{ + relays_onoff(relays, RELAYS_RESET_MTIME); +} + +void relays_powermode(int relays) +{ + relays_onoff(relays, RELAYS_POWER_MTIME); +} + +void relays_resetmodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_RESET_MTIME); +} + +void relays_powermodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_POWER_MTIME); +} + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c new file mode 100644 index 0000000000000..d1aa4127a14ef --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "cloudctrl.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the cloudctrl board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ +#endif + + /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ + +#ifdef CONFIG_STM32_SPI3 + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c new file mode 100644 index 0000000000000..92b57904640c0 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "cloudctrl.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..bde124645141a --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c new file mode 100644 index 0000000000000..3fbcf5b60fb7a --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "cloudctrl.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-3 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c new file mode 100644 index 0000000000000..16de2838d3a91 --- /dev/null +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * boards/arm/stm32f1/cloudctrl/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" +#include "cloudctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/oocd.sh b/boards/arm/stm32f1/cloudctrl/tools/oocd.sh similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/oocd.sh rename to boards/arm/stm32f1/cloudctrl/tools/oocd.sh diff --git a/boards/arm/stm32/cloudctrl/tools/stm32.cfg b/boards/arm/stm32f1/cloudctrl/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/stm32.cfg rename to boards/arm/stm32f1/cloudctrl/tools/stm32.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/usb-driver.txt b/boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/usb-driver.txt rename to boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/common/CMakeLists.txt b/boards/arm/stm32f1/common/CMakeLists.txt new file mode 100644 index 0000000000000..b46b5b7c6779a --- /dev/null +++ b/boards/arm/stm32f1/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f1/common/Kconfig b/boards/arm/stm32f1/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f1/common/Makefile b/boards/arm/stm32f1/common/Makefile new file mode 100644 index 0000000000000..f00fda1b6e974 --- /dev/null +++ b/boards/arm/stm32f1/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f1/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt new file mode 100644 index 0000000000000..eb55f812bdab1 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/Kconfig b/boards/arm/stm32f1/et-stm32-stamp/Kconfig similarity index 100% rename from boards/arm/stm32/et-stm32-stamp/Kconfig rename to boards/arm/stm32f1/et-stm32-stamp/Kconfig diff --git a/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig new file mode 100644 index 0000000000000..33ca638408156 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="et-stm32-stamp" +CONFIG_ARCH_BOARD_ET_STM32_STAMP=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/et-stm32-stamp/include/board.h b/boards/arm/stm32f1/et-stm32-stamp/include/board.h new file mode 100644 index 0000000000000..7cb521fadc8b8 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/include/board.h @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The ET-STM32 Stamp doesn't have an on-board LED. These innocent macros + * can still be here. + */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +#endif /* __BOARDS_ARM_STM32_ET_STM32_STAMP_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs new file mode 100644 index 0000000000000..3470a34f64a50 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script new file mode 100644 index 0000000000000..6c11e86fc69bb --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* The STM32F103RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103RET6 has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt new file mode 100644 index 0000000000000..b7aae37dd01da --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt @@ -0,0 +1,27 @@ +# ############################################################################## +# boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs new file mode 100644 index 0000000000000..d022a6aad9892 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs @@ -0,0 +1,29 @@ +############################################################################ +# boards/arm/stm32f1/et-stm32-stamp/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h similarity index 96% rename from boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h rename to boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h index 4daca3f0bfb6c..81ca060fcaba8 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h +++ b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h + * boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c new file mode 100644 index 0000000000000..498eae42453b9 --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "et-stm32-stamp.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Empty for now. */ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt new file mode 100644 index 0000000000000..aaab83b6d0dcc --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/fire-stm32v2/Kconfig b/boards/arm/stm32f1/fire-stm32v2/Kconfig similarity index 100% rename from boards/arm/stm32/fire-stm32v2/Kconfig rename to boards/arm/stm32f1/fire-stm32v2/Kconfig diff --git a/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig new file mode 100644 index 0000000000000..a310a44055529 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="fire-stm32v2" +CONFIG_ARCH_BOARD_FIRE_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ENC28J60=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=2 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/fire-stm32v2/include/board.h b/boards/arm/stm32f1/fire-stm32v2/include/board.h new file mode 100644 index 0000000000000..27e228b92572c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/include/board.h @@ -0,0 +1,451 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz crytal + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. + * These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/up_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + */ + + /* LED1 LED2 LED3 */ +#define LED_STARTED 0 /* OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* ON OFF OFF */ +#define LED_IRQSENABLED 2 /* OFF ON OFF */ +#define LED_STACKCREATED 3 /* OFF OFF OFF */ + +#define LED_INIRQ 4 /* NC NC ON (momentary) */ +#define LED_SIGNAL 4 /* NC NC ON (momentary) */ +#define LED_ASSERTION 4 /* NC NC ON (momentary) */ +#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */ +#undef LED_IDLE /* Sleep mode indication not supported */ + +/* The M3 Wildfire supports several two user buttons: KEY1 and KEY2 */ + +#define BUTTON_KEY1 0 +#define BUTTON_KEY2 1 +#define NUM_BUTTONS 2 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) + +/* Pin Remapping ************************************************************/ + +/* USB 2.0 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 70 PA11 PA11-USBDM USB2.0 + * 71 PA12 PA12-USBDP USB2.0 + * 2 PE3 PE3-USB-M USB2.0 + */ + +/* 2.4" TFT + Touchscreen + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" +#endif + +/* AT24C02 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + */ + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "SPI1 requires CONFIG_STM32_I2C1_REMAP=n" +#endif + +/* Potentiometer/ADC + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 16 PC1 PC1/ADC123-IN11 Potentiometer (R16) + * 24 PA1 PC1/ADC123-IN1 + */ + +/* USARTs + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 68 PA9 PA9-US1-TX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 69 PA10 PA10-US1-RX MAX3232, DB9 D8, + * Requires !CONFIG_STM32_USART1_REMAP + * 25 PA2 PA2-US2-TX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP + * 26 PA3 PA3-US2-RX MAX3232, DB9 D7, + * Requires !CONFIG_STM32_USART2_REMAP + */ + +#if defined(CONFIG_STM32_USART1) && defined(CONFIG_STM32_USART1_REMAP) +# error "USART1 requires CONFIG_STM32_USART1_REMAP=n" +#endif + +#if defined(CONFIG_STM32_USART2) && defined(CONFIG_STM32_USART2_REMAP) +# error "USART2 requires CONFIG_STM32_USART2_REMAP=n" +#endif + +/* 2MBit SPI FLASH + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "SPI1 requires CONFIG_STM32_SPI1_REMAP=n" +#endif + +/* MP3 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 48 PB11 PB11-MP3-RST MP3 + * 51 PB12 PB12-SPI2-NSS MP3 + * 52 PB13 PB13-SPI2-SCK MP3 + * 53 PB14 PB14-SPI2-MISO MP3 + * 54 PB15 PB15-SPI2-MOSI MP3 + * 63 PC6 PC6-MP3-XDCS MP3 + * 64 PC7 PC7-MP3-DREQ MP3 + */ + +/* SD Card + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 65 PC8 PC8-SDIO-D0 SD card, pulled high + * 66 PC9 PC9-SDIO-D1 SD card, pulled high + * 78 PC10 PC10-SDIO-D2 SD card, pulled high + * 79 PC11 PC10-SDIO-D3 SD card, pulled high + * 80 PC12 PC12-SDIO-CLK SD card + * 83 PD2 PD2-SDIO-CMD SD card, pulled high + */ + +/* CAN + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 95 PB8 PB8-CAN-RX CAN transceiver, Header 2H + * 96 PB9 PB9-CAN-TX CAN transceiver, Header 2H + */ + +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP1) +# error "SPI1 requires CONFIG_STM32_CAN1_REMAP1=y" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: fire_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the M3 Wildfire board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void fire_lcdclear(uint16_t color); +#endif + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +#endif /* __BOARDS_ARM_STM32_FIRE_STM32V2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs new file mode 100644 index 0000000000000..82ac28f1b37d3 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = fire-stm32v2-dfu.ld +else + LDSCRIPT = fire-stm32v2.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld index 98e7d8a77d353..32ac24c4ef2f9 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld index d9e527a239cbe..64ee682f7b682 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt new file mode 100644 index 0000000000000..a589de40419b0 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt @@ -0,0 +1,59 @@ +# ############################################################################## +# boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c) + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ENC28J60) + list(APPEND SRCS stm32_enc28j60.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2-dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/fire-stm32v2.ld") +endif() diff --git a/boards/arm/stm32f1/fire-stm32v2/src/Make.defs b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs new file mode 100644 index 0000000000000..741b5125d192f --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32f1/fire-stm32v2/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_usbdev.c stm32_mmcsd.c + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ENC28J60),y) +CSRCS += stm32_enc28j60.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h rename to boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h index 7bfd672d81e86..8b6606826eec3 100644 --- a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h +++ b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h + * boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c new file mode 100644 index 0000000000000..74380388b5092 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c @@ -0,0 +1,359 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings. + * + * OFFBITS ONBITS + * CLR SET CLR SET + * 210 210 210 210 + */ + +#define FIRE_LED1 (1 << 0) +#define FIRE_LED2 (1 << 1) +#define FIRE_LED3 (1 << 2) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (3) +#define OFF_SETBITS_SHIFT (6) +#define OFF_CLRBITS_SHIFT (9) + +#define ON_BITS(v) ((v) & 0x3f) +#define OFF_BITS(v) (((v) >> 6) & 0x03f) +#define SETBITS(b) ((b) & 0x07) +#define CLRBITS(b) (((b) >> 3) & 0x07) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +/* ON OFF + * -------------------------- -- ------------------ ----------------- + * LED1 LED2 LED3 LED1 LED2 LED3 + * -------------------------- -- ------ ----- ----- ----- ----- ----- + * LED_STARTED 0 OFF OFF OFF OFF OFF OFF + * LED_HEAPALLOCATE 1 ON OFF OFF OFF OFF OFF + * LED_IRQSENABLED 2 OFF ON OFF ON OFF OFF + * LED_STACKCREATED 3 OFF OFF OFF OFF ON OFF + * + * LED_INIRQ 4 NC NC ON NC NC OFF + * LED_SIGNAL 4 NC NC ON NC NC OFF + * LED_ASSERTION 4 NC NC ON NC NC OFF + * LED_PANIC 4 NC NC ON NC NC OFF + * -------------------------- -- ------ ----- ----- ----- ----- ----- + */ + +#define LED_STARTED_ON_SETBITS (0) +#define LED_STARTED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0) +#define LED_STARTED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((FIRE_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((FIRE_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((FIRE_LED1|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((FIRE_LED1) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS (0) +#define LED_STACKCREATED_ON_CLRBITS ((FIRE_LED1|FIRE_LED2|FIRE_LED3) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((FIRE_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((FIRE_LED1|FIRE_LED3) << OFF_CLRBITS_SHIFT) + +#define LED_FLASH_ON_SETBITS ((FIRE_LED3) << ON_SETBITS_SHIFT) +#define LED_FLASH_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_FLASH_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_FLASH_OFF_CLRBITS ((FIRE_LED3) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_FLASH_ON_SETBITS | LED_FLASH_ON_CLRBITS | + LED_FLASH_OFF_SETBITS | LED_FLASH_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & FIRE_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & FIRE_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & FIRE_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & FIRE_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & FIRE_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & FIRE_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c new file mode 100644 index 0000000000000..0ab15a7fc136c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" +#include "arm_internal.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_W25 1 + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* Only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO +# error "Only one MMC/SD slot: Slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO STM32_MMCSDSLOTNO +# endif +#endif + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if the USB peripheral or the USB + * device infrastructure is not enabled + */ + +#if !defined(CONFIG_STM32_USB) || !defined(CONFIG_USBDEV) +# undef HAVE_USBDEV +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#if defined(HAVE_MMCSD) || defined(HAVE_W25) + int ret; +#endif + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + +#ifdef HAVE_MMCSD + /* Initialize the SDIO-based MMC/SD slot */ + + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", + CONFIG_NSH_MMCSDSLOTNO, ret); + return; + } +#endif +} +#endif diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c new file mode 100644 index 0000000000000..24e083f6f65c9 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "fire-stm32v2.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + stm32_configgpio(GPIO_BTN_KEY1); + stm32_configgpio(GPIO_BTN_KEY2); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key. + * A LOW value means that the key is pressed. + */ + + if (!stm32_gpioread(GPIO_BTN_KEY1)) + { + ret |= BUTTON_KEY1_BIT; + } + + if (!stm32_gpioread(GPIO_BTN_KEY2)) + { + ret |= BUTTON_KEY2_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration values. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint16_t gpio; + int ret; + + if (id == BUTTON_KEY1) + { + gpio = GPIO_KEY1; + } + else if (id == BUTTON_KEY2) + { + gpio = GPIO_KEY2; + } + else + { + return -EINVAL; + } + + return stm32_gpiosetevent(gpio, true, true, true, irqhandler, arg); +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c new file mode 100644 index 0000000000000..f75a83fa181e9 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c @@ -0,0 +1,222 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* 2MBit SPI FLASH OR ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_spi.h" + +#include "fire-stm32v2.h" + +#ifdef CONFIG_ENC28J60 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +/* ENC28J60 is on SPI1 */ + +#ifndef CONFIG_STM32_SPI1 +# error "Need CONFIG_STM32_SPI1 in the configuration" +#endif + +/* SPI Assumptions **********************************************************/ + +#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ +#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_lower_s +{ + const struct enc_lower_s lower; /* Low-level MCU interface */ + xcpt_t handler; /* ENC28J60 interrupt handler */ + void *arg; /* Argument that accompanies the interrupt */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg); +static void up_enable(const struct enc_lower_s *lower); +static void up_disable(const struct enc_lower_s *lower); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The + * following structure provides an MCU-independent mechanixm for controlling + * the ENC28J60 GPIO interrupt. + */ + +static struct stm32_lower_s g_enclower = +{ + .lower = + { + .attach = up_attach, + .enable = up_enable, + .disable = up_disable + }, + .handler = NULL, + .arg = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: struct enc_lower_s methods + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void up_enable(const struct enc_lower_s *lower) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + DEBUGASSERT(priv->handler); + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + priv->handler, priv->arg); +} + +/* REVISIT: Since the interrupt is completely torn down, not just disabled, + * in interrupt requests that occurs while the interrupt is disabled will be + * lost. + */ + +static void up_disable(const struct enc_lower_s *lower) +{ + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + NULL, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +void arm_netinitialize(void) +{ + struct spi_dev_s *spi; + int ret; + + /* Assumptions: + * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. + */ + + spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); + if (!spi) + { + nerr("ERROR: Failed to initialize SPI port %d\n", + ENC28J60_SPI_PORTNO); + return; + } + + /* Take ENC28J60 out of reset (active low) */ + + stm32_gpiowrite(GPIO_ENC28J60_RESET, true); + + /* Bind the SPI port to the ENC28J60 driver */ + + ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); + if (ret < 0) + { + nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); + return; + } + + ninfo("Bound SPI port %d to ENC28J60 device %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); +} + +#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..7b24f9062cf3e --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_sdio.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SDIO=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); + return -ENODEV; + } + + finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(minor, sdio); + if (ret != OK) + { + ferr("ERROR:"); + ferr(" Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + } + + finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the M3 Wildfire board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + return OK; +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..153572749c569 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* 2.4" TFT + Touchscreen. FSMC Bank1 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, + * SPI 2M FLASH + * 92 PB6 PB6-I2C1-SCL 2.4" TFT + Touchscreen, AT24C02 + * 93 PB7 PB7-I2C1-SDA 2.4" TFT + Touchscreen, AT24C02 + * 81 PD0 PD0-FSMC_D2 2.4" TFT + Touchscreen + * 82 PD1 PD1-FSMC_D3 2.4" TFT + Touchscreen + * 85 PD4 PD4-FSMC_NOE 2.4" TFT + Touchscreen + * 86 PD5 PD5-FSMC_NWE 2.4" TFT + Touchscreen + * 88 PD7 PD7-FSMC_NE1 2.4" TFT + Touchscreen + * 55 PD8 PD8-FSMC_D13 2.4" TFT + Touchscreen + * 56 PD9 PD9-FSMC_D14 2.4" TFT + Touchscreen + * 57 PD10 PD10-FSMC_D15 2.4" TFT + Touchscreen + * 58 PD11 PD11-FSMC_A16 2.4" TFT + Touchscreen + * 60 PD13 PD13-LCD/LIGHT 2.4" TFT + Touchscreen + * 61 PD14 PD14-FSMC_D0 2.4" TFT + Touchscreen + * 62 PD15 PD15-FSMC_D1 2.4" TFT + Touchscreen + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen + * 38 PE7 PE7-FSMC_D4 2.4" TFT + Touchscreen + * 39 PE8 PE8-FSMC_D5 2.4" TFT + Touchscreen + * 40 PE9 PE9-FSMC_D6 2.4" TFT + Touchscreen + * 41 PE10 PE10-FSMC_D7 2.4" TFT + Touchscreen + * 42 PE11 PE11-FSMC_D8 2.4" TFT + Touchscreen + * 43 PE12 PE12-FSMC_D9 2.4" TFT + Touchscreen + * 44 PE13 PE13-FSMC_D10 2.4" TFT + Touchscreen + * 45 PE14 PE14-FSMC_D11 2.4" TFT + Touchscreen + * 46 PE15 PE15-FSMC_D12 2.4" TFT + Touchscreen + * + * NOTE: + * SPI and I2C pin configuration is controlled in the SPI and I2C drivers, + * respectively. + */ + +static const uint16_t g_lcdconfig[NCOMMON_CONFIG] = +{ + /* Address Lines: A16 only */ + + GPIO_NPS_A16, + + /* Data Lines: D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, + GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, + GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, + GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, + + /* NOE, NWE, NE1, NBL1 */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1, GPIO_NPS_NBL1, + + /* Backlight GPIO */ + + GPIO_LCD_BACKLIGHT +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig) / sizeof(uint16_t)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD pin configuration. + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + irqstate_t flags; + int i; + + /* Configure LCD GPIO pis */ + + flags = enter_critical_section(); + for (i = 0; i < NLCD_GPIOS; i++) + { + stm32_configgpio(g_lcdconfig[i]); + } + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + + putreg32(0xffffffff, STM32_FSMC_BWTR4); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + leave_critical_section(flags); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c new file mode 100644 index 0000000000000..42f31b0005e63 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c @@ -0,0 +1,181 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the M3 Wildfire board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the TFT/Touchscreen CS GPIO */ + +#if 0 /* Need to study this */ + stm32_configgpio(GPIO_LCD_CS); +#endif + + /* Configure the TFT/Touchscreen and ENC28J60 or SPI-based FLASH PIOs */ + + /* Configure ENC28J60 SPI1 CS (also RESET and interrupt pins) */ + +#ifdef CONFIG_ENC28J60 + stm32_configgpio(GPIO_ENC28J60_CS); + stm32_configgpio(GPIO_ENC28J60_RESET); + stm32_configgpio(GPIO_ENC28J60_INTR); +#else + + /* Configure FLASH SPI1 CS */ + + stm32_configgpio(GPIO_FLASH_CS); +#endif + +#endif /* CONFIG_STM32_SPI1 */ + +#ifdef CONFIG_STM32_SPI2 + /* Configure the MP3 SPI2 CS GPIO */ + + stm32_configgpio(GPIO_MP3_CS); + +#endif /* CONFIG_STM32_SPI2 */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if 0 /* Need to study this */ + if (devid == SPIDEV_LCD) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCD_CS, !selected); + } + else +#endif +#ifdef CONFIG_ENC28J60 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); + } +#else + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_AUDIO) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MP3_CS, !selected); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c new file mode 100644 index 0000000000000..51fb1b1ab516c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the M3 Wildfire board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup */ + +#if 0 /* REVISIT */ + stm32_configgpio(GPIO_USB_PULLUP); +#endif +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined + * to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); +#if 0 /* REVISIT */ + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..c34d41e68965c --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c new file mode 100644 index 0000000000000..f94020021af18 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "fire-stm32v2.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + return 3; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Set one LED to the 'ledon' state. The LEDs are pulled up and, hence, + * active low. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Set each LED to the bit encoded state. The LEDs are pulled up and, + * hence, active low. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c new file mode 100644 index 0000000000000..56ed032c057b3 --- /dev/null +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c @@ -0,0 +1,144 @@ +/**************************************************************************** + * boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" +#include "fire-stm32v2.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt new file mode 100644 index 0000000000000..4af2981effa4a --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/hymini-stm32v/Kconfig b/boards/arm/stm32f1/hymini-stm32v/Kconfig similarity index 100% rename from boards/arm/stm32/hymini-stm32v/Kconfig rename to boards/arm/stm32f1/hymini-stm32v/Kconfig diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig new file mode 100644 index 0000000000000..2b1d0d38fe169 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig new file mode 100644 index 0000000000000..fda1334b5880a --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXIMAGE=y +CONFIG_EXAMPLES_NXIMAGE_BPP=16 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_ROMFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_ADS7843E=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_MAXPOWER=100 +CONFIG_LCD_SSD1289=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_SSD1289_PROFILE2=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_TRACE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..3686bd67351e8 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_INIT_ENTRYPOINT="msconn_main" +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..1d4d819411950 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_BKP=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig new file mode 100644 index 0000000000000..488745ba2fb05 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig @@ -0,0 +1,37 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="hymini-stm32v" +CONFIG_ARCH_BOARD_HYMINI_STM32V=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_INIT_ENTRYPOINT="usbserial_main" +CONFIG_PL2303=y +CONFIG_PL2303_PRODUCTSTR="USBdev Serial" +CONFIG_PL2303_RXBUFSIZE=512 +CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=49152 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/hymini-stm32v/include/board.h b/boards/arm/stm32f1/hymini-stm32v/include/board.h new file mode 100644 index 0000000000000..820d03a162b66 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/include/board.h @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_STM32_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has 2 LEDs that we will encode as: */ +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* The board supports two user buttons + * + * KeyA -- Connected to PC.13 + * KeyB -- Connected to PB.2 + */ + +#define BUTTON_KEYA 0 +#define BUTTON_KEYB 1 + +#define NUM_BUTTONS 2 + +#define BUTTON_KEYA_BIT (1 << BUTTON_KEYA) +#define BUTTON_KEYB_BIT (1 << BUTTON_KEYB) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* TIM3 */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 +#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 +#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 +#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 +#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) + +/* FSMC NPS_A address pins (used by LCD srcs) */ + +#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A23 GPIO_ADJUST_MODE(GPIO_NPS_A23_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A24 GPIO_ADJUST_MODE(GPIO_NPS_A24_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A25 GPIO_ADJUST_MODE(GPIO_NPS_A25_0, GPIO_MODE_50MHz) + +/* FSMC NPS_D pins (used by LCD srcs) */ + +#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE1 GPIO_ADJUST_MODE(GPIO_NPS_NE1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_HYMINI_STM32V_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs new file mode 100644 index 0000000000000..cc9f4fdc84e01 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script new file mode 100644 index 0000000000000..faa108e1d4b20 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103VCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and + * 48Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt new file mode 100644 index 0000000000000..aa571e0ce0911 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +else() + if(CONFIG_LCD_R61505U) + list(APPEND SRCS stm32_r61505u.c) + endif() +endif() + +if(CONFIG_INPUT) + list(APPEND SRCS stm32_ts.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/hymini-stm32v/src/Make.defs b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs new file mode 100644 index 0000000000000..7285c60b44a59 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs @@ -0,0 +1,45 @@ +############################################################################ +# boards/arm/stm32f1/hymini-stm32v/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_buttons.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +else +ifeq ($(CONFIG_LCD_R61505U),y) +CSRCS += stm32_r61505u.c +endif +endif + +ifeq ($(CONFIG_INPUT),y) +CSRCS += stm32_ts.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h rename to boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h index e8966e76f0117..ba053fc552fff 100644 --- a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h +++ b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h + * boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c new file mode 100644 index 0000000000000..934454ae8b896 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c @@ -0,0 +1,264 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* Check if we can have USB device in NSH */ + +#define NSH_HAVEUSBDEV 1 + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Check if we can have MMC/SD slot support in NSH */ + +#define NSH_HAVEMMCSD 1 + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef NSH_HAVEMMCSD +#endif + +#ifdef NSH_HAVEMMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +static struct sdio_dev_s *g_sdiodev; +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nsh_cdinterrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static int nsh_cdinterrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SD_CD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdiodev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef NSH_HAVEMMCSD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SD_CD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, nsh_cdinterrupt, NULL); + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + + g_sdiodev = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdiodev) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdiodev); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Use SD card detect pin to check if a card is inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SD_CD); + _info("Card detect : %hhu\n", g_sd_inserted); + + sdio_mediachange(g_sdiodev, g_sd_inserted); +#endif + +#ifdef CONFIG_INPUT + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c new file mode 100644 index 0000000000000..14082bc395a3e --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "hymini-stm32v.h" + +#ifdef CONFIG_ARCH_BUTTONS + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_KEYA); + stm32_configgpio(GPIO_BTN_KEYB); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + bool value; + + /* Check that state of each key */ + + /* Pin is pulled up */ + + value = stm32_gpioread(GPIO_BTN_KEYA); + if (!value) + { + /* Button pressed */ + + ret = 1 << BUTTON_KEYA; + } + + /* Pin is pulled down */ + + value = stm32_gpioread(GPIO_BTN_KEYB); + if (value) + { + /* Button pressed */ + + ret |= 1 << BUTTON_KEYB; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint32_t pinset = GPIO_BTN_KEYA; + int ret = -EINVAL; + + if (id == 1) + { + pinset = GPIO_BTN_KEYB; + } + + if (id < 2) + { + ret = stm32_gpiosetevent(pinset, true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c new file mode 100644 index 0000000000000..166971c8b24e7 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c @@ -0,0 +1,224 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define HYMINI_STM32_LED1 (1 << 0) +#define HYMINI_STM32_LED2 (1 << 1) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +/* On: !LED1 + !LED2 Off: - */ + +#define LED_STARTED_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((HYMINI_STM32_LED1|HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS (0 << OFF_CLRBITS_SHIFT) + +/* On: LED1+!LED2 Off: N/A */ + +#define LED_HEAPALLOCATE_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS (0) +#define LED_HEAPALLOCATE_OFF_CLRBITS (0) + +/* On: LED2+!LED1 Off: N/A */ + +#define LED_IRQSENABLED_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS (0) +#define LED_IRQSENABLED_OFF_CLRBITS (0) + +/* On: LED1+!LED2 Off: N/A */ + +#define LED_STACKCREATED_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS (0) +#define LED_STACKCREATED_OFF_CLRBITS (0) + +/* On: !LED1 Off: LED1 */ + +#define LED_INIRQ_ON_SETBITS ((0) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((HYMINI_STM32_LED1) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((HYMINI_STM32_LED1) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* On: LED2 Off: !LED2 */ + +#define LED_SIGNAL_ON_SETBITS ((HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((HYMINI_STM32_LED2) << OFF_CLRBITS_SHIFT) + +/* On: LED1+LED2 Off: - */ + +#define LED_ASSERTION_ON_SETBITS ((HYMINI_STM32_LED2|HYMINI_STM32_LED2) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((0) << OFF_CLRBITS_SHIFT) + +/* On: LED1 Off: LED2 */ + +#define LED_PANIC_ON_SETBITS ((HYMINI_STM32_LED1) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((HYMINI_STM32_LED2) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((HYMINI_STM32_LED2) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((HYMINI_STM32_LED1) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & HYMINI_STM32_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & HYMINI_STM32_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & HYMINI_STM32_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & HYMINI_STM32_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1 & LED2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c index 531e96e91b571..a43d7b85e278f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c new file mode 100644 index 0000000000000..6e88b17755f22 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the SPI-based touch screen CS GPIO */ + + spiinfo("Configure GPIO for SPI1/CS\n"); + stm32_configgpio(GPIO_TS_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_TS_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..679d23535de72 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c @@ -0,0 +1,489 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +#include /* Should always be included last due to dependencies */ + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* Color depth and format */ + +#define LCD_BPP 16 +#define LCD_COLORFMT FB_FMT_RGB16_565 + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) +# define LCD_XRES 320 +# define LCD_YRES 240 +#else +# define LCD_XRES 240 +# define LCD_YRES 320 +#endif + +#define LCD_BL_TIMER_PERIOD 8999 + +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship + * select signal + */ + +/* RS <==> A16 */ + +#define LCD_INDEX 0x60000000 /* RS = 0 */ +#define LCD_DATA 0x60020000 /* RS = 1 */ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +const uint16_t fsmc_gpios[] = +{ + /* A16... A24 */ + + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, + GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, + GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, + GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, + GPIO_NPS_D15, + + /* NOE, NWE */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, + + /* NE1 */ + + GPIO_NPS_NE1 +}; + +#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) + +/* This is the driver state structure */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). + * Used here to set pwm duty on timer used for backlight. + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + uint32_t duty; + + /* Calculate the new backlight duty. It is a fraction of the timer + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / + CONFIG_LCD_MAXPOWER; + if (duty >= LCD_BL_TIMER_PERIOD) + { + duty = LCD_BL_TIMER_PERIOD - 1; + } + + putreg16((uint16_t)duty, STM32_TIM3_CCR2); + } + else + { + putreg16((uint16_t)0, STM32_TIM3_CCR2); + } +} + +static void init_lcd_backlight(void) +{ + uint16_t ccmr; + uint16_t ccer; + + /* Configure PB5 as TIM3 CH2 output */ + + stm32_configgpio(GPIO_TIM3_CH2OUT); + + /* Enable timer 3 clocking */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + + /* Reset timer 3 */ + + modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); + modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM3_CR1); + + /* Set the Autoreload value */ + + putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); + + /* Set the Prescaler value */ + + putreg16(0, STM32_TIM3_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); + + /* Disable the Channel 2 */ + + ccer = getreg16(STM32_TIM3_CCER); + ccer &= ~ATIM_CCER_CC2E; + putreg16(ccer, STM32_TIM3_CCER); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM3_CCMR1); + ccmr &= ATIM_CCMR1_OC2M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); + + putreg16(0, STM32_TIM3_CCR2); + + /* Select the output polarity level == HIGH */ + + ccer &= ~ATIM_CCER_CC2P; + + /* Enable channel 2 */ + + ccer |= ATIM_CCER_CC2E; + + /* Write the timer configuration */ + + putreg16(ccmr, STM32_TIM3_CCMR1); + putreg16(ccer, STM32_TIM3_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer !!!! */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); + + /* Dump timer3 registers */ + + lcdinfo("APB1ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB1ENR)); + lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR1)); + lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CR2)); + lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SMCR)); + lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM3_DIER)); + lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM3_SR)); + lcdinfo("EGR: %04" PRIx32 "\n", getreg32(STM32_TIM3_EGR)); + lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR1)); + lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCMR2)); + lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCER)); + lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM3_CNT)); + lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM3_PSC)); + lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM3_ARR)); + lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR1)); + lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR2)); + lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR3)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM3_DMAR)); +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize the memory controller (FSMC) + * + ****************************************************************************/ + +static void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(fsmc_gpios, NGPIOS); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) | + FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, + STM32_FSMC_BTR1); + + /* As ext mode is not active the write timing is ignored!! */ + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, + STM32_FSMC_BCR1); +} + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + init_lcd_backlight(); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_ts.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c index e7e7a8720c3f4..86b9a9137e8cb 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ts.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c new file mode 100644 index 0000000000000..108df51135fad --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "hymini-stm32v.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO + * (for USB software connect and disconnect), then the board software must + * provide stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can + * be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..ed78a1b866504 --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" + +/* There is nothing to do here if SDIO support is not selected. */ + +#ifdef CONFIG_STM32_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_HYMINI_STM32V +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1); + + ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); + if (ret != OK) + { + syslog(LOG_ERR, "" + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the Hy-Mini STM32v board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32f1/maple/CMakeLists.txt b/boards/arm/stm32f1/maple/CMakeLists.txt new file mode 100644 index 0000000000000..c22e019a545c6 --- /dev/null +++ b/boards/arm/stm32f1/maple/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/maple/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/maple/Kconfig b/boards/arm/stm32f1/maple/Kconfig similarity index 100% rename from boards/arm/stm32/maple/Kconfig rename to boards/arm/stm32f1/maple/Kconfig diff --git a/boards/arm/stm32f1/maple/configs/nsh/defconfig b/boards/arm/stm32f1/maple/configs/nsh/defconfig new file mode 100644 index 0000000000000..619ff1f1dbf30 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/configs/nx/defconfig b/boards/arm/stm32f1/maple/configs/nx/defconfig new file mode 100644 index 0000000000000..5d98c00a330c9 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/nx/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NX_BPP=1 +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_SHARP_MEMLCD=y +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_USBCONSOLE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SPI_BITORDER=y +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2CTIMEOSEC=1 +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/configs/usbnsh/defconfig b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..128d504fd3f56 --- /dev/null +++ b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="maple" +CONFIG_ARCH_BOARD_MAPLE=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_RAND_ORDER=2 +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_USBCONSOLE=y +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/maple/include/board.h b/boards/arm/stm32f1/maple/include/board.h new file mode 100644 index 0000000000000..af797c5453d2b --- /dev/null +++ b/boards/arm/stm32f1/maple/include/board.h @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* I2C2 */ + +#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_MAPLE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/maple/scripts/Make.defs b/boards/arm/stm32f1/maple/scripts/Make.defs new file mode 100644 index 0000000000000..659d183e62795 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/maple/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/maple/scripts/ld.script b/boards/arm/stm32f1/maple/scripts/ld.script new file mode 100644 index 0000000000000..0a473342b7501 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/maple/scripts/ld.script.dfu b/boards/arm/stm32f1/maple/scripts/ld.script.dfu new file mode 100644 index 0000000000000..c1b90e6d7aff7 --- /dev/null +++ b/boards/arm/stm32f1/maple/scripts/ld.script.dfu @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103xB has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * maple's DFU bootloader is being used. In that case, the correct + * load .text load address is 0x0800:5000 (leaving 108Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08005000, LENGTH = 108K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/maple/src/CMakeLists.txt b/boards/arm/stm32f1/maple/src/CMakeLists.txt new file mode 100644 index 0000000000000..97ee99bae6293 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# boards/arm/stm32f1/maple/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c) + +if(CONFIG_NX_LCDDRIVER) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_BOARDCTL) + +endif() + +if(CONFIG_INPUT) + +endif() + +if(CONFIG_USBMSC) + +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/maple/src/Make.defs b/boards/arm/stm32f1/maple/src/Make.defs new file mode 100644 index 0000000000000..1a04a2a8db646 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f1/maple/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_usbdev.c stm32_spi.c + +ifeq ($(CONFIG_NX_LCDDRIVER),y) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +endif + +ifeq ($(CONFIG_INPUT),y) +endif + +ifeq ($(CONFIG_USBMSC),y) +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/maple/src/maple.h b/boards/arm/stm32f1/maple/src/maple.h similarity index 98% rename from boards/arm/stm32/maple/src/maple.h rename to boards/arm/stm32f1/maple/src/maple.h index 01bb5e5758f2f..26626776fb6d6 100644 --- a/boards/arm/stm32/maple/src/maple.h +++ b/boards/arm/stm32f1/maple/src/maple.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/maple.h + * boards/arm/stm32f1/maple/src/maple.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f1/maple/src/stm32_boot.c b/boards/arm/stm32f1/maple/src/stm32_boot.c new file mode 100644 index 0000000000000..cbf666746d35b --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_boot.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called after up_initialize() and board_early_initialize() and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers for which board_early_initialize() is not + * suitable. + * + * Waiting for events, use of I2C, SPI, etc are permissible in the context + * of board_late_initialize(). That is because board_late_initialize() + * will run on a temporary, internal kernel thread. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f1/maple/src/stm32_lcd.c b/boards/arm/stm32f1/maple/src/stm32_lcd.c new file mode 100644 index 0000000000000..58f5831a33fe8 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_lcd.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define EXTCOMIN_FREQ 24 +#define TIMER_FREQ 1200 /* 72000000/60000 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct lcd_dev_s *l_lcddev; +static struct spi_dev_s *spi; +static struct stm32_tim_dev_s *tim; +static xcpt_t g_isr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int up_lcdextcominisr(int irq, void *context, void *arg) +{ + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); + if (g_isr == NULL) + { + lcderr("ERROR: error, irq not attached, disabled\n"); + STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); + return OK; + } + + return g_isr(irq, context, arg); +} + +static int up_lcdirqattach(xcpt_t isr, void * arg) +{ + lcdinfo("%s IRQ\n", isr == NULL ? "Detach" : "Attach"); + + if (isr != NULL) + { + STM32_TIM_SETISR(tim, up_lcdextcominisr, arg, ATIM_SR_UIF); + g_isr = isr; + } + else + { + STM32_TIM_SETISR(tim, NULL, NULL, ATIM_SR_UIF); + g_isr = NULL; + } + + return OK; +} + +static void up_lcddispcontrol(bool on) +{ + lcdinfo("set: %s\n", on ? "on" : "off"); + + if (on) + { + stm32_gpiowrite(GPIO_MEMLCD_DISP, 1); + STM32_TIM_ENABLEINT(tim, ATIM_DIER_UIE); + } + else + { + stm32_gpiowrite(GPIO_MEMLCD_DISP, 0); + STM32_TIM_DISABLEINT(tim, ATIM_DIER_UIE); + } +} + +#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW +static void up_lcdsetpolarity(bool pol) +{ + stm32_gpiowrite(GPIO_LED, pol); + stm32_gpiowrite(GPIO_MEMLCD_EXTCOMIN, pol); +} +#endif + +static void up_lcdsetvcomfreq(unsigned int freq) +{ + lcdinfo("freq: %d\n", freq); + DEBUGASSERT(freq >= 1 && freq <= 60); + STM32_TIM_SETPERIOD(tim, TIMER_FREQ / freq); +} + +static struct memlcd_priv_s memlcd_priv = +{ + .attachirq = up_lcdirqattach, + .dispcontrol = up_lcddispcontrol, +#ifndef CONFIG_MEMLCD_EXTCOMIN_MODE_HW + .setpolarity = up_lcdsetpolarity, +#endif + .setvcomfreq = up_lcdsetvcomfreq, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing lcd\n"); + + lcdinfo("init spi1\n"); + spi = stm32_spibus_initialize(1); + DEBUGASSERT(spi); + + lcdinfo("configure related io\n"); + stm32_configgpio(GPIO_MEMLCD_EXTCOMIN); + stm32_configgpio(GPIO_MEMLCD_DISP); + + lcdinfo("configure EXTCOMIN timer\n"); + if (tim == NULL) + { + tim = stm32_tim_init(2); + DEBUGASSERT(tim); + STM32_TIM_SETPERIOD(tim, TIMER_FREQ / EXTCOMIN_FREQ); + STM32_TIM_SETCLOCK(tim, TIMER_FREQ); + STM32_TIM_SETMODE(tim, STM32_TIM_MODE_UP); + } + + lcdinfo("init lcd\n"); + l_lcddev = memlcd_initialize(spi, &memlcd_priv, 0); + DEBUGASSERT(l_lcddev); + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return l_lcddev; +} diff --git a/boards/arm/stm32f1/maple/src/stm32_leds.c b/boards/arm/stm32f1/maple/src/stm32_leds.c new file mode 100644 index 0000000000000..61d8957f2e498 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_leds.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED, v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, we simply turn + * it on when the board boots + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + + default: + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + ledinfo("board_autoled_off(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + + default: + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/maple/src/stm32_spi.c b/boards/arm/stm32f1/maple/src/stm32_spi.c new file mode 100644 index 0000000000000..1b644a2eb7b90 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_spi.c @@ -0,0 +1,138 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "maple.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the maple board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + stm32_configgpio(GPIO_MEMLCD_CS); +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +# if defined(CONFIG_LCD_SHARP_MEMLCD) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_MEMLCD_CS, selected); + } +# endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +int stm32_spi1cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +int stm32_spi1cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/maple/src/stm32_usbdev.c b/boards/arm/stm32f1/maple/src/stm32_usbdev.c new file mode 100644 index 0000000000000..301485eb42cf1 --- /dev/null +++ b/boards/arm/stm32f1/maple/src/stm32_usbdev.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/maple/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "maple.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. Alternatively, if no pull-up GPIO the following EXTERN + * can be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32/maple/tools/dfu.sh b/boards/arm/stm32f1/maple/tools/dfu.sh similarity index 100% rename from boards/arm/stm32/maple/tools/dfu.sh rename to boards/arm/stm32f1/maple/tools/dfu.sh diff --git a/boards/arm/stm32/maple/tools/env.sh b/boards/arm/stm32f1/maple/tools/env.sh similarity index 100% rename from boards/arm/stm32/maple/tools/env.sh rename to boards/arm/stm32f1/maple/tools/env.sh diff --git a/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt new file mode 100644 index 0000000000000..2b4f584cf31b9 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f103rb/Kconfig b/boards/arm/stm32f1/nucleo-f103rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f103rb/Kconfig rename to boards/arm/stm32f1/nucleo-f103rb/Kconfig diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig new file mode 100644 index 0000000000000..03b0dc7c45924 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig new file mode 100644 index 0000000000000..603393f380612 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -0,0 +1,86 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..c3f979d2d130b --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig new file mode 100644 index 0000000000000..f581b347f7672 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig new file mode 100644 index 0000000000000..3e080577801b8 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_PARTIAL_REMAP_1=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/nucleo-f103rb/include/board.h b/boards/arm/stm32f1/nucleo-f103rb/include/board.h new file mode 100644 index 0000000000000..508c91177a32b --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/include/board.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB2 TIM 1 will receive PCLK2 (72MHz) */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo F103RB board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F103RBT6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F103RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F103RB supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F103RBT6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F103RBT6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#ifdef CONFIG_BOARD_STM32_IHM07M1 + +/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with + * the L6230 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +/* Configured in stm32/hardware/stm32f103r_pinmap.h */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) + +/* DIAG/ENABLE */ + +# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_CNF_OUTOD|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM07M1 */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F103RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs new file mode 100644 index 0000000000000..cec74ca3dda8d --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script new file mode 100644 index 0000000000000..2d8d8c9c134d7 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103RBT6 has 128Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..f8e649461b796 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ############################################################################## +# boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() + + if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) + endif() +endif() + +if(CONFIG_BOARD_STM32_IHM07M1) + list(APPEND SRCS stm32_foc_ihm07m1.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs new file mode 100644 index 0000000000000..f3c2bb7582290 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32f1/nucleo-f103rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) +CSRCS += stm32_foc_ihm07m1.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h rename to boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h index d4cb2b2383add..09dd3b1dd5451 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h +++ b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h + * boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c new file mode 100644 index 0000000000000..5b5ff6d6bc82c --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less) */ + +static const uint8_t g_chanlist1[3] = +{ + 0, + 1, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC123_IN0_0, /* PA0/A0 */ + GPIO_ADC123_IN1_0, /* PA1/A1 */ + GPIO_ADC12_IN4_0, /* PA4/A2 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC12_IN8_0, /* PB0/A3 */ + GPIO_ADC123_IN11_0, /* PC1/A4 */ + GPIO_ADC123_IN10_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC12_IN8_0, /* PB0/A3 */ + GPIO_ADC123_IN11_0, /* PC1/A4 */ + GPIO_ADC123_IN10_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..9185329bab1f7 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c new file mode 100644 index 0000000000000..0084bba60a882 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..d4583edc58e9a --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c @@ -0,0 +1,143 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F103RB_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..ce1e2da780ebf --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c new file mode 100644 index 0000000000000..632f8770ef304 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_ihm07m1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_28p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_239p5 +#define POT_SAMPLE_TIME ADC_SMPR_239p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS +# define IHM07M1_VBUS 1 +#else +# define IHM07M1_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT +# define IHM07M1_POT 1 +#else +# define IHM07M1_POT 0 +#endif + +#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +/* Check ADC1 configuration */ + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +/* TIM1 configuration */ + +#ifndef CONFIG_STM32_TIM1_PARTIAL_REMAP +# error +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* FOC ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN0 (PA0) + * - Current Phase U -> ADC1 INJ2 -> ADC1_IN11 (PC1) + * - Current Phase W -> ADC1 INJ3 -> ADC1_I10 (PC0) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN1 (PA1) + * - POT -> ADC1 REG -> ADC1_IN9 (PB1) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase W high -> TIM1_CH3 (PA10) + * + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + 1, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + 9, /* ADC1 REG - POT */ +#endif + 0, /* ADC1 INJ1 - PHASE 1 */ +#if CONFIG_MOTOR_FOC_SHUNTS == 3 + 11, /* ADC1 INJ2 - PHASE 2 */ + 10, /* ADC1 INJ3 - PHASE 3 */ +#endif +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + GPIO_ADC123_IN1_0, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + GPIO_ADC12_IN9_0, +#endif + GPIO_ADC123_IN0_0, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + GPIO_ADC123_IN11_0, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + GPIO_ADC123_IN10_0, +#endif +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + { + .channel = 2, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + { + .channel = 12, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 1, + .sample_time = CURRENT_SAMPLE_TIME + }, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + { + .channel = 7, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + { + .channel = 6, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + return board_ihm07m1_initialize(&g_adc_cfg); +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c new file mode 100644 index 0000000000000..e4942fddead1e --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f103rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF103RB_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..3e9985bd99864 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f103rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt new file mode 100644 index 0000000000000..0a2eaea0a5fa6 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p107/Kconfig b/boards/arm/stm32f1/olimex-stm32-p107/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p107/Kconfig rename to boards/arm/stm32f1/olimex-stm32-p107/Kconfig diff --git a/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig new file mode 100644 index 0000000000000..8b360b4955289 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p107" +CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DRIPADDR=0xc0a80201 +CONFIG_NETINIT_IPADDR=0xc0a80232 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/olimex-stm32-p107/include/board.h b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h new file mode 100644 index 0000000000000..612ecb223fdcf --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h @@ -0,0 +1,145 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. From above, we already have PLL3 input + * frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs new file mode 100644 index 0000000000000..dda83d8898358 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script new file mode 100644 index 0000000000000..7a37a617e0702 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu new file mode 100644 index 0000000000000..410230772b174 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Don't know if this is correct. Just 256K-48K (not testet) */ +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt new file mode 100644 index 0000000000000..36500b34205ae --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt @@ -0,0 +1,35 @@ +# ############################################################################## +# boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ENCX24J600) + list(APPEND SRCS stm32_encx24j600.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs new file mode 100644 index 0000000000000..c50f59af776f6 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ENCX24J600),y) +CSRCS += stm32_encx24j600.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h rename to boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h index 4ce6a7ce0f9cb..97366814f1fe6 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h + * boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c new file mode 100644 index 0000000000000..63c23905de96e --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "arm_internal.h" +#include "olimex-stm32-p107.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c new file mode 100644 index 0000000000000..e6381bb949c36 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c index c689ee908232f..a3b484f5a1667 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c new file mode 100644 index 0000000000000..19f74116c0cb2 --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "olimex-stm32-p107.h" + +#if defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Olimex stm32-p107 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* Configure ENCX24J600 SPI1 CS (also RESET and interrupt pins) */ + +#if defined(CONFIG_ENCX24J600) && defined(CONFIG_STM32_SPI3) + stm32_configgpio(GPIO_ENCX24J600_CS); + stm32_configgpio(GPIO_ENCX24J600_INTR); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENCX24J600_CS, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt new file mode 100644 index 0000000000000..79a8aa20d7491 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/Kconfig b/boards/arm/stm32f1/olimexino-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/olimexino-stm32/Kconfig rename to boards/arm/stm32f1/olimexino-stm32/Kconfig diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig new file mode 100644 index 0000000000000..250c12385ea57 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_RESET=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_NSH_NESTDEPTH=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig new file mode 100644 index 0000000000000..15da06b5596df --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig @@ -0,0 +1,133 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_CDCACM_NRDREQS=2 +CONFIG_CDCACM_NWRREQS=2 +CONFIG_CDCACM_RXBUFSIZE=96 +CONFIG_CDCACM_TXBUFSIZE=96 +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MMCSD=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_BKP=y +CONFIG_STM32_CRC=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 +CONFIG_USART2_RXBUFSIZE=32 +CONFIG_USART2_TXBUFSIZE=32 +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_SCSI_STACKSIZE=340 +CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig new file mode 100644 index 0000000000000..d5366a2e5fcc6 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig @@ -0,0 +1,114 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FAT_MAXFNAME=12 +CONFIG_FILE_STREAM=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_NAMED_SEMAPHORES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MMCSD=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_BKP=y +CONFIG_STM32_CRC=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C_DUTY16_9=y +CONFIG_STM32_I2C_DYNTIMEO=y +CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP=10 +CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE=40 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 +CONFIG_USART2_RXBUFSIZE=32 +CONFIG_USART2_TXBUFSIZE=32 +CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig new file mode 100644 index 0000000000000..d21cfa15a197c --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=40 +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CODECS_BUFSIZE=0 +CONFIG_NSH_FILEIOSIZE=128 +CONFIG_NSH_NESTDEPTH=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=758 +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig new file mode 100644 index 0000000000000..14bbaffe7b963 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimexino-stm32" +CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_INTERRUPTSTACK=340 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_LOOPBACK=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FDCLONE_DISABLE=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=300 +CONFIG_INIT_ENTRYPOINT="can_main" +CONFIG_INIT_STACKSIZE=880 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_SMALL=y +CONFIG_NAME_MAX=8 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=5 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=768 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_STACK_DEFAULT=464 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=758 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=768 +CONFIG_STACK_COLORATION=y +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_REMAP1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PARTIAL_REMAP=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_PARTIAL_REMAP=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_USART1_RXBUFSIZE=32 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=32 diff --git a/boards/arm/stm32f1/olimexino-stm32/include/board.h b/boards/arm/stm32f1/olimexino-stm32/include/board.h new file mode 100644 index 0000000000000..43d1b956c90f3 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/include/board.h @@ -0,0 +1,252 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEXINO_STM32_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* Buttons ******************************************************************/ + +#define BUTTON_BOOT0_BIT (0) +#define BUTTON_BOOT0_MASK (1< flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu new file mode 100644 index 0000000000000..5e711e9bf4496 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Don't know if this is correct. Just 256K-48K (not tested) */ +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt new file mode 100644 index 0000000000000..92c20f5852f57 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt @@ -0,0 +1,47 @@ +# ############################################################################## +# boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_leds.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/olimexino-stm32/src/Make.defs b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs new file mode 100644 index 0000000000000..3e70dc2362c6e --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/stm32f1/olimexino-stm32/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_leds.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h similarity index 99% rename from boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h rename to boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h index 09d5de74303ea..e0f4f7c67c1b2 100644 --- a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h +++ b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h + * boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c new file mode 100644 index 0000000000000..3e0ea392f3aec --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_USBDEV +# include "stm32_usbdev.h" +#endif + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: vbus_handler + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +static int vbus_handler(int irq, void *context, void *arg) +{ + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + stm32_led_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board buttons. */ + + board_button_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_USBMSC +#if !defined(CONFIG_NSH_BUILTIN_APPS) && !defined(CONFIG_SYSTEM_USBMSC) + ret = board_usbmsc_initialize(0); +#endif +#endif + +#if !defined(CONFIG_NSH_BUILTIN_APPS) && defined(CONFIG_USBDEV_COMPOSITE) + ret = board_composite_initialize(0); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + +#if defined(CONFIG_USBDEV) + stm32_usb_set_pwr_callback(vbus_handler); +#endif +} +#endif diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c new file mode 100644 index 0000000000000..341e220517ec8 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimexino-stm32.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(BUTTON_BOOT0N); + return 1; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(BUTTON_BOOT0N) ? 0 : BUTTON_BOOT0_MASK; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id == IRQBUTTON) + { + ret = stm32_gpiosetevent(BUTTON_BOOT0N, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c new file mode 100644 index 0000000000000..06c03bd103f98 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#include "olimexino-stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c new file mode 100644 index 0000000000000..79a7efdc01ead --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c @@ -0,0 +1,448 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/* There is nothing to do here if SPI support is not selected. */ + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No SPI? Then no USB MSC device in composite */ + +#ifndef CONFIG_STM32_SPI +# undef CONFIG_USBMSC_COMPOSITE +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 +# undef OLIMEXINO_STM32_MMCSDSLOTNO +# define OLIMEXINO_STM32_MMCSDSLOTNO 0 +# undef OLIMEXINO_STM32_MMCSDSPIPORTNO +# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. This is just an + * application specific wrapper aboutn usbmsc_unitialize() that is called + * form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + DEBUGASSERT(g_mschandle != NULL); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[0]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[0].classobject = cdcacm_classobject; + dev[0].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[0].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[0].devinfo.ninterfaces; + strbase += dev[0].devinfo.nstrings; + + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[1]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[1].classobject = board_mscclassobject; + dev[1].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[1].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; + dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; + + /* Count up the base numbers */ + + ifnobase += dev[1].devinfo.ninterfaces; + strbase += dev[1].devinfo.nstrings; + + return composite_initialize(composite_getdevdescs(), dev, 2); +} +#endif + +/**************************************************************************** + * Name: board_composite1_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 1. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite1_connect(int port) +{ + /* REVISIT: This configuration currently fails. stm32_epallocpma() fails + * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte + * buffers, two required for EP0, leaving only buffers for 5 additional + * endpoints. + */ + +#if 0 + struct composite_devdesc_s dev[2]; + int strbase = COMPOSITE_NSTRIDS; + int ifnobase = 0; + int epno; + int i; + + for (i = 0, epno = 1; i < 2; i++) + { + /* Ask the cdcacm driver to fill in the constants we didn't know here */ + + cdcacm_get_composite_devdesc(&dev[i]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[i].classobject = cdcacm_classobject; + dev[i].uninitialize = cdcacm_uninitialize; + + dev[i].minor = i; /* The minor interface number */ + + /* Interfaces */ + + dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + + /* Strings */ + + dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; + + ifnobase += dev[i].devinfo.ninterfaces; + strbase += dev[i].devinfo.nstrings; + } + + return composite_initialize(composite_getdevdescs(), dev, 2); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + /* If system/composite is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + + struct spi_dev_s *spi; + int ret; + + /* First, get an instance of the SPI interface */ + + syslog(LOG_INFO, "Initializing SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + /* Now bind the SPI interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=0 slot=%d\n", + OLIMEXINO_STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(0, OLIMEXINO_STM32_MMCSDSLOTNO, spi); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port %d to MMC/SD minor=0 slot=%d %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO, OLIMEXINO_STM32_MMCSDSLOTNO, + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { +#ifdef CONFIG_USBMSC_COMPOSITE + return board_composite0_connect(port); +#else + return NULL; +#endif + } + else if (configid == 1) + { + return board_composite1_connect(port); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c new file mode 100644 index 0000000000000..49fc941fc4581 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Dump GPIO registers */ + +#ifdef CONFIG_DEBUG_LEDS_INFO +# define led_dumpgpio(m) stm32_dumpgpio(GPIO_LED_GREEN, m) +#else +# define led_dumpgpio(m) +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +static bool g_initialized = false; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize/board_userled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +uint32_t stm32_led_initialize(void) +#else +uint32_t board_userled_initialize(void) +#endif +{ + /* Configure all LED GPIO lines */ + + led_dumpgpio("board_*led_initialize() Entry)"); + + stm32_configgpio(GPIO_LED_YELLOW); + stm32_configgpio(GPIO_LED_GREEN); + + led_dumpgpio("board_*led_initialize() Exit"); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED_GREEN) + { + stm32_gpiowrite(GPIO_LED_GREEN, !ledon); + } + else if (led == BOARD_LED_YELLOW) + { + stm32_gpiowrite(GPIO_LED_YELLOW, !ledon); + } +} +#endif + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +#ifndef CONFIG_ARCH_LEDS +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_LED_YELLOW_BIT) == 0); + stm32_gpiowrite(GPIO_LED_YELLOW, (ledset & BOARD_LED_YELLOW_BIT) == 0); +} +#endif + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_on(int led) +{ + switch (led) + { + default: + case LED_STARTED: + case LED_HEAPALLOCATE: + case LED_IRQSENABLED: + stm32_gpiowrite(GPIO_LED_GREEN, false); + stm32_gpiowrite(GPIO_LED_YELLOW, false); + break; + + case LED_STACKCREATED: + stm32_gpiowrite(GPIO_LED_GREEN, true); + stm32_gpiowrite(GPIO_LED_YELLOW, false); + g_initialized = true; + break; + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + stm32_gpiowrite(GPIO_LED_YELLOW, true); + break; + + case LED_IDLE : /* IDLE */ + stm32_gpiowrite(GPIO_LED_GREEN, false); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_off(int led) +{ + switch (led) + { + default: + case LED_STARTED: + case LED_HEAPALLOCATE: + case LED_IRQSENABLED: + case LED_STACKCREATED: + stm32_gpiowrite(GPIO_LED_GREEN, false); + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + stm32_gpiowrite(GPIO_LED_YELLOW, false); + break; + + case LED_IDLE: /* IDLE */ + stm32_gpiowrite(GPIO_LED_GREEN, g_initialized); + break; + } +} +#endif diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c new file mode 100644 index 0000000000000..50e199d75dca3 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include "chip.h" +#include "stm32.h" +#include "olimexino-stm32.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* Setup CS */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(USER_CSN); +#endif + +#ifdef CONFIG_STM32_SPI2 + stm32_configgpio(MMCSD_CSN); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver + * to the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + if (devid == SPIDEV_USER(0)) + { + stm32_gpiowrite(USER_CSN, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(MMCSD_CSN, !selected); + } +#endif +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + /* No switch on SD card socket so assume it is here */ + + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c new file mode 100644 index 0000000000000..fbbca672512e5 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_set_pwr_callback() + * + * Description: + * Input Parameters: + * pwr_changed_handler: An interrupt handler that will be called on VBUS + * power state changes. + * + ****************************************************************************/ + +void stm32_usb_set_pwr_callback(xcpt_t pwr_changed_handler) +{ + stm32_gpiosetevent(GPIO_USB_VBUS, true, true, true, + pwr_changed_handler, NULL); +} + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUPN); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can + * be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUPN, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..9a9a44a028fef --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "olimexino-stm32.h" + +/* There is nothing to do here if SPI support is not selected. */ + +#ifdef CONFIG_STM32_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_OLIMEXINO_STM32 +# undef OLIMEXINO_STM32_MMCSDSLOTNO +# define OLIMEXINO_STM32_MMCSDSLOTNO 0 +# undef OLIMEXINO_STM32_MMCSDSPIPORTNO +# define OLIMEXINO_STM32_MMCSDSPIPORTNO 2 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + + struct spi_dev_s *spi; + int ret; + + /* First, get an instance of the SPI interface */ + + syslog(LOG_INFO, "Initializing SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(OLIMEXINO_STM32_MMCSDSPIPORTNO); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO); + + /* Now bind the SPI interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SPI to the MMC/SD driver, minor=%d slot=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1, OLIMEXINO_STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, + OLIMEXINO_STM32_MMCSDSLOTNO, spi); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port %d to MMC/SD minor=%d slot=%d %d\n", + OLIMEXINO_STM32_MMCSDSPIPORTNO, CONFIG_SYSTEM_USBMSC_DEVMINOR1, + OLIMEXINO_STM32_MMCSDSLOTNO, ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + + return OK; +} + +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32f1/shenzhou/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/CMakeLists.txt new file mode 100644 index 0000000000000..23fa95383dd8e --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/shenzhou/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/Kconfig b/boards/arm/stm32f1/shenzhou/Kconfig similarity index 100% rename from boards/arm/stm32/shenzhou/Kconfig rename to boards/arm/stm32f1/shenzhou/Kconfig diff --git a/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig new file mode 100644 index 0000000000000..cc6a676e941f6 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=12500000 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=1 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig new file mode 100644 index 0000000000000..39fd4cf05d07b --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig @@ -0,0 +1,126 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ADS7843E_SPIDEV=3 +CONFIG_ADS7843E_SWAPXY=y +CONFIG_ADS7843E_THRESHX=39 +CONFIG_ADS7843E_THRESHY=51 +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_ETH0_PHY_DM9161=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INPUT=y +CONFIG_INPUT_ADS7843E=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_SSD1289=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_LISTENERSTACK=1596 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_CALIBRATION_LISTENERSTACK=1024 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_KEYBOARD_LISTENERSTACK=1024 +CONFIG_NXWM_NXTERM_STACKSIZE=1596 +CONFIG_NXWM_STARTWINDOW_STACKSIZE=1596 +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=101 +CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2012 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_REMAP=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=1596 +CONFIG_SYSTEM_TELNETD_STACKSIZE=1596 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig new file mode 100644 index 0000000000000..9d4170bfa9e3d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="shenzhou" +CONFIG_ARCH_BOARD_SHENZHOU=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DM9161=y +CONFIG_EXAMPLES_THTTPD=y +CONFIG_EXAMPLES_THTTPD_DRIPADDR=0xc0a80001 +CONFIG_EXAMPLES_THTTPD_NOMAC=y +CONFIG_FS_NXFFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="thttp_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MTD=y +CONFIG_MTD_W25=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETINIT_IPADDR=0xc0a80032 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_THTTPD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=768 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFLAT=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_BKP=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=17 +CONFIG_STM32_PHYSR_100FD=0x8000 +CONFIG_STM32_PHYSR_100HD=0x4000 +CONFIG_STM32_PHYSR_10FD=0x2000 +CONFIG_STM32_PHYSR_10HD=0x1000 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0xf000 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_THTTPD_CGI_BYTECOUNT=20000 +CONFIG_THTTPD_CGI_PRIORITY=50 +CONFIG_THTTPD_CGI_STACKSIZE=1024 +CONFIG_THTTPD_IOBUFFERSIZE=1024 +CONFIG_THTTPD_IPADDR=0xc0a80032 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/shenzhou/include/board.h b/boards/arm/stm32f1/shenzhou/include/board.h new file mode 100644 index 0000000000000..858074f77dfe5 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/include/board.h @@ -0,0 +1,463 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* PLL output is 72MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d5 /* 25MHz / 5 => 5MHz */ +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx8 /* 5MHz * 8 => 40MHz */ +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d5 /* 40MHz / 5 => 8MHz */ +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9 => 72Mhz */ +#define STM32_PLL_FREQUENCY (72000000) + +/* SYCLLK and HCLK are the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* MCO output driven by PLL3. + * From above, we already have PLL3 input frequency as: + * + * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz + */ + +#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO) +# define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK /* Source: PLL3 */ +# define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_KEY1 0 /* Name printed on board */ +#define BUTTON_KEY2 1 +#define BUTTON_KEY3 2 +#define BUTTON_KEY4 3 +#define NUM_BUTTONS 4 + +#define BUTTON_USERKEY2 BUTTON_KEY1 /* Names in schematic */ +#define BUTTON_USERKEY BUTTON_KEY2 +#define BUTTON_TAMPER BUTTON_KEY3 +#define BUTTON_WAKEUP BUTTON_KEY4 + +#define BUTTON_KEY1_BIT (1 << BUTTON_KEY1) +#define BUTTON_KEY2_BIT (1 << BUTTON_KEY2) +#define BUTTON_KEY3_BIT (1 << BUTTON_KEY3) +#define BUTTON_KEY4_BIT (1 << BUTTON_KEY4) + +#define BUTTON_USERKEY2_BIT BUTTON_KEY1_BIT +#define BUTTON_USERKEY_BIT BUTTON_KEY2_BIT +#define BUTTON_TAMPER_BIT BUTTON_KEY3_BIT +#define BUTTON_WAKEUP_BIT BUTTON_KEY4_BIT + +/* Relays */ + +#define NUM_RELAYS 2 + +/* Pin selections ***********************************************************/ + +/* Ethernet + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in RMII + * 48 PB11 MII_TX_EN Ethernet PHY mode. + * 51 PB12 MII_TXD0 Ethernet PHY + * 52 PB13 MII_TXD1 Ethernet PHY + * 16 PC1 MII_MDC Ethernet PHY + * 34 PC5 MII_INT Ethernet PHY + * 55 PD8 MII_RX_DV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 55 PD8 RMII_CRSDV Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 56 PD9 MII_RXD0 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * 57 PD10 MII_RXD1 Ethernet PHY. Requires CONFIG_STM32_ETH_REMAP + * + * The board desdign can support a 50MHz external clock to drive the PHY + * (U9). However, on my board, U9 is not present. + * + * 67 PA8 MCO DM9161AEP + */ + +#ifdef CONFIG_STM32_ETHMAC +# ifndef CONFIG_STM32_ETH_REMAP +# error "STM32 Ethernet requires CONFIG_STM32_ETH_REMAP" +# endif +# ifndef CONFIG_STM32_RMII +# error "STM32 Ethernet requires CONFIG_STM32_RMII" +# endif +# ifndef CONFIG_STM32_RMII_MCO +# error "STM32 Ethernet requires CONFIG_STM32_RMII_MCO" +# endif +#endif + +/* USB + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USB_VBUS MINI-USB-AB. JP3 + * 69 PA10 USB_ID MINI-USB-AB. JP5 + * 70 PA11 USB_DM MINI-USB-AB + * 71 PA12 USB_DP MINI-USB-AB + * 95 PB8 USB_PWR Drives USB VBUS + */ + +/* UARTS/USARTS + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP + * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 87 PD6 USART2_RX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP + * 86 PD5 485_TX Same as USART2_TX but goes to SP3485 + * 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4) + */ + +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_STM32_USART1_REMAP) +# error "CONFIG_STM32_USART1 requires CONFIG_STM32_USART1_REMAP" +#endif + +#if defined(CONFIG_STM32_USART2) && !defined(CONFIG_STM32_USART2_REMAP) +# error "CONFIG_STM32_USART2 requires CONFIG_STM32_USART2_REMAP" +#endif + +/* SPI + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. + * Requires !CONFIG_STM32_SPI1_REMAP + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. + * Requires CONFIG_STM32_SPI3_REMAP. + */ + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_STM32_SPI1_REMAP) +# error "CONFIG_STM32_SPI1 must not have CONFIG_STM32_SPI1_REMAP" +#endif + +#if defined(CONFIG_STM32_SPI3) && !defined(CONFIG_STM32_SPI3_REMAP) +# error "CONFIG_STM32_SPI3 requires CONFIG_STM32_SPI3_REMAP" +#endif + +/* DAC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 29 PA4 DAC_OUT1 To CON5(CN14) + * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 + */ + +/* ADC + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) + * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) + * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 + */ + +/* CAN + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 91 PB5 CAN2_RX Requires CONFIG_STM32_CAN2_REMAP. + * 92 PB6 CAN2_TX Requires CONFIG_STM32_CAN2_REMAP. See also JP11 + * 81 PD0 CAN1_RX Requires CONFIG_STM32_CAN1_REMAP2. + * 82 PD1 CAN1_TX Requires CONFIG_STM32_CAN1_REMAP2. + */ + +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_REMAP2) +# error "CONFIG_STM32_CAN1 requires CONFIG_STM32_CAN1_REMAP2" +#endif + +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_REMAP) +# error "CONFIG_STM32_CAN2 requires CONFIG_STM32_CAN2_REMAP" +#endif + +/* I2C + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 92 PB6 I2C1_SCL Requires !CONFIG_STM32_I2C1_REMAP + * 93 PB7 I2C1_SDA + */ + +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_STM32_I2C1_REMAP) +# error "CONFIG_STM32_I2C1 must not have CONFIG_STM32_I2C1_REMAP" +#endif + +/* I2S + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 51 PB12 I2S_WS GPIO_I2S2_WS. Audio DAC + * 52 PB13 I2S_CK GPIO_I2S2_CK. Audio DAC + * 54 PB15 I2S_DIN ??? Audio DAC data in. + * 63 PC6 I2S_MCK GPIO_I2S2_MCK. Audio DAC. Active low: Pulled high + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm32_lcdclear(uint16_t color); + +/**************************************************************************** + * Relay control functions + * + * Description: + * Non-standard functions for relay control from the Shenzhou board. + * + * NOTE: These must match the prototypes in include/nuttx/arch.h + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_RELAYS +void up_relaysinit(void); +void relays_setstat(int relays, bool stat); +bool relays_getstat(int relays); +void relays_setstats(uint32_t relays_stat); +uint32_t relays_getstats(void); +void relays_onoff(int relays, uint32_t mdelay); +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay); +void relays_resetmode(int relays); +void relays_powermode(int relays); +void relays_resetmodes(uint32_t relays_stat); +void relays_powermodes(uint32_t relays_stat); +#endif + +/**************************************************************************** + * Chip ID functions + * + * Description: + * Non-standard functions to obtain chip ID information. + * + ****************************************************************************/ + +const char *stm32_getchipid(void); +const char *stm32_getchipid_string(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* SPI3 */ + +#define GPIO_SPI3_NSS GPIO_ADJUST_MODE(GPIO_SPI3_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_SCK GPIO_ADJUST_MODE(GPIO_SPI3_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_MISO GPIO_ADJUST_MODE(GPIO_SPI3_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI3_MOSI GPIO_ADJUST_MODE(GPIO_SPI3_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_SHENZHOU_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/shenzhou/scripts/Make.defs b/boards/arm/stm32f1/shenzhou/scripts/Make.defs new file mode 100644 index 0000000000000..d43905ce21972 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32f1/shenzhou/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +# Pick the linker script + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +MKNXFLAT = mknxflat +LDNXFLAT = ldnxflat + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +#NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections + +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/shenzhou/scripts/ld.script b/boards/arm/stm32f1/shenzhou/scripts/ld.script new file mode 100644 index 0000000000000..8487eb9e18295 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and + * 64K of SRAM beginning at address 0x2000:0000. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu new file mode 100644 index 0000000000000..02c796db472e9 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F107VC has 256K of FLASH beginning at address 0x0800:0000 and + * 64K of SRAM beginning at address 0x2000:0000. Here we assume that the + * STMicro DFU bootloader is being used. In that case, the correct load .text + * load address is 0x08003000 (leaving 208K). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F107VC has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt new file mode 100644 index 0000000000000..162ec56a04e9e --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt @@ -0,0 +1,73 @@ +# ############################################################################## +# boards/arm/stm32f1/shenzhou/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_RELAYS) + list(APPEND SRCS stm32_relays.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +# NOTE: SSD1289 is not supported on the board + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +else() + list(APPEND SRCS stm32_ili93xx.c) +endif() + +if(CONFIG_INPUT_ADS7843E) + list(APPEND SRCS stm32_touchscreen.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/shenzhou/src/Make.defs b/boards/arm/stm32f1/shenzhou/src/Make.defs new file mode 100644 index 0000000000000..262f74241035f --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/stm32f1/shenzhou/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_mmcsd.c stm32_chipid.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_RELAYS),y) +CSRCS += stm32_relays.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_MTD_W25),y) +CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +# NOTE: SSD1289 is not supported on the board + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +else +CSRCS += stm32_ili93xx.c +endif + +ifeq ($(CONFIG_INPUT_ADS7843E),y) +CSRCS += stm32_touchscreen.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/shenzhou/src/shenzhou.h b/boards/arm/stm32f1/shenzhou/src/shenzhou.h similarity index 99% rename from boards/arm/stm32/shenzhou/src/shenzhou.h rename to boards/arm/stm32f1/shenzhou/src/shenzhou.h index 9bf3f825b80ea..089c07fd6f15d 100644 --- a/boards/arm/stm32/shenzhou/src/shenzhou.h +++ b/boards/arm/stm32f1/shenzhou/src/shenzhou.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/shenzhou.h + * boards/arm/stm32f1/shenzhou/src/shenzhou.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_adc.c b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c new file mode 100644 index 0000000000000..922698d8e7400 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "shenzhou.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. + * The only internal signal for ADC testing is the potentiometer input: + * + * ADC1_IN10(PC0) Potentiometer + * + * External signals are also available on CON5 CN14: + * + * ADC_IN8 (PB0) CON5 CN14 Pin2 + * ADC_IN9 (PB1) CON5 CN14 Pin1 + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* {10, 8, 9}; */ + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c new file mode 100644 index 0000000000000..4ea472253b4dd --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define SHENZHOU_LED1 (1 << 0) +#define SHENZHOU_LED2 (1 << 1) +#define SHENZHOU_LED3 (1 << 2) +#define SHENZHOU_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((SHENZHOU_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((SHENZHOU_LED2|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((SHENZHOU_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((SHENZHOU_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((SHENZHOU_LED1|SHENZHOU_LED2|SHENZHOU_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((SHENZHOU_LED1|SHENZHOU_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((SHENZHOU_LED3|SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((SHENZHOU_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((SHENZHOU_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((SHENZHOU_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((SHENZHOU_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((SHENZHOU_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((SHENZHOU_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((clrbits & SHENZHOU_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & SHENZHOU_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & SHENZHOU_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & SHENZHOU_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + /* All LEDs are pulled up and, hence, active low */ + + if ((setbits & SHENZHOU_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((setbits & SHENZHOU_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((setbits & SHENZHOU_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((setbits & SHENZHOU_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: up_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void up_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_boot.c b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c new file mode 100644 index 0000000000000..c2e3492aaa343 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c @@ -0,0 +1,270 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_W25 1 + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define STM32_MMCSDSPIPORTNO 1 /* SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* Only one slot */ + +#ifndef CONFIG_STM32_SPI1 +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != STM32_MMCSDSLOTNO +# error "Only one MMC/SD slot: Slot 0" +# endif + +/* Verify configured SPI port number */ + +# if defined(CONFIG_NSH_MMCSDSPIPORTNO) && CONFIG_NSH_MMCSDSPIPORTNO != STM32_MMCSDSPIPORTNO +# error "Only one MMC/SD port: SPI1" +# endif +#endif + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return; + } +#endif + +#ifdef HAVE_MMCSD + /* Initialize the SPI-based MMC/SD slot */ + + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot %d: %d\n", + STM32_MMCSDSLOTNO, ret); + return; + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor + * for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_INPUT_ADS7843E + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c new file mode 100644 index 0000000000000..15dcb93fae35f --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "shenzhou.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Shenzhou button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USERKEY2, GPIO_BTN_USERKEY, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_can.c b/boards/arm/stm32f1/shenzhou/src/stm32_can.c new file mode 100644 index 0000000000000..5a8f603b946e7 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_can.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "shenzhou.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c new file mode 100644 index 0000000000000..8ae5a0fd1813d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_chipid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +const char *stm32_getchipid(void) +{ + static char cpuid[12]; + int i; + + for (i = 0; i < 12; i++) + { + cpuid[i] = getreg8(0x1ffff7e8 + i); + } + + return cpuid; +} + +const char *stm32_getchipid_string(void) +{ + static char cpuid[27]; + int c; + int i; + + for (i = 0, c = 0; i < 12; i++) + { + snprintf(&cpuid[c], sizeof(cpuid) - c, + "%02X", getreg8(0x1ffff7e8 + 11 - i)); + c += 2; + if (i % 4 == 3) + { + cpuid[c++] = '-'; + } + } + + cpuid[26] = '\0'; + return cpuid; +} diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_ili93xx.c rename to boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c index eb190ae7884a3..5610e1946a196 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ili93xx.c + * boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..d9e7cbfa97dac --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI1 connects to the SD CARD (and to the SPI FLASH) */ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSPIPORTNO 1 /* Port is SPI1 */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +#ifndef CONFIG_STM32_SPI1 +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if MMC/SD driver support is not selected */ + +#ifndef CONFIG_MMCSD +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SPI1=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct spi_dev_s *spi; + int ret; + + /* Get the SPI port */ + + finfo("Initializing SPI port %d\n", STM32_MMCSDSPIPORTNO); + + spi = stm32_spibus_initialize(STM32_MMCSDSPIPORTNO); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port %d\n", + STM32_MMCSDSPIPORTNO); + return -ENODEV; + } + + finfo("Successfully initialized SPI port %d\n", STM32_MMCSDSPIPORTNO); + + /* Bind the SPI port to the slot */ + + finfo("Binding SPI port %d to MMC/SD slot %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); + + ret = mmcsd_spislotinitialize(minor, STM32_MMCSDSLOTNO, spi); + if (ret < 0) + { + ferr("ERROR: Failed to bind SPI port %d to MMC/SD slot %d: %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO, ret); + return ret; + } + + finfo("Successfully bound SPI port %d to MMC/SD slot %d\n", + STM32_MMCSDSPIPORTNO, STM32_MMCSDSLOTNO); +#endif + return OK; +} diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_relays.c b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c new file mode 100644 index 0000000000000..6c7fd95eeaa09 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c @@ -0,0 +1,274 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_relays.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "shenzhou.h" + +#ifdef CONFIG_ARCH_RELAYS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RELAYS_MIN_RESET_TIME 5 +#define RELAYS_RESET_MTIME 5 +#define RELAYS_POWER_MTIME 50 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_relays_stat = 0; +static bool g_relays_init = false; + +static const uint16_t g_relays[NUM_RELAYS] = +{ + GPIO_RELAYS_R00 +#ifdef GPIO_RELAYS_R01 + , GPIO_RELAYS_R01 +#endif +#ifdef GPIO_RELAYS_R02 + , GPIO_RELAYS_R02 +#endif +#ifdef GPIO_RELAYS_R03 + , GPIO_RELAYS_R03 +#endif +#ifdef GPIO_RELAYS_R04 + , GPIO_RELAYS_R04 +#endif +#ifdef GPIO_RELAYS_R05 + , GPIO_RELAYS_R05 +#endif +#ifdef GPIO_RELAYS_R06 + , GPIO_RELAYS_R06 +#endif +#ifdef GPIO_RELAYS_R07 + , GPIO_RELAYS_R07 +#endif +#ifdef GPIO_RELAYS_R08 + , GPIO_RELAYS_R08 +#endif +#ifdef GPIO_RELAYS_R09 + , GPIO_RELAYS_R09 +#endif +#ifdef GPIO_RELAYS_R10 + , GPIO_RELAYS_R10 +#endif +#ifdef GPIO_RELAYS_R11 + , GPIO_RELAYS_R11 +#endif +#ifdef GPIO_RELAYS_R12 + , GPIO_RELAYS_R12 +#endif +#ifdef GPIO_RELAYS_R13 + , GPIO_RELAYS_R13 +#endif +#ifdef GPIO_RELAYS_R14 + , GPIO_RELAYS_R14 +#endif +#ifdef GPIO_RELAYS_R15 + , GPIO_RELAYS_R15 +#endif +#ifdef GPIO_RELAYS_R16 + , GPIO_RELAYS_R16 +#endif +#ifdef GPIO_RELAYS_R17 + , GPIO_RELAYS_R17 +#endif +#ifdef GPIO_RELAYS_R18 + , GPIO_RELAYS_R18 +#endif +#ifdef GPIO_RELAYS_R19 + , GPIO_RELAYS_R19 +#endif +#ifdef GPIO_RELAYS_R20 + , GPIO_RELAYS_R20 +#endif +#ifdef GPIO_RELAYS_R21 + , GPIO_RELAYS_R21 +#endif +#ifdef GPIO_RELAYS_R22 + , GPIO_RELAYS_R22 +#endif +#ifdef GPIO_RELAYS_R23 + , GPIO_RELAYS_R23 +#endif +#ifdef GPIO_RELAYS_R24 + , GPIO_RELAYS_R24 +#endif +#ifdef GPIO_RELAYS_R25 + , GPIO_RELAYS_R25 +#endif +#ifdef GPIO_RELAYS_R26 + , GPIO_RELAYS_R26 +#endif +#ifdef GPIO_RELAYS_R27 + , GPIO_RELAYS_R27 +#endif +#ifdef GPIO_RELAYS_R28 + , GPIO_RELAYS_R28 +#endif +#ifdef GPIO_RELAYS_R29 + , GPIO_RELAYS_R29 +#endif +#ifdef GPIO_RELAYS_R30 + , GPIO_RELAYS_R30 +#endif +#ifdef GPIO_RELAYS_R31 + , GPIO_RELAYS_R31 +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void up_relaysinit(void) +{ + int i; + + if (g_relays_init) + { + return; + } + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_RELAYS; i++) + { + stm32_configgpio(g_relays[i]); + stm32_gpiowrite(g_relays[i], false); + } + + g_relays_init = true; +} + +void relays_setstat(int relays, bool stat) +{ + if ((unsigned)relays < NUM_RELAYS) + { + stm32_gpiowrite(g_relays[relays], stat); + if (!stat) + { + g_relays_stat &= ~(1 << relays); + } + else + { + g_relays_stat |= (1 << relays); + } + } +} + +bool relays_getstat(int relays) +{ + if ((unsigned)relays < NUM_RELAYS) + { + return (g_relays_stat & (1 << relays)) != 0; + } + + return false; +} + +void relays_setstats(uint32_t relays_stat) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_setstat(i, (relays_stat & (1 << i)) != 0); + } +} + +uint32_t relays_getstats(void) +{ + return (uint32_t)g_relays_stat; +} + +void relays_onoff(int relays, uint32_t mdelay) +{ + if ((unsigned)relays < NUM_RELAYS) + { + if (mdelay > 0) + { + if (relays_getstat(relays)) + { + relays_setstat(relays, false); + nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); + } + + relays_setstat(relays, true); + nxsched_usleep(mdelay * 100 * 1000); + relays_setstat(relays, false); + } + } +} + +void relays_onoffs(uint32_t relays_stat, uint32_t mdelay) +{ + int i; + + for (i = 0; i < NUM_RELAYS; i++) + { + relays_onoff(i, mdelay); + } +} + +void relays_resetmode(int relays) +{ + relays_onoff(relays, RELAYS_RESET_MTIME); +} + +void relays_powermode(int relays) +{ + relays_onoff(relays, RELAYS_POWER_MTIME); +} + +void relays_resetmodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_RESET_MTIME); +} + +void relays_powermodes(uint32_t relays_stat) +{ + relays_onoffs(relays_stat, RELAYS_POWER_MTIME); +} + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_spi.c b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c new file mode 100644 index 0000000000000..d77612c7eb6f1 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "shenzhou.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Shenzhou board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_SD_CS); /* SD card chip select */ + stm32_configgpio(GPIO_SD_CD); /* SD card detect */ + stm32_configgpio(GPIO_FLASH_CS); /* FLASH chip select */ +#endif + + /* SPI3 connects to TFT LCD module and the RF24L01 2.4G wireless module */ + +#ifdef CONFIG_STM32_SPI3 + stm32_configgpio(GPIO_TP_CS); /* Touchscreen chip select */ + stm32_configgpio(GPIO_LCDDF_CS); /* Data flash chip select (on the LCD module) */ + stm32_configgpio(GPIO_LCDSD_CS); /* SD chip select (on the LCD module) */ + stm32_configgpio(GPIO_WIRELESS_CS); /* Wireless chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including stm32_spibus_initialize()) are provided by + * common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI1 connects to the SD CARD and to the SPI FLASH */ + + if (devid == SPIDEV_MMCSD(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SD_CS, !selected); + } + else if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + /* The card detect pin is pulled up so that we detect the presence of a + * card by see a low value on the input pin. + */ + + if (stm32_gpioread(GPIO_SD_CD)) + { + return 0; + } + + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* SPI3 connects to TFT LCD (for touchscreen and SD) and the RF24L01 2.4G + * wireless module. + */ + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_TP_CS, !selected); + } + else if (devid == SPIDEV_MMCSD(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCDDF_CS, !selected); + } + else if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_LCDSD_CS, !selected); + } + else if (devid == SPIDEV_WIRELESS(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_WIRELESS_CS, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..d4bbe679b1b94 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c @@ -0,0 +1,597 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#undef CONFIG_LCD_FASTCONFIG +#define CONFIG_LCD_FASTCONFIG 1 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of this driver */ + +struct stm32_lower_s +{ + struct ssd1289_lcd_s dev; /* This is externally visible the driver state */ + struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ + bool output; /* True: Configured for output */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +#ifdef CONFIG_LCD_REGDEBUG +static void stm32_lcdshow(struct stm32_lower_s *priv, + const char *msg); +#else +# define stm32_lcdshow(p,m) +#endif + +static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data); +#ifndef CONFIG_LCD_NOGETRUN +static inline uint16_t stm32_rddata(struct stm32_lower_s *priv); +#endif + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_LCD_NOGETRUN +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +/* Initialization */ + +#ifndef CONFIG_LCD_NOGETRUN +static void stm32_lcdinput(struct stm32_lower_s *priv); +#endif +static void stm32_lcdoutput(struct stm32_lower_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* TFT LCD + * + * -- ---- -------------- --------------------------------------------------- + * PN NAME SIGNAL NOTES + * -- ---- -------------- --------------------------------------------------- + * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) + * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and + * to the W25X16 SPI FLASH + * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) + * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) + * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) + * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) + * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) + * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) + * 58 PD11 SD_CS Active low: Pulled high + * (See also TFT LCD CN13, pin 32) + * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) + * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). + * Schematic is wrong LCD_WR is PB14. + * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) + * 97 PE0 DB00 To TFT LCD (CN13, pin 3) + * 98 PE1 DB01 To TFT LCD (CN13, pin 4) + * 1 PE2 DB02 To TFT LCD (CN13, pin 5) + * 2 PE3 DB03 To TFT LCD (CN13, pin 6) + * 3 PE4 DB04 To TFT LCD (CN13, pin 7) + * 4 PE5 DB05 To TFT LCD (CN13, pin 8) + * 5 PE6 DB06 To TFT LCD (CN13, pin 9) + * 38 PE7 DB07 To TFT LCD (CN13, pin 10) + * 39 PE8 DB08 To TFT LCD (CN13, pin 11) + * 40 PE9 DB09 To TFT LCD (CN13, pin 12) + * 41 PE10 DB10 To TFT LCD (CN13, pin 13) + * 42 PE11 DB11 To TFT LCD (CN13, pin 16) + * 43 PE12 DB12 To TFT LCD (CN13, pin 15) + * 44 PE13 DB13 To TFT LCD (CN13, pin 16) + * 45 PE14 DB14 To TFT LCD (CN13, pin 17) + * 46 PE15 DB15 To TFT LCD (CN13, pin 18) + * + * NOTE: + * The backlight signl NC_BL (CN13, pin 24) is pulled high and not under + * software control + * + * On LCD module: + * -- -------------- -------------------------------------------------------- + * PN SIGNAL NOTES + * -- -------------- -------------------------------------------------------- + * 3 DB01 To LCD DB1 + * 4 DB00 To LCD DB0 + * 5 DB03 To LCD DB3 + * 6 DB02 To LCD DB2 + * 7 DB05 To LCD DB5 + * 8 DB04 To LCD DB4 + * 9 DB07 To LCD DB7 + * 10 DB06 To LCD DB6 + * 11 DB09 To LCD DB9 + * 12 DB08 To LCD DB8 + * 13 DB11 To LCD DB11 + * 14 DB10 To LCD DB10 + * 15 DB13 To LCD DB13 + * 16 DB12 To LCD DB12 + * 17 DB15 To LCD DB15 + * 18 DB14 To LCD DB14 + * 19 RS To LCD RS + * 20 /LCD_CS To LCD CS + * 21 /RD To LCD RD + * 22 /WR To LCD WR + * 23 BL_EN (Not referenced) + * 24 /RESET + * 25 /INT To Touch IC /INT + * 26 MISO To Touch IC DOUT; To AT45DB161B SO; To SD card DAT0 + * 27 LE To 74HC573 that controls LCD 8-bit/16-bit mode + * 28 MOSI To Touch IC DIN; To AT45DB161B SI; To SD card CMD + * 29 /DF_CS To AT45DB161B Data Flash /CS + * 30 SCLK To Touch IC DCLK; To AT45DB161B SCK; To SD card CLK + * 31 /SD_CS To SD card /CS + * 31 /TP_CS To Touch IC CS + */ + +/* LCD GPIO configurations */ + +#ifndef CONFIG_LCD_FASTCONFIG +static const uint32_t g_lcdout[16] = +{ + GPIO_LCD_D0OUT, GPIO_LCD_D1OUT, + GPIO_LCD_D2OUT, GPIO_LCD_D3OUT, + GPIO_LCD_D4OUT, GPIO_LCD_D5OUT, + GPIO_LCD_D6OUT, GPIO_LCD_D7OUT, + GPIO_LCD_D8OUT, GPIO_LCD_D9OUT, + GPIO_LCD_D10OUT, GPIO_LCD_D11OUT, + GPIO_LCD_D12OUT, GPIO_LCD_D13OUT, + GPIO_LCD_D14OUT, GPIO_LCD_D15OUT +}; + +static const uint32_t g_lcdin[16] = +{ + GPIO_LCD_D0IN, GPIO_LCD_D1IN, + GPIO_LCD_D2IN, GPIO_LCD_D3IN, + GPIO_LCD_D4IN, GPIO_LCD_D5IN, + GPIO_LCD_D6IN, GPIO_LCD_D7IN, + GPIO_LCD_D8IN, GPIO_LCD_D9IN, + GPIO_LCD_D10IN, GPIO_LCD_D11IN, + GPIO_LCD_D12IN, GPIO_LCD_D13IN, + GPIO_LCD_D14IN, GPIO_LCD_D15IN +}; +#endif + +static const uint32_t g_lcdconfig[] = +{ + GPIO_LCD_RS, GPIO_LCD_CS, + GPIO_LCD_RD, GPIO_LCD_WR, + GPIO_LCD_LE, +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/* Driver state structure (only supports one LCD) */ + +static struct stm32_lower_s g_lcdlower = +{ + { + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_LCD_NOGETRUN + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight + }, + .drvr = NULL, + .output = false +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_lcdshow + * + * Description: + * Show the state of the interface + * + ****************************************************************************/ + +#ifdef CONFIG_LCD_REGDEBUG +static void stm32_lcdshow(struct stm32_lower_s *priv, + const char *msg) +{ + _info("%s:\n", msg); + _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", + getreg32(LCD_RS_READ), getreg32(LCD_CS_READ), getreg32(LCD_RD_READ), + getreg32(LCD_WR_READ), getreg32(LCD_LE_READ)); + _info(" DATA CR: %08x %08x\n", getreg32(LCD_CRL), getreg32(LCD_CRH)); + if (priv->output) + { + _info(" OUTPUT: %08x\n", getreg32(LCD_ODR)); + } + else + { + _info(" INPUT: %08x\n", getreg32(LCD_IDR)); + } +} +#endif + +/**************************************************************************** + * Name: stm32_wrdata + * + * Description: + * Latch data on D0-D15 and toggle the WR line. + * + ****************************************************************************/ + +static void stm32_wrdata(struct stm32_lower_s *priv, uint16_t data) +{ + /* Make sure D0-D15 are configured as outputs */ + + stm32_lcdoutput(priv); + + /* Latch the 16-bit LCD data and toggle the WR line */ + + putreg32(1, LCD_WR_CLEAR); + putreg32((uint32_t)data, LCD_ODR); + + /* Total WR pulse with should be 50ns wide. */ + + putreg32(1, LCD_WR_SET); +} + +/**************************************************************************** + * Name: stm32_rddata + * + * Description: + * Latch data on D0-D15 and toggle the WR line. + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static inline uint16_t stm32_rddata(struct stm32_lower_s *priv) +{ + uint16_t regval; + + /* Make sure D0-D15 are configured as inputs */ + + stm32_lcdinput(priv); + + /* Toggle the RD line to latch the 16-bit LCD data */ + + putreg32(1, LCD_RD_CLEAR); + + /* Data should appear 250ns after RD. + * Total RD pulse width should be 500nS + */ + + __asm__ __volatile__(" nop\n nop\n nop\n nop\n"); + regval = (uint16_t)getreg32(LCD_IDR); + putreg32(1, LCD_RD_SET); + return regval; +} +#endif + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Select the LCD by setting the LCD_CS low */ + + putreg32(1, LCD_CS_CLEAR); +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* De-select the LCD by setting the LCD_CS high */ + + putreg32(1, LCD_CS_SET); +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Clear the RS signal to select the index address */ + + putreg32(1, LCD_RS_CLEAR); + + /* And write the index */ + + stm32_wrdata(priv, (uint16_t)index); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Set the RS signal to select the data address */ + + putreg32(1, LCD_RS_SET); + + /* Read and return the data */ + + return stm32_rddata(priv); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)dev; + + /* Set the RS signal to select the data address */ + + putreg32(1, LCD_RS_SET); + + /* And write the data */ + + stm32_wrdata(priv, data); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + /* There is no software control over the backlight */ +} + +/**************************************************************************** + * Name: stm32_lcdinput + * + * Description: + * Config data lines for input operations. + * + ****************************************************************************/ + +#ifndef CONFIG_LCD_NOGETRUN +static void stm32_lcdinput(struct stm32_lower_s *priv) +{ +#ifndef CONFIG_LCD_FASTCONFIG + int i; +#endif + + /* Check if we are already configured for input */ + + if (priv->output) + { + /* Configure GPIO data lines as inputs */ + +#ifdef CONFIG_LCD_FASTCONFIG + putreg32(LCD_INPUT, LCD_CRL); + putreg32(LCD_INPUT, LCD_CRH); +#else + for (i = 0; i < 16; i++) + { + stm32_configgpio(g_lcdin[i]); + } +#endif + + /* No longer configured for output */ + + priv->output = false; + } +} +#endif + +/**************************************************************************** + * Name: stm32_lcdoutput + * + * Description: + * Config data lines for output operations. + * + ****************************************************************************/ + +static void stm32_lcdoutput(struct stm32_lower_s *priv) +{ +#ifndef CONFIG_LCD_FASTCONFIG + int i; +#endif + + /* Check if we are already configured for output */ + + if (!priv->output) + { + /* Configure GPIO data lines as outputs */ + +#ifdef CONFIG_LCD_FASTCONFIG + putreg32(LCD_OUTPUT, LCD_CRL); + putreg32(LCD_OUTPUT, LCD_CRH); +#else + for (i = 0; i < 16; i++) + { + stm32_configgpio(g_lcdout[i]); + } +#endif + + /* Now we are configured for output */ + + priv->output = true; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + struct stm32_lower_s *priv = &g_lcdlower; + int i; + + /* Only initialize the driver once */ + + if (!priv->drvr) + { + lcdinfo("Initializing\n"); + + /* Configure GPIO pins */ + + stm32_lcdoutput(priv); + for (i = 0; i < NLCD_CONFIG; i++) + { + stm32_configgpio(g_lcdconfig[i]); + } + + /* Configure and enable the LCD */ + + priv->drvr = ssd1289_lcdinitialize(&priv->dev); + if (!priv->drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + priv->drvr->setpower(priv->drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + struct stm32_lower_s *priv = &g_lcdlower; + DEBUGASSERT(lcddev == 0); + return priv->drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + struct stm32_lower_s *priv = &g_lcdlower; + + /* Turn the display off */ + + priv->drvr->setpower(priv->drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c new file mode 100644 index 0000000000000..c7733ba51f97d --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c @@ -0,0 +1,276 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_ADS7843E +#ifndef CONFIG_INPUT +# error "Touchscreen support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_SPI3 +# error "Touchscreen support requires CONFIG_STM32_SPI3" +#endif + +#ifndef CONFIG_ADS7843E_FREQUENCY +# define CONFIG_ADS7843E_FREQUENCY 500000 +#endif + +#ifndef CONFIG_ADS7843E_SPIDEV +# define CONFIG_ADS7843E_SPIDEV 3 +#endif + +#if CONFIG_ADS7843E_SPIDEV != 3 +# error "CONFIG_ADS7843E_SPIDEV must be three" +#endif + +#ifndef CONFIG_ADS7843E_DEVMINOR +# define CONFIG_ADS7843E_DEVMINOR 0 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_config_s +{ + struct ads7843e_config_s dev; + xcpt_t handler; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the ADS7843E driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(struct ads7843e_config_s *state, xcpt_t isr); +static void tsc_enable(struct ads7843e_config_s *state, bool enable); +static void tsc_clear(struct ads7843e_config_s *state); +static bool tsc_busy(struct ads7843e_config_s *state); +static bool tsc_pendown(struct ads7843e_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the ADS7843E + * driver. This structure provides information about the configuration + * of the ADS7843E and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_config_s g_tscinfo = +{ + { + .frequency = CONFIG_ADS7843E_FREQUENCY, + .attach = tsc_attach, + .enable = tsc_enable, + .clear = tsc_clear, + .busy = tsc_busy, + .pendown = tsc_pendown, + }, + .handler = NULL, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the ADS7843E driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * attach - Attach the ADS7843E interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + * pendown - Return the state of the pen down GPIO input + */ + +static int tsc_attach(struct ads7843e_config_s *state, xcpt_t handler) +{ + struct stm32_config_s *priv = (struct stm32_config_s *)state; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + return OK; +} + +static void tsc_enable(struct ads7843e_config_s *state, bool enable) +{ + struct stm32_config_s *priv = (struct stm32_config_s *)state; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv->handler || !enable); + + /* Attach and enable, or detach and disable */ + + iinfo("enable:%d\n", enable); + if (enable) + { + stm32_gpiosetevent(GPIO_TP_INT, true, true, false, + priv->handler, NULL); + } + else + { + stm32_gpiosetevent(GPIO_TP_INT, false, false, false, + NULL, NULL); + } +} + +static void tsc_clear(struct ads7843e_config_s *state) +{ + /* Does nothing */ +} + +static bool tsc_busy(struct ads7843e_config_s *state) +{ + /* Hmmm... The ADS7843E BUSY pin is not brought out on the Shenzhou board. + * We will most certainly have to revisit this. There is this cryptic + * statement in the XPT2046 spec: "No DCLK delay required with dedicated + * serial port." + * + * The busy state is used by the ADS7843E driver to control the delay + * between sending the command, then reading the returned data. + */ + + return false; +} + +static bool tsc_pendown(struct ads7843e_config_s *state) +{ + /* XPT2046 uses an an internal pullup resistor. The PENIRQ output goes low + * due to the current path through the touch screen to ground, which + * initiates an interrupt to the processor via TP_INT. + */ + + bool pendown = !stm32_gpioread(GPIO_TP_INT); + iinfo("pendown:%d\n", pendown); + return pendown; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ + struct spi_dev_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Configure and enable the ADS7843E interrupt pin as an input. */ + + stm32_configgpio(GPIO_TP_INT); + + /* Get an instance of the SPI interface */ + + dev = stm32_spibus_initialize(CONFIG_ADS7843E_SPIDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); + return -ENODEV; + } + + /* Initialize and register the SPI touschscreen device */ + + ret = ads7843e_register(dev, &g_tscinfo.dev, + CONFIG_ADS7843E_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to initialize SPI bus %d\n", + CONFIG_ADS7843E_SPIDEV); + + /* up_spiuninitialize(dev); */ + + return -ENODEV; + } + + return OK; +} + +#endif /* CONFIG_INPUT_ADS7843E */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_usb.c b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c new file mode 100644 index 0000000000000..bbc47272d2334 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "shenzhou.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..bce9cfc30f6b0 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c new file mode 100644 index 0000000000000..9b18917f728a0 --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "shenzhou.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/shenzhou/src/stm32_w25.c b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c new file mode 100644 index 0000000000000..1658b957ca3ab --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c @@ -0,0 +1,145 @@ +/**************************************************************************** + * boards/arm/stm32f1/shenzhou/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include + +# include "stm32_spi.h" +#endif + +#include "shenzhou.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and NXFFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_NXFFS) +# warning "Can't support both FAT and NXFFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#ifdef CONFIG_FS_NXFFS + char devname[12]; +#endif + int ret; + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + ferr("ERROR: Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + ferr("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n"); + return -ENODEV; + } + +#ifndef CONFIG_FS_NXFFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", -ret); + return ret; + } + + /* Mount the file system at /mnt/w25 */ + + snprintf(devname, sizeof(devname), "/mnt/w25%c", 'a' + minor); + ret = nx_mount(NULL, devname, "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif +#endif + + return OK; +} diff --git a/boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f1/shenzhou/tools/oocd.sh b/boards/arm/stm32f1/shenzhou/tools/oocd.sh new file mode 100755 index 0000000000000..e965ac36e90cc --- /dev/null +++ b/boards/arm/stm32f1/shenzhou/tools/oocd.sh @@ -0,0 +1,90 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +unset DEBUG + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + DEBUG=-d3 + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/shenzhou/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="${DEBUG} -s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/shenzhou/tools/stm32.cfg b/boards/arm/stm32f1/shenzhou/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/stm32.cfg rename to boards/arm/stm32f1/shenzhou/tools/stm32.cfg diff --git a/boards/arm/stm32/shenzhou/tools/usb-driver.txt b/boards/arm/stm32f1/shenzhou/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/shenzhou/tools/usb-driver.txt rename to boards/arm/stm32f1/shenzhou/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt new file mode 100644 index 0000000000000..c8d5f73a4984d --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/Kconfig b/boards/arm/stm32f1/stm3210e-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3210e-eval/Kconfig rename to boards/arm/stm32f1/stm3210e-eval/Kconfig diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig new file mode 100644 index 0000000000000..ceb671630bab5 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_COMPOSITE_CONFIGSTR="system/composite" +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_PRODUCTSTR="Composite Device" +CONFIG_COMPOSITE_SERIALSTR="12345" +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="conn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_COMPOSITE=y +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..7b6a0aa141087 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..9fab1ef45c748 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig @@ -0,0 +1,110 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf +CONFIG_EXAMPLES_NXHELLO_FONTID=6 +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=2 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXTK_BORDERCOLOR1=0xd69a +CONFIG_NXTK_BORDERCOLOR2=0xad55 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig new file mode 100644 index 0000000000000..280f178d64d4b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig new file mode 100644 index 0000000000000..aeaf6de160c35 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXTERM=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxterm_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=256 +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2012 +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig new file mode 100644 index 0000000000000..bf5f62f52ccec --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig @@ -0,0 +1,95 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NXHELLO_DEFAULT_FONT is not set +# CONFIG_EXAMPLES_NX_DEFAULT_COLORS is not set +# CONFIG_EXAMPLES_NX_DEFAULT_FONT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_CUSTOM_PMINIT=y +CONFIG_ARCH_IDLE_CUSTOM=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_FONTCOLOR=0xffdf +CONFIG_EXAMPLES_NXHELLO_FONTID=6 +CONFIG_EXAMPLES_NX_BGCOLOR=0x0011 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_NX_COLOR1=0xaedc +CONFIG_EXAMPLES_NX_COLOR2=0xe7ff +CONFIG_EXAMPLES_NX_FONTCOLOR=0x0000 +CONFIG_EXAMPLES_NX_FONTID=0 +CONFIG_EXAMPLES_NX_TBCOLOR=0xd69a +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_MAXCONTRAST=100 +CONFIG_LCD_MAXPOWER=100 +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_RPORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PM=y +CONFIG_PM_BUTTONS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_FREQUENCY=16384 +CONFIG_RTC_HIRES=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM3210E_LCD=y +CONFIG_STM3210E_LCD_BACKLIGHT=y +CONFIG_STM3210E_LCD_PWM=y +CONFIG_STM3210E_R61580_DISABLE=y +CONFIG_STM32_BKP=y +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..862ffdecb9ea9 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_INIT_ENTRYPOINT="msconn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_BULKINREQLEN=256 +CONFIG_USBMSC_BULKOUTREQLEN=256 +CONFIG_USBMSC_EPBULKIN=5 +CONFIG_USBMSC_NRDREQS=2 +CONFIG_USBMSC_NWRREQS=2 +CONFIG_USBMSC_PRODUCTSTR="USBdev Storage" +CONFIG_USBMSC_REMOVABLE=y +CONFIG_USBMSC_VERSIONNO=0x0399 diff --git a/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig new file mode 100644 index 0000000000000..0fda54afcae8a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3210e-eval" +CONFIG_ARCH_BOARD_STM3210E_EVAL=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_INIT_ENTRYPOINT="usbserial_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_PL2303=y +CONFIG_PL2303_PRODUCTSTR="USBdev Serial" +CONFIG_PL2303_RXBUFSIZE=512 +CONFIG_PL2303_TXBUFSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=23 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2009 +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm3210e-eval/include/board.h b/boards/arm/stm32f1/stm3210e-eval/include/board.h new file mode 100644 index 0000000000000..ad0c8628d22e4 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/include/board.h @@ -0,0 +1,402 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/* Logic in arch/arm/src and boards/ may need to include these file prior to + * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be + * included here because board.h is used in other contexts where the STM32 + * internal header files are not available. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 2-7, 12-14 */ + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* SRAM definitions *********************************************************/ + +/* The 8 Mbit SRAM is provided on the PT3 board using the FSMC_NE3 chip + * select. + */ + +/* This is the Bank1 SRAM3 address: */ + +#define BOARD_SRAM_BASE 0x68000000 /* Bank2 SRAM3 base address */ +#define BOARD_SRAM_SIZE (1*1024*1024) /* 8-Mbit = 1-Mbyte */ + +/* LED definitions **********************************************************/ + +/* The STM3210E-EVAL board has 4 LEDs that we will encode as: */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* The STM3210E-EVAL supports several buttons + * + * Reset -- Connected to NRST + * Wakeup -- Connected to PA.0 + * Tamper -- Connected to PC.13 + * Key -- Connected to PG.8 + * + * And a Joystick + * + * Joystick center -- Connected to PG.7 + * Joystick down -- Connected to PD.3 + * Joystick left -- Connected to PG.14 + * Joystick right -- Connected to PG.13 + * Joystick up -- Connected to PG.15 + * + * The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should be + * used by the discrete joystick driver. + */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_KEY 2 + +#ifdef CONFIG_INPUT_DJOYSTICK +# define NUM_BUTTONS 3 +#else +# define JOYSTICK_SEL 3 +# define JOYSTICK_DOWN 4 +# define JOYSTICK_LEFT 5 +# define JOYSTICK_RIGHT 6 +# define JOYSTICK_UP 7 + +# define NUM_BUTTONS 8 +#endif + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_KEY_BIT (1 << BUTTON_KEY) + +#ifndef CONFIG_INPUT_DJOYSTICK +# define JOYSTICK_SEL_BIT (1 << JOYSTICK_SEL) +# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) +# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) +# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) +# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3210e_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3210e_lcdclear(uint16_t color); +#endif + +/**************************************************************************** + * Name: stm32_lm75initialize + * + * Description: + * Initialize and register the LM-75 Temperature Sensor driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/temp0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) +int stm32_lm75initialize(const char *devpath); +#endif + +/**************************************************************************** + * Name: stm32_lm75attach + * + * Description: + * Attach the LM-75 interrupt handler + * + * Input Parameters: + * irqhandler - the LM-75 interrupt handler + * arg - The argument that will accompany the interrupt + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_LM75_I2C) && defined(CONFIG_STM32_I2C1) +int stm32_lm75attach(xcpt_t irqhandler, void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* SDIO */ + +#define GPIO_SDIO_CK GPIO_ADJUST_MODE(GPIO_SDIO_CK_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_CMD GPIO_ADJUST_MODE(GPIO_SDIO_CMD_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D0 GPIO_ADJUST_MODE(GPIO_SDIO_D0_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D1 GPIO_ADJUST_MODE(GPIO_SDIO_D1_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D2 GPIO_ADJUST_MODE(GPIO_SDIO_D2_0, GPIO_MODE_50MHz) +#define GPIO_SDIO_D3 GPIO_ADJUST_MODE(GPIO_SDIO_D3_0, GPIO_MODE_50MHz) + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* FSMC NPS pins (used by board srcs) */ + +#define GPIO_NPS_A0 GPIO_ADJUST_MODE(GPIO_NPS_A0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A1 GPIO_ADJUST_MODE(GPIO_NPS_A1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A10 GPIO_ADJUST_MODE(GPIO_NPS_A10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A11 GPIO_ADJUST_MODE(GPIO_NPS_A11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A12 GPIO_ADJUST_MODE(GPIO_NPS_A12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A13 GPIO_ADJUST_MODE(GPIO_NPS_A13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A14 GPIO_ADJUST_MODE(GPIO_NPS_A14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A15 GPIO_ADJUST_MODE(GPIO_NPS_A15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A16 GPIO_ADJUST_MODE(GPIO_NPS_A16_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A17 GPIO_ADJUST_MODE(GPIO_NPS_A17_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A18 GPIO_ADJUST_MODE(GPIO_NPS_A18_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A19 GPIO_ADJUST_MODE(GPIO_NPS_A19_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A2 GPIO_ADJUST_MODE(GPIO_NPS_A2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A20 GPIO_ADJUST_MODE(GPIO_NPS_A20_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A21 GPIO_ADJUST_MODE(GPIO_NPS_A21_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A22 GPIO_ADJUST_MODE(GPIO_NPS_A22_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A3 GPIO_ADJUST_MODE(GPIO_NPS_A3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A4 GPIO_ADJUST_MODE(GPIO_NPS_A4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A5 GPIO_ADJUST_MODE(GPIO_NPS_A5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A6 GPIO_ADJUST_MODE(GPIO_NPS_A6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A7 GPIO_ADJUST_MODE(GPIO_NPS_A7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A8 GPIO_ADJUST_MODE(GPIO_NPS_A8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_A9 GPIO_ADJUST_MODE(GPIO_NPS_A9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D0 GPIO_ADJUST_MODE(GPIO_NPS_D0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D1 GPIO_ADJUST_MODE(GPIO_NPS_D1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D10 GPIO_ADJUST_MODE(GPIO_NPS_D10_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D11 GPIO_ADJUST_MODE(GPIO_NPS_D11_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D12 GPIO_ADJUST_MODE(GPIO_NPS_D12_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D13 GPIO_ADJUST_MODE(GPIO_NPS_D13_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D14 GPIO_ADJUST_MODE(GPIO_NPS_D14_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D15 GPIO_ADJUST_MODE(GPIO_NPS_D15_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D2 GPIO_ADJUST_MODE(GPIO_NPS_D2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D3 GPIO_ADJUST_MODE(GPIO_NPS_D3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D4 GPIO_ADJUST_MODE(GPIO_NPS_D4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D5 GPIO_ADJUST_MODE(GPIO_NPS_D5_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D6 GPIO_ADJUST_MODE(GPIO_NPS_D6_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D7 GPIO_ADJUST_MODE(GPIO_NPS_D7_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D8 GPIO_ADJUST_MODE(GPIO_NPS_D8_0, GPIO_MODE_50MHz) +#define GPIO_NPS_D9 GPIO_ADJUST_MODE(GPIO_NPS_D9_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NBL0 GPIO_ADJUST_MODE(GPIO_NPS_NBL0_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NBL1 GPIO_ADJUST_MODE(GPIO_NPS_NBL1_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE2 GPIO_ADJUST_MODE(GPIO_NPS_NE2_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE3 GPIO_ADJUST_MODE(GPIO_NPS_NE3_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NE4 GPIO_ADJUST_MODE(GPIO_NPS_NE4_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NOE GPIO_ADJUST_MODE(GPIO_NPS_NOE_0, GPIO_MODE_50MHz) +#define GPIO_NPS_NWE GPIO_ADJUST_MODE(GPIO_NPS_NWE_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM3210E_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs new file mode 100644 index 0000000000000..42002bd0d2967 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script new file mode 100644 index 0000000000000..0f14faebace94 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu new file mode 100644 index 0000000000000..1a8c3f20a865e --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * STM3210E-EVAL's DFU bootloader is being used. In that case, the correct + * load .text load address is 0x08003000 (leaving 464Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 464K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103Z has 64Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..34dd5c8b2858b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt @@ -0,0 +1,70 @@ +# ############################################################################## +# boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_extcontext.c stm32_extmem.c + stm32_selectnor.c) + list(APPEND SRCS stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c) + list(APPEND SRCS stm32_selectlcd.c stm32_deselectlcd.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) + + if(CONFIG_PM_BUTTONS) + list(APPEND SRCS stm32_pmbuttons.c) + endif() +endif() + +if(CONFIG_INPUT_DJOYSTICK) + list(APPEND SRCS stm32_djoystick.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm3210e-eval/src/Make.defs b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs new file mode 100644 index 0000000000000..06d9de85d5af2 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs @@ -0,0 +1,71 @@ +############################################################################ +# boards/arm/stm32f1/stm3210e-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_extcontext.c stm32_extmem.c stm32_selectnor.c +CSRCS += stm32_deselectnor.c stm32_selectsram.c stm32_deselectsram.c +CSRCS += stm32_selectlcd.c stm32_deselectlcd.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c + +ifeq ($(CONFIG_PM_BUTTONS),y) +CSRCS += stm32_pmbuttons.c +endif +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) +CSRCS += stm32_djoystick.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h rename to boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h index 0f56d7a932858..f97c09d7bf257 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h + * boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..dca12d9b1b80f --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel: Variable Resistor */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 14 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN14 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..cb9730521db75 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* If the FSMC and external RAM are selected, then enable SRAM access */ + +#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) + stm32_selectsram(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c new file mode 100644 index 0000000000000..45beb076a2658 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c @@ -0,0 +1,317 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# define NSH_HAVEUSBDEV 1 +# define NSH_HAVEMMCSD 1 +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#else + +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +# undef NSH_HAVEUSBDEV +# undef NSH_HAVEMMCSD +#endif + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef NSH_HAVEMMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 1\n"); + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 1\n"); + + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + return -ENODEV; + } + + syslog(LOG_INFO, + "Successfully bound SPI port 0 to the SPI FLASH driver\n"); +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + + /* Create the SPI FLASH MTD instance */ + + /* The M25Pxx is not a give media to implement a file system.. + * its block sizes are too large + */ + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef NSH_HAVEMMCSD + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO + * to detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the simulated framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + /* Initialize and register the joystick driver */ + + ret = stm32_djoy_initialization(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully registered the joystick driver\n"); +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..9833133076a16 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_KEY, + + /* The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should + * be used by the discrete joystick driver. + */ + +#ifndef CONFIG_INPUT_DJOYSTICK + GPIO_JOY_SEL, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_UP +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c new file mode 100644 index 0000000000000..4bd62db364e7a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F103ZE supports only CAN1 */ + +#define CAN_PORT 1 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#ifdef CONFIG_STM32_CAN1 + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c new file mode 100644 index 0000000000000..7eaeac511209a --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c @@ -0,0 +1,450 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No SDIO? Then no USB MSC device in composite */ + +#ifndef CONFIG_STM32_SDIO +# undef CONFIG_USBMSC_COMPOSITE +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application- specific wrapper about usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + DEBUGASSERT(g_mschandle != NULL); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[0]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[0].classobject = cdcacm_classobject; + dev[0].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[0].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[0].devinfo.ninterfaces; + strbase += dev[0].devinfo.nstrings; + + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[1]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[1].classobject = board_mscclassobject; + dev[1].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[1].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 5; + dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 4; + + /* Count up the base numbers */ + + ifnobase += dev[1].devinfo.ninterfaces; + strbase += dev[1].devinfo.nstrings; + + return composite_initialize(composite_getdevdescs(), dev, 2); +} +#endif + +/**************************************************************************** + * Name: board_composite1_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 1. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite1_connect(int port) +{ + /* REVISIT: This configuration currently fails. stm32_epallocpma() fails + * allocate a buffer for the 6th endpoint. Currently it supports 7x64 byte + * buffers, two required for EP0, leaving only buffers for 5 additional + * endpoints. + */ + +#if 0 + struct composite_devdesc_s dev[2]; + int strbase = COMPOSITE_NSTRIDS; + int ifnobase = 0; + int epno; + int i; + + for (i = 0, epno = 1; i < 2; i++) + { + /* Ask the cdcacm driver to fill in the constants we didn't know here */ + + cdcacm_get_composite_devdesc(&dev[i]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[i].classobject = cdcacm_classobject; + dev[i].uninitialize = cdcacm_uninitialize; + + dev[i].minor = i; /* The minor interface number */ + + /* Interfaces */ + + dev[i].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + + /* Strings */ + + dev[i].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[i].devinfo.epno[CDCACM_EP_INTIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epno++; + dev[i].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epno++; + + ifnobase += dev[i].devinfo.ninterfaces; + strbase += dev[i].devinfo.nstrings; + } + + return composite_initialize(composite_getdevdescs(), dev, 2); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + /* If system/composite is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + * + * NOTE: CONFIG_NSH_BUILTIN_APPS is not a fool-proof indication that NSH + * was built. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=0\n"); + + ret = mmcsd_slotinitialize(0, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3210E-EVAL board supports a GPIO to detect if + * there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { +#ifdef CONFIG_USBMSC_COMPOSITE + return board_composite0_connect(port); +#else + return NULL; +#endif + } + else if (configid == 1) + { + return board_composite1_connect(port); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..e36b381ba7c79 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c index 64260e9803876..1798b2b4c943f 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..2a23173f2a441 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable NOR FLASH + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0x000030d2, STM32_FSMC_BCR3); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR3); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c new file mode 100644 index 0000000000000..4b3b7868e3316 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t +djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_SEL +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t +djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialization + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialization(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c index c6b2b4afc386e..64f822a232fe8 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..3b2779e4ffb27 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* It would be much more efficient to brute force these all into the + * the appropriate registers. Just a little tricky. + */ + +/* GPIO configurations common to SRAM and NOR Flash */ + +const uint16_t g_commonconfig[NCOMMON_CONFIG] = +{ + /* A0... A18 */ + + GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3, + GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7, + GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11, + GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15, + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, + GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, + GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, + GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, + + /* NOE, NWE */ + + GPIO_NPS_NOE, GPIO_NPS_NWE +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c new file mode 100644 index 0000000000000..1c4cb71b0df62 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c @@ -0,0 +1,437 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to STM32 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (STM32 standby mode). + */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/* Values for the RTC Alarm to reset from the PM_SLEEP mode (STM32 + * standby mode). If CONFIG_PM_SLEEP_WAKEUP is defined in the + * configuration, then the logic in this file will program the RTC + * alarm to wakeup the processor after an a delay. + * + * This feature might be useful, for example, in a system that needs to + * use minimal power but awake up to perform some task at periodic + * intervals. + */ + +#ifdef CONFIG_PM_SLEEP_WAKEUP + +# ifndef CONFIG_RTC_ALARM +# error "CONFIG_RTC_ALARM should be enabled to use CONFIG_PM_SLEEP_WAKEUP" +# endif + +/* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC + * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 + * awakens from PM_SLEEP mode. + */ + +# ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 10 +# endif + +# ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static volatile bool g_alarmwakeup; /* Wakeup Alarm indicator */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_alarmcb + * + * Description: + * RTC alarm callback + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void) +{ + /* Note that we were awaken by an alarm */ + + g_alarmwakeup = true; +} +#endif + +/**************************************************************************** + * Name: stm32_alarm_exti + * + * Description: + * RTC alarm EXTI interrupt service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static int stm32_alarm_exti(int irq, void *context, void *arg) +{ + stm32_alarmcb(); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_exti_cancel + * + * Description: + * Disable the ALARM EXTI interrupt + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_exti_cancel(void) +{ + stm32_exti_alarm(false, false, false, NULL, NULL); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_alarm + * + * Description: + * Set the alarm + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static int stm32_rtc_alarm(time_t tv_sec, time_t tv_nsec, bool exti) +{ + struct timespec alarmtime; + int ret; + + /* Configure to receive RTC Alarm EXTI interrupt */ + + if (exti) + { + /* TODO: Make sure that that is no pending EXTI interrupt */ + + stm32_exti_alarm(true, true, true, stm32_alarm_exti, NULL); + } + + /* Configure the RTC alarm to Auto Wake the system */ + + up_rtc_gettime(&alarmtime); + + alarmtime.tv_sec += tv_sec; + alarmtime.tv_nsec += tv_nsec; + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + + if (alarmtime.tv_nsec >= NSEC_PER_SEC) + { + /* Carry to the seconds */ + + alarmtime.tv_sec++; + alarmtime.tv_nsec -= NSEC_PER_SEC; + } + + /* Set the alarm */ + + g_alarmwakeup = false; + ret = stm32_rtc_setalarm(&alarmtime, stm32_alarmcb); + if (ret < 0) + { + serr("ERROR: Warning: The alarm is already set\n"); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + int ret; + + /* The following is logic that is done after the wake-up from PM_STANDBY + * state. It decides whether to go back to the PM_NORMAL or to the deeper + * power-saving mode PM_SLEEP: If the alarm expired with no "normal" + * wake-up event, then PM_SLEEP is entered. + * + * Logically, this code belongs at the end of the PM_STANDBY case below, + * does not work in the position for some unknown reason. + */ + + if (oldstate == PM_STANDBY) + { + /* Were we awakened by the alarm? */ + +#ifdef CONFIG_RTC_ALARM + if (g_alarmwakeup) + { + /* Yes.. Go to SLEEP mode */ + + newstate = PM_SLEEP; + } + else +#endif + { + /* Resume normal operation */ + + newstate = PM_NORMAL; + } + } + else + { + /* Let the PM system decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + } + + /* Check for state changes */ + + if (newstate != oldstate) + { + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + sched_lock(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + /* If we just awakened from PM_STANDBY mode, then reconfigure + * clocking. + */ + + if (oldstate == PM_STANDBY) + { + /* Re-enable clocking */ + + stm32_clockenable(); + + /* The system timer was disabled while in PM_STANDBY or + * PM_SLEEP modes. But the RTC has still be running: Reset + * the system time the current RTC time. + */ + +#ifdef CONFIG_RTC + clock_synchronize(NULL); +#endif + } + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { + /* Set the alarm as an EXTI Line */ + +#ifdef CONFIG_RTC_ALARM + stm32_rtc_alarm(CONFIG_PM_ALARM_SEC, CONFIG_PM_ALARM_NSEC, true); +#endif + /* Wait 10ms */ + + up_mdelay(10); + + /* Enter the STM32 stop mode */ + + stm32_pmstop(false); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM + stm32_exti_cancel(); + ret = stm32_rtc_cancelalarm(); + if (ret < 0) + { + swarn("WARNING: Cancel alarm failed\n"); + } +#endif + + /* Note: See the additional PM_STANDBY related logic at the + * beginning of this function. That logic is executed after + * this point. + */ + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + /* Configure the RTC alarm to Auto Reset the system */ + +#ifdef CONFIG_PM_SLEEP_WAKEUP + stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, + CONFIG_PM_SLEEP_WAKEUP_NSEC, false); +#endif + /* Wait 10ms */ + + up_mdelay(10); + + /* Enter the STM32 standby mode */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + sched_unlock(); + } +} +#else +# define stm32_idlepm() +#endif /* CONFIG_PM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..f0b29a830d7b0 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c @@ -0,0 +1,1841 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs: + * + * 1. Ampire AM-240320LTNQW00H + * 2. Orise Tech SPFD5408B + * 3. RenesasSP R61580 + * + * The driver dynamically selects the LCD based on the reported LCD ID value. + * However, code size can be reduced by suppressing support for individual + * LCDs using: + * + * CONFIG_STM3210E_AM240320_DISABLE + * CONFIG_STM3210E_SPFD5408B_DISABLE + * CONFIG_STM3210E_R61580_DISABLE + * + * Omitting the above (or setting them to "n") enables support for the LCD. + * Setting any of the above to "y" will disable support for the + * corresponding LCD. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Backlight */ + +#ifndef CONFIG_STM3210E_LCD_BACKLIGHT +# undef CONFIG_STM3210E_LCD_PWM +#endif + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# if !defined(CONFIG_STM32_TIM1) +# warning "CONFIG_STM3210E_LCD_PWM requires CONFIG_STM32_TIM1" +# undef CONFIG_STM3210E_LCD_PWM +# endif +# if defined(CONFIG_STM32_TIM1_FULL_REMAP) +# warning "PA8 cannot be configured as TIM1 CH1 with full remap" +# undef CONFIG_STM3210E_LCD_PWM +# endif +#endif + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# if CONFIG_LCD_MAXPOWER < 2 +# warning "A larger value of CONFIG_LCD_MAXPOWER is recommended" +# endif +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# undef CONFIG_LCD_MAXPOWER +# if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) +# define CONFIG_LCD_MAXPOWER 100 +# else +# define CONFIG_LCD_MAXPOWER 1 +# endif +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* PWM Frequency */ + +#ifndef CONFIG_STM3210E_LCD_PWMFREQUENCY +# define CONFIG_STM3210E_LCD_PWMFREQUENCY 100 +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_PORTRAIT) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif !defined(CONFIG_LCD_LANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* When reading 16-bit gram data, there may some shifts in the returned data + * and/or there may be some colors in the incorrect posisions: + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * Red and green appear to be swapped on read-back as well + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * - AM240320: Unknown -- assume colors are correct for now. + */ + +#define SPFD5408B_RDSHIFT 5 + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#ifdef CONFIG_LCD_LANDSCAPE +# define STM3210E_XRES 320 +# define STM3210E_YRES 240 +#else +# define STM3210E_XRES 240 +# define STM3210E_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3210E_BPP 16 +#define STM3210E_COLORFMT FB_FMT_RGB16_565 + +/* STM3210E-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 4 of NOR/SRAM Bank 1~4 */ + +#define STM3210E_LCDBASE ((uint32_t)(0x60000000 | 0x0c000000)) +#define LCD ((struct lcd_regs_s *) STM3210E_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define SPFD5408B_ID 0x5408 +#define R61580_ID 0x1580 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_SPFD5408B, + LCD_TYPE_R61580, + LCD_TYPE_AM240320 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3210e_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) + uint32_t reload; +#endif + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3210e_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3210e_readreg(uint8_t regaddr); +static inline void stm3210e_gramselect(void); +static inline void stm3210e_writegram(uint16_t rgbval); +static void stm3210e_readsetup(uint16_t *accum); +#ifndef CONFIG_STM3210E_AM240320_DISABLE +static void stm3210e_readnosetup(uint16_t *accum); +#endif +static uint16_t stm3210e_readshift(uint16_t *accum); +static uint16_t stm3210e_readnoshift(uint16_t *accum); +static void stm3210e_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3210e_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, + size_t npixels); +static int stm3210e_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, + size_t npixels); + +/* LCD Configuration */ + +static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3210e_getpower(struct lcd_dev_s *dev); +static int stm3210e_setpower(struct lcd_dev_s *dev, int power); +static int stm3210e_getcontrast(struct lcd_dev_s *dev); +static int stm3210e_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* LCD Power Management */ + +#ifdef CONFIG_PM +static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/* Initialization */ + +static inline void stm3210e_lcdinitialize(void); +#ifdef CONFIG_STM3210E_LCD_BACKLIGHT +static void stm3210e_backlight(void); +#else +# define stm3210e_backlight() +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3210E_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3210E_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3210E_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3210E_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3210e_putrun, /* Put a run into LCD memory */ + .getrun = stm3210e_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3210E_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3210e_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3210e_getvideoinfo, + .getplaneinfo = stm3210e_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3210e_getpower, + .setpower = stm3210e_setpower, + .getcontrast = stm3210e_getcontrast, + .setcontrast = stm3210e_setcontrast, + }, +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_lcdcb = +{ + .notify = stm3210e_pm_notify, + .prepare = stm3210e_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3210e_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3210e_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3210e_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3210e_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3210e_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3210e_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3210e_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3210e_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3210e_readsetup / stm3210e_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * - AM240320: Unknown -- assuming no shift in the return data + * + ****************************************************************************/ + +/* Used for SPFD5408B and R61580 */ + +#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) +static void stm3210e_readsetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} +#endif + +/* Used only for AM240320 */ + +#ifndef CONFIG_STM3210E_AM240320_DISABLE +static void stm3210e_readnosetup(uint16_t *accum) +{ +} +#endif + +/**************************************************************************** + * Name: stm3210e_readshift / stm3210e_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. Possibly + * shifting the data and possibly swapping red and green components. + * + * - SPFD5408B: There appears to be a 5-bit shift in the returned data. + * Red and green appear to be swapped on read-back as well + * - R61580: There is a 16-bit (1 pixel) shift in the returned data. + * All colors in the normal order + * - AM240320: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +/* This version is used only for the SPFD5408B. It shifts the data by + * 5-bits and swaps red and green + */ + +#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE +static uint16_t stm3210e_readshift(uint16_t *accum) +{ + uint16_t red; + uint16_t green; + uint16_t blue; + + /* Read the value (GRAM register already selected) */ + + uint16_t next = LCD->value; + + /* Return previous bits 0-10 as bits 6-15 and next data bits 11-15 as + * bits 0-5 + * + * xxxx xPPP PPPP PPPP + * NNNN Nxxx xxxx xxxx + * + * Assuming that SPFD5408B_RDSHIFT == 5 + */ + + uint16_t value = *accum << SPFD5408B_RDSHIFT | + next >> (16 - SPFD5408B_RDSHIFT); + + /* Save the value for the next time we are called */ + + *accum = next; + + /* Tear the RGB655 apart. Swap read and green */ + + red = (value << (11 - 5)) & 0xf800; /* Move bits 5-9 to 11-15 */ + green = (value >> (10 - 5)) & 0x07e0; /* Move bits 10-15 to bits 5-10 */ + blue = value & 0x001f; /* Blue is in the right place */ + + /* And put the RGB565 back together */ + + value = red | green | blue; + + /* This is weird... If blue is zero, then red+green values are off by 0x20. + * Except that both 0x0000 and 0x0020 can map to 0x0000. Need to revisit + * this!!!!!!!!!!! I might be misinterpreting some of the data that I + * have. + */ + +#if 0 /* REVISIT */ + if (value != 0 && blue == 0) + { + value += 0x20; + } +#endif + + return value; +} +#endif + +/* This version is used for the R61580 and for the AM240320. It neither + * shifts nor swaps colors. + */ + +#if !defined(CONFIG_STM3210E_R61580_DISABLE) || !defined(CONFIG_STM3210E_AM240320_DISABLE) +static uint16_t stm3210e_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} +#endif + +/**************************************************************************** + * Name: stm3210e_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3210e_setcursor(uint16_t col, uint16_t row) +{ + stm3210e_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3210e_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3210e_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The lcd device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3210e_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, + size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Which edge of the display is the "top?" Here the + * edge with the simplest conversion is used. + */ + + col = (STM3210E_XRES - 1) - col; + + /* Set the cursor position */ + + stm3210e_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3210e_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position (auto-decrements to the next + * column) + */ + + stm3210e_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. (Swap row and column. This is done implicitly). */ + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + stm3210e_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. (Swap row and column. This is done implicitly). + * Which edge of the display is the "top"? + */ + + col = (STM3210E_XRES - 1) - col; + row = (STM3210E_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + stm3210e_writegram(*src++); + + /* Decrement to next column */ + + col--; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The lcd device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3210e_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, + size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type */ + + switch (g_lcddev.type) + { +#ifndef CONFIG_STM3210E_SPFD5408B_DISABLE + case LCD_TYPE_SPFD5408B: + readsetup = stm3210e_readsetup; + readgram = stm3210e_readshift; + break; +#endif + +#ifndef CONFIG_STM3210E_R61580_DISABLE + case LCD_TYPE_R61580: + readsetup = stm3210e_readsetup; + readgram = stm3210e_readnoshift; + break; +#endif + +#ifndef CONFIG_STM3210E_AM240320_DISABLE + case LCD_TYPE_AM240320: + readsetup = stm3210e_readnosetup; + readgram = stm3210e_readnoshift; + break; +#endif + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Which edge of the display is the "top?" Here the + * edge with the simplest conversion is used. + */ + + col = (STM3210E_XRES - 1) - col; + + /* Set the cursor position */ + + stm3210e_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3210e_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position (autoincrements to the next + * row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates (Swap row and column. This is done implicitly). */ + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. (Swap row and column. This is done implicitly). + * Which edge of the display is the "top"? + */ + + col = (STM3210E_XRES - 1) - col; + row = (STM3210E_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3210e_setcursor(row, col); + stm3210e_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col--; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3210e_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3210e_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + ginfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getpower + * + * Description: + * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_getpower(struct lcd_dev_s *dev) +{ + ginfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3210e_poweroff + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_poweroff(void) +{ + /* Turn the display off */ + + stm3210e_writereg(LCD_REG_7, 0); + + /* Disable timer 1 clocking */ + +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) +# if defined(CONFIG_STM3210E_LCD_PWM) + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); +# endif + + /* Configure the PA8 pin as an output */ + + stm32_configgpio(GPIO_LCD_BACKLIGHT); + + /* Turn the backlight off */ + + stm32_gpiowrite(GPIO_LCD_BACKLIGHT, false); +#endif + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3210e_setpower + * + * Description: + * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: + * full on). On backlit LCDs, this setting may correspond to the backlight + * setting. + * + ****************************************************************************/ + +static int stm3210e_setpower(struct lcd_dev_s *dev, int power) +{ + ginfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { +#if defined(CONFIG_STM3210E_LCD_BACKLIGHT) && defined(CONFIG_STM3210E_LCD_PWM) + uint32_t frac; + uint32_t duty; + + /* If we are coming up from the power off state, then re-configure + * the timer + */ + + if (g_lcddev.power == 0) + { + stm3210e_backlight(); + } + + /* Make sure that the power value is within range */ + + if (power > CONFIG_LCD_MAXPOWER) + { + power = CONFIG_LCD_MAXPOWER; + } + + /* Calculate the new backlight duty. It is a faction of the timer1 + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + frac = (power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#else + /* Turn the backlight on */ + + stm32_gpiowrite(GPIO_LCD_BACKLIGHT, true); +#endif + /* Then turn the display on */ + +#ifndef CONFIG_STM3210E_AM240320_DISABLE +# if !defined (CONFIG_STM3210E_SPFD5408B_DISABLE) || !defined(CONFIG_STM3210E_R61580_DISABLE) + stm3210e_writereg(LCD_REG_7, + g_lcddev.type == LCD_TYPE_AM240320 ? + 0x0173 : 0x0112); +# else + stm3210e_writereg(LCD_REG_7, 0x0173); +# endif +#else + stm3210e_writereg(LCD_REG_7, 0x0112); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3210e_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3210e_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3210e_getcontrast(struct lcd_dev_s *dev) +{ + ginfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3210e_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3210e_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + ginfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3210e_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm3210e_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ +#ifdef CONFIG_STM3210E_LCD_PWM + uint32_t frac; + uint32_t duty; +#endif + + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LCD operation */ + +#ifdef CONFIG_STM3210E_LCD_PWM + frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Reduce LCD light */ + +#ifdef CONFIG_STM3210E_LCD_PWM + frac = (g_lcddev.power << 16) / CONFIG_LCD_MAXPOWER; + duty = (g_lcddev.reload * frac) >> 16; + if (duty > 0) + { + duty--; + } + + /* Reduce the LCD backlight to 50% of the MAXPOWER */ + + duty >>= 1; + putreg16((uint16_t)duty, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Turn display backlight off */ + +#ifdef CONFIG_STM3210E_LCD_PWM + putreg16(0, STM32_TIM1_CCR1); +#endif + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Turn off LCD */ + + if (g_lcddev.type == LCD_TYPE_AM240320) + { + /* Display off sequence */ + + stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ + up_mdelay(10); /* Wait for 2 frame scan */ + stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ + + /* Power off sequence */ + + stm3210e_writereg(LCD_REG_30, 0x09); /* VCOM stop */ + stm3210e_writereg(LCD_REG_27, 0x0e); /* VS/VDH turn off */ + stm3210e_writereg(LCD_REG_24, 0xc0); /* CP1, CP2, CP3 turn off */ + up_mdelay(10); /* wait 10 ms */ + + stm3210e_writereg(LCD_REG_24, 0x00); /* VR1 / VR2 off */ + stm3210e_writereg(LCD_REG_28, 0x30); /* Step up circuit operating current stop */ + up_mdelay(10); + + stm3210e_poweroff(); + stm3210e_writereg(LCD_REG_0, 0xa0); /* White display mode setting */ + up_mdelay(10); /* Wait for 2 frame scan */ + + stm3210e_writereg(LCD_REG_59, 0x00); /* Gate scan stop */ + } + else + { + stm3210e_poweroff(); + } + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: stm3210e_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm3210e_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LCD driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm3210e_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3210e_lcdinitialize(void) +{ + uint16_t id; + + /* Check if the LCD is Orise Tech SPFD5408B Controller (or the compatible + * RenesasSP R61580). + */ + + id = stm3210e_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the SPFD5408B */ + +#if !defined(CONFIG_STM3210E_SPFD5408B_DISABLE) + if (id == SPFD5408B_ID) + { + /* Set the LCD type for the SPFD5408B */ + + g_lcddev.type = LCD_TYPE_SPFD5408B; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ + stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ + stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ + + /* Power On sequence */ + + stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3210e_writereg(LCD_REG_17, 0x0007); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_16, 0x12b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_18, 0x01bd); /* External reference voltage= Vci */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_19, 0x1400); /* VDV[4:0] for VCOM amplitude */ + stm3210e_writereg(LCD_REG_41, 0x000e); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3210e_writereg(LCD_REG_33, 0x013f); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (SPFD5408B) */ + + stm3210e_writereg(LCD_REG_48, 0x0b0d); + stm3210e_writereg(LCD_REG_49, 0x1923); + stm3210e_writereg(LCD_REG_50, 0x1c26); + stm3210e_writereg(LCD_REG_51, 0x261c); + stm3210e_writereg(LCD_REG_52, 0x2419); + stm3210e_writereg(LCD_REG_53, 0x0d0b); + stm3210e_writereg(LCD_REG_54, 0x1006); + stm3210e_writereg(LCD_REG_55, 0x0610); + stm3210e_writereg(LCD_REG_56, 0x0706); + stm3210e_writereg(LCD_REG_57, 0x0304); + stm3210e_writereg(LCD_REG_58, 0x0e05); + stm3210e_writereg(LCD_REG_59, 0x0e01); + stm3210e_writereg(LCD_REG_60, 0x010e); + stm3210e_writereg(LCD_REG_61, 0x050e); + stm3210e_writereg(LCD_REG_62, 0x0403); + stm3210e_writereg(LCD_REG_63, 0x0607); + + /* Set GRAM area */ + + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ + + /* Partial Display Control */ + + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x0000); + stm3210e_writereg(LCD_REG_131, 0x0000); + stm3210e_writereg(LCD_REG_132, 0x0000); + stm3210e_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3210e_writereg(LCD_REG_144, 0x0010); + stm3210e_writereg(LCD_REG_146, 0x0000); + stm3210e_writereg(LCD_REG_147, 0x0003); + stm3210e_writereg(LCD_REG_149, 0x0110); + stm3210e_writereg(LCD_REG_151, 0x0000); + stm3210e_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR=1 + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3210e_writereg(LCD_REG_3, 0x1018); + stm3210e_writereg(LCD_REG_7, 0); /* Display OFF */ + } + else +#endif + + /* Check if the ID is for the almost compatible R61580 */ + +#if !defined(CONFIG_STM3210E_R61580_DISABLE) + if (id == R61580_ID) + { + /* Set the LCD type for the R61580 */ + + g_lcddev.type = LCD_TYPE_R61580; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + up_mdelay(100); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_0, 0x0000); + stm3210e_writereg(LCD_REG_164, 0x0001); + up_mdelay(100); + stm3210e_writereg(LCD_REG_96, 0xa700); + stm3210e_writereg(LCD_REG_8, 0x0808); + + /* Gamma Setting */ + + stm3210e_writereg(LCD_REG_48, 0x0203); + stm3210e_writereg(LCD_REG_49, 0x080f); + stm3210e_writereg(LCD_REG_50, 0x0401); + stm3210e_writereg(LCD_REG_51, 0x050b); + stm3210e_writereg(LCD_REG_52, 0x3330); + stm3210e_writereg(LCD_REG_53, 0x0b05); + stm3210e_writereg(LCD_REG_54, 0x0005); + stm3210e_writereg(LCD_REG_55, 0x0f08); + stm3210e_writereg(LCD_REG_56, 0x0302); + stm3210e_writereg(LCD_REG_57, 0x3033); + + /* Power Setting */ + + stm3210e_writereg(LCD_REG_144, 0x0018); /* 80Hz */ + stm3210e_writereg(LCD_REG_16, 0x0530); /* BT, AP */ + stm3210e_writereg(LCD_REG_17, 0x0237); /* DC1,DC0,VC */ + stm3210e_writereg(LCD_REG_18, 0x01bf); + stm3210e_writereg(LCD_REG_19, 0x1000); /* VCOM */ + up_mdelay(200); + + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS bit */ + stm3210e_writereg(LCD_REG_2, 0x0200); + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_9, 0x0001); + stm3210e_writereg(LCD_REG_10, 0x0008); + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB 18-bit System interface setting */ + stm3210e_writereg(LCD_REG_13, 0xd000); + stm3210e_writereg(LCD_REG_14, 0x0030); + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity, no impact */ + stm3210e_writereg(LCD_REG_32, 0x0000); /* H Start */ + stm3210e_writereg(LCD_REG_33, 0x0000); /* V Start */ + stm3210e_writereg(LCD_REG_41, 0x002e); + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL, VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* set scrolling line */ + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x005f); + stm3210e_writereg(LCD_REG_147, 0x0701); + + stm3210e_writereg(LCD_REG_7, 0x0000); /* Display OFF */ + } + else +#endif + { +#ifndef CONFIG_STM3210E_AM240320_DISABLE + /* Set the LCD type for the AM240320 */ + + g_lcddev.type = LCD_TYPE_AM240320; + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3210e_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + stm3210e_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3210e_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3210e_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3210e_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + stm3210e_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3210e_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3210e_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3210e_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3210e_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3210e_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3210e_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3210e_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3210e_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3210e_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3210e_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3210e_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3210e_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3210e_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3210e_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve */ + + stm3210e_writereg(LCD_REG_48, 0x0006); + stm3210e_writereg(LCD_REG_49, 0x0101); + stm3210e_writereg(LCD_REG_50, 0x0003); + stm3210e_writereg(LCD_REG_53, 0x0106); + stm3210e_writereg(LCD_REG_54, 0x0b02); + stm3210e_writereg(LCD_REG_55, 0x0302); + stm3210e_writereg(LCD_REG_56, 0x0707); + stm3210e_writereg(LCD_REG_57, 0x0007); + stm3210e_writereg(LCD_REG_60, 0x0600); + stm3210e_writereg(LCD_REG_61, 0x020b); + + /* Set GRAM area */ + + stm3210e_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3210e_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3210e_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3210e_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3210e_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + stm3210e_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3210e_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3210e_writereg(LCD_REG_128, 0x0000); + stm3210e_writereg(LCD_REG_129, 0x0000); + stm3210e_writereg(LCD_REG_130, 0x0000); + stm3210e_writereg(LCD_REG_131, 0x0000); + stm3210e_writereg(LCD_REG_132, 0x0000); + stm3210e_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3210e_writereg(LCD_REG_144, 0x0010); + stm3210e_writereg(LCD_REG_146, 0x0000); + stm3210e_writereg(LCD_REG_147, 0x0003); + stm3210e_writereg(LCD_REG_149, 0x0110); + stm3210e_writereg(LCD_REG_151, 0x0000); + stm3210e_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3210e_writereg(LCD_REG_3, 0x1018); + stm3210e_writereg(LCD_REG_7, 0); /* Display off */ +#else + lcderr("ERROR: Unsupported LCD type\n"); +#endif + } +} + +/**************************************************************************** + * Name: stm3210e_backlight + * + * Description: + * The LCD backlight is driven from PA8 which must be configured as TIM1 + * CH1. TIM1 must then be configured to output a clock on PA8; the duty + * of the clock determineds the backlight level. + * + ****************************************************************************/ + +#ifdef CONFIG_STM3210E_LCD_BACKLIGHT +static void stm3210e_backlight(void) +{ +#ifdef CONFIG_STM3210E_LCD_PWM + uint32_t prescaler; + uint32_t reload; + uint32_t timclk; + uint16_t bdtr; + uint16_t ccmr; + uint16_t ccer; + uint16_t cr2; + + /* Calculate the TIM1 prescaler value */ + + prescaler = (STM32_PCLK2_FREQUENCY / CONFIG_STM3210E_LCD_PWMFREQUENCY + + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + else if (prescaler > 65536) + { + prescaler = 65536; + } + + /* Calculate the TIM1 reload value */ + + timclk = STM32_PCLK2_FREQUENCY / prescaler; + reload = timclk / CONFIG_STM3210E_LCD_PWMFREQUENCY; + + if (reload < 1) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + + g_lcddev.reload = reload; + + /* Configure PA8 as TIM1 CH1 output */ + + stm32_configgpio(GPIO_TIM1_CH1OUT); + + /* Enabled timer 1 clocking */ + + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + + /* Reset timer 1 */ + + modifyreg32(STM32_RCC_APB2RSTR, 0, RCC_APB2RSTR_TIM1RST); + modifyreg32(STM32_RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM1_CR1); + + /* Set the Autoreload value */ + + putreg16(reload - 1, STM32_TIM1_ARR); + + /* Set the Prescaler value */ + + putreg16(prescaler - 1, STM32_TIM1_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM1_EGR); + + /* Reset the Repetition Counter value */ + + putreg16(0, STM32_TIM1_RCR); + + /* Set the main output enable (MOE) bit and clear the OSSI and OSSR + * bits in the BDTR register. + */ + + bdtr = getreg16(STM32_TIM1_BDTR); + bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); + bdtr |= ATIM_BDTR_MOE; + putreg16(bdtr, STM32_TIM1_BDTR); + + /* Disable the Channel 1 */ + + ccer = getreg16(STM32_TIM1_CCER); + ccer &= ~ATIM_CCER_CC1E; + putreg16(ccer, STM32_TIM1_CCER); + + /* Get the TIM1 CR2 register value */ + + cr2 = getreg16(STM32_TIM1_CR2); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM1_CCMR1); + ccmr &= ATIM_CCMR1_OC1M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT); + ccmr |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); + + /* Set the power to the minimum value */ + + g_lcddev.power = 0; + putreg16(0, STM32_TIM1_CCR1); + + /* Select the output polarity level == LOW and enable */ + + ccer |= (ATIM_CCER_CC1E); + + /* Reset the Output N Polarity level */ + + ccer &= ~(ATIM_CCER_CC1NP | ATIM_CCER_CC1NE); + + /* Reset the Output Compare and Output Compare N IDLE State */ + + cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N); + + /* Write the timer configuration */ + + putreg16(cr2, STM32_TIM1_CR2); + putreg16(ccmr, STM32_TIM1_CCMR1); + putreg16(ccer, STM32_TIM1_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM1_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer */ + + ccer |= ATIM_CR1_CEN; + putreg16(ccer, STM32_TIM1_CR1); + + /* Dump timer1 registers */ + + lcdinfo("APB2ENR: %08" PRIx32 "\n", getreg32(STM32_RCC_APB2ENR)); + lcdinfo("CR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR1)); + lcdinfo("CR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CR2)); + lcdinfo("SMCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SMCR)); + lcdinfo("DIER: %04" PRIx32 "\n", getreg32(STM32_TIM1_DIER)); + lcdinfo("SR: %04" PRIx32 "\n", getreg32(STM32_TIM1_SR)); + lcdinfo("BDTR: %04" PRIx32 "\n", getreg32(STM32_TIM1_BDTR)); + lcdinfo("CCMR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR1)); + lcdinfo("CCMR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCMR2)); + lcdinfo("CCER: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCER)); + lcdinfo("CNT: %04" PRIx32 "\n", getreg32(STM32_TIM1_CNT)); + lcdinfo("PSC: %04" PRIx32 "\n", getreg32(STM32_TIM1_PSC)); + lcdinfo("ARR: %04" PRIx32 "\n", getreg32(STM32_TIM1_ARR)); + lcdinfo("RCR: %04" PRIx32 "\n", getreg32(STM32_TIM1_RCR)); + lcdinfo("CCR1: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR1)); + lcdinfo("CCR2: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR2)); + lcdinfo("CCR3: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR3)); + lcdinfo("CCR4: %04" PRIx32 "\n", getreg32(STM32_TIM1_CCR4)); + lcdinfo("DMAR: %04" PRIx32 "\n", getreg32(STM32_TIM1_DMAR)); +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ +#ifdef CONFIG_PM + int ret; +#endif + + ginfo("Initializing\n"); + + /* Register to receive power management callbacks */ + +#ifdef CONFIG_PM + ret = pm_register(&g_lcdcb); + if (ret != OK) + { + lcderr("ERROR: pm_register failed: %d\n", ret); + } +#endif + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3210e_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3210e_lcdclear(0); + + /* Turn the backlight off */ + + stm3210e_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3210e_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3210e_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3210e_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3210e_setcursor(0, STM3210E_XRES - 1); + stm3210e_gramselect(); + for (i = 0; i < STM3210E_XRES * STM3210E_YRES; i++) + { + LCD->value = color; + } +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c new file mode 100644 index 0000000000000..d2b6e2f5f57df --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED State Controls */ + +static inline void led_clrbits(unsigned int clrbits); +static inline void led_setbits(unsigned int setbits); +static void led_setonoff(unsigned int bits); + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_clrbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_setbits + * + * Description: + * Set all LEDs to the bit encoded state + * + ****************************************************************************/ + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Name: led_setonoff + * + * Description: + * Set/clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: stm32_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c new file mode 100644 index 0000000000000..0f4aa4ac80baa --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm3210e-eval.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pmbuttons(); +#endif + + /* Initialize the LED PM */ + + stm32_ledpminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c new file mode 100644 index 0000000000000..bc9823007cdad --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c @@ -0,0 +1,181 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" +#include "stm3210e-eval.h" + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_BUTTONS +# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" +#endif + +#define BUTTON_MIN 0 +#ifdef CONFIG_INPUT_DJOYSTICK +# define BUTTON_MAX 2 +#else +# define BUTTON_MAX 7 +#endif + +#ifndef CONFIG_PM_BUTTONS_MIN +# define CONFIG_PM_BUTTONS_MIN BUTTON_MIN +#endif +#ifndef CONFIG_PM_BUTTONS_MAX +# define CONFIG_PM_BUTTONS_MAX BUTTON_MAX +#endif + +#if CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX +# error "CONFIG_PM_BUTTONS_MIN > CONFIG_PM_BUTTONS_MAX" +#endif + +#if CONFIG_PM_BUTTONS_MAX > BUTTON_MAX +# error "CONFIG_PM_BUTTONS_MAX > BUTTON_MAX" +#endif + +#ifndef CONFIG_ARCH_IRQBUTTONS +# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_PM_IRQBUTTONS_MIN +# define CONFIG_PM_IRQBUTTONS_MIN CONFIG_PM_BUTTONS_MIN +#endif + +#ifndef CONFIG_PM_IRQBUTTONS_MAX +# define CONFIG_PM_IRQBUTTONS_MAX CONFIG_PM_BUTTONS_MAX +#endif + +#if CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX +# error "CONFIG_PM_IRQBUTTONS_MIN > CONFIG_PM_IRQBUTTONS_MAX" +#endif + +#if CONFIG_PM_IRQBUTTONS_MAX > 7 +# error "CONFIG_PM_IRQBUTTONS_MAX > 7" +#endif + +#ifndef CONFIG_PM_BUTTON_ACTIVITY +# define CONFIG_PM_BUTTON_ACTIVITY 10 +#endif + +/* Miscellaneous Definitions ************************************************/ + +#define MIN_BUTTON MIN(CONFIG_PM_BUTTONS_MIN, CONFIG_PM_IRQBUTTONS_MIN) +#define MAX_BUTTON MAX(CONFIG_PM_BUTTONS_MAX, CONFIG_PM_IRQBUTTONS_MAX) + +#define NUM_PMBUTTONS (MAX_BUTTON - MIN_BUTTON + 1) +#define BUTTON_INDEX(b) ((b)-MIN_BUTTON) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +/**************************************************************************** + * Name: button_handler + * + * Description: + * Handle a button wake-up interrupt + * + ****************************************************************************/ + +static int button_handler(int irq, void *context, void *arg) +{ + /* At this point the MCU should have already awakened. The state + * change will be handled in the IDLE loop when the system is re-awakened + * The button interrupt handler should be totally ignorant of the PM + * activities and should report button activity as if nothing + * special happened. + */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); + return 0; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pmbuttons + * + * Description: + * Configure all the buttons of the STM3210e-eval board as EXTI, + * so any button is able to wakeup the MCU from the PM_STANDBY mode + * + ****************************************************************************/ + +void stm32_pmbuttons(void) +{ +#ifdef CONFIG_ARCH_IRQBUTTONS + int ret; + int i; +#endif + + /* Initialize the button GPIOs */ + + board_button_initialize(); + +#ifdef CONFIG_ARCH_IRQBUTTONS + for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) + { + ret = board_button_irq(i, button_handler, (void *)i); + if (ret < 0) + { + serr("ERROR: board_button_irq failed: %d\n", ret); + } + } +#endif +} + +#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..f506a43e45957 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* GPIO configurations unique to the LCD */ + +static const uint16_t g_lcdconfig[] = +{ + /* NE4 */ + + GPIO_NPS_NE4 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint16_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank4 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR4); + + /* Bank4 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR4); + + putreg32(0xffffffff, STM32_FSMC_BWTR4); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR4); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c index ce5039b0501d4..f5823c781e2a4 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..6d46f6c872e4c --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3210e-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and + * 16-bit accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of + * SRAM, respectively. + * + * Pin Usage (per schematic) + * FLASH SRAM NAND LCD + * D[0..15] [0..15] [0..15] [0..7] [0..15] + * A[0..23] [0..22] [0..18] [16,17] [0] + * FSMC_NBL0 PE0 OUT ~BLE --- --- --- + * FSMC_NBL1 PE1 OUT ~BHE --- --- --- + * FSMC_NE2 PG9 OUT --- ~E --- --- + * FSMC_NE3 PG10 OUT ~CE --- --- --- + * FSMC_NE4 PG12 OUT --- --- --- ~CS + * FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL + * FSMC_NOE PD4 OUT ~OE ~G ~R ~RD + * FSMC_NWAIT PD6 IN --- R~B --- --- + * FSMC_INT2 PG6* IN --- --- R~B --- + * + * *JP7 will switch to PD6 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint16_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG); + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(3) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_MWID16 | + FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..69641713aa004 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c @@ -0,0 +1,146 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3210E-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI1 + /* Configure the SPI-based FLASH CS GPIO */ + + stm32_configgpio(GPIO_FLASH_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (devid == SPIDEV_FLASH(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_FLASH_CS, !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c new file mode 100644 index 0000000000000..ac892b7e8af7b --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3210e-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the STM3210E-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup: PB.14 */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. Alternatively, if no pull-up GPIO the following EXTERN can be + * redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..ecb66a7f25d82 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "stm32.h" + +/* There is nothing to do here if SDIO support is not selected. */ + +#ifdef CONFIG_STM32_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_STM3210E_EVAL +# undef STM32_MMCSDSLOTNO +# define STM32_MMCSDSLOTNO 0 +#else +/* Add configuration for new STM32 boards here */ + +# error "Unrecognized STM32 board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + struct sdio_dev_s *sdio; + int ret; + + /* First, get an instance of the SDIO interface */ + + syslog(LOG_INFO, "Initializing SDIO slot %d\n", STM32_MMCSDSLOTNO); + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + STM32_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_SYSTEM_USBMSC_DEVMINOR1); + + ret = mmcsd_slotinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDIO to the MMC/SD driver\n"); + + /* Then let's guess and say that there is a card in the slot. + * I need to check to see if the STM3210E-EVAL board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} + +#endif /* CONFIG_STM32_SDIO */ diff --git a/boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh new file mode 100755 index 0000000000000..04c7a7606c2a1 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh @@ -0,0 +1,87 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/stm3210e-eval/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3210e-eval/tools/stm32.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/stm32.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt b/boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt rename to boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt new file mode 100644 index 0000000000000..a22235736fc87 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32_tiny/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32_tiny/Kconfig b/boards/arm/stm32f1/stm32_tiny/Kconfig similarity index 100% rename from boards/arm/stm32/stm32_tiny/Kconfig rename to boards/arm/stm32f1/stm32_tiny/Kconfig diff --git a/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig new file mode 100644 index 0000000000000..b6dfc1579c239 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32_tiny" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32_TINY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NRF24L01TERM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0b88bf691343d --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32_tiny" +CONFIG_ARCH_BOARD_STM32_TINY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/stm32_tiny/include/board.h b/boards/arm/stm32f1/stm32_tiny/include/board.h new file mode 100644 index 0000000000000..2a9a1ac8c9218 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/include/board.h @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H +#define __BOARD_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The board has only one controllable LED */ +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* NRF24L01 Driver **********************************************************/ + +/* NRF24L01 chip enable: PB.1 */ + +#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) + +/* NRF24L01 IRQ line: PA.0 */ + +#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE +#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI2 */ + +#define GPIO_SPI2_NSS GPIO_ADJUST_MODE(GPIO_SPI2_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_SCK GPIO_ADJUST_MODE(GPIO_SPI2_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_MISO GPIO_ADJUST_MODE(GPIO_SPI2_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI2_MOSI GPIO_ADJUST_MODE(GPIO_SPI2_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +#endif /* __ARCH_ARM_STM32_STM32_TINY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs new file mode 100644 index 0000000000000..fd9ee583e0705 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/stm32_tiny/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32_tiny/scripts/ld.script b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script new file mode 100644 index 0000000000000..d8c2424728fae --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt new file mode 100644 index 0000000000000..b09d5da50b72c --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c) + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm32_tiny/src/Make.defs b/boards/arm/stm32f1/stm32_tiny/src/Make.defs new file mode 100644 index 0000000000000..3e58ff4b7fee3 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/Make.defs @@ -0,0 +1,33 @@ +############################################################################ +# boards/arm/stm32f1/stm32_tiny/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c stm32_spi.c stm32_usbdev.c + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c new file mode 100644 index 0000000000000..b392a99ddf8c2 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_tiny.h" + +#ifdef CONFIG_WL_NRF24L01 +#include "stm32_nrf24l01.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_WL_NRF24L01) + /* Initialize the NRF24L01 wireless module */ + + ret = board_nrf24l01_initialize(2); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize failed: %d\n", ret); + } +#endif +} +#endif diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c new file mode 100644 index 0000000000000..79b15918460de --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED, v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, + * we simply turn it on when the board boots + */ + + set_led(true); + break; + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c new file mode 100644 index 0000000000000..332755c7b21c0 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM32 Tiny board provides a LED on GPIO line B5. + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32TINY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c new file mode 100644 index 0000000000000..0b27f331ef712 --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32_tiny.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32_SPI2 +# ifdef CONFIG_WL_NRF24L01 + /* Configure the SPI-based NRF24L01 chip select GPIO */ + + spiinfo("Configure GPIO for SPI2/CS\n"); + stm32_configgpio(GPIO_NRF24L01_CS); +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + spiinfo("nRF24L01 device %s\n", selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + switch (devid) + { +#ifdef CONFIG_WL_NRF24L01 + case SPIDEV_WIRELESS(0): + status |= SPI_STATUS_PRESENT; + break; +#endif + default: + break; + } + + return status; +} + +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_tiny.h rename to boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h index 1d113843ecf3a..300fdd01bb155 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_tiny.h + * boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c new file mode 100644 index 0000000000000..b183b6827ef9c --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_tiny.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the Hy-Mini STM32v board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + uinfo("called\n"); + + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined + * to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt new file mode 100644 index 0000000000000..7c8a40cb663a6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/Kconfig b/boards/arm/stm32f1/stm32butterfly2/Kconfig similarity index 100% rename from boards/arm/stm32/stm32butterfly2/Kconfig rename to boards/arm/stm32f1/stm32butterfly2/Kconfig diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig new file mode 100644 index 0000000000000..151be594518f0 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 +CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 +CONFIG_EXAMPLES_MOUNT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig new file mode 100644 index 0000000000000..4ffa586a44c71 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STM32_AUTONEG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_MOUNT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="butterfly2" +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NET=y +CONFIG_NETINIT_DRIPADDR=0x0a010101 +CONFIG_NETINIT_IPADDR=0x0a010163 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOCAL=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PL2303=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ETH100MBPS=y +CONFIG_STM32_ETHFD=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_ETH_REMAP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_MII_EXTCLK=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig new file mode 100644 index 0000000000000..a2793fec93239 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_MOUNT=y +CONFIG_EXAMPLES_USBSERIAL=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PL2303=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_MAXPOWER=500 diff --git a/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig new file mode 100644 index 0000000000000..151be594518f0 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32butterfly2" +CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_HIDKBD_DEFPRIO=50 +CONFIG_EXAMPLES_HIDKBD_STACKSIZE=1024 +CONFIG_EXAMPLES_MOUNT=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBC_STRERROR_SHORT=y +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_MOTD=y +CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you" +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=100 +CONFIG_SCHED_CPULOAD_SYSCLK=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_YEAR=1970 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_REMAP=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_VI=y +CONFIG_TESTING_RAMTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f1/stm32butterfly2/include/board.h b/boards/arm/stm32f1/stm32butterfly2/include/board.h new file mode 100644 index 0000000000000..cef38c97de014 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/include/board.h @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 8 MHz RC factory-trimmed + * LSI - 40 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 14.7456MHz + * LSE - LSE is not connected + */ + +#define STM32_BOARD_XTAL 14745600ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000u +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 0 + +/* PLL output is 71.8848MHz */ + +#define STM32_PLL_PREDIV2 RCC_CFGR2_PREDIV2d4 +#define STM32_PLL_PLL2MUL RCC_CFGR2_PLL2MULx12 +#define STM32_PLL_PREDIV1 RCC_CFGR2_PREDIV1d4 +#define STM32_PLL_PLLMUL RCC_CFGR_PLLMUL_CLKx65 +#define STM32_PLL_FREQUENCY 71884800ul + +/* SYSCLK and HCLK adre the PLL frequency */ + +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* USB clock output is 47.9232MHz */ + +#define STM32_CFGR_OTGFSPRE RCC_CFGR_OTGFSPREd3 + +/* APB2 clock (PCLK2) is HCLK */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY + +#define STM32APB_TIM1_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (35.9424MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* There are four LEDs on stm32butterfly2 board that can be controlled by + * software. + * All pulled high and van be illuminated by driving the output low. + * + * LED1 PB0 + * LED2 PB1 + * LED3 PC4 + * LED4 PC5 + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In thath case, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + */ + +#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF ON */ +#define LED_INIRQ 5 /* In an interrupt N/C N/C N/C GLOW */ +#define LED_SIGNAL 6 /* In a signal handler N/C N/C N/C GLOW */ +#define LED_ASSERTION 7 /* An assertion failed N/C N/C N/C GLOW */ +#define LED_PANIC 8 /* The system has crashed N/C N/C N/C FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. + */ + +/* ADC configuration. Right now only ADC12_IN10 is supported + * (potentiometer) + */ + +#ifdef CONFIG_STM32_ADC2 +# error "CONFIG_STM32_ADC2 is not supported" +#endif + +/* SPI configuration. Only SPI1 is supported */ + +#ifdef CONFIG_STM32_SPI2 +# error "CONFIG_STM32_SPI2 is not supported" +#endif + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM GPIO_ADJUST_MODE(GPIO_OTGFS_DM_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_DP GPIO_ADJUST_MODE(GPIO_OTGFS_DP_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_ID GPIO_ADJUST_MODE(GPIO_OTGFS_ID_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_SOF GPIO_ADJUST_MODE(GPIO_OTGFS_SOF_0, GPIO_MODE_50MHz) +#define GPIO_OTGFS_VBUS GPIO_OTGFS_VBUS_0 + +#endif /* __BOARDS_ARM_STM32_STM32_BUTTERFLY2_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs new file mode 100644 index 0000000000000..42d7ff815b502 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = dfu.ld +else + LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld new file mode 100644 index 0000000000000..dcdeb43f940d6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld new file mode 100644 index 0000000000000..3fc5750bbfc16 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt new file mode 100644 index 0000000000000..6005e74d05fb6 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt @@ -0,0 +1,55 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_leds.c) + +if(CONFIG_STM32_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_SPI1) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_USBHOST) + list(APPEND SRCS stm32_usbhost.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f1/stm32butterfly2/src/Make.defs b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs new file mode 100644 index 0000000000000..f6e1bc4b4f599 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs @@ -0,0 +1,57 @@ +############################################################################ +# boards/arm/stm32f1/stm32butterfly2/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_leds.c + +ifeq ($(CONFIG_STM32_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_SPI1),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +CSRCS += stm32_usbhost.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c new file mode 100644 index 0000000000000..e38387e607b72 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + uint8_t channel[1] = + { + 10 + }; + + struct adc_dev_s *adc; + int rv; + + if (initialized) + { + return OK; + } + + ainfo("INFO: Initializing ADC12_IN10\n"); + stm32_configgpio(GPIO_ADC12_IN10_0); + if ((adc = stm32_adcinitialize(1, channel, 1)) == NULL) + { + aerr("ERROR: Failed to get adc interface\n"); + return -ENODEV; + } + + if ((rv = adc_register("/dev/adc0", adc)) < 0) + { + aerr("ERROR: adc_register failed: %d\n", rv); + return rv; + } + + initialized = true; + ainfo("INFO: ADC12_IN10 initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c new file mode 100644 index 0000000000000..b3391b7eb5699 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32_butterfly2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * Initializes low level pins for the drivers. + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + stm32_led_initialize(); + stm32_spidev_initialize(); + stm32_usb_initialize(); +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret = 0; + +#ifdef CONFIG_MMCSD + ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_USBHOST + ret = stm32_usbhost_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h index f034a407985b3..1f7def6679975 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h + * boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c new file mode 100644 index 0000000000000..8f5f81e84e817 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_BUTTONS 5 + +#define GPIO_JOY_O (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN7) +#define GPIO_JOY_U (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN8) +#define GPIO_JOY_D (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN9) +#define GPIO_JOY_R (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN10) +#define GPIO_JOY_L (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT |\ + GPIO_PORTC | GPIO_PIN11) + +/**************************************************************************** + * Private Declarations + ****************************************************************************/ + +static const uint32_t buttons[NUM_BUTTONS] = +{ + GPIO_JOY_O, GPIO_JOY_U, GPIO_JOY_D, GPIO_JOY_R, GPIO_JOY_L +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * Initializes gpio pins for joystick buttons + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + for (i = 0; i != NUM_BUTTONS; ++i) + { + stm32_configgpio(buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * Reads keys + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t rv = 0; + int i; + + for (i = 0; i != NUM_BUTTONS; ++i) + { + if (stm32_gpioread(buttons[i]) == 0) + { + rv |= 1 << i; + } + } + + return rv; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c new file mode 100644 index 0000000000000..08723b683580f --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c @@ -0,0 +1,257 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN4) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_CNF_OUTPP | GPIO_MODE_50MHz |\ + GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Identifies led state */ + +enum led_state +{ + LED_ON = false, + LED_OFF = true +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_state + * + * Description: + * Sets pack of leds to given state + ****************************************************************************/ + +static void led_state(enum led_state state, unsigned int leds) +{ + if (leds & BOARD_LED1_BIT) + { + stm32_gpiowrite(GPIO_LED1, state); + } + + if (leds & BOARD_LED2_BIT) + { + stm32_gpiowrite(GPIO_LED2, state); + } + + if (leds & BOARD_LED3_BIT) + { + stm32_gpiowrite(GPIO_LED3, state); + } + + if (leds & BOARD_LED4_BIT) + { + stm32_gpiowrite(GPIO_LED4, state); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + * + * Description: + * Initializes low level gpio pins for board LEDS + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Drives board leds when specific RTOS state led occurs. + * + * Input Parameters: + * led - This is actually RTOS state not led number of anything like that + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case LED_STARTED: + led_state(LED_OFF, BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED1_BIT); + break; + + case LED_HEAPALLOCATE: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED2_BIT); + break; + + case LED_IRQSENABLED: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); + led_state(LED_ON, BOARD_LED3_BIT); + break; + + case LED_STACKCREATED: + led_state(LED_OFF, BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT); + led_state(LED_ON, BOARD_LED4_BIT); + break; + + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + led_state(LED_ON, BOARD_LED4_BIT); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Drives board leds when specific RTOS state led ends + * + * Input Parameters: + * led - This is actually RTOS state not led number of anything like that + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_STARTED: + led_state(LED_OFF, BOARD_LED1_BIT); + break; + + case LED_HEAPALLOCATE: + led_state(LED_OFF, BOARD_LED2_BIT); + break; + + case LED_IRQSENABLED: + led_state(LED_OFF, BOARD_LED3_BIT); + break; + + case LED_STACKCREATED: + case LED_INIRQ: + case LED_SIGNAL: + case LED_ASSERTION: + case LED_PANIC: + led_state(LED_OFF, BOARD_LED4_BIT); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * This function should initialize leds for user use, but on RTOS start we + * initialize every led for use by RTOS and at end, when RTOS is fully + * booted up, we give control of these specific leds for user. So that's + * why this function is empty. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Already initialized by stm32_led_initialize. */ + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Sets led to ledon state. + * + * Input Parameters: + * led - Led to be set, indexed from 0 + * ledon - new state for the led. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + unsigned int ledbit; + +#ifndef CONFIG_ARCH_LEDS + if (led == BOARD_LED4) + { + return; + } +#endif + + ledbit = 1 << led; + led_state(ledon, ledbit); +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Sets whole ledset to given state. + * + * Input Parameters: + * ledset - Led bits to be set on or off + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ +#ifdef CONFIG_ARCH_LEDS + led_state(LED_ON, ledset & ~BOARD_LED4_BIT); + led_state(LED_OFF, ~(ledset | BOARD_LED4_BIT)); +#else + led_state(LED_ON, ledset); + led_state(LED_OFF, ~ledset); +#endif +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..b471480af3487 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_butterfly2.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_SPI1 +# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/* Media changed callback */ + +static spi_mediachange_t g_chmediaclbk; + +/* Argument for media changed callback */ + +static void *g_chmediaarg; + +/* Semafor to inform stm32_cd_thread that card was inserted or pulled out */ + +static sem_t g_cdsem = SEM_INITIALIZER(0); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cd_thread + * + * Description: + * Working thread to call mediachanged function when card is inserted or + * pulled out. + ****************************************************************************/ + +static void *stm32_cd_thread(void *arg) +{ + spiinfo("INFO: Running card detect thread\n"); + while (1) + { + nxsem_wait(&g_cdsem); + spiinfo("INFO: Card has been inserted, initializing\n"); + + if (g_chmediaclbk) + { + /* Card doesn't seem to initialize properly without letting it to + * rest for a millisecond or so. + */ + + nxsched_usleep(1 * 1000); + g_chmediaclbk(g_chmediaarg); + } + } + + return NULL; +} + +/**************************************************************************** + * Name: stm32_cd + * + * Description: + * Card detect interrupt handler. + ****************************************************************************/ + +static int stm32_cd(int irq, void *context, void *arg) +{ + static const int debounce_time = 100; /* [ms] */ + static uint32_t now = 0; + static uint32_t prev = 0; + struct timespec tp; + + clock_systime_timespec(&tp); + now = tp.tv_sec * 1000 + tp.tv_nsec / 1000000; + + /* When inserting card, card detect plate might bounce causing this + * interrupt to be called many time on single card insert/deinsert. Thus + * we are allowing only one interrupt every 100ms. + */ + + if (now - debounce_time > prev) + { + prev = now; + nxsem_post(&g_cdsem); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + g_chmediaclbk = callback; + g_chmediaarg = arg; + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int minor) +{ + struct spi_dev_s *spi; + struct sched_param schparam; + pthread_attr_t pattr; + int rv; + + spiinfo("INFO: Initializing mmcsd card\n"); + if ((spi = stm32_spibus_initialize(SD_SPI_PORT)) == NULL) + { + ferr("failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + if ((rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi)) < 0) + { + ferr("failed to bind SPI port %d to SD slot %d\n", SD_SPI_PORT, + SD_SLOT_NO); + return rv; + } + + stm32_gpiosetevent(GPIO_SD_CD, true, true, true, stm32_cd, NULL); + + pthread_attr_init(&pattr); +#ifdef CONFIG_DEBUG_FS + pthread_attr_setstacksize(&pattr, 1024); +#else + pthread_attr_setstacksize(&pattr, 256); +#endif + + schparam.sched_priority = 50; + pthread_attr_setschedparam(&pattr, &schparam); + pthread_create(NULL, &pattr, stm32_cd_thread, NULL); + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c new file mode 100644 index 0000000000000..0d6e77b58db94 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32_butterfly2.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + * Note: + * Here only CS pins are configured as SPI pins are configured by driver + * itself. + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + spiinfo("INFO: Initializing spi gpio pins\n"); + + stm32_configgpio(GPIO_SD_CS); + stm32_configgpio(GPIO_SD_CD); +} + +/**************************************************************************** + * Name: stm32_spi1select + * + * Description: + * Function asserts given devid based on select + ****************************************************************************/ + +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool select) +{ + spiinfo("INFO: Selecting spi dev: %" PRId32 ", state: %d\n", + devid, select); + + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SD_CS, !select); + } +} + +/**************************************************************************** + * Name: stm32_spi1status + * + * Description: + * Return status of devid + ****************************************************************************/ + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + spiinfo("INFO: Requesting info from spi dev: %" PRId32 "\n", devid); + + if (devid == SPIDEV_MMCSD(0)) + { + if (stm32_gpioread(GPIO_SD_CD) == 0) + { + return SPI_STATUS_PRESENT; + } + } + + return 0; +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c new file mode 100644 index 0000000000000..53cdb720cf874 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c @@ -0,0 +1,51 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_gpio.h" + +#include +#include "stm32_butterfly2.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_initialize + * + * Description: + * Initializes USB pins + ****************************************************************************/ + +void stm32_usb_initialize(void) +{ + uinfo("INFO: Initializing usb otgfs gpio pins\n"); + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c new file mode 100644 index 0000000000000..b7414d0669f3f --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_OTGFS +# error "CONFIG_USBDEV requires CONFIG_STM32_OTGFS to be enabled" +#endif + +#ifdef CONFIG_USBHOST +# error "CONFIG_USBDEV cannot be set alongside CONFIG_USBHOST" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + * TODO: + * - Well... implement those features like clock shutdown. + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("INFO: usb %s", resume ? "resumed" : "suspended"); +} diff --git a/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c new file mode 100644 index 0000000000000..6510e703c9b53 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_butterfly2.h" +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_OTGFS +# error "CONFIG_USBHOST requires CONFIG_STM32_OTGFS to be enabled" +#endif + +#ifdef CONFIG_USBDEV +# error "CONFIG_USBHOST cannot be set alongside CONFIG_USBDEV" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct usbhost_connection_s *g_usbconn; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_detect + * + * Description: + * Wait for USB devices to be connected. + ****************************************************************************/ + +static void *usbhost_detect(void *arg) +{ + struct usbhost_hubport_s *hport; + + uinfo("INFO: Starting usb detect thread\n"); + + for (; ; ) + { + CONN_WAIT(g_usbconn, &hport); + + if (hport->connected) + { + CONN_ENUMERATE(g_usbconn, hport); + } + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Initializes USB host functionality. + ****************************************************************************/ + +int stm32_usbhost_initialize(void) +{ + int rv; + +#ifdef CONFIG_USBHOST_MSC + uinfo("INFO: Initializing USB MSC class\n"); + + if ((rv = usbhost_msc_initialize()) < 0) + { + uerr("ERROR: Failed to register mass storage class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_CDACM + uinfo("INFO: Initializing CDCACM usb class\n"); + + if ((rv = usbhost_cdacm_initialize()) < 0) + { + uerr("ERROR: Failed to register CDC/ACM serial class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + uinfo("INFO: Initializing HID Keyboard usb class\n"); + + if ((rv = usbhost_kbdinit()) < 0) + { + uerr("ERROR: Failed to register the KBD class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + uinfo("INFO: Initializing HID Mouse usb class\n"); + + if ((rv = usbhost_mouse_init()) < 0) + { + uerr("ERROR: Failed to register the mouse class: %d\n", rv); + } +#endif + +#ifdef CONFIG_USBHOST_HUB + uinfo("INFO: Initializing USB HUB class\n"); + + if ((rv = usbhost_hub_initialize()) < 0) + { + uerr("ERROR: Failed to register hub class: %d\n", rv); + } +#endif + + if ((g_usbconn = stm32_otgfshost_initialize(0))) + { + pthread_attr_t pattr; + struct sched_param schparam; + + pthread_attr_init(&pattr); + pthread_attr_setstacksize(&pattr, 2048); + + schparam.sched_priority = 50; + pthread_attr_setschedparam(&pattr, &schparam); + + return pthread_create(NULL, &pattr, usbhost_detect, NULL); + } + + return -ENODEV; +} + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. + * + * The application uses this field to control power to this port, and the + * core clears this bit on an overcurrent condition. + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + ****************************************************************************/ + +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt new file mode 100644 index 0000000000000..617cc91dd8803 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/Kconfig b/boards/arm/stm32f1/stm32f103-minimum/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f103-minimum/Kconfig rename to boards/arm/stm32f1/stm32f103-minimum/Kconfig diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig new file mode 100644 index 0000000000000..36fb231b5a9fa --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ADBD_DEVICE_ID="test" +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FILE_STREAM=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="adbd_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DFU=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=8 +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig new file mode 100644 index 0000000000000..cbb116b3a5311 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_APDS9960=y +CONFIG_FILE_STREAM=y +CONFIG_I2C_DRIVER=y +CONFIG_IDLETHREAD_STACKSIZE=512 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PTHREAD_STACK_MIN=512 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=3072 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_APDS9960=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig new file mode 100644 index 0000000000000..002da5d5dbb8a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_TONE=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig new file mode 100644 index 0000000000000..1909d11c9d45a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig new file mode 100644 index 0000000000000..1ef7b1dec1d77 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=4 +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_HOST_MACOS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig new file mode 100644 index 0000000000000..175e2d56fbca7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="hello_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_LINE_MAX=80 +CONFIG_MM_SMALL=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_NOEXT_VECTORS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig new file mode 100644 index 0000000000000..abeabb55778c9 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 +CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_ST7567=y +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXTK_BORDERWIDTH=1 +CONFIG_NX_BLOCKING=y +CONFIG_NX_WRITEONLY=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..d9b48e9bb91a7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FILE_STREAM=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD_BACKPACK=y +CONFIG_LCD_LCD1602=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SLCD=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig new file mode 100644 index 0000000000000..f86c33c470acb --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_CANUTILS_CANLIB=y +CONFIG_CAN_MCP2515=y +CONFIG_CAN_TXREADY=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_READ=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_MCP2515_PHASESEG1=3 +CONFIG_MCP2515_PROPSEG=1 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig new file mode 100644 index 0000000000000..9c543b8150d49 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NRF24L01TERM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WL_NRF24L01=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig new file mode 100644 index 0000000000000..17c41e7e90488 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig new file mode 100644 index 0000000000000..36708cff5947c --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig new file mode 100644 index 0000000000000..8a19f92058947 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CL_MFRC522=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_CONTACTLESS=y +CONFIG_EXAMPLES_RFID_READUID=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig new file mode 100644 index 0000000000000..f13a149685258 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH4OUT=y +CONFIG_STM32_TIM4_CHANNEL=4 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig new file mode 100644 index 0000000000000..ded90e2212abe --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_I2C=y +CONFIG_I2C_DRIVER=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM_TOOLCHAIN=y +CONFIG_LINE_MAX=80 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_DS18B20=y +CONFIG_SENSORS_DS18B20_POLL=y +CONFIG_SENSORS_HYT271=y +CONFIG_SENSORS_HYT271_POLL=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C2=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART2_1WIREDRIVER=y +CONFIG_STM32_USART_SINGLEWIRE=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SENSORTEST=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig new file mode 100644 index 0000000000000..88c42001647ae --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_SSD1306_I2C=y +CONFIG_LCD_UG2864HSWEG01=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0f71cd1624691 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USB=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV_TRACE=y +CONFIG_USBDEV_TRACE_NRECORDS=32 diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig new file mode 100644 index 0000000000000..a1bd26f706dff --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig new file mode 100644 index 0000000000000..79db5a7a98fe7 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f103-minimum" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_VEML6070=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/stm32f103-minimum/include/board.h b/boards/arm/stm32f1/stm32f103-minimum/include/board.h new file mode 100644 index 0000000000000..52c125f7cc8c1 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/include/board.h @@ -0,0 +1,321 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* BUTTON definitions *******************************************************/ + +#define NUM_BUTTONS 2 + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) + +/* LED definitions **********************************************************/ + +/* Define how many LEDs this board has (needed by userleds) */ + +#define BOARD_NLEDS 1 + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED2 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 off */ +#define LED_SIGNAL 5 /* LED2 on */ +#define LED_ASSERTION 6 /* LED1 + LED2 */ +#define LED_PANIC 7 /* LED1 / LED2 blinking */ + +/* PWM + * + * The STM32F103-Minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH3 on PB0. + * + * Note: we don't need redefine GPIO_TIM3_CH3OUT because PB0 is not + * remap pin. + */ + +/* RGB LED + * + * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 + * + * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT + */ + +#define RGBLED_RPWMTIMER 1 +#define RGBLED_RPWMCHANNEL 1 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 2 +#define RGBLED_BPWMTIMER 4 +#define RGBLED_BPWMCHANNEL 4 + +/* Tone Driver **************************************************************/ + +#define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */ +#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */ +#define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */ +#define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */ + +/* NRF24L01 Driver **********************************************************/ + +/* Chip enable: PB.1 */ + +#define GPIO_NRF24L01_CE (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) + +/* IRQ line: PA.0 */ + +#define GPIO_NRF24L01_IRQ (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_NRF24L01_GPIO_CE GPIO_NRF24L01_CE +#define BOARD_NRF24L01_GPIO_IRQ GPIO_NRF24L01_IRQ + +/* HCSR04 driver */ + +/* Pins config to use with HC-SR04 sensor */ + +#define GPIO_HCSR04_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) +#define GPIO_HCSR04_TRIG (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1) + +#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT +#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG +#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ + +/* Pin for APDS-9960 sensor */ + +#define GPIO_APDS9960_INT (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT + +/* ZERO CROSS pin definition */ + +#define BOARD_ZEROCROSS_GPIO \ + (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_PORTA|GPIO_PIN0) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* USART2 */ + +#define GPIO_USART2_TX GPIO_ADJUST_MODE(GPIO_USART2_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART2_RX GPIO_USART2_RX_0 +#define GPIO_USART2_CTS GPIO_USART2_CTS_0 +#define GPIO_USART2_RTS GPIO_ADJUST_MODE(GPIO_USART2_RTS_0, GPIO_MODE_50MHz) +#define GPIO_USART2_CK GPIO_ADJUST_MODE(GPIO_USART2_CK_0, GPIO_MODE_50MHz) + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* I2C1 */ + +#define GPIO_I2C1_SCL GPIO_ADJUST_MODE(GPIO_I2C1_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C1_SDA GPIO_ADJUST_MODE(GPIO_I2C1_SDA_0, GPIO_MODE_50MHz) + +/* I2C2 */ + +#define GPIO_I2C2_SCL GPIO_ADJUST_MODE(GPIO_I2C2_SCL_0, GPIO_MODE_50MHz) +#define GPIO_I2C2_SDA GPIO_ADJUST_MODE(GPIO_I2C2_SDA_0, GPIO_MODE_50MHz) + +/* CAN1 */ + +#define GPIO_CAN1_RX GPIO_CAN1_RX_0 +#define GPIO_CAN1_TX GPIO_ADJUST_MODE(GPIO_CAN1_TX_0, GPIO_MODE_50MHz) + +/* USB */ + +#define GPIO_USB_DM GPIO_USB_DM_0 +#define GPIO_USB_DP GPIO_USB_DP_0 + +/* TIM1 */ + +#define GPIO_TIM1_CH1IN GPIO_TIM1_CH1IN_0 +#define GPIO_TIM1_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2IN GPIO_TIM1_CH2IN_0 +#define GPIO_TIM1_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3IN GPIO_TIM1_CH3IN_0 +#define GPIO_TIM1_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH4IN GPIO_TIM1_CH4IN_0 +#define GPIO_TIM1_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM1_CH4OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_BKIN GPIO_TIM1_BKIN_0 +#define GPIO_TIM1_ETR GPIO_TIM1_ETR_0 +#define GPIO_TIM1_CH1NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH1NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH2NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH2NOUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM1_CH3NOUT GPIO_ADJUST_MODE(GPIO_TIM1_CH3NOUT_0, GPIO_MODE_50MHz) + +/* TIM2 */ + +#define GPIO_TIM2_CH1IN GPIO_TIM2_CH1IN_0 +#define GPIO_TIM2_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH2IN GPIO_TIM2_CH2IN_0 +#define GPIO_TIM2_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH3IN GPIO_TIM2_CH3IN_0 +#define GPIO_TIM2_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM2_CH4IN GPIO_TIM2_CH4IN_0 +#define GPIO_TIM2_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM2_CH4OUT_0, GPIO_MODE_50MHz) + +/* TIM3 */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_0 +#define GPIO_TIM3_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_0 +#define GPIO_TIM3_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH3IN GPIO_TIM3_CH3IN_0 +#define GPIO_TIM3_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM3_CH4IN GPIO_TIM3_CH4IN_0 +#define GPIO_TIM3_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM3_CH4OUT_0, GPIO_MODE_50MHz) + +/* TIM4 */ + +#define GPIO_TIM4_CH1IN GPIO_TIM4_CH1IN_0 +#define GPIO_TIM4_CH1OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH1OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH2IN GPIO_TIM4_CH2IN_0 +#define GPIO_TIM4_CH2OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH2OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH3IN GPIO_TIM4_CH3IN_0 +#define GPIO_TIM4_CH3OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH3OUT_0, GPIO_MODE_50MHz) +#define GPIO_TIM4_CH4IN GPIO_TIM4_CH4IN_0 +#define GPIO_TIM4_CH4OUT GPIO_ADJUST_MODE(GPIO_TIM4_CH4OUT_0, GPIO_MODE_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F103_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs new file mode 100644 index 0000000000000..2fc72d54d7f9f --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script new file mode 100644 index 0000000000000..2b4373a395604 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + * + * NOTE: While the STM32F103C8T6 states that the part has 64Kb of FLASH, + * all parts that I have seen do, in fact, have 128Kb of FLASH. That + * additional 64Kb of FLASH can be utilized by simply change the LENGTH + * of the flash region from 64K to 128K. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = LOADADDR(.data); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu new file mode 100644 index 0000000000000..28a18a1d04ad3 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F103C8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 20Kb of SRAM beginning at address 0x2000:0000. Here we assume that the + * STM32duino bootloader is being used. In that case, the correct load .text + * address is 0x0800:2000 (leaving 56Kb). + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08002000, LENGTH = 120K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */ + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt new file mode 100644 index 0000000000000..20cf639591054 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt @@ -0,0 +1,120 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SENSORS_HYT271) + list(APPEND SRCS stm32_hyt271.c) +endif() + +if(CONFIG_SENSORS_DS18B20) + list(APPEND SRCS stm32_ds18b20.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_MTD_AT24XX) + if(CONFIG_STM32_I2C1) + list(APPEND SRCS stm32_at24.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +if(CONFIG_LCD_MAX7219) + list(APPEND SRCS stm32_max7219.c) +endif() + +if(CONFIG_INPUT_NUNCHUCK) + list(APPEND SRCS stm32_nunchuck.c) +endif() + +if(CONFIG_LCD_SSD1306_I2C) + list(APPEND SRCS stm32_lcd_ssd1306.c) +endif() + +if(CONFIG_LCD_ST7567) + list(APPEND SRCS stm32_lcd_st7567.c) +endif() + +if(CONFIG_LCD_PCD8544) + list(APPEND SRCS stm32_pcd8544.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs new file mode 100644 index 0000000000000..c704b2c356464 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs @@ -0,0 +1,122 @@ +############################################################################ +# boards/arm/stm32f1/stm32f103-minimum/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) + CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_HYT271),y) + CSRCS += stm32_hyt271.c +endif + +ifeq ($(CONFIG_SENSORS_DS18B20),y) + CSRCS += stm32_ds18b20.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_MMCSD),y) + CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_MTD_W25),y) + CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_MTD_AT24XX),y) +ifeq ($(CONFIG_STM32_I2C1),y) +CSRCS += stm32_at24.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) + CSRCS += stm32_max7219.c +endif + +ifeq ($(CONFIG_INPUT_NUNCHUCK),y) + CSRCS += stm32_nunchuck.c +endif + +ifeq ($(CONFIG_LCD_SSD1306_I2C),y) +CSRCS += stm32_lcd_ssd1306.c +endif + +ifeq ($(CONFIG_LCD_ST7567),y) + CSRCS += stm32_lcd_st7567.c +endif + +ifeq ($(CONFIG_LCD_PCD8544),y) + CSRCS += stm32_pcd8544.c +endif + +ifeq ($(CONFIG_USBDEV),y) + CSRCS += stm32_usbdev.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c new file mode 100644 index 0000000000000..ab527d7429ea5 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32f103_minimum.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 2 ADC interfaces are supported */ + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel to be used with Variable Resistor + * (Pontentiometer) + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; /* ADC12_IN0 */ + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN0 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c new file mode 100644 index 0000000000000..f4ac9eccdcc15 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" +#include "stm32f103_minimum.h" + +#ifdef HAVE_AT24 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_automount + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_automount(int minor) +{ + struct i2c_master_s *i2c; + struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + mtd = at24c_initialize(i2c); + if (!mtd) + { + ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + +#if defined(CONFIG_STM32F103MINIMUM_AT24_FTL) + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", AT24_MINOR); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } + +#elif defined(CONFIG_STM32F103MINIMUM_AT24_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + finfo("Initialize the NXFFS file system\n"); + ret = nxffs_initialize(mtd); + if (ret < 0) + { + ferr("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/at24 */ + + finfo("Mount the NXFFS file system at /dev/at24\n"); + ret = nx_mount(NULL, "/mnt/at24", "nxffs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } +#endif + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* HAVE_AT24 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c new file mode 100644 index 0000000000000..341981c8dd2d4 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED1, !v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + + /* As the board provides only one soft controllable LED, we simply + * turn it on when the board boots. + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c new file mode 100644 index 0000000000000..029f62453edd4 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is + * 1) USBDEV is selected, + * 2) the USB controller is not disabled, and + * 3) the weak function stm32_usbinitialize() has been brought + * into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c new file mode 100644 index 0000000000000..90273d107320b --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c @@ -0,0 +1,603 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#include "stm32f103_minimum.h" + +/* Conditional logic in stm32f103_minimum.h will determine if certain + * features are supported. Tests for these features need to be made after + * including stm32f103_minimum.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_LEDS_APA102 +#include "stm32_apa102.h" +#endif + +#ifdef CONFIG_WS2812 +#include "stm32_ws2812.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +#ifdef CONFIG_SENSORS_VEML6070 +#include "stm32_veml6070.h" +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK +#include "stm32_nunchuck.h" +#endif + +#ifdef CONFIG_AUDIO_TONE +#include "stm32_tone.h" +#endif + +#ifdef CONFIG_SENSORS_LM75 +#include "stm32_lm75.h" +#endif + +#ifdef CONFIG_WL_NRF24L01 +#include "stm32_nrf24l01.h" +#endif + +#ifdef CONFIG_SENSORS_HCSR04 +#include "stm32_hcsr04.h" +#endif + +#ifdef CONFIG_SENSORS_APDS9960 +#include "stm32_apds9960.h" +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS +#include "stm32_zerocross.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HYT271 +# define HAVE_SENSORS_DEVICE +#endif + +#ifdef CONFIG_SENSORS_DS18B20 +# define HAVE_SENSORS_DEVICE +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_USBADB +#include +#endif + +#ifdef CONFIG_I2C_DRIVER +#include +#include "stm32_i2c.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by W25 Flash */ + +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/* Checking needed by MMC/SDCard */ + +#ifdef CONFIG_NSH_MMCSDMINOR +# define MMCSD_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define MMCSD_MINOR 0 +#endif + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_DRIVER +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_SENSORS_DEVICE +static int g_sensor_devno; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_ONESHOT + struct oneshot_lowerhalf_s *os = NULL; +#endif + int ret = OK; + +#ifdef CONFIG_DEV_GPIO + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_I2C_DRIVER + /* Register I2C drivers on behalf of the I2C tool */ + #ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); + #endif + #ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); + #endif + #ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); + #endif +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS + /* Configure the zero-crossing driver */ + + ret = board_zerocross_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize Zero-Cross, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD + ret = stm32_mmcsd_initialize(MMCSD_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef HAVE_AT24 + /* Initialize the AT24 driver */ + + ret = stm32_at24_automount(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_at24_automount() failed: %d\n", ret); + return ret; + } +#endif /* HAVE_AT24 */ + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_AUDIO_TONE + /* Configure and initialize the tone generator. */ + + ret = board_tone_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_tone_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LEDS_APA102 + /* Configure and initialize the APA102 LED Strip. */ + + ret = board_apa102_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apa102_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WS2812 + /* Configure and initialize the WS2812 LEDs. */ + + ret = board_ws2812_initialize(0, WS2812_SPI, WS2812_NLEDS); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_HYT271 + /* Configure and initialize the HYT271 sensors */ + + ret = stm32_hyt271initialize(g_sensor_devno); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_hyt271initialize() failed: %d\n", ret); + } + else + { + g_sensor_devno += ret; + } +#endif + +#ifdef CONFIG_SENSORS_DS18B20 + /* Configure and initialize the DS18B20 sensors */ + + ret = stm32_ds18b20initialize(g_sensor_devno); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ds18b20initialize() failed: %d\n", ret); + } + else + { + g_sensor_devno += ret; + } +#endif + +#ifdef CONFIG_LM75_I2C + /* Configure and initialize the LM75 sensor */ + + ret = board_lm75_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_HCSR04 + /* Configure and initialize the HC-SR04 distance sensor */ + + ret = board_hcsr04_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: board_max6675_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ONESHOT + os = oneshot_initialize(1, 10); + if (os) + { + ret = oneshot_register("/dev/oneshot", os); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = board_nunchuck_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nunchuck_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, + CONFIG_STM32F103MINIMUM_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_APDS9960 + /* Register the APDS-9960 gesture sensor */ + + ret = board_apds9960_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_SENSORS_VEML6070 + /* Register the UV-A light sensor */ + + ret = board_veml6070_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_veml6070_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_WL_NRF24L01) + /* Initialize the NRF24L01 wireless module */ + + ret = board_nrf24l01_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_nrf24l01_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + /* STM32F103C8 may not have enough Flash for SocketCAN; use a part with + * more Flash (e.g. STM32F103CB). + */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c new file mode 100644 index 0000000000000..55775a26fd983 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER1, GPIO_BTN_USER2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c new file mode 100644 index 0000000000000..3b80bc794fd9a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32.h" +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c new file mode 100644 index 0000000000000..db15840d4b867 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_cansockinitialize() to register the CAN network device */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c index 91b7c4e8da079..3749f5d14c063 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c new file mode 100644 index 0000000000000..aa0cf6dc13b77 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif /* BOARD_NGPIOIN > 0 */ +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif /* BOARD_NGPIOOUT > 0 */ +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif /* BOARD_NGPIOINT > 0 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif /* BOARD_NGPIOIN > 0 */ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif /* BOARD_NGPIOOUT > 0 */ + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif /* BOARD_NGPIOINT > 0 */ + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + + #if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif /* BOARD_NGPIOINT > 0 */ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif /* BOARD_NGPIOIN > 0*/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif /* BOARD_NGPIOOUT > 0 */ + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif /* BOARD_NGPIOINT > 0 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c index e054a450031e4..7ebd76dd08a59 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..206ed62e678c8 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f103_minimum.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_I2C_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c index 97381277ed099..e0337214ebf25 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c new file mode 100644 index 0000000000000..d4205a9f0e534 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct spi_dev_s *g_spidev; +struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (!g_spidev) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = max7219_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..ed9b317847f85 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..a8aa3c854896b --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f103_minimum.h" +#include "stm32_spi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_SPI1 +# error "SD driver requires CONFIG_STM32_SPI1 to be enabled" +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Private Definitions + ****************************************************************************/ + +static const int SD_SPI_PORT = 1; /* SD is connected to SPI1 port */ +static const int SD_SLOT_NO = 0; /* There is only one SD slot */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* NOTE: We are using a SDCard adapter/module without Card Detect pin! + * Then we don't need to Card Detect callback here. + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi1 device\n"); + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int minor) +{ + struct spi_dev_s *spi; + int rv; + + mcinfo("INFO: Initializing mmcsd card\n"); + + spi = stm32_spibus_initialize(SD_SPI_PORT); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, SD_SLOT_NO, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + SD_SPI_PORT, SD_SLOT_NO); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c index 1bff3d3426aa5..da8ff4b7a2230 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c new file mode 100644 index 0000000000000..8cdb0e0fe6eb0 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f103-minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connect to CN5 just for this purpose: + * + * PB0 ADC12_IN8/TIM3_CH3 + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F103MINIMUM_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F103MINIMUM_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c new file mode 100644 index 0000000000000..886ca544518ed --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ +#ifdef CONFIG_STM32_DFU + /* TODO handle reboot to bootloader */ + +#endif + + up_systemreset(); + return 0; +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c new file mode 100644 index 0000000000000..5363f128f711e --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_RGBLED +#endif + +#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c new file mode 100644 index 0000000000000..46f22b8038bda --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c @@ -0,0 +1,285 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the HY-MiniSTM32 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_LCD_ST7567 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_LCD_PCD8544 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_WL_NRF24L01 + stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_CD, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c new file mode 100644 index 0000000000000..812481439f930 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the STM32F103 Minimum board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* USB Soft Connect Pullup */ + + stm32_configgpio(GPIO_USB_PULLUP); +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. Alternatively, if no pull-up GPIO the following EXTERN + * can be redefined to be NULL. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..d7e83b0581e7a --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c new file mode 100644 index 0000000000000..96c7b06056852 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f103_minimum.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c new file mode 100644 index 0000000000000..96b95da27caff --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" + +#include "stm32f103_minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the watchdog + * timer + */ + +#define W25_SPI_PORT 1 + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/* Can't support both FAT and SMARTFS */ + +#if defined(CONFIG_FS_FAT) && defined(CONFIG_FS_SMARTFS) +# warning "Can't support both FAT and SMARTFS -- using FAT" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ + int ret; +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; + struct mtd_geometry_s geo; +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F103MINIMUM_FLASH_PART_NAMES; +#endif + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(W25_SPI_PORT); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + W25_SPI_PORT); + return -ENODEV; + } + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" + "W25 FLASH driver\n", W25_SPI_PORT); + return -ENODEV; + } + +#ifndef CONFIG_FS_SMARTFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide SMARTFS on the MTD interface */ + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_STM32F103MINIMUM_FLASH_PART + { + int partno; + int partsize; + int partoffset; + int partszbytes; + int erasesize; + const char *partstring = CONFIG_STM32F103MINIMUM_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partref[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + /* Get the Flash erase size */ + + erasesize = geo.erasesize; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + partszbytes = (partsize << 10); /* partsize is defined in KB */ + + /* Check if partition size is bigger then erase block */ + + if (partszbytes < erasesize) + { + syslog(LOG_ERR, + "ERROR: Partition size is lesser than erasesize!\n"); + return -1; + } + + /* Check if partition size is multiple of erase block */ + + if ((partszbytes % erasesize) != 0) + { + syslog(LOG_ERR, + "ERROR: Partition size isn't multiple of erasesize!\n"); + return -1; + } + + mtd_part = mtd_partition(mtd, partoffset, partszbytes / erasesize); + partoffset += partszbytes / erasesize; + +#ifdef CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_STM32F103MINIMUM_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partref, sizeof(partref), "p%d", partno); + smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, + mtd_part, partref); +#endif + } + + /* Set the partition name */ + +#if defined(CONFIG_MTD_PARTITION_NAMES) + if (!mtd_part) + { + syslog(LOG_ERR, "Error: failed to create partition %s\n", + partname); + return -1; + } + + mtd_setpartitionname(mtd_part, partname); + + /* Now skip to next name. We don't need to split the string here + * because the MTD partition logic will only display names up to + * the comma, thus allowing us to use a single static name + * in the code. + */ + + while (*partname != ',' && *partname != '\0') + { + /* Skip to next ',' */ + + partname++; + } + + if (*partname == ',') + { + partname++; + } +#endif + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_STM32F103MINIMUM_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F103MINIMUM_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_STM32F103MINIMUM_FLASH_PART */ +#endif /* CONFIG_FS_SMARTFS */ +#endif /* HAVE_W25 */ + + return OK; +} diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h index a3cac399ded8f..5270b996e1c83 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h + * boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt new file mode 100644 index 0000000000000..82b0be5e77cee --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/Kconfig b/boards/arm/stm32f1/stm32vldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32vldiscovery/Kconfig rename to boards/arm/stm32f1/stm32vldiscovery/Kconfig diff --git a/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..dc5b5c596e92c --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32vldiscovery" +CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F100RB=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2398 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_IDLETHREAD_STACKSIZE=128 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=768 +CONFIG_INTELHEX_BINARY=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=4 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PTHREAD_STACK_DEFAULT=128 +CONFIG_PTHREAD_STACK_MIN=128 +CONFIG_RAM_SIZE=8192 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STDIO_BUFFER_SIZE=0 +CONFIG_STM32_BKP=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_RXBUFSIZE=128 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=128 diff --git a/boards/arm/stm32f1/stm32vldiscovery/include/board.h b/boards/arm/stm32f1/stm32vldiscovery/include/board.h new file mode 100644 index 0000000000000..cde0a062e8e30 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/include/board.h @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* On-board crystal frequency is 8MHz (HSE) */ + +#define STM32_BOARD_XTAL 8000000ul + +/* PLL source is HSE / 1, + * PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz + */ + +#define STM32_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1d1 +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx3 +#define STM32_PLL_FREQUENCY (3 * STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (24MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers (1, 15-17) will receive PCLK2. */ + +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB1 timers (2-7, 12-14) will receive PCLK1. */ + +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM12_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM13_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM14_CLKIN STM32_PCLK1_FREQUENCY + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,15-17 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* It is assumed that a generic board has 1 LED. Thus only two different + * states can be shown. Statuses defined as "1" will light the LED, the + * ones defined as "0" will turn the LED off. + */ + +#define LED_STARTED 1 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 1 +#define LED_STACKCREATED 1 +#define LED_INIRQ 1 +#define LED_SIGNAL 1 +#define LED_ASSERTION 0 +#define LED_PANIC 0 + +/* Button definitions *******************************************************/ + +/* It is assumed that a generic board has 1 button. */ + +#define BUTTON_0 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_0_BIT (1 << BUTTON_0) + +/* Alternate function pin selections ****************************************/ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +#endif /* __BOARDS_ARM_STM32_STM32VLDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs new file mode 100644 index 0000000000000..ae0bf8f97a444 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = stm32vldiscovery.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld rename to boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld index d0ce202ebf6d0..0decb5ac94d45 100644 --- a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld + * boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..d28696c419692 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c) + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32vldiscovery.ld") diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs new file mode 100644 index 0000000000000..2cac864f9dcd7 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs @@ -0,0 +1,29 @@ +############################################################################ +# boards/arm/stm32f1/stm32vldiscovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_buttons.c + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c new file mode 100644 index 0000000000000..dcf8e4960a11b --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + stm32_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..fa7c252e32629 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#ifdef CONFIG_FS_PROCFS +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..fe0a79c175428 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32vldiscovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_0); /* Configure the GPIO pins as inputs. */ + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + ret = (stm32_gpioread(GPIO_BTN_0) == false ? 1 : 0); + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == 0) + { + ret = stm32_gpiosetevent(GPIO_BTN_0, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c new file mode 100644 index 0000000000000..084e383263370 --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32vldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void stm32_led_initialize(void) +{ + stm32_configgpio(GPIO_LED1); /* Configure LED1 GPIO for output */ +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h similarity index 97% rename from boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h index 23898505690f0..d3b3191071251 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h + * boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt new file mode 100644 index 0000000000000..23add80a6ace8 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/Kconfig b/boards/arm/stm32f1/viewtool-stm32f107/Kconfig similarity index 100% rename from boards/arm/stm32/viewtool-stm32f107/Kconfig rename to boards/arm/stm32f1/viewtool-stm32f107/Kconfig diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig new file mode 100644 index 0000000000000..5cfee10bef73b --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_FT80X=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FT80X=y +CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=24 +CONFIG_START_MONTH=2 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig new file mode 100644 index 0000000000000..40363260dd68a --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=22 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART1=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIEWTOOL_HIGHPRI=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig new file mode 100644 index 0000000000000..ff5671048b632 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_ROUTE=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=23 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig new file mode 100644 index 0000000000000..04627a445fcce --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_START_DAY=21 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2009 +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig new file mode 100644 index 0000000000000..0feae7117d368 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="viewtool-stm32f107" +CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y +CONFIG_ARCH_CHIP="stm32f1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TCPBLASTER=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=50 +CONFIG_IOB_NCHAINS=12 +CONFIG_LIBC_HOSTNAME="Viewtool-STM32F107" +CONFIG_LIBM=y +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_ROUTE=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=120 +CONFIG_START_DAY=23 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h index 3fa04fc724078..75e96c764593d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h index 4f88851d81dc5..ac40282bdcc68 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/include/board.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h new file mode 100644 index 0000000000000..dc37787be0cb0 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Clocking *****************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_STM32F107VC) +# include +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) +# include +#else +# error Unrecognized STM32 chip +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* There are four LEDs on the ViewTool STM32F103/F107 board that can be + * controlled by software: LED1 through LED4. All pulled high and can be + * illuminated by driving the output to low + * + * LED1 PA6 + * LED2 PA7 + * LED3 PB12 + * LED4 PB13 + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + */ +#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled ON ON OFF OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON OFF */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C N/C GLOW */ +#define LED_SIGNAL 4 /* In a signal handler N/C N/C N/C GLOW */ +#define LED_ASSERTION 4 /* An assertion failed N/C N/C N/C GLOW */ +#define LED_PANIC 4 /* The system has crashed N/C N/C N/C FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. + */ + +/* Buttons ******************************************************************/ + +/* All pulled high and will be sensed low when depressed. + * + * SW2 PC11 Needs J42 closed + * SW3 PC12 Needs J43 closed + * SW4 PA0 Needs J44 closed + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 +#define BUTTON_SW4 2 +#define NUM_BUTTONS 3 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) +#define BUTTON_SW4_BIT (1 << BUTTON_SW4) + +/* Alternate function pin selections (auto-aliased for new pinmap) */ + +/* USART1 */ + +#define GPIO_USART1_TX GPIO_ADJUST_MODE(GPIO_USART1_TX_0, GPIO_MODE_50MHz) +#define GPIO_USART1_RX GPIO_USART1_RX_0 + +/* SPI1 */ + +#define GPIO_SPI1_NSS GPIO_ADJUST_MODE(GPIO_SPI1_NSS_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_SCK GPIO_ADJUST_MODE(GPIO_SPI1_SCK_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MISO GPIO_ADJUST_MODE(GPIO_SPI1_MISO_0, GPIO_MODE_50MHz) +#define GPIO_SPI1_MOSI GPIO_ADJUST_MODE(GPIO_SPI1_MOSI_0, GPIO_MODE_50MHz) + +/* MCO */ + +#define GPIO_MCO GPIO_ADJUST_MODE(GPIO_MCO_0, GPIO_MODE_50MHz) + +/* Ethernet (MII/RMII) */ + +#define GPIO_ETH_MDC GPIO_ADJUST_MODE(GPIO_ETH_MDC_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MDIO GPIO_ADJUST_MODE(GPIO_ETH_MDIO_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_0 +#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_0 +#define GPIO_ETH_MII_RX_CLK GPIO_ETH_MII_RX_CLK_0 +#define GPIO_ETH_MII_RXD0 GPIO_ETH_MII_RXD0_0 +#define GPIO_ETH_MII_RXD1 GPIO_ETH_MII_RXD1_0 +#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_0 +#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_0 +#define GPIO_ETH_MII_RX_DV GPIO_ETH_MII_RX_DV_0 +#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_0 +#define GPIO_ETH_MII_TX_CLK GPIO_ETH_MII_TX_CLK_0 +#define GPIO_ETH_MII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD2 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD2_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TXD3 GPIO_ADJUST_MODE(GPIO_ETH_MII_TXD3_0, GPIO_MODE_50MHz) +#define GPIO_ETH_MII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_MII_TX_EN_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_CRS_DV GPIO_ETH_RMII_CRS_DV_0 +#define GPIO_ETH_RMII_REF_CLK GPIO_ETH_RMII_REF_CLK_0 +#define GPIO_ETH_RMII_RXD0 GPIO_ETH_RMII_RXD0_0 +#define GPIO_ETH_RMII_RXD1 GPIO_ETH_RMII_RXD1_0 +#define GPIO_ETH_RMII_TXD0 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD0_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TXD1 GPIO_ADJUST_MODE(GPIO_ETH_RMII_TXD1_0, GPIO_MODE_50MHz) +#define GPIO_ETH_RMII_TX_EN GPIO_ADJUST_MODE(GPIO_ETH_RMII_TX_EN_0, GPIO_MODE_50MHz) + +/* TIM6 has no GPIO pins (basic timer) */ + +#endif /* __BOARDS_ARM_STM32_VIEWTOOL_STM32F107_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs new file mode 100644 index 0000000000000..6789123bb8cc6 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = dfu.ld +else + LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld new file mode 100644 index 0000000000000..a83768dd0966d --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld new file mode 100644 index 0000000000000..904f9b611a6de --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt new file mode 100644 index 0000000000000..c801fe9de8713 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c) + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usbdev.c) +else() + if(CONFIG_STM32_USB) + list(APPEND SRCS stm32_usbdev.c) + endif() +endif() + +if(CONFIG_INPUT_ADS7843E) + list(APPEND SRCS stm32_ads7843e.c) +endif() + +if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_VIEWTOOL_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_VIEWTOOL_FT80X_SPI1) + list(APPEND SRCS stm32_ft80x.c) +elseif(CONFIG_VIEWTOOL_FT80X_SPI2) + list(APPEND SRCS stm32_ft80x.c) +endif() + +if(CONFIG_VIEWTOOL_MAX3421E_SPI1) + list(APPEND SRCS stm32_max3421e.c) +elseif(CONFIG_VIEWTOOL_MAX3421E_SPI2) + list(APPEND SRCS stm32_max3421e.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_DFU) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") +endif() diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs new file mode 100644 index 0000000000000..00ba8c4b620c6 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_leds.c stm32_spi.c + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) # F107 +CSRCS += stm32_usbdev.c +else +ifeq ($(CONFIG_STM32_USB),y) # F103 +CSRCS += stm32_usbdev.c +endif +endif + +ifeq ($(CONFIG_INPUT_ADS7843E),y) # F103 +CSRCS += stm32_ads7843e.c +endif + +ifeq ($(CONFIG_LCD_SSD1289),y) # F103 +CSRCS += stm32_ssd1289.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_VIEWTOOL_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI1),y) +CSRCS += stm32_ft80x.c +else ifeq ($(CONFIG_VIEWTOOL_FT80X_SPI2),y) +CSRCS += stm32_ft80x.c +endif + +ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI1),y) +CSRCS += stm32_max3421e.c +else ifeq ($(CONFIG_VIEWTOOL_MAX3421E_SPI2),y) +CSRCS += stm32_max3421e.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c index 99c2c0315eb79..9982aca8aa2bc 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c new file mode 100644 index 0000000000000..a5b6fbb767c25 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbdev_initialize() has been + * brought into the build. + */ + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBDEV) + if (stm32_usbdev_initialize) + { + stm32_usbdev_initialize(); + } +#endif + + /* Configure on-board LEDs (unconditionally). */ + + stm32_led_initialize(); +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c new file mode 100644 index 0000000000000..a8ea0f1113525 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c @@ -0,0 +1,202 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#ifdef CONFIG_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_SENSORS_MPL115A +#include "stm32_mpl115a.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Default MMC/SD SLOT number */ + +#ifdef HAVE_MMCSD +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != VIEWTOOL_MMCSD_SLOTNO +# error "Only one MMC/SD slot: VIEWTOOL_MMCSD_SLOTNO" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO VIEWTOOL_MMCSD_SLOTNO +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_driver_initialize + * + * Description: + * Initialize and register the RTC driver. + * + ****************************************************************************/ + +#ifdef HAVE_RTC_DRIVER +static int rtc_driver_initialize(void) +{ + struct rtc_lowerhalf_s *lower; + int ret; + + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (lower == NULL) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + ret = -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_RTC_DRIVER + ret = rtc_driver_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: rtc_driver_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef HAVE_MMCSD + ret = stm32_sdinitialize(CONFIG_NSH_MMCSDSLOTNO); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_sdinitialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_ADS7843E + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MPL115A + ret = board_mpl115a_initialize(0, 5); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mpl115ainitialize failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) + ret = stm32_ft80x_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) + ret = stm32_max3421e_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ft80x_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c new file mode 100644 index 0000000000000..427e07f6c76d9 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_SW2, GPIO_SW3, GPIO_SW4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for some pins but NOT used in this file + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. The + * exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c new file mode 100644 index 0000000000000..672a1294a2b8d --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The STM32F107VC supports CAN1 and CAN2 */ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c index 59620fcab0fd9..cba254d55703d 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c new file mode 100644 index 0000000000000..d7a113d035b63 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c @@ -0,0 +1,277 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" +#include "stm32_tim.h" + +#include "viewtool_stm32f107.h" + +#include + +#ifdef CONFIG_VIEWTOOL_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_CHIP_STM32F103VC +# warning This only only been verified with CONFIG_ARCH_CHIP_STM32F103VC +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_STM32_TIM6 +# error CONFIG_STM32_TIM6 is required +#endif + +#ifndef CONFIG_VIEWTOOL_TIM6_FREQUENCY +# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_APB1_TIM6_CLKIN +# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#endif + +#ifndef CONFIG_VIEWTOOL_TIM6_PERIOD +# warning CONFIG_VIEWTOOL_TIM6_PERIOD defaulting to 1MS +# define CONFIG_VIEWTOOL_TIM6_PERIOD (CONFIG_VIEWTOOL_TIM6_FREQUENCY / 1000) +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct highpri_s +{ + struct stm32_tim_dev_s *dev; /* TIM6 driver instance */ + volatile uint64_t basepri[16]; + volatile uint64_t handler; + volatile uint64_t thread; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline_function bool is_nesting_interrupt(void) +{ + return up_interrupt_context(); +} + +/**************************************************************************** + * Name: tim6_handler + * + * Description: + * This is the handler for the high speed TIM6 interrupt. + * + ****************************************************************************/ + +void tim6_handler(void) +{ + uint8_t basepri; + int index; + + /* Acknowledge the timer interrupt */ + + STM32_TIM_ACKINT(g_highpri.dev, ATIM_SR_UIF); + + /* Increment the count associated with the current basepri */ + + basepri = getbasepri(); + index = ((basepri >> 4) & 15); + g_highpri.basepri[index]++; + + /* Check if we are in an interrupt handle */ + + if (is_nesting_interrupt()) + { + g_highpri.handler++; + } + else + { + g_highpri.thread++; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ + struct stm32_tim_dev_s *dev; + uint64_t basepri[16]; + uint64_t handler; + uint64_t thread; + uint64_t total; + uint32_t seconds; + int prescaler; + int ret; + int i; + + printf("highpri_main: Started\n"); + + /* Configure basic timer TIM6 and enable interrupts */ + + dev = stm32_tim_init(6); + if (!dev) + { + fprintf(stderr, "highpri_main: ERROR: stm32_tim_init(6) failed\n"); + return EXIT_FAILURE; + } + + g_highpri.dev = dev; + + prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); + printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", + (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, + prescaler); + + STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); + printf("TIM6 period=%d cycles; interrupt rate=%d Hz\n", + CONFIG_VIEWTOOL_TIM6_PERIOD, + CONFIG_VIEWTOOL_TIM6_FREQUENCY / CONFIG_VIEWTOOL_TIM6_PERIOD); + + /* Attach TIM6 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + return EXIT_FAILURE; + } + + /* Set the priority of the TIM6 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + return EXIT_FAILURE; + } + + /* Enable the timer interrupt at the NVIC and at TIM6 */ + + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(dev, ATIM_DIER_UIE); + + /* Monitor interrupts */ + + seconds = 0; + for (; ; ) + { + /* Flush stdout and wait a bit */ + + fflush(stdout); + nxsched_sleep(1); + seconds++; + + /* Sample counts so that they are not volatile. Missing a count now + * and then is a normal consequence of this design. + */ + + for (i = 0; i < 16; i++) + { + basepri[i] = g_highpri.basepri[i]; + } + + handler = g_highpri.handler; + thread = g_highpri.thread; + + /* Then print out what is happening */ + + printf("Elapsed time: %" PRId32 " seconds\n\n", seconds); + for (i = 0, total = 0; i < 16; i++) + { + total += basepri[i]; + } + + if (total > 0) + { + for (i = 0; i < 16; i++) + { + if (basepri[i] > 0) + { + printf(" basepri[%02x]: %lld (%d%%)\n", + i << 4, basepri[i], + (int)((100 * basepri[i] + (total / 2)) / total)); + } + } + } + + total = handler + thread; + if (total > 0) + { + printf(" Handler: %lld (%d%%)\n", + handler, (int)((100*handler + (total / 2)) / total)); + printf(" Thread: %lld (%d%%)\n\n", + thread, (int)((100*thread + (total / 2)) / total)); + } + } + + return EXIT_SUCCESS; +} + +#endif /* CONFIG_VIEWTOOL_HIGHPRI */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c new file mode 100644 index 0000000000000..51573cbff7560 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c @@ -0,0 +1,280 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_onbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_onbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +/**************************************************************************** + * Name: led_offbits + * + * Description: + * Clear all LEDs to the bit encoded state + * + ****************************************************************************/ + +static void led_offbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + * + * Description: + * Configure LEDs. LEDs are left in the OFF state. + * + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + /* Configure LED1-4 GPIOs for output. Initial state is OFF */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Select the "logical" ON state: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + * LED_STARTED 0 NuttX has been started ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF + * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW + * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW + * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW + * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH + * ED_IDLE MCU is in sleep mode Not used + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_on(int led) +{ + switch (led) + { + case 0: + led_offbits(BOARD_LED2_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED1_BIT); + break; + + case 1: + led_offbits(BOARD_LED1_BIT | BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED2_BIT); + break; + + case 2: + led_offbits(BOARD_LED3_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED1_BIT | BOARD_LED2_BIT); + break; + + case 3: + led_offbits(BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED4_BIT); + led_onbits(BOARD_LED3_BIT); + break; + + case 4: + stm32_gpiowrite(GPIO_LED4, false); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Select the "logical" OFF state: + * + * SYMBOL Val Meaning LED state + * LED1 LED2 LED3 LED4 + * ----------------- --- ----------------------- ---- ---- ---- ---- + * LED_STARTED 0 NuttX has been started ON OFF OFF OFF + * LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF + * LED_IRQSENABLED 2 Interrupts enabled ON ON OFF OFF + * LED_STACKCREATED 3 Idle stack created OFF OFF ON OFF + * LED_INIRQ 4 In an interrupt N/C N/C N/C GLOW + * LED_SIGNAL 4 In a signal handler N/C N/C N/C GLOW + * LED_ASSERTION 4 An assertion failed N/C N/C N/C GLOW + * LED_PANIC 4 The system has crashed N/C N/C N/C FLASH + * ED_IDLE MCU is in sleep mode Not used + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_off(int led) +{ + switch (led) + { + case 0: + case 1: + case 2: + case 3: + break; + + case 4: + stm32_gpiowrite(GPIO_LED4, true); + break; + } +} +#endif + +/**************************************************************************** + * Name: board_userled_initialize, board_userled, and board_userled_all + * + * Description: + * These interfaces allow user control of the board LEDs. + * + * If CONFIG_ARCH_LEDS is defined, then NuttX will control both on-board + * LEDs up until the completion of boot. The it will continue to control + * LED2; LED1 is available for application use. + * + * If CONFIG_ARCH_LEDS is not defined, then both LEDs are available for + * application use. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Already initialized by stm32_led_initialize */ + + return BOARD_NLEDS; +} + +void board_userled(int led, bool ledon) +{ + uint32_t pinset; + + switch (led) + { + case BOARD_LED1: + pinset = GPIO_LED1; + break; + + case BOARD_LED2: + pinset = GPIO_LED2; + break; + + case BOARD_LED3: + pinset = GPIO_LED3; + break; + + case BOARD_LED4: +#ifndef CONFIG_ARCH_LEDS + pinset = GPIO_LED4; + break; +#endif + default: + return; + } + + stm32_gpiowrite(pinset, !ledon); +} + +void board_userled_all(uint32_t ledset) +{ +#ifdef CONFIG_ARCH_LEDS + led_onbits(ledset & ~BOARD_LED4_BIT); + led_offbits(~(ledset | BOARD_LED4_BIT)); +#else + led_onbits(ledset); + led_offbits(~ledset); +#endif +} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c index b7b6d1053be83..f397f0925237b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..318d2badb5409 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_sdio.h" +#include "viewtool_stm32f107.h" + +/* Only the STM32F103 supports the SDIO interface */ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_MMCSD 1 /* Assume that we have SD support */ +#define STM32_MMCSDSLOTNO 0 /* There is only one slot */ + +/* Can't support MMC/SD features if the SDIO peripheral is disabled */ + +#ifndef CONFIG_STM32_SDIO +# undef HAVE_MMCSD +#endif + +/* Can't support MMC/SD features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_MMCSD +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdinitialize + * + * Description: + * Initialize the SPI-based SD card. Requires CONFIG_DISABLE_MOUNTPOINT=n + * and CONFIG_STM32_SDIO=y + * + ****************************************************************************/ + +int stm32_sdinitialize(int minor) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; + int ret; + + /* Configure the card-detect GPIO */ +#warning REVISIT: Missing logic + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(STM32_MMCSDSLOTNO); + if (!sdio) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", STM32_MMCSDSLOTNO); + return -ENODEV; + } + + finfo("Initialized SDIO slot %d\n", STM32_MMCSDSLOTNO); + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(minor, sdio); + if (ret != OK) + { + ferr("ERROR:"); + ferr("Failed to bind SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + } + + finfo("Bound SDIO slot %d to the MMC/SD driver, minor=%d\n", + STM32_MMCSDSLOTNO, minor); + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the M3 Wildfire board supports a GPIO to detect if there + * is a card in the slot. + */ +#warning REVISIT: Need to read the current state of the card-detect pin +#warning REVISIT: Need to support interrupts from the card-detect pin + sdio_mediachange(sdio, true); +#endif + return OK; +} + +#endif /* CONFIG_ARCH_CHIP_STM32F103VC */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c new file mode 100644 index 0000000000000..04ec48f81d2d8 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c @@ -0,0 +1,210 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "viewtool_stm32f107.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Viewtool + * stm32f103/107 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPIx was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_INPUT_ADS7843E) + /* Configure the XPT2046 SPI2 CS pin as an output */ + + stm32_configgpio(GPIO_LCDTP_CS); +#endif + +#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_SENSORS_MPL115A) + /* Configure the MPL115A SPI3 CS pin as an output */ + + stm32_configgpio(GPIO_MPL115A_CS); +#endif + +#if defined(CONFIG_VIEWTOOL_FT80X_SPI1) || defined(CONFIG_VIEWTOOL_FT80X_SPI2) + /* Configure the FT80x CS pin as an input */ + + stm32_configgpio(GPIO_FT80X_CS); +#endif + +#if defined(CONFIG_VIEWTOOL_MAX3421E_SPI1) || defined(CONFIG_VIEWTOOL_MAX3421E_SPI2) + /* Configure the MAX3421E CS pin as an input */ + + stm32_configgpio(GPIO_MAX3421E_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_VIEWTOOL_FT80X_SPI1 + /* Select/de-select the FT80x */ + + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_FT80X_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI1 + /* Select/de-select the MAX3421E */ + + if (devid == SPIDEV_USBHOST(0)) + { + stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); + } + else +#endif + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_INPUT_ADS7843E + /* Select/de-select the touchscreen */ + + if (devid == SPIDEV_TOUCHSCREEN(0)) + { + stm32_gpiowrite(GPIO_LCDTP_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_FT80X_SPI2 + /* Select/de-select the FT80x */ + + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_FT80X_CS, !selected); + } + else +#endif +#ifdef CONFIG_VIEWTOOL_MAX3421E_SPI2 + /* Select/de-select the MAX3421E */ + + if (devid == SPIDEV_USBHOST(0)) + { + stm32_gpiowrite(GPIO_MAX3421E_CS, !selected); + } + else +#endif + { + spierr("ERROR: Unrecognized devid: %08lx\n", (unsigned long)devid); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3*/ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..4d80b05f9d86f --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c @@ -0,0 +1,568 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "viewtool_stm32f107.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* Color depth and format */ + +#define LCD_BPP 16 +#define LCD_COLORFMT FB_FMT_RGB16_565 + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) +# define LCD_XRES 320 +# define LCD_YRES 240 +#else +# define LCD_XRES 240 +# define LCD_YRES 320 +#endif + +#define LCD_BL_TIMER_PERIOD 8999 + +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as chip + * select signal + */ + +/* RS <==> A16 */ + +#define LCD_INDEX 0x60000000 /* RS = 0 */ +#define LCD_DATA 0x60020000 /* RS = 1 */ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LCD + * + * An LCD may be connected via J11. Only the STM32F103 supports the FSMC + * signals needed to drive the LCD. + * + * The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, + * and (a) a XPT2046 touch screen controller. + * + * LCD Connector + * ------------- + * + * ------------------------- --------------------- --------------- + * Connector J11 GPIO CONFIGURATION(s) + * PIN SIGNAL LEGEND (F103 only) LCD Module + * --- --------- ----------- --------------------- --------------- + * 1 VDD_5 NC N/A 5V --- + * 2 GND GND N/A GND --- + * 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D + * 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D + * 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D + * 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D + * 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D + * 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D + * 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D + * 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D + * 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D + * 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D + * 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D + * 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D + * 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D + * 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D + * 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D + * 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D + * 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D + * 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D + * 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D + * 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D + * 23 PB1 LCD_RESET (GPIO) RESET HY32D + * 24 N/C NC N/A TE (unused?) + * 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 + * (Drives LCD backlight) + * 26 GND BL_GND N/A BLGND CA6219 + * 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219 + * 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046 + * 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046 + * 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046 + * 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046 + * 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046 + * 33 VDD_3.3 VDD_3.3 N/A 3.3V --- + * 34 GND GND N/A GND --- + * --- --------- ----------- --------------------- --------------- + * + * NOTES: + * 1) Only the F103 version of the board supports the FSMC + * 2) No remap + * 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately): + * + * 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input + * (active LOW) + * 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input + * So will chip enable to either LCD_CS or + * Flash_CS. + * 5->6 : 1Y0 output to LCD_CS : 1Y0 address output + * 7->8 : 1Y1 output to Flash_CE : 1Y1 address output + * + * Truth Table: + * 1E\ 1A0 1A1 1Y0 1Y1 + * --- --- --- --- --- + * HI N/A N/A HI HI + * LO LO LO LO HI + * LO HI LO HI LO + */ + +const uint16_t fsmc_gpios[] = +{ + /* A16... A23. REVISIT: only A16 is used by the LCD */ + + GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18, GPIO_NPS_A19, GPIO_NPS_A20, + GPIO_NPS_A21, GPIO_NPS_A22, GPIO_NPS_A23, + + /* D0... D15 */ + + GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, GPIO_NPS_D4, + GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, + GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, + GPIO_NPS_D15, + + /* NOE, NWE, and NE1 */ + + GPIO_NPS_NOE, GPIO_NPS_NWE, GPIO_NPS_NE1 +}; + +#define NGPIOS (sizeof(fsmc_gpios)/sizeof(uint16_t)) + +/* This is the driver state structure */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_index + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_backlight + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). + * Used here to set pwm duty on timer used for backlight. + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ + DEBUGASSERT(power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + uint32_t duty; + + /* Calculate the new backlight duty. It is a fraction of the timer + * period based on the ration of the current power setting to the + * maximum power setting. + */ + + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * + (uint32_t)power) / CONFIG_LCD_MAXPOWER; + if (duty >= LCD_BL_TIMER_PERIOD) + { + duty = LCD_BL_TIMER_PERIOD - 1; + } + + putreg16((uint16_t)duty, STM32_TIM3_CCR2); + } + else + { + putreg16((uint16_t)0, STM32_TIM3_CCR2); + } +} + +static void init_lcd_backlight(void) +{ + uint16_t ccmr; + uint16_t ccer; + + /* Configure PB5 as TIM3 CH2 output */ + + stm32_configgpio(GPIO_TIM3_CH2OUT); + + /* Enable timer 3 clocking */ + + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + + /* Reset timer 3 */ + + modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_TIM3RST); + modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST, 0); + + /* Reset the Counter Mode and set the clock division */ + + putreg16(0, STM32_TIM3_CR1); + + /* Set the Autoreload value */ + + putreg16(LCD_BL_TIMER_PERIOD, STM32_TIM3_ARR); + + /* Set the Prescaler value */ + + putreg16(0, STM32_TIM3_PSC); + + /* Generate an update event to reload the Prescaler value immediately */ + + putreg16(ATIM_EGR_UG, STM32_TIM3_EGR); + + /* Disable the Channel 2 */ + + ccer = getreg16(STM32_TIM3_CCER); + ccer &= ~ATIM_CCER_CC2E; + putreg16(ccer, STM32_TIM3_CCER); + + /* Select the Output Compare Mode Bits */ + + ccmr = getreg16(STM32_TIM3_CCMR1); + ccmr &= ATIM_CCMR1_OC2M_MASK; + ccmr |= (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT); + + putreg16(0, STM32_TIM3_CCR2); + + /* Select the output polarity level == HIGH */ + + ccer &= ~ATIM_CCER_CC2P; + + /* Enable channel 2 */ + + ccer |= ATIM_CCER_CC2E; + + /* Write the timer configuration */ + + putreg16(ccmr, STM32_TIM3_CCMR1); + putreg16(ccer, STM32_TIM3_CCER); + + /* Set the auto preload enable bit */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); + + /* Enable Backlight Timer !!!! */ + + modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); + + /* Dump timer3 registers */ + + lcdinfo("APB1ENR: %08x\n", getreg32(STM32_RCC_APB1ENR)); + lcdinfo("CR1: %04x\n", getreg32(STM32_TIM3_CR1)); + lcdinfo("CR2: %04x\n", getreg32(STM32_TIM3_CR2)); + lcdinfo("SMCR: %04x\n", getreg32(STM32_TIM3_SMCR)); + lcdinfo("DIER: %04x\n", getreg32(STM32_TIM3_DIER)); + lcdinfo("SR: %04x\n", getreg32(STM32_TIM3_SR)); + lcdinfo("EGR: %04x\n", getreg32(STM32_TIM3_EGR)); + lcdinfo("CCMR1: %04x\n", getreg32(STM32_TIM3_CCMR1)); + lcdinfo("CCMR2: %04x\n", getreg32(STM32_TIM3_CCMR2)); + lcdinfo("CCER: %04x\n", getreg32(STM32_TIM3_CCER)); + lcdinfo("CNT: %04x\n", getreg32(STM32_TIM3_CNT)); + lcdinfo("PSC: %04x\n", getreg32(STM32_TIM3_PSC)); + lcdinfo("ARR: %04x\n", getreg32(STM32_TIM3_ARR)); + lcdinfo("CCR1: %04x\n", getreg32(STM32_TIM3_CCR1)); + lcdinfo("CCR2: %04x\n", getreg32(STM32_TIM3_CCR2)); + lcdinfo("CCR3: %04x\n", getreg32(STM32_TIM3_CCR3)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("CCR4: %04x\n", getreg32(STM32_TIM3_CCR4)); + lcdinfo("DMAR: %04x\n", getreg32(STM32_TIM3_DMAR)); +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize the memory controller (FSMC) + * + ****************************************************************************/ + +static void stm32_selectlcd(void) +{ + /* Configure new GPIO state */ + + stm32_extmemgpios(fsmc_gpios, NGPIOS); + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32( + FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, + STM32_FSMC_BTR1); + + /* As ext mode is not active the write timing is ignored!! */ + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, + STM32_FSMC_BCR1); + + /* Configure the LCD RESET pin. + * Initial value will take the LCD out of reset + */ + + stm32_configgpio(GPIO_LCD_RESET); +} + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for NOR or SRAM + * + ****************************************************************************/ + +static void stm32_extmemgpios(const uint16_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + /* Initialize the backlight */ + + init_lcd_backlight(); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c new file mode 100644 index 0000000000000..c94e99e18cdaa --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_otgfs.h" +#include "viewtool_stm32f107.h" + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_USB) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbdev_initialize + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB related GPIO pins for the Viewtool STM32F107 board. + * + ****************************************************************************/ + +void stm32_usbdev_initialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC + stm32_configgpio(GPIO_USB_PULLUP); +#endif +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional + * description of this method. Alternatively, if no pull-up GPIO the + * following EXTERN can be redefined to be NULL. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_CHIP_STM32F103VC +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + stm32_gpiowrite(GPIO_USB_PULLUP, !enable); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} + +#endif /* CONFIG_STM32_OTGFS || CONFIG_STM32_USB*/ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..2a2d8f2984798 --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "viewtool_stm32f107.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 VIEWTOOL_MMCSD_SLOTNO +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#if defined(HAVE_MMCSD) && !defined(CONFIG_NSH_BUILTIN_APPS) + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h rename to boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h index be6c8199aff3c..35c858e0a753a 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h + * boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/common/CMakeLists.txt b/boards/arm/stm32f2/common/CMakeLists.txt new file mode 100644 index 0000000000000..ada7f1b5fc03f --- /dev/null +++ b/boards/arm/stm32f2/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f2/common/Kconfig b/boards/arm/stm32f2/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f2/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f2/common/Makefile b/boards/arm/stm32f2/common/Makefile new file mode 100644 index 0000000000000..2b5f1ae16b15d --- /dev/null +++ b/boards/arm/stm32f2/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f2/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f2/emw3162/CMakeLists.txt b/boards/arm/stm32f2/emw3162/CMakeLists.txt new file mode 100644 index 0000000000000..3ae13f51fc402 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/emw3162/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/emw3162/Kconfig b/boards/arm/stm32f2/emw3162/Kconfig similarity index 100% rename from boards/arm/stm32/emw3162/Kconfig rename to boards/arm/stm32f2/emw3162/Kconfig diff --git a/boards/arm/stm32f2/emw3162/configs/nsh/defconfig b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig new file mode 100644 index 0000000000000..ba23a8e0b0ec9 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/emw3162/configs/wlan/defconfig b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig new file mode 100644 index 0000000000000..a623c00de3555 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig @@ -0,0 +1,83 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="emw3162" +CONFIG_ARCH_BOARD_EMW3162=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EMW3162_WLAN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=800 +CONFIG_NET_GUARDSIZE=32 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_SDIO_PULLUP=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/emw3162/include/board.h b/boards/arm/stm32f2/emw3162/include/board.h new file mode 100644 index 0000000000000..04fe380ce64ce --- /dev/null +++ b/boards/arm/stm32f2/emw3162/include/board.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The EMW3162 board features a single 26MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) + * PLLM : 26 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG HS : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 26MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 26000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (26,000,000 / 26) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* Thus if LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Alternate function pin selections ****************************************/ + +/* UART1 */ + +#ifdef CONFIG_STM32_USART1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) +#endif + +/* MCO1 */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* SDIO definitions *********************************************************/ + +/* Note that slower clocking is required when DMA is disabled in order + * to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * + * These values have not been tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_EMW3162_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/emw3162/scripts/Make.defs b/boards/arm/stm32f2/emw3162/scripts/Make.defs new file mode 100644 index 0000000000000..0f1c1fb18ddc2 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/emw3162/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -Wl,-d -Wl,-warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -Wl,-no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/emw3162/scripts/ld.script b/boards/arm/stm32f2/emw3162/scripts/ld.script new file mode 100644 index 0000000000000..6728bf250c633 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/scripts/ld.script @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F205RG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 112Kb of SRAM in main SRAM1 and 16 Kb in auxiliary SRAM2. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + + wlan_firmware_image_location = .; + *(.wlan_firmware_image .wlan_firmware_image.*) + wlan_firmware_image_end = .; + + wlan_nvram_image_location = .; + *(.wlan_nvram_image .wlan_nvram_image.*) + wlan_nvram_image_end = .; + + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/emw3162/src/CMakeLists.txt b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt new file mode 100644 index 0000000000000..74410fcc34ea8 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt @@ -0,0 +1,38 @@ +# ############################################################################## +# boards/arm/stm32f2/emw3162/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_EMW3162_WLAN) + list(APPEND SRCS stm32_wlan.c) + list(APPEND SRCS stm32_wlan_firmware.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/emw3162/src/Make.defs b/boards/arm/stm32f2/emw3162/src/Make.defs new file mode 100644 index 0000000000000..1cd6ec0b13d29 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32f2/emw3162/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_EMW3162_WLAN),y) +CSRCS += stm32_wlan.c +CSRCS += stm32_wlan_firmware.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/emw3162/src/emw3162.h b/boards/arm/stm32f2/emw3162/src/emw3162.h similarity index 98% rename from boards/arm/stm32/emw3162/src/emw3162.h rename to boards/arm/stm32f2/emw3162/src/emw3162.h index 6142ab2310eed..2930b3292652f 100644 --- a/boards/arm/stm32/emw3162/src/emw3162.h +++ b/boards/arm/stm32f2/emw3162/src/emw3162.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/emw3162.h + * boards/arm/stm32f2/emw3162/src/emw3162.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c new file mode 100644 index 0000000000000..e385fbbbd863b --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ----------------------- ------ + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "emw3162.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_boot.c b/boards/arm/stm32f2/emw3162/src/stm32_boot.c new file mode 100644 index 0000000000000..afed8722823e4 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_boot.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + stm32_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_bringup.c b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c new file mode 100644 index 0000000000000..f78b630f1385d --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "emw3162.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * This function initializes and configures all on-board features + * appropriate for the selected configuration. + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_EMW3162_WLAN + /* Initialize wlan driver and hardware */ + + ret = emw3162_wlan_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f2/emw3162/src/stm32_userleds.c b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c new file mode 100644 index 0000000000000..51cadf4321bb9 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "emw3162.h" + +#include "stm32_gpio.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure EMW3162 LED gpio as output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c new file mode 100644 index 0000000000000..ff0e8ccaf1de5 --- /dev/null +++ b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f2/emw3162/src/stm32_wlan.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_sdio.h" + +#include "emw3162.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bcmf_board_reset + ****************************************************************************/ + +void bcmf_board_reset(int minor, bool reset) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); +} + +/**************************************************************************** + * Name: bcmf_board_power + ****************************************************************************/ + +void bcmf_board_power(int minor, bool power) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_PWRDN, !power); +} + +/**************************************************************************** + * Name: bcmf_board_initialize + ****************************************************************************/ + +void bcmf_board_initialize(int minor) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure MCO1 output to drive EXT_SLEEP_CLK input pin of BCM43362 */ + + stm32_configgpio(GPIO_MCO1); + stm32_mco1config(RCC_CFGR_MCO1_LSE, RCC_CFGR_MCO1PRE_NONE); + + /* Configure PowerDown pin */ + + stm32_configgpio(GPIO_WLAN0_PWRDN); + + /* Shutdown wlan chip */ + + bcmf_board_power(minor, false); + + /* Configure reset pin */ + + stm32_configgpio(GPIO_WLAN0_RESET); + + /* Put wlan chip in reset state */ + + bcmf_board_reset(minor, true); +} + +/**************************************************************************** + * Name: bcmf_board_setup_oob_irq + ****************************************************************************/ + +void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure SDIO card in-band interrupt callback */ + + if (g_sdio_dev != NULL) + { + sdio_set_sdio_card_isr(g_sdio_dev, func, arg); + } +} + +/**************************************************************************** + * Name: bcmf_board_etheraddr + ****************************************************************************/ + +bool bcmf_board_etheraddr(struct ether_addr *ethaddr) +{ + return false; +} + +/**************************************************************************** + * Name: emw3162_wlan_initialize + ****************************************************************************/ + +int emw3162_wlan_initialize() +{ + int ret; + + /* Initialize sdio interface */ + + wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); + + if (!g_sdio_dev) + { + wlerr("ERROR: Failed to initialize SDIO with slot %d\n", + SDIO_WLAN0_SLOTNO); + return ERROR; + } + + /* Bind the SDIO interface to the bcmf driver */ + + ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); + + if (ret != OK) + { + wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); + + /* FIXME deinitialize sdio device */ + + return ERROR; + } + + return OK; +} diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c similarity index 100% rename from boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c diff --git a/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt new file mode 100644 index 0000000000000..4f4af60fbffd3 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/Kconfig b/boards/arm/stm32f2/nucleo-f207zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f207zg/Kconfig rename to boards/arm/stm32f2/nucleo-f207zg/Kconfig diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig new file mode 100644 index 0000000000000..53b10cb1c268e --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig new file mode 100644 index 0000000000000..2679b5c5e8b9f --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig @@ -0,0 +1,38 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig new file mode 100644 index 0000000000000..04c5b15c5027e --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_PWM=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/nucleo-f207zg/include/board.h b/boards/arm/stm32f2/nucleo-f207zg/include/board.h new file mode 100644 index 0000000000000..62f9ed1e30ef6 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/include/board.h @@ -0,0 +1,209 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = + * PLL input clock frequency / PLLM, 2 <= PLLM <= 63 + * VCO output frequency = + * VCO input frequency × PLLN, 50 <= PLLN <= 432 + * PLL output clock frequency = + * VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = + * VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 2) * 100 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 4 = 100,000,000 + * RNG Clock + * = PLL_VCO / PLLQ + * = 400,000,000 / 8 = 50,000,000 + * + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(100) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 100000000ul + +/* AHB clock (HCLK) is SYSCLK (100MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timers driven from APB1 will be twice PCLK1 (50MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Button definitions *******************************************************/ + +/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. A high value will be sensed when the button is + * depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART3 (Nucleo Virtual Console) */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F207ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs new file mode 100644 index 0000000000000..63f3a3eb5cedf --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script new file mode 100644 index 0000000000000..5ea1a69efb101 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207ZG has 1Mb of FLASH beginning at address 0x0800:0000, + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1M + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt new file mode 100644 index 0000000000000..06e696f957093 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs new file mode 100644 index 0000000000000..71bb086e05788 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f2/nucleo-f207zg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h rename to boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h index c6d2497a86498..26ec0f5cb0903 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h +++ b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h + * boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c new file mode 100644 index 0000000000000..3e2a2c19e32aa --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 3, + 10, + 13 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN3_0, /* PA3/A0 */ + GPIO_ADC1_IN10_0, /* PC0/A1 */ + GPIO_ADC1_IN13_0, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN9_0, /* PF3/A3 */ + GPIO_ADC3_IN15_0, /* PF5/A4 */ + GPIO_ADC3_IN8_0, /* PF10/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN9_0, /* PF3/A3 */ + GPIO_ADC3_IN15_0, /* PF5/A4 */ + GPIO_ADC3_IN8_0, /* PF10/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c new file mode 100644 index 0000000000000..10db82a159ec9 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c new file mode 100644 index 0000000000000..5828a05c690c6 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "nucleo-f207zg.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) + /* Initialize USB */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c new file mode 100644 index 0000000000000..1927f3bca09be --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "nucleo-f207zg.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + syslog(LOG_INFO, "Initialize CDCACM device\n"); + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c new file mode 100644 index 0000000000000..8638a37a4b613 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c new file mode 100644 index 0000000000000..a43f95dc57e24 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f207zg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF207ZG_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c new file mode 100644 index 0000000000000..6d3390be492aa --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otgfs.h" +#include "nucleo-f207zg.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEOF207ZG_USBHOST_PRIO +# define CONFIG_NUCLEOF207ZG_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE +# define CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_NUCLEOF207ZG_USBHOST_PRIO, + CONFIG_NUCLEOF207ZG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c new file mode 100644 index 0000000000000..7ee325e6000c9 --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f207zg.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt new file mode 100644 index 0000000000000..f2381912c114f --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/Kconfig b/boards/arm/stm32f2/olimex-stm32-p207/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p207/Kconfig rename to boards/arm/stm32f2/olimex-stm32-p207/Kconfig diff --git a/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig new file mode 100644 index 0000000000000..d74bd22eb862f --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p207" +CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZE=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DRIPADDR=0xa0000001 +CONFIG_NETINIT_IPADDR=0xa0000002 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG2=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y diff --git a/boards/arm/stm32f2/olimex-stm32-p207/include/board.h b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h new file mode 100644 index 0000000000000..7ad51256922fb --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN1 BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_GREEN2 BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the Olimex STM32-P207. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-P207 supports seven buttons: */ + +#define BUTTON_TAMPER 0 +#define BUTTON_WKUP 1 +#define BUTTON_RIGHT 2 +#define BUTTON_UP 3 +#define BUTTON_LEFT 4 +#define BUTTON_DOWN 5 +#define BUTTON_CENTER 6 + +#define NUM_BUTTONS 7 + +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) +#define BUTTON_RIGHT_BIT (1 << BUTTON_RIGHT) +#define BUTTON_UP_BIT (1 << BUTTON_UP) +#define BUTTON_LEFT_BIT (1 << BUTTON_LEFT) +#define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) +#define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ + +/* CAN: */ +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* Ethernet: */ + +/* - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT - NC (not connected) + * - PA0 is ETH_MII_CRS - NC + * - PA3 is ETH_MII_COL - NC + * - PB10 is ETH_MII_RX_ER - NC + * - PB0 is ETH_MII_RXD2 - NC + * - PH7 is ETH_MII_RXD3 - NC + * - PC3 is ETH_MII_TX_CLK - NC + * - PC2 is ETH_MII_TXD2 - NC + * - PB8 is ETH_MII_TXD3 - NC + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P207_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs new file mode 100644 index 0000000000000..d8143a48feef7 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script new file mode 100644 index 0000000000000..b658404f87cdc --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207ZET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt new file mode 100644 index 0000000000000..1f6060c53a7c4 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs new file mode 100644 index 0000000000000..f506294680bc3 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h rename to boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h index 5f69d7f4934bd..30f8489f63342 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h + * boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c new file mode 100644 index 0000000000000..4c75b624f493e --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P207 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10_0 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a748ff57c4c23 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LED_STARTED_BITS (BOARD_LED1_BIT) +#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) +#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) +#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) +#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) +#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_PANIC_BITS (BOARD_LED4_BIT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const unsigned int g_ledbits[8] = +{ + LED_STARTED_BITS, + LED_HEAPALLOCATE_BITS, + LED_IRQSENABLED_BITS, + LED_STACKCREATED_BITS, + LED_INIRQ_BITS, + LED_SIGNAL_BITS, + LED_ASSERTION_BITS, + LED_PANIC_BITS +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); + led_setbits(g_ledbits[led]); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_clrbits(g_ledbits[led]); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c new file mode 100644 index 0000000000000..1fee37320cfcf --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-p207.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_STM32_USBHOST +# undef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c new file mode 100644 index 0000000000000..20089fe607e81 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_TAMPER, + GPIO_BTN_WKUP, + GPIO_BTN_RIGHT, + GPIO_BTN_UP, + GPIO_BTN_LEFT, + GPIO_BTN_DOWN, + GPIO_BTN_CENTER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) + { + ret |= BUTTON_TAMPER_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_WKUP])) + { + ret |= BUTTON_WKUP_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_RIGHT])) + { + ret |= BUTTON_RIGHT_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_UP])) + { + ret |= BUTTON_UP_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_LEFT])) + { + ret |= BUTTON_LEFT_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_DOWN])) + { + ret |= BUTTON_DOWN_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_CENTER])) + { + ret |= BUTTON_CENTER_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c new file mode 100644 index 0000000000000..f64cb2f25b3e6 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c new file mode 100644 index 0000000000000..3931c992d829b --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c @@ -0,0 +1,313 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-p207.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c new file mode 100644 index 0000000000000..b552c74f23790 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-p207.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/photon/CMakeLists.txt b/boards/arm/stm32f2/photon/CMakeLists.txt new file mode 100644 index 0000000000000..425a22bcb9f1e --- /dev/null +++ b/boards/arm/stm32f2/photon/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/photon/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/photon/Kconfig b/boards/arm/stm32f2/photon/Kconfig similarity index 100% rename from boards/arm/stm32/photon/Kconfig rename to boards/arm/stm32f2/photon/Kconfig diff --git a/boards/arm/stm32f2/photon/configs/adb/defconfig b/boards/arm/stm32f2/photon/configs/adb/defconfig new file mode 100644 index 0000000000000..08ea7b3596958 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/adb/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ADBD_AUTHENTICATION=y +CONFIG_ADBD_AUTH_PUBKEY=y +CONFIG_ADBD_DEVICE_ID="serialno" +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_LOGCAT_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_URANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="adbd_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=2048 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/stm32f2/photon/configs/nsh/defconfig b/boards/arm/stm32f2/photon/configs/nsh/defconfig new file mode 100644 index 0000000000000..e5d1d5b3b9c33 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f2/photon/configs/rgbled/defconfig b/boards/arm/stm32f2/photon/configs/rgbled/defconfig new file mode 100644 index 0000000000000..dc5e7d9718c03 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/rgbled/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=8192 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RGBLED_INVERT=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CH3OUT=y +CONFIG_STM32_TIM2_CH4OUT=y +CONFIG_STM32_TIM2_CHANNEL2=y +CONFIG_STM32_TIM2_CHANNEL3=y +CONFIG_STM32_TIM2_CHANNEL4=y +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f2/photon/configs/usbnsh/defconfig b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..d364c6b0c33fd --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig new file mode 100644 index 0000000000000..d763e1d77aac2 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DFU_BASE=0x8020000 +CONFIG_DFU_BINARY=y +CONFIG_DFU_PID=0xd006 +CONFIG_DFU_VID=0x2b04 +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=32 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PHOTON_WLAN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/photon/configs/wlan/defconfig b/boards/arm/stm32f2/photon/configs/wlan/defconfig new file mode 100644 index 0000000000000..98f29fac9ed95 --- /dev/null +++ b/boards/arm/stm32f2/photon/configs/wlan/defconfig @@ -0,0 +1,101 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_IEEE80211_BROADCOM_FWFILES is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="photon" +CONFIG_ARCH_BOARD_PHOTON=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DFU_BASE=0x8020000 +CONFIG_DFU_BINARY=y +CONFIG_DFU_PID=0xd006 +CONFIG_DFU_VID=0x2b04 +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE80211_BROADCOM_BCM43362=y +CONFIG_IEEE80211_BROADCOM_DMABUF_ALIGNMENT=16 +CONFIG_IEEE80211_BROADCOM_FRAME_POOL_SIZE=16 +CONFIG_IEEE80211_BROADCOM_FULLMAC_SDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y +CONFIG_MM_REGIONS=2 +CONFIG_NDEBUG=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1518 +CONFIG_NET_GUARDSIZE=32 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_PKT=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PHOTON_DFU_BOOTLOADER=y +CONFIG_PHOTON_IWDG=y +CONFIG_PHOTON_WDG_THREAD=y +CONFIG_PHOTON_WLAN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA2=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_PROCESSID=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y diff --git a/boards/arm/stm32f2/photon/include/board.h b/boards/arm/stm32f2/photon/include/board.h new file mode 100644 index 0000000000000..a26b8826bffae --- /dev/null +++ b/boards/arm/stm32f2/photon/include/board.h @@ -0,0 +1,311 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Particle photon board features a single 26MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 26000000 (STM32_BOARD_XTAL) + * PLLM : 26 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG HS : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 26MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 26000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (26,000,000 / 26) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(26) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* USB OTG HS definitions ***************************************************/ + +/* Do not enable external PHY clock or OTG_HS module will not work */ + +#undef BOARD_ENABLE_USBOTG_HSULPI + +/* LED definitions **********************************************************/ + +/* LEDs + * + * A single LED is available driven by PA13. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ---------------------------- ------ + * SYMBOL Meaning LED + * ------------------- ---------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* MCU is in sleep mode Not used */ + +/* Thus if LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) + +/* RGB LED + * + * R = TIM2 CH2 on PA1 | G = TIM2 CH3 on PA2 | B = TIM4 CH4 on PA3 + * + * Note: Pin boards: GPIO_TIM2_CH2OUT ; GPIO_TIM2_CH3OUT ; GPIO_TIM2_CH4OUT + */ + +#define RGBLED_RPWMTIMER 2 +#define RGBLED_RPWMCHANNEL 2 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 3 +#define RGBLED_BPWMTIMER 2 +#define RGBLED_BPWMCHANNEL 4 + +/* Button definitions *******************************************************/ + +#define BOARD_BUTTON1 0 +#define NUM_BUTTONS 1 +#define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) + +/* Alternate function pin selections ****************************************/ + +/* UART1 */ + +#ifdef CONFIG_STM32_USART1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) +#endif + +/* SPI1 */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ + +/* SPI3 */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) /* PB3 */ + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* OTG HS */ + +#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 +#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 + +/* SDIO definitions *********************************************************/ + +/* Note that slower clocking is required when DMA is disabled in order + * to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. + * + * These values have not been tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_PHOTON_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/photon/scripts/Make.defs b/boards/arm/stm32f2/photon/scripts/Make.defs new file mode 100644 index 0000000000000..930772652d6ab --- /dev/null +++ b/boards/arm/stm32f2/photon/scripts/Make.defs @@ -0,0 +1,68 @@ +############################################################################ +# boards/arm/stm32f2/photon/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) +LDSCRIPT = photon_dfu.ld +else +LDSCRIPT = photon_jtag.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +# See http://dfu-util.sourceforge.net/ + +DFUSUFFIX = dfu-suffix +DFUUTIL = dfu-util + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ifeq ($(CONFIG_DFU_BINARY),y) + +define FLASH + $(Q) echo "DFUSUFFIX: $(1).dfu" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(1) $(1).dfu + $(Q) $(DFUSUFFIX) -v $(subst 0x,,$(CONFIG_DFU_VID)) -p $(subst 0x,,$(CONFIG_DFU_PID)) -a $(1).dfu + $(Q) $(DFUUTIL) -d $(CONFIG_DFU_VID):$(CONFIG_DFU_PID) -a 0 -s $(CONFIG_DFU_BASE) -D $(1).dfu +endef + +else + +define FLASH + $(Q) $(ECHO) "Photon firmware upload through JTAG is not supported" +endef + +endif diff --git a/boards/arm/stm32/photon/scripts/photon_dfu.ld b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_dfu.ld rename to boards/arm/stm32f2/photon/scripts/photon_dfu.ld index 0272b8a715797..d5fdad6367dfa 100644 --- a/boards/arm/stm32/photon/scripts/photon_dfu.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_dfu.ld + * boards/arm/stm32f2/photon/scripts/photon_dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/scripts/photon_jtag.ld b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_jtag.ld rename to boards/arm/stm32f2/photon/scripts/photon_jtag.ld index ca944b41a41b3..ad1ecad2b09af 100644 --- a/boards/arm/stm32/photon/scripts/photon_jtag.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_jtag.ld + * boards/arm/stm32f2/photon/scripts/photon_jtag.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/photon/src/CMakeLists.txt b/boards/arm/stm32f2/photon/src/CMakeLists.txt new file mode 100644 index 0000000000000..e9248b8107f1b --- /dev/null +++ b/boards/arm/stm32f2/photon/src/CMakeLists.txt @@ -0,0 +1,68 @@ +# ############################################################################## +# boards/arm/stm32f2/photon/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_PHOTON_DFU_BOOTLOADER) + list(APPEND SRCS dfu_signature.c) +endif() + +if(CONFIG_INPUT_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_PHOTON_WDG) + list(APPEND SRCS stm32_wdt.c) +endif() + +if(CONFIG_PHOTON_WLAN) + list(APPEND SRCS stm32_wlan.c) + list(APPEND SRCS stm32_wlan_firmware.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_PHOTON_DFU_BOOTLOADER) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/photon_dfu.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/photon_jtag.ld") +endif() diff --git a/boards/arm/stm32f2/photon/src/Make.defs b/boards/arm/stm32f2/photon/src/Make.defs new file mode 100644 index 0000000000000..36c65e38e42d1 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f2/photon/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_PHOTON_DFU_BOOTLOADER),y) +CSRCS += dfu_signature.c +endif + +ifeq ($(CONFIG_INPUT_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_PHOTON_WDG),y) +CSRCS += stm32_wdt.c +endif + +ifeq ($(CONFIG_PHOTON_WLAN),y) +CSRCS += stm32_wlan.c +CSRCS += stm32_wlan_firmware.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/photon/src/dfu_signature.c b/boards/arm/stm32f2/photon/src/dfu_signature.c similarity index 98% rename from boards/arm/stm32/photon/src/dfu_signature.c rename to boards/arm/stm32f2/photon/src/dfu_signature.c index 0ac237a385281..3738ed93a4208 100644 --- a/boards/arm/stm32/photon/src/dfu_signature.c +++ b/boards/arm/stm32f2/photon/src/dfu_signature.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/dfu_signature.c + * boards/arm/stm32f2/photon/src/dfu_signature.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/photon.h b/boards/arm/stm32f2/photon/src/photon.h similarity index 98% rename from boards/arm/stm32/photon/src/photon.h rename to boards/arm/stm32f2/photon/src/photon.h index 299fe0294ecd0..30f904847d118 100644 --- a/boards/arm/stm32/photon/src/photon.h +++ b/boards/arm/stm32f2/photon/src/photon.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/photon.h + * boards/arm/stm32f2/photon/src/photon.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f2/photon/src/stm32_autoleds.c b/boards/arm/stm32f2/photon/src/stm32_autoleds.c new file mode 100644 index 0000000000000..fe1a324f455d5 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_autoleds.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* LEDs + * + * A single LED is available driven by PA13. + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * ------------------- ----------------------- ------ + * SYMBOL Meaning LED + * ------------------- ----------------------- ------ + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt N/C + * LED_SIGNAL In a signal handler N/C + * LED_ASSERTION An assertion failed N/C + * LED_PANIC The system has crashed FLASH + * + * Thus is LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "photon.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure Photon LED gpio as output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1 || led == 3) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 3) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/photon/src/stm32_boot.c b/boards/arm/stm32f2/photon/src/stm32_boot.c new file mode 100644 index 0000000000000..8acf417ab0f0c --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_boot.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "photon.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGHS + /* Initialize USB if the + * 1) OTG HS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into + * the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + stm32_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f2/photon/src/stm32_bringup.c b/boards/arm/stm32f2/photon/src/stm32_bringup.c new file mode 100644 index 0000000000000..7bcb3c0afa0e3 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_bringup.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "photon.h" +#include "stm32_wdg.h" + +#ifdef CONFIG_USBADB +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * This function initializes and configures all on-board features + * appropriate for the selected configuration. + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#ifdef CONFIG_STM32_IWDG + /* Initialize the watchdog timer */ + + stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); +#endif + +#ifdef CONFIG_PHOTON_WDG + /* Start WDG kicker thread */ + + ret = photon_watchdog_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to start watchdog thread: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PHOTON_WLAN + /* Initialize wlan driver and hardware */ + + ret = photon_wlan_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize wlan: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_USBDEV_COMPOSITE + +#ifndef CONFIG_BOARDCTL_USBDEVCTRL + ret = board_composite_initialize(0); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize composite: %d\n", ret); + return ret; + } + + if (board_composite_connect(0, 0) == NULL) + { + syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); + return ret; + } +#endif /* !CONFIG_BOARDCTL_USBDEVCTRL */ +#else +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif +#endif /* CONFIG_USBDEV_COMPOSITE */ + return ret; +} diff --git a/boards/arm/stm32f2/photon/src/stm32_buttons.c b/boards/arm/stm32f2/photon/src/stm32_buttons.c new file mode 100644 index 0000000000000..c4f6bd29b3a08 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_buttons.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include "photon.h" + +#include "stm32_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure Photon button gpio as input */ + + stm32_configgpio(GPIO_BUTTON1); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the only button */ + + if (stm32_gpioread(GPIO_BUTTON1)) + { + return BOARD_BUTTON1_BIT; + } + + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + if (id != BOARD_BUTTON1) + { + /* Invalid button id */ + + return -EINVAL; + } + + /* Configure interrupt on falling edge only */ + + return stm32_gpiosetevent(GPIO_BUTTON1, false, true, false, + irqhandler, arg); +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/boards/arm/stm32f2/photon/src/stm32_composite.c b/boards/arm/stm32f2/photon/src/stm32_composite.c new file mode 100644 index 0000000000000..49f82ed1d23ef --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_composite.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite0_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite0_connect(int port) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + /* Change "dev" array size to add more composite devs */ + + struct composite_devdesc_s dev[1]; + int ifnobase = 0; + int strbase = (COMPOSITE_NSTRIDS) - 1; + + int dev_idx = 0; + +#ifdef CONFIG_USBADB + /* Configure the ADB USB device */ + + /* Ask the adb driver to fill in the constants we didn't + * know here. + */ + + usbdev_adb_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBADB_EP_BULKIN_IDX] = 1; + dev[dev_idx].devinfo.epno[USBADB_EP_BULKOUT_IDX] = 2; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Add other composite devices here */ + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + + return NULL; +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f2/photon/src/stm32_rgbled.c b/boards/arm/stm32f2/photon/src/stm32_rgbled.c new file mode 100644 index 0000000000000..3b56149af249c --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_rgbled.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "photon.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL2 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM2_CHANNEL4 +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct file file; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + ledr->ops->setup(ledr); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + ledg->ops->setup(ledg); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + ledb->ops->setup(ledb); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + ret = file_open(&file, "/dev/rgbled0", O_WRONLY); + if (ret < 0) + { + lederr("ERROR: open failed: %d\n", ret); + return ret; + } + + /* Initialize led off */ + + file_write(&file, "#000000", 8); + file_close(&file); + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f2/photon/src/stm32_spi.c b/boards/arm/stm32f2/photon/src/stm32_spi.c new file mode 100644 index 0000000000000..775b45ed32d14 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_spi.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "photon.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 + * STM32 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + switch (devid) + { + default: + break; + } + + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f2/photon/src/stm32_usb.c b/boards/arm/stm32f2/photon/src/stm32_usb.c new file mode 100644 index 0000000000000..3bb76c85e31a8 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_usb.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "photon.h" +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Photon board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. + * This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif diff --git a/boards/arm/stm32f2/photon/src/stm32_userleds.c b/boards/arm/stm32f2/photon/src/stm32_userleds.c new file mode 100644 index 0000000000000..30b2933307b43 --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_userleds.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include "photon.h" + +#include "stm32_gpio.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure Photon LED gpio as output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/photon/src/stm32_wdt.c b/boards/arm/stm32f2/photon/src/stm32_wdt.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_wdt.c rename to boards/arm/stm32f2/photon/src/stm32_wdt.c index 738312db16eb9..09db859e1df03 100644 --- a/boards/arm/stm32/photon/src/stm32_wdt.c +++ b/boards/arm/stm32f2/photon/src/stm32_wdt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wdt.c + * boards/arm/stm32f2/photon/src/stm32_wdt.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/photon/src/stm32_wlan.c b/boards/arm/stm32f2/photon/src/stm32_wlan.c new file mode 100644 index 0000000000000..88bfa4561e9cf --- /dev/null +++ b/boards/arm/stm32f2/photon/src/stm32_wlan.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f2/photon/src/stm32_wlan.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "stm32_sdio.h" + +#include "photon.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bcmf_board_reset + ****************************************************************************/ + +void bcmf_board_reset(int minor, bool reset) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + stm32_gpiowrite(GPIO_WLAN0_RESET, !reset); +} + +/**************************************************************************** + * Name: bcmf_board_power + ****************************************************************************/ + +void bcmf_board_power(int minor, bool power) +{ + /* Power signal is not used on Photon board */ +} + +/**************************************************************************** + * Name: bcmf_board_initialize + ****************************************************************************/ + +void bcmf_board_initialize(int minor) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure reset pin */ + + stm32_configgpio(GPIO_WLAN0_RESET); + + /* Put wlan chip in reset state */ + + bcmf_board_reset(minor, true); +} + +/**************************************************************************** + * Name: bcmf_board_setup_oob_irq + ****************************************************************************/ + +void bcmf_board_setup_oob_irq(int minor, int (*func)(void *), void *arg) +{ + if (minor != SDIO_WLAN0_MINOR) + { + return; + } + + /* Configure SDIO card in-band interrupt callback */ + + if (g_sdio_dev != NULL) + { + sdio_set_sdio_card_isr(g_sdio_dev, func, arg); + } +} + +/**************************************************************************** + * Name: bcmf_board_etheraddr + ****************************************************************************/ + +bool bcmf_board_etheraddr(struct ether_addr *ethaddr) +{ + return false; +} + +/**************************************************************************** + * Name: photon_wlan_initialize + ****************************************************************************/ + +int photon_wlan_initialize() +{ + int ret; + + /* Initialize sdio interface */ + + wlinfo("Initializing SDIO slot %d\n", SDIO_WLAN0_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_WLAN0_SLOTNO); + + if (!g_sdio_dev) + { + wlerr("ERROR: Failed to initialize SDIO with slot %d\n", + SDIO_WLAN0_SLOTNO); + return ERROR; + } + + /* Bind the SDIO interface to the bcmf driver */ + + ret = bcmf_sdio_initialize(SDIO_WLAN0_MINOR, g_sdio_dev); + + if (ret != OK) + { + wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); + + /* FIXME deinitialize sdio device */ + + return ERROR; + } + + return OK; +} diff --git a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c similarity index 99% rename from boards/arm/stm32/photon/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c index 2374ae038c923..ace87343d4e79 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan_firmware.c + * boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt new file mode 100644 index 0000000000000..9107f3bbd27ee --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/Kconfig b/boards/arm/stm32f2/stm3220g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3220g-eval/Kconfig rename to boards/arm/stm32f2/stm3220g-eval/Kconfig diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig new file mode 100644 index 0000000000000..4e83650fdf40e --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_DHCPD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="dhcpd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig new file mode 100644 index 0000000000000..431b3151a62e2 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_NOMAC=y +CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nettest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NET=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..26a63e10c0781 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..5dff42667f25d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig new file mode 100644 index 0000000000000..8a2c4444608fc --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig @@ -0,0 +1,126 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig new file mode 100644 index 0000000000000..5d80ddff92c0a --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3220g-eval" +CONFIG_ARCH_BOARD_STM3220G_EVAL=y +CONFIG_ARCH_CHIP="stm32f2" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10926 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NSH_LIBRARY=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2012 +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f2/stm3220g-eval/include/board.h b/boards/arm/stm32f2/stm3220g-eval/include/board.h new file mode 100644 index 0000000000000..fb3043eada22d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/include/board.h @@ -0,0 +1,552 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four clock sources are available on STM3220G-EVAL evaluation board for + * STM32F207IGH6 and RTC embedded: + * + * X1, 25 MHz crystal for ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU + * X2, 26 MHz crystal for USB OTG HS PHY + * X3, 32 kHz crystal for embedded RTC + * X4, 25 MHz crystal with socket for STM32F207IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) + * + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration + * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 240 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 5 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 240 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(240) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)= 16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)= 12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* Ethernet *****************************************************************/ + +/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +# if !defined(CONFIG_STM32_MII) +# warning "CONFIG_STM32_MII required for Ethernet" +# elif !defined(CONFIG_STM32_MII_MCO1) +# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" +# else + + /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ + +# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE +# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE + +# endif +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3220G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3220G-EVAL supports three buttons: */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_USER 2 + +#define NUM_BUTTONS 3 + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* UART3: + * + * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) + * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX + */ + +#ifdef CONFIG_STM32_USART3 +# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) +#endif + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT + * - PH2 is ETH_MII_CRS + * - PH3 is ETH_MII_COL + * - PI10 is ETH_MII_RX_ER + * - PH6 is ETH_MII_RXD2 + * - PH7 is ETH_MII_RXD3 + * - PC3 is ETH_MII_TX_CLK + * - PC2 is ETH_MII_TXD2 + * - PB8 is ETH_MII_TXD3 + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM3220G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using the following: + * + * If FSMC is not used: + * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT + * Daughterboard Extension Connector, CN3, pin 32 + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. + * + * TIM1 CH1OUT: PE9 FSMC_D6 + * Daughterboard Extension Connector, CN2, pin 24 + * + * TIM1_CH2OUT: PE11 FSMC_D8 + * Daughterboard Extension Connector, CN2, pin 26 + * + * TIM1_CH3OUT: PE13 FSMC_D10 + * Daughterboard Extension Connector, CN2, pin 28 + * + * TIM1_CH4OUT: PE14 FSMC_D11 + * Daughterboard Extension Connector, CN2, pin 29 + * + * If OTG FS is not used + * + * TIM1_CH3OUT: PA10 OTG_FS_ID + * Daughterboard Extension Connector, CN3, pin 14 + * + * TIM1_CH4OUT: PA11 OTG_FS_DM + * Daughterboard Extension Connector, CN3, pin 11 + * + * If DMCI is not used + * + * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC + * Daughterboard Extension Connector, CN4, pin 4 + * + * TIM8_CH2OUT: PI6 DCMI_D6 & MC + * Daughterboard Extension Connector, CN4, pin 3 + * + * TIM8_CH3OUT: PI7 DCMI_D7 & MC + * Daughterboard Extension Connector, CN4, pin 2 + * + * If SDIO is not used + * + * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC + * Daughterboard Extension Connector, CN3, pin 18 + * + * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) + * Daughterboard Extension Connector, CN3, pin 17 + * + * Others + * + * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) + */ + +#if !defined(CONFIG_STM32_FSMC) +# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) +#elif !defined(CONFIG_STM32_OTGFS) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +#if !defined(CONFIG_STM32_DCMI) +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) +#else +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) +# if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) +# endif +#endif + +#if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +/* CAN + * + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. + * + * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver + * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver + * + * CAN signals are then available on CN10 pins: + * + * CN10 Pin 7 = CANH + * CN10 Pin 2 = CANL + * + * Mapping to STM32 GPIO pins: + * + * PD0 = FSMC_D2 & CAN1_RX + * PD1 = FSMC_D3 & CAN1_TX + * PB13 = ULPI_D6 & CAN2_TX + * PB5 = ULPI_D7 & CAN2_RX + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) + +/* I2C. + * Only I2C1 is available on the STM3220G-EVAL. I2C1_SCL and I2C1_SDA are + * available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* FSMC (LCD/SRAM) */ + +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3220g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3220g_lcdclear(uint16_t color); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_STM3220G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs new file mode 100644 index 0000000000000..3b902ef1830a2 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script new file mode 100644 index 0000000000000..bb2f5e12f4c53 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F207IGH6U has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..c198e622bed54 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt @@ -0,0 +1,69 @@ +# ############################################################################## +# boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_FSMC) + list( + APPEND + SRCS + stm32_lcd.c + stm32_selectlcd.c + stm32_deselectlcd.c + stm32_selectsram.c + stm32_deselectsram.c + stm32_extmem.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f2/stm3220g-eval/src/Make.defs b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs new file mode 100644 index 0000000000000..3c938b3299867 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f2/stm3220g-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h rename to boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h index 7908e0a422c30..775b69a377d8b 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h + * boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..347835c5d36a1 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC3 +# warning "Channel information only available for ADC3" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The STM3220G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of + * STM32F207IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC3 +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC3 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c new file mode 100644 index 0000000000000..58d3ebc7653ac --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..f73fd6ed35a54 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c @@ -0,0 +1,368 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* MMCSD PORT and SLOT number probably depend on the board configuration */ + +#define HAVE_USBDEV 1 +#define HAVE_MMCSD 1 +#define HAVE_USBHOST 1 + +#if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +#endif + +#ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef HAVE_MMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* If the FSMC is enabled, then enable SRAM access */ + +#ifdef CONFIG_STM32_FSMC + stm32_selectsram(); +#endif + + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) the weak function stm32_usbinitialize() has been brought into the + * build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); + return; + } + + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to the SPI FLASH driver\n"); + return; + } + +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return; + } + + /* Then let's guess and say that there is a card in the slot. I need to + * check to see if the STM3220G-EVAL board supports a GPIO to detect if + * there is a card in the slot. + */ + + sdio_mediachange(sdio, true); +#endif + + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + +#ifdef HAVE_USBHOST + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..f054a70494d16 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm3220g-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c new file mode 100644 index 0000000000000..5a2826f4674ff --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..3ef672f986de7 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..e1fe12d86a533 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable SRAM + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..7a0344fcc7e5e --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..d8c10b4639535 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c @@ -0,0 +1,1186 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs on the STM324xG_EVAL board: + * + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# define CONFIG_LCD_MAXPOWER 1 +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_LANDSCAPE) +# ifdef CONFIG_LCD_RLANDSCAPE +# error "Cannot define both landscape and any other orientations" +# endif +#elif !defined(CONFIG_LCD_RLANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# define STM3220G_XRES 320 +# define STM3220G_YRES 240 +#else +# define STM3220G_XRES 240 +# define STM3220G_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3220G_BPP 16 +#define STM3220G_COLORFMT FB_FMT_RGB16_565 + +/* STM3220G-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ + +#define STM3220G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) +#define LCD ((struct lcd_regs_s *)STM3220G_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define ILI9320_ID 0x9320 +#define ILI9321_ID 0x9321 +#define ILI9325_ID 0x9325 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_ILI9320, + LCD_TYPE_ILI9325 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3220g_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3220g_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3220g_readreg(uint8_t regaddr); +static inline void stm3220g_gramselect(void); +static inline void stm3220g_writegram(uint16_t rgbval); +static void stm3220g_readnosetup(uint16_t *accum); +static uint16_t stm3220g_readnoshift(uint16_t *accum); +static void stm3220g_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3220g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels); +static int stm3220g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels); + +/* LCD Configuration */ + +static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3220g_getpower(struct lcd_dev_s *dev); +static int stm3220g_setpower(struct lcd_dev_s *dev, int power); +static int stm3220g_getcontrast(struct lcd_dev_s *dev); +static int stm3220g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* Initialization */ + +static inline void stm3220g_lcdinitialize(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3220G_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3220G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3220G_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3220G_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3220g_putrun, /* Put a run into LCD memory */ + .getrun = stm3220g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3220G_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3220g_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3220g_getvideoinfo, + .getplaneinfo = stm3220g_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3220g_getpower, + .setpower = stm3220g_setpower, + .getcontrast = stm3220g_getcontrast, + .setcontrast = stm3220g_setcontrast, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3220g_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3220g_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3220g_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3220g_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3220g_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3220g_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3220g_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3220g_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - ILI932x: Discard first dummy read; no shift in the return data + * + ****************************************************************************/ + +static void stm3220g_readnosetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. + * Possibly shifting the data and possibly swapping red and green + * components. + * + * - ILI932x: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +static uint16_t stm3220g_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} + +/**************************************************************************** + * Name: stm3220g_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3220g_setcursor(uint16_t col, uint16_t row) +{ + stm3220g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3220g_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3220g_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The LCD device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3220g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + /* Write the GRAM data, manually incrementing X */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(col, row); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3220g_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3220g_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ + + stm3220g_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are at the + * bottom of the board). + */ + + col = (STM3220G_XRES - 1) - col; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3220G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + stm3220g_writegram(*src++); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The LCD device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3220g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ + + switch (g_lcddev.type) + { + case LCD_TYPE_ILI9320: + case LCD_TYPE_ILI9325: + readsetup = stm3220g_readnosetup; + readgram = stm3220g_readnoshift; + break; + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3220G-EVAL is used as the top. + */ + + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3220g_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3220g_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position + * (autoincrements to the next row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). + */ + + col = (STM3220G_XRES - 1) - col; + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). + */ + + row = (STM3220G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3220g_setcursor(row, col); + stm3220g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3220g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3220g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getpower + * + * Description: + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_getpower(struct lcd_dev_s *dev) +{ + lcdinfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3220g_poweroff + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_poweroff(void) +{ + /* Turn the display off */ + + stm3220g_writereg(LCD_REG_7, 0); + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3220g_setpower + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3220g_setpower(struct lcd_dev_s *dev, int power) +{ + lcdinfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + /* Then turn the display on */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9325_DISABLE) + stm3220g_writereg(LCD_REG_7, 0x0173); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3220g_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3220g_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3220g_getcontrast(struct lcd_dev_s *dev) +{ + lcdinfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3220g_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3220g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + lcdinfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3220g_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3220g_lcdinitialize(void) +{ + uint16_t id; + + /* Check LCD ID */ + + id = stm3220g_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) +#elif !defined(CONFIG_STM32_ILI9320_DISABLE) && defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID) +#else /* if defined(CONFIG_STM32_ILI9320_DISABLE) && !defined(CONFIG_STM32_ILI9325_DISABLE)) */ + if (id == ILI9325_ID) +#endif + { + /* Save the LCD type (not actually used at for anything important) */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) + if (id == ILI9325_ID) + { + g_lcddev.type = LCD_TYPE_ILI9325; + } + else +# endif + { + g_lcddev.type = LCD_TYPE_ILI9320; + stm3220g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + } +#else /* if !defined(CONFIG_STM32_ILI9325_DISABLE) */ + g_lcddev.type = LCD_TYPE_ILI9325; +#endif + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3220g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3220g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3220g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3220g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + + /* stm3220g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + + stm3220g_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3220g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3220g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3220g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3220g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3220g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3220g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3220g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3220g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3220g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3220g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3220g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3220g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3220g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3220g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3220g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (ILI9320/1) */ + +#if !defined(CONFIG_STM32_ILI9320_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) + if (g_lcddev.type == LCD_TYPE_ILI9320) +# endif + { + stm3220g_writereg(LCD_REG_48, 0x0006); + stm3220g_writereg(LCD_REG_49, 0x0101); + stm3220g_writereg(LCD_REG_50, 0x0003); + stm3220g_writereg(LCD_REG_53, 0x0106); + stm3220g_writereg(LCD_REG_54, 0x0b02); + stm3220g_writereg(LCD_REG_55, 0x0302); + stm3220g_writereg(LCD_REG_56, 0x0707); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0600); + stm3220g_writereg(LCD_REG_61, 0x020b); + } +#endif + + /* Adjust the Gamma Curve (ILI9325) */ + +#if !defined(CONFIG_STM32_ILI9325_DISABLE) +# if !defined(CONFIG_STM32_ILI9320_DISABLE) + else +# endif + { + stm3220g_writereg(LCD_REG_48, 0x0007); + stm3220g_writereg(LCD_REG_49, 0x0302); + stm3220g_writereg(LCD_REG_50, 0x0105); + stm3220g_writereg(LCD_REG_53, 0x0206); + stm3220g_writereg(LCD_REG_54, 0x0808); + stm3220g_writereg(LCD_REG_55, 0x0206); + stm3220g_writereg(LCD_REG_56, 0x0504); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0105); + stm3220g_writereg(LCD_REG_61, 0x0808); + } +#endif + + /* Set GRAM area */ + + stm3220g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3220g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3220g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3220g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3220g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + + /* stm3220g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + + stm3220g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3220g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3220g_writereg(LCD_REG_128, 0x0000); + stm3220g_writereg(LCD_REG_129, 0x0000); + stm3220g_writereg(LCD_REG_130, 0x0000); + stm3220g_writereg(LCD_REG_131, 0x0000); + stm3220g_writereg(LCD_REG_132, 0x0000); + stm3220g_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3220g_writereg(LCD_REG_144, 0x0010); + stm3220g_writereg(LCD_REG_146, 0x0000); + stm3220g_writereg(LCD_REG_147, 0x0003); + stm3220g_writereg(LCD_REG_149, 0x0110); + stm3220g_writereg(LCD_REG_151, 0x0000); + stm3220g_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3220g_writereg(LCD_REG_3, 0x1018); + stm3220g_writereg(LCD_REG_7, 0); /* Display off */ + } + else + { + lcderr("ERROR: Unsupported LCD type\n"); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3220g_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3220g_lcdclear(0); + + /* Turn the display off */ + + stm3220g_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3220g_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3220g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the stm3220g-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3220g_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3220g_setcursor(0, STM3220G_XRES - 1); + stm3220g_gramselect(); + for (i = 0; i < STM3220G_XRES * STM3220G_YRES; i++) + { + LCD->value = color; + } +} + +#endif /* !CONFIG_STM32_ILI9320_DISABLE || !CONFIG_STM32_ILI9325_DISABLE */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c new file mode 100644 index 0000000000000..55325a9f41d31 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM3220G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the + * board for PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM3220G_EVAL_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..9931766925263 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 +#define LCD_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin Usage (per schematic) + * SRAM LCD + * D[0..15] [0..15] [0..15] + * A[0..25] [0..22] [0] RS + * FSMC_NBL0 PE0 OUT --- --- + * FSMC_NBL1 PE1 OUT --- --- + * FSMC_NE2 PG9 OUT --- --- + * FSMC_NE3 PG10 OUT --- ~CS + * FSMC_NE4 PG12 OUT --- --- + * FSMC_NWE PD5 OUT --- ~WR/SCL + * FSMC_NOE PD4 OUT --- ~RD + * FSMC_NWAIT PD6 IN --- --- + * FSMC_INT2 PG6* IN --- --- + * FSMC_INT3 + * FSMC_INTR + * FSMC_CD + * FSMC_CLK + * FSMC_NCE2 + * FSMC_NCE3 + * FSMC_NCE4_1 + * FSMC_NCE4_2 + * FSMC_NIORD + * FSMC_NIOWR + * FSMC_NL + * FSMC_NREG + */ + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* NOE, NWE, and NE3 */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank3 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank3 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..3a0016a1a4947 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM Timing */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 1 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 1 +#define SRAM_DATA_LATENCY 2 + +/* SRAM pin definitions */ + +#define SRAM_NADDRLINES 21 +#define SRAM_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIOs Configuration ****************************************************** + * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 + * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 + * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 + * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 + * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 + * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 + * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 + * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 + * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 + * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 + * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 + * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 + * PE15 <-> FSMC_D12 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint32_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can + * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data + * width. Some simple transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ + stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..c766ed8ca4424 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3220G-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..4b37d489a8eab --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm3220g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C1 +# error "STMPE811 support requires CONFIG_STM32_I2C1" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 1 +#endif + +#if CONFIG_STMPE811_I2CDEV != 1 +# error "CONFIG_STMPE811_I2CDEV must be one" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3220G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and loss- + * of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. We will use it when EXTI interruptsare enabled */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c new file mode 100644 index 0000000000000..18abe851b1637 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm3220g-eval.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3220G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +#ifdef HAVE_USB + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c new file mode 100644 index 0000000000000..c7c5a9f1c708d --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3220g-eval.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh new file mode 100755 index 0000000000000..9d01a7c87563c --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh @@ -0,0 +1,87 @@ +#!/usr/bin/env bash + +# Get command line parameters + +USAGE="USAGE: $0 [-dh] " +ADVICE="Try '$0 -h' for more information" + +while [ ! -z "$1" ]; do + case $1 in + -d ) + set -x + ;; + -h ) + echo "$0 is a tool for generation of proper version files for the NuttX build" + echo "" + echo $USAGE + echo "" + echo "Where:" + echo " -d" + echo " Enable script debug" + echo " -h" + echo " show this help message and exit" + echo " Use the OpenOCD 0.4.0" + echo " " + echo " The full path to the top-level NuttX directory" + exit 0 + ;; + * ) + break; + ;; + esac + shift +done + +TOPDIR=$1 +if [ -z "${TOPDIR}" ]; then + echo "Missing argument" + echo $USAGE + echo $ADVICE + exit 1 +fi + +# This script *probably* only works with the following versions of OpenOCD: + +# Local search directory and configurations + +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f2/stm3220g-eval/tools" +OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" + +OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" +OPENOCD_EXE=openocd.exe +OPENOCD_INTERFACE="olimex-arm-usb-ocd.cfg" + +OPENOCD_TARGET="stm32.cfg" +OPENOCD_ARGS="-s ${OPENOCD_WSEARCHDIR} -f ${OPENOCD_INTERFACE} -f ${OPENOCD_TARGET}" + +echo "Trying OpenOCD 0.4.0 path: ${OPENOCD_PATH}/${OPENOCD_EXE}" + +# Verify that everything is what it claims it is and is located where it claims it is. + +if [ ! -x "${OPENOCD_PATH}/${OPENOCD_EXE}" ]; then + echo "OpenOCD executable does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" ]; then + echo "OpenOCD target config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_TARGET}" + exit 1 +fi +if [ ! -f "${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" ]; then + echo "OpenOCD interface config file does not exist: ${OPENOCD_SEARCHDIR}/${OPENOCD_INTERFACE}" + exit 1 +fi + +# Enable debug if so requested + +if [ "X$2" = "X-d" ]; then + OPENOCD_ARGS=$OPENOCD_ARGS" -d3" + set -x +fi + +# Okay... do it! + +echo "Starting OpenOCD" +"${OPENOCD_PATH}/${OPENOCD_EXE}" ${OPENOCD_ARGS} & +echo "OpenOCD daemon started" +ps -ef | grep openocd +echo "In GDB: target remote localhost:3333" diff --git a/boards/arm/stm32/stm3220g-eval/tools/stm32.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/stm32.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt b/boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt rename to boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt diff --git a/boards/arm/stm32f3/common/CMakeLists.txt b/boards/arm/stm32f3/common/CMakeLists.txt new file mode 100644 index 0000000000000..6d2b8c896bd73 --- /dev/null +++ b/boards/arm/stm32f3/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f3/common/Kconfig b/boards/arm/stm32f3/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f3/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f3/common/Makefile b/boards/arm/stm32f3/common/Makefile new file mode 100644 index 0000000000000..e7a1eed83cc33 --- /dev/null +++ b/boards/arm/stm32f3/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f3/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt new file mode 100644 index 0000000000000..d777a964b1855 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/Kconfig b/boards/arm/stm32f3/nucleo-f302r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f302r8/Kconfig rename to boards/arm/stm32f3/nucleo-f302r8/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig new file mode 100644 index 0000000000000..5e2a50cea1ad3 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_FS_LARGEFILE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_NAME_MAX=16 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_QUOTE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=255 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig new file mode 100644 index 0000000000000..de7101c186d01 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_INITTHREAD_STACKSIZE=1024 +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=64 +CONFIG_IOB_NBUFFERS=5 +CONFIG_IRQ_WORK_STACKSIZE=1024 +CONFIG_LTO_FULL=y +CONFIG_NAME_MAX=0 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_ERRORS=y +CONFIG_NET_PREALLOC_DEVIF_CALLBACKS=2 +CONFIG_NET_SOCKOPTS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_MAX=8 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=0 +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig new file mode 100644 index 0000000000000..f415d6e0fc5c4 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF302R8_HIGHPRI=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_PWM=y +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig new file mode 100644 index 0000000000000..b0a78520cab60 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_HELP=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig new file mode 100644 index 0000000000000..95222d7a3e89f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM07M1=y +CONFIG_BOARD_STM32_IHM07M1_POT=y +CONFIG_BOARD_STM32_IHM07M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=5000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig new file mode 100644 index 0000000000000..7363a11f42d78 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig @@ -0,0 +1,86 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig new file mode 100644 index 0000000000000..f8824d5845013 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig @@ -0,0 +1,112 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_MQUEUE_NOTIFICATION is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_DMESG is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_SOURCE is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_UPTIME is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f302r8" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F302R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM_TOOLCHAIN=y +CONFIG_LINE_MAX=80 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_CLE=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PREALLOC_MQ_IRQ_MSGS=8 +CONFIG_PREALLOC_MQ_MSGS=8 +CONFIG_PTHREAD_MUTEX_ROBUST=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f302r8/include/board.h b/boards/arm/stm32f3/nucleo-f302r8/include/board.h new file mode 100644 index 0000000000000..14529925ce35c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/include/board.h @@ -0,0 +1,308 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F302R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PB13 of the + * STM32F302R8T6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F302R8. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F302R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F302R8T6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F302R8T6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM2 input ***************************************************************/ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) /* PA2 */ + +/* USART1 + * + * At default use: + * USART1_RX - PB7 + * USART1_TX - PB6 + * + * If CONFIG_NUCLEOF302R8_RS485_WAVESHARE=y use configuration to match RS485 + * shield from Waveshare: + * + * USART1_RX - PA10 + * USART1_TX - PA9 + * RS485_DIR - PA8 (arduino D7) + * + */ + +#ifdef CONFIG_NUCLEOF302R8_RS485_WAVESHARE +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ +# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | \ + GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \ + GPIO_PORTA | GPIO_PIN8) +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_50MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ +#endif + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_3|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN_TX_3|GPIO_SPEED_50MHz) /* PB9 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define STM32_TIM1_TRGO 0 + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PA9 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* PA12 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_3|GPIO_SPEED_50MHz) /* PB1 */ + +/* TIM2 PWM */ + +#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1_ETR_1|GPIO_SPEED_50MHz) /* PA0 */ +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) /* PA1 */ +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_1|GPIO_SPEED_50MHz) /* PA9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +#ifdef CONFIG_BOARD_STM32_IHM07M1 + +/* Configuration specific for the X-NUCLEO-IHM07M1 expansion board with + * the L6230 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +# define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN10) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN11) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN12) + +/* DIAG/ENABLE */ + +# define GPIO_FOC_DIAGEN (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN11) + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM07M1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F302R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs new file mode 100644 index 0000000000000..32cfbf2717852 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script new file mode 100644 index 0000000000000..a5bad8b6daca6 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F302R8T6 has 64Kb of FLASH beginning at address 0x0800:0000 and + * 16Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt new file mode 100644 index 0000000000000..d2e1166c77e9c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt @@ -0,0 +1,62 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_NUCLEOF302R8_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_BOARD_STM32_IHM07M1) + list(APPEND SRCS stm32_foc_ihm07m1.c) +else() + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs new file mode 100644 index 0000000000000..4b4fc883e987f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f302r8/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_NUCLEOF302R8_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM07M1),y) +CSRCS += stm32_foc_ihm07m1.c +else +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h rename to boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h index 6c3c83d04a00a..f38dbe2ed2873 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h +++ b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h + * boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c new file mode 100644 index 0000000000000..b4aed937ec96b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ADC1 +# error ADC1 support must be enabled +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# error ADC1 DMA support must be enabled +#endif + +#define ADC1_NCHANNELS 4 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Use CN8 pins 35, 36, 37 and 38 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 6, 7, 8, 9 +}; + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN6_0, /* PC0 */ + GPIO_ADC1_IN7_0, /* PC1 */ + GPIO_ADC1_IN8_0, /* PC2 */ + GPIO_ADC1_IN9_0, /* PC3 */ +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c new file mode 100644 index 0000000000000..16b52f1961fb9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c new file mode 100644 index 0000000000000..58c14e3183616 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c new file mode 100644 index 0000000000000..ddf259cacf795 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F302R8_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c new file mode 100644 index 0000000000000..718b549d346af --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c new file mode 100644 index 0000000000000..c75d14627c29d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c new file mode 100644 index 0000000000000..6a7ed672f30bb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c new file mode 100644 index 0000000000000..b06c6378f9dab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "stm32_ihm07m1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_19p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_601p5 +#define POT_SAMPLE_TIME ADC_SMPR_601p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS +# define IHM07M1_VBUS 1 +#else +# define IHM07M1_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT +# define IHM07M1_POT 1 +#else +# define IHM07M1_POT 0 +#endif + +#define ADC1_REGULAR (IHM07M1_VBUS + IHM07M1_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +/* Check ADC1 configuration */ + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +#if CONFIG_STM32_ADC1_RESOLUTION != 0 +# error +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* FOC ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN1 (PA0) + * - Current Phase U -> ADC1 INJ2 -> ADC1_IN7 (PC1) + * - Current Phase W -> ADC1 INJ3 -> ADC1_IN6 (PC0) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN2 (PA1) + * - POT -> ADC1 REG -> ADC1_IN12 (PB1) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase W high -> TIM1_CH3 (PA10) + * + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + 2, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + 12, /* ADC1 REG - POT */ +#endif + 1, /* ADC1 INJ1 - PHASE 1 */ +#if CONFIG_MOTOR_FOC_SHUNTS == 3 + 7, /* ADC1 INJ2 - PHASE 2 */ + 6, /* ADC1 INJ3 - PHASE 3 */ +#endif +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + GPIO_ADC1_IN2_0, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + GPIO_ADC1_IN12_0, +#endif + GPIO_ADC1_IN1_0, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + GPIO_ADC1_IN7_0, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + GPIO_ADC1_IN6_0, +#endif +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_IHM07M1_VBUS + { + .channel = 2, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_IHM07M1_POT + { + .channel = 12, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 1, + .sample_time = CURRENT_SAMPLE_TIME + }, +#if CONFIG_MOTOR_FOC_SHUNTS > 1 + { + .channel = 7, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +#if CONFIG_MOTOR_FOC_SHUNTS > 2 + { + .channel = 6, + .sample_time = CURRENT_SAMPLE_TIME + }, +#endif +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + return board_ihm07m1_initialize(&g_adc_cfg); +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c new file mode 100644 index 0000000000000..2882d646db15d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c @@ -0,0 +1,544 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include + +#ifdef CONFIG_NUCLEOF302R8_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if !defined(HIGHPRI_HAVE_TIM1) +# error "Needs TIM1 to trigger ADC DMA" +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) +# error Max 2 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (3) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 1, +#ifdef CONFIG_STM32_ADC1_DMA + 2, + 11, +#endif +#if INJ_NCHANNELS > 0 + 7, +#endif +#if INJ_NCHANNELS > 1 + 6 +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ +#ifdef CONFIG_STM32_ADC1_DMA + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +#endif +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN7_0, /* PC1/A4 */ +#endif +#if INJ_NCHANNELS > 1 + GPIO_ADC1_IN6_0 /* PC0/A5 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc12_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOS) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dmach1_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma1ch1_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; + int i; + + pending = stm32_dma_intget(STM32_DMA1_CHAN1); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(STM32_DMA1_CHAN1, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC12 ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC12); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA1 CH1 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA1CH1 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA1CH1); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected sequence end interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_NUCLEOF302R8_HIGHPRI */ diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c new file mode 100644 index 0000000000000..3270dce669b6c --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f302r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF302R8_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c new file mode 100644 index 0000000000000..5b5c35cf20d09 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f302r8.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt new file mode 100644 index 0000000000000..98d4d6771d75e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303re/Kconfig b/boards/arm/stm32f3/nucleo-f303re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303re/Kconfig rename to boards/arm/stm32f3/nucleo-f303re/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig new file mode 100644 index 0000000000000..800369214a2b5 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig new file mode 100644 index 0000000000000..464b73deff777 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_EXAMPLES_CAN=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="can_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_SYSLOG_NONE=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig new file mode 100644 index 0000000000000..e8470d5fdbdcb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="hello_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig new file mode 100644 index 0000000000000..4b5ead9b89fa8 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig @@ -0,0 +1,36 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig new file mode 100644 index 0000000000000..6c5fbbe4e1c31 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_CAN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_SSD1351=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXSTART_EXTERNINIT=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SPI1=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig new file mode 100644 index 0000000000000..e6ef3644349bf --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=2 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig new file mode 100644 index 0000000000000..cdfbb2e02b01b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303re" +CONFIG_ARCH_BOARD_NUCLEO_F303RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="serialrx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_UART4=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART4_BAUD=9600 diff --git a/boards/arm/stm32f3/nucleo-f303re/include/board.h b/boards/arm/stm32f3/nucleo-f303re/include/board.h new file mode 100644 index 0000000000000..a27906b0a72a9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/include/board.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F303RE board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F303RET6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F303RE. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F303RE supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F303RET6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F303RET6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_25MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_25MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) + +/* UART4 */ + +#define GPIO_UART4_RX (GPIO_UART4_RX_0|GPIO_SPEED_50MHz) +#define GPIO_UART4_TX (GPIO_UART4_TX_0|GPIO_SPEED_50MHz) + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC2_DMA_CHAN DMACHAN_ADC2_1 +#define ADC3_DMA_CHAN DMACHAN_ADC3 +#define ADC4_DMA_CHAN DMACHAN_ADC4_1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F303RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs new file mode 100644 index 0000000000000..8d2299c83d6d5 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script new file mode 100644 index 0000000000000..49e73ee56d140 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303RET6 has 512Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt new file mode 100644 index 0000000000000..1388c1f7d1eda --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt @@ -0,0 +1,69 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_LCD_SSD1351) + list(APPEND SRCS stm32_ssd1351.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f303re/src/Make.defs b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs new file mode 100644 index 0000000000000..d65a5d39ac5b2 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs @@ -0,0 +1,71 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_LCD_SSD1351),y) +CSRCS += stm32_ssd1351.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h similarity index 99% rename from boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h rename to boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h index bcd7bb841769a..01ce746a80522 100644 --- a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h +++ b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h + * boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c new file mode 100644 index 0000000000000..8031cccfaeeaa --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c @@ -0,0 +1,374 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && \ + (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if (defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2)) || \ + (defined(CONFIG_STM32_ADC3) && defined(CONFIG_STM32_ADC4)) +# error "will not work with this combination of ADCs" +#endif + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +# endif +#endif + +#if defined(CONFIG_STM32_ADC4) +# if defined(DEV2_PORT) +# error "Choose maximum two of ADC1, ADC2, ADC3, ADC4" +# else +# if defined(DEV1_PORT) +# define DEV2_PORT 4 +# else +# define DEV1_PORT 4 +# endif +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 4 +#define ADC2_NCHANNELS 3 +#define ADC3_NCHANNELS 3 +#define ADC4_NCHANNELS 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[4] = +{ + 1, + 2, + 6, + 7, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[4] = +{ + GPIO_ADC1_IN1_0, + GPIO_ADC1_IN2_0, + GPIO_ADC1_IN6_0, + GPIO_ADC1_IN7_0 +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 3, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, + GPIO_ADC2_IN3_0, + GPIO_ADC2_IN4_0 +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 5, + 12 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN1_0, + GPIO_ADC3_IN5_0, + GPIO_ADC3_IN12_0 +}; + +#elif DEV1_PORT == 4 + +#define DEV1_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 3 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC4_IN3_0 +}; + +#endif + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 1 + +#define DEV2_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist2[4] = +{ + 1, + 2, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[4] = +{ + GPIO_ADC1_IN1_0, + GPIO_ADC1_IN2_0, + GPIO_ADC1_IN6_0, + GPIO_ADC1_IN7_0 +}; + +#elif DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 3, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, + GPIO_ADC2_IN3_0, + GPIO_ADC2_IN4_0 +}; + +#elif DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 5, + 12 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN1_0, + GPIO_ADC3_IN5_0, + GPIO_ADC3_IN12_0 +}; + +#elif DEV2_PORT == 4 + +#define DEV2_NCHANNELS ADC4_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = +{ + 3 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[1] = +{ + GPIO_ADC4_IN3_0 +}; + +#endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4) */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..b8bd4ec3c7f06 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c new file mode 100644 index 0000000000000..8ff26cda3c57b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f303re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_SPI + if (stm32_spidev_initialize != NULL) + { + stm32_spidev_initialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + + /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. + * Il faut le faire ici + */ + +#ifdef HAVE_DAC + ret = board_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_dac_setup() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c new file mode 100644 index 0000000000000..0dbfc2add9f6b --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c new file mode 100644 index 0000000000000..5aad29928486f --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#ifdef CONFIG_STM32_CAN1 + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c new file mode 100644 index 0000000000000..c9910bee3d00a --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_pwm.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEO_F303RE_PWMTIMER); + if (pwm == NULL) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c new file mode 100644 index 0000000000000..70e8e235c6efc --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_SPI + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ + stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SSD1351 D/C n bit to select data (true) or command + * (false). This function must be provided by platform-specific logic. + * This is an implementation of the cmddata method of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * spi - SPI device that controls the bus the device that requires the + * CMD/DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for + * example, one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_SSD1351 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_DC, !cmd); + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_SPI */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c new file mode 100644 index 0000000000000..35e09d621e525 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-f303re.h" + +#ifdef CONFIG_LCD_SSD1351 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The pin configurations here require that SPI1 is selected */ + +#ifndef CONFIG_STM32_SPI1 +# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" +#endif + +#ifndef CONFIG_SSD1351_SPI4WIRE +# error "The configuration requires the SPI 4-wire interface" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_graphics_setup + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +struct lcd_dev_s *board_graphics_setup(unsigned int devno) +{ + struct spi_dev_s *spi; + struct lcd_dev_s *dev; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + stm32_configgpio(GPIO_OLED_RESET); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_OLED_RESET, true); + + /* Get the SPI1 port interface */ + + spi = stm32_spibus_initialize(1); + if (spi == NULL) + { + lcderr("ERROR: Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ssd1351_initialize(spi, devno); + if (dev == NULL) + { + lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); + } + else + { + lcdinfo("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + dev->setpower(dev, LCD_FULL_ON); + return dev; + } + } + + return NULL; +} + +#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c new file mode 100644 index 0000000000000..61e2ff9d063a1 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "nucleo-f303re.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c new file mode 100644 index 0000000000000..54e03ff99d1e7 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c new file mode 100644 index 0000000000000..fdcf173464039 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-f303re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt new file mode 100644 index 0000000000000..236a1e371d10e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/Kconfig b/boards/arm/stm32f3/nucleo-f303ze/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303ze/Kconfig rename to boards/arm/stm32f3/nucleo-f303ze/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig new file mode 100644 index 0000000000000..f9450ed1b9f70 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_RESOLUTION=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig new file mode 100644 index 0000000000000..c6f9fe743d03a --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig @@ -0,0 +1,39 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig new file mode 100644 index 0000000000000..028b18ca152f2 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f303ze" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1 +CONFIG_EXAMPLES_NXLINES_BPP=1 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff +CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=255 +CONFIG_LCD_SH1106_OLED_132=y +CONFIG_LCD_SSD1306_I2C=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f303ze/include/board.h b/boards/arm/stm32f3/nucleo-f303ze/include/board.h new file mode 100644 index 0000000000000..2f7b5950dd010 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/include/board.h @@ -0,0 +1,207 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSEBYP_ENABLE +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ ---- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Button definitions *******************************************************/ + +/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PC13. A high value will be sensed when the button is + * depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART3 (Nucleo Virtual Console) */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_50MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_50MHz) /* PD8 */ + +/* I2C1 Use Nucleo I2C1 pins */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) /* PB8 - D15 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) /* PB9 - D14 */ + +/* I2C2 Use Nucleo I2C2 pins */ + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2|GPIO_SPEED_50MHz) /* PF1 - D69 */ +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) /* PF0 - D68 */ +#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2|GPIO_SPEED_50MHz) /* PF2 - D70 */ + +/* DMA **********************************************************************/ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 +#define ADC3_DMA_CHAN DMACHAN_ADC3 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F303ZE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs new file mode 100644 index 0000000000000..1a1821fb246ab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script new file mode 100644 index 0000000000000..055c0bbe01f36 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303ZET6 has 512Kb of FLASH beginning at address 0x0800:0000, + * 64Kb of SRAM and 16kb CCM RAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt new file mode 100644 index 0000000000000..1ad333906e15e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs new file mode 100644 index 0000000000000..57baf0dc88aab --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303ze/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_LCD_SSD1306),y) +CSRCS += stm32_lcd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h rename to boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h index 7f302796b5f3e..35d4d81fa9abc 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h +++ b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h + * boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c new file mode 100644 index 0000000000000..e137704a98a88 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 4, + 6, + 9 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN4_0, /* PA3/A0 */ + GPIO_ADC1_IN6_0, /* PC0/A1 */ + GPIO_ADC1_IN9_0, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c new file mode 100644 index 0000000000000..1861cae6b24e3 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c new file mode 100644 index 0000000000000..8984995d203f7 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "nucleo-f303ze.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c new file mode 100644 index 0000000000000..3daad9db6c2be --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "nucleo-f303ze.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + return OK; +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c new file mode 100644 index 0000000000000..ff143d50418ac --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c new file mode 100644 index 0000000000000..2499bfdbb64ba --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f303ze.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_I2C_PORT 1 /* OLED display connected to I2C1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_I2C_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c new file mode 100644 index 0000000000000..770c74720d13d --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f303ze.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. NOTE: since + * there is only a single LED on-board, this is function is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt new file mode 100644 index 0000000000000..6822d936f9563 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/Kconfig b/boards/arm/stm32f3/nucleo-f334r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f334r8/Kconfig rename to boards/arm/stm32f3/nucleo-f334r8/Kconfig diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig new file mode 100644 index 0000000000000..c5b882ea44497 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig @@ -0,0 +1,96 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig new file mode 100644 index 0000000000000..1c1da0ff5ee24 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_HIGHPRI=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC1_INJECTED_CHAN=1 +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG1=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig new file mode 100644 index 0000000000000..7a8a8baf3f1a4 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig new file mode 100644 index 0000000000000..351e8d90ad43e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="spwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_SPWM=y +CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=3 +CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_INTERRUPTS=y +CONFIG_STM32_HRTIM_MASTER=y +CONFIG_STM32_HRTIM_MASTER_IRQ=y +CONFIG_STM32_HRTIM_NO_ENABLE_TIMERS=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_TIMA_PWM=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMB=y +CONFIG_STM32_HRTIM_TIMB_PWM=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMD=y +CONFIG_STM32_HRTIM_TIMD_PWM=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y +CONFIG_STM32_HRTIM_TIME=y +CONFIG_STM32_HRTIM_TIME_PWM=y +CONFIG_STM32_HRTIM_TIME_PWM_CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig new file mode 100644 index 0000000000000..2427abbae0bcc --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f334r8" +CONFIG_ARCH_BOARD_NUCLEO_F334R8=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="spwm_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NUCLEOF334R8_SPWM=y +CONFIG_NUCLEOF334R8_SPWM_PHASE_NUM=4 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/nucleo-f334r8/include/board.h b/boards/arm/stm32f3/nucleo-f334r8/include/board.h new file mode 100644 index 0000000000000..52d5fbd8889cf --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/include/board.h @@ -0,0 +1,344 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: PLL frequency is + * 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32F334R8. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo F334R8. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo F334R8 supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32F334R8. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_50MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_50MHz) /* PA2 */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_50MHz) /* PA9 */ + +/* COMP */ + +/* OPAMP */ + +#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5 +#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14 + +/* Configuration specific to high priority interrupts example: + * - HRTIM Timer A trigger for ADC if DMA transfer and HRTIM + * - TIM1 CC1 trigger for ADC if DMA transfer and TIM1 PWM + * - ADC DMA transfer on DMA1_CH1 + */ + +#ifdef CONFIG_NUCLEOF334R8_HIGHPRI + +#if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_ADC1_DMA) + +/* HRTIM - ADC trigger */ + +#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 +#define HRTIM_TIMA_MODE HRTIM_MODE_CONT +#define HRTIM_TIMA_UPDATE 0 +#define HRTIM_TIMA_RESET 0 + +#define HRTIM_ADC_TRG1 HRTIM_ADCTRG13_APER + +#endif /* CONFIG_STM32_HRTIM1 && CONFIG_STM32_ADC1_DMA*/ +#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ + +#ifdef CONFIG_NUCLEOF334R8_SPWM +# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_TIM1 + +/* TIM1 PWM configuration ***************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 */ +# define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_3|GPIO_SPEED_50MHz) /* TIM1 CH1N - PA7 */ + /* TIM1 CH2 - PA9 */ +# define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_50MHz) /* TIM1 CH2N - PB0 */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 */ +# define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_50MHz) /* TIM1 CH3N - PB1 */ +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH4 - PA11 */ +# endif + +# ifdef CONFIG_NUCLEOF334R8_SPWM_USE_HRTIM1 + +/* HRTIM configuration ******************************************************/ + +# define HRTIM_MASTER_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_MASTER_MODE HRTIM_MODE_CONT + +# define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMA_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMA_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMA_RESET 0 + +# define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMB_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMB_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMB_RESET 0 + +# define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMC_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMC_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMC_RESET 0 + +# define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIMD_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIMD_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIMD_RESET 0 + +# define HRTIM_TIME_PRESCALER HRTIM_PRESCALER_128 +# define HRTIM_TIME_MODE (HRTIM_MODE_CONT | HRTIM_MODE_PRELOAD) +# define HRTIM_TIME_CH1_SET HRTIM_OUT_SET_PER +# define HRTIM_TIME_CH1_RST HRTIM_OUT_RST_CMP1 +# define HRTIM_TIME_UPDATE HRTIM_UPDATE_MSTU +# define HRTIM_TIME_RESET 0 + +# define HRTIM_MASTER_IRQ HRTIM_IRQ_MCMP1 +# endif + +#endif /* CONFIG_NUCLEOF334R8_SPWM */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + +/* TIM1 CH2 alias (used by spwm2 config) */ + +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0|GPIO_SPEED_50MHz) + +/* HRTIM1 */ + +#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 +#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 +#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 +#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 +#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 +#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F334R8_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs new file mode 100644 index 0000000000000..26228f81667ec --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script new file mode 100644 index 0000000000000..83850802f0114 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F334R8 has 64Kb of FLASH beginning at address 0x0800:0000, + * 12Kb of SRAM and 4Kb of CCM SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt new file mode 100644 index 0000000000000..e56987f9cbacb --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt @@ -0,0 +1,59 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_STM32_HRTIM) + list(APPEND SRCS stm32_hrtim.c) +endif() + +if(CONFIG_COMP) + list(APPEND SRCS stm32_comp.c) +endif() + +if(CONFIG_OPAMP) + list(APPEND SRCS stm32_opamp.c) +endif() + +if(CONFIG_NUCLEOF334R8_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +if(CONFIG_NUCLEOF334R8_SPWM) + list(APPEND SRCS stm32_spwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs new file mode 100644 index 0000000000000..a3a09d9253c52 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs @@ -0,0 +1,61 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f334r8/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +CSRCS += stm32_hrtim.c +endif + +ifeq ($(CONFIG_COMP),y) +CSRCS += stm32_comp.c +endif + +ifeq ($(CONFIG_OPAMP),y) +CSRCS += stm32_opamp.c +endif + +ifeq ($(CONFIG_NUCLEOF334R8_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +ifeq ($(CONFIG_NUCLEOF334R8_SPWM),y) +CSRCS += stm32_spwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h rename to boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h index ddcab273b090b..b2a0f7c72f4dd 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h +++ b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h + * boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c new file mode 100644 index 0000000000000..d6530730994c9 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 11 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a108db4e5e303 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-f334r8.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c new file mode 100644 index 0000000000000..69051c8f1b3e0 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f334r8.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c new file mode 100644 index 0000000000000..cc95203cb1e4e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP6)) + +#ifdef CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP6 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + comp = stm32_compinitialize(6); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 6); + return -ENODEV; + } +#endif + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 + * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c new file mode 100644 index 0000000000000..961fcdd3a3f00 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c @@ -0,0 +1,586 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include + +#ifdef CONFIG_NUCLEOF334R8_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_HRTIM1) && defined(CONFIG_STM32_HRTIM_TIMA) +# define HIGHPRI_HAVE_HRTIM +# endif +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if defined(HIGHPRI_HAVE_HRTIM) && defined(HIGHPRI_HAVE_TIM1) +# error HRTIM TIM A or TIM1 ! +# elif !defined(HIGHPRI_HAVE_HRTIM) && !defined(HIGHPRI_HAVE_TIM1) +# error "Needs HRTIM TIMA or TIM1 to trigger ADC DMA" +# endif +#endif + +#ifdef HIGHPRI_HAVE_HRTIM +# if !defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || !defined(CONFIG_STM32_HRTIM_ADC) +# error +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 2) +# error Max 2 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (3) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_HRTIM + struct hrtim_dev_s *hrtim; +#endif +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 1, +#ifdef CONFIG_STM32_ADC1_DMA + 2, + 11, +#endif +#if INJ_NCHANNELS > 0 + 7, +#endif +#if INJ_NCHANNELS > 1 + 6 +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ +#ifdef CONFIG_STM32_ADC1_DMA + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +#endif +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN7_0, /* PC1/A4 */ +#endif +#if INJ_NCHANNELS > 1 + GPIO_ADC1_IN6_0 /* PC0/A5 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc12_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOS) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dmach1_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma1ch1_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; + int i; + + pending = stm32_dma_intget(STM32_DMA1_CHAN1); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(STM32_DMA1_CHAN1, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_HRTIM + struct hrtim_dev_s *hrtim; +#endif +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_HRTIM + /* Configure HRTIM */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + printf("ERROR: Failed to get HRTIM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->hrtim = hrtim; + + /* Set Timer A Period */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, 0xffd0); +#endif /* HIGHPRI_HAVE_HRTIM */ + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC12 ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC12); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA1 CH1 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA1CH1, dma1ch1_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA1CH1 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA1CH1, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA1CH1); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected sequence end interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOS); +#endif + +#ifdef HIGHPRI_HAVE_HRTIM + /* Enable HRTIM TIMA after ADC configuration */ + + HRTIM_TIM_ENABLE(highpri->hrtim, HRTIM_TIMER_TIMA, true); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_NUCLEOF334R8_HIGHPRI */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c new file mode 100644 index 0000000000000..6e33327441494 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_hrtim.h" + +#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtim_setup + * + * Description: + * Initialize HRTIM driver + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_hrtim_setup(void) +{ + static bool initialized = false; + struct hrtim_dev_s *hrtim = NULL; + int ret; + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + tmrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Register the HRTIM character driver at /dev/hrtim0 */ + + ret = hrtim_register("/dev/hrtim0", hrtim); + if (ret < 0) + { + tmrerr("ERROR: hrtim_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c new file mode 100644 index 0000000000000..33a3febc2ab3e --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_opamp_setup + * + * Description: + * Initialize OPAMP + * + ****************************************************************************/ + +int stm32_opamp_setup(void) +{ + static bool initialized = false; + struct opamp_dev_s *opamp = NULL; + int ret; + + if (!initialized) + { + /* Get the OPAMP interface */ + +#ifdef CONFIG_STM32_OPAMP2 + opamp = stm32_opampinitialize(2); + if (opamp == NULL) + { + aerr("ERROR: Failed to get OPAMP%d interface\n", 2); + return -ENODEV; + } +#endif + + /* Register the OPAMP character driver at /dev/opamp0 */ + + ret = opamp_register("/dev/opamp0", opamp); + if (ret < 0) + { + aerr("ERROR: opamp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c index 1bb93258e20ab..3fd7576b0120c 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt new file mode 100644 index 0000000000000..25937ad493c21 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/Kconfig b/boards/arm/stm32f3/stm32f334-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f334-disco/Kconfig rename to boards/arm/stm32f3/stm32f334-disco/Kconfig diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig new file mode 100644 index 0000000000000..2736b34ef80b1 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig @@ -0,0 +1,129 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DRIVERS_SMPS=y +CONFIG_EXAMPLES_SMPS=y +CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" +CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBDSP=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_ECHO=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_FREE=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HELP=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y +CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=128 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_INJECTED_CHAN=2 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG2=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DEADTIME=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMA=y +CONFIG_STM32_HRTIM_TIMA_DT=y +CONFIG_STM32_HRTIM_TIMA_PWM=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMA_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMB=y +CONFIG_STM32_HRTIM_TIMB_DT=y +CONFIG_STM32_HRTIM_TIMB_PWM=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMB_PWM_CH2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..7bdc5a61d0faf --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig new file mode 100644 index 0000000000000..a6bccf5b39779 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_DMESG is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXPORT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_TRUNCATE is not set +# CONFIG_NSH_DISABLE_UPTIME is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f334-disco" +CONFIG_ARCH_BOARD_STM32F334_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_COMP=y +CONFIG_DAC=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DRIVERS_POWERLED=y +CONFIG_EXAMPLES_POWERLED=y +CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_POWERLED_DEVPATH="/dev/powerled0" +CONFIG_FDCLONE_STDIO=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_NAME_MAX=16 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_MAXARGUMENTS=16 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PREALLOC_TIMERS=2 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=12288 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_PREALLOC_IRQ_ACTIONS=8 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_COMP4=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_DAC1CH1_DMA=y +CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE=5 +CONFIG_STM32_DAC1CH1_DMA_EXTERNAL=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_BURST=y +CONFIG_STM32_HRTIM_CLK_FROM_PLL=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_DMA=y +CONFIG_STM32_HRTIM_EEV2=y +CONFIG_STM32_HRTIM_EVENTS=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_BURST=y +CONFIG_STM32_HRTIM_TIMC_BURST_CH1=y +CONFIG_STM32_HRTIM_TIMC_DMA=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f3/stm32f334-disco/include/board.h b/boards/arm/stm32f3/stm32f334-disco/include/board.h new file mode 100644 index 0000000000000..b4c5ffeca08aa --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/include/board.h @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - 8 MHz from MCO output of ST-LINK + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 1, 8, 15-17 and HRTIM1 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f334-disco. The following definitions describe how NuttX + * controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F334-DISCO supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PA0 of the STM32F334R8. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32F334R8. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN_TX_2|GPIO_SPEED_50MHz) + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_3|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_3|GPIO_SPEED_50MHz) + +/* SPI */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* TIM */ + +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH3OUT (GPIO_TIM2_CH3OUT_3|GPIO_SPEED_50MHz) + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_4|GPIO_SPEED_50MHz) + +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) + +/* USART */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_3|GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_3|GPIO_SPEED_50MHz) /* PB3 */ + +/* Board configuration for powerled example: + * - Set HRTIM TIMC output 1 (PB12) on PERIOD. + * - Reset HRTIM TIMC output 1 on HRTIM EEV2. + * - HRTIM EEV2 is connected to COMP4 output which works as current limit. + * - COMP4 inverting input is connected to DAC1CH1 output. + * - COMP4 non-inverting input (PB1) is connected to current sense + * resistor (1 Ohm). + * - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used + * to provide slope compensation. + */ + +#if defined(CONFIG_EXAMPLES_POWERLED) + +/* Comparators configuration ************************************************/ + +#define COMP4_INM COMP_INMSEL_DAC1CH1 + +/* HRTIM configuration ******************************************************/ + +#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMC_MODE HRTIM_MODE_CONT +#define HRTIM_TIMC_DMA (HRTIM_DMA_REP|HRTIM_DMA_CMP1|HRTIM_DMA_CMP2| \ + HRTIM_DMA_CMP3|HRTIM_DMA_CMP4) +#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_PER +#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_EXTEVNT2 +#define HRTIM_TIMC_CH1_IDLE_STATE HRTIM_IDLE_INACTIVE + +#define HRTIM_EEV_SAMPLING HRTIM_EEV_SAMPLING_d1 +#define HRTIM_EEV2_SRC HRTIM_EEV_SRC_ANALOG +#define HRTIM_EEV2_FILTER HRTIM_EEV_DISABLE +#define HRTIM_EEV2_POL HRTIM_EEV_POL_HIGH +#define HRTIM_EEV2_SEN HRTIM_EEV_SEN_LEVEL +#define HRTIM_EEV2_MODE HRTIM_EEV_MODE_FAST + +#define HRTIM_BURST_CLOCK HRTIM_BURST_CLOCK_HRTIM +#define HRTIM_BURST_PRESCALER HRTIM_BURST_PRESCALER_1 +#define HRTIM_BURST_TRIGGERS 0 + +/* DMA channels *************************************************************/ + +/* DAC */ + +#define DAC1CH1_DMA_CHAN DMACHAN_HRTIM1_C + +#endif /* CONFIG_EXAMPLES_POWERLED */ + +/* Board configuration for SMPS example: + * PA8 - HRTIM_CHA1 + * PA9 - HRTIM_CHA2 + * PA10 - HRTIM_CHB1 + * PA11 - HRTIM_CHB2 + * VIN - ADC Channel 2 (PA1) + * VOUT - ADC Channel 4 (PA3) + */ + +#if defined(CONFIG_EXAMPLES_SMPS) + +/* HRTIM configuration ******************************************************/ + +/* Timer A configuration - Buck operations */ + +#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMA_MODE HRTIM_MODE_CONT +#define HRTIM_TIMA_UPDATE 0 +#define HRTIM_TIMA_RESET 0 + +#define HRTIM_TIMA_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMA_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMA_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMA_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMA_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMA_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMA_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMA_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMA_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMA_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMA_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +/* Timer B configuration - Boost operations */ + +#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMB_MODE HRTIM_MODE_CONT +#define HRTIM_TIMB_UPDATE 0 +#define HRTIM_TIMB_RESET 0 + +#define HRTIM_TIMB_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMB_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMB_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMB_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMB_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMB_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMB_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMB_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMB_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMB_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMB_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4 + +/* DMA channels *************************************************************/ + +#endif /* CONFIG_EXAMPLES_SMPS */ + +/* HRTIM1 */ + +#define GPIO_HRTIM1_CHA1 GPIO_HRTIM1_CHA1_0 +#define GPIO_HRTIM1_CHA2 GPIO_HRTIM1_CHA2_0 +#define GPIO_HRTIM1_CHB1 GPIO_HRTIM1_CHB1_0 +#define GPIO_HRTIM1_CHB2 GPIO_HRTIM1_CHB2_0 +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 +#define GPIO_HRTIM1_CHE1 GPIO_HRTIM1_CHE1_0 +#define GPIO_HRTIM1_CHE2 GPIO_HRTIM1_CHE2_0 +#define GPIO_HRTIM1_EEV1 GPIO_HRTIM1_EEV1_0 +#define GPIO_HRTIM1_EEV2 GPIO_HRTIM1_EEV2_0 +#define GPIO_HRTIM1_EEV3 GPIO_HRTIM1_EEV3_0 +#define GPIO_HRTIM1_FLT1 GPIO_HRTIM1_FLT1_0 +#define GPIO_HRTIM1_FLT2 GPIO_HRTIM1_FLT2_0 +#define GPIO_HRTIM1_FLT3 GPIO_HRTIM1_FLT3_0 +#define GPIO_HRTIM1_FLT4 GPIO_HRTIM1_FLT4_0 +#define GPIO_HRTIM1_FLT5 GPIO_HRTIM1_FLT5_0 + +/* COMP */ + +#define GPIO_COMP2_INP GPIO_COMP2_INP_0 +#define GPIO_COMP4_INP GPIO_COMP4_INP_0 +#define GPIO_COMP6_INP GPIO_COMP6_INP_0 + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +#endif /* __BOARDS_ARM_STM32_STM32F334_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs new file mode 100644 index 0000000000000..808988ed8e20d --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script new file mode 100644 index 0000000000000..f5f4236470b70 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F334C8 has 64Kb of FLASH beginning at address 0x0800:0000, + * 12Kb of SRAM and 4Kb of CCM SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..0f8f031ecba1b --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt @@ -0,0 +1,55 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_DRIVERS_POWERLED) + list(APPEND SRCS stm32_powerled.c) +endif() + +if(CONFIG_DRIVERS_SMPS) + list(APPEND SRCS stm32_smps.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/stm32f334-disco/src/Make.defs b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs new file mode 100644 index 0000000000000..fc16406ada6f5 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs @@ -0,0 +1,57 @@ +############################################################################ +# boards/arm/stm32f3/stm32f334-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_DRIVERS_POWERLED),y) +CSRCS += stm32_powerled.c +endif + +ifeq ($(CONFIG_DRIVERS_SMPS),y) +CSRCS += stm32_smps.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c new file mode 100644 index 0000000000000..82267bb3d83f0 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 11 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN11_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[1] = +{ + 1, + 6, + 7 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN1_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..2adf161687a1d --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f334-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..0dce4b87b7d74 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c @@ -0,0 +1,194 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f334-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC1 1 +# define HAVE_DAC2 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS) +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_COMP + /* Initialize COMP and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_OPAMP + /* Initialize OPAMP and register the OPAMP driver. */ + + ret = stm32_opamp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_HRTIM + /* Initialize HRTIM and register the HRTIM driver. */ + + ret = stm32_hrtim_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_hrtim_setup failed: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_DRIVERS_POWERLED + /* Initialize powerled and register the powerled driver */ + + ret = stm32_powerled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_powerled_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DRIVERS_SMPS + /* Initialize smps and register the smps driver */ + + ret = stm32_smps_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c new file mode 100644 index 0000000000000..9f0c52f925b54 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_COMP) && (defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) || \ + defined(CONFIG_STM32_COMP6)) + +#ifdef CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP4) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP6) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP6 +# if defined(CONFIG_STM32_COMP2) || defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP6 + comp = stm32_compinitialize(6); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 6); + return -ENODEV; + } +#endif + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 + * CONFIG_STM32_COMP6) */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c new file mode 100644 index 0000000000000..38885ff50b9f9 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32_hrtim.h" + +#if defined(CONFIG_STM32_HRTIM) && defined(CONFIG_STM32_HRTIM1) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_hrtim_setup + * + * Description: + * Initialize HRTIM driver + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_hrtim_setup(void) +{ + static bool initialized = false; + struct hrtim_dev_s *hrtim = NULL; + int ret; + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + tmrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Register the HRTIM character driver at /dev/hrtim0 */ + + ret = hrtim_register("/dev/hrtim0", hrtim); + if (ret < 0) + { + tmrerr("ERROR: hrtim_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_STM32_HRTIM && CONFIG_STM32_HRTIM1 */ diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c new file mode 100644 index 0000000000000..03f9557d1e14a --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_opamp_setup + * + * Description: + * Initialize OPAMP + * + ****************************************************************************/ + +int stm32_opamp_setup(void) +{ + static bool initialized = false; + struct opamp_dev_s *opamp = NULL; + int ret; + + if (!initialized) + { + /* Get the OPAMP interface */ + +#ifdef CONFIG_STM32_OPAMP2 + opamp = stm32_opampinitialize(2); + if (opamp == NULL) + { + aerr("ERROR: Failed to get OPAMP%d interface\n", 2); + return -ENODEV; + } +#endif + + /* Register the OPAMP character driver at /dev/opamp0 */ + + ret = opamp_register("/dev/opamp0", opamp); + if (ret < 0) + { + aerr("ERROR: opamp_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c index 0f7890bd25fd6..81430e490d8d7 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c new file mode 100644 index 0000000000000..9253f274ce9d0 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c @@ -0,0 +1,1143 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_adc.h" + +#include + +#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) + +#ifndef CONFIG_LIBDSP +# error CONFIG_LIBDSP is required +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) +# error "SMPS example requires HRTIM1 support" +#endif + +#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) +# error "SMPS example requires ADC1 support" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC1 channels used in this example */ + +#define ADC1_NCHANNELS 2 + +/* ADC1 injected channels numeration */ + +#define V_IN_ADC_INJ_CHANNEL 0 +#define V_OUT_ADC_INJ_CHANNEL 1 + +/* Voltage reference for ADC */ + +#define ADC_REF_VOLTAGE ((float)3.3) + +/* ADC resolution */ + +#define ADC_VAL_MAX 4095 + +/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ + +#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) + +/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ + +#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) + +/* Some absolute limits */ + +#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 +#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 +#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 + +#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA +# error "Output current limit great than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV +# error "Output voltage limit greater than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV +# error "Input voltage limit greater than absolute limit!" +#endif + +/* Maximum output voltage for boost converter in float */ + +#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) + +/* Current limit table dimension */ + +#define SMPS_CURRENT_LIMIT_TAB_DIM 15 + +/* At this time only PID controller implemented */ + +#define SMPS_CONTROLLER_PID 1 + +/* Converter's finite accuracy */ + +#define SMPS_VOLTAGE_ACCURACY ((float)0.01) + +/* Buck-boost mode threshold */ + +#define SMPS_BUCKBOOST_RANGE ((float)0.5) + +/* PID controller configuration */ + +#define PID_KP ((float)1.0) +#define PID_KI ((float)0.1) +#define PID_KD ((float)0.0) + +/* Converter frequencies: + * - TIMA_PWM_FREQ - buck converter 250kHz + * - TIMB_PWM_FREQ - boost converter 250kHz + */ + +#define TIMA_PWM_FREQ 250000 +#define TIMB_PWM_FREQ 250000 + +/* Deadtime configuration */ + +#define DT_RISING 0x0A0 +#define DT_FALLING 0x0A0 + +/* Helper macros */ + +#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMA_CH1|HRTIM_OUT_TIMA_CH2| \ + HRTIM_OUT_TIMB_CH1|HRTIM_OUT_TIMB_CH2, state); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Current converter mode */ + +enum converter_mode_e +{ + CONVERTER_MODE_INIT, /* Initial mode */ + CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ + CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ + CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ +}; + +/* SMPS lower drivers structure */ + +struct smps_lower_dev_s +{ + struct hrtim_dev_s *hrtim; /* PWM generation */ + struct stm32_adc_dev_s *adc; /* input and output voltage sense */ + struct comp_dev_s *comp; /* not used in this demo - only as reference */ + struct dac_dev_s *dac; /* not used in this demo - only as reference */ + struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ +}; + +/* Private data for smps */ + +struct smps_priv_s +{ + uint8_t conv_mode; /* Converter mode */ + uint16_t v_in_raw; /* Voltage input RAW value */ + uint16_t v_out_raw; /* Voltage output RAW value */ + float v_in; /* Voltage input real value in V */ + float v_out; /* Voltage output real value in V */ + bool running; /* Running flag */ + pid_controller_f32_t pid; /* PID controller */ + float *c_limit_tab; /* Current limit tab */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev); +static int smps_shutdown(struct smps_dev_s *dev); +static int smps_start(struct smps_dev_s *dev); +static int smps_stop(struct smps_dev_s *dev); +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param); +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits); +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state); +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); +static int smps_fault_get(struct smps_dev_s *dev, + uint8_t *fault); +static int smps_fault_clean(struct smps_dev_s *dev, + uint8_t fault); +static int smps_ioctl(struct smps_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct smps_lower_dev_s g_smps_lower; +struct smps_priv_s g_smps_priv; +struct smps_s g_smps; + +struct smps_ops_s g_smps_ops = +{ + .setup = smps_setup, + .shutdown = smps_shutdown, + .start = smps_start, + .stop = smps_stop, + .params_set = smps_params_set, + .mode_set = smps_mode_set, + .limits_set = smps_limits_set, + .fault_set = smps_fault_set, + .state_get = smps_state_get, + .fault_get = smps_fault_get, + .fault_clean = smps_fault_clean, + .ioctl = smps_ioctl +}; + +struct smps_dev_s g_smps_dev = +{ + .ops = &g_smps_ops, + .priv = &g_smps, + .lower = NULL +}; + +/* ADC configuration: + * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) + * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) + * + * ADC channels configured in injected mode. + * + * Transistors configuration in buck mode: + * - T5 - ON + * - T12 - OFF + * - T4 and T11 - buck operation + * Transistors configuration in boost mode: + * - T4 - ON + * - T11 - OFF + * - T5 and T12 - boost operation + * Transistors configuration in buck-boost mode: + * - T4, T11 - buck operation + * - T5 and T12 - boost operation + * + * HRTIM outputs configuration: + * - T4 -> PA8 -> HRTIM_CHA1 + * - T5 -> PA11 -> HRTIM_CHB2 + * - T11 -> PA9 -> HRTIM_CHA2 + * - T12 -> PA10 -> HRTIM_CHB1 + * + */ + +/* ADC channel list */ + +static const uint8_t g_adc1chan[ADC1_NCHANNELS] = +{ + 2, + 4 +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_adc1pins[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN2_0, /* PA1 - V_IN */ + GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int smps_shutdown(struct smps_dev_s *dev) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + + /* Stop smps if running */ + + if (priv->running == true) + { + smps_stop(dev); + } + + /* Reset smps structure */ + + memset(smps, 0, sizeof(struct smps_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_setup + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct hrtim_dev_s *hrtim = NULL; + struct stm32_adc_dev_s *adc = NULL; + struct smps_priv_s *priv; + struct adc_channel_s channels[ADC1_NCHANNELS]; + struct adc_sample_time_s stime; + int ret = OK; + int i = 0; + + /* Initialize smps structure */ + + smps->opmode = SMPS_OPMODE_INIT; + smps->state.state = SMPS_STATE_INIT; + smps->priv = &g_smps_priv; + + /* Check lower half drivers */ + + hrtim = lower->hrtim; + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get hrtim "); + ret = ERROR; + goto errout; + } + + adc = lower->adc; + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC lower level interface"); + ret = ERROR; + goto errout; + } + + /* Update ADC sample time */ + + for (i = 0; i < ADC1_NCHANNELS; i += 1) + { + channels[i].sample_time = ADC_SMPR_61p5; + channels[i].channel = g_adc1chan[i]; + } + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ADC1_NCHANNELS; + stime.channel = channels; + + STM32_ADC_SAMPLETIME_SET(adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(adc); + + /* TODO: create current limit table */ + + UNUSED(priv); + +errout: + return ret; +} + +static int smps_start(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + volatile uint64_t per = 0; + uint64_t fclk = 0; + int ret = OK; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Reset SMPS private structure */ + + memset(priv, 0, sizeof(struct smps_priv_s)); + +#ifdef SMPS_CONTROLLER_PID + /* Initialize PID controller */ + + pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); + + /* Set PID controller saturation */ + + pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); + + /* Reset PI integral if saturated */ + + pi_ireset_enable(&priv->pid, true); +#endif + + /* Get TIMA period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMA); + per = fclk / TIMA_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve tima pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMA_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMA period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMA, (uint16_t)per); + + /* Get TIMB period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMB); + per = fclk / TIMB_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timb pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMB_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMB period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMB, (uint16_t)per); + + /* ADC trigger on TIMA CMP4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP4, 10000); + + /* Configure TIMER A and TIMER B deadtime mode + * + * NOTE: In deadtime mode we have to configure output 1 only + * (SETx1, RSTx1), output 2 configuration is not significant. + */ + + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMA, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMB, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + + /* Set T4 and T12 to a low state. + * Deadtime mode force T11 and T5 to a high state. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, HRTIM_OUT_RST_PER); + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, HRTIM_OUT_RST_PER); + + /* Set running flag */ + + priv->running = true; + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); + + /* Enable ADC JEOS interrupts */ + + STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); + + /* Enable ADC12 interrupts */ + + up_enable_irq(STM32_IRQ_ADC12); + + /* Start injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, true); + +errout: + return ret; +} + +static int smps_stop(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Stop injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, false); + + /* Disable ADC JEOS interrupts */ + + STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); + + /* Disable ADC12 interrupts */ + + up_disable_irq(STM32_IRQ_ADC12); + + /* Reset running flag */ + + priv->running = false; + + return OK; +} + +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only output voltage */ + + smps->param.v_out = param->v_out; + + /* REVISIT: use current and power parameters ? */ + + if (param->i_out > 0) + { + pwrwarn("WARNING: Output current parameters not used in this demo\n"); + } + + if (param->p_out > 0) + { + pwrwarn("WARNING: Output power parameters not used in this demo\n"); + } + + return ret; +} + +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only constant voltage mode supported */ + + if (mode == SMPS_OPMODE_CV) + { + smps->opmode = mode; + } + else + { + pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Some assertions */ + + if (limits->v_out <= 0) + { + pwrerr("ERROR: Output voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_in <= 0) + { + pwrerr("ERROR: Input voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->i_out <= 0) + { + pwrerr("ERROR: Output current limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) + { + limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output voltage limiit > SMPS absolute output voltage " + "limit. Set output voltage limit to %.2f.\n", + limits->v_out); + } + + if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) + { + limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS input voltage limiit > SMPS absolute input voltage " + "limit. Set input voltage limit to %.2f.\n", + limits->v_in); + } + + if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) + { + limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output current limiit > SMPS absolute output current " + "limit. Set output current limit to %.2f.\n", + limits->i_out); + } + + /* Set output voltage limit */ + + smps->limits.v_out = limits->v_out; + + /* Set input voltage limit */ + + smps->limits.v_in = limits->v_in; + + /* Set current limit */ + + smps->limits.i_out = limits->i_out; + + /* Lock limits */ + + smps->limits.lock = true; + +errout: + return ret; +} + +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + + /* Copy locally stored feedbacks data to status structure */ + + smps->state.fb.v_in = g_smps_priv.v_in; + smps->state.fb.v_out = g_smps_priv.v_out; + + /* Return state structure to caller */ + + memcpy(state, &smps->state, sizeof(struct smps_state_s)); + + return OK; +} + +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) +{ + return OK; +} + +static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_controller + ****************************************************************************/ + +static float smps_controller(struct smps_priv_s *priv, float err) +{ + float out = 0.0; + +#ifdef SMPS_CONTROLLER_PID + out = pid_controller(&priv->pid, err); +#else +# error "At this time only PID controller implemented" +#endif + + return out; +} + +/**************************************************************************** + * Name: smps_duty_set + ****************************************************************************/ + +static void smps_duty_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + float out) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + uint8_t mode = priv->conv_mode; + uint16_t cmp = 0; + float duty = 0.0; + uint16_t per = 0; + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + /* Do nothing */ + + break; + } + + case CONVERTER_MODE_BUCK: + { + if (out >= priv->v_in) out = priv->v_in; + if (out < 0.0) out = 0.0; + + duty = out / priv->v_in; + +#warning TODO: current limit in buck mode + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + cmp = (uint16_t)(per * duty); + + if (cmp > per - 30) cmp = per - 30; + + /* Set T4 duty cycle. T11 is complementary to T4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BOOST: + { + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T12 duty cycle. T5 is complementary to T12 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Buck converter is set to fixed duty cycle (80%). + * Now we need set boost converter + */ + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMA); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in buck boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T12 duty cycle. T5 is complementary to T12 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMB, HRTIM_CMP1, cmp); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } +} + +/**************************************************************************** + * Name: smps_conv_mode_set + * + * Description: + * Change converter mode (buck/boost/buck-boost). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + + /* Disable all outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + break; + } + + case CONVERTER_MODE_BUCK: + { + /* Set T12 low (T5 high) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_PER); + + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BOOST: + { + /* Set T4 high (T11 low) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_NONE); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMA_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMB_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMA, HRTIM_CMP1, + 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, + HRTIM_TIMER_TIMA))); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } + + /* Set mode in private data */ + + priv->conv_mode = mode; + + /* Enable outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); +} + +/**************************************************************************** + * Name: adc12_handler + ****************************************************************************/ + +static void adc12_handler(void) +{ + struct smps_dev_s *dev = &g_smps_dev; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct smps_lower_dev_s *lower = dev->lower; + struct stm32_adc_dev_s *adc = lower->adc; + uint32_t pending; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + float err; + float out; + uint8_t mode; + + pending = STM32_ADC_INT_GET(adc); + + if (pending & ADC_INT_JEOC && priv->running == true) + { + /* Get raw ADC values */ + + priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); + priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); + + /* Convert raw values to real values */ + + priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; + priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; + + /* According to measured voltages we set converter + * in appropriate mode + */ + + if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage greater than input voltage - set + * boost converter + */ + + mode = CONVERTER_MODE_BOOST; + } + + else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage lower than input voltage - set + * buck converter + */ + + mode = CONVERTER_MODE_BUCK; + } + + else + { + /* Desired output voltage close to input voltage - set + * buck-boost converter + */ + + mode = CONVERTER_MODE_BUCKBOOST; + } + + /* Configure converter to the new mode if needed */ + + if (priv->conv_mode != mode) + { + smps_conv_mode_set(priv, lower, mode); + } + + /* Get regulator error */ + + err = smps->param.v_out - priv->v_out; + + if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) + { + /* PID controller */ + + out = smps_controller(priv, err); + + /* Update duty cycle */ + + smps_duty_set(priv, lower, out); + } + } + + /* Clear pending */ + + STM32_ADC_INT_ACK(adc, pending); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_smps_setup(void) +{ + struct smps_lower_dev_s *lower = &g_smps_lower; + struct smps_dev_s *smps = &g_smps_dev; + struct hrtim_dev_s *hrtim = NULL; + struct adc_dev_s *adc = NULL; + static bool initialized = false; + int ret = OK; + int i; + + /* Initialize only once */ + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1pins[i]); + } + + /* Get the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC %d interface\n", 1); + return -ENODEV; + } + + /* Initialize SMPS lower driver interfaces */ + + lower->hrtim = hrtim; + lower->adc = adc->ad_priv; + lower->comp = NULL; + lower->dac = NULL; + lower->opamp = NULL; + + /* Attach ADC12 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Setup ADC hardware */ + + adc->ad_ops->ao_setup(adc); + + /* We do not need register character drivers for SMPS lower + * peripherals. All control should be done via SMPS character + * driver. + */ + + ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); + if (ret < 0) + { + pwrerr("ERROR: smps_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + +errout: + return ret; +} + +#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h rename to boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h index 213f549b42778..0aac0ea8e6c43 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h + * boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt new file mode 100644 index 0000000000000..898b9836865dd --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/Kconfig b/boards/arm/stm32f3/stm32f3discovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f3discovery/Kconfig rename to boards/arm/stm32f3/stm32f3discovery/Kconfig diff --git a/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..e05647d329bb3 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f3discovery" +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=40960 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..ca4b9b582409e --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f3discovery" +CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f3" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=40960 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USB=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f3/stm32f3discovery/include/board.h b/boards/arm/stm32f3/stm32f3discovery/include/board.h new file mode 100644 index 0000000000000..0e989224f4505 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/include/board.h @@ -0,0 +1,275 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - Internal 8 MHz RC Oscillator + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* X1 on board */ + +#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL source is HSE/1, + * PLL multiplier is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ + +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLXTPRE 0 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9 +#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL) + +/* Use the PLL and set the SYSCLK source to be the PLL */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (72MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (72MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */ + +/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 PWR: red LED indicates that the board is powered. + * LD2 COM: LD2 default status is red. LD2 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2. + * + * And eight can be controlled by software: + * + * User LEDs connected to the I/O of the STM32F303VCT6. + * User LD3: red LED is a user LED connected to the PE9 I/O. + * User LD4: blue LED is a user LED connected to the PE8 I/O. + * User LD5: orange LED is a user LED connected to the PE10 I/O. + * User LD6: green LED is a user LED connected to the PE15 I/O. + * User LD7: green LED is a user LED connected to the PE11 I/O. + * User LD8: orange LED is a user LED connected to the PE14 I/O. + * User LD9: blue LED is a user LED connected to the PE12 I/O. + * User LD10: red LED is a user LED connected to the PE13 I/O. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_LED3 2 /* User LD5 */ +#define BOARD_LED4 3 /* User LD6 */ +#define BOARD_LED5 4 /* User LD7 */ +#define BOARD_LED6 5 /* User LD8 */ +#define BOARD_LED7 6 /* User LD9 */ +#define BOARD_LED8 7 /* User LD10 */ +#define BOARD_NLEDS 8 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) +#define BOARD_LED5_BIT (1 << BOARD_LED5) +#define BOARD_LED6_BIT (1 << BOARD_LED6) +#define BOARD_LED7_BIT (1 << BOARD_LED7) +#define BOARD_LED8_BIT (1 << BOARD_LED8) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on + * board the stm32f3discovery. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * Initially all LEDs are OFF + * ------------------- ----------------------- ------------- ------------ + * LED_STARTED NuttX has been started LD3 ON + * LED_HEAPALLOCATE Heap has been allocated LD4 ON + * LED_IRQSENABLED Interrupts enabled LD4 ON + * LED_STACKCREATED Idle stack created LD6 ON + * LED_INIRQ In an interrupt LD7 should glow + * LED_SIGNAL In a signal handler LD8 might glow + * LED_ASSERTION An assertion failed LD9 ON while handling + * the assertion + * LED_PANIC The system has crashed LD10 Blinking at 2Hz + * LED_IDLE STM32 is in sleep mode (Optional, not used) + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 1 +#define LED_IRQSENABLED 2 +#define LED_STACKCREATED 3 +#define LED_INIRQ 4 +#define LED_SIGNAL 5 +#define LED_ASSERTION 6 +#define LED_PANIC 7 + +/* Button definitions *******************************************************/ + +/* The STM32F3Discovery supports two buttons; only one button is controllable + * by software: + * + * B1 USER: + * user and wake-up button connected to the I/O PA0 of the + * STM32F303VCT6. + * B2 RESET: + * pushbutton connected to NRST is used to RESET the STM32F303VCT6. + */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART + * + * USART1: Hardwired to embedded STLinkV2 hardware debugger + * RX (PC5) + * TX (PC4) + * + * USART2: + * Connect to an external UART<->RS232 transceiver for use as console. + * RX (PA3) + * TX (PA2) + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_50MHz) + +/* SPI + * + * SPI1: Hardwired to ST L3GD20 MEMS device + * MISO (PA6) + * MSOI (PA7) + * SCK (PA5) + */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* I2C + * + * I2C1: Accessible via expansion headers + * SCL (PA15) + * SDA (PA14) + * SMBA (PB5) + * + * I2C2: Accessible via expansion headers + * SCL (PA9) + * SDA (PA10) + * SMBA (PB12) + */ + +#ifdef CONFIG_STM32_I2C1 +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) +#endif + +#ifdef CONFIG_STM32_I2C2 +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#endif + +/* USB */ + +#define GPIO_USB_DM (GPIO_USB_DM_0|GPIO_SPEED_50MHz) +#define GPIO_USB_DP (GPIO_USB_DP_0|GPIO_SPEED_50MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs new file mode 100644 index 0000000000000..be421233cda68 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script new file mode 100644 index 0000000000000..a54ec9fcb66f1 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F303VCT has 256Kb of FLASH beginning at address 0x0800:0000 and + * 40Kb of SRAM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..b630617db143d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_USB) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f3/stm32f3discovery/src/Make.defs b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs new file mode 100644 index 0000000000000..726b069c0ef0d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32f3/stm32f3discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..a88f93396fb4a --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, + GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_onoff + ****************************************************************************/ + +void board_autoled_onoff(int led, bool state) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], state); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + board_autoled_onoff(led, true); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + board_autoled_onoff(led, false); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..88ceb8fb8611d --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f3discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB if the 1) USB device controller is in the configuration + * and 2) disabled, and 3) the weak function stm32_usbinitialize() has + * been brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + +#ifdef CONFIG_STM32_USB + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..4b4f5a63b7323 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBMONITOR 1 + +/* Can't support USB device features if the STM32 USB peripheral is not + * enabled. + */ + +#ifndef CONFIG_STM32_USB +# undef HAVE_USBDEV +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32F3DISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..b95f1899118dc --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f3discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..132b6bbdf5630 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f3discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f3discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. This pin is used + * by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c new file mode 100644 index 0000000000000..9b9e324250dd4 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f3discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ + stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ + stm32_configgpio(GPIO_MEMS_INT2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + stm32_gpiowrite(GPIO_MEMS_CS, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c new file mode 100644 index 0000000000000..7084ab7babdea --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifdef CONFIG_STM32_USB + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_USB is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F3Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* Does the STM32 F3 have an external soft pull-up? */ +} + +/**************************************************************************** + * Name: stm32_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. + * See include/nuttx/usb/usbdev.h for additional description of this + * method. + * + ****************************************************************************/ + +int stm32_usbpullup(struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + return OK; +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("Resume: %d\n", resume); +} + +#endif /* CONFIG_STM32_USB */ diff --git a/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..f38041a78a167 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f3discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4, + GPIO_LED5, GPIO_LED6, GPIO_LED7, GPIO_LED8 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-8 GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h rename to boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h index 44464bcf3a854..79b1062803433 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h + * boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include -#include +#include #include "stm32.h" diff --git a/boards/arm/stm32f4/axoloti/CMakeLists.txt b/boards/arm/stm32f4/axoloti/CMakeLists.txt new file mode 100644 index 0000000000000..83d2d132d5d67 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/axoloti/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/axoloti/Kconfig b/boards/arm/stm32f4/axoloti/Kconfig similarity index 100% rename from boards/arm/stm32/axoloti/Kconfig rename to boards/arm/stm32f4/axoloti/Kconfig diff --git a/boards/arm/stm32f4/axoloti/configs/nsh/defconfig b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig new file mode 100644 index 0000000000000..00ea1126c4189 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig @@ -0,0 +1,40 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="axoloti" +CONFIG_ARCH_BOARD_AXOLOTI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F427I=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_MM_REGIONS=2 +CONFIG_RAW_BINARY=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART6_BAUD=31250 +CONFIG_USART6_RXBUFSIZE=128 +CONFIG_USART6_TXBUFSIZE=32 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f4/axoloti/include/board.h b/boards/arm/stm32f4/axoloti/include/board.h new file mode 100644 index 0000000000000..07a076bda5aa6 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/include/board.h @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Clocking + * The Axoloti board has an external 8MHz crystal. + * The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be + * configured at that system clock rate, so the core clock is 168MHz. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, + * SDIO and RNG clock : Enabled + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/**************************************************************************** + * LED Definitions + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_RED BOARD_LED2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/**************************************************************************** + * Button Definitions + * There are two buttons on the axoloti, one of them is GPIO connected. The + * other is a reset button and is not under software control. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/**************************************************************************** + * UARTs + * The MIDI in/out ports of the axoloti are connected on USART6. + * It maybe convenient to run a serial port connected to the header pins, + * so we can optionally use USART1 for that. + */ + +/* USART1 - console on header pins */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* AF7, PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* AF7, PB6 */ + +/* USART6 - midi in/out */ + +#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \ + GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL) + +#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \ + GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN) + +/**************************************************************************** + * I2C Bus + * Turn on the internal pullups since there are no external pullups. + */ + +/* I2C1 - for external devices */ + +#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +#define GPIO_I2C1_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +/* I2C3 - for the ADAU1961 codec */ + +#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \ + GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP) + +/**************************************************************************** + * SAI Bus + * Used with the ADAU1961 CODEC + * PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1) + * PE4_SAI1_FS_A (GPIO_SAI1_FS_A) + * PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A) + * PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2) + * PA8_MCO1 + */ + +#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */ +#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */ + +#define STM32_SAI1_FREQUENCY (48000 * 2 * 256) /* TODO ?? */ + +/* DAC DMA to Codec + * dma 2, stream 1, channel 0 + * memory to peripheral + * 32 bits + */ +#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1 + +/* ADC DMA from Codec + * dma 2, stream 4, channel 1, + * peripheral to memory + * 32 bits + */ +#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2 + +/**************************************************************************** + * SDIO + * Used for the SD card interface. + * d0 (AF12, PC8) + * d1 (AF12, PC9) + * d2 (AF12, PC10) + * d3 (AF12, PC11) + * clk (AF12, PC12) + * cmd (AF12, PD2) + * cd1 PD13 + */ + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* dma 2, stream 6, channel 4 */ + +#define DMAMAP_SDIO DMAMAP_SDIO_2 + +#endif /* __BOARDS_ARM_STM32_AXOLOTI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/axoloti/scripts/Make.defs b/boards/arm/stm32f4/axoloti/scripts/Make.defs new file mode 100644 index 0000000000000..9f486f1452db0 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/axoloti/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld new file mode 100644 index 0000000000000..f87d33f4f4417 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/scripts/ld.script b/boards/arm/stm32f4/axoloti/scripts/ld.script new file mode 100644 index 0000000000000..72142ae7d5a12 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/ld.script @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and + * 256KiB of SRAM. SRAM is split up into four blocks: + * + * 1) 112KiB of SRAM beginning at address 0x2000:0000 + * 2) 16KiB of SRAM beginning at address 0x2001:c000 + * 3) 64KiB of SRAM beginning at address 0x2002:0000 + * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/scripts/memory.ld b/boards/arm/stm32f4/axoloti/scripts/memory.ld new file mode 100644 index 0000000000000..a168b907bc879 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and + * 256KiB of SRAM. SRAM is split up into four blocks: + * + * 1) 112KiB of SRAM beginning at address 0x2000:0000 + * 2) 16KiB of SRAM beginning at address 0x2001:c000 + * 3) 64KiB of SRAM beginning at address 0x2002:0000 + * 4) 64KiB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/axoloti/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/axoloti/scripts/user-space.ld b/boards/arm/stm32f4/axoloti/scripts/user-space.ld new file mode 100644 index 0000000000000..c5b08c5f8471b --- /dev/null +++ b/boards/arm/stm32f4/axoloti/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/axoloti/src/CMakeLists.txt b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt new file mode 100644 index 0000000000000..e1eb12177d57a --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt @@ -0,0 +1,53 @@ +# ############################################################################## +# boards/arm/stm32f4/axoloti/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_AUDIO_ADAU1961) + list(APPEND SRCS stm32_adau1961.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_USBHOST) + list(APPEND SRCS stm32_usbhost.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/axoloti/src/Make.defs b/boards/arm/stm32f4/axoloti/src/Make.defs new file mode 100644 index 0000000000000..69fd26fb33db0 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/Make.defs @@ -0,0 +1,55 @@ +############################################################################ +# boards/arm/stm32f4/axoloti/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_STM32_FMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_AUDIO_ADAU1961),y) +CSRCS += stm32_adau1961.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_USBHOST),y) +CSRCS += stm32_usbhost.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/axoloti/src/axoloti.h b/boards/arm/stm32f4/axoloti/src/axoloti.h similarity index 99% rename from boards/arm/stm32/axoloti/src/axoloti.h rename to boards/arm/stm32f4/axoloti/src/axoloti.h index d6a2c7ac57707..2554ef11df13c 100644 --- a/boards/arm/stm32/axoloti/src/axoloti.h +++ b/boards/arm/stm32f4/axoloti/src/axoloti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/axoloti.h + * boards/arm/stm32f4/axoloti/src/axoloti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/axoloti/src/stm32_adau1961.c b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c similarity index 99% rename from boards/arm/stm32/axoloti/src/stm32_adau1961.c rename to boards/arm/stm32f4/axoloti/src/stm32_adau1961.c index 1d3851ba296a4..30fbef9abdd3f 100644 --- a/boards/arm/stm32/axoloti/src/stm32_adau1961.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_adau1961.c + * boards/arm/stm32f4/axoloti/src/stm32_adau1961.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/axoloti/src/stm32_boot.c b/boards/arm/stm32f4/axoloti/src/stm32_boot.c new file mode 100644 index 0000000000000..2eb3a1596fb26 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_boot.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "axoloti.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_OTGFS) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/axoloti/src/stm32_bringup.c b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c new file mode 100644 index 0000000000000..f110e09055822 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGHS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "axoloti.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#ifdef HAVE_SDRAM + /* Initialize access to the SDRAM device */ + + ret = stm32_sdram_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_sdram_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_sdio_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_usbhost_initialize failed %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "usbmonitor_start failed %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "btn_lower_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_REI2C + /* Register the rei2c driver */ + + ret = rei2c_initialize("/dev/re0"); + if (ret < 0) + { + syslog(LOG_ERR, "rei2c_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "userled_lower_initialize failed %d\n", ret); + } +#endif + +#ifdef HAVE_ADAU1961 + /* Configure ADAU1961 audio */ + + ret = stm32_adau1961_initialize(1); + if (ret != OK) + { + syslog(LOG_ERR, "stm32_adau1961_initialize failed %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "failed to mount procfs at %s %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/axoloti/src/stm32_buttons.c b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c new file mode 100644 index 0000000000000..5ec7863e74cdf --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "axoloti.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each axoloti button. This array is indexed by + * the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. + * EXTI interrupts are configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A HI value means that the key is pressed. */ + + bool pressed = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (pressed) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = + stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_extmem.c b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c new file mode 100644 index 0000000000000..496b14c757d89 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "axoloti.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FMC +#warning "FMC is not enabled" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Axoloti SDRAM GPIO configuration */ + +static const uint32_t g_sdram_config[] = +{ + /* Data lines */ + + GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, + GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, + GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, + GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, + + /* Address lines */ + + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, + GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, + GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + GPIO_FMC_A12, + + /* Control lines */ + + GPIO_FMC_BA0, /* ba0 */ + GPIO_FMC_BA1, /* ba1 */ + GPIO_FMC_NBL0, /* ldqm */ + GPIO_FMC_NBL1, /* udqm */ + GPIO_FMC_SDCLK, /* clk */ + GPIO_FMC_SDCKE0_1, /* cke */ + GPIO_FMC_SDNWE_2, /* we */ + GPIO_FMC_SDNCAS, /* cas */ + GPIO_FMC_SDNRAS, /* ras */ + GPIO_FMC_SDNE0_1, /* cs0 */ + GPIO_FMC_SDNE1_2, /* cs1 */ +}; + +#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdram_memtest + * + * Description: + * Test the SDRAM. + * + ****************************************************************************/ + +#define RAND_A 22695477 +#define RAND_C 1 +#define TEST_ITERATIONS 16 + +int stm32_sdram_memtest(void *base, uint32_t size) +{ + volatile int iter; + volatile int i; + + /* Linear write with linear congruential generator values */ + + for (iter = 0; iter < TEST_ITERATIONS; iter++) + { + uint32_t x = iter; + + /* Write */ + + for (i = 0; i < size / 4; i++) + { + x = (RAND_A * x) + RAND_C; + ((volatile uint32_t *)base)[i] = x; + } + + /* Read/verify */ + + x = iter; + for (i = 0; i < size / 4; i++) + { + x = (RAND_A * x) + RAND_C; + if (((volatile uint32_t *)base)[i] != x) + { + return -1; + } + } + } + + /* Scattered byte write at linear congruential generator addresses */ + + for (iter = 0; iter < TEST_ITERATIONS; iter++) + { + uint32_t x = iter; + + /* Write */ + + for (i = 0; i < 1024 * 1024; i++) + { + x = (RAND_A * x) + RAND_C; + ((volatile uint8_t *)base)[x & (size - 1)] = (uint8_t) i; + } + + /* Read/verify */ + + x = iter; + for (i = 0; i < 1024 * 1024; i++) + { + x = (RAND_A * x) + RAND_C; + if (((volatile uint8_t *)base)[x & (size - 1)] != (uint8_t) i) + { + return -1; + } + } + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_sdram_initialize + * + * Description: + * Called from stm32_bringup to initialize external SDRAM access. + * The Axoloti uses an Alliance Memory AS4C4M16SA SDRAM. + * + ****************************************************************************/ + +int stm32_sdram_initialize(void) +{ + uint32_t val; + int i; + + /* Configure SDRAM GPIOs */ + + for (i = 0; i < NUM_SDRAM_GPIOS; i++) + { + stm32_configgpio(g_sdram_config[i]); + } + + /* Enable the FMC */ + + stm32_fmc_enable(); + + /* Go through the SDRAM initialization steps per the reference manual. + * The sdclk period is set to 2 x hclk. That is: 168 /2 = 84 MHz + * This gives a clock period of about 11.9 ns + */ + + /* Step 1: + * Program the memory device features into the FMC_SDCRx register. The + * SDRAM clock frequency, RBURST and RPIPE must be programmed in the + * FMC_SDCR1 register. + */ + + val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ + FMC_SDCR_READBURST | /* read burst enabled */ + FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ + FMC_SDCR_CAS_LATENCY_2 | /* cas latency = 2 cycles */ + FMC_SDCR_NBANKS_4 | /* 4 internal banks */ + FMC_SDCR_WIDTH_16 | /* width = 16 bits */ + FMC_SDCR_ROWS_12 | /* numrows = 12 */ + FMC_SDCR_COLS_8; /* numcols = 8 bits */ + stm32_fmc_sdram_set_control(1, val); + + /* Step 2: + * Program the memory device timing into the FMC_SDTRx register. The + * TRP and TRC timings must be programmed in the FMC_SDTR1 register. + */ + + val = FMC_SDTR_TRCD(2) | /* ras to cas delay 21ns => 2x11.90ns */ + FMC_SDTR_TRP(2) | /* row precharge 21ns => 2x11.90ns */ + FMC_SDTR_TRC(6) | /* row cycle time 63ns => 6x11.9ns */ + FMC_SDTR_TRAS(4) | /* row active time 42ns = >4x11.9ns */ + FMC_SDTR_TWR(4) | /* write to precharge 42ns => 4x11.9ns */ + FMC_SDTR_TXSR(6) | /* exit self refresh 65ns => 6x11.9ns */ + FMC_SDTR_TMRD(2); /* load mode register to active 2 clks */ + stm32_fmc_sdram_set_timing(1, val); + + /* Step 3: + * Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 + * and/or CTB2) in the FMC_SDCMR register to start delivering the clock + * to the memory (SDCKE is driven high). + */ + + val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_CLK_ENABLE; + stm32_fmc_sdram_command(val); + + /* Step 4: + * Wait during the prescribed delay period. Typical delay is around 100 + * μs (refer to the SDRAM datasheet for the required delay after + * power-up). + */ + + nxsched_usleep(1000); + + /* Step 5: + * Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 + * and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All” + * command. + */ + + val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_PALL; + stm32_fmc_sdram_command(val); + + /* Step 6: + * Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 + * and/or CTB2) as well as the number of consecutive Auto-refresh + * commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM + * datasheet for the number of Auto-refresh commands that should be + * issued. Typical number is 8. + */ + + val = FMC_SDCMR_NRFS(5) | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_AUTO_REFRESH; + stm32_fmc_sdram_command(val); + + /* Step 7: + * Configure the MRD field according to your SDRAM device, set the MODE + * bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2) + * in the FMC_SDCMR register to issue a "Load Mode Register" command in + * order to program the SDRAM. In particular: + * a) The CAS latency must be selected following configured value in + * FMC_SDCR1/2 registers + * b) The Burst Length (BL) of 1 must be selected by configuring the + * M[2:0] bits to 000 in the mode register (refer to the SDRAM + * datasheet). If the Mode Register is not the same for both SDRAM + * banks, this step has to be repeated twice, once for each bank, + * and the Target Bank bits set accordingly. + */ + + val = FMC_SDCMR_MDR_BURST_LENGTH_2 | + FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MDR_CAS_LATENCY_2 | + FMC_SDCMR_MDR_MODE_NORMAL | + FMC_SDCMR_MDR_WBL_SINGLE | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_LOAD_MODE; + stm32_fmc_sdram_command(val); + + /* Step 8: + * Program the refresh rate in the FMC_SDRTR register + * The refresh rate corresponds to the delay between refresh cycles. Its + * value must be adapted to SDRAM devices. + */ + + stm32_fmc_sdram_set_refresh_rate(1292); /* (64ms/4096rows) x 84MHz) - 20 */ + + /* Step 9: + * For mobile SDRAM devices, to program the extended mode register it + * should be done once the SDRAM device is initialized: First, a dummy + * read access should be performed while BA1=1 and BA=0 (refer to SDRAM + * address mapping section for BA[1:0] address mapping) in order to select + * the extended mode register instead of Load mode register and then + * program the needed value. + */ + + /* Setting EMRS is optional and we're not bothering ... */ + + /* Enable memory writes for bank 1 */ + + stm32_fmc_sdram_write_protect(1, false); + + /* Wait for the controller to be ready */ + + stm32_fmc_sdram_wait(); + return OK; +} diff --git a/boards/arm/stm32f4/axoloti/src/stm32_sdio.c b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c new file mode 100644 index 0000000000000..35236a2039c14 --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "axoloti.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +#undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver. + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c new file mode 100644 index 0000000000000..94aed1ef76b3b --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c @@ -0,0 +1,265 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_usbhost.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otghs.h" +#include "axoloti.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +#define HAVE_USB 1 +#else +#warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#undef HAVE_USB +#endif + +#ifndef CONFIG_AXOLOTI_USBHOST_PRIO +#define CONFIG_AXOLOTI_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_AXOLOTI_USBHOST_STACKSIZE +#define CONFIG_AXOLOTI_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + uinfo("Running\n"); + + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Axoloti board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided + * be each platform that implements the STM32 OTG HS host interface + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should + * be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + ret = kthread_create("usbhost", CONFIG_AXOLOTI_USBHOST_PRIO, + CONFIG_AXOLOTI_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/axoloti/src/stm32_userleds.c b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c new file mode 100644 index 0000000000000..b6825a8b06b2a --- /dev/null +++ b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f4/axoloti/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "axoloti.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt new file mode 100644 index 0000000000000..c6fa956e228ba --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/clicker2-stm32/Kconfig b/boards/arm/stm32f4/clicker2-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/clicker2-stm32/Kconfig rename to boards/arm/stm32f4/clicker2-stm32/Kconfig diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig new file mode 100644 index 0000000000000..3f73f847e27d5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/clicker2-stm32/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig new file mode 100644 index 0000000000000..d468e8c135bef --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -0,0 +1,109 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig new file mode 100644 index 0000000000000..37c9d51ec17c5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig new file mode 100644 index 0000000000000..9906db1241ab4 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -0,0 +1,94 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_TELNET=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STAR=y +CONFIG_NET_STARHUB=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig new file mode 100644 index 0000000000000..6f66c0144f9b1 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -0,0 +1,110 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="MRF24J40" +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STAR=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig new file mode 100644 index 0000000000000..50e12a7f9e480 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..33748ef3ecab5 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=3 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_INTBUFSIZE=396 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig new file mode 100644 index 0000000000000..853fec364b7df --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -0,0 +1,105 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="clicker2-stm32" +CONFIG_ARCH_BOARD_CLICKER2_STM32=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CLICKER2_STM32_MB1_XBEE=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_NETTEST_SERVERIPv6ADDR_8=0x0800 +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_1=0xfe80 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_6=0x00ff +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_7=0xfe00 +CONFIG_EXAMPLES_UDP_SERVERIPv6ADDR_8=0x0d00 +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_XBEE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LIBC_HOSTNAME="XBee" +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=160 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/clicker2-stm32/include/board.h b/boards/arm/stm32f4/clicker2-stm32/include/board.h new file mode 100644 index 0000000000000..5234be7f4f8b6 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/include/board.h @@ -0,0 +1,321 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC + * crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* The Mikroe Clicker2 STM32 has two user controllable LEDs: + * + * LD1 - PE12, Active high output illuminates + * LD2 - PE15, Active high output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the Clicker2 for STM32. + * The following definitions describe how NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt N/C ON + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 3 +#define LED_ASSERTION 3 +#define LED_PANIC 4 + +/* Button definitions *******************************************************/ + +/* The Mikroe Clicker2 STM32 has two buttons available to software: + * + * T2 - PE0, Low sensed when pressed + * T3 - PA10, Low sensed when pressed + */ + +#define BUTTON_T2 0 +#define BUTTON_T3 1 +#define NUM_BUTTONS 2 + +#define BUTTON_T2_BIT (1 << BUTTON_T2) +#define BUTTON_T3_BIT (1 << BUTTON_T3) + +/* Alternate function pin selections ****************************************/ + +/* U[S]ARTs + * + * USART2 - mikroBUS1 + * USART3 - mikroBUS2 + * + * Assuming RS-232 connverted connected on mikroMB1/12 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ + +/* SPI + * + * SPI2 - mikroBUS2 + * SPI3 - mikroBUS1 + */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PC12 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PC11 */ +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PB15 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PB14 */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ + +/* I2C + * + * I2C2 - mikroBUS2 + * I2C3 - mikroBUS1 + */ + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) /* PB10 */ +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) /* PB11 */ + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) /* PC9 */ + +/* Analog + * + * mikroBUS1 ADC: PA2-MB1_AN + * mikroBUS1 ADC: PA3-MB2_AN + */ + +/* PWM + * + * mikroBUS1 ADC: PE9-MB1-PWM (TIM1, channel 1) + * mikroBUS1 ADC: PD12-MB2-PWM (TIM4, channel 1) + */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_2|GPIO_SPEED_50MHz) /* PD12 */ + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_CLICKER2_STM32_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile new file mode 100644 index 0000000000000..2f5b6553e7264 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..fcaa153b6704d --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by + * the linker script. + */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs new file mode 100644 index 0000000000000..a90d88a34ec92 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld new file mode 100644 index 0000000000000..4615162c950c8 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld new file mode 100644 index 0000000000000..4ab5390cf829c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : + { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld new file mode 100644 index 0000000000000..c19be9593b5db --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld new file mode 100644 index 0000000000000..a7fa7ca7f5626 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : + { + *(.userspace) + } > uflash + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : + { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt new file mode 100644 index 0000000000000..ae754f915ab1c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt @@ -0,0 +1,65 @@ +# ############################################################################## +# boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS stm32_mrf24j40.c) +endif() + +if(CONFIG_IEEE802154_XBEE) + list(APPEND SRCS stm32_xbee.c) +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_FS_AUTOMOUNTER) + list(APPEND SRCS stm32_automount.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/clicker2-stm32/src/Make.defs b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs new file mode 100644 index 0000000000000..8aa9073a43a93 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32f4/clicker2-stm32/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += stm32_mrf24j40.c +endif + +ifeq ($(CONFIG_IEEE802154_XBEE),y) +CSRCS += stm32_xbee.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_FS_AUTOMOUNTER),y) +CSRCS += stm32_automount.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h rename to boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h index 206efc3a8ba01..021d8c0ceac95 100644 --- a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h +++ b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h + * boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c new file mode 100644 index 0000000000000..2da98b9f340d4 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c new file mode 100644 index 0000000000000..c05d2d69f3a0e --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c @@ -0,0 +1,189 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the Clicker2 for STM32. The following definitions describe how + * NuttX controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt N/C ON + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + * + * VALUE + * -------------------------------------------- -------- -------- + * 0 OFF OFF + * 1 ON OFF + * 2 N/C ON + * 3 N/C N/C + * 4 OFF ON + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_led1_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED1=OFF */ + case 4: /* LED1=OFF */ + break; + + case 1: /* LED1=ON */ + ledon = true; + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED1, ledon); +} + +static void board_led2_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + break; + + case 2: /* LED2=ON */ + case 4: /* LED2=ON */ + ledon = true; + break; + + case 3: /* LED2=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED2, ledon); +} + +static void board_led1_off(int led) +{ + switch (led) + { + case 0: /* LED1=OFF */ + case 1: /* LED1=OFF */ + case 4: /* LED1=OFF */ + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED1, false); +} + +static void board_led2_off(int led) +{ + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + case 2: /* LED2=OFF */ + case 4: /* LED2=OFF */ + break; + + case 3: /* LED2=N/C */ + default: + return; + } + + stm32_gpiowrite(GPIO_LED2, false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + board_led1_on(led); + board_led2_on(led); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + board_led1_off(led); + board_led2_off(led); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_automount.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c index 6b2927ae6b590..7b3b777ceebb0 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_automount.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c new file mode 100644 index 0000000000000..89ef2589b8e43 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "clicker2-stm32.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usb_configure() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + stm32_usb_configure(); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + + ret = stm32_bringup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_bringup() failed: %d\n", ret); + return; + } + +#ifdef CONFIG_CLICKER2_STM32_SYSLOG_FILE + + /* Delay some time for the automounter to finish mounting before + * bringing up file syslog. + */ + + nxsched_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000); + + syslog_channel_t *channel; + channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH); + if (channel == NULL) + { + syslog(LOG_ERR, "ERROR: syslog_file_channel() failed\n"); + return; + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c new file mode 100644 index 0000000000000..385e36e540a8f --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c @@ -0,0 +1,193 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_RNDIS +# include +# include +#endif + +#include "stm32.h" +#include "clicker2-stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_RNDIS +# ifndef CONFIG_CLICKER2_STM32_RNDIS_MACADDR +# define CONFIG_CLICKER2_STM32_RNDIS_MACADDR 0xfadedeadbeef +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_BEE) || defined(CONFIG_CLICKER2_STM32_MB2_BEE) + /* Configure MRF24J40 wireless */ + + ret = stm32_mrf24j40_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed: %d\n", + ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_XBEE) || defined(CONFIG_CLICKER2_STM32_MB2_XBEE) + /* Configure XBee wireless */ + + ret = stm32_xbee_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_xbee_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT) || \ + defined(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT) + /* Configure uSD automounter */ + + ret = stm32_automount_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_automount_initialize() failed: %d\n", + ret); + } +#endif + +#if defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) || defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) + /* Configure uSD card slot */ + + ret = stm32_mmcsd_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mmcsd_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RNDIS + uint8_t mac[IFHWADDRLEN]; + + mac[0] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 5)) & 0xff; + mac[1] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 4)) & 0xff; + mac[2] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_CLICKER2_STM32_RNDIS_MACADDR >> (8 * 0)) & 0xff; + + /* Register USB RNDIS Driver */ + + ret = usbdev_rndis_initialize(mac); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: usbdev_rndis_initialize() failed %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c new file mode 100644 index 0000000000000..357926885bde3 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure BUTTONS T2-T3 GPIOs for input */ + + stm32_configgpio(GPIO_BTN_T2); + stm32_configgpio(GPIO_BTN_T3); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key. A low value will be sensed when the + * button is pressed. + */ + + if (!stm32_gpioread(GPIO_BTN_T2)) + { + ret |= BUTTON_T2_BIT; + } + + if (!stm32_gpioread(GPIO_BTN_T3)) + { + ret |= BUTTON_T3_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint32_t btncfg; + + btncfg = (id == BUTTON_T2) ? GPIO_BTN_T2 : GPIO_BTN_T3; + return stm32_gpiosetevent(btncfg, true, true, true, irqhandler, arg); +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c new file mode 100644 index 0000000000000..c5487024a4751 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..6d34e4bb2150a --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c @@ -0,0 +1,423 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_spi.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_MMCSD_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_CLICKER2_STM32_MB1_MMCSD) && \ + !defined(CONFIG_CLICKER2_STM32_MB2_MMCSD) +# error Only the Mikroe uSD click boards are supported +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# error Mountpoints are required for MMCSD support +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +# ifndef CONFIG_STM32_SPI3 +# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI3 +# endif +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +# ifndef CONFIG_STM32_SPI2 +# error MMCSD on mikroBUS1 requires CONFIG_STM32_SPI2 +# endif +#endif + +#ifdef CONFIG_SCHED_LPWORK +# define MMCSDWORK LPWORK +#elif defined (CONFIG_SCHED_HPWORK) +# define MMCSDWORK HPWORK +#else +# error High or low priority work queue required for MMCSD support +#endif + +/* Card Detect + * + * mikroBUS1 Card Detect (AN pin): PE10-MB1_INT + * mikroBUS2 Card Detect (AN pin: PE14-MB2_INT + * + * There is a pull-up on the uSD click board` + */ + +#define GPIO_MB1_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) +#define GPIO_MB2_CD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN3) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure holds static information unique to one MMCSD slot */ + +struct stm32_mmcsd_state_s +{ + uint8_t spidev; /* SPI bus used for MMCSD */ + uint8_t slotno; /* Slot number */ + int minor; /* The MMC/SD minor device number */ + uint32_t cdcfg; /* Card detect PIO pin configuration */ + xcpt_t handler; /* Interrupt handler */ + bool cd; /* TRUE: card is inserted */ + spi_mediachange_t callback; /* SPI media change callback */ + void *cbarg; /* Argument to pass to media change callback */ + struct work_s work; /* For deferring card detect interrupt work */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state); +static void stm32_mmcsd_carddetect(void *arg); +static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *); + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, + void *regs, + void *arg); +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, + void *regs, + void *arg); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* MMCSD device state */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg); + +static struct stm32_mmcsd_state_s g_mb1_mmcsd = +{ + .spidev = 3, + .slotno = MB1_MMCSD_SLOTNO, + .minor = MB1_MMCSD_MINOR, + .cdcfg = GPIO_MB1_CD, + .handler = stm32_mb1_mmcsd_carddetect, + .callback = NULL, + .cbarg = NULL, +}; +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg); + +static struct stm32_mmcsd_state_s g_mb2_mmcsd = +{ + .spidev = 2, + .slotno = MB2_MMCSD_SLOTNO, + .minor = MB2_MMCSD_MINOR, + .cdcfg = GPIO_MB2_CD, + .handler = stm32_mb2_mmcsd_carddetect, + .callback = NULL, + .cbarg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cardinserted_internal + * + * Description: + * Check if a card is inserted into the selected MMCSD slot + * + ****************************************************************************/ + +static bool stm32_cardinserted_internal(struct stm32_mmcsd_state_s *state) +{ + bool inserted; + + /* Get the state of the PIO pin */ + + inserted = stm32_gpioread(state->cdcfg); + finfo("Slot %d inserted: %s\n", state->slotno, inserted ? "NO" : "YES"); + return !inserted; +} + +/**************************************************************************** + * Name: stm32_mmcsd_carddetect, stm32_mb1_mmcsd_carddetect, and + * stm32_mb2_mmcsd_carddetect + * + * Description: + * Card detect interrupt handlers + * + ****************************************************************************/ + +static void stm32_mmcsd_carddetect(void *arg) +{ + bool cd; + struct stm32_mmcsd_state_s *state = + (struct stm32_mmcsd_state_s *)arg; + + /* Get the current card insertion state */ + + cd = stm32_cardinserted_internal(state); + + /* Has the card detect state changed? */ + + if (cd != state->cd) + { + /* Yes... remember that new state and inform the HSMCI driver */ + + state->cd = cd; + + /* Report the new state to the SPI driver */ + + if (state->callback) + { + state->callback(state->cbarg); + } + } + +#ifdef HAVE_AUTOMOUNTER + /* Let the automounter know about the insertion event */ + + stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); +#endif +} + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD +static int stm32_mb1_mmcsd_carddetect(int irq, void *regs, void *arg) +{ + if (work_available(&g_mb1_mmcsd.work)) + { + return work_queue(MMCSDWORK, &g_mb1_mmcsd.work, stm32_mmcsd_carddetect, + &g_mb1_mmcsd, 0); + } + + return OK; +} +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD +static int stm32_mb2_mmcsd_carddetect(int irq, void *regs, void *arg) +{ + if (work_available(&g_mb2_mmcsd.work)) + { + return work_queue(MMCSDWORK, &g_mb2_mmcsd.work, stm32_mmcsd_carddetect, + &g_mb2_mmcsd, 0); + } + + return OK; +} +#endif + +static int stm32_mmcsd_setup(struct stm32_mmcsd_state_s *state) +{ + struct spi_dev_s *spi; + int ret; + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(state->spidev); + if (spi == NULL) + { + spierr("ERROR: Failed to initialize SPI bus %d\n", state->spidev); + return -ENODEV; + } + + ret = mmcsd_spislotinitialize(state->minor, state->slotno, spi); + if (ret < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + state->spidev, state->slotno); + return ret; + } + + /* Initialize Card Detect pin and enable interrupt on edges */ + + stm32_configgpio(state->cdcfg); + stm32_gpiosetevent(state->cdcfg, true, true, true, state->handler, NULL); + + state->cd = stm32_cardinserted_internal(state); + if (state->callback) + { + state->callback(state->cbarg); + } + +#ifdef HAVE_AUTOMOUNTER + /* Let the automounter know about the insertion event */ + + stm32_automount_event(state->slotno, stm32_cardinserted(state->slotno)); +#endif + + mcinfo("INFO: mmcsd%d card has been initialized successfully\n", + state->minor); + return OK; +} + +/**************************************************************************** + * Public Function + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize the MMCSD device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mmcsd_initialize(void) +{ + int ret; + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + finfo("Configuring MMCSD on mikroBUS1\n"); + + ret = stm32_mmcsd_setup(&g_mb1_mmcsd); + if (ret < 0) + { + mcerr("ERROR: Failed to initialize MMCSD on mikroBus1: %d\n", ret); + } +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + finfo("Configuring MMCSD on mikroBUS2\n"); + ret = stm32_mmcsd_setup(&g_mb2_mmcsd); + if (ret < 0) + { + mcerr("ERROR: Failed to initialize MMCSD on mikroBus2: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: stm32_cardinserted + * + * Description: + * Check if a card is inserted into the selected MMCSD slot + * + ****************************************************************************/ + +bool stm32_cardinserted(int slotno) +{ + struct stm32_mmcsd_state_s *state; + + /* Get the MMCSD description */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + if (slotno == g_mb1_mmcsd.slotno) + { + state = &g_mb1_mmcsd; + } +#endif +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + + if (slotno == g_mb2_mmcsd.slotno) + { + state = &g_mb2_mmcsd; + } +#endif + + if (!state) + { + ferr("ERROR: No state for slotno %d\n", slotno); + return false; + } + + /* Return the state of the CD pin */ + + return stm32_cardinserted_internal(state); +} + +/**************************************************************************** + * Name: stm32_spi2register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi2 device\n"); +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + g_mb2_mmcsd.callback = callback; + g_mb2_mmcsd.cbarg = arg; +#endif + return OK; +} + +/**************************************************************************** + * Name: stm32_spi3register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + spiinfo("INFO: Registering spi3 device\n"); +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + g_mb1_mmcsd.callback = callback; + g_mb1_mmcsd.cbarg = arg; +#endif + return OK; +} + +#endif /* CONFIG_MMCSD_SPI */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c new file mode 100644 index 0000000000000..ecd813fb9a5fc --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c @@ -0,0 +1,328 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "clicker2-stm32.h" + +#ifdef CONFIG_IEEE802154_MRF24J40 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DRIVERS_WIRELESS +# error Wireless support requires CONFIG_DRIVERS_WIRELESS +#endif + +#if !defined(CONFIG_CLICKER2_STM32_MB1_BEE) && \ + !defined(CONFIG_CLICKER2_STM32_MB2_BEE) +# error Only the Mikroe BEE board is supported +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE +# ifndef CONFIG_STM32_SPI3 +# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI3 +# endif +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE +# ifndef CONFIG_STM32_SPI2 +# error Mikroe BEE on mikroBUS1 requires CONFIG_STM32_SPI2 +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_priv_s +{ + struct mrf24j40_lower_s dev; + xcpt_t handler; + void *arg; + uint32_t intcfg; + uint8_t spidev; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MRF24J40 driver from differences in GPIO interrupt handling + * varying boards and MCUs. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg); +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state); +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MRF24J40 + * driver. This structure provides information about the configuration + * of the MRF24J40 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE +static struct stm32_priv_s g_mrf24j40_mb1_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MB1_INT, + .spidev = 3, +}; +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE +static struct stm32_priv_s g_mrf24j40_mb2_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MB2_INT, + .spidev = 2, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the MRF24J40 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + DEBUGASSERT(priv != NULL); + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); + +#ifdef CONFIG_CLICKER2_STM32_MRF24J40LH_VERBOSE + wlinfo("state:%d\n", (int)state); +#endif + + /* Attach and enable, or detach and disable */ + + if (state) + { + stm32_gpiosetevent(priv->intcfg, false, true, true, + priv->handler, priv->arg); + } + else + { + stm32_gpiosetevent(priv->intcfg, false, false, false, + NULL, NULL); + } +} + +/**************************************************************************** + * Name: stm32_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + struct spi_dev_s *spi; + int ret; + + /* Configure the interrupt pin */ + + stm32_configgpio(priv->intcfg); + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(priv->spidev); + if (spi == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Initialize and register the SPI MRF24J40 device */ + + radio = mrf24j40_init(spi, &priv->dev); + if (radio == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC interface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("ERROR:"); + wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mrf24j40_initialize(void) +{ + int ret; + +#ifdef CONFIG_CLICKER2_STM32_MB1_BEE + wlinfo("Configuring BEE in mikroBUS1\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); + } +#endif + +#ifdef CONFIG_CLICKER2_STM32_MB2_BEE + wlinfo("Configuring BEE in mikroBUS2\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb2_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS2: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} +#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c new file mode 100644 index 0000000000000..3e631a3b6a33c --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "clicker2-stm32.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 + * STM32 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_STM32_SPI3) && defined(CONFIG_CLICKER2_STM32_MB1_SPI) + /* Enable chip select for mikroBUS1 */ + + stm32_configgpio(GPIO_MB1_CS); +#endif +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_CLICKER2_STM32_MB2_SPI) + /* Enable chip select for mikroBUS2 */ + + stm32_configgpio(GPIO_MB2_CS); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif +#ifdef CONFIG_IEEE802154_XBEE + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif +#ifdef CONFIG_MMCSD_SPI + case SPIDEV_MMCSD(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB2_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_CLICKER2_STM32_MB2_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + status = stm32_cardinserted(MB2_MMCSD_SLOTNO); + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif +#ifdef CONFIG_IEEE802154_XBEE + case SPIDEV_IEEE802154(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif +#ifdef CONFIG_MMCSD_SPI + case SPIDEV_MMCSD(0): + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_MB1_CS, !selected); + break; +#endif + default: + break; + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_CLICKER2_STM32_MB1_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + status |= stm32_cardinserted(MB1_MMCSD_SLOTNO); + } +#endif + + return status; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* To be provided */ + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c new file mode 100644 index 0000000000000..6c32c09880b88 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_otgfs.h" +#include "stm32_gpio.h" +#include "clicker2-stm32.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO */ + + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c new file mode 100644 index 0000000000000..4d9f9190137d9 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "clicker2-stm32.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + gpioconfig_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, true); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c index c5bd9cafb82cb..8aef55384ca8d 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/common/CMakeLists.txt b/boards/arm/stm32f4/common/CMakeLists.txt new file mode 100644 index 0000000000000..c0b10dbf603f3 --- /dev/null +++ b/boards/arm/stm32f4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f4/common/Kconfig b/boards/arm/stm32f4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32f4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f4/common/Makefile b/boards/arm/stm32f4/common/Makefile new file mode 100644 index 0000000000000..cb4984cccea4d --- /dev/null +++ b/boards/arm/stm32f4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32f4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt new file mode 100644 index 0000000000000..ea2ce2c8f04c7 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/mikroe-stm32f4/Kconfig b/boards/arm/stm32f4/mikroe-stm32f4/Kconfig similarity index 100% rename from boards/arm/stm32/mikroe-stm32f4/Kconfig rename to boards/arm/stm32f4/mikroe-stm32f4/Kconfig diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig new file mode 100644 index 0000000000000..b72204cedca5f --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig @@ -0,0 +1,137 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXPLAYER_INCLUDE_PREFERRED_DEVICE is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_FORMAT_MIDI=y +CONFIG_AUDIO_VS1053=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_FATDEVNO=0 +CONFIG_ETC_ROMFS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FS_BINFS=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SPICLOCK=30000000 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_MTD_CONFIG=y +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NX=y +CONFIG_NXFONT_SANS17X23B=y +CONFIG_NXFONT_SANS20X27B=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS28X37B=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/usr/sounds" +CONFIG_NXPLAYER_INCLUDE_SYSTEM_RESET=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_BACKGROUND_IMAGE="" +CONFIG_NXWM_HEXCALCULATOR_BACKGROUNDCOLOR=0x39C7 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_COLORS=y +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_KEYBOARD_DEVPATH="/dev/ttyS0" +CONFIG_NXWM_KEYBOARD_LISTENERPRIO=100 +CONFIG_NXWM_MEDIAPLAYER=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TOUCHSCREEN_CONFIGDATA=y +CONFIG_NXWM_TOUCHSCREEN_LISTENERPRIO=100 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PLATFORM_CONFIGDATA=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_TASK_NAME_SIZE=11 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig new file mode 100644 index 0000000000000..1c3eb8c59df96 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="ostest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/mikroe-stm32f4/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=11 +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig new file mode 100644 index 0000000000000..b1dfc76caa8f1 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig new file mode 100644 index 0000000000000..000e9a61f2990 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nx_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig new file mode 100644 index 0000000000000..c67e2e80f97fc --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_WRITEONLY is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0x87F0 +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0x861F +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig new file mode 100644 index 0000000000000..30d89a2cdffdb --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NXTEXT=y +CONFIG_EXAMPLES_NXTEXT_BPP=16 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxtext_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MIO283QT2=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SERIF22X28B=y +CONFIG_NXTK_BORDERCOLOR1=0x8410 +CONFIG_NXTK_BORDERCOLOR2=0x4208 +CONFIG_NXTK_BORDERCOLOR3=0xc618 +CONFIG_NXTK_BORDERWIDTH=3 +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..598b990801356 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mikroe-stm32f4" +CONFIG_ARCH_BOARD_MIKROE_STM32F4=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_MANUFACTURER=0x1C +CONFIG_M25P_MEMORY_TYPE=0x31 +CONFIG_M25P_SUBSECTOR_ERASE=y +CONFIG_MIKROE_FLASH=y +CONFIG_MIKROE_FLASH_PART=y +CONFIG_MIKROE_FLASH_PART_LIST="256,768" +CONFIG_MIKROE_RAMMTD=y +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/mikroe-stm32f4/include/board.h b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h new file mode 100644 index 0000000000000..8c6d5b2833ef7 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h @@ -0,0 +1,251 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Mikroe STM32F4 Mikromedia board features a single 32kHz crystal. + * The main clock uses the internal 16Mhz RC oscillator. + * + * This is the canonical configuration: + * System Clock source :PLL (HSE) + * SYSCLK(Hz) :168000000 Determined by PLL configuration + * HCLK(Hz) :168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler :1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler :4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler :2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) :16000000 (STM32_HSI_FREQUENCY) + * PLLM :16 (STM32_PLLCFG_PLLM) + * PLLN :36 (STM32_PLLCFG_PLLN) + * PLLP :2 (STM32_PLLCFG_PLLP) + * PLLQ :7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage :Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) :5 + * Prefetch Buffer :OFF + * Instruction cache :ON + * Data cache :ON + * Require 48MHz for USB OTG FS, :Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#if 0 +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#endif +#define BOARD_NLEDS 0 + +#if 0 +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, + * then NuttX will control the 4 LEDs on board the stm32f4discovery. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 0 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* 0 */ + +/* Alternate function pin selections ****************************************/ + +/* UART2: + * + * The Mikroe-STM32F4 board has no on-board serial devices, but it brings out + * UART2 to the expansion header. + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +/* SPI - Onboard devices use SPI3, plus SPI2 routes to the I/O header */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_2 + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_MIKROE_STM32F4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile new file mode 100644 index 0000000000000..085f09c0d79a0 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..75c04f0ea07e9 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs new file mode 100644 index 0000000000000..c97f06d478ed3 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld new file mode 100644 index 0000000000000..153de5546bda5 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script new file mode 100644 index 0000000000000..b0a85f1be26e6 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld new file mode 100644 index 0000000000000..9d0a6f39cf69d --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/stm32f4discovery/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld new file mode 100644 index 0000000000000..56cf83bb0fac8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt new file mode 100644 index 0000000000000..1f0c3d19eed73 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt @@ -0,0 +1,67 @@ +# ############################################################################## +# boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c) + +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + list(APPEND SRCS stm32_clockconfig.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_INPUT) + list(APPEND SRCS stm32_touchscreen.c) +endif() + +if(CONFIG_LCD_MIO283QT2) + list(APPEND SRCS stm32_mio283qt2.c) +endif() + +if(CONFIG_LCD_MIO283QT9A) + list(APPEND SRCS stm32_mio283qt9a.c) +endif() + +if(CONFIG_AUDIO_VS1053) + list(APPEND SRCS stm32_vs1053.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs new file mode 100644 index 0000000000000..aea83e0fe0551 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs @@ -0,0 +1,73 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) +CSRCS += stm32_clockconfig.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_INPUT),y) +CSRCS += stm32_touchscreen.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT2),y) +CSRCS += stm32_mio283qt2.c +endif + +ifeq ($(CONFIG_LCD_MIO283QT9A),y) +CSRCS += stm32_mio283qt9a.c +endif + +ifeq ($(CONFIG_AUDIO_VS1053),y) +CSRCS += stm32_vs1053.c +endif + +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c index 158b6f532564a..8e4bde5a9f646 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c + * boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h rename to boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h index beeb62fda1f6b..ab13436ea2165 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h + * boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c new file mode 100644 index 0000000000000..548e44dd179ef --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c @@ -0,0 +1,467 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI3 +# include +#endif + +#ifdef CONFIG_MTD_M25P +# include +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART +#ifdef CONFIG_PLATFORM_CONFIGDATA +# include +#endif +#endif + +#ifdef CONFIG_AUDIO +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "arm_internal.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +#define NSH_HAVEMMCSD 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SPI3) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +# ifndef CONFIG_RAMMTD_BLOCKSIZE +# define CONFIG_RAMMTD_BLOCKSIZE 512 +# endif + +# ifndef CONFIG_RAMMTD_ERASESIZE +# define CONFIG_RAMMTD_ERASESIZE 4096 +# endif + +# ifndef CONFIG_TESTING_SMART_NEBLOCKS +# define CONFIG_TESTING_SMART_NEBLOCKS (22) +# endif + +#ifdef CONFIG_MIKROE_RAMMTD +# ifndef CONFIG_MIKROE_RAMMTD_MINOR +# define CONFIG_MIKROE_RAMMTD_MINOR 1 +# endif +# ifndef CONFIG_MIKROE_RAMMTD_SIZE +# define CONFIG_MIKROE_RAMMTD_SIZE 32 +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* First reset the VS1053 since it tends to produce noise out of power on + * reset + */ + +#ifdef CONFIG_AUDIO_VS1053 + stm32_configgpio(GPIO_VS1053_RST); +#endif + + /* Configure GPIOs for controlling the LCD */ + +#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) + stm32_lcdinitialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#ifdef CONFIG_STM32_SPI3 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif + int ret = OK; + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI3 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 3\n"); + spi = stm32_spibus_initialize(3); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 3\n"); + return; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 3\n"); + + /* Now bind the SPI interface to the M25P8 SPI FLASH driver */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MIKROE_FLASH) + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port 3 to the SPI" + " FLASH driver\n"); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI port 3 to the SPI" + " FLASH driver\n"); + +#ifdef CONFIG_MIKROE_FLASH_PART + { + int partno; + int partsize; + int partoffset; + const char *partstring = CONFIG_MIKROE_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partname[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + mtd_part = mtd_partition(mtd, partoffset, + (partsize >> 2) * 16); + partoffset += (partsize >> 2) * 16; + +#ifdef CONFIG_MIKROE_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_MIKROE_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + + #if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partname, sizeof(partname), "p%d", partno); + smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd_part, + partname); +#endif + } + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_MIKROE_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_MIKROE_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_MIKROE_FLASH_PART */ + } + + /* Create a RAM MTD device if configured */ + +#if defined(CONFIG_RAMMTD) && defined(CONFIG_MIKROE_RAMMTD) + { + uint8_t *start = + kmm_malloc(CONFIG_MIKROE_RAMMTD_SIZE * 1024); + mtd = rammtd_initialize(start, CONFIG_MIKROE_RAMMTD_SIZE * 1024); + mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + + /* Now initialize a SMART Flash block device and bind it to the + * MTD device + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + smart_initialize(CONFIG_MIKROE_RAMMTD_MINOR, mtd, NULL); +#endif + } + +#endif /* CONFIG_RAMMTD && CONFIG_MIKROE_RAMMTD */ + +#endif /* CONFIG_MTD */ +#endif /* CONFIG_STM32_SPI3 */ + + /* Create the SPI FLASH MTD instance */ + + /* The M25Pxx is not a good media to implement a file system.. + * its block sizes are too large + */ + + /* Mount the SDIO-based MMC/SD block driver */ + +#ifdef NSH_HAVEMMCSD + /* Bind the spi interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDIO to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR, + CONFIG_NSH_MMCSDSLOTNO, spi); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI to the MMC/SD driver:" + " %d\n", ret); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI to the MMC/SD driver\n"); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_LCD_MIO283QT2) || defined(CONFIG_LCD_MIO283QT9A) + /* Configure the TFT LCD module */ + + syslog(LOG_INFO, "Initializing TFT LCD module\n"); + + ret = board_lcd_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize TFT LCD module\n"); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_MIKROE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return; + } +#endif + +#ifdef CONFIG_AUDIO + /* Configure the Audio sub-system if enabled and bind it to SPI 3 */ + + up_vs1053initialize(spi); +#endif +} +#endif diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c index 75b6870101ab3..2bf857538d281 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c new file mode 100644 index 0000000000000..3f04746a7eca8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1 , GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4 , GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1 , GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4 , GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c new file mode 100644 index 0000000000000..f9cef25fff2b8 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ +#ifdef CONFIG_RTC_ALARM + struct timespec alarmtime; +#endif + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + up_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c index c56b43eed1a16..259eaf710b705 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c index b40aff992d589..aab48c5e5e561 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c new file mode 100644 index 0000000000000..1905d67954d5e --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + up_pmbuttons(); +#endif + + /* Initialize the LED PM */ + + up_ledpminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c new file mode 100644 index 0000000000000..0e96a7fd9a247 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "mikroe-stm32f4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The mikroe_stm32f4 has no real on-board PWM devices, but the board can be + * configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); + if (!pwm) + { + _err("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c new file mode 100644 index 0000000000000..35f55d130af89 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "mikroe-stm32f4.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI3 + +#ifdef CONFIG_MTD_M25P + stm32_configgpio(GPIO_CS_FLASH); /* FLASH chip select */ +#endif + +#if defined(CONFIG_MMCSD) + stm32_configgpio(GPIO_CS_MMCSD); /* MMC/SD chip select */ + stm32_configgpio(GPIO_SD_CD); /* MMC/SD card detect */ +#endif + +#ifdef CONFIG_AUDIO_VS1053 + stm32_configgpio(GPIO_CS_MP3_DATA); /* MP3 codec chip select for DATA */ + stm32_configgpio(GPIO_CS_MP3_CMD); /* MP3 codec chip select for CMD */ +#endif + + /* Configure the EXP I/O cs for SPI3 */ + + stm32_configgpio(GPIO_CS_EXP_SPI3); /* Expander chip select */ + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_AUDIO_VS1053) + if (devid == SPIDEV_AUDIO_DATA(0)) + { + stm32_gpiowrite(GPIO_CS_MP3_DATA, !selected); + } + else if (devid == SPIDEV_AUDIO_CTRL(0)) + { + stm32_gpiowrite(GPIO_CS_MP3_CMD, !selected); + } + else +#endif + +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_CS_MMCSD, !selected); + } + else +#endif + +#if defined(CONFIG_MTD_M25P) + if (devid == SPIDEV_FLASH(0)) + { + stm32_gpiowrite(GPIO_CS_FLASH, !selected); + } + else +#endif + + /* Must be the expansion header device */ + + if (devid == SPIDEV_EXPANDER(0)) + { + stm32_gpiowrite(GPIO_CS_EXP_SPI3, !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t ret = 0; + +#if defined(CONFIG_MMCSD) + if (devid == SPIDEV_MMCSD(0)) + { + /* A low value indicates the card is present */ + + if (!stm32_gpioread(GPIO_SD_CD)) + { + ret = SPI_STATUS_PRESENT; + } + } +#endif + + return ret; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c new file mode 100644 index 0000000000000..c1ca271395472 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c @@ -0,0 +1,1547 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "arm_internal.h" +#include "stm32_adc.h" +#include "stm32_gpio.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_INPUT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Reference counting is partially implemented, but not needed in the current + * design. + */ + +#define CONFIG_TOUCHSCREEN_REFCNT +/* Should we try again on bad samples? */ + +#undef CONFIG_TOUCHSCREEN_RESAMPLE + +/* TP uses ADC Channel #2 in a dedicated mode. Ensure ADC2 not selected for + * general use via the menuconfig + */ + +#ifndef CONFIG_STM32_ADC2 +# error Touchpanel Input (CONFIG_INPUT=y) requires enablinga ADC2 (CONFIG_STM32_ADC2=y) +#endif + +/* Work queue support is required */ + +#ifndef CONFIG_SCHED_WORKQUEUE +# warning Work queue support is required (CONFIG_SCHED_WORKQUEUE=y) +#endif + +/* CONFIG_TOUCHSCREEN_THRESHX and CONFIG_TOUCHSCREEN_THRESHY + * Touchscreen data comes in a a very high rate. New touch positions + * will only be reported when the X or Y data changes by these thresholds. + * This trades reduces data rate for some loss in dragging accuracy. The + * touchscreen is configure for 12-bit values so the raw ranges are 0-4096. + * So for example, if your display is 320x240, then THRESHX=3 and THRESHY=4 + * would correspond to one pixel. Default: 4 + */ + +#ifndef CONFIG_TOUCHSCREEN_THRESHX +# define CONFIG_TOUCHSCREEN_THRESHX 12 +#endif + +#ifndef CONFIG_TOUCHSCREEN_THRESHY +# define CONFIG_TOUCHSCREEN_THRESHY 12 +#endif + +#ifndef CONFIG_TOUCHSCREEN_AVG_SAMPLES +# define CONFIG_TOUCHSCREEN_AVG_SAMPLES 2 +#endif + +#ifndef CONFIG_TOUCHSCREEN_NPOLLWAITERS +# define CONFIG_TOUCHSCREEN_NPOLLWAITERS 2 +#endif + +/* Driver support ***********************************************************/ + +/* This format is used to construct the /dev/input[n] device driver path. It + * is defined here so that it will be used consistently in all places. + */ + +#define DEV_FORMAT "/dev/input%d" +#define DEV_NAMELEN 16 + +/* Mikroe-STM32M4 Touchscreen Hardware Definitions ************************** + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * --- ---------------------------------- -------------------- -------------- + * 35 PB0 LCD-YD YD Analog input + * 36 PB1 LCD-XL XL Analog input + * 95 PB8 DRIVEA Drives XR, XL and YU + * 96 PB9 DRIVEB Drives YD + */ + +#define LCD_YD_PIN (0) +#define LCD_XL_PIN (1) +#define LCD_YD_CHANNEL (8) +#define LCD_XL_CHANNEL (9) +#define LCD_DRIVEA_PIN (8) +#define LCD_DRIVEB_PIN (9) + +#define LCD_DRIVEA_BIT (1 << LCD_DRIVEA_PIN) +#define LCD_DRIVEB_BIT (1 << LCD_DRIVEB_PIN) +#define LCD_SAMPX_BITS (LCD_DRIVEA_BIT | (LCD_DRIVEB_BIT << 16)) +#define LCD_SAMPY_BITS (LCD_DRIVEB_BIT | (LCD_DRIVEA_BIT << 16)) +#define LCD_TP_PORT_SETRESET STM32_GPIOB_BSRR + +#define TC_ADC_BASE STM32_ADC2_BASE /* ADC Channel base for TP */ +#define ADC_CR1_ALLINTS (ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_JEOCIE) + +/* Conversions are performed as 10-bit samples represented as 16-bit */ + +#define MAX_ADC (4096) + +/* A measured value has to be within this range to be considered */ + +#define UPPER_THRESHOLD (MAX_ADC-1) +#define LOWER_THRESHOLD (362) + +/* Delays *******************************************************************/ + +/* All values will be increased by one system timer tick (probably 10MS). */ + +#define TC_PENUP_POLL_TICKS MSEC2TICK(70) /* IDLE polling rate: 70 MSec */ +#define TC_PENDOWN_POLL_TICKS MSEC2TICK(40) /* Active polling rate: 40 MSec */ +#define TC_DEBOUNCE_TICKS MSEC2TICK(16) /* Delay before re-sampling: 16 MSec */ +#define TC_SAMPLE_TICKS MSEC2TICK(4) /* Delay for A/D sampling: 4 MSec */ +#define TC_SETTLE_TICKS MSEC2TICK(10) /* Delay for A/D settling: 10 MSec */ +#define TC_RESAMPLE_TICKS TC_SAMPLE_TICKS + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This enumeration describes the state of touchscreen state machine */ + +enum tc_state_e +{ + TC_READY = 0, /* Ready to begin next sample */ + TC_READY_SETTLE, /* Allowing time for Y DRIVE to settle */ + TC_YPENDOWN, /* Allowing time for the Y pen down sampling */ + TC_DEBOUNCE, /* Allowing a debounce time for the first sample */ + TC_RESAMPLE, /* Restart sampling on a bad measurement */ + TC_YSAMPLE, /* Allowing time for the Y sampling */ + TC_XSETTLE, /* Allowing time for the X to settle after changing DRIVE */ + TC_XSAMPLE, /* Allowing time for the X sampling */ + TC_XRESAMPLE, /* Allow time to resample X */ + TC_PENDOWN, /* Conversion is complete -- pen down */ + TC_PENUP /* Conversion is complete -- pen up */ +}; + +/* This describes the state of one contact */ + +enum tc_contact_e +{ + CONTACT_NONE = 0, /* No contact */ + CONTACT_DOWN, /* First contact */ + CONTACT_MOVE, /* Same contact, possibly different position */ + CONTACT_UP, /* Contact lost */ +}; + +/* This structure describes the results of one touchscreen sample */ + +struct tc_sample_s +{ + uint8_t id; /* Sampled touch point ID */ + uint8_t contact; /* Contact state (see enum tc_contact_e) */ + bool valid; /* True: x,y contain valid, sampled data */ + uint16_t x; /* Thresholded X position */ + uint16_t y; /* Thresholded Y position */ +}; + +/* This structure describes the state of one touchscreen driver instance */ + +struct tc_dev_s +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + uint8_t crefs; /* Number of times the device has been opened */ +#endif + uint8_t state; /* See enum tc_state_e */ + uint8_t nwaiters; /* Number of threads waiting for touchscreen data */ + uint8_t id; /* Current touch point ID */ + volatile bool penchange; /* An unreported event is buffered */ + uint16_t value; /* Partial sample value (Y+ or X-) */ + uint16_t newy; /* New, un-thresholded Y value */ + uint8_t sampcount; /* Count of samples for average so far */ + uint8_t resamplecount; /* Countdown to PENUP */ + mutex_t devlock; /* Manages exclusive access to this structure */ + sem_t waitsem; /* Used to wait for the availability of data */ + struct tc_sample_s sample; /* Last sampled touch point data */ + struct work_s work; /* Supports the state machine delayed processing */ + + /* The following is a list if poll structures of threads waiting for + * driver events. The 'struct pollfd' reference for each open is also + * retained in the f_priv field of the 'struct file'. + */ + + struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void tc_adc_init(void); +static void tc_adc_start_sample(int pin); +static uint16_t tc_adc_read_sample(void); +static void tc_y_sample(void); +static void tc_x_sample(void); +static inline bool tc_valid_sample(uint16_t sample); + +static void tc_notify(struct tc_dev_s *priv); +static int tc_sample(struct tc_dev_s *priv, + struct tc_sample_s *sample); +static int tc_waitsample(struct tc_dev_s *priv, + struct tc_sample_s *sample); +static void tc_worker(void *arg); + +/* Character driver methods */ + +static int tc_open(struct file *filep); +static int tc_close(struct file *filep); +static ssize_t tc_read(struct file *filep, char *buffer, size_t len); +static int tc_ioctl(struct file *filep, int cmd, unsigned long arg); +static int tc_poll(struct file *filep, struct pollfd *fds, bool setup); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This the vtable that supports the character driver interface */ + +static const struct file_operations g_tc_fops = +{ + tc_open, /* open */ + tc_close, /* close */ + tc_read, /* read */ + NULL, /* write */ + NULL, /* seek */ + tc_ioctl, /* ioctl */ + NULL, /* mmap */ + NULL, /* truncate */ + tc_poll /* poll */ +}; + +/* If only a single touchscreen device is supported, then the driver state + * structure may as well be pre-allocated. + */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE +static struct tc_dev_s g_touchscreen; +static bool g_touchinitdone = false; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc_adc_getreg + * + * Description: + * Read the value of an TC ADC channel (#2) register. + * + * Input Parameters: + * offset - The offset to the register to read + * value + * + * Returned Value: + * + ****************************************************************************/ + +static inline uint32_t tc_adc_getreg(int offset) +{ + return getreg32(TC_ADC_BASE + offset); +} + +/**************************************************************************** + * Name: tc_adc_putreg + * + * Description: + * Set the value of an ADC register. + * + * Input Parameters: + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +static inline void tc_adc_putreg(int offset, uint32_t value) +{ + putreg32(value, TC_ADC_BASE + offset); +} + +/**************************************************************************** + * Name: tc_adc_init + * + * Description: + * Initialize ADC Channel #2 for use with the touch panel. The touch panel + * uses Channels 8 and 9 (PB0 and PB1) to read the X and Y axis touch + * positions. + * + ****************************************************************************/ + +static void tc_adc_init(void) +{ + irqstate_t flags; + uint32_t regval; + + /* Do an rcc reset to reset the ADC peripheral */ + + /* Disable interrupts. This is necessary because the APB2RTSR register + * is used by several different drivers. + */ + + flags = enter_critical_section(); + + /* Enable ADC reset state */ + + regval = getreg32(STM32_RCC_APB2RSTR); + regval |= RCC_APB2RSTR_ADCRST; + putreg32(regval, STM32_RCC_APB2RSTR); + + /* Release ADC from reset state */ + + regval &= ~RCC_APB2RSTR_ADCRST; + putreg32(regval, STM32_RCC_APB2RSTR); + + /* Initialize the watchdog high threshold register */ + + tc_adc_putreg(STM32_ADC_HTR_OFFSET, 0x00000fff); + + /* Initialize the watchdog low threshold register */ + + tc_adc_putreg(STM32_ADC_LTR_OFFSET, 0x00000000); + + /* Initialize the same sample time for each ADC 55.5 cycles + * + * During sample cycles channel selection bits must remain unchanged. + * + * 000: 1.5 cycles + * 001: 7.5 cycles + * 010: 13.5 cycles + * 011: 28.5 cycles + * 100: 41.5 cycles + * 101: 55.5 cycles + * 110: 71.5 cycles + * 111: 239.5 cycles + */ + + tc_adc_putreg(STM32_ADC_SMPR1_OFFSET, 0x00b6db6d); + tc_adc_putreg(STM32_ADC_SMPR2_OFFSET, 0x00b6db6d); + + /* ADC CR1 Configuration */ + + regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET); + + /* Initialize the Analog watchdog enable */ + + regval &= ~ADC_CR1_AWDEN; + regval |= (LCD_YD_CHANNEL << ADC_CR1_AWDCH_SHIFT); + + /* Enable interrupt flags */ + + /* regval |= ADC_CR1_ALLINTS; */ + + /* Disable Overrun interrupt */ + + regval &= ~ADC_CR1_OVRIE; + + /* Set the resolution of the conversion. We only need 10 bits. */ + + regval |= ADC_CR1_RES_12BIT; + + tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); + + /* ADC CR2 Configuration */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + + /* Clear CONT, continuous mode disable. We will perform single + * sampling on one channel at a time. + */ + + regval &= ~ADC_CR2_CONT; + + /* Set ALIGN (Right = 0) */ + + regval &= ~ADC_CR2_ALIGN; + + /* External trigger disable. We will do SW triggering */ + + regval &= ~ADC_CR2_EXTEN_MASK; + + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); + + /* Configuration of the channel conversion - start with Y sampling */ + + regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; + regval |= LCD_YD_CHANNEL; + tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); + + /* Set the number of conversions = 1 */ + + regval = tc_adc_getreg(STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED; + regval |= 0 << ADC_SQR1_L_SHIFT; + tc_adc_putreg(STM32_ADC_SQR1_OFFSET, regval); + + /* ADC CCR configuration */ + + regval = getreg32(STM32_ADC_CCR); + regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | + ADC_CCR_DMA_MASK | ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATEN | + ADC_CCR_TSVREFE); + regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | + ADC_CCR_ADCPRE_DIV2); + putreg32(regval, STM32_ADC_CCR); + + /* Set ADON to wake up the ADC from Power Down state. */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + regval |= ADC_CR2_ADON; + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); + + /* Restore the IRQ state */ + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: tc_adc_start_sample + * + * Description: + * Perform A/D sampling. Time must be allowed between the start of + * sampling and conversion (approx. 100Ms). + * + ****************************************************************************/ + +static void tc_adc_start_sample(int channel) +{ + uint32_t regval; + + /* Configure the specified channel for ADC conversion. */ + + regval = tc_adc_getreg(STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED; + regval |= channel; + tc_adc_putreg(STM32_ADC_SQR3_OFFSET, regval); + + /* Configure the Watchdog for this channel */ + + regval = tc_adc_getreg(STM32_ADC_CR1_OFFSET) & ADC_CR1_AWDCH_MASK; + regval |= (channel << ADC_CR1_AWDCH_SHIFT); + tc_adc_putreg(STM32_ADC_CR1_OFFSET, regval); + + /* Start the conversion */ + + regval = tc_adc_getreg(STM32_ADC_CR2_OFFSET); + regval |= ADC_CR2_SWSTART; + tc_adc_putreg(STM32_ADC_CR2_OFFSET, regval); +} + +/**************************************************************************** + * Name: tc_adc_read_sample + * + * Description: + * Begin A/D conversion. Time must be allowed between the start of + * sampling and conversion (approx. 100Ms). + * + * Assumptions: + * 1) All output pins configured as outputs: + * 2) Appropriate pins are driven high and low + * + ****************************************************************************/ + +static uint16_t tc_adc_read_sample(void) +{ + uint16_t retval; + uint32_t adcsr; + uint16_t count = 0; + + /* Validate the conversion is complete */ + + adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); + while ((adcsr & ADC_SR_EOC) == 0) + { + adcsr = tc_adc_getreg(STM32_ADC_SR_OFFSET); + count++; + } + + /* Read the sample */ + + retval = tc_adc_getreg(STM32_ADC_DR_OFFSET); + retval &= ADC_DR_RDATA_MASK; + + if (count > 0) + { + iinfo("Count = %d\n", count); + } + + return retval; +} + +/**************************************************************************** + * Name: tc_y_sample + * + * Description: + * Initiate sampling on Y + * + ****************************************************************************/ + +static void tc_y_sample(void) +{ + /* Start the Y axis sampling */ + + tc_adc_start_sample(LCD_XL_CHANNEL); +} + +/**************************************************************************** + * Name: tc_x_sample + * + * Description: + * Initiate sampling on X + * + ****************************************************************************/ + +static void tc_x_sample(void) +{ + /* Start the X axis sampling */ + + tc_adc_start_sample(LCD_YD_CHANNEL); +} + +/**************************************************************************** + * Name: tc_valid_sample + ****************************************************************************/ + +static inline bool tc_valid_sample(uint16_t sample) +{ + return (sample > LOWER_THRESHOLD); +} + +/**************************************************************************** + * Name: tc_notify + ****************************************************************************/ + +static void tc_notify(struct tc_dev_s *priv) +{ + /* If no threads have the driver open, then just dump the state */ + +#ifdef CONFIG_TOUCHSCREEN_REFCNT + if ((priv->crefs == 0) && priv->sample.contact == CONTACT_UP) + { + priv->sample.contact = CONTACT_NONE; + priv->sample.valid = false; + priv->id++; + return; + } +#endif + + /* If there are threads waiting on poll() for touchscreen data to become + * available, then wake them up now. NOTE: we wake up all waiting threads + * because we do not know that they are going to do. If they all try to + * read the data, then some make end up blocking after all. + */ + + poll_notify(priv->fds, CONFIG_TOUCHSCREEN_NPOLLWAITERS, POLLIN); + + /* If there are threads waiting for read data, then signal one of them + * that the read data is available. + */ + + if (priv->nwaiters > 0) + { + /* After posting this semaphore, we need to exit because the + * touchscreen is no longer available. + */ + + nxsem_post(&priv->waitsem); + } +} + +/**************************************************************************** + * Name: tc_sample + * + * Assumptions: pre-emption is disabled + * + ****************************************************************************/ + +static int tc_sample(struct tc_dev_s *priv, + struct tc_sample_s *sample) +{ + int ret = -EAGAIN; + + /* Is there new touchscreen sample data available? */ + + if (priv->penchange) + { + /* Yes.. the state has changed in some way. Return a copy of the + * sampled data. + */ + + memcpy(sample, &priv->sample, sizeof(struct tc_sample_s)); + + /* Now manage state transitions */ + + if (sample->contact == CONTACT_UP) + { + /* Next.. no contact. Increment the ID so that next contact ID + * will be unique. X/Y positions are no longer valid. + */ + + priv->sample.contact = CONTACT_NONE; + priv->sample.valid = false; + priv->id++; + } + else if (sample->contact == CONTACT_DOWN) + { + /* First report -- next report will be a movement */ + + priv->sample.contact = CONTACT_MOVE; + } + + priv->penchange = false; + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: tc_waitsample + ****************************************************************************/ + +static int tc_waitsample(struct tc_dev_s *priv, + struct tc_sample_s *sample) +{ + int ret; + irqstate_t flags; + + /* Interrupts must be disabled when this is called to (1) prevent posting + * of semaphores from interrupt handlers, and (2) to prevent sampled data + * from changing until it has been reported. + */ + + flags = enter_critical_section(); + + /* Now release the mutex that manages mutually exclusive access to + * the device structure. This may cause other tasks to become ready to + * run, but they cannot run yet because pre-emption is disabled. + */ + + nxmutex_unlock(&priv->devlock); + + /* Try to get the a sample... if we cannot, then wait on the semaphore + * that is posted when new sample data is available. + */ + + while (tc_sample(priv, sample) < 0) + { + /* Wait for a change in the touchscreen state */ + + priv->nwaiters++; + ret = nxsem_wait(&priv->waitsem); + priv->nwaiters--; + + if (ret < 0) + { + goto errout; + } + } + + /* Re-acquire the semaphore that manages mutually exclusive access to + * the device structure. We may have to wait here. But we have our + * sample. Interrupts and pre-emption will be re-enabled while we wait. + */ + + ret = nxmutex_lock(&priv->devlock); + +errout: + /* Then re-enable interrupts. We might get interrupt here and there + * could be a new sample. But no new threads will run because we still + * have pre-emption disabled. + */ + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: tc_worker + ****************************************************************************/ + +static void tc_worker(void *arg) +{ + struct tc_dev_s *priv = (struct tc_dev_s *)arg; + uint32_t delay = TC_PENUP_POLL_TICKS; + uint16_t value; + uint16_t newx = 0; + int16_t xdiff; + int16_t ydiff; + + DEBUGASSERT(priv != NULL); + + /* Perform the next action based on the state of the conversions */ + + switch (priv->state) + { + /* The touchscreen is IDLE and we are ready to begin the next sample */ + + case TC_READY: + { + /* Select DRIVE for Y sampling */ + + /* Configure XL, XR with drive voltages and disable YU drive. Note + * that this is configuring the DRIVEA and DRIVEB outputs to enable + * the on-board transistor drive logic to energize the touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; + + /* Allow time for the Y DRIVE to settle */ + + priv->resamplecount = 0; + priv->sampcount = 0; + priv->value = 0; + priv->state = TC_READY_SETTLE; + delay = TC_SETTLE_TICKS; + } + break; + + case TC_READY_SETTLE: + { + /* Start Y sampling */ + + tc_y_sample(); + + /* Allow time for the Y pend down sampling */ + + priv->state = TC_YPENDOWN; + delay = TC_SAMPLE_TICKS; + } + break; + + /* The Y sampling time has elapsed and the Y value should be ready + * for conversion + */ + + case TC_YPENDOWN: + { + /* Convert the Y sample value */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that there is no touch + * and that the sampling period is complete. + */ + + if (!tc_valid_sample(value)) + { + priv->state = TC_PENUP; + } + else + { + /* Allow time for touch inputs to stabilize */ + + priv->state = TC_DEBOUNCE; + delay = TC_DEBOUNCE_TICKS; + } + } + break; + + /* The debounce time period has elapsed and we are ready to re-sample + * the touchscreen. + */ + + case TC_RESAMPLE: + { + /* Select DRIVE for Y sampling */ + + /* Configure XL, XR with drive voltages and disable YU drive. Note + * that this is configuring the DRIVEA and DRIVEB outputs to enable + * the on-board transistor drive logic to energize the touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPY_BITS; + + /* Allow time for the Y DRIVE to settle */ + + priv->state = TC_DEBOUNCE; + delay = TC_SETTLE_TICKS; + } + break; + + case TC_DEBOUNCE: + { + /* (Re-)start Y sampling */ + + tc_y_sample(); + + /* Allow time for the Y sampling */ + + priv->state = TC_YSAMPLE; + delay = TC_SAMPLE_TICKS; + } + break; + + /* The Y sampling period has elapsed and we are ready to perform the + * conversion. + */ + + case TC_YSAMPLE: /* Allowing time for the Y sampling */ + { + /* Read the Y axis position */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that we lost the + * contact before all of the conversions were completed. At + * converted value at the maximum value is probably bad too. + */ + + if (!tc_valid_sample(value)) + { +#ifdef CONFIG_TOUCHSCREEN_RESAMPLE + priv->state = TC_RESAMPLE; + delay = TC_RESAMPLE_TICKS; +#else + priv->state = TC_PENUP; +#endif + } + else + { + value = MAX_ADC - value; + priv->value += value; + if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) + { + priv->state = TC_READY_SETTLE; + delay = 1; + break; + } + + priv->newy = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; + priv->value = 0; + priv->sampcount = 0; + iinfo("Y=%d\n", priv->newy); + + /* Configure YU and YD with drive voltages and disable XR drive. + * Note that this is configuring the DRIVEA and DRIVEB outputs + * to enable the on-board transistor drive logic to energize the + * touch panel. + */ + + *((uint32_t *)LCD_TP_PORT_SETRESET) = LCD_SAMPX_BITS; + + /* Allow time for the X sampling */ + + priv->state = TC_XSETTLE; + delay = TC_SETTLE_TICKS; + } + } + break; + + case TC_XRESAMPLE: /* Perform X resampling */ + { + if (priv->resamplecount-- == 0) + { + priv->state = TC_PENUP; + break; + } + } + + case TC_XSETTLE: /* Allowing time X to settle after changing DRIVE */ + { + /* The X Drive settling time has elaspsed and it's time to start + * the conversion + */ + + /* Start X sampling */ + + tc_x_sample(); + + /* Allow time for the X sampling */ + + priv->state = TC_XSAMPLE; + delay = TC_SAMPLE_TICKS; + } + break; + + case TC_XSAMPLE: /* Allowing time for the X sampling */ + { + /* Read the converted X axis position */ + + value = tc_adc_read_sample(); + + /* A converted value at the minimum would mean that we lost the + * contact before all of the conversions were completed. At + * converted value at the maximum value is probably bad too. + */ + + if (!tc_valid_sample(value)) + { +#ifdef CONFIG_TOUCHSCREEN_RESAMPLE + priv->state = TC_XRESAMPLE; + if (priv->resamplecount == 0) + priv->resamplecount = 1; + delay = TC_RESAMPLE_TICKS; +#else + priv->state = TC_PENUP; +#endif + } + else + { + /* Calculate the X axis position */ + + priv->value += value; + if (++priv->sampcount < CONFIG_TOUCHSCREEN_AVG_SAMPLES) + { + priv->state = TC_XSETTLE; + delay = 1; + break; + } + + newx = value / CONFIG_TOUCHSCREEN_AVG_SAMPLES; + iinfo("X=%d\n", newx); + + /* Samples are available */ + + priv->state = TC_PENDOWN; + } + } + break; + } + + /* Check for terminal conditions.. */ + + /* Check if the sampling resulted in a pen up decision. If so, we need to + * handle the change from pen down to pen up. + */ + + if (priv->state == TC_PENUP) + { + /* Ignore if the pen was already down (CONTACT_NONE == pen up and + * already reported. CONTACT_UP == pen up, but not reported) + */ + + if (priv->sample.contact != CONTACT_NONE && + priv->sample.contact != CONTACT_UP) + { + /* The pen is up. We know from the above test, that this is a + * loss of contact condition. This will be changed to CONTACT_NONE + * after the loss of contact is sampled. + */ + + priv->sample.contact = CONTACT_UP; + + /* Indicate the availability of new sample data for this ID */ + + priv->sample.id = priv->id; + priv->penchange = true; + + /* Notify any waiters that new touchscreen data is available */ + + iinfo("1:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); + + tc_notify(priv); + } + + /* Set up for the next poll */ + + priv->sample.valid = false; + priv->state = TC_READY; + delay = TC_PENUP_POLL_TICKS; + } + + /* Check if the sampling resulted in a pen down decision. */ + + else if (priv->state == TC_PENDOWN) + { + /* It is a pen down event. If the last loss-of-contact event has not + * been processed yet, then we have to ignore the pen down event (or + * else it will look like a drag event) + */ + + if (priv->sample.contact != CONTACT_UP) + { + /* Perform a thresholding operation so that the results will be + * more stable. If the difference from the last sample is small, + * then ignore the event. + */ + + xdiff = (int16_t)priv->sample.x - (int16_t)newx; + if (xdiff < 0) + { + xdiff = -xdiff; + } + + ydiff = (int16_t)priv->sample.y - (int16_t)priv->newy; + if (ydiff < 0) + { + ydiff = -ydiff; + } + + if (xdiff >= CONFIG_TOUCHSCREEN_THRESHX || + ydiff >= CONFIG_TOUCHSCREEN_THRESHY) + { + /* There is some change above the threshold... + * Report the change. + */ + +#ifdef CONFIG_LCD_LANDSCAPE + priv->sample.x = MAX_ADC - priv->newy; + priv->sample.y = newx; +#else + priv->sample.x = newx; + priv->sample.y = priv->newy; +#endif + priv->sample.valid = true; + + /* If this is the first (acknowledged) penddown report, then + * report this as the 1st contact. If contact == CONTACT_DOWN, + * it will be set to set to CONTACT_MOVE after the contact is + * first sampled. + */ + + if (priv->sample.contact != CONTACT_MOVE) + { + /* First contact */ + + priv->sample.contact = CONTACT_DOWN; + } + + /* Indicate the availability of new sample data for this ID */ + + priv->sample.id = priv->id; + priv->penchange = true; + + /* Notify any waiters that nes touchscreen data is available */ + + iinfo("2:X=%d, Y=%d\n", priv->sample.x, priv->sample.y); + + tc_notify(priv); + } + } + + /* Set up for the next poll */ + + priv->state = TC_READY; + delay = TC_PENDOWN_POLL_TICKS; + } + + /* Set up the next sample event */ + + work_queue(HPWORK, &priv->work, tc_worker, priv, delay); +} + +/**************************************************************************** + * Name: tc_open + ****************************************************************************/ + +static int tc_open(struct file *filep) +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + struct inode *inode; + struct tc_dev_s *priv; + uint8_t tmp; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Increment the reference count */ + + tmp = priv->crefs + 1; + if (tmp == 0) + { + /* More than 255 opens; uint8_t overflows to zero */ + + ret = -EMFILE; + goto errout_with_lock; + } + + /* When the reference increments to 1, this is the first open event + * on the driver.. and an opportunity to do any one-time initialization. + */ + + /* Save the new open count on success */ + + priv->crefs = tmp; + +errout_with_lock: + nxmutex_unlock(&priv->devlock); + return ret; +#else + return OK; +#endif +} + +/**************************************************************************** + * Name: tc_close + ****************************************************************************/ + +static int tc_close(struct file *filep) +{ +#ifdef CONFIG_TOUCHSCREEN_REFCNT + struct inode *inode; + struct tc_dev_s *priv; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Decrement the reference count unless it would decrement a negative + * value. When the count decrements to zero, there are no further + * open references to the driver. + */ + + if (priv->crefs >= 1) + { + priv->crefs--; + } + + nxmutex_unlock(&priv->devlock); +#endif + return OK; +} + +/**************************************************************************** + * Name: tc_read + ****************************************************************************/ + +static ssize_t tc_read(struct file *filep, char *buffer, size_t len) +{ + struct inode *inode; + struct tc_dev_s *priv; + struct touch_sample_s *report; + struct tc_sample_s sample; + int ret; + + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Verify that the caller has provided a buffer large enough to receive + * the touch data. + */ + + if (len < SIZEOF_TOUCH_SAMPLE_S(1)) + { + /* We could provide logic to break up a touch report into segments and + * handle smaller reads... but why? + */ + + return -ENOSYS; + } + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Try to read sample data. */ + + ret = tc_sample(priv, &sample); + if (ret < 0) + { + /* Sample data is not available now. We would ave to wait to get + * receive sample data. If the user has specified the O_NONBLOCK + * option, then just return an error. + */ + + if (filep->f_oflags & O_NONBLOCK) + { + ret = -EAGAIN; + goto errout; + } + + /* Wait for sample data */ + + ret = tc_waitsample(priv, &sample); + if (ret < 0) + { + /* We might have been awakened by a signal */ + + goto errout; + } + } + + /* In any event, we now have sampled touchscreen data that we can report + * to the caller. + */ + + report = (struct touch_sample_s *)buffer; + memset(report, 0, SIZEOF_TOUCH_SAMPLE_S(1)); + report->npoints = 1; + report->point[0].id = sample.id; + report->point[0].x = sample.x; + report->point[0].y = sample.y; + + /* Report the appropriate flags */ + + if (sample.contact == CONTACT_UP) + { + /* Pen is now up. Is the positional data valid? This is important to + * know because the release will be sent to the window based on its + * last positional data. + */ + + if (sample.valid) + { + report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID | + TOUCH_POS_VALID | TOUCH_PRESSURE_VALID; + } + else + { + report->point[0].flags = TOUCH_UP | TOUCH_ID_VALID; + } + } + else + { + if (sample.contact == CONTACT_DOWN) + { + /* First contact */ + + report->point[0].flags = TOUCH_DOWN | TOUCH_ID_VALID | + TOUCH_POS_VALID; + } + else /* if (sample->contact == CONTACT_MOVE) */ + { + /* Movement of the same contact */ + + report->point[0].flags = TOUCH_MOVE | TOUCH_ID_VALID | + TOUCH_POS_VALID; + } + } + + ret = SIZEOF_TOUCH_SAMPLE_S(1); + +errout: + nxmutex_unlock(&priv->devlock); + return ret; +} + +/**************************************************************************** + * Name: tc_ioctl + ****************************************************************************/ + +static int tc_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if 1 + iinfo("cmd: %d arg: %ld\n", cmd, arg); + return -ENOTTY; /* None yet supported */ +#else + struct inode *inode; + struct tc_dev_s *priv; + int ret; + + iinfo("cmd: %d arg: %ld\n", cmd, arg); + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Get exclusive access to the driver data structure */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + /* Process the IOCTL by command */ + + switch (cmd) + { + /* ADD IOCTL COMMAND CASES HERE */ + + default: + ret = -ENOTTY; + break; + } + + nxmutex_unlock(&priv->devlock); + return ret; +#endif +} + +/**************************************************************************** + * Name: tc_poll + ****************************************************************************/ + +static int tc_poll(struct file *filep, struct pollfd *fds, bool setup) +{ + struct inode *inode; + struct tc_dev_s *priv; + int ret; + int i; + + iinfo("setup: %d\n", (int)setup); + DEBUGASSERT(fds); + inode = filep->f_inode; + + DEBUGASSERT(inode->i_private); + priv = inode->i_private; + + /* Are we setting up the poll? Or tearing it down? */ + + ret = nxmutex_lock(&priv->devlock); + if (ret < 0) + { + return ret; + } + + if (setup) + { + /* Ignore waits that do not include POLLIN */ + + if ((fds->events & POLLIN) == 0) + { + ierr("ERROR: Missing POLLIN: revents: %08" PRIx32 "\n", + fds->revents); + ret = -EDEADLK; + goto errout; + } + + /* This is a request to set up the poll. Find an available + * slot for the poll structure reference + */ + + for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++) + { + /* Find an available slot */ + + if (!priv->fds[i]) + { + /* Bind the poll structure and this slot */ + + priv->fds[i] = fds; + fds->priv = &priv->fds[i]; + break; + } + } + + if (i >= CONFIG_TOUCHSCREEN_NPOLLWAITERS) + { + ierr("ERROR: No available slot found: %d\n", i); + fds->priv = NULL; + ret = -EBUSY; + goto errout; + } + + /* Should we immediately notify on any of the requested events? */ + + if (priv->penchange) + { + poll_notify(&fds, 1, POLLIN); + } + } + else if (fds->priv) + { + /* This is a request to tear down the poll. */ + + struct pollfd **slot = (struct pollfd **)fds->priv; + DEBUGASSERT(slot != NULL); + + /* Remove all memory of the poll setup */ + + *slot = NULL; + fds->priv = NULL; + } + +errout: + nxmutex_unlock(&priv->devlock); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ + struct tc_dev_s *priv; + char devname[DEV_NAMELEN]; +#ifdef CONFIG_TOUCHSCREEN_MULTIPLE + irqstate_t flags; +#endif + int ret; + + iinfo("minor: %d\n", minor); + DEBUGASSERT(minor >= 0 && minor < 100); + + /* If we only have one touchscreen, check if we already did init */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + if (g_touchinitdone) + { + return OK; + } +#endif + + /* Configure the touchscreen DRIVEA and DRIVEB pins for output */ + + stm32_configgpio(GPIO_TP_DRIVEA); + stm32_configgpio(GPIO_TP_DRIVEB); + + /* Configure Analog inputs for sampling X and Y coordinates */ + + stm32_configgpio(GPIO_TP_XL); + stm32_configgpio(GPIO_TP_YD); + + tc_adc_init(); + + /* Create and initialize a touchscreen device driver instance */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + priv = &g_touchscreen; +#else + priv = kmm_malloc(sizeof(struct tc_dev_s)); + if (!priv) + { + ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct tc_dev_s)); + return -ENOMEM; + } +#endif + + /* Initialize the touchscreen device driver instance */ + + memset(priv, 0, sizeof(struct tc_dev_s)); + nxmutex_init(&priv->devlock); /* Initialize device structure mutex */ + nxsem_init(&priv->waitsem, 0, 0); /* Initialize pen event wait semaphore */ + + /* Register the device as an input device */ + + snprintf(devname, sizeof(devname), DEV_FORMAT, minor); + iinfo("Registering %s\n", devname); + + ret = register_driver(devname, &g_tc_fops, 0666, priv); + if (ret < 0) + { + ierr("ERROR: register_driver() failed: %d\n", ret); + goto errout_with_priv; + } + + /* Schedule work to perform the initial sampling and to set the data + * availability conditions. + */ + + priv->state = TC_READY; + ret = work_queue(HPWORK, &priv->work, tc_worker, priv, 0); + if (ret != 0) + { + ierr("ERROR: Failed to queue work: %d\n", ret); + goto errout_with_priv; + } + + /* And return success (?) */ + +#ifndef CONFIG_TOUCHSCREEN_MULTIPLE + g_touchinitdone = true; +#endif + + return OK; + +errout_with_priv: + nxmutex_destroy(&priv->devlock); + nxsem_destroy(&priv->waitsem); +#ifdef CONFIG_TOUCHSCREEN_MULTIPLE + kmm_free(priv); +#endif + return ret; +} + +#endif /* CONFIG_INPUT */ diff --git a/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c new file mode 100644 index 0000000000000..fc2c9b7af8f0c --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "mikroe-stm32f4.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB host Mass Storage Class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c index 00f3c919e2e8c..938fa1764412d 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt new file mode 100644 index 0000000000000..a8b1f68f8e169 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f401re/Kconfig b/boards/arm/stm32f4/nucleo-f401re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f401re/Kconfig rename to boards/arm/stm32f4/nucleo-f401re/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig new file mode 100644 index 0000000000000..7e41a42500837 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f401re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F401RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_FB_MODULEINFO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DEV=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_UG2864HSWEG01=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_SPI_DRIVER=y +CONFIG_SSD1306_FREQUENCY=1000000 +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig new file mode 100644 index 0000000000000..691067a8b3ab0 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f401re" +CONFIG_ARCH_BOARD_NUCLEO_F401RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f401re/include/board.h b/boards/arm/stm32f4/nucleo-f401re/include/board.h new file mode 100644 index 0000000000000..f8cff6a2383a6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/include/board.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-F401RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 84000000 Determined by PLL + * configuration + * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 16 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. + * Some possible solutions include: + * + * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 4 = 84,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 336,000,000 / 7 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 84000000ul + +/* AHB clock (HCLK) is SYSCLK (84MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F401RE board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F401RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs new file mode 100644 index 0000000000000..35c3c0c4e272d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld new file mode 100644 index 0000000000000..66d8d456dc6d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F401RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 96Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt new file mode 100644 index 0000000000000..b0ff5784c01e8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/nucleo-f401re/src/Make.defs b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs new file mode 100644 index 0000000000000..369d8455de3ec --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs @@ -0,0 +1,56 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f401re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c + +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c +endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h rename to boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h index 09a0d7af69a92..3e3010ad53b70 100644 --- a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h +++ b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h + * boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c new file mode 100644 index 0000000000000..71b9e0974ec49 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_adc.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_ADC_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_ADC_DMA +/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, GPIO_ADC1_IN0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* Configura ADC input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0 +}; + +#endif /* CONFIG_ADC_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..7aa585817726b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f401re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ + + /* Open the ADC driver for reading. */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..7ccc090918848 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c new file mode 100644 index 0000000000000..c37cf6b9febc7 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f401re.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c new file mode 100644 index 0000000000000..224f1ead6d9e8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#undef HAVE_LEDS +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + struct spi_dev_s *spi; + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + +#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) + board_lcd_initialize(); +#endif + +#ifdef CONFIG_VIDEO_FB + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ +#endif + + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F401RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c new file mode 100644 index 0000000000000..da3e2fb0ee6cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f401re.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..4865b4d69b089 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f401re.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..3a87e3e7af2d6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "nucleo-f401re.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c new file mode 100644 index 0000000000000..721b001a01463 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f401re.h" + +#include + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef CONFIG_LCD_SSD1306_SPI + stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ + stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CS, !selected); + } +#endif + +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); + } +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c new file mode 100644 index 0000000000000..c7737d5e3e0ec --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f401re.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (BOARD_LD2_BIT == (1 << led)) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* An output of '1' illuminates the LED */ + + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +#ifdef CONFIG_USERLED_LOWER_READSTATE +/**************************************************************************** + * Name: board_userled_getall + ****************************************************************************/ + +void board_userled_getall(uint32_t *ledset) +{ + /* Clear the LED bits */ + + *ledset = 0; + + /* Get LED state. An output of '1' illuminates the LED. */ + + *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); +} + +#endif /* CONFIG_USERLED_LOWER_READSTATE */ + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt new file mode 100644 index 0000000000000..bbf909582a5b7 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/Kconfig b/boards/arm/stm32f4/nucleo-f410rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f410rb/Kconfig rename to boards/arm/stm32f4/nucleo-f410rb/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..2f7c904678df6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f410rb" +CONFIG_ARCH_BOARD_NUCLEO_F410RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F410RB=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=32768 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2017 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FLASH_CONFIG_B=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32f4/nucleo-f410rb/include/board.h b/boards/arm/stm32f4/nucleo-f410rb/include/board.h new file mode 100644 index 0000000000000..4a264975b6f73 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/include/board.h @@ -0,0 +1,303 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEO410RB supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X3 crystals is not populated. + * Therefore the Nucleo-F410RB will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 100000000 Determined by PLL configuration + * HCLK(Hz) : 100000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 2 (STM32_PLLCFG_PLLM) + * PLLN : 50 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency � PLLN, + * 50 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 2) * 50 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 4 = 100,000,000 + * RNG Clock + * = PLL_VCO / PLLQ + * = 400,000,000 / 8 = 50,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 100000000ul + +/* AHB clock (HCLK) is SYSCLK (100MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (100MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* Timers driven from APB2 will be PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,9,11 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN +#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F410RB board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F410RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs new file mode 100644 index 0000000000000..02cb165c1f3af --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f410rb.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld rename to boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld index ec48fa2500b75..3cabdd87366e0 100644 --- a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld + * boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..99f2c446b2035 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt @@ -0,0 +1,41 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f410rb.ld") diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs new file mode 100644 index 0000000000000..dce7ead7aff34 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f410rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h rename to boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h index 1ff343716d0e6..a6f43ec0118de 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h +++ b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h + * boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c new file mode 100644 index 0000000000000..db05549543825 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "nucleo-f410rb.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_STM32_ADC1_DMA +/* ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 9, 8 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN9_0, GPIO_ADC1_IN8_0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 9 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN9_0 +}; + +#endif /* CONFIG_STM32_ADC1_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + syslog(LOG_ERR, "stm32_adc_setup configuration: %d\n", ADC1_NCHANNELS); + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..f182bd93aedbe --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f410rb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c new file mode 100644 index 0000000000000..41ead6f349cfd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nucleo-f410rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..53c3ee92501d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "nucleo-f410rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..a400a0692c98e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f410rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..80c619214d63b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f410rb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LD2) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt new file mode 100644 index 0000000000000..cbf8d25eb2d0e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/Kconfig b/boards/arm/stm32f4/nucleo-f411re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f411re/Kconfig rename to boards/arm/stm32f4/nucleo-f411re/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig new file mode 100644 index 0000000000000..a15efeda08509 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f411re" +CONFIG_ARCH_BOARD_NUCLEO_F411RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_CANUTILS_CANLIB=y +CONFIG_CAN_EXTID=y +CONFIG_CAN_MCP2515=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MCP2515_PHASESEG1=3 +CONFIG_MCP2515_PROPSEG=1 +CONFIG_MCP2515_SPI_SCK_FREQUENCY=500000 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig new file mode 100644 index 0000000000000..97a7772143003 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f411re" +CONFIG_ARCH_BOARD_NUCLEO_F411RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f411re/include/board.h b/boards/arm/stm32f4/nucleo-f411re/include/board.h new file mode 100644 index 0000000000000..6613554b8c486 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/include/board.h @@ -0,0 +1,377 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEOF411RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-FF411RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 104000000 Determined by PLL + * configuration + * HCLK(Hz) : 104000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 216 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 9 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=104MHz and we must have + * the USB clock= 48MHz. + * + * PLLQ = 13 PLLP = 6 PLLN=390 PLLM=10 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 10) * 390 + * = 624,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 624,000,000 / 6 = 104,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 624,000,000 / 13 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(10) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(390) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_6 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(13) + +#define STM32_SYSCLK_FREQUENCY 104000000ul + +/* AHB clock (HCLK) is SYSCLK (104MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (104MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F411RE board provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: + * the user button is connected to the I/O PC13 (pin 2) of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F411RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs new file mode 100644 index 0000000000000..15d0e61e1e998 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld new file mode 100644 index 0000000000000..2a160e7bbfca3 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and + * 128Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt new file mode 100644 index 0000000000000..951b203a531f1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_spi.c stm32_bringup.c) + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() +endif() + +if(CONFIG_CAN_MCP2515) + list(APPEND SRCS stm32_mcp2515.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/nucleo-f411re/src/Make.defs b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs new file mode 100644 index 0000000000000..9f0e1dfa8db92 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs @@ -0,0 +1,56 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f411re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c + +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c +endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif + +ifeq ($(CONFIG_CAN_MCP2515),y) + CSRCS += stm32_mcp2515.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h rename to boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h index 036d7b73c37de..2f052ef44dc34 100644 --- a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h +++ b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h + * boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c new file mode 100644 index 0000000000000..d07d2edbc6aae --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_adc.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_ADC_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_ADC_DMA +/* Configure ADC inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, GPIO_ADC1_IN0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* Configura ADC input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0 +}; + +#endif /* CONFIG_ADC_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..9ba5d9f69aa94 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c @@ -0,0 +1,490 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f411re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F411RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* NOTE: The ADC driver was initialized earlier in the bring-up sequence. */ + + /* Open the ADC driver for reading. */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..16655c5a13e3d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c new file mode 100644 index 0000000000000..aabbaf87e948d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f411re.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + stm32_spidev_initialize(); +#endif + + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c new file mode 100644 index 0000000000000..5d0025fdac224 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#undef HAVE_LEDS +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + struct spi_dev_s *spi; + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 1\n"); + return -ENODEV; + } + +#if defined(CONFIG_LCD_SSD1306_SPI) && !defined(CONFIG_VIDEO_FB) + board_lcd_initialize(); +#endif + +#ifdef CONFIG_VIDEO_FB + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN_MCP2515 +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MCP2515_CS); /* MEMS chip select */ +#endif + + /* Configure and initialize the MCP2515 CAN device */ + + ret = stm32_mcp2515initialize("/dev/can0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mcp2515initialize() failed: %d\n", ret); + } +#endif +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F411RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c new file mode 100644 index 0000000000000..25f46f0715463 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-f411re.h" + +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..1fda9fe85e2dc --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "stm32.h" +#include "nucleo-f411re.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c new file mode 100644 index 0000000000000..3b5cf927c8d3e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c @@ -0,0 +1,241 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_spi.h" +#include "nucleo-f411re.h" + +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI1) && \ + defined(CONFIG_CAN_MCP2515) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MCP2515_SPI_PORTNO 1 /* On SPI1 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_mcp2515config_s +{ + /* Configuration structure as seen by the MCP2515 driver */ + + struct mcp2515_config_s config; + + /* Additional private definitions only known to this driver */ + + struct mcp2515_can_s *handle; /* The MCP2515 driver handle */ + mcp2515_handler_t handler; /* The MCP2515 interrupt handler */ + void *arg; /* Argument to pass to the interrupt handler */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MCP2515 driver from differences in GPIO interrupt handling + * by varying boards and MCUs. + * + * attach - Attach the MCP2515 interrupt handler to the GPIO interrupt + */ + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MCP2515 + * driver. This structure provides information about the configuration + * of the MCP2515 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_mcp2515config_s g_mcp2515config = +{ + .config = + { + .spi = NULL, + .baud = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .btp = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .devid = 0, + .mode = 0, /* REVISIT. Probably broken by commit eb7373cedfa */ + .nfilters = 6, +#ifdef MCP2515_LOOPBACK + .loopback = false; +#endif + .attach = mcp2515_attach, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* This is the MCP2515 Interrupt handler */ + +int mcp2515_interrupt(int irq, void *context, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)arg; + + DEBUGASSERT(priv != NULL); + + /* Verify that we have a handler attached */ + + if (priv->handler) + { + /* Yes.. forward with interrupt along with its argument */ + + priv->handler(&priv->config, priv->arg); + } + + return OK; +} + +static int mcp2515_attach(struct mcp2515_config_s *state, + mcp2515_handler_t handler, void *arg) +{ + struct stm32_mcp2515config_s *priv = + (struct stm32_mcp2515config_s *)state; + irqstate_t flags; + + caninfo("Saving handler %p\n", handler); + + flags = enter_critical_section(); + + priv->handler = handler; + priv->arg = arg; + + /* Configure the interrupt for falling edge */ + + stm32_gpiosetevent(GPIO_MCP2515_IRQ, false, true, false, + mcp2515_interrupt, priv); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mcp2515initialize + * + * Description: + * Initialize and register the MCP2515 RFID driver. + * + * Input Parameters: + * devpath - The full path to the driver to register. E.g., "/dev/rfid0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_mcp2515initialize(const char *devpath) +{ + struct spi_dev_s *spi; + struct can_dev_s *can; + struct mcp2515_can_s *mcp2515; + int ret; + + /* Check if we are already initialized */ + + if (!g_mcp2515config.handle) + { + sninfo("Initializing\n"); + + /* Configure the MCP2515 interrupt pin as an input */ + + stm32_configgpio(GPIO_MCP2515_IRQ); + + spi = stm32_spibus_initialize(MCP2515_SPI_PORTNO); + + if (!spi) + { + return -ENODEV; + } + + /* Save the SPI instance in the mcp2515_config_s structure */ + + g_mcp2515config.config.spi = spi; + + /* Instantiate the MCP2515 CAN Driver */ + + mcp2515 = mcp2515_instantiate(&g_mcp2515config.config); + if (mcp2515 == NULL) + { + canerr("ERROR: Failed to get MCP2515 Driver Loaded\n"); + return -ENODEV; + } + + /* Save the opaque structure */ + + g_mcp2515config.handle = mcp2515; + + /* Initialize the CAN Device with the MCP2515 operations */ + + can = mcp2515_initialize(mcp2515); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register(devpath, can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + } + + return OK; +} + +#endif /* CONFIG_SPI && CONFIG_CAN_MCP2515 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c new file mode 100644 index 0000000000000..69a16d88c7f37 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f411re.h" + +#include + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F411RE + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef CONFIG_LCD_SSD1306_SPI + stm32_configgpio(GPIO_SSD1306_CS); /* SSD1306 chip select */ + stm32_configgpio(GPIO_SSD1306_CMD); /* SSD1306 data/!command */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CS, !selected); + } +#endif + +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306_SPI) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_SSD1306_CMD, !cmd); + } +#endif + + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c new file mode 100644 index 0000000000000..0cb15012e4ed0 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f411re.h" + +#include + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (BOARD_LD2_BIT == (1 << led)) + { + stm32_gpiowrite(GPIO_LD2, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* An output of '1' illuminates the LED */ + + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); +} + +#ifdef CONFIG_USERLED_LOWER_READSTATE +/**************************************************************************** + * Name: board_userled_getall + ****************************************************************************/ + +void board_userled_getall(uint32_t *ledset) +{ + /* Clear the LED bits */ + + *ledset = 0; + + /* Get LED state. An output of '1' illuminates the LED. */ + + *ledset |= ((stm32_gpioread(GPIO_LD2) & 1) << BOARD_LD2); +} + +#endif /* CONFIG_USERLED_LOWER_READSTATE */ + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt new file mode 100644 index 0000000000000..78c8c99ff2578 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/Kconfig b/boards/arm/stm32f4/nucleo-f412zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f412zg/Kconfig rename to boards/arm/stm32f4/nucleo-f412zg/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig new file mode 100644 index 0000000000000..4f4f921618ca3 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_MKRD=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig new file mode 100644 index 0000000000000..ece24fb0b1a7d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_TIMER=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig new file mode 100644 index 0000000000000..e6c03ecfce8b5 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f412zg" +CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CAN=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_HAVE_CXX=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/nucleo-f412zg/include/board.h b/boards/arm/stm32f4/nucleo-f412zg/include/board.h new file mode 100644 index 0000000000000..35a7fa13dd5b1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/include/board.h @@ -0,0 +1,228 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz Crystal + * LSE - not installed + */ + +#define STM32_BOARD_USEHSE 1 +#define STM32_BOARD_XTAL 8000000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 + +/* Main PLL Configuration */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) + +#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16) +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SSRC RCC_PLLI2SCFGR_PLLI2SSRC(0) /* HSE or HSI depending on PLLSRC of PLLCFGR*/ + +#define STM32_RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_PLL +#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB +#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (96MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* Timers driven from APB2 will be PCLK2 since no prescale division */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* Alternate function pin selections ****************************************/ + +/* USART2: + * RXD: PD6 CN9 pin 4 + * TXD: PD5 CN9 pin 6 + */ + +# define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) +# define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) + +/* USART3 (ST-LINK Virtual COM Port): + * RXD: PD9 + * TXD: PD8 + */ + +# define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) +# define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) + +/* USART6: + * RXD: PG9 CN10 pin 16 + * TXD: PG14 CN10 pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) + +/* I2C1: + * SCL: PB8 CN7 pin2 + * SDA: PB9 CN7 pin4 + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +/* SPI1: + * MISO: PA6 CN7 pin 12 + * MOSI: PA7 CN7 pin 14 + * SCK: PA5 CN7 pin 10 + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* CAN1: + * RX: PD0 CN9 pin 25 + * TX: PD1 CN9 pin 27 + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +/* LEDs + * + * The NUCLEO-F412ZG board has 3 user leds. + * LD1: PB0 GREEN + * LD2: PB7 BLUE + * LD3: PB14 RED + */ + +#define BOARD_NLEDS 3 + +#define GPIO_LD1 \ +(GPIO_PORTB | GPIO_PIN0 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD2 \ +(GPIO_PORTB | GPIO_PIN7 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +#define GPIO_LD3 \ +(GPIO_PORTB | GPIO_PIN14 | GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_PULLUP | \ +GPIO_SPEED_50MHz) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning + * ------------------- ----------------------- + * LED_STARTED NuttX has been started + * LED_HEAPALLOCATE Heap has been allocated + * LED_IRQSENABLED Interrupts enabled + * LED_STACKCREATED Idle stack created + * LED_INIRQ In an interrupt + * LED_SIGNAL In a signal handler + * LED_ASSERTION An assertion failed + * LED_PANIC The system has crashed + * LED_IDLE MCU is in sleep mode + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 1 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 3 +#define LED_INIRQ 0 +#define LED_SIGNAL 0 +#define LED_ASSERTION 1 +#define LED_PANIC 1 + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F412ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs new file mode 100644 index 0000000000000..7bd8f7113fd08 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f412zg.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld rename to boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld index 0c66b0979e5a4..d89c019092523 100644 --- a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld + * boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt new file mode 100644 index 0000000000000..48cd9e8753692 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt @@ -0,0 +1,35 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f412zg.ld") diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs new file mode 100644 index 0000000000000..9c28d010d9304 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs @@ -0,0 +1,38 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f412zg/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h rename to boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h index e0a4726994c8d..203f5ce92737b 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h +++ b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h + * boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c new file mode 100644 index 0000000000000..c9e7efe0a2481 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + stm32_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD3); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, true); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD3, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 1: + stm32_gpiowrite(GPIO_LD1, false); + break; + case 2: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + break; + case 3: + stm32_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD3, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c new file mode 100644 index 0000000000000..407e508cc35d5 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f412zg.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c new file mode 100644 index 0000000000000..695de2977b5d4 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c new file mode 100644 index 0000000000000..5359021bc9597 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c @@ -0,0 +1,352 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "nucleo-f412zg.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO +# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F411 Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required. + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs. + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, + CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface. + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt new file mode 100644 index 0000000000000..cefebbf5e5096 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/Kconfig b/boards/arm/stm32f4/nucleo-f429zi/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f429zi/Kconfig rename to boards/arm/stm32f4/nucleo-f429zi/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig new file mode 100644 index 0000000000000..d6a052fbd2a7f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig new file mode 100644 index 0000000000000..262b4becc718f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig new file mode 100644 index 0000000000000..a03f1d5e458d9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f429zi" +CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_NOTE=y +CONFIG_DRIVERS_NOTECTL=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_DUMP=y +CONFIG_SCHED_INSTRUMENTATION_FILTER=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_STACK_USAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TRACE=y +CONFIG_SYSTEM_TRACE_STACKSIZE=8192 +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f429zi/include/board.h b/boards/arm/stm32f4/nucleo-f429zi/include/board.h new file mode 100644 index 0000000000000..4e259c13a929c --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/include/board.h @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Do not include STM32 F4 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F4 Discovery board features a single 8MHz crystal. Space is + * provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 180000000 Determined by PLL config + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for highspeed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDMMC DMA is on DMA2 + * + * SDMMC1 DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + * + * SDMMC2 DMA + * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 + * DMAMAP_SDMMC3_2 = Channel 11, Stream 5 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 + +/* FLASH wait states + * + * --------- ---------- ----------- + * VDD MAX SYSCLK WAIT STATES + * --------- ---------- ----------- + * 1.7-2.1 V 180 MHz 8 + * 2.1-2.4 V 216 MHz 9 + * 2.4-2.7 V 216 MHz 8 + * 2.7-3.6 V 216 MHz 7 + * --------- ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 7 + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_BLUE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ --- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: Pushbutton B1, labeled "User", + * is connected to GPIO PI11. + * A high value will be sensed when the button is depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH1OUT (GPIO_TIM2_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM4_CH1OUT (GPIO_TIM4_CH1OUT_1|GPIO_SPEED_50MHz) + +#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_ARDUINO) + +/* USART6: + * + * These configurations assume that you are using a standard Arduio RS-232 + * shield with the serial interface with RX on pin D0 and TX on pin D1: + * + * -------- --------------- + * STM32F4 + * ARDUIONO FUNCTION GPIO + * -- ----- --------- ----- + * DO RX USART6_RX PG9 + * D1 TX USART6_TX PG14 + * -- ----- --------- ----- + */ + + # define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) + # define GPIO_USART6_TX (GPIO_USART6_TX_2|GPIO_SPEED_100MHz) +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port + */ + +#if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL) + # define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) + # define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) +#endif + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 +#define ADC2_DMA_CHAN DMAMAP_ADC2_1 +#define ADC3_DMA_CHAN DMAMAP_ADC3_1 + +/* SPI + * + * + * PA6 SPI1_MISO CN12-13 + * PA7 SPI1_MOSI CN12-15 + * PA5 SPI1_SCK CN12-11 + * + * PB14 SPI2_MISO CN12-28 + * PB15 SPI2_MOSI CN12-26 + * PB13 SPI2_SCK CN12-30 + * + * PB4 SPI3_MISO CN12-27 + * PB5 SPI3_MOSI CN12-29 + * PB3 SPI3_SCK CN12-31 + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_3|GPIO_SPEED_50MHz) + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +/* I2C + * + * + * PB8 I2C1_SCL CN12-3 + * PB9 I2C1_SDA CN12-5 + + * PB10 I2C2_SCL CN11-51 + * PB11 I2C2_SDA CN12-18 + * + * PA8 I2C3_SCL CN12-23 + * PC9 I2C3_SDA CN12-1 + * + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) + +/* The STM32 F4 connects to a SMSC LAN8742A PHY using these pins: + * + * STM32 F4 BOARD LAN8742A + * GPIO SIGNAL PIN NAME + * -------- ------------ ------------- + * PG11 RMII_TX_EN TXEN + * PG13 RMII_TXD0 TXD0 + * PB13 RMII_TXD1 TXD1 + * PC4 RMII_RXD0 RXD0/MODE0 + * PC5 RMII_RXD1 RXD1/MODE1 + * PG2 RMII_RXER RXER/PHYAD0 -- Not used + * PA7 RMII_CRS_DV CRS_DV/MODE2 + * PC1 RMII_MDC MDC + * PA2 RMII_MDIO MDIO + * N/A NRST nRST + * PA1 RMII_REF_CLK nINT/REFCLK0 + * N/A OSC_25M XTAL1/CLKIN + * + * The PHY address is either 0 or 1, depending on the state of PG2 on reset. + * PG2 is not controlled but appears to result in a PHY address of 0. + */ + +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32F4_NUCLEO_F429ZI_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs new file mode 100644 index 0000000000000..b60be2ea2217a --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld new file mode 100644 index 0000000000000..c1decce24f5f9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script new file mode 100644 index 0000000000000..9a1d4001a9959 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld new file mode 100644 index 0000000000000..ec8a5798e4ac2 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld new file mode 100644 index 0000000000000..2a9866a6758cf --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt new file mode 100644 index 0000000000000..1f6f30ca92b66 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt @@ -0,0 +1,73 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_BBSRAM) + list(APPEND SRCS stm32_bbsram.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs new file mode 100644 index 0000000000000..22ef4de2cdd6e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f429zi/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +CSRCS += stm32_bbsram.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += stm32_romfs_initialize.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h rename to boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h index c66f463faa4fc..60e0078b43c8a 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h +++ b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h + * boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c new file mode 100644 index 0000000000000..1c8b4361bdf3a --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "nucleo-144.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32F4_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32F4_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32F4_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = + { + 3 + }; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, + * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, + * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = + { + GPIO_ADC1_IN3 + }; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + if (g_pinlist[i] != 0) + { + stm32_configgpio(g_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c new file mode 100644 index 0000000000000..54359c2a1741f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_BLUE, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_BLUE, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_BLUE, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_BLUE, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c index a9c35cc5cc4f0..3d90e5cb5a21b 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c new file mode 100644 index 0000000000000..656da24f96794 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c @@ -0,0 +1,252 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "nucleo-144.h" + +#ifdef CONFIG_STM32_ROMFS +#include "stm32_romfs.h" +#endif + +#ifdef CONFIG_SENSORS_AMG88XX +#include "stm32_amg88xx.h" +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +# include "stm32_i2c.h" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization + * after all memory has been configured and mapped but + * before any devices have been initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_HOST) + stm32_usbinitialize(); +#endif + +#if defined(CONFIG_SPI) + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and + * just before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + /* Mount the romfs partition */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return; + } +#endif + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_BBSRAM + /* Initialize battery-backed RAM */ + + stm32_bbsram_int(); +#endif + +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) + /* Create SPI interfaces */ + + ret = stm32_spidev_bus_test(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI interfaces: %d\n", + ret); + return; + } +#endif + +#if defined(CONFIG_MMCSD) + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return; + } +#endif + +#if defined(CONFIG_PWM) + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2c_register(1); +#endif + +#ifdef CONFIG_SENSORS_AMG88XX + board_amg88xx_initialize(1); +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c new file mode 100644 index 0000000000000..26101a63eb997 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current + * state of all buttons or board_button_irq() may be called to register + * button interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() + * may be called to collect the state of all buttons. board_buttons() + * returns an 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each + * bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value + * is a button enumeration value that uniquely identifies a button + * resource. See the BUTTON_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, + true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c index c11a26e3adb8c..0cc0979f5780e 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c new file mode 100644 index 0000000000000..b58bf7c7a5c1f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c @@ -0,0 +1,323 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c new file mode 100644 index 0000000000000..a7186ebdb7c6e --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-144.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HAVE_PWM 1 +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32F4 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c new file mode 100644 index 0000000000000..c17caaa874e35 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h new file mode 100644 index 0000000000000..2e8f7f643cb82 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32F4_NUCLEOF429ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c new file mode 100644 index 0000000000000..8eaaf58c73dc1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file provides contents of an optional ROMFS volume, mounted at boot */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#else + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + " .section .rodata, \"a\" \n" + " .balign 16 \n" + " .globl romfs_data_begin \n" + "romfs_data_begin: \n" + " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" + " .balign " STR(ROMFS_SECTOR_SIZE) "\n" + " .globl romfs_data_end \n" + "romfs_data_end: \n" + ); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + size_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c new file mode 100644 index 0000000000000..fd8a1dca33e1b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "nucleo-144.h" +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" + +#ifdef CONFIG_MMCSD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(GPIO_SDMMC1_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDMMC1_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c new file mode 100644 index 0000000000000..fa7a2cc7519f8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c @@ -0,0 +1,496 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-144.h" + +#if defined(CONFIG_SPI) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_NUCLEO_SPI1_TEST) +# if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE1) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE2) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI1_TEST_MODE3) +# define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) +# if defined(CONFIG_NUCLEO_SPI2_TEST_MODE0) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE1) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE2) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI2_TEST_MODE3) +# define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" +# endif +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) +# if defined(CONFIG_NUCLEO_SPI3_TEST_MODE0) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE0 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE1) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE1 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE2) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE2 +# elif defined(CONFIG_NUCLEO_SPI3_TEST_MODE3) +# define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 +# else +# error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_STM32_SPI1) +static const uint32_t g_spi1gpio[] = +{ +# if defined(GPIO_SPI1_CS0) + GPIO_SPI1_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS1) + GPIO_SPI1_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS2) + GPIO_SPI1_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI1_CS3) + GPIO_SPI1_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_STM32_SPI2) +static const uint32_t g_spi2gpio[] = +{ +# if defined(GPIO_SPI2_CS0) + GPIO_SPI2_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS1) + GPIO_SPI2_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS2) + GPIO_SPI2_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI2_CS3) + GPIO_SPI2_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_STM32_SPI3) +static const uint32_t g_spi3gpio[] = +{ +# if defined(GPIO_SPI3_CS0) + GPIO_SPI3_CS0, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS1) + GPIO_SPI3_CS1, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS2) + GPIO_SPI3_CS2, +# else + 0, +# endif +# if defined(GPIO_SPI3_CS3) + GPIO_SPI3_CS3 +# else + 0 +# endif +}; +#endif + +#if defined(CONFIG_NUCLEO_SPI_TEST) +# if defined(CONFIG_STM32_SPI1) +struct spi_dev_s *spi1; +# endif +# if defined(CONFIG_STM32_SPI2) +struct spi_dev_s *spi2; +# endif +# if defined(CONFIG_STM32_SPI3) +struct spi_dev_s *spi3; +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + /* Configure SPI CS GPIO for output */ + +#if defined(CONFIG_STM32_SPI1) + for (int i = 0; i < nitems(g_spi1gpio); i++) + { + if (g_spi1gpio[i] != 0) + { + stm32_configgpio(g_spi1gpio[i]); + } + } +#endif + +#if defined(CONFIG_STM32_SPI2) + for (int i = 0; i < nitems(g_spi2gpio); i++) + { + if (g_spi2gpio[i] != 0) + { + stm32_configgpio(g_spi2gpio[i]); + } + } +#endif + +#if defined(CONFIG_STM32_SPI3) + for (int i = 0; i < nitems(g_spi3gpio); i++) + { + if (g_spi3gpio[i] != 0) + { + stm32_configgpio(g_spi3gpio[i]); + } + } +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5/6select and stm32_spi1/2/3/4/5/6status + * + * Description: + * The external functions, stm32_spi1/2/3/4/5/6select and + * stm32_spi1/2/3/4/5/6status must be provided by board-specific logic. + * They are implementations of the select and status methods of + * the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common + * STM32 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3/4/5/6select() and stm32_spi1/2/3/4/5/6status() + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in + * the way your board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI + * driver to the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi1gpio[index] != 0) + { + stm32_gpiowrite(g_spi1gpio[index], !selected); + } +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi2gpio[index] != 0) + { + stm32_gpiowrite(g_spi2gpio[index], !selected); + } +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + uint32_t index = SPIDEVID_INDEX(devid); + + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + if (g_spi3gpio[index] != 0) + { + stm32_gpiowrite(g_spi3gpio[index], !selected); + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI6 +void stm32_spi6select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5/6cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI6 +int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +#if defined(CONFIG_NUCLEO_SPI_TEST) +int stm32_spidev_bus_test(void) +{ + /* Configure and test SPI */ + + uint8_t *tx = (uint8_t *)CONFIG_NUCLEO_SPI_TEST_MESSAGE; + +#if defined(CONFIG_NUCLEO_SPI1_TEST) + spi1 = stm32_spibus_initialize(1); + + if (!spi1) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 1\n"); + return -ENODEV; + } + + /* Default SPI1 to NUCLEO_SPI1_FREQ and mode */ + + SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); + SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); + SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); + SPI_EXCHANGE(spi1, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI2_TEST) + spi2 = stm32_spibus_initialize(2); + + if (!spi2) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI2 to NUCLEO_SPI2_FREQ and mode */ + + SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); + SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); + SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); + SPI_EXCHANGE(spi2, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + +#if defined(CONFIG_NUCLEO_SPI3_TEST) + spi3 = stm32_spibus_initialize(3); + + if (!spi3) + { + syslog(LOG_ERR, "ERROR Failed to initialize SPI port 2\n"); + return -ENODEV; + } + + /* Default SPI3 to NUCLEO_SPI3_FREQ and mode */ + + SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); + SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); + SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); + SPI_EXCHANGE(spi3, tx, NULL, nitems(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); +#endif + + return OK; +} +#endif /* NUCLEO_SPI_TEST */ +#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c new file mode 100644 index 0000000000000..47d002de4cc52 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c @@ -0,0 +1,322 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "nucleo-144.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEO144_USBHOST_PRIO +# define CONFIG_NUCLEO144_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE +# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization + * to setup USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the + * USB host functionality. This function will start a thread + * that will monitor for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function + * must be provided be each platform that implements the + * STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, + * a charge pump or, if 5 V are available on the application board, + * a basic power switch, must be added externally to drive the 5 V + * VBUS line. The external charge pump can be driven by any GPIO + * output. When the application decides to power on VBUS using + * the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an + * overcurrent condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno + * value is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the + * USBDEV driver is used. This function is called whenever the + * USB enters or leaves suspend mode. This is an opportunity + * for the board logic to shutdown clocks, power, etc. while the + * USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c new file mode 100644 index 0000000000000..7677d7ba65c61 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-144.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_BLUE, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * NOTE: since there is only a single LED on-board, this is function + * is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt new file mode 100644 index 0000000000000..4371e311a7bf9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/Kconfig b/boards/arm/stm32f4/nucleo-f446re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f446re/Kconfig rename to boards/arm/stm32f4/nucleo-f446re/Kconfig diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig new file mode 100644 index 0000000000000..5b5f4de0bc0a4 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=2 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1 +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig new file mode 100644 index 0000000000000..bf16478bf0f30 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_CAN=y +CONFIG_EXAMPLES_CAN_NMSGS=100 +CONFIG_EXAMPLES_CAN_WRITE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN2=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig new file mode 100644 index 0000000000000..e549ee92ce967 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=16 +CONFIG_IOB_NBUFFERS=1024 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_EXTID=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=176 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=13 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig new file mode 100644 index 0000000000000..12275ba08bfb9 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig new file mode 100644 index 0000000000000..9367b5a74c27f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig new file mode 100644 index 0000000000000..243dbde9820d1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM08M1=y +CONFIG_BOARD_STM32_IHM08M1_POT=y +CONFIG_BOARD_STM32_IHM08M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH1NPOL=1 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH2NPOL=1 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_CH3NPOL=1 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig new file mode 100644 index 0000000000000..ce02324a89ad6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM08M1=y +CONFIG_BOARD_STM32_IHM08M1_POT=y +CONFIG_BOARD_STM32_IHM08M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=19152 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH1NPOL=1 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH2NPOL=1 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_CH3NPOL=1 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_TIM2=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig new file mode 100644 index 0000000000000..aa93ca052f811 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PULSECOUNT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig new file mode 100644 index 0000000000000..db27a7127b80b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_ILI9225=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig new file mode 100644 index 0000000000000..a4266c978ab70 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig new file mode 100644 index 0000000000000..d56c5382c30a6 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_DEVPATH="/dev/pwm2" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CRC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig new file mode 100644 index 0000000000000..9227f770c5526 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NUCLEO_F446RE_QETIMER=2 +CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=16386 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig new file mode 100644 index 0000000000000..891ed15e1505c --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DRIVERS_NOTERAM is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f446re" +CONFIG_ARCH_BOARD_NUCLEO_F446RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_NOTE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SEGGER_SYSVIEW=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/nucleo-f446re/include/board.h b/boards/arm/stm32f4/nucleo-f446re/include/board.h new file mode 100644 index 0000000000000..dc46e111057ad --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/include/board.h @@ -0,0 +1,444 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The NUCLEOF446RE supports both HSE and LSE crystals (X2 and X3). + * However, as shipped, the X2 and X3 crystals are not populated. + * Therefore the Nucleo-FF446RE will need to run off the 16MHz HSI clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 180000000 Determined by PLL config + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 216 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 9 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 4 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * target 180 MHz, source 16 MHz -> ratio = 11.25 = 22.5 x 2 = 45 x 4 + * so we can select a divider of 4 and a multiplier of 45 + * However multiplier must be between 50 and 432 + * so we double again to choose a multiplier of 90, and a divider of 8 + * VCO output frequency must be in range 100...432 MHz + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 50 <= PLLN <= 432 (50-99 only if VCO input > 1 MHz) + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + + * PLLQ = 7.5 PLLP = 2 PLLN=90 PLLM=4 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 4) * 90 + * = 360 MHz + * SYSCLK = PLL_VCO / PLLP + * = 360,000,000 / 2 = 180,000,000 + * USB OTG FS and SDIO Clock + * = TODO 7.5 is not possible + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(90) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(15) + +#define STM32_SYSCLK_FREQUENCY 180000000ul + +/* AHB clock (HCLK) is SYSCLK (104MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (52MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 (REVISIT) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (104MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + * + * REVISIT + */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + * + * REVISIT + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + * + * REVISIT + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* ADC 1 */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if !defined(CONFIG_BOARD_STM32_IHM08M1) +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET| \ + GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The Nucleo F446RE and F411RE boards provide a single user LED, LD2. LD2 + * is the green LED connected to Arduino signal D13 corresponding to MCU I/O + * PA5 (pin 21) or PB13 (pin 34) depending on the STM32 target. + * + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD2 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD2_BIT (1 << BOARD_LD2) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PC13 (pin 2) of + * the STM32 microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* TIM2 input ***************************************************************/ + +#ifndef CONFIG_NUCLEO_F446RE_QETIMER_TIM2_IHM08M1_MAP +# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA8 */ +# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB0 */ +#else +# define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +# define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ +#endif + +/* TIM3 configuration *******************************************************/ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) + +/* TIM8 configuration *******************************************************/ + +#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) /* PC6 */ + +#ifdef CONFIG_BOARD_STM32_IHM08M1 + +/* Configuration specific to the X-NUCLEO-IHM08M1 expansion board with + * the L6398 gate drivers. + */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_1 /* TIM1 CH1N - PA7 - U low */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_1 /* TIM1 CH2N - PB0 - V low */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_1 /* TIM1 CH3N - PB1 - W low */ +#define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* Board LED */ + +# define GPIO_FOC_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +/* Debug pin */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5) + +#endif /* CONFIG_BOARD_STM32_IHM08M1 */ + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs new file mode 100644 index 0000000000000..e2c1dea47e06f --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f446re.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld similarity index 98% rename from boards/arm/stm32/nucleo-f446re/scripts/f446re.ld rename to boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld index bdb91d982c9dc..cc81e91e33f55 100644 --- a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/scripts/f446re.ld + * boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt new file mode 100644 index 0000000000000..25458b16ff5ca --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_LCD_ILI9225) + list(APPEND SRCS stm32_ili9225.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + if(CONFIG_INPUT_AJOYSTICK) + list(APPEND SRCS stm32_ajoystick.c) + endif() + endif() +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_BOARD_STM32_IHM08M1) + list(APPEND SRCS stm32_foc_ihm08m1.c) +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs new file mode 100644 index 0000000000000..f861a66574e08 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs @@ -0,0 +1,81 @@ +############################################################################ +# boards/arm/stm32f4/nucleo-f446re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LCD_ILI9225),y) +CSRCS += stm32_ili9225.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +ifeq ($(CONFIG_INPUT_AJOYSTICK),y) +CSRCS += stm32_ajoystick.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) +CSRCS += stm32_foc_ihm08m1.c +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += stm32_romfs_initialize.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h rename to boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h index 9510bade876e0..d3e51ce12cccd 100644 --- a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h +++ b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h + * boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c new file mode 100644 index 0000000000000..a39c53c93c552 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#ifdef CONFIG_STM32_ADC1_DMA +# define ADC1_NCHANNELS 2 +#else +# define ADC1_NCHANNELS 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +#ifdef CONFIG_STM32_ADC1_DMA +/* The Itead analog joystick gets inputs on ADC_IN0 and ADC_IN1 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 1 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0, + GPIO_ADC1_IN1_0 +}; + +#else +/* Without DMA, only a single channel can be supported */ + +/* The Itead analog joystick gets input on ADC_IN0 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0_0 +}; + +#endif /* CONFIG_STM32_ADC1_DMA */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c new file mode 100644 index 0000000000000..4027f6b925860 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c @@ -0,0 +1,491 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "hardware/stm32_adc.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Check for pre-requisites and pin conflicts */ + +#ifdef CONFIG_INPUT_AJOYSTICK +# if !defined(CONFIG_ADC) +# error CONFIG_ADC is required for the Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick +# undef CONFIG_INPUT_AJOYSTICK +# endif +#endif /* CONFIG_INPUT_AJOYSTICK */ + +#ifdef CONFIG_INPUT_AJOYSTICK + +/* A no-ADC, buttons only version can be built for testing */ + +#undef NO_JOYSTICK_ADC + +/* Maximum number of ADC channels */ + +#define MAX_ADC_CHANNELS 8 + +/* Dual channel ADC support requires DMA */ + +#ifdef CONFIG_ADC_DMA +# define NJOYSTICK_CHANNELS 2 +#else +# define NJOYSTICK_CHANNELS 1 +#endif + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 3 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT) +#else +/* Number of Joystick buttons */ + +# define AJOY_NGPIOS 7 + +/* Bitset of supported Joystick buttons */ + +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ + AJOY_BUTTON_3_BIT | AJOY_BUTTON_4_BIT | \ + AJOY_BUTTON_5_BIT | AJOY_BUTTON_6_BIT | \ + AJOY_BUTTON_7_BIT ) +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower); +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample); +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower); +static void +ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg); + +static void ajoy_disable(void); +static int ajoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Itead joystick button. Index using AJOY_* + * button definitions in include/nuttx/input/ajoystick.h. + */ + +#ifdef CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3 +}; +#else +static const uint32_t g_joygpio[AJOY_NGPIOS] = +{ + GPIO_BUTTON_1, GPIO_BUTTON_2, GPIO_BUTTON_3, GPIO_BUTTON_4, + GPIO_BUTTON_5, GPIO_BUTTON_6, GPIO_BUTTON_7 +}; +#endif + +/* This is the button joystick lower half driver interface */ + +static const struct ajoy_lowerhalf_s g_ajoylower = +{ + .al_supported = ajoy_supported, + .al_sample = ajoy_sample, + .al_buttons = ajoy_buttons, + .al_enable = ajoy_enable, +}; + +#ifndef NO_JOYSTICK_ADC +/* Thread-independent file structure for the open ADC driver */ + +static struct file g_adcfile; +#endif + +/* Current interrupt handler and argument */ + +static ajoy_handler_t g_ajoyhandler; +static void *g_ajoyarg; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ajoy_supported + * + * Description: + * Return the set of buttons supported on the button joystick device + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_supported(const struct ajoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", AJOY_SUPPORTED); + return (ajoy_buttonset_t)AJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: ajoy_sample + * + * Description: + * Return the current state of all button joystick buttons + * + ****************************************************************************/ + +static int ajoy_sample(const struct ajoy_lowerhalf_s *lower, + struct ajoy_sample_s *sample) +{ +#ifndef NO_JOYSTICK_ADC + struct adc_msg_s adcmsg[MAX_ADC_CHANNELS]; + struct adc_msg_s *ptr; + ssize_t nread; + ssize_t offset; + int have; + int i; + + /* Read all of the available samples (handling the case where additional + * channels are enabled). + */ + + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + if (nread < 0) + { + if (nread != -EINTR) + { + ierr("ERROR: read failed: %d\n", (int)nread); + } + + return nread; + } + else if (nread < NJOYSTICK_CHANNELS * sizeof(struct adc_msg_s)) + { + ierr("ERROR: read too small: %ld\n", (long)nread); + return -EIO; + } + + /* Sample and the raw analog inputs */ + +#ifdef CONFIG_ADC_DMA + have = 0; + +#else + /* If DMA is not supported, then we will have only a single ADC channel */ + + have = 2; + sample->as_y = 0; +#endif + + for (i = 0, offset = 0; + i < MAX_ADC_CHANNELS && offset < nread && have != 3; + i++, offset += sizeof(struct adc_msg_s)) + { + ptr = &adcmsg[i]; + + /* Is this one of the channels that we need? */ + + if ((have & 1) == 0 && ptr->am_channel == 0) + { + int32_t tmp = ptr->am_data; + sample->as_x = (int16_t)tmp; + have |= 1; + + iinfo("X sample: %ld -> %d\n", (long)tmp, (int)sample->as_x); + } + +#ifdef CONFIG_ADC_DMA + if ((have & 2) == 0 && ptr->am_channel == 1) + { + int32_t tmp = ptr->am_data; + sample->as_y = (int16_t)tmp; + have |= 2; + + iinfo("Y sample: %ld -> %d\n", (long)tmp, (int)sample->as_y); + } +#endif + } + + if (have != 3) + { + ierr("ERROR: Could not find joystick channels\n"); + return -EIO; + } + +#else + /* ADC support is disabled */ + + sample->as_x = 0; + sample->as_y = 0; +#endif + + /* Sample the discrete button inputs */ + + sample->as_buttons = ajoy_buttons(lower); + iinfo("Returning: %02x\n", sample->as_buttons); + return OK; +} + +/**************************************************************************** + * Name: ajoy_buttons + * + * Description: + * Return the current state of button data (only) + * + ****************************************************************************/ + +static ajoy_buttonset_t +ajoy_buttons(const struct ajoy_lowerhalf_s *lower) +{ + ajoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Button outputs are pulled high. So a sensed low level means that the + * button is pressed. + */ + + if (!stm32_gpioread(g_joygpio[i])) + { + ret |= (1 << i); + } + } + + iinfo("Returning: %02x\n", ret); + return ret; +} + +/**************************************************************************** + * Name: ajoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, + ajoy_buttonset_t press, ajoy_buttonset_t release, + ajoy_handler_t handler, void *arg) +{ + irqstate_t flags; + ajoy_buttonset_t either = press | release; + ajoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + ajoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_ajoyhandler = handler; + g_ajoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, ajoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: ajoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void ajoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < AJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_ajoyhandler = NULL; + g_ajoyarg = NULL; +} + +/**************************************************************************** + * Name: ajoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int ajoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_ajoyhandler); + + if (g_ajoyhandler) + { + g_ajoyhandler(&g_ajoylower, g_ajoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ajoy_initialize + * + * Description: + * Initialize and register the button joystick driver + * + ****************************************************************************/ + +int board_ajoy_initialize(void) +{ + int ret; + int i; + +#ifndef NO_JOYSTICK_ADC + iinfo("Initialize ADC driver: /dev/adc0\n"); + + /* Open the ADC driver for reading. + * NOTE: The ADC driver was initialized earlier in the bring-up sequence. + */ + + ret = file_open(&g_adcfile, "/dev/adc0", O_RDONLY); + if (ret < 0) + { + ierr("ERROR: Failed to open /dev/adc0: %d\n", ret); + return ret; + } +#endif + + /* Configure the GPIO pins as interrupting inputs. NOTE: This is + * unnecessary for interrupting pins since it will also be done by + * stm32_gpiosetevent(). + */ + + for (i = 0; i < AJOY_NGPIOS; i++) + { + /* Configure the PIO as an input */ + + stm32_configgpio(g_joygpio[i]); + } + + /* Register the joystick device as /dev/ajoy0 */ + + iinfo("Initialize joystick driver: /dev/ajoy0\n"); + + ret = ajoy_register("/dev/ajoy0", &g_ajoylower); + if (ret < 0) + { + ierr("ERROR: ajoy_register failed: %d\n", ret); +#ifndef NO_JOYSTICK_ADC + file_close(&g_adcfile); +#endif + } + + return ret; +} + +#endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ab223ac8a5284 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LD2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LD2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c new file mode 100644 index 0000000000000..9ac3db6e971d8 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * broughtvinto the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c new file mode 100644 index 0000000000000..94dd44f58397a --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c @@ -0,0 +1,302 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#ifdef CONFIG_PULSECOUNT +# include "stm32_pulsecount.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32_romfs.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef CONFIG_PULSECOUNT + struct pulsecount_lowerhalf_s *pulsecount; +#endif + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_STM32_ROMFS + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_MMCSD + /* First, get an instance of the SDIO interface */ + + g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_sdio) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. There is no + * card detect GPIO. + */ + + sdio_mediachange(g_sdio, true); + + syslog(LOG_INFO, "[boot] Initialized SDIO\n"); +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PULSECOUNT + /* Initialize and register the pulse count driver. */ + + pulsecount = stm32_pulsecountinitialize(8); + if (pulsecount == NULL) + { + syslog(LOG_ERR, "ERROR: stm32_pulsecountinitialize failed\n"); + return -ENODEV; + } + + ret = pulsecount_register("/dev/pulsecount0", pulsecount); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pulsecount_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_F446RE_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_AJOYSTICK + /* Initialize and register the joystick driver */ + + ret = board_ajoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the joystick driver: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c new file mode 100644 index 0000000000000..9b267ab7ae7ce --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c @@ -0,0 +1,115 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-f446re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check that state of each USER button. A LOW value means that the key is + * pressed. + */ + + bool released = stm32_gpioread(GPIO_BTN_USER); + return !released; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c new file mode 100644 index 0000000000000..bb052a7c12464 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + +#ifdef CONFIG_STM32_CAN1 + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_STM32_CAN2 + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(2); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can1" */ + + ret = can_register("/dev/can1", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + +#endif + UNUSED(ret); + UNUSED(can); + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c new file mode 100644 index 0000000000000..a41b61f230761 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_can.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_STM32_CAN1 + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + goto errout; + } +#endif + +#ifdef CONFIG_STM32_CAN2 + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + ret = stm32_cansockinitialize(2); + if (ret < 0) + { + canerr("ERROR: Failed to get CAN interface %d\n", ret); + goto errout; + } +#endif + +errout: + return ret; +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c new file mode 100644 index 0000000000000..bb835a90f0423 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "nucleo-f446re.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_DAC1CH1 +static struct dac_dev_s *g_dac1; +#endif + +#ifdef CONFIG_STM32_DAC1CH2 +static struct dac_dev_s *g_dac2; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + int ret; +#ifdef CONFIG_STM32_DAC1CH1 + g_dac1 = stm32_dacinitialize(1); + if (g_dac1 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac1); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif +#ifdef CONFIG_STM32_DAC1CH2 + g_dac2 = stm32_dacinitialize(2); + if (g_dac2 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac1" */ + + ret = dac_register("/dev/dac1", g_dac2); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c index 99857b6aa012a..047dca4ffa0a5 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c new file mode 100644 index 0000000000000..46fba657f50cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c index 435ba03a61295..5966852282063 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c new file mode 100644 index 0000000000000..e091f026a7124 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-f446re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + * Return Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef CONFIG_PWM + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + +#if defined(CONFIG_STM32_TIM1_PWM) + pwm = stm32_pwminitialize(1); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM2_PWM) + pwm = stm32_pwminitialize(2); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM3_PWM) + pwm = stm32_pwminitialize(3); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_TIM4_PWM) + pwm = stm32_pwminitialize(4); + if (!pwm) + { + pwmerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + pwmerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + +#endif + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h new file mode 100644 index 0000000000000..fa4e75ddadddf --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c new file mode 100644 index 0000000000000..f1fe6d0806254 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file provides contents of an optional ROMFS volume, mounted at boot */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#else + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + " .section .rodata, \"a\" \n" + " .balign 16 \n" + " .globl romfs_data_begin \n" + "romfs_data_begin: \n" + " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" + " .balign " STR(ROMFS_SECTOR_SIZE) "\n" + " .globl romfs_data_end \n" + "romfs_data_end: \n" + ); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + uintptr_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = (uintptr_t)romfs_data_end - (uintptr_t)romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c new file mode 100644 index 0000000000000..65b9768161fff --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c @@ -0,0 +1,236 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "nucleo-f446re.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 +struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 +struct spi_dev_s *g_spi2; +#endif +#ifdef CONFIG_STM32_SPI3 +struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and + * Nucleo-F411RE boards. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + /* Configure SPI-based devices */ + + g_spi1 = stm32_spibus_initialize(1); + if (!g_spi1) + { + spierr("ERROR: FAILED to initialize SPI port 1\n"); + } + +#ifdef HAVE_MMCSD + stm32_configgpio(GPIO_SPI_CS_SD_CARD); +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Configure SPI-based devices */ + + g_spi2 = stm32_spibus_initialize(2); +#endif + +#ifdef CONFIG_STM32_SPI3 + /* Configure SPI-based devices */ + + g_spi3 = stm32_spibus_initialize(3); + +#ifdef HAVE_LCD + stm32_configgpio(GPIO_LCD_CS); + stm32_configgpio(GPIO_LCD_RS); +#endif + +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef HAVE_MMCSD + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef HAVE_LCD + stm32_gpiowrite(GPIO_LCD_CS, !selected); +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return OK; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + stm32_gpiowrite(GPIO_LCD_RS, !cmd); + return OK; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c new file mode 100644 index 0000000000000..8a2c4d80797cd --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-f446re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD2, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/odrive36/CMakeLists.txt b/boards/arm/stm32f4/odrive36/CMakeLists.txt new file mode 100644 index 0000000000000..61c57407acdf8 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/odrive36/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/odrive36/Kconfig b/boards/arm/stm32f4/odrive36/Kconfig similarity index 100% rename from boards/arm/stm32/odrive36/Kconfig rename to boards/arm/stm32f4/odrive36/Kconfig diff --git a/boards/arm/stm32f4/odrive36/configs/nsh/defconfig b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig new file mode 100644 index 0000000000000..fd7a87f012fc6 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="odrive36" +CONFIG_ARCH_BOARD_ODRIVE36=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15272 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0ce1ca15d65e4 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="odrive36" +CONFIG_ARCH_BOARD_ODRIVE36=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=15272 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/odrive36/include/board.h b/boards/arm/stm32f4/odrive36/include/board.h new file mode 100644 index 0000000000000..88d42164eaf24 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/include/board.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif +#include "stm32_rcc.h" +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* DMA Channel/Stream Selections ********************************************/ + +/* ADC 1 */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* Alternate function pin selections ****************************************/ + +/* ADC */ + +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 +#define GPIO_ADC1_IN6 GPIO_ADC1_IN6_0 +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 + +#define GPIO_ADC2_IN10 GPIO_ADC2_IN10_0 +#define GPIO_ADC2_IN11 GPIO_ADC2_IN11_0 +#define GPIO_ADC2_IN12 GPIO_ADC2_IN13_0 + +#define GPIO_ADC3_IN12 GPIO_ADC3_IN12_0 +#define GPIO_ADC3_IN13 GPIO_ADC3_IN13_0 + +/* USART2: + * USART2_TX - PA2 - GPIO_3 + * USART2_RX - PA3 - GPIO_4 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) + +/* CAN: + * CAN_R - PB8 + * CAN_T - PB9 + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +/* SPI3 - connected to DRV8301 + * SPI3_SCK - PC10 + * SPI3_MISO - PC11 + * SPI3_MOSI - PC12 + */ + +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) + +/* USBDEV */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) + +/* Dual FOC configuration */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1N_2|GPIO_SPEED_100MHz) /* TIM1 CH1N - PB13 - U low */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2N_2|GPIO_SPEED_100MHz) /* TIM1 CH2N - PB14 - V low */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3N_2|GPIO_SPEED_100MHz) /* TIM1 CH3N - PB15 - W low */ +#define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* TIM8 configuration *******************************************************/ + +#define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH1 - PC6 - U high */ +#define GPIO_TIM8_CH1NOUT (GPIO_TIM8_CH1N_2|GPIO_SPEED_100MHz) /* TIM8 CH1N - PA7 - U low */ +#define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH2 - PC7 - V high */ +#define GPIO_TIM8_CH2NOUT (GPIO_TIM8_CH2N_1|GPIO_SPEED_100MHz) /* TIM8 CH2N - PB0 - V low */ +#define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_100MHz) /* TIM8 CH3 - PC8 - W high */ +#define GPIO_TIM8_CH3NOUT (GPIO_TIM8_CH3N_1|GPIO_SPEED_100MHz) /* TIM8 CH3N - PB1 - W low */ +#define GPIO_TIM8_CH4OUT 0 /* not used as output */ + +/* QEN3 configuration *******************************************************/ + +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) /* TIM3 CH1IN - PB4 */ +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) /* TIM3 CH2IN - PB5 */ + +/* QEN4 configuration *******************************************************/ + +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_1|GPIO_SPEED_50MHz) /* TIM4 CH1IN - PB6 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_1|GPIO_SPEED_50MHz) /* TIM4 CH2IN - PB7 */ + +#endif /* __BOARDS_ARM_STM32_ODRIVE36_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/odrive36/scripts/Make.defs b/boards/arm/stm32f4/odrive36/scripts/Make.defs new file mode 100644 index 0000000000000..afe5816161125 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/scripts/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/odrive36/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/odrive36/scripts/ld.script b/boards/arm/stm32f4/odrive36/scripts/ld.script new file mode 100644 index 0000000000000..e96bd2dde2af2 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/odrive36/src/CMakeLists.txt b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt new file mode 100644 index 0000000000000..3cb279a2f7221 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt @@ -0,0 +1,39 @@ +# ############################################################################## +# boards/arm/stm32f4/odrive36/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/odrive36/src/Make.defs b/boards/arm/stm32f4/odrive36/src/Make.defs new file mode 100644 index 0000000000000..1b8f5678a4648 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/odrive36/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CSRCS += stm32_foc.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += $(shell $(INCDIR) "$(CC)" $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board) diff --git a/boards/arm/stm32/odrive36/src/odrive.h b/boards/arm/stm32f4/odrive36/src/odrive.h similarity index 99% rename from boards/arm/stm32/odrive36/src/odrive.h rename to boards/arm/stm32f4/odrive36/src/odrive.h index c8de89d3b2a99..22d37671a3d2b 100644 --- a/boards/arm/stm32/odrive36/src/odrive.h +++ b/boards/arm/stm32f4/odrive36/src/odrive.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/odrive.h + * boards/arm/stm32f4/odrive36/src/odrive.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/odrive36/src/stm32_boot.c b/boards/arm/stm32f4/odrive36/src/stm32_boot.c new file mode 100644 index 0000000000000..8d0b01456725b --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_boot.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "odrive.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_SEGGER_SYSVIEW + up_perf_init((void *)STM32_SYSCLK_FREQUENCY); +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/odrive36/src/stm32_bringup.c b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c new file mode 100644 index 0000000000000..23a07ac524b8d --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include +#include + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +# include "stm32_qencoder.h" +#endif + +#include "odrive.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the PROC filesystem: %d\n", + ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ + +#if defined(CONFIG_STM32_TIM3_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver - TIM3 */ + + ret = board_qencoder_initialize(0, 3); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); + } + + /* Connect QE index pin */ + + ret = stm32_qe_index_init(3, GPIO_QE3_INDEX); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); + } +#endif + +#if defined(CONFIG_STM32_TIM4_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver - TIM4 */ + + ret = board_qencoder_initialize(1, 4); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", ret); + } + + /* Connect QE index pin */ + + ret = stm32_qe_index_init(4, GPIO_QE4_INDEX); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to register qe index pin: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register FOC devices */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/odrive36/src/stm32_foc.c b/boards/arm/stm32f4/odrive36/src/stm32_foc.c new file mode 100644 index 0000000000000..8e3ee20001356 --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_foc.c @@ -0,0 +1,962 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_foc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include "stm32_foc.h" +#include "stm32_gpio.h" +#ifdef CONFIG_ADC +# include "stm32_adc.h" +#endif + +#include "odrive.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_ODRIVE_HW_VOLTAGE_56 +# error Tested only for ODrive 56V version +#endif + +/* Supported FOC instances */ + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +# define ODRIVE_FOC_FOC0 1 +#else +# define ODRIVE_FOC_FOC0 0 +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +# define ODRIVE_FOC_FOC1 1 +#else +# define ODRIVE_FOC_FOC1 0 +#endif + +#define ODRIVE_FOC_INST (ODRIVE_FOC_FOC0 + ODRIVE_FOC_FOC1) + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +# define ODRIVE32_FOC0_DEVPATH "/dev/foc0" +# define ODRIVE32_FOC0_INST (0) +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +# define ODRIVE32_FOC1_DEVPATH "/dev/foc1" +# define ODRIVE32_FOC1_INST (1) +#endif + +/* Must match upper-half configuration */ + +#if ODRIVE_FOC_INST != CONFIG_MOTOR_FOC_INST +# error Invalid configuration +#endif + +/* Only 2-shunt configuration supported by board */ + +#if CONFIG_MOTOR_FOC_SHUNTS != 2 +# error For now only 2-shunts configuration is supported +#endif + +/* Configuration specific for DRV8301: + * 1. PWM channels must have positive polarity + * 2. PWM complementary channels must have positive polarity + */ + +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# error +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + +# if CONFIG_STM32_TIM1_CH1POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH2POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH3POL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH1NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH2NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM1_CH3NPOL != 0 +# error +# endif + +/* FOC0 uses ADC2 */ + +# ifndef CONFIG_STM32_FOC_FOC0_ADC2 +# error +# endif + +# if CONFIG_STM32_ADC2_RESOLUTION != 0 +# error +# endif + +#endif /* CONFIG_ODRIVE_FOC_FOC0 */ + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + +# if CONFIG_STM32_TIM8_CH1POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH2POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH3POL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH1NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH2NPOL != 0 +# error +# endif +# if CONFIG_STM32_TIM8_CH3NPOL != 0 +# error +# endif + +/* FOC1 uses ADC3 */ + +# ifndef CONFIG_STM32_FOC_FOC1_ADC3 +# error +# endif + +# if CONFIG_STM32_ADC3_RESOLUTION != 0 +# error +# endif + +#endif /* CONFIG_ODRIVE_FOC_FOC1 */ + +/* Aux ADC needs DMA enabled */ + +#ifdef CONFIG_ADC +# ifndef CONFIG_STM32_ADC1_DMA +# error +# endif +# ifndef CONFIG_STM32_ADC1_SCAN +# error +# endif +#endif + +/* TODO: */ + +#define PWM_DEADTIME (50) +#define PWM_DEADTIME_NS (320) + +/* Board parameters: + * Current shunt resistance = 0.0005 + * Current sense gain = (10/20/40/80) + * Vbus min = 12V + * Vbus max = 24V or 56V + * Iout max = 40A (no cooling for + * MOSFETs) + * IPHASE_RATIO = 1/(R_shunt*gain) + * ADC_REF_VOLTAGE = 3.3 + * ADC_VAL_MAX = 4095 + * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX + * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = 0.02014 (gain=80) + * VBUS_RATIO = 1/VBUS_gain = 11 or 19 + */ + +#define ADC_VOLT_REF 3300000 /* micro volt */ +#define ADC_VAL_MAX 4095 +#define R_SHUNT 500 /* micro ohm */ + +/* Center-aligned PWM duty cycle limits */ + +#define MAX_DUTY_B16 ftob16(0.95f) + +/* ADC configuration */ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_3 +#define VBUS_SAMPLE_TIME ADC_SMPR_15 +#define TEMP_SAMPLE_TIME ADC_SMPR_15 + +#define ODRIVE_ADC_AUX (1) +#define ODRIVE_ADC_FOC0 (2) +#define ODRIVE_ADC_FOC1 (3) + +#ifdef CONFIG_ODRIVE_FOC_VBUS +# define ODRIVE_FOC_VBUS 1 +#else +# define ODRIVE_FOC_VBUS 0 +#endif +#ifdef CONFIG_ODRIVE_FOC_TEMP +# define ODRIVE_FOC_TEMP 3 +#else +# define ODRIVE_FOC_TEMP 0 +#endif + +#ifdef CONFIG_ADC +# define ODRIVE_ADC_AUX_DEVPATH "/dev/adc0" +# define ODRIVE_ADC_AUX_NCHAN (ODRIVE_FOC_VBUS + ODRIVE_FOC_TEMP) +#endif + +#define ADC1_INJECTED (0) +#define ADC1_REGULAR (0) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +#define ADC2_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) +#define ADC2_REGULAR (0) +#define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) + +#define ADC3_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) +#define ADC3_REGULAR (0) +#define ADC3_NCHANNELS (ADC3_INJECTED + ADC3_REGULAR) + +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +#endif + +#if ADC2_INJECTED != CONFIG_STM32_ADC2_INJECTED_CHAN +# error +#endif + +#if ADC3_INJECTED != CONFIG_STM32_ADC3_INJECTED_CHAN +# error +#endif + +/* DRV8301 configuration */ + +#ifndef CONFIG_STM32_SPI3 +# error +#endif + +#define DRV8301_0_SPI (3) +#define DRV8301_1_SPI (3) + +#define DRV8301_FREQUENCY (500000) + +/* Qenco configuration */ + +#ifdef CONFIG_SENSORS_QENCODER +# ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS +# error Invalid configuration +# endif +# ifndef CONFIG_STM32_QENCODER_INDEX_PIN +# error Invalid configuration +# endif +# ifdef CONFIG_STM32_TIM3_QE +# if CONFIG_STM32_TIM3_QEPSC != 0 +# error Invalid TIM3 QEPSC value +# endif +# endif +# ifdef CONFIG_STM32_TIM4_QE +# if CONFIG_STM32_TIM4_QEPSC != 0 +# error Invalid TIM4 QEPSC value +# endif +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev); +static int board_foc_shutdown(struct foc_dev_s *dev); +static int board_foc_calibration(struct foc_dev_s *dev, bool state); +static int board_foc_fault_clear(struct foc_dev_s *dev); +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); +static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, + foc_current_t *curr); +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info); +static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, + unsigned long arg); +#ifdef CONFIG_MOTOR_FOC_TRACE +static int board_foc_trace_init(struct foc_dev_s *dev); +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); +#endif + +static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, + xcpt_t isr, void *arg); +static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, + bool enable); +static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev); + +static int stm32_focdev_setup(int devno, int spino, + struct stm32_foc_board_s *board); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Board specific ops */ + +static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = +{ + .setup = board_foc_setup, + .shutdown = board_foc_shutdown, + .calibration = board_foc_calibration, + .fault_clear = board_foc_fault_clear, + .pwm_start = board_foc_pwm_start, + .current_get = board_foc_current_get, + .info_get = board_foc_info_get, + .ioctl = board_foc_ioctl, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace_init = board_foc_trace_init, + .trace = board_foc_trace +#endif +}; + +/* Board specific ADC configuration + * + * AUX (only VBUS used): + * VBUS - ADC1 - ADC1_IN6 (PA6) + * M0_TEMP - ADC1 - ADC1_IN15 (PC5) + * M1_TEMP - ADC1 - ADC1_IN4 (PA4) + * AUX_TEMP - ADC1 - ADC1_IN5 (PA5) + * + * FOC device 0: + * Phase 1 - ADC2 - ADC2_IN10 (PC0) + * Phase 2 - ADC2 - ADC2_IN11 (PC1) + * + * FOC device 1: + * Phase 1 - ADC3 - ADC3_IN13 (PC3) + * Phase 2 - ADC3 - ADC3_IN12 (PC2) + * + */ + +#ifdef CONFIG_ADC + +/* AUX ADC configuration */ + +static uint8_t g_adc_aux_chan[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + 6, +#endif +#ifdef ODRIVE_ADC_TEMP + 15, + 4, + 5 +#endif +}; + +static uint32_t g_adc_aux_pins[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + GPIO_ADC1_IN6, +#endif +#ifdef ODRIVE_ADC_TEMP + GPIO_ADC1_IN15, + GPIO_ADC1_IN4, + GPIO_ADC1_IN5 +#endif +}; + +static adc_channel_t g_adc_aux_stime[] = +{ +#ifdef CONFIG_ODRIVE_FOC_VBUS + { + .channel = 6, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef ODRIVE_ADC_TEMP + { + .channel = 15, + .sample_time = TEMP_SAMPLE_TIME + }, + { + .channel = 4, + .sample_time = TEMP_SAMPLE_TIME + }, + { + .channel = 5, + .sample_time = TEMP_SAMPLE_TIME + } +#endif +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +/* Board specific ADC configuration for FOC device 0 */ + +static uint8_t g_adc_foc0_chan[] = +{ + 10, + 11 +}; + +static uint32_t g_adc_foc0_pins[] = +{ + GPIO_ADC2_IN10, + GPIO_ADC2_IN11, +}; + +static adc_channel_t g_adc_foc0_stime[] = +{ + { + .channel = 10, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 11, + .sample_time = CURRENT_SAMPLE_TIME + } +}; + +static struct stm32_foc_adc_s g_adc_foc0_cfg = +{ + .chan = g_adc_foc0_chan, + .pins = g_adc_foc0_pins, + .stime = g_adc_foc0_stime, + .nchan = ADC2_NCHANNELS, + .regch = ADC2_REGULAR, + .intf = ODRIVE_ADC_FOC0 +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +/* Board specific ADC configuration for FOC device 1 */ + +static uint8_t g_adc_foc1_chan[] = +{ + 13, + 12 +}; + +static uint32_t g_adc_foc1_pins[] = +{ + GPIO_ADC3_IN13, + GPIO_ADC3_IN12, +}; + +static adc_channel_t g_adc_foc1_stime[] = +{ + { + .channel = 13, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 12, + .sample_time = CURRENT_SAMPLE_TIME + } +}; + +static struct stm32_foc_adc_s g_adc_foc1_cfg = +{ + .chan = g_adc_foc1_chan, + .pins = g_adc_foc1_pins, + .stime = g_adc_foc1_stime, + .nchan = ADC3_NCHANNELS, + .regch = ADC3_REGULAR, + .intf = ODRIVE_ADC_FOC1 +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC0 +/* Board specific data - FOC 0 */ + +static struct stm32_foc_board_data_s g_stm32_foc0_board_data = +{ + .adc_cfg = &g_adc_foc0_cfg, + .pwm_dt = (PWM_DEADTIME), +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc0_board = +{ + .data = &g_stm32_foc0_board_data, + .ops = &g_stm32_foc_board_ops, +}; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 +/* Board specific data - FOC 1 */ + +static struct stm32_foc_board_data_s g_stm32_foc1_board_data = +{ + .adc_cfg = &g_adc_foc1_cfg, + .pwm_dt = (PWM_DEADTIME), +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc1_board = +{ + .data = &g_stm32_foc1_board_data, + .ops = &g_stm32_foc_board_ops, +}; +#endif + +/* DRV8301 board ops */ + +static struct drv8301_ops_s g_drv8301_board_ops = +{ + .fault_attach = stm32_foc_drv8301_fault_attach, + .gate_enable = stm32_foc_drv8301_gate_enable, + .fault_handle = stm32_foc_drv8301_fault_handle +}; + +/* Global data */ + +static mutex_t g_common_lock = NXMUTEX_INITIALIZER; +static bool g_fault_attached = false; +static bool g_gate_enabled = false; + +static struct foc_dev_s *g_foc_dev[2] = +{ + NULL, + NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_foc_setup + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->setup(dev->pwr); +} + +/**************************************************************************** + * Name: board_foc_shutdown + ****************************************************************************/ + +static int board_foc_shutdown(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->shutdown(dev->pwr); +} + +/**************************************************************************** + * Name: board_foc_calibration + ****************************************************************************/ + +static int board_foc_calibration(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->calibration(dev->pwr, state); +} + +/**************************************************************************** + * Name: board_foc_fault_clear + ****************************************************************************/ + +static int board_foc_fault_clear(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* TODO: clear DRV8301 faults */ + + return OK; +} + +/**************************************************************************** + * Name: board_foc_pwm_start + ****************************************************************************/ + +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_current_get + ****************************************************************************/ + +static int board_foc_current_get(struct foc_dev_s *dev, int16_t *curr_raw, + foc_current_t *curr) +{ + DEBUGASSERT(dev); + DEBUGASSERT(curr_raw); + DEBUGASSERT(curr); + + /* Get currents */ + + curr[1] = curr_raw[0]; + curr[2] = curr_raw[1]; + + /* From Kirchhoff's current law: ia = -(ib + ic) */ + + curr[0] = -(curr[1] + curr[2]); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_info_get + ****************************************************************************/ + +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info) +{ + struct foc_get_boardcfg_s cfg; + + DEBUGASSERT(dev); + DEBUGASSERT(info); + + UNUSED(dev); + + /* PWM */ + + info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; + info->hw_cfg.pwm_max = MAX_DUTY_B16; + + /* Get power stage configuration */ + + board_foc_ioctl(dev, MTRIOC_GET_BOARDCFG, (unsigned long)&cfg); + + /* ADC Current */ + + info->hw_cfg.iphase_max = 40000; + + info->hw_cfg.iphase_scale = ((100000ul * (ADC_VOLT_REF / ADC_VAL_MAX)) / + (cfg.gain * R_SHUNT)); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_ioctl + ****************************************************************************/ + +static int board_foc_ioctl(struct foc_dev_s *dev, int cmd, unsigned long arg) +{ + DEBUGASSERT(dev); + DEBUGASSERT(dev->pwr); + + return dev->pwr->ops->ioctl(dev->pwr, cmd, arg); +} + +#ifdef CONFIG_MOTOR_FOC_TRACE +/**************************************************************************** + * Name: board_foc_trace_init + ****************************************************************************/ + +static int board_foc_trace_init(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* Not supported */ + + return -1; +} + +/**************************************************************************** + * Name: board_foc_trace + ****************************************************************************/ + +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); +} +#endif + +/**************************************************************************** + * Name: stm32_foc_drv8301_fault_attach + ****************************************************************************/ + +static int stm32_foc_drv8301_fault_attach(struct focpwr_dev_s *dev, + xcpt_t isr, void *arg) +{ + int ret = OK; + + nxmutex_lock(&g_common_lock); + + /* nFAULT is common for both FOC instances */ + + if (g_fault_attached != (bool) isr) + { + ret = stm32_gpiosetevent(GPIO_DRV8301_NFAULT, false, true, false, + isr, arg); + + g_fault_attached = (bool) isr; + } + + nxmutex_unlock(&g_common_lock); + + return ret; +} + +/**************************************************************************** + * Name: stm32_foc_drv8301_gate_enable + ****************************************************************************/ + +static int stm32_foc_drv8301_gate_enable(struct focpwr_dev_s *dev, + bool enable) +{ + /* ENGATE is common for both FOC instances */ + + nxmutex_lock(&g_common_lock); + + if (enable != g_gate_enabled) + { + stm32_gpiowrite(GPIO_DRV8301_ENGATE, enable); + + g_gate_enabled = enable; + } + + nxmutex_unlock(&g_common_lock); + + return OK; +} + +/**************************************************************************** + * Name: stm32_foc_drv8301_fault_handle + ****************************************************************************/ + +static void stm32_foc_drv8301_fault_handle(struct focpwr_dev_s *dev) +{ + UNUSED(dev); + + /* Set fault state for both instances */ + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + g_foc_dev[0]->state.fault |= FOC_FAULT_BOARD; +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + g_foc_dev[1]->state.fault |= FOC_FAULT_BOARD; +#endif + + /* Disable gates for both instances */ + + stm32_gpiowrite(GPIO_DRV8301_ENGATE, false); +} + +/**************************************************************************** + * Name: stm32_focdev_setup + ****************************************************************************/ + +static int stm32_focdev_setup(int devno, int spino, + struct stm32_foc_board_s *board) +{ + struct drv8301_cfg_s drv8301_cfg; + struct drv8301_board_s drv8301_board; + struct spi_dev_s *spi = NULL; + struct foc_dev_s *foc = NULL; + int ret = OK; + char devpath[20]; + + /* Initialize arch specific FOC 0 lower-half */ + + foc = stm32_foc_initialize(devno, board); + if (foc == NULL) + { + ret = -errno; + mtrerr("Failed to initialize STM32 FOC: %d\n", ret); + goto errout; + } + + DEBUGASSERT(foc->lower); + + /* Get devpath */ + + snprintf(devpath, sizeof(devpath), "/dev/foc%d", devno); + + /* Get SPI device */ + + spi = stm32_spibus_initialize(spino); + if (spi == NULL) + { + ret = -errno; + goto errout; + } + + /* DRV8301 configuration */ + + drv8301_cfg.freq = DRV8301_FREQUENCY; + drv8301_cfg.gate_curr = DRV8301_GATECURR_1p7; + drv8301_cfg.gain = DRV8301_GAIN_80; + drv8301_cfg.pwm_mode = DRV8301_PWM_6IN; + drv8301_cfg.oc_adj = DRV8301_OCADJ_DEFAULT; + + /* DRV8301 board data */ + + drv8301_board.spi = spi; + drv8301_board.ops = &g_drv8301_board_ops; + drv8301_board.cfg = &drv8301_cfg; + drv8301_board.devno = devno; + + /* Register DRV8301 device */ + + ret = drv8301_register(devpath, foc, &drv8301_board); + if (ret < 0) + { + mtrerr("Failed to register drv8301 device: %d\n", ret); + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Setup FOC devices + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + int ret = OK; + + /* Configure common EN_GATE */ + + stm32_configgpio(GPIO_DRV8301_ENGATE); + +#ifdef CONFIG_ODRIVE_FOC_FOC0 + ret = stm32_focdev_setup(0, DRV8301_0_SPI, &g_stm32_foc0_board); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_focdev_setup 0 failed: %d\n", ret); + goto errout; + } +#endif + +#ifdef CONFIG_ODRIVE_FOC_FOC1 + ret = stm32_focdev_setup(1, DRV8301_1_SPI, &g_stm32_foc1_board); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_focdev_setup 1 failed: %d\n", ret); + goto errout; + } +#endif + +errout: + return ret; +} + +#ifdef CONFIG_ADC +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc = NULL; + struct stm32_adc_dev_s *stm32_adc = NULL; + struct adc_sample_time_s stime; + int i = 0; + int ret = OK; + + /* Configure pins */ + + for (i = 0; i < ODRIVE_ADC_AUX_NCHAN; i += 1) + { + stm32_configgpio(g_adc_aux_pins[i]); + } + + /* Initialize ADC */ + + adc = stm32_adcinitialize(ODRIVE_ADC_AUX, g_adc_aux_chan, + ODRIVE_ADC_AUX_NCHAN); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface %d\n", ODRIVE_ADC_AUX); + ret = -ENODEV; + goto errout; + } + + /* Register ADC */ + + ret = adc_register(ODRIVE_ADC_AUX_DEVPATH, adc); + if (ret < 0) + { + aerr("ERROR: adc_register %s failed: %d\n", + ODRIVE_ADC_AUX_DEVPATH, ret); + goto errout; + } + + /* Get lower-half ADC */ + + stm32_adc = (struct stm32_adc_dev_s *)adc->ad_priv; + DEBUGASSERT(stm32_adc); + + /* Configure ADC sample time */ + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ODRIVE_ADC_AUX_NCHAN; + stime.channel = g_adc_aux_stime; + + STM32_ADC_SAMPLETIME_SET(stm32_adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(stm32_adc); + + ret = OK; + +errout: + return ret; +} +#endif diff --git a/boards/arm/stm32f4/odrive36/src/stm32_spi.c b/boards/arm/stm32f4/odrive36/src/stm32_spi.c new file mode 100644 index 0000000000000..1e462af7a338b --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_spi.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "odrive.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f4discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_MOTOR_FOC +# ifdef CONFIG_ODRIVE_FOC_FOC0 + stm32_configgpio(GPIO_GATEDRV0_CS); +# endif +# ifdef CONFIG_ODRIVE_FOC_FOC1 + stm32_configgpio(GPIO_GATEDRV1_CS); +# endif +#endif /* CONFIG_MOTOR_FOC */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_MOTOR_FOC +# ifdef CONFIG_ODRIVE_FOC_FOC0 + if (devid == SPIDEV_MOTOR(0)) + { + stm32_gpiowrite(GPIO_GATEDRV0_CS, !selected); + } +# endif + +# ifdef CONFIG_ODRIVE_FOC_FOC1 + if (devid == SPIDEV_MOTOR(1)) + { + stm32_gpiowrite(GPIO_GATEDRV1_CS, !selected); + } +# endif +#endif /* CONFIG_MOTOR_FOC */ +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/odrive36/src/stm32_usb.c b/boards/arm/stm32f4/odrive36/src/stm32_usb.c new file mode 100644 index 0000000000000..d3f53924d0c3e --- /dev/null +++ b/boards/arm/stm32f4/odrive36/src/stm32_usb.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/odrive36/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "odrive.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt new file mode 100644 index 0000000000000..389002b8fac05 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-e407/Kconfig b/boards/arm/stm32f4/olimex-stm32-e407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-e407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-e407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig new file mode 100644 index 0000000000000..0234ae05eba53 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BMP180=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP180=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig new file mode 100644 index 0000000000000..7c870afe0d1f1 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DAC=y +CONFIG_EXAMPLES_DAC=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1CH1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig new file mode 100644 index 0000000000000..67d4415b193ee --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_DISCOVER=y +CONFIG_EXAMPLES_DISCOVER_DHCPC=y +CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_DISCOVER_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="discover_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig new file mode 100644 index 0000000000000..c945c4e776bc8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_INA219=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_INA219=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig new file mode 100644 index 0000000000000..44eab998857a8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -0,0 +1,104 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_NET_ERROR=y +CONFIG_DEBUG_NET_INFO=y +CONFIG_DEBUG_NET_WARN=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_INFO=y +CONFIG_DEBUG_WIRELESS_WARN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=32 +CONFIG_IOB_NCHAINS=16 +CONFIG_LINE_MAX=64 +CONFIG_MAC802154_NTXDESC=32 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_6LOWPAN_COMPRESSION_THRESHOLD=500 +CONFIG_NET_6LOWPAN_EXTENDEDADDR=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_AUTOCONF=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_ROUTER=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_PROMISCUOUS=y +CONFIG_NET_ROUTE=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig new file mode 100644 index 0000000000000..1f65505de8fef --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_INFO=y +CONFIG_DEBUG_WIRELESS_WARN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig new file mode 100644 index 0000000000000..40f0c41a88e7d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a80101 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig new file mode 100644 index 0000000000000..0dd7bf92b27cb --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig new file mode 100644 index 0000000000000..bd9d1caa9a893 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xc0a80101 +CONFIG_EXAMPLES_TELNETD_IPADDR=0xc0a80185 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_LIBRARY=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_READLINE=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig new file mode 100644 index 0000000000000..578b077e1bad4 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..9cfbc79057571 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig new file mode 100644 index 0000000000000..05748b1f5ee17 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-e407" +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_EXAMPLES_WEBSERVER_DRIPADDR=0xc0a80101 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="webserver_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-e407/include/board.h b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h new file mode 100644 index 0000000000000..a12b129b4ddcc --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h @@ -0,0 +1,280 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Olimex-STM32-E407 board features a 12MHz crystal and + * a 32kHz RTC backup crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output + * voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for : Enabled + * USB OTG FS, + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 12MHz + * LSE - 32.768 kHz + * STM32F407ZGT6 - too 168Mhz + */ + +#define STM32_BOARD_XTAL 12000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + * + * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 + * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-E405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-E405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART1 */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ + +/* USART2 */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_2|GPIO_SPEED_100MHz) /* PD6 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_2|GPIO_SPEED_100MHz) /* PD5 */ + +/* USART3 */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ + +/* CAN */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* I2C */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) /* PB6 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) /* PB7 */ + +/* SPI1 */ + +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ + +/* Ethernet *****************************************************************/ + +#if defined(CONFIG_STM32_ETHMAC) +/* RMII interface to the LAN8710 PHY (works with LAN8720 driver) */ + +# ifndef CONFIG_STM32_RMII +# error CONFIG_STM32_RMII must be defined +# endif + +/* Clocking is provided by an external 50Mhz XTAL */ + +# ifndef CONFIG_STM32_RMII_EXTCLK +# error CONFIG_STM32_RMII_EXTCLK must be defined +# endif + +/* Pin disambiguation */ + +# define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) /* PA3 */ +# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) /* PG13 */ +# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) /* PG14 */ +# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ + +#endif + +/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs new file mode 100644 index 0000000000000..884d70b69442b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZE),y) +LDSCRIPT = f407ze.ld +else ifeq ($(CONFIG_ARCH_CHIP_STM32F407ZG),y) +LDSCRIPT = f407zg.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld index 654c8e73ab517..283be36be0f54 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld index 3760d7df2012c..f0bd2b2277403 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt new file mode 100644 index 0000000000000..c3ee8a36e6686 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt @@ -0,0 +1,77 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_CAN) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS stm32_mrf24j40.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32F407ZE) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407ze.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f407zg.ld") +endif() diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs new file mode 100644 index 0000000000000..84b3dce9a7828 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs @@ -0,0 +1,75 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_DAC),y) +CSRCS += stm32_dac.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += stm32_mrf24j40.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h rename to boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h index 7d1d5064417ca..ee640dbc99df9 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h + * boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include "stm32.h" diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c new file mode 100644 index 0000000000000..7796617d96b7a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, + * GPIO_ADC1_IN4, GPIO_ADC1_IN5, GPIO_ADC1_IN6, + * GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, + * GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + adbg("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..d58f96ed9e944 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c new file mode 100644 index 0000000000000..b9bc201270e0e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_ccm.h" +#include "stm32.h" +#include "stm32_i2c.h" + +#include "olimex-stm32-e407.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c new file mode 100644 index 0000000000000..6dab2b6595451 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-e407.h" + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_SENSORS_INA219 +#include "stm32_ina219.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +/* #define HAVE_I2CTOOL 1 */ + +/* Can't support USB host or device features if USB OTG HS is not enabled */ + +#ifndef CONFIG_STM32_OTGHS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# undef CONFIG_CAN +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef CONFIG_CAN + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_DAC + /* Initialize DAC and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to start ADC1: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_INA219 + /* Configure and initialize the INA219 sensor */ + + ret = board_ina219_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_ina219initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_TIMER) + /* Initialize the timer, at this moment it's only Timer 1,2,3 */ + + #if defined(CONFIG_STM32_TIM1) + stm32_timer_driver_setup("/dev/timer1", 1); + #endif + #if defined(CONFIG_STM32_TIM2) + stm32_timer_driver_setup("/dev/timer2", 2); + #endif + #if defined(CONFIG_STM32_TIM3) + stm32_timer_driver_setup("/dev/timer3", 3); + #endif +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + /* Configure MRF24J40 wireless */ + + ret = stm32_mrf24j40_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mrf24j40_initialize() failed:" + " %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c new file mode 100644 index 0000000000000..09c257fd4079e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is + * indexed by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c new file mode 100644 index 0000000000000..2550c1b3f140b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + candbg("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + candbg("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c new file mode 100644 index 0000000000000..f553f6d94b4ef --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2019 Acutronics Robotics All rights reserved. + * SPDX-FileContributor: Juan Flores + * SPDX-FileContributor: Juha Niskanen + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "olimex-stm32-e407.h" + +#include + +#if defined(CONFIG_DAC) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct dac_dev_s *g_dac; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC0 of the microcontroller. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + static bool initialized = false; + + if (!initialized) + { + int ret; + + g_dac = stm32_dacinitialize(1); + if (g_dac == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + + return OK; +} + +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c new file mode 100644 index 0000000000000..3baadf6977c6a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_IEEE802154_MRF24J40 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_priv_s +{ + struct mrf24j40_lower_s dev; + xcpt_t handler; + void *arg; + uint32_t intcfg; + uint8_t spidev; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MRF24J40 driver from differences in GPIO interrupt handling + * varying boards and MCUs. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg); +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state); +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MRF24J40 + * driver. This structure provides information about the configuration + * of the MRF24J40 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct stm32_priv_s g_mrf24j40_mb1_priv = +{ + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MRF24J40_INT, + .spidev = 1, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the MRF24J40 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. If possible, + * interrupts should be configured on both rising and falling edges + * so that contact and loss-of-contact events can be detected. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int stm32_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + DEBUGASSERT(priv != NULL); + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void stm32_enable_irq(const struct mrf24j40_lower_s *lower, + bool state) +{ + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); + + wlinfo("state:%d\n", (int)state); + + /* Attach and enable, or detach and disable */ + + if (state) + { + stm32_gpiosetevent(priv->intcfg, false, true, true, + priv->handler, priv->arg); + } + else + { + stm32_gpiosetevent(priv->intcfg, false, false, false, + NULL, NULL); + } +} + +/**************************************************************************** + * Name: stm32_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static int stm32_mrf24j40_devsetup(struct stm32_priv_s *priv) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + struct spi_dev_s *spi; + int ret; + + /* Configure the interrupt pin */ + + stm32_configgpio(priv->intcfg); + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = stm32_spibus_initialize(priv->spidev); + if (spi == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Initialize and register the SPI MRF24J40 device */ + + radio = mrf24j40_init(spi, &priv->dev); + if (radio == NULL) + { + wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC interface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("ERROR: " + "Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_mrf24j40_initialize(void) +{ + int ret; + + wlinfo("Configuring MRF24J40\n"); + + ret = stm32_mrf24j40_devsetup(&g_mrf24j40_mb1_priv); + if (ret < 0) + { + wlerr("ERROR: Failed to initialize BD in mikroBUS1: %d\n", ret); + } + + UNUSED(ret); + return OK; +} +#endif /* CONFIG_IEEE802154_MRF24J40 */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c new file mode 100644 index 0000000000000..c188a6abe7e3d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c @@ -0,0 +1,303 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Olimex-STM32-E407 + * board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_CAN_MCP2515 + stm32_configgpio(GPIO_MCP2515_CS); /* MCP2515 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_LCD_ST7567 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_LCD_PCD8544 + stm32_configgpio(STM32_LCD_CS); /* ST7567 chip select */ +#endif + +#ifdef CONFIG_WL_NRF24L01 + stm32_configgpio(GPIO_NRF24L01_CS); /* nRF24L01 chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + stm32_configgpio(GPIO_MRF24J40_CS); /* MRF24J40 chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#if defined(CONFIG_CAN_MCP2515) + if (devid == SPIDEV_CANBUS(0)) + { + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif + +#ifdef CONFIG_IEEE802154_MRF24J40 + if (devid == SPIDEV_IEEE802154(0)) + { + stm32_gpiowrite(GPIO_MRF24J40_CS, !selected); + } +#endif + +#if defined(CONFIG_IEEE802154_XBEE) + if (devid == SPIDEV_IEEE802154(0)) + { + stm32_gpiowrite(GPIO_XBEE_CS, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_NRF24L01_CS, !selected); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_WL_NRF24L01 + if (devid == SPIDEV_WIRELESS(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ +#ifdef CONFIG_LCD_ST7567 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#ifdef CONFIG_LCD_PCD8544 + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_CD, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c new file mode 100644 index 0000000000000..8d696f1f725d8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c new file mode 100644 index 0000000000000..29725ddce93ce --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c @@ -0,0 +1,329 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor + * for device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uvdbg("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, andi + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c new file mode 100644 index 0000000000000..b45090679214f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt new file mode 100644 index 0000000000000..8f277b475ed80 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/Kconfig b/boards/arm/stm32f4/olimex-stm32-h405/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h405/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h405/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..04484f5b989c8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h405" +CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_CAN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG2=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-h405/include/board.h b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h new file mode 100644 index 0000000000000..139fac64fa5c8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(12) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(360) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) + +#define STM32_SYSCLK_FREQUENCY 120000000ul + +/* AHB clock (HCLK) is SYSCLK (120MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (30MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-H405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-H405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ +#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H405_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs new file mode 100644 index 0000000000000..f9d445c42f7d8 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script new file mode 100644 index 0000000000000..3bf301337f5b9 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F405RGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt new file mode 100644 index 0000000000000..5c6283a1d120b --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs new file mode 100644 index 0000000000000..edf6087d9fd98 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h rename to boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h index 06359cc80bd93..610c2384d5cd5 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h + * boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c new file mode 100644 index 0000000000000..6415a54736bc5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; +/* , 2, 3, + * 4, 5, 6, + * 7, 8, 9, + * 10, 11, 12, + * 13, 15 + * }; + */ + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1_0 +}; +/* , GPIO_ADC1_IN2_0, GPIO_ADC1_IN3_0, + * GPIO_ADC1_IN4_0, GPIO_ADC1_IN5_0, GPIO_ADC1_IN6_0, + * GPIO_ADC1_IN7_0, GPIO_ADC1_IN8_0, GPIO_ADC1_IN9_0, + * GPIO_ADC1_IN10_0, GPIO_ADC1_IN11_0, GPIO_ADC1_IN12_0, + * GPIO_ADC1_IN13_0, GPIO_ADC1_IN15_0 + * }; + */ +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c new file mode 100644 index 0000000000000..2c131bdac98c6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c new file mode 100644 index 0000000000000..c030d22076a64 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-h405.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# undef CONFIG_CAN +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV is also + * selected. + */ + +#ifdef CONFIG_STM32_OTGFS + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c new file mode 100644 index 0000000000000..8f180773eb7a6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c new file mode 100644 index 0000000000000..44529b9f1ef12 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c new file mode 100644 index 0000000000000..c64185910443d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-h405.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c new file mode 100644 index 0000000000000..1662368f1a3c7 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-h405.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt new file mode 100644 index 0000000000000..8bbac202e6fdf --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/Kconfig b/boards/arm/stm32f4/olimex-stm32-h407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig new file mode 100644 index 0000000000000..d1ceb8ccdc762 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h407" +CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig new file mode 100644 index 0000000000000..1c67edfa136a3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_EXCHANGE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-h407" +CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-h407/include/board.h b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h new file mode 100644 index 0000000000000..231db8e186534 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h @@ -0,0 +1,287 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Olimex-STM32-H407 board features a 12MHz crystal and + * a 32kHz RTC backup crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output + * voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, + * SDIO and RNG clock : Enabled + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 12MHz + * LSE - 32.768 kHz + * STM32F407ZGT6 - too 168Mhz + */ + +#define STM32_BOARD_XTAL 12000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + * + * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 + * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status + * LED in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED_STATUS) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of + * the Olimex STM32-H405. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-H405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#if 0 +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14 */ +#endif + +/* USART2: */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) +#define GPIO_USART2_CTS GPIO_USART2_CTS_1 +#define GPIO_USART2_RTS GPIO_USART2_RTS_1 + +/* USART6: (UEXT connector) */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) + +/* GPIO_USART6_CTS and GPIO_USART6_RTS aren't used for UEXT */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ +#define GPIO_CAN2_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_CAN2_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB6 */ + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_H407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs new file mode 100644 index 0000000000000..e158e90e0f33c --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script new file mode 100644 index 0000000000000..5fc191cd18ccf --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407ZGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt new file mode 100644 index 0000000000000..51a4ddbada411 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt @@ -0,0 +1,65 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs new file mode 100644 index 0000000000000..7fd882bf3aa8d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h rename to boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h index 5fe28b34fab4a..bb73d19691f6f 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h + * boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c new file mode 100644 index 0000000000000..1e6c8c43807df --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 1 +}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, + * GPIO_ADC1_IN5, GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, + * GPIO_ADC1_IN9, GPIO_ADC1_IN10, GPIO_ADC1_IN11, GPIO_ADC1_IN12, + * GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN1 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..6c9fa1b273fba --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c new file mode 100644 index 0000000000000..63eb2232eb3e5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "olimex-stm32-h407.h" +#include "stm32_ccm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. + * Presumably either CONFIG_USBDEV is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c new file mode 100644 index 0000000000000..83932835b4b7a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-h407.h" + +/* Conditional logic in olimex-stm32-h407.h will determine if certain + * features are supported. + * Tests for these features need to be made after including + * olimex-stm32-h407.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret; + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize MMC/SD driver: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. + * stm32_usbhost_initialize() starts a thread will monitor for USB + * connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to start USB monitor: %d\n", + ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c new file mode 100644 index 0000000000000..2c8c1b3b4904a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c new file mode 100644 index 0000000000000..3953ecafb566a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c new file mode 100644 index 0000000000000..e8c8fda4baad7 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c new file mode 100644 index 0000000000000..fefb1776b45ff --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c @@ -0,0 +1,311 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32_otghs.h" +#include "olimex-stm32-h407.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F407_USBHOST_PRIO +# define CONFIG_STM32F407_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F407_USBHOST_STACKSIZE +# define CONFIG_STM32F407_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_VBUS); + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32H407_USBHOST_PRIO, + CONFIG_STM32H407_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c new file mode 100644 index 0000000000000..807ad57522dc5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "olimex-stm32-h407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt new file mode 100644 index 0000000000000..03081b159c48f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/Kconfig b/boards/arm/stm32f4/olimex-stm32-p407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-p407/Kconfig diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig new file mode 100644 index 0000000000000..c4aa5630fee81 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_CS4344=y +CONFIG_AUDIO_EXCLUDE_TONE=y +CONFIG_AUDIO_EXCLUDE_VOLUME=y +CONFIG_AUDIO_I2S=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S3=y +CONFIG_STM32_I2S3_TX=y +CONFIG_STM32_I2S_MCK=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_DMA=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig new file mode 100644 index 0000000000000..c2568a49d5a41 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_DHTXX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_DHTXX=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FREERUN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig new file mode 100644 index 0000000000000..1474e1bd56540 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_HIDKBD=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs new file mode 100644 index 0000000000000..9c06da91d4e6e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig new file mode 100644 index 0000000000000..15ba73092b067 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_ELF_STACKSIZE=4096 +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_ELF_DEVPATH="/dev/sda" +CONFIG_EXAMPLES_ELF_FSREMOVEABLE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="elf_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PATH_INITIAL="/mnt/vfat" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=4 +CONFIG_START_MONTH=8 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs new file mode 100644 index 0000000000000..22979d8184d48 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig new file mode 100644 index 0000000000000..1026bb269dd02 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/sda" +CONFIG_EXAMPLES_MODULE_FSREMOVEABLE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="module_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_MODULE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=8 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs new file mode 100644 index 0000000000000..f9a6444eca014 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT1 = memory.ld +LDSCRIPT2 = kernel-space.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig new file mode 100644 index 0000000000000..40beb1054dc67 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig new file mode 100644 index 0000000000000..a9a50a224efb3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LINE_MAX=64 +CONFIG_MODULE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=393216 +CONFIG_RAM_START=0x20400000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_MONTH=6 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig new file mode 100644 index 0000000000000..6dc5ccbb18bb5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig @@ -0,0 +1,83 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STM32_AUTONEG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_KS8721=y +CONFIG_EXAMPLES_MQTTC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HTS221_DEBUG=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0xc0a80101 +CONFIG_NETINIT_DRIPADDR=0xc0a80101 +CONFIG_NETINIT_IPADDR=0xc0a801e1 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_MQTTC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_NOTIFIER=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_HTS221=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_ETH100MBPS=y +CONFIG_STM32_ETHFD=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NETDB=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig new file mode 100644 index 0000000000000..20dfd48105d7f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig new file mode 100644 index 0000000000000..d14e46b5dd711 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="olimex-stm32-p407" +CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_I2S=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_IFLOWCONTROL_LOWER_WATERMARK=25 +CONFIG_SERIAL_IFLOWCONTROL_UPPER_WATERMARK=75 +CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SPI=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=5 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_FLOWCONTROL_BROKEN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USART6=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_SYSTEM_ZMODEM_DEVNAME="/dev/ttyS1" +CONFIG_SYSTEM_ZMODEM_IFLOW=y +CONFIG_SYSTEM_ZMODEM_MOUNTPOINT="/mnt" +CONFIG_SYSTEM_ZMODEM_OFLOW=y +CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 +CONFIG_USART3_BAUD=9600 +CONFIG_USART3_IFLOWCONTROL=y +CONFIG_USART3_OFLOWCONTROL=y +CONFIG_USART3_RXBUFSIZE=512 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/olimex-stm32-p407/include/board.h b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h new file mode 100644 index 0000000000000..e1d157fa0dd95 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h @@ -0,0 +1,453 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN1 BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_GREEN2 BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the Olimex STM32-P407. The following definitions describe how + * NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The Olimex STM32-P407 supports seven buttons: */ + +#define BUTTON_TAMPER 0 +#define BUTTON_WKUP 1 + +#ifdef CONFIG_INPUT_DJOYSTICK +# define NUM_BUTTONS 2 +#else +# define JOYSTICK_RIGHT 2 +# define JOYSTICK_UP 3 +# define JOYSTICK_LEFT 4 +# define JOYSTICK_DOWN 5 +# define JOYSTICK_CENTER 6 + +# define NUM_BUTTONS 7 +#endif + +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_WKUP_BIT (1 << BUTTON_WKUP) + +#ifndef CONFIG_INPUT_DJOYSTICK +# define JOYSTICK_RIGHT_BIT (1 << JOYSTICK_RIGHT) +# define JOYSTICK_UP_BIT (1 << JOYSTICK_UP) +# define JOYSTICK_LEFT_BIT (1 << JOYSTICK_LEFT) +# define JOYSTICK_DOWN_BIT (1 << JOYSTICK_DOWN) +# define JOYSTICK_CENTER_BIT (1 << JOYSTICK_CENTER) +#endif + +/* Alternate function pin selections ****************************************/ + +/* USART3: */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) /* PD8 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */ + +/* UEXT USART3: This will redefine the above macros if enabled. */ + +#ifdef CONFIG_STM32_OLIMEXP407_UEXT_USART3 +# undef GPIO_USART3_RX (GPIO_USART3_RX_3|GPIO_SPEED_100MHz) +# undef GPIO_USART3_TX (GPIO_USART3_TX_3|GPIO_SPEED_100MHz) +# undef GPIO_USART3_CTS GPIO_USART3_CTS_2 +# undef GPIO_USART3_RTS GPIO_USART3_RTS_2 + +# define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) /* PC11 */ +# define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) /* PC10 */ +#endif + +/* USART6: */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_2|GPIO_SPEED_100MHz) /* PG9 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* microSD Connector: + * + * ----------------- ----------------- ------------------------ + * SD/MMC CONNECTOR BOARD GPIO CONFIGURATION(s + * PIN SIGNAL SIGNAL (no remapping) + * --- ------------- ----------------- ------------------------- + * 1 DAT2/RES SD_D2/USART3_TX/ PC10 GPIO_SDIO_D2 + * SPI3_SCK + * 2 CD/DAT3/CS SD_D3/USART3_RX/ PC11 GPIO_SDIO_D3 + * SPI3_MISO + * 3 CMD/DI SD_CMD PD2 GPIO_SDIO_CMD + * 4 VDD N/A N/A + * 5 CLK/SCLK SD_CLK/SPI3_MOSI PC12 GPIO_SDIO_CK + * 6 VSS N/A N/A + * 7 DAT0/D0 SD_D0/DCMI_D2 PC8 GPIO_SDIO_D0 + * 8 DAT1/RES SD_D1/DCMI_D3 PC9 GPIO_SDIO_D1 + * --- ------------- ----------------- ------------------------- + * + * NOTES: + * 1. DAT4, DAT4, DAT6, and DAT7 not connected. + * 2. There are no alternative pin selections. + * 3. There is no card detect (CD) GPIO input so we will not + * sense if there is a card in the SD slot or not. This will + * make usage very awkward. + */ + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT - NC (not connected) + * - PA0 is ETH_MII_CRS - NC + * - PA3 is ETH_MII_COL - NC + * - PB10 is ETH_MII_RX_ER - NC + * - PB0 is ETH_MII_RXD2 - NC + * - PH7 is ETH_MII_RXD3 - NC + * - PC3 is ETH_MII_TX_CLK - NC + * - PC2 is ETH_MII_TXD2 - NC + * - PB8 is ETH_MII_TXD3 - NC + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PB11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* USART6 + * + * DMAMAP_USART6_RX_1 = Channel 5, Stream1 + * DMAMAP_USART6_RX_2 = Channel 5, Stream2 + * DMAMAP_USART6_TX_1 = Channel 5, Stream6 + * DMAMAP_USART6_TX_2 = Channel 5, Stream7 + */ + +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 +#define DMAMAP_USART6_TX DMAMAP_USART6_TX_1 + +/* DHTxx pin configuration */ + +#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9) +#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN) +#define GPIO_DHTXX_PIN_INPUT (GPIO_INPUT|GPIO_FLOAT|GPIO_DHTXX_PIN) + +#define BOARD_DHTXX_GPIO_INPUT GPIO_DHTXX_PIN_INPUT +#define BOARD_DHTXX_GPIO_OUTPUT GPIO_DHTXX_PIN_OUTPUT +#define BOARD_DHTXX_FRTIMER 1 /* Free-run timer 1 */ + +/* SPI3 - As present in the UEXT header */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 + +/* I2S3 - CS4344 configuration uses I2S3 */ + +#define GPIO_I2S3_SD GPIO_I2S3_SD_1 +#define GPIO_I2S3_CK GPIO_I2S3_CK_1 +#define GPIO_I2S3_WS GPIO_I2S3_WS_2 +#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 + +#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 + +/* ETH MII/RMII inputs and MDC/MDIO (referenced by arch driver) */ + +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* FSMC SRAM */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OLIMEX_STM32_P407_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile new file mode 100644 index 0000000000000..e056219e025ae --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..db4079eff62b9 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs new file mode 100644 index 0000000000000..086726dad0f23 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld new file mode 100644 index 0000000000000..577a9d8f2df75 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld new file mode 100644 index 0000000000000..8eab527b056ae --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld new file mode 100644 index 0000000000000..a636ac8e99f0d --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 8Kb of SRAM. (See boards/stm32f4discovery/scripts/kernel-space.ld). + * Allowing additional memory permitis configuring debug instrumentation to + * be added to the kernel space without overflowing the partition. This could + * just as easily be set to 256Kb or even 512Kb. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000 (it cannot be positioned at 0x0800000 because vectors power-up + * reset vectors are places at the beginning of that range). If you change + * this address, don't forget to change the CONFIG_NUTTX_USERSPACE + * configuration setting to match and to modify the check in kernel/userspace.c. + * + * With 112Kb of SRAM a 64Kb user heap would seem possible but it is not in + * the current organization of SRAM memory (that could be changed with a + * little effort). The current ordering of SRAM is: (1) kernel .bss/.data, + * (2) user .bss/.data, (3) kernel heap (determined by CONFIG_MM_KERNEL_HEAPSIZE), + * and (4) the user heap. The maximum size of the user space heap is then + * limited to 32Kb beginning at address 0x20008000. + * + * Both of these alignment limitations could be reduced by using multiple + * regions to map the FLASH/SDRAM range or perhaps with some clever use of + * subregions or with multiple MPU regions per memory region. + * + * NOTE: The MPU is used in a mode where mappings are not required for + * kernel addresses and, hence, there are not alignment issues for those + * case. Only the user address spaces suffer from alignment requirements. + * However, in order to exploit this fact, we would still need to change + * the ordering of memory regions in SRAM. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x2000 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 8KB + * 0x2000 2000: User .data region. Size is variable. + * ------ ---- User .bss region Size is variable. + * 0x2000 4000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. + * 0x2000 8000: Beginning of 32Kb user heap. + * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. + * 0x2001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x2000a000, LENGTH = 80K +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld new file mode 100644 index 0000000000000..97ddb090ed1ac --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt new file mode 100644 index 0000000000000..1ba829e0eeee5 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt @@ -0,0 +1,61 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_sram.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_AUDIO_CS4344) + list(APPEND SRCS stm32_cs4344.c) +endif() + +if(CONFIG_INPUT_DJOYSTICK) + list(APPEND SRCS stm32_djoystick.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs new file mode 100644 index 0000000000000..490a60598470e --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs @@ -0,0 +1,63 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_st7735.c + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) + CSRCS += stm32_sram.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) + CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) + CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) + CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_AUDIO_CS4344),y) + CSRCS += stm32_cs4344.c +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) + CSRCS += stm32_djoystick.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h rename to boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h index 8847489d52044..a158aaf9af686 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h + * boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c new file mode 100644 index 0000000000000..0278cefdd267c --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The Olimex STM32-P407 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN10 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c new file mode 100644 index 0000000000000..8ac94043160c2 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define LED_STARTED_BITS (BOARD_LED1_BIT) +#define LED_HEAPALLOCATE_BITS (BOARD_LED2_BIT) +#define LED_IRQSENABLED_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT) +#define LED_STACKCREATED_BITS (BOARD_LED3_BIT) +#define LED_INIRQ_BITS (BOARD_LED1_BIT | BOARD_LED3_BIT) +#define LED_SIGNAL_BITS (BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_ASSERTION_BITS (BOARD_LED1_BIT | BOARD_LED2_BIT | BOARD_LED3_BIT) +#define LED_PANIC_BITS (BOARD_LED4_BIT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const unsigned int g_ledbits[8] = +{ + LED_STARTED_BITS, + LED_HEAPALLOCATE_BITS, + LED_IRQSENABLED_BITS, + LED_STACKCREATED_BITS, + LED_INIRQ_BITS, + LED_SIGNAL_BITS, + LED_ASSERTION_BITS, + LED_PANIC_BITS +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & BOARD_LED1_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & BOARD_LED2_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & BOARD_LED3_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & BOARD_LED4_BIT) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_clrbits(BOARD_LED1_BIT | BOARD_LED2_BIT | + BOARD_LED3_BIT | BOARD_LED4_BIT); + led_setbits(g_ledbits[led]); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_clrbits(g_ledbits[led]); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c new file mode 100644 index 0000000000000..96f423fd65d3a --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "olimex-stm32-p407.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_stram_configure(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration + * and 2) disabled, and 3) the weak function stm32_usb_configure() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + stm32_usb_configure(); +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + +#ifdef CONFIG_ARCH_BUTTONS + board_button_initialize(); +#endif + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ + defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization here if so configured */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c new file mode 100644 index 0000000000000..23aef9764d545 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_MODULE +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_SENSORS_DHTXX +#include "stm32_dhtxx.h" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef HAVE_MODSYMS +extern const struct symtab_s MODSYMS_SYMTAB_ARRAY[]; +extern const int MODSYMS_NSYMBOLS_VAR; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_MODSYMS + /* Install the module symbol table */ + + libelf_setsymtab(MODSYMS_SYMTAB_ARRAY, MODSYMS_NSYMBOLS_VAR); +#endif + +#ifdef HAVE_MMCSD + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(MMCSD_SLOTNO); + if (!sdio) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SDIO slot %d\n", + MMCSD_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(MMCSD_MINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + return ret; + } + + /* Then let's guess and say that there is a card in the slot. The Olimex + * STM32 P407 does not support a GPIO to detect if there is a card in + * the slot so we are reduced to guessing. + */ + + sdio_mediachange(sdio, true); +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_setup() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_setup(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_DHTXX + ret = board_dhtxx_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dhtxx_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_CS4344 + /* Configure CS4344 audio */ + + ret = stm32_cs4344_initialize(1); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + ret = stm32_djoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c new file mode 100644 index 0000000000000..7e53c997deead --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c @@ -0,0 +1,188 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" + +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_TAMPER, + GPIO_BTN_WKUP, + + /* The Joystick is treated like the other buttons unless + * CONFIG_INPUT_DJOYSTICK is defined, then it is assumed that they should + * be used by the discrete joystick driver. + */ + +#ifndef CONFIG_INPUT_DJOYSTICK + GPIO_JOY_RIGHT, + GPIO_JOY_UP, + GPIO_JOY_LEFT, + GPIO_JOY_DOWN, + GPIO_JOY_CENTER +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_TAMPER])) + { + ret |= BUTTON_TAMPER_BIT; + } + + if (stm32_gpioread(g_buttons[BUTTON_WKUP])) + { + ret |= BUTTON_WKUP_BIT; + } + +#ifndef CONFIG_INPUT_DJOYSTICK + if (stm32_gpioread(g_buttons[JOYSTICK_RIGHT])) + { + ret |= JOYSTICK_RIGHT_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_UP])) + { + ret |= JOYSTICK_UP_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_LEFT])) + { + ret |= JOYSTICK_LEFT_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_DOWN])) + { + ret |= JOYSTICK_DOWN_BIT; + } + + if (stm32_gpioread(g_buttons[JOYSTICK_CENTER])) + { + ret |= JOYSTICK_CENTER_BIT; + } +#endif + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c new file mode 100644 index 0000000000000..abb3d539c7289 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c index fdef20aabf027..caebdff338f3b 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c new file mode 100644 index 0000000000000..191399950d24f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t + djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-P407 joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialize + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c new file mode 100644 index 0000000000000..d7777549c85b6 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "olimex-stm32-p407.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) ||\ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the olimex + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ + stm32_configgpio(GPIO_ST7735_CS); +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a call to stm32_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#ifdef CONFIG_LCD_ST7735 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_ST7735_CS, !selected); + } +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + +#ifdef CONFIG_LCD_ST7735 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_ST7735_AO, !cmd); + return OK; + } +#endif + + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c index d2d7a1c260822..0e3a7159be359 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c index 9e74c73f2780f..3ee27f56b0ac6 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c new file mode 100644 index 0000000000000..63700d43db542 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c @@ -0,0 +1,330 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-p407.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_OLIMEXP407_USBHOST_PRIO +# define CONFIG_OLIMEXP407_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_OLIMEXP407_USBHOST_STACKSIZE +# define CONFIG_OLIMEXP407_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_usb_configure very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_setup + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_setup(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_OLIMEXP407_USBHOST_PRIO, + CONFIG_OLIMEXP407_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c new file mode 100644 index 0000000000000..01b7c08ceade3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "olimex-stm32-p407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/omnibusf4/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt new file mode 100644 index 0000000000000..b1118af49bb66 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/omnibusf4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/Kconfig b/boards/arm/stm32f4/omnibusf4/Kconfig similarity index 100% rename from boards/arm/stm32/omnibusf4/Kconfig rename to boards/arm/stm32f4/omnibusf4/Kconfig diff --git a/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig new file mode 100644 index 0000000000000..848febabe21a9 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig @@ -0,0 +1,124 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="omnibusf4" +CONFIG_ARCH_BOARD_OMNIBUSF4=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_IOCTL=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_URANDOM=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_LEDS_LEDSET=0x1 +CONFIG_EXAMPLES_LEDS_STACKSIZE=512 +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_PRINTHEX=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=24 +CONFIG_IOB_NCHAINS=8 +CONFIG_LIBC_HOSTNAME="omnibusf4" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_M25P_SPIFREQUENCY=75000000 +CONFIG_MMCSD=y +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_MPU60X0_EXTI=y +CONFIG_MTD=y +CONFIG_MTD_M25P=y +CONFIG_MTD_SECT512=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MMCSDSPIPORTNO=2 +CONFIG_NSH_PROMPT_STRING="omnibusf4> " +CONFIG_NSH_READLINE=y +CONFIG_PIPES=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MPU60X0=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CCMDATARAM=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DFU=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_TIM10=y +CONFIG_STM32_TIM12=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH3OUT=y +CONFIG_STM32_TIM2_CH4OUT=y +CONFIG_STM32_TIM2_CHANNEL3=y +CONFIG_STM32_TIM2_CHANNEL4=y +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CH4OUT=y +CONFIG_STM32_TIM3_CHANNEL3=y +CONFIG_STM32_TIM3_CHANNEL4=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM9=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DMA=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y +CONFIG_VIDEO_MAX7456=y +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32f4/omnibusf4/include/board.h b/boards/arm/stm32f4/omnibusf4/include/board.h new file mode 100644 index 0000000000000..3fd9a21b8f2a6 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/include/board.h @@ -0,0 +1,262 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The OMNIBUSF4 board uses a single 8MHz crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* Pin configurations *******************************************************/ + +#define BOARD_NLEDS 2 /* One literal LED, one beeper */ +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5) +#define GPIO_BEEPER1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTB|GPIO_PIN4) + +/* USART1: */ + +#if 0 +#define INVERTER_PIN_USART1 PC0 /* DYS F4 Pro, Omnibus F4 AIO 1st Gen only */ +#endif +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ + +/* USART2: + * + * TODO: Do OMNIBUSF4 targets use USART2? + */ + +/* USART3: */ + +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10 */ +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11 */ + +/* USART4: */ + +/* USART6: */ + +#if 0 +#define INVERTER_PIN_UART6 PC8 /* Omnibus F4 V3 and later, EXUAVF4PRO */ +#endif +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM - motor outputs, etc. are on these pins: */ + +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S1_OUT PB0 */ +#define GPIO_TIM3_CH4OUT (GPIO_TIM3_CH4OUT_1|GPIO_SPEED_50MHz) /* S2_OUT PB1 */ +#define GPIO_TIM2_CH4OUT (GPIO_TIM2_CH4OUT_1|GPIO_SPEED_50MHz) /* S3_OUT PA3 */ +#define GPIO_TIM2_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) /* S4_OUT PA2 */ + +/* SPI1 : + * + * MPU6000 6-axis motion sensor (accelerometer + gyroscope), or + * MPU6500 6-Axis MEMS MotionTracking Device with DMP + * + * MPU6000 interrupts + * #define USE_GYRO_EXTI + * #define GYRO_1_EXTI_PIN PC4 + * #define USE_MPU_DATA_READY_SIGNAL + * + * #define GYRO_1_ALIGN CW270_DEG + * #define ACC_1_ALIGN CW270_DEG + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) /* PA6 */ +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) /* PA7 */ +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) /* PA5 */ +#if 0 +#define GPIO_SPI1_NSS (GPIO_SPI1_NSS_2|GPIO_SPEED_50MHz) /* PA4 */ +#endif +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 /* 2:0:3 */ +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 /* 2:3:3 */ + +/* SPI2 : + * + * Used for MMC/SD on OMNIBUSF4SD. + */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) /* PB14 */ +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) /* PB15 */ +#define GPIO_SPI2_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) /* PB13 */ +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX /* 1:3:0 */ +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX /* 1:4:0 */ + +#define GPIO_MMCSD_NSS GPIO_SPI2_NSS +#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTB | GPIO_PIN7) /* PB7 SD_DET */ + +/* SPI3 : + * + * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 + * (? BF code says "PB3"). + * define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4 + * + * Barometer and/or MAX7456, depending on the target. + * (OMNIBUSF4BASE targets appear to have a cyrf6936 device.) + */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_2|GPIO_SPEED_50MHz) /* PC11 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_2|GPIO_SPEED_50MHz) /* PC12 */ +#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_1|GPIO_SPEED_50MHz) /* PA15 */ /* TODO: doesn't work like a chip select */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_2|GPIO_SPEED_50MHz) /* PC10 */ + +#if 0 +/* I2C : */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#endif + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/omnibusf4/kernel/Makefile b/boards/arm/stm32f4/omnibusf4/kernel/Makefile new file mode 100644 index 0000000000000..9ccee530286fc --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..77bf45552f209 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/omnibusf4/scripts/Make.defs b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs new file mode 100644 index 0000000000000..f5c23b2b86ca9 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld new file mode 100644 index 0000000000000..6c45eaa4e84e0 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/ld.script b/boards/arm/stm32f4/omnibusf4/scripts/ld.script new file mode 100644 index 0000000000000..947c33103d258 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/memory.ld b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld new file mode 100644 index 0000000000000..196d3591fffc7 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld new file mode 100644 index 0000000000000..b50708ae317ee --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt new file mode 100644 index 0000000000000..531c7feb5d6f6 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt @@ -0,0 +1,83 @@ +# ############################################################################## +# boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c) + +if(CONFIG_SENSORS_MPU60X0) + list(APPEND SRCS stm32_mpu6000.c) +endif() + +if(CONFIG_VIDEO_MAX7456) + list(APPEND SRCS stm32_max7456.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_NETDEVICES) + list(APPEND SRCS stm32_netinit.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_BOARDCTL_IOCTL) + list(APPEND SRCS stm32_ioctl.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_MMCSD) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/omnibusf4/src/Make.defs b/boards/arm/stm32f4/omnibusf4/src/Make.defs new file mode 100644 index 0000000000000..b0c74f55cdee9 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/Make.defs @@ -0,0 +1,84 @@ +############################################################################ +# boards/arm/stm32f4/omnibusf4/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c stm32_userleds.c + +ifeq ($(CONFIG_SENSORS_MPU60X0),y) +CSRCS += stm32_mpu6000.c +endif + +ifeq ($(CONFIG_VIDEO_MAX7456),y) +CSRCS += stm32_max7456.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) +CSRCS += stm32_ioctl.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += stm32_romfs_initialize.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += stm32_mmcsd.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/omnibusf4/src/omnibusf4.h b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h similarity index 98% rename from boards/arm/stm32/omnibusf4/src/omnibusf4.h rename to boards/arm/stm32f4/omnibusf4/src/omnibusf4.h index d401a52253d24..1eb7d9667cb9e 100644 --- a/boards/arm/stm32/omnibusf4/src/omnibusf4.h +++ b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/omnibusf4.h + * boards/arm/stm32f4/omnibusf4/src/omnibusf4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c new file mode 100644 index 0000000000000..1eb7e82d4bae0 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "omnibusf4.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the + * 1) OTG FS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into the + * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + * selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef HAVE_NETMONITOR + /* Configure board resources to support networking. */ + + if (stm32_netinitialize) + { + stm32_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef HAVE_CCM_HEAP + /* Initialize CCM allocator */ + + ccm_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c new file mode 100644 index 0000000000000..59aa712f47fda --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c @@ -0,0 +1,292 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#include "stm32_romfs.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#include "omnibusf4.h" + +/* Conditional logic in omnibusf4.h will determine if certain features + * are supported. Tests for these features need to be made after including + * omnibusf4.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + uerr("ERROR: Failed to start USB monitor: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Our MMC/SD port is on SPI2. */ + + ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + +#ifdef CONFIG_PWM + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MPU60X0 + /* Initialize the MPU6000 device. */ + + ret = stm32_mpu6000_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mpu6000_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_MAX7456 + /* Initialize the MAX7456 OSD device. */ + + ret = stm32_max7456_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_max7456_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + /* Initialize and mount ROMFS. */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#if defined(CONFIG_RNDIS) + /* Set up a MAC address for the RNDIS device. */ + + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c new file mode 100644 index 0000000000000..ae1ed8241462b --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c @@ -0,0 +1,260 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_ioctl.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c index c7d7674e3bf64..c744806de825a 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_ioctl.c + * boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_max7456.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c index 58413d89ee70f..05c90434478ff 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_max7456.c + * boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..2459813e68b58 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + /* TODO: media change callback */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int port, int minor) +{ + struct spi_dev_s *spi; + int rv; + + stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ + + mcinfo("INFO: Initializing mmcsd port %d minor %d SD_DET %x\n", + port, minor, stm32_gpioread(GPIO_MMCSD_NCD)); + + spi = stm32_spibus_initialize(port); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", port); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, minor, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + port, minor); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c index 9d79cf9790e83..c2957c2a7e1de 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c + * boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c new file mode 100644 index 0000000000000..3360c835506fe --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c @@ -0,0 +1,41 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c new file mode 100644 index 0000000000000..dfe132e9f78dd --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "omnibusf4.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pm_buttons(); +#endif + + /* Initialize the LED PM */ + + stm32_led_pminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c new file mode 100644 index 0000000000000..41770c035b60d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "omnibusf4.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * + * Initialize PWM and register Omnibus F4's TIM2 and TIM3 PWM devices: + * + * TIM3 CH3 PB0 S1_OUT + * TIM3 CH4 PB1 S2_OUT + * TIM2 CH4 PA3 S3_OUT + * TIM2 CH3 PA2 S4_OUT + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + int npwm = 0; /* hardware device enumerator */ + const char *ppwm = NULL; /* pointer to PWM device name */ + struct pwm_lowerhalf_s *pwm = NULL; /* lower-half driver handle */ + + /* Initialize TIM2 and TIM3. + * + * Ihe underlying STM32 driver "knows" there are up to four channels + * available for each timer device, so we don't have to do anything + * special here to export the two channels each that we're + * interested in. The user will want to avoid the channels that + * aren't connected to anything, however, or risk death by boredom + * from resulting non-response. + */ + + for (npwm = 2; npwm <= 3; npwm++) + { + pwm = stm32_pwminitialize(npwm); + + /* If we can't get the lower-half handle, skip and keep going. */ + + if (!pwm) + { + continue; + } + + /* Translate the peripheral number to a device name. */ + + switch (npwm) + { + case 2: + ppwm = "/dev/pwm2"; + break; + + case 3: + ppwm = "/dev/pwm3"; + break; + + /* Skip missing names. */ + + default: + continue; + } + + pwm_register(ppwm, pwm); + } + + return 0; +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c new file mode 100644 index 0000000000000..4d6ec55831d9d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32_dfumode.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int board_reset(int mode) +{ + if (mode == 0) + { + /* Normal reset */ + + up_systemreset(); + } + else + { + /* DFU reset */ + + stm32_dfumode(); + } +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h new file mode 100644 index 0000000000000..b1376c031e76b --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c new file mode 100644 index 0000000000000..8c5d8069a9522 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#else + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + ".section .rodata, \"a\"\n" + ".balign 16\n" + ".globl romfs_data_begin\n" +"romfs_data_begin:\n" + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ + \ + ".balign " STR(ROMFS_SECTOR_SIZE) "\n" + ".globl romfs_data_end\n" +"romfs_data_end:\n"); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + size_t romfs_data_len + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c new file mode 100644 index 0000000000000..91a4916ca6f77 --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "omnibusf4.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the omnibusf4 board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_CS_MPU6000); + stm32_configgpio(GPIO_EXTI_MPU6000); +#endif +#ifdef CONFIG_STM32_SPI3 + stm32_configgpio(GPIO_CS_MAX7456); +#endif +#if defined(CONFIG_MMCSD_SPI) + stm32_configgpio(GPIO_MMCSD_NCD); /* SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* CS */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and + * status operations using GPIOs in the way your board is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: CS is active-low. */ + + stm32_gpiowrite(GPIO_CS_MPU6000, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: NSS is active-low. */ + + stm32_gpiowrite(GPIO_MMCSD_NSS, selected ? 0 : 1); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + /* Note: SD_DET is pulled high when there's no SD card present. */ + + return stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + /* Note: MAX7456 CS is active-low. */ + + stm32_gpiowrite(GPIO_CS_MAX7456, selected ? 0 : 1); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c new file mode 100644 index 0000000000000..c0b13b8a0a26d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "omnibusf4.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. This should be of the + * form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c new file mode 100644 index 0000000000000..5ea001248f0cd --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c new file mode 100644 index 0000000000000..d229c176ce9ed --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c @@ -0,0 +1,338 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "omnibusf4.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_OMNIBUSF4_USBHOST_PRIO +# define CONFIG_OMNIBUSF4_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_OMNIBUSF4_USBHOST_STACKSIZE +# define CONFIG_OMNIBUSF4_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Omnibusf4 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_OMNIBUSF4_USBHOST_PRIO, + CONFIG_OMNIBUSF4_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..5fb5e1124971d --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_sdinitialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c new file mode 100644 index 0000000000000..ecfafda5b1fac --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c @@ -0,0 +1,217 @@ +/**************************************************************************** + * boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "omnibusf4.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, + GPIO_BEEPER1 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) + { + stm32_configgpio(g_ledcfg[wled]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + for (unsigned wled = 0; wled < BOARD_NLEDS; wled++) + { + stm32_gpiowrite(g_ledcfg[wled], + (ledset & (1 << wled)) == 0 ? 1 : 0); + } +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt new file mode 100644 index 0000000000000..efa9246cf956b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/Kconfig b/boards/arm/stm32f4/stm3240g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3240g-eval/Kconfig rename to boards/arm/stm32f4/stm3240g-eval/Kconfig diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig new file mode 100644 index 0000000000000..f6c6f56690768 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NETUTILS_DHCPD_IGNOREBROADCAST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_DHCPD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="dhcpd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig new file mode 100644 index 0000000000000..616c7e441cb72 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISCOVER_DESCR="STM3240G-EVAL" +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_DISCOVER=y +CONFIG_EXAMPLES_DISCOVER_DHCPC=y +CONFIG_EXAMPLES_DISCOVER_DRIPADDR=0xc0a80201 +CONFIG_EXAMPLES_DISCOVER_NOMAC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="discover_main" +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig new file mode 100644 index 0000000000000..7658129cd2b0b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_PDCURSES=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_PDCURSES=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0x64000000 +CONFIG_HEAP2_SIZE=2097152 +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PDCURSES_FONT_6X9=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=9 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs new file mode 100644 index 0000000000000..bdadecf86030b --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)kernel-space.ld + +ARCHCXXFLAGS += -fpermissive +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig new file mode 100644 index 0000000000000..8e78252589727 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig @@ -0,0 +1,99 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NXWM_NXTERM is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_ARM_TOOLCHAIN_BUILDROOT=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIBC_USRWORK=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NUTTX_USERSPACE=0x08040000 +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXSTART_SERVERSTACK=1596 +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm3240g-eval/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig new file mode 100644 index 0000000000000..1f3385947f2d1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_NOMAC=y +CONFIG_EXAMPLES_NETTEST_PERFORMANCE=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nettest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_NETLIB=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig new file mode 100644 index 0000000000000..80a98d96abb30 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig new file mode 100644 index 0000000000000..005e9e04a08fe --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_NSH_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDIO=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig new file mode 100644 index 0000000000000..25740c07a6c71 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig @@ -0,0 +1,104 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_NXTERM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0x64000000 +CONFIG_HEAP2_SIZE=2097152 +CONFIG_HOST_WINDOWS=y +CONFIG_I2C=y +CONFIG_I2CTOOL_DEFFREQ=100000 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxterm_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=256 +CONFIG_NXTK_BORDERCOLOR1=0xad55 +CONFIG_NXTK_BORDERCOLOR2=0x6b4d +CONFIG_NXTK_BORDERCOLOR3=0xdedb +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig new file mode 100644 index 0000000000000..9104b7cd84a13 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig @@ -0,0 +1,123 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_MULTIPLE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig new file mode 100644 index 0000000000000..fbe59922f17a5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_CLIENTPRIO=128 +CONFIG_EXAMPLES_TELNETD_DAEMONPRIO=128 +CONFIG_EXAMPLES_TELNETD_NOMAC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="telnetd_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NSH_LIBRARY=y +CONFIG_NUNGET_CHARS=0 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DFU=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig new file mode 100644 index 0000000000000..28c7c0ac95600 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="webserver_main" +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MTD=y +CONFIG_NET=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART3=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig new file mode 100644 index 0000000000000..530c00545a4e2 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm3240g-eval" +CONFIG_ARCH_BOARD_STM3240G_EVAL=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_ETH0_PHY_DP83848C=y +CONFIG_EXAMPLES_XMLRPC=y +CONFIG_EXAMPLES_XMLRPC_DHCPC=y +CONFIG_EXAMPLES_XMLRPC_NOMAC=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_INIT_ENTRYPOINT="xmlrpc_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT_ENTRIES=4 +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=650 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=40 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=196608 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYSR=16 +CONFIG_STM32_PHYSR_100MBPS=0x0000 +CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004 +CONFIG_STM32_PHYSR_MODE=0x0004 +CONFIG_STM32_PHYSR_SPEED=0x0002 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_RXBUFSIZE=128 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USART3_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm3240g-eval/include/board.h b/boards/arm/stm32f4/stm3240g-eval/include/board.h new file mode 100644 index 0000000000000..702e2d93d9084 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/include/board.h @@ -0,0 +1,603 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H +#define __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Logic in arch/arm/src and boards/ may need to include these file prior to + * including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be + * included here because board.h is used in other contexts where the STM32 + * internal header files are not available. + */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four clock sources are available on STM3240G-EVAL evaluation board for + * STM32F407IGH6 and RTC embedded: + * + * X1, 25 MHz crystal for Ethernet PHY with socket. + * It can be removed when clock is provided by MCO pin of the MCU + * X2, 26 MHz crystal for USB OTG HS PHY + * X3, 32 kHz crystal for embedded RTC + * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller + * (It can be removed from socket when internal RC clock is used.) + * + * This is the "standard" configuration as set up by + * arch/arm/src/stm32f40xx_rcc.c: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 25MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same as APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8-11 are on APB2, others on APB1 + */ + +#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN +#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN +#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN +#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN + +#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN +#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN +#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN +#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN +#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* Ethernet *****************************************************************/ + +/* We need to provide clocking to the MII PHY via MCO1 (PA8) */ + +#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC) + +# if !defined(CONFIG_STM32_MII) +# warning "CONFIG_STM32_MII required for Ethernet" +# elif !defined(CONFIG_STM32_MII_MCO1) +# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII" +# else + + /* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */ + +# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE +# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE + +# endif +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM3240G-EVAL supports three buttons: */ + +#define BUTTON_WAKEUP 0 +#define BUTTON_TAMPER 1 +#define BUTTON_USER 2 + +#define NUM_BUTTONS 3 + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* SRAM definitions *********************************************************/ + +/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares + * the same I/Os with the CAN1 bus. Jumper settings: + * + * JP1: Connect PE4 to SRAM as A20 + * JP2: onnect PE3 to SRAM as A19 + * + * JP3 and JP10 must not be fitted for SRAM and LCD application. + * JP3 and JP10 select CAN1 or CAN2 if fitted; neither if not fitted. + */ + +#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM) +# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) +# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM" +# endif +#endif + +/* This is the Bank1 SRAM2 address: */ + +#define BOARD_SRAM_BASE 0x64000000 +#define BOARD_SRAM_SIZE (2*1024*1024) + +/* Alternate function pin selections ****************************************/ + +/* UART3: + * + * - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open) + * - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX + */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_2|GPIO_SPEED_100MHz) +#define GPIO_USART3_TX (GPIO_USART3_TX_2|GPIO_SPEED_100MHz) + +/* Ethernet: + * + * - PA2 is ETH_MDIO + * - PC1 is ETH_MDC + * - PB5 is ETH_PPS_OUT + * - PH2 is ETH_MII_CRS + * - PH3 is ETH_MII_COL + * - PI10 is ETH_MII_RX_ER + * - PH6 is ETH_MII_RXD2 + * - PH7 is ETH_MII_RXD3 + * - PC3 is ETH_MII_TX_CLK + * - PC2 is ETH_MII_TXD2 + * - PB8 is ETH_MII_TXD3 + * - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK + * - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV + * - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0 + * - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1 + * - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN + * - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0 + * - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1 + */ + +#define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_CRS (GPIO_ETH_MII_CRS_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_COL (GPIO_ETH_MII_COL_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_ER (GPIO_ETH_MII_RX_ER_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD2 (GPIO_ETH_MII_RXD2_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD3 (GPIO_ETH_MII_RXD3_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD3 (GPIO_ETH_MII_TXD3_1|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_EN (GPIO_ETH_MII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD0 (GPIO_ETH_MII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD1 (GPIO_ETH_MII_TXD1_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_2|GPIO_SPEED_100MHz) + +/* PWM + * + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using the following: + * + * If FSMC is not used: + * TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT + * Daughterboard Extension Connector, CN3, pin 32 + * Motor Control Connector CN15, + * pin 33 -- not available unless you bridge SB14. + * + * TIM1 CH1OUT: PE9 FSMC_D6 + * Daughterboard Extension Connector, CN2, pin 24 + * + * TIM1_CH2OUT: PE11 FSMC_D8 + * Daughterboard Extension Connector, CN2, pin 26 + * + * TIM1_CH3OUT: PE13 FSMC_D10 + * Daughterboard Extension Connector, CN2, pin 28 + * + * TIM1_CH4OUT: PE14 FSMC_D11 + * Daughterboard Extension Connector, CN2, pin 29 + * + * If OTG FS is not used + * + * TIM1_CH3OUT: PA10 OTG_FS_ID + * Daughterboard Extension Connector, CN3, pin 14 + * + * TIM1_CH4OUT: PA11 OTG_FS_DM + * Daughterboard Extension Connector, CN3, pin 11 + * + * If DMCI is not used + * + * TIM8 CH1OUT: PI5 DCMI_VSYNC & MC + * Daughterboard Extension Connector, CN4, pin 4 + * + * TIM8_CH2OUT: PI6 DCMI_D6 & MC + * Daughterboard Extension Connector, CN4, pin 3 + * + * TIM8_CH3OUT: PI7 DCMI_D7 & MC + * Daughterboard Extension Connector, CN4, pin 2 + * + * If SDIO is not used + * + * TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC + * Daughterboard Extension Connector, CN3, pin 18 + * + * TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open) + * Daughterboard Extension Connector, CN3, pin 17 + * + * Others + * + * TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open) + */ + +#if !defined(CONFIG_STM32_FSMC) +# define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) +#elif !defined(CONFIG_STM32_OTGFS) +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) +# define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +#if !defined(CONFIG_STM32_DCMI) +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH2OUT (GPIO_TIM8_CH2OUT_2|GPIO_SPEED_50MHz) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_2|GPIO_SPEED_50MHz) +#else +# define GPIO_TIM8_CH1OUT (GPIO_TIM8_CH1OUT_1|GPIO_SPEED_50MHz) +# if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH3OUT (GPIO_TIM8_CH3OUT_1|GPIO_SPEED_50MHz) +# endif +#endif + +#if !defined(CONFIG_STM32_SDIO) +# define GPIO_TIM8_CH4OUT (GPIO_TIM8_CH4OUT_1|GPIO_SPEED_50MHz) +#endif + +/* CAN + * + * Connector 10 (CN10) + * is DB-9 male connector that can be used with CAN1 or CAN2. + * + * JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver + * JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver + * + * CAN signals are then available on CN10 pins: + * + * CN10 Pin 7 = CANH + * CN10 Pin 2 = CANL + * + * Mapping to STM32 GPIO pins: + * + * PD0 = FSMC_D2 & CAN1_RX + * PD1 = FSMC_D3 & CAN1_TX + * PB13 = ULPI_D6 & CAN2_TX + * PB5 = ULPI_D7 & CAN2_RX + */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) + +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) + +/* I2C. + * Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are + * available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3240g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the STM3210E-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_FSMC +void stm3240g_lcdclear(uint16_t color); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/* ETH MII/RMII inputs and MDC/MDIO + MCO1 */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_CLK (GPIO_ETH_MII_RX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RX_DV (GPIO_ETH_MII_RX_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD0 (GPIO_ETH_MII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_RXD1 (GPIO_ETH_MII_RXD1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TX_CLK (GPIO_ETH_MII_TX_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MII_TXD2 (GPIO_ETH_MII_TXD2_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* FSMC SRAM/LCD */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARD_ARM_STM32_STM3240G_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile new file mode 100644 index 0000000000000..f89e2210f73fe --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..ca655d1ada4bc --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08040000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08040000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs new file mode 100644 index 0000000000000..9f8df9bce9c68 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld new file mode 100644 index 0000000000000..7712a4771a100 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script new file mode 100644 index 0000000000000..a4987bf37e078 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld new file mode 100644 index 0000000000000..4f997fbe4f9ac --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 256Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + uflash (rx) : ORIGIN = 0x08040000, LENGTH = 256K + xflash (rx) : ORIGIN = 0x08080000, LENGTH = 512K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K + usram (rwx) : ORIGIN = 0x20001800, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002800, LENGTH = 102K +} diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld new file mode 100644 index 0000000000000..fd7922b7737e5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt new file mode 100644 index 0000000000000..1969d7755e529 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt @@ -0,0 +1,62 @@ +# ############################################################################## +# boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c) + list(APPEND SRCS stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/stm3240g-eval/src/Make.defs b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs new file mode 100644 index 0000000000000..529bccfba93f0 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_lcd.c stm32_selectlcd.c stm32_deselectlcd.c +CSRCS += stm32_selectsram.c stm32_deselectsram.c stm32_extmem.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h rename to boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h index b607dc33408ba..da73e0674a9bd 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h + * boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c new file mode 100644 index 0000000000000..ec49c4f1225d0 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC3 +# warning "Channel information only available for ADC3" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The STM3240G-EVAL has a 10 Kohm potentiometer RV1 connected to PF9 of + * STM32F407IGH6 on the board: TIM14_CH1/FSMC_CD/ADC3_IN7 + */ + +/* Identifying number of each ADC channel: Variable Resistor. */ + +#ifdef CONFIG_STM32_ADC3 +static const uint8_t g_chanlist[ADC3_NCHANNELS] = +{ + 7 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_IN7 +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#ifdef CONFIG_STM32_ADC3 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(3, g_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c new file mode 100644 index 0000000000000..d09719923af0a --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM3210E_LED1 (1 << 0) +#define STM3210E_LED2 (1 << 1) +#define STM3210E_LED3 (1 << 2) +#define STM3210E_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM3210E_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM3210E_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM3210E_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM3210E_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_led_initialize + ****************************************************************************/ + +void stm32_led_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c new file mode 100644 index 0000000000000..f77dac198d8ec --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm3240g-eval.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) + * the weak function stm32_spidev_initialize() has been brought into the + * link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_FSMC + /* If the FSMC is enabled, then enable SRAM access */ + + stm32_selectsram(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought the weak function stm32_usbinitialize() has been brought into + * the build. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + stm32_led_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform the board initialization on the start-up thread. Some + * initializations may fail in this case due to the limited capability of + * the start-up thread. + */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c new file mode 100644 index 0000000000000..80e06aa4a9aee --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c @@ -0,0 +1,390 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +#endif + +#ifdef CONFIG_STM32_SDIO +# include +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_INPUT_STMPE811 +# include +#endif + +#include "stm32.h" +#include "stm32_i2c.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* For now, don't build in any SPI1 support -- NSH is not using it */ + +#undef CONFIG_STM32_SPI1 + +/* Assume that we support everything until convinced otherwise */ + +#define HAVE_MMCSD 1 +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_RTC_DRIVER 1 + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO) +# undef HAVE_MMCSD +#endif + +/* Default MMC/SD minor number */ + +#ifdef HAVE_MMCSD +# ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +# endif + +/* Default MMC/SD SLOT number */ + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif + +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#endif + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +#endif + +/* Can't support USB device is USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we can support the RTC driver */ + +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; +#endif +#ifdef HAVE_MMCSD + struct sdio_dev_s *sdio; +#endif + int ret; + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", + ret); + } + } +#endif + + /* Configure SPI-based devices */ + +#ifdef CONFIG_STM32_SPI1 + /* Get the SPI port */ + + spi = stm32_spibus_initialize(1); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 0\n"); + } + else + { + /* Now bind the SPI interface to the M25P64/128 SPI FLASH driver */ + + mtd = m25p_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SPI port 0 to SPI FLASH driver\n"); + } + } + +#warning "Now what are we going to do with this SPI FLASH driver?" +#endif + +#ifdef HAVE_MMCSD + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!sdio) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SDIO slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + } + else + { + /* Now bind the SDIO interface to the MMC/SD driver */ + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, sdio); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", + ret); + } + + /* Then let's guess and say that there is a card in the slot. I need + * to check to see if the STM3240G-EVAL board supports a GPIO to + * detect if there is a card in the slot. + */ + + sdio_mediachange(sdio, true); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread that will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the simulated framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen. + * WARNING: stm32_tsc_setup() cannot be called from the IDLE thread. + */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c new file mode 100644 index 0000000000000..6f53a11fb24d5 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm3240g-eval.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM3210E-EVAL button. This array is indexed by + * the BUTTON_* and JOYSTICK_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed for most keys. + * The exception is the WAKEUP button. + */ + + bool released = stm32_gpioread(g_buttons[i]); + if (i == BUTTON_WAKEUP) + { + released = !released; + } + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c new file mode 100644 index 0000000000000..ec742a605d557 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c new file mode 100644 index 0000000000000..ff9e69d2c0daa --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectlcd + * + * Description: + * Disable the LCD + * + ****************************************************************************/ + +void stm32_deselectlcd(void) +{ + /* Restore registers to their power up settings */ + + putreg32(0xffffffff, STM32_FSMC_BCR4); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(0x0fffffff, STM32_FSMC_BTR4); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c new file mode 100644 index 0000000000000..2ced0277d8fb1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_deselectsram + * + * Description: + * Disable SRAM + * + ****************************************************************************/ + +void stm32_deselectsram(void) +{ + /* Restore registers to their power up settings */ + + putreg32(FSMC_BCR_RSTVALUE, STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_RSTVALUE, STM32_FSMC_BTR2); + + /* Disable AHB clocking to the FSMC */ + + stm32_fsmc_disable(); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c new file mode 100644 index 0000000000000..46afe66b92805 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c new file mode 100644 index 0000000000000..0bd00dd976be1 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c @@ -0,0 +1,1188 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This driver supports the following LCDs on the STM324xG_EVAL board: + * + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR + * AM-240320D5TOQW01H (LCD_ILI9325) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H(LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H(LCD_ILI9325) + */ + +/* Check contrast selection */ + +#if !defined(CONFIG_LCD_MAXCONTRAST) +# define CONFIG_LCD_MAXCONTRAST 1 +#endif + +/* Check power setting */ + +#if !defined(CONFIG_LCD_MAXPOWER) || CONFIG_LCD_MAXPOWER < 1 +# define CONFIG_LCD_MAXPOWER 1 +#endif + +#if CONFIG_LCD_MAXPOWER > 255 +# error "CONFIG_LCD_MAXPOWER must be less than 256 to fit in uint8_t" +#endif + +/* Check orientation */ + +#if defined(CONFIG_LCD_PORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) || defined(CONFIG_LCD_RPORTRAIT) +# error "Cannot define both portrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_RPORTRAIT) +# if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# error "Cannot define both rportrait and any other orientations" +# endif +#elif defined(CONFIG_LCD_LANDSCAPE) +# ifdef CONFIG_LCD_RLANDSCAPE +# error "Cannot define both landscape and any other orientations" +# endif +#elif !defined(CONFIG_LCD_RLANDSCAPE) +# define CONFIG_LCD_LANDSCAPE 1 +#endif + +/* Display/Color Properties *************************************************/ + +/* Display Resolution */ + +#if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) +# define STM3240G_XRES 320 +# define STM3240G_YRES 240 +#else +# define STM3240G_XRES 240 +# define STM3240G_YRES 320 +#endif + +/* Color depth and format */ + +#define STM3240G_BPP 16 +#define STM3240G_COLORFMT FB_FMT_RGB16_565 + +/* STM3240G-EVAL LCD Hardware Definitions ***********************************/ + +/* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ + +#define STM3240G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) +#define LCD ((struct lcd_regs_s *)STM3240G_LCDBASE) + +#define LCD_REG_0 0x00 +#define LCD_REG_1 0x01 +#define LCD_REG_2 0x02 +#define LCD_REG_3 0x03 +#define LCD_REG_4 0x04 +#define LCD_REG_5 0x05 +#define LCD_REG_6 0x06 +#define LCD_REG_7 0x07 +#define LCD_REG_8 0x08 +#define LCD_REG_9 0x09 +#define LCD_REG_10 0x0a +#define LCD_REG_12 0x0c +#define LCD_REG_13 0x0d +#define LCD_REG_14 0x0e +#define LCD_REG_15 0x0f +#define LCD_REG_16 0x10 +#define LCD_REG_17 0x11 +#define LCD_REG_18 0x12 +#define LCD_REG_19 0x13 +#define LCD_REG_20 0x14 +#define LCD_REG_21 0x15 +#define LCD_REG_22 0x16 +#define LCD_REG_23 0x17 +#define LCD_REG_24 0x18 +#define LCD_REG_25 0x19 +#define LCD_REG_26 0x1a +#define LCD_REG_27 0x1b +#define LCD_REG_28 0x1c +#define LCD_REG_29 0x1d +#define LCD_REG_30 0x1e +#define LCD_REG_31 0x1f +#define LCD_REG_32 0x20 +#define LCD_REG_33 0x21 +#define LCD_REG_34 0x22 +#define LCD_REG_36 0x24 +#define LCD_REG_37 0x25 +#define LCD_REG_40 0x28 +#define LCD_REG_41 0x29 +#define LCD_REG_43 0x2b +#define LCD_REG_45 0x2d +#define LCD_REG_48 0x30 +#define LCD_REG_49 0x31 +#define LCD_REG_50 0x32 +#define LCD_REG_51 0x33 +#define LCD_REG_52 0x34 +#define LCD_REG_53 0x35 +#define LCD_REG_54 0x36 +#define LCD_REG_55 0x37 +#define LCD_REG_56 0x38 +#define LCD_REG_57 0x39 +#define LCD_REG_58 0x3a +#define LCD_REG_59 0x3b +#define LCD_REG_60 0x3c +#define LCD_REG_61 0x3d +#define LCD_REG_62 0x3e +#define LCD_REG_63 0x3f +#define LCD_REG_64 0x40 +#define LCD_REG_65 0x41 +#define LCD_REG_66 0x42 +#define LCD_REG_67 0x43 +#define LCD_REG_68 0x44 +#define LCD_REG_69 0x45 +#define LCD_REG_70 0x46 +#define LCD_REG_71 0x47 +#define LCD_REG_72 0x48 +#define LCD_REG_73 0x49 +#define LCD_REG_74 0x4a +#define LCD_REG_75 0x4b +#define LCD_REG_76 0x4c +#define LCD_REG_77 0x4d +#define LCD_REG_78 0x4e +#define LCD_REG_79 0x4f +#define LCD_REG_80 0x50 +#define LCD_REG_81 0x51 +#define LCD_REG_82 0x52 +#define LCD_REG_83 0x53 +#define LCD_REG_96 0x60 +#define LCD_REG_97 0x61 +#define LCD_REG_106 0x6a +#define LCD_REG_118 0x76 +#define LCD_REG_128 0x80 +#define LCD_REG_129 0x81 +#define LCD_REG_130 0x82 +#define LCD_REG_131 0x83 +#define LCD_REG_132 0x84 +#define LCD_REG_133 0x85 +#define LCD_REG_134 0x86 +#define LCD_REG_135 0x87 +#define LCD_REG_136 0x88 +#define LCD_REG_137 0x89 +#define LCD_REG_139 0x8b +#define LCD_REG_140 0x8c +#define LCD_REG_141 0x8d +#define LCD_REG_143 0x8f +#define LCD_REG_144 0x90 +#define LCD_REG_145 0x91 +#define LCD_REG_146 0x92 +#define LCD_REG_147 0x93 +#define LCD_REG_148 0x94 +#define LCD_REG_149 0x95 +#define LCD_REG_150 0x96 +#define LCD_REG_151 0x97 +#define LCD_REG_152 0x98 +#define LCD_REG_153 0x99 +#define LCD_REG_154 0x9a +#define LCD_REG_157 0x9d +#define LCD_REG_164 0xa4 +#define LCD_REG_192 0xc0 +#define LCD_REG_193 0xc1 +#define LCD_REG_229 0xe5 + +/* LCD IDs */ + +#define ILI9320_ID 0x9320 +#define ILI9321_ID 0x9321 +#define ILI9325_ID 0x9325 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* LCD type */ + +enum lcd_type_e +{ + LCD_TYPE_UNKNOWN = 0, + LCD_TYPE_ILI9320, + LCD_TYPE_ILI9325 +}; + +/* This structure describes the LCD registers */ + +struct lcd_regs_s +{ + volatile uint16_t address; + volatile uint16_t value; +}; + +/* This structure describes the state of this driver */ + +struct stm3240g_dev_s +{ + /* Publicly visible device structure */ + + struct lcd_dev_s dev; + + /* Private LCD-specific information follows */ + + uint8_t type; /* LCD type. See enum lcd_type_e */ + uint8_t power; /* Current power setting */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm3240g_writereg(uint8_t regaddr, uint16_t regval); +static uint16_t stm3240g_readreg(uint8_t regaddr); +static inline void stm3240g_gramselect(void); +static inline void stm3240g_writegram(uint16_t rgbval); +static void stm3240g_readnosetup(uint16_t *accum); +static uint16_t stm3240g_readnoshift(uint16_t *accum); +static void stm3240g_setcursor(uint16_t col, uint16_t row); + +/* LCD Data Transfer Methods */ + +static int stm3240g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels); +static int stm3240g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels); + +/* LCD Configuration */ + +static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo); +static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo); + +/* LCD RGB Mapping */ + +#ifdef CONFIG_FB_CMAP +# error "RGB color mapping not supported by this driver" +#endif + +/* Cursor Controls */ + +#ifdef CONFIG_FB_HWCURSOR +# error "Cursor control not supported by this driver" +#endif + +/* LCD Specific Controls */ + +static int stm3240g_getpower(struct lcd_dev_s *dev); +static int stm3240g_setpower(struct lcd_dev_s *dev, int power); +static int stm3240g_getcontrast(struct lcd_dev_s *dev); +static int stm3240g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); + +/* Initialization */ + +static inline void stm3240g_lcdinitialize(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is working memory allocated by the LCD driver for each LCD device + * and for each color plane. This memory will hold one raster line of data. + * The size of the allocated run buffer must therefore be at least + * (bpp * xres / 8). Actual alignment of the buffer must conform to the + * bitwidth of the underlying pixel type. + * + * If there are multiple planes, they may share the same working buffer + * because different planes will not be operate on concurrently. However, + * if there are multiple LCD devices, they must each have unique run buffers. + */ + +static uint16_t g_runbuffer[STM3240G_XRES]; + +/* This structure describes the overall LCD video controller */ + +static const struct fb_videoinfo_s g_videoinfo = +{ + .fmt = STM3240G_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ + .xres = STM3240G_XRES, /* Horizontal resolution in pixel columns */ + .yres = STM3240G_YRES, /* Vertical resolution in pixel rows */ + .nplanes = 1, /* Number of color planes supported */ +}; + +/* This is the standard, NuttX Plane information object */ + +static const struct lcd_planeinfo_s g_planeinfo = +{ + .putrun = stm3240g_putrun, /* Put a run into LCD memory */ + .getrun = stm3240g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3240G_BPP, /* Bits-per-pixel */ +}; + +/* This is the standard, NuttX LCD driver object */ + +static struct stm3240g_dev_s g_lcddev = +{ + .dev = + { + /* LCD Configuration */ + + .getvideoinfo = stm3240g_getvideoinfo, + .getplaneinfo = stm3240g_getplaneinfo, + + /* LCD RGB Mapping -- Not supported */ + + /* Cursor Controls -- Not supported */ + + /* LCD Specific Controls */ + + .getpower = stm3240g_getpower, + .setpower = stm3240g_setpower, + .getcontrast = stm3240g_getcontrast, + .setcontrast = stm3240g_setcontrast, + }, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm3240g_writereg + * + * Description: + * Write to an LCD register + * + ****************************************************************************/ + +static void stm3240g_writereg(uint8_t regaddr, uint16_t regval) +{ + /* Write the register address then write the register value */ + + LCD->address = regaddr; + LCD->value = regval; +} + +/**************************************************************************** + * Name: stm3240g_readreg + * + * Description: + * Read from an LCD register + * + ****************************************************************************/ + +static uint16_t stm3240g_readreg(uint8_t regaddr) +{ + /* Write the register address then read the register value */ + + LCD->address = regaddr; + return LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_gramselect + * + * Description: + * Setup to read or write multiple pixels to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3240g_gramselect(void) +{ + LCD->address = LCD_REG_34; +} + +/**************************************************************************** + * Name: stm3240g_writegram + * + * Description: + * Write one pixel to the GRAM memory + * + ****************************************************************************/ + +static inline void stm3240g_writegram(uint16_t rgbval) +{ + /* Write the value (GRAM register already selected) */ + + LCD->value = rgbval; +} + +/**************************************************************************** + * Name: stm3240g_readnosetup + * + * Description: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: + * + * - ILI932x: Discard first dummy read; no shift in the return data + * + ****************************************************************************/ + +static void stm3240g_readnosetup(uint16_t *accum) +{ + /* Read-ahead one pixel */ + + *accum = LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_readnoshift + * + * Description: + * Read one correctly aligned pixel from the GRAM memory. Possibly + * shifting the data and possibly swapping red and green components. + * + * - ILI932x: Unknown -- assuming colors are in the color order + * + ****************************************************************************/ + +static uint16_t stm3240g_readnoshift(uint16_t *accum) +{ + /* Read the value (GRAM register already selected) */ + + return LCD->value; +} + +/**************************************************************************** + * Name: stm3240g_setcursor + * + * Description: + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. + * + ****************************************************************************/ + +static void stm3240g_setcursor(uint16_t col, uint16_t row) +{ + stm3240g_writereg(LCD_REG_32, row); /* GRAM horizontal address */ + stm3240g_writereg(LCD_REG_33, col); /* GRAM vertical address */ +} + +/**************************************************************************** + * Name: stm3240g_putrun + * + * Description: + * This method can be used to write a partial raster line to the LCD: + * + * dev - The lcd device + * row - Starting row to write to (range: 0 <= row < yres) + * col - Starting column to write to (range: 0 <= col <= xres-npixels) + * buffer - The buffer containing the run to be written to the LCD + * npixels - The number of pixels to write to the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3240g_putrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + const uint8_t *buffer, size_t npixels) +{ + const uint16_t *src = (const uint16_t *)buffer; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Write the run to GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + /* Write the GRAM data, manually incrementing X */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(col, row); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3240g_setcursor(col, row); + + /* Then write the GRAM data, auto-decrementing X */ + + stm3240g_gramselect(); + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ + + stm3240g_writegram(*src++); + } +#elif defined(CONFIG_LCD_PORTRAIT) + + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + col = (STM3240G_XRES - 1) - col; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3240G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + stm3240g_writegram(*src++); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getrun + * + * Description: + * This method can be used to read a partial raster line from the LCD: + * + * dev - The lcd device + * row - Starting row to read from (range: 0 <= row < yres) + * col - Starting column to read read (range: 0 <= col <= xres-npixels) + * buffer - The buffer in which to return the run read from the LCD + * npixels - The number of pixels to read from the LCD + * (range: 0 < npixels <= xres-col) + * + ****************************************************************************/ + +static int stm3240g_getrun(struct lcd_dev_s *dev, + fb_coord_t row, fb_coord_t col, + uint8_t *buffer, size_t npixels) +{ + uint16_t *dest = (uint16_t *)buffer; + void (*readsetup)(uint16_t *accum); + uint16_t (*readgram)(uint16_t *accum); + uint16_t accum; + int i; + + /* Buffer must be provided and aligned to a 16-bit address boundary */ + + lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); + DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); + + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ + + switch (g_lcddev.type) + { + case LCD_TYPE_ILI9320: + case LCD_TYPE_ILI9325: + readsetup = stm3240g_readnosetup; + readgram = stm3240g_readnoshift; + break; + + default: /* Shouldn't happen */ + return -ENOSYS; + } + + /* Read the run from GRAM. */ + +#ifdef CONFIG_LCD_LANDSCAPE + /* Convert coordinates -- Here the edge away from the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col++; + } +#elif defined(CONFIG_LCD_RLANDSCAPE) + /* Convert coordinates -- Here the edge next to the row of buttons on + * the STM3240G-EVAL is used as the top. + */ + + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; + + /* Set the cursor position */ + + stm3240g_setcursor(col, row); + + /* Then read the GRAM data, auto-decrementing Y */ + + stm3240g_gramselect(); + + /* Prime the pump for unaligned read data */ + + readsetup(&accum); + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position + * (autoincrements to the next row) + */ + + *dest++ = readgram(&accum); + } +#elif defined(CONFIG_LCD_PORTRAIT) + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + col = (STM3240G_XRES - 1) - col; + + /* Then read the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Read the next pixel from this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Increment to next column */ + + col--; + } +#else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). + */ + + row = (STM3240G_YRES - 1) - row; + + /* Then write the GRAM data, manually incrementing Y (which is col) */ + + for (i = 0; i < npixels; i++) + { + /* Write the next pixel to this position */ + + stm3240g_setcursor(row, col); + stm3240g_gramselect(); + readsetup(&accum); + *dest++ = readgram(&accum); + + /* Decrement to next column */ + + col++; + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getvideoinfo + * + * Description: + * Get information about the LCD video controller configuration. + * + ****************************************************************************/ + +static int stm3240g_getvideoinfo(struct lcd_dev_s *dev, + struct fb_videoinfo_s *vinfo) +{ + DEBUGASSERT(dev && vinfo); + lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); + memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getplaneinfo + * + * Description: + * Get information about the configuration of each LCD color plane. + * + ****************************************************************************/ + +static int stm3240g_getplaneinfo(struct lcd_dev_s *dev, + unsigned int planeno, + struct lcd_planeinfo_s *pinfo) +{ + DEBUGASSERT(dev && pinfo && planeno == 0); + lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); + memcpy(pinfo, &g_planeinfo, sizeof(struct lcd_planeinfo_s)); + pinfo->dev = dev; + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getpower + * + * Description: + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_getpower(struct lcd_dev_s *dev) +{ + lcdinfo("power: %d\n", 0); + return g_lcddev.power; +} + +/**************************************************************************** + * Name: stm3240g_poweroff + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_poweroff(void) +{ + /* Turn the display off */ + + stm3240g_writereg(LCD_REG_7, 0); + + /* Remember the power off state */ + + g_lcddev.power = 0; + return OK; +} + +/**************************************************************************** + * Name: stm3240g_setpower + * + * Description: + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. + * + ****************************************************************************/ + +static int stm3240g_setpower(struct lcd_dev_s *dev, int power) +{ + lcdinfo("power: %d\n", power); + DEBUGASSERT((unsigned)power <= CONFIG_LCD_MAXPOWER); + + /* Set new power level */ + + if (power > 0) + { + /* Then turn the display on */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) || !defined(CONFIG_STM3240G_ILI9325_DISABLE) + stm3240g_writereg(LCD_REG_7, 0x0173); +#endif + g_lcddev.power = power; + } + else + { + /* Turn the display off */ + + stm3240g_poweroff(); + } + + return OK; +} + +/**************************************************************************** + * Name: stm3240g_getcontrast + * + * Description: + * Get the current contrast setting (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3240g_getcontrast(struct lcd_dev_s *dev) +{ + lcdinfo("Not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3240g_setcontrast + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) +{ + lcdinfo("contrast: %d\n", contrast); + return -ENOSYS; +} + +/**************************************************************************** + * Name: stm3240g_lcdinitialize + * + * Description: + * Set LCD panel contrast (0-CONFIG_LCD_MAXCONTRAST). + * + ****************************************************************************/ + +static inline void stm3240g_lcdinitialize(void) +{ + uint16_t id; + + /* Check LCD ID */ + + id = stm3240g_readreg(LCD_REG_0); + lcdinfo("LCD ID: %04x\n", id); + + /* Check if the ID is for the STM32_ILI9320 (or ILI9321) or STM32_ILI9325 */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID || id == ILI9325_ID) +#elif !defined(CONFIG_STM3240G_ILI9320_DISABLE) && defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9320_ID || id == ILI9321_ID) +#else /* if defined(CONFIG_STM3240G_ILI9320_DISABLE) && !defined(CONFIG_STM3240G_ILI9325_DISABLE)) */ + if (id == ILI9325_ID) +#endif + { + /* Save the LCD type + * (not actually used at for anything important) + */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (id == ILI9325_ID) + { + g_lcddev.type = LCD_TYPE_ILI9325; + } + else +# endif + { + g_lcddev.type = LCD_TYPE_ILI9320; + stm3240g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ + } +#else /* if !defined(CONFIG_STM3240G_ILI9325_DISABLE) */ + g_lcddev.type = LCD_TYPE_ILI9325; +#endif + lcdinfo("LCD type: %d\n", g_lcddev.type); + + /* Start Initial Sequence */ + + stm3240g_writereg(LCD_REG_0, 0x0001); /* Start internal OSC. */ + stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ + stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ + stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ + + /* stm3240g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + + stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */ + stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ + stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ + stm3240g_writereg(LCD_REG_10, 0x0000); /* FMARK function */ + stm3240g_writereg(LCD_REG_12, 0x0000); /* RGB interface setting */ + stm3240g_writereg(LCD_REG_13, 0x0000); /* Frame marker Position */ + stm3240g_writereg(LCD_REG_15, 0x0000); /* RGB interface polarity */ + + /* Power On sequence */ + + stm3240g_writereg(LCD_REG_16, 0x0000); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3240g_writereg(LCD_REG_17, 0x0000); /* DC1[2:0], DC0[2:0], VC[2:0] */ + stm3240g_writereg(LCD_REG_18, 0x0000); /* VREG1OUT voltage */ + stm3240g_writereg(LCD_REG_19, 0x0000); /* VDV[4:0] for VCOM amplitude */ + up_mdelay(200); /* Dis-charge capacitor power voltage (200ms) */ + + stm3240g_writereg(LCD_REG_16, 0x17b0); /* SAP, BT[3:0], AP, DSTB, SLP, STB */ + stm3240g_writereg(LCD_REG_17, 0x0137); /* DC1[2:0], DC0[2:0], VC[2:0] */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_18, 0x0139); /* VREG1OUT voltage */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_19, 0x1d00); /* VDV[4:0] for VCOM amplitude */ + stm3240g_writereg(LCD_REG_41, 0x0013); /* VCM[4:0] for VCOMH */ + up_mdelay(50); + + stm3240g_writereg(LCD_REG_32, 0x0000); /* GRAM horizontal Address */ + stm3240g_writereg(LCD_REG_33, 0x0000); /* GRAM Vertical Address */ + + /* Adjust the Gamma Curve (ILI9320/1) */ + +#if !defined(CONFIG_STM3240G_ILI9320_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) + if (g_lcddev.type == LCD_TYPE_ILI9320) +# endif + { + stm3240g_writereg(LCD_REG_48, 0x0006); + stm3240g_writereg(LCD_REG_49, 0x0101); + stm3240g_writereg(LCD_REG_50, 0x0003); + stm3240g_writereg(LCD_REG_53, 0x0106); + stm3240g_writereg(LCD_REG_54, 0x0b02); + stm3240g_writereg(LCD_REG_55, 0x0302); + stm3240g_writereg(LCD_REG_56, 0x0707); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0600); + stm3240g_writereg(LCD_REG_61, 0x020b); + } +#endif + + /* Adjust the Gamma Curve (ILI9325) */ + +#if !defined(CONFIG_STM3240G_ILI9325_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) + else +# endif + { + stm3240g_writereg(LCD_REG_48, 0x0007); + stm3240g_writereg(LCD_REG_49, 0x0302); + stm3240g_writereg(LCD_REG_50, 0x0105); + stm3240g_writereg(LCD_REG_53, 0x0206); + stm3240g_writereg(LCD_REG_54, 0x0808); + stm3240g_writereg(LCD_REG_55, 0x0206); + stm3240g_writereg(LCD_REG_56, 0x0504); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0105); + stm3240g_writereg(LCD_REG_61, 0x0808); + } +#endif + + /* Set GRAM area */ + + stm3240g_writereg(LCD_REG_80, 0x0000); /* Horizontal GRAM Start Address */ + stm3240g_writereg(LCD_REG_81, 0x00ef); /* Horizontal GRAM End Address */ + stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ + stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ + stm3240g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ + + /* stm3240g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + + stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ + stm3240g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ + + /* Partial Display Control */ + + stm3240g_writereg(LCD_REG_128, 0x0000); + stm3240g_writereg(LCD_REG_129, 0x0000); + stm3240g_writereg(LCD_REG_130, 0x0000); + stm3240g_writereg(LCD_REG_131, 0x0000); + stm3240g_writereg(LCD_REG_132, 0x0000); + stm3240g_writereg(LCD_REG_133, 0x0000); + + /* Panel Control */ + + stm3240g_writereg(LCD_REG_144, 0x0010); + stm3240g_writereg(LCD_REG_146, 0x0000); + stm3240g_writereg(LCD_REG_147, 0x0003); + stm3240g_writereg(LCD_REG_149, 0x0110); + stm3240g_writereg(LCD_REG_151, 0x0000); + stm3240g_writereg(LCD_REG_152, 0x0000); + + /* Set GRAM write direction and BGR = 1 + * + * I/D=01 (Horizontal : increment, Vertical : decrement) + * AM=1 (address is updated in vertical writing direction) + */ + + stm3240g_writereg(LCD_REG_3, 0x1018); + stm3240g_writereg(LCD_REG_7, 0); /* Display off */ + } + else + { + lcderr("ERROR: Unsupported LCD type\n"); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Configure and enable LCD */ + + up_mdelay(50); + stm3240g_lcdinitialize(); + + /* Clear the display (setting it to the color 0=black) */ + + stm3240g_lcdclear(0); + + /* Turn the display off */ + + stm3240g_poweroff(); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return &g_lcddev.dev; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + stm3240g_poweroff(); + stm32_deselectlcd(); +} + +/**************************************************************************** + * Name: stm3240g_lcdclear + * + * Description: + * This is a non-standard LCD interface just for the stm3240g-EVAL board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. + * + ****************************************************************************/ + +void stm3240g_lcdclear(uint16_t color) +{ + uint32_t i = 0; + + stm3240g_setcursor(0, STM3240G_XRES - 1); + stm3240g_gramselect(); + for (i = 0; i < STM3240G_XRES * STM3240G_YRES; i++) + { + LCD->value = color; + } +} + +#endif /* !CONFIG_STM3240G_ILI9320_DISABLE || !CONFIG_STM3240G_ILI9325_DISABLE */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c new file mode 100644 index 0000000000000..4182be207e593 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM3240G-Eval has no real on-board PWM devices, but the board can be + * configured to output a pulse train using variously unused pins on the + * board for PWM output (see board.h for details of pins). + */ + +#ifdef CONFIG_PWM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM3240G_EVAL_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_PWM */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c new file mode 100644 index 0000000000000..e8ec7732462ec --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 +#define LCD_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin Usage (per schematic) + * SRAM LCD + * D[0..15] [0..15] [0..15] + * A[0..25] [0..22] [0] RS + * FSMC_NBL0 PE0 OUT --- --- + * FSMC_NBL1 PE1 OUT --- --- + * FSMC_NE2 PG9 OUT --- --- + * FSMC_NE3 PG10 OUT --- ~CS + * FSMC_NE4 PG12 OUT --- --- + * FSMC_NWE PD5 OUT --- ~WR/SCL + * FSMC_NOE PD4 OUT --- ~RD + * FSMC_NWAIT PD6 IN --- --- + * FSMC_INT2 PG6* IN --- --- + * FSMC_INT3 + * FSMC_INTR + * FSMC_CD + * FSMC_CLK + * FSMC_NCE2 + * FSMC_NCE3 + * FSMC_NCE4_1 + * FSMC_NCE4_2 + * FSMC_NIORD + * FSMC_NIOWR + * FSMC_NL + * FSMC_NREG + */ + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* NOE, NWE, and NE3 */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE3 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(LCD_NADDRLINES); /* Common address lines: A0 */ + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank3 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + + /* Bank3 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + + putreg32(0xffffffff, STM32_FSMC_BWTR3); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c new file mode 100644 index 0000000000000..2fd43e8b2fb50 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_FSMC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +/* SRAM Timing */ + +#define SRAM_ADDRESS_SETUP_TIME 3 +#define SRAM_ADDRESS_HOLD_TIME 1 +#define SRAM_DATA_SETUP_TIME 6 +#define SRAM_BUS_TURNAROUND_DURATION 1 +#define SRAM_CLK_DIVISION 1 +#define SRAM_DATA_LATENCY 2 + +/* SRAM pin definitions */ + +#define SRAM_NADDRLINES 21 +#define SRAM_NDATALINES 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIOs Configuration ****************************************************** + * PD0 <-> FSMC_D2 PE0 <-> FSMC_NBL0 PF0 <-> FSMC_A0 PG0 <-> FSMC_A10 + * PD1 <-> FSMC_D3 PE1 <-> FSMC_NBL1 PF1 <-> FSMC_A1 PG1 <-> FSMC_A11 + * PD4 <-> FSMC_NOE PE3 <-> FSMC_A19 PF2 <-> FSMC_A2 PG2 <-> FSMC_A12 + * PD5 <-> FSMC_NWE PE4 <-> FSMC_A20 PF3 <-> FSMC_A3 PG3 <-> FSMC_A13 + * PD8 <-> FSMC_D13 PE7 <-> FSMC_D4 PF4 <-> FSMC_A4 PG4 <-> FSMC_A14 + * PD9 <-> FSMC_D14 PE8 <-> FSMC_D5 PF5 <-> FSMC_A5 PG5 <-> FSMC_A15 + * PD10 <-> FSMC_D15 PE9 <-> FSMC_D6 PF12 <-> FSMC_A6 PG9 <-> FSMC_NE2 + * PD11 <-> FSMC_A16 PE10 <-> FSMC_D7 PF13 <-> FSMC_A7 + * PD12 <-> FSMC_A17 PE11 <-> FSMC_D8 PF14 <-> FSMC_A8 + * PD13 <-> FSMC_A18 PE12 <-> FSMC_D9 PF15 <-> FSMC_A9 + * PD14 <-> FSMC_D0 PE13 <-> FSMC_D10 + * PD15 <-> FSMC_D1 PE14 <-> FSMC_D11 + * PE15 <-> FSMC_D12 + */ + +/* GPIO configurations unique to SRAM */ + +static const uint32_t g_sramconfig[] = +{ + /* NE3, NBL0, NBL1, */ + + GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NBL0, GPIO_FSMC_NBL1, GPIO_FSMC_NE2 +}; +#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_selectsram + * + * Description: + * Initialize to access external SRAM. SRAM will be visible at the FSMC + * Bank NOR/SRAM2 base address (0x64000000) + * + * General transaction rules. The requested AHB transaction data size can + * be 8-, 16- or 32-bit wide whereas the SRAM has a fixed 16-bit data + * width. Some simple transaction rules must be followed: + * + * Case 1: AHB transaction width and SRAM data width are equal + * There is no issue in this case. + * Case 2: AHB transaction size is greater than the memory size + * In this case, the FSMC splits the AHB transaction into smaller + * consecutive memory accesses in order to meet the external data width. + * Case 3: AHB transaction size is smaller than the memory size. + * SRAM supports the byte select feature. + * a) FSMC allows write transactions accessing the right data through its + * byte lanes (NBL[1:0]) + * b) Read transactions are allowed (the controller reads the entire + * memory word and uses the needed byte only). The NBL[1:0] are always + * kept low during read transactions. + * + ****************************************************************************/ + +void stm32_selectsram(void) +{ + /* Configure new GPIO pins */ + + stm32_extmemaddr(SRAM_NADDRLINES); /* Common address lines: A0-A20 */ + stm32_extmemdata(SRAM_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG); /* SRAM-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Bank1 NOR/SRAM control register configuration + * + * Bank enable : Not yet + * Data address mux : Disabled + * Memory Type : PSRAM + * Data bus width : 16-bits + * Flash access : Disabled + * Burst access mode : Disabled + * Polarity : Low + * Wrapped burst mode : Disabled + * Write timing : Before state + * Write enable : Yes + * Wait signal : Disabled + * Extended mode : Disabled + * Asynchronous wait : Disabled + * Write burst : Disabled + */ + + putreg32((FSMC_BCR_PSRAM | FSMC_BCR_MWID16 | + FSMC_BCR_WREN), STM32_FSMC_BCR2); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32((FSMC_BTR_ADDSET(SRAM_ADDRESS_SETUP_TIME) | + FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) | + FSMC_BTR_DATAST(SRAM_DATA_SETUP_TIME) | + FSMC_BTR_BUSTURN(SRAM_BUS_TURNAROUND_DURATION) | + FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) | + FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) | + FSMC_BTR_ACCMODA), + STM32_FSMC_BTR2); + + /* Bank1 NOR/SRAM timing register for write configuration, + * if extended mode is used + */ + + putreg32(0xffffffff, STM32_FSMC_BWTR2); /* Extended mode not used */ + + /* Enable the bank */ + + putreg32((FSMC_BCR_MBKEN | FSMC_BCR_PSRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN), STM32_FSMC_BCR2); +} + +#endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c new file mode 100644 index 0000000000000..b14ec2bd65965 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the STM3240G-EVAL + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..ec55412bec3fb --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm3240g-eval.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C1 +# error "STMPE811 support requires CONFIG_STM32_I2C1" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 1 +#endif + +#if CONFIG_STMPE811_I2CDEV != 1 +# error "CONFIG_STMPE811_I2CDEV must be one" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. + * They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and + * loss-of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. + * We will use it when EXTI interruptsare enabled + */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c new file mode 100644 index 0000000000000..9f7e3c0c97c6c --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c @@ -0,0 +1,304 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm3240g-eval.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 50 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# ifdef CONFIG_USBHOST_HUB +# define CONFIG_USBHOST_STACKSIZE 1536 +# else +# define CONFIG_USBHOST_STACKSIZE 1024 +# endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM3240G-EVAL board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c new file mode 100644 index 0000000000000..48f0eb969509f --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm3240g-eval.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt new file mode 100644 index 0000000000000..ef6c336e42215 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f401rc-rs485/Kconfig b/boards/arm/stm32f4/stm32f401rc-rs485/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f401rc-rs485/Kconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/Kconfig diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig new file mode 100644 index 0000000000000..18ba4c3363436 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig new file mode 100644 index 0000000000000..702fd4ebb5f16 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BMP280_I2C_ADDR_77=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BMP280=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP280=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig new file mode 100644 index 0000000000000..dfa0032c87be6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_PWM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig new file mode 100644 index 0000000000000..20321b364cd5f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_HCSR04=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FREERUN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..9e5dd06e38d92 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_SLCD=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_BACKPACK=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig new file mode 100644 index 0000000000000..ab31f55aabe59 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_LM75=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_LM75=y +CONFIG_SYSTEM_LM75_CELSIUS=y +CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig new file mode 100644 index 0000000000000..71205dd34696a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NX_DISABLE_1BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAX7219=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig new file mode 100644 index 0000000000000..bd6c560ffa67a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CL_MFRC522=y +CONFIG_DRIVERS_CONTACTLESS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_RFID_READUID=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig new file mode 100644 index 0000000000000..09aa15441b04a --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUSMASTER=y +CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_MASTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MB_RTU_MASTER=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig new file mode 100644 index 0000000000000..54650ba01e5ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_ASCII_ENABLED is not set +# CONFIG_MB_TCP_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUS=y +CONFIG_EXAMPLES_MODBUS_PORT=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_SLAVE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig new file mode 100644 index 0000000000000..6579a60a22385 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig new file mode 100644 index 0000000000000..6e145c65d59b9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_QENCODER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig new file mode 100644 index 0000000000000..be5813d65a637 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig @@ -0,0 +1,87 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig new file mode 100644 index 0000000000000..cd419b48e967e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig new file mode 100644 index 0000000000000..d9828a3ad379c --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_FB=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DD12864WO4A=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig new file mode 100644 index 0000000000000..303875d809fa1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SYSTEM_TELNETD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_TELNETD=y +CONFIG_EXAMPLES_TELNETD_DRIPADDR=0xC0A80101 +CONFIG_EXAMPLES_TELNETD_IPADDR=0xC0A80102 +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_DRIPADDR=0xC0A80101 +CONFIG_NETINIT_IPADDR=0xC0A80102 +CONFIG_NETINIT_NETMASK=0xFFFFFF00 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..95f8b90b02a9e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..594ab62510eef --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig new file mode 100644 index 0000000000000..260bbbe3bf96f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_WS2812=y +CONFIG_EXAMPLES_WS2812_DEFAULT_DEV="/dev/leddrv0" +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_WS2812=y +CONFIG_WS2812_FREQUENCY=9000000 +CONFIG_WS2812_LED_COUNT=10 diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h new file mode 100644 index 0000000000000..4225ee4db7475 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h @@ -0,0 +1,470 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F401RC-RS485 uses an external 32kHz crystal (X2) to enable HSE + * clock. + * + * System Clock source : PLL (HSI) + * SYSCLK(Hz) : 84000000 Determined by PLL + * configuration + * HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 16 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - not installed + * LSE - not installed + */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_BOARD_USEHSI 1 + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz. + * Some possible solutions include: + * + * PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000 + * PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000 + * + * We will configure like this + * + * PLL source is HSI + * PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN + * = (16,000,000 / 16) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 4 = 84,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 336,000,000 / 7 = 48,000,000 + * + * REVISIT: Trimming of the HSI is not yet supported. + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 84000000ul + +/* AHB clock (HCLK) is SYSCLK (84MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) + +/* Timers driven from APB2 will be twice PCLK2 */ + +/* REVISIT */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in + * the future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART2: + * RXD: PA3 CN4 pin 20 + * TXD: PA2 CN4 pin 18 + */ + +#ifdef CONFIG_USART2_RS485 + /* Lets use for RS485 */ + +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ + + /* RS485 DIR pin: PA1 */ + +# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) + +#endif + +/* USART6: + * RXD: PC7 CN2 pin 15 + * TXD: PC6 CN2 pin 17 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM3 CH1 on PA6. + */ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_1|GPIO_SPEED_50MHz) + +/* Quadrature Encoder + * + * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. + */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_1 + +/* HCSR04 driver */ + +/* Pins config to use with HC-SR04 sensor */ + +#define GPIO_HCSR04_INT (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN1) +#define GPIO_HCSR04_TRIG (GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN0) + +#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT +#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG +#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2|GPIO_SPEED_50MHz) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* MAX7219 */ + +#define STM32_LCD_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) + +/* MFRC522 */ + +#define GPIO_RFID_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) + +/* MAX31855 */ + +#define GPIO_MAX31855_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN4) + +/* MAX6675 */ + +#define GPIO_MAX6675_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5) +/* LEDs + * + * The STM32F401RC-RS485 boards provide 4 blue user LEDs. LD1, LD2, LD3 + * and LD4 that are connected to MCU I/O pins PC0, PC1, PC2 and PC3. + * - When the I/O is HIGH value, the LED is on. + * - When the I/O is LOW, the LED is off. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD1 0 +#define BOARD_LD2 1 +#define BOARD_LD3 2 +#define BOARD_LD4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LD1) +#define BOARD_LED2_BIT (1 << BOARD_LD2) +#define BOARD_LED3_BIT (1 << BOARD_LD3) +#define BOARD_LED4_BIT (1 << BOARD_LD4) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related + * events as follows when the red LED (PE24) is available: + * + * SYMBOL Meaning LD2 + * ------------------- ----------------------- ----------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE MCU is in sleep mode Not used + * + * Thus if LD2, NuttX has successfully booted and is, apparently, running + * normally. If LD2 is flashing at approximately 2Hz, then a fatal error + * has been detected and the system has halted. + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Buttons + * The STM32F401RC-RS485 has 3 user buttons: SW3, SW4, and SW5. + * They are connected to PB13, PB14, and PB15 respectively. + */ + +#define BUTTON_SW3 0 +#define BUTTON_SW4 1 +#define BUTTON_SW5 2 +#define NUM_BUTTONS 3 + +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) +#define BUTTON_SW4_BIT (1 << BUTTON_SW4) +#define BUTTON_SW5_BIT (1 << BUTTON_SW5) + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP | GPIO_SPEED_50MHz) + +/* Stepper Motor - DRV8266 */ + +#define GPIO_DIR (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7) +#define GPIO_STEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN4) +#define GPIO_SLEEP (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN5) + +#define GPIO_M1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0) +#define GPIO_M2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1) +#define GPIO_M3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN2) + +#define GPIO_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32F401RC_RS485_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs new file mode 100644 index 0000000000000..51422c125e678 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32F401RC),y) +LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) + +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script new file mode 100644 index 0000000000000..fc6386990b81e --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F401RC has 256Kb of FLASH beginning at address 0x0800:0000 and + * 64Kb of SRAM beginning at address 0x2000:0000. When booting from FLASH, + * FLASH memory is aliased to address 0x0000:0000 where the code expects to + * begin execution by jumping to the entry point in the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + /* The STM32F401RC has 128Kb of SRAM beginning at the following address */ + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt new file mode 100644 index 0000000000000..64b46b4813d14 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt @@ -0,0 +1,86 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_USERLED) + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32_CONFIG_I2C_EE_24XXEEPROM) + list(APPEND SRCS stm32_at24.c) +endif() + +if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_VIDEO_FB) + if(CONFIG_LCD_SSD1306) + list(APPEND SRCS stm32_lcd_ssd1306.c) + endif() + if(CONFIG_LCD_ST7735) + list(APPEND SRCS stm32_lcd_st7735.c) + endif() +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32F401RC) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") +endif() diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs new file mode 100644 index 0000000000000..04f89e99e4f6d --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs @@ -0,0 +1,86 @@ +############################################################################ +# boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_VIDEO_FB),y) + ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c + endif + ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += stm32_lcd_st7735.c + endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_USERLED),y) +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_I2C_EE_24XX),y) +CSRCS += stm32_at24.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) +CSRCS += stm32_hx711.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c new file mode 100644 index 0000000000000..538937c28d15d --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 2 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +/* There are two trimpots on the board connected to ADC1_IN0 and ADC1_IN4 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 4 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC\1_IN\2_0, + GPIO_ADC\1_IN\2_0 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c new file mode 100644 index 0000000000000..8cad42b70a299 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AT24_I2C_BUS 1 /* EEPROM chip is configured to use I2C1 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_init + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_init(char *path) +{ + struct i2c_master_s *i2c; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + ret = ee24xx_initialize(i2c, 0x50, path, EEPROM_AT24CM02, false); + if (ret < 0) + { + ferr("ERROR: Failed to bind I2C%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c new file mode 100644 index 0000000000000..1d02e1f7d139b --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#include + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LD2 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == 1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c new file mode 100644 index 0000000000000..eb622ee8ac4fa --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include + +#include "arm_internal.h" +#include "stm32f401rc-rs485.h" + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif + + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c new file mode 100644 index 0000000000000..61d5448a187f3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c @@ -0,0 +1,405 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#include "stm32f401rc-rs485.h" + +#include + +#ifdef CONFIG_SENSORS_LM75 +#include "stm32_lm75.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_SENSORS_HCSR04 +#include "stm32_hcsr04.h" +#endif + +#ifdef CONFIG_LCD_MAX7219 +#include "stm32_max7219_matrix.h" +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#ifdef CONFIG_STEPPER_DRV8825 +#include "stm32_drv8266.h" +#endif + +#ifdef CONFIG_SENSORS_BMP280 +#include "stm32_bmp280.h" +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_WS2812 +#include "stm32_ws2812.h" +#endif + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_SENSORS_MAX31855 +#include "stm32_max31855.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_SENSORS_MAX31855 + /* Register device 0 on spi channel 1 */ + + ret = board_max31855_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: stm32_max31855initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: stm32_max6675initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_I2C_EE_24XX + ret = stm32_at24_init("/dev/eeprom"); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize EEPROM HX24LCXXB: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_LM75_I2C + /* Configure and initialize the LM75 sensor */ + + ret = board_lm75_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_MAX7219 + /* Configure and initialize the MAX7219 driver */ + + ret = board_max7219_matrix_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, \ + "ERROR: board_max7219_matrix_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD driver: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, STM32F401RCRS485_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_SENSORS_HCSR04 + /* Configure and initialize the HC-SR04 distance sensor */ + + ret = board_hcsr04_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STEPPER_DRV8825 + /* Configure and initialize the drv8825 driver */ + + ret = board_drv8825_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_drv8825_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP280 + /* Initialize the BMP280 pressure sensor. */ + + ret = board_bmp280_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP280, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_WS2812) && defined(CONFIG_WS2812_LED_COUNT) + /* Configure and initialize the WS2812 LEDs. */ + + ret = board_ws2812_initialize(0, WS2812_SPI, CONFIG_WS2812_LED_COUNT); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ws2812_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + /* Initialize GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_gpio_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c new file mode 100644 index 0000000000000..9ab473a526722 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F401RC RS485 button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c new file mode 100644 index 0000000000000..0cfe7d24a6755 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c @@ -0,0 +1,343 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; +#endif + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c new file mode 100644 index 0000000000000..772a358f7d521 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..2bb64bfa1a2b5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + /* Initialize the RESET and DC pins */ + + stm32_configgpio(GPIO_LCD_RESET); + stm32_configgpio(GPIO_LCD_DC); + + /* Reset the OLED display */ + + stm32_gpiowrite(GPIO_LCD_RESET, 0); + up_mdelay(1); + stm32_gpiowrite(GPIO_LCD_RESET, 1); + up_mdelay(120); + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c index 876e5b82346dc..bffad71e473ac 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c new file mode 100644 index 0000000000000..2579135afcf3b --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c @@ -0,0 +1,121 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH1. + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F401RCRS485_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F401RCRS485_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c new file mode 100644 index 0000000000000..5e24309298006 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c new file mode 100644 index 0000000000000..959cc8637dbc5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c new file mode 100644 index 0000000000000..eef9dbcd0701f --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f401rc-rs485 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + stm32_configgpio(GPIO_LCD_CS); /* LCD chip select */ +#endif + +#ifdef CONFIG_LCD_MAX7219 + stm32_configgpio(STM32_LCD_CS); /* MAX7219 chip select */ +#endif + +#ifdef CONFIG_CL_MFRC522 + stm32_configgpio(GPIO_RFID_CS); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX31855) + stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MAX66755) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + #if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_LCD_CS, !selected); + } + #endif + + #ifdef CONFIG_LCD_MAX7219 + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } + #endif + + #if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_RFID_CS, !selected); + } + #endif + + #if defined(CONFIG_SENSORS_MAX31855) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX31855_CS, !selected); + } + #endif + + #if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } + #endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306) || defined(CONFIG_LCD_ST7735) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(GPIO_LCD_DC, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c new file mode 100644 index 0000000000000..c9ad90a99763c --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_otgfs.h" +#include "stm32_gpio.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* We don´t have the OTG FS VBUS sensing GPIO */ +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..506a30b7e7937 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_mmcsd_initialize(port, CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c new file mode 100644 index 0000000000000..7b97b71c8ece8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h index b8fbec7e25a6d..f6065bbdb8c63 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt new file mode 100644 index 0000000000000..f4b26f4eddd51 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f4/stm32f411-minimum/Kconfig b/boards/arm/stm32f4/stm32f411-minimum/Kconfig new file mode 100644 index 0000000000000..44ee6a9040708 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/Kconfig @@ -0,0 +1,86 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_STM32F411_MINIMUM + +config STM32F411MINIMUM_USBHOST_STACKSIZE + int "USB host waiter stack size" + default 1024 + depends on USBHOST + +config STM32F411MINIMUM_USBHOST_PRIO + int "USB host waiter task priority" + default 100 + depends on USBHOST + +config STM32F411MINIMUM_FLASH + bool "MTD driver for external 8Mbyte W25Q64FV FLASH on SPI1" + default n + select MTD + select MTD_W25 + select MTD_SMART + select FS_SMARTFS + select STM32_SPI1 + select MTD_BYTE_WRITE + ---help--- + Configures an MTD device for use with the onboard flash + +config STM32F411MINIMUM_FLASH_MINOR + int "Minor number for the FLASH /dev/smart entry" + default 0 + depends on STM32F411MINIMUM_FLASH + ---help--- + Sets the minor number for the FLASH MTD /dev entry + +menuconfig STM32F411MINIMUM_HX711 + bool "Enable hx711 scale sensor" + default n + select ADC_HX711 + +if STM32F411MINIMUM_HX711 + +choice + prompt "Select GPIO port for clock pin" + default STM32F411MINIMUM_HX711_CLK_PORTA + +config STM32F411MINIMUM_HX711_CLK_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_CLK_PORTB + bool "Port B" + +endchoice # Select GPIO port for clock pin + +config STM32F411MINIMUM_HX711_CLK_PIN + int "Select GPIO pin number for clock pin" + default 1 + range 0 15 + +choice + prompt "Select GPIO port for data pin" + default STM32F411MINIMUM_HX711_DATA_PORTA + +config STM32F411MINIMUM_HX711_DATA_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_DATA_PORTB + bool "Port B" + +endchoice # Select GPIO port for data pin + +config STM32F411MINIMUM_HX711_DATA_PIN + int "Select GPIO pin number for data pin" + default 2 + range 0 15 + +endif # STM32F411MINIMUM_HX711 + +menuconfig STM32F411MINIMUM_GPIO + select DEV_GPIO + bool "enable gpio subsystem" + +if STM32F411MINIMUM_GPIO +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio" +endif + +endif diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio b/boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio similarity index 100% rename from boards/arm/stm32/stm32f411-minimum/Kconfig.gpio rename to boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig new file mode 100644 index 0000000000000..f7e74ef5eb194 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_COMPOSITE_IAD=y +CONFIG_COMPOSITE_PRODUCTID=0x2022 +CONFIG_COMPOSITE_VENDORID=0x03eb +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig new file mode 100644 index 0000000000000..6d7961ef2fa3c --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig new file mode 100644 index 0000000000000..6d7545748b8b7 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PWM=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig new file mode 100644 index 0000000000000..cadadfaea585d --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2020 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CHMODE=0 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_CHMODE=0 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_CHMODE=0 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH4OUT=y +CONFIG_STM32_TIM4_CHANNEL=4 +CONFIG_STM32_TIM4_CHMODE=0 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig new file mode 100644 index 0000000000000..d9edd314500c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..825535f82171a --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411-minimum" +CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_STM32F411MINIMUM_FLASH=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_FLASH_PREFETCH=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/smart0" +CONFIG_TASK_NAME_SIZE=15 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBMSC=y diff --git a/boards/arm/stm32f4/stm32f411-minimum/include/board.h b/boards/arm/stm32f4/stm32f411-minimum/include/board.h new file mode 100644 index 0000000000000..c90a3ade986b2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/include/board.h @@ -0,0 +1,363 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* System Clock source : PLLCLK (HSE) + * SYSCLK(Hz) : 96000000 Determined by PLL config + * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 4 (STM32_PLLCFG_PLLM) + * PLLN : 192 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 25 MHz Crystal + * LSE - 32 KHz Crystal + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input freq = PLL input clock freq/PLLM 2 <= PLLM <= 63 + * VCO output freq = VCO input freq × PLLN, 192 <= PLLN <= 432 + * PLL output clock freq = VCO freq / PLLP, PLLP = 2,4,6 or 8 + * USB OTG FS clock freq = VCO freq / PLLQ, 2 <= PLLQ <= 15 + * + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=96MHz and we must have the USB + * clock = 48MHz + * + * PLLQ = 2 PLLP = 2 PLLN=192 PLLM=25 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 25) * 192 + * = 192,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 192,000,000 / 2 = 96,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 96,000,000 / 2 = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(2) + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM4 CH2 on PD13. + */ +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) //PA8 +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) //PA1 +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) //PB0 +#define GPIO_TIM4_CH4OUT (GPIO_TIM4_CH4OUT_1|GPIO_SPEED_50MHz) //PB9 + +/* RGB LED + * + * R = TIM1 CH1 on PA8 | G = TIM2 CH2 on PA1 | B = TIM4 CH4 on PB9 + * + * Note: Pin boards: GPIO_TIM1_CH1OUT ; GPIO_TIM2_CH2OUT ; GPIO_TIM4_CH4OUT + */ + +#define RGBLED_RPWMTIMER 1 +#define RGBLED_RPWMCHANNEL 1 +#define RGBLED_GPWMTIMER 2 +#define RGBLED_GPWMCHANNEL 2 +#define RGBLED_BPWMTIMER 4 +#define RGBLED_BPWMCHANNEL 4 + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The STM32F411-Minimum (aka BlackPill) has a LED on PC13 pin. + */ + +/* The board has only one controllable LED */ + +#define LED_STARTED 0 /* No LEDs */ +#define LED_HEAPALLOCATE 1 /* LED1 on */ +#define LED_IRQSENABLED 2 /* LED1 on */ +#define LED_STACKCREATED 3 /* LED1 on */ +#define LED_INIRQ 4 /* LED1 on */ +#define LED_SIGNAL 5 /* LED1 on */ +#define LED_ASSERTION 6 /* LED1 on */ +#define LED_PANIC 7 /* LED1 blinking */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PA0 of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define BUTTON_EXTERNAL 1 //External user button connected to PA1 +#define NUM_BUTTONS 2 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) +#define BUTTON_EXTERNAL_BIT (1 << BUTTON_EXTERNAL) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs new file mode 100644 index 0000000000000..15e53eadfbdfe --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = stm32f411ce.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld rename to boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld index b5b77c8a49bb2..58afcc5198500 100644 --- a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld + * boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt new file mode 100644 index 0000000000000..0b5473d5b55e5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt @@ -0,0 +1,76 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +endif() + +if(CONFIG_USERLED) + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_MTD_W25) + list(APPEND SRCS stm32_w25.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +if(CONFIG_STM32F411MINIMUM_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32f411ce.ld") diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs new file mode 100644 index 0000000000000..dcda7c6643082 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411-minimum/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +endif + +ifeq ($(CONFIG_USERLED),y) + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_PWM),y) + CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_RGBLED),y) + CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) + CSRCS += stm32_hx711.c +endif + +ifeq ($(CONFIG_SPI),y) + CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32F411MINIMUM_GPIO),y) + CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_MTD_W25),y) + CSRCS += stm32_w25.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) + CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) + CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c new file mode 100644 index 0000000000000..5287975f236a5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LED1, !v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + /* As the board provides only one soft controllable LED, we simply + * turn it on when the board boots. + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c new file mode 100644 index 0000000000000..4bc171dc6a8a4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c new file mode 100644 index 0000000000000..9264b917c7dfe --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by W25 Flash */ + +#define HAVE_W25 1 + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# undef HAVE_W25 +#endif + +/* Default W25 minor number */ + +#if defined(HAVE_W25) && !defined(CONFIG_NSH_W25MINOR) +# define CONFIG_NSH_W25MINOR 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure and initialize the RGB LED. */ + + ret = stm32_rgbled_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_rgbled_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO + ret = stm32_gpio_initialize(); + if (ret != OK) + { + gerr("ERROR: Failed to initialize gpio: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_W25 + /* Initialize and register the W25 FLASH file system. */ + + ret = stm32_w25initialize(CONFIG_NSH_W25MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize W25 minor %d: %d\n", + CONFIG_NSH_W25MINOR, ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c new file mode 100644 index 0000000000000..4ccae3e1a4d96 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER, GPIO_BTN_EXTERNAL +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c new file mode 100644 index 0000000000000..88e53ea4840ab --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c @@ -0,0 +1,278 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/smart0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/smart0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/smart0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + /* Here we are composing the configuration of the usb composite device. + * + * The standard is to use one CDC/ACM and one USB mass storage device. + */ + + if (configid == 0) + { + struct composite_devdesc_s dev[2]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int dev_idx = 0; + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[dev_idx].classobject = board_mscclassobject; + dev[dev_idx].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 3; + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 3; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + dev_idx++; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[dev_idx].classobject = cdcacm_classobject; + dev[dev_idx].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = 1; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 2; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 2; + dev_idx++; +#endif + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); + } + else + { + return NULL; + } +} + +#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c new file mode 100644 index 0000000000000..d7b499aaa79d3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c @@ -0,0 +1,741 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +struct stm32gpio_info_s +{ + uint32_t pin; + const char *pinname; /* Holds pin name like gpio_a0, gpio_custom_name */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIO_IN]; +static const struct stm32gpio_info_s g_gpio_inputs[BOARD_NGPIO_IN] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_IN + { .pin = GPIO_A0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_IN + { .pin = GPIO_A1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_IN + { .pin = GPIO_A2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_IN + { .pin = GPIO_A3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_IN + { .pin = GPIO_A4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_IN + { .pin = GPIO_A5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_IN + { .pin = GPIO_A6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_IN + { .pin = GPIO_A7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_IN + { .pin = GPIO_A8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_IN + { .pin = GPIO_A9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_IN + { .pin = GPIO_A10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_IN + { .pin = GPIO_A11_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_IN + { .pin = GPIO_A12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_IN + { .pin = GPIO_A15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_IN + { .pin = GPIO_B0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_IN + { .pin = GPIO_B1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_IN + { .pin = GPIO_B2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_IN + { .pin = GPIO_B3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_IN + { .pin = GPIO_B4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_IN + { .pin = GPIO_B5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_IN + { .pin = GPIO_B6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_IN + { .pin = GPIO_B7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_IN + { .pin = GPIO_B8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_IN + { .pin = GPIO_B9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_IN + { .pin = GPIO_B10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_IN + { .pin = GPIO_B12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_IN + { .pin = GPIO_B13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_IN + { .pin = GPIO_B14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_IN + { .pin = GPIO_B15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_IN + { .pin = GPIO_C13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_IN + { .pin = GPIO_C14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_IN + { .pin = GPIO_C15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_IN > 0 */ + +#if BOARD_NGPIO_OUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIO_OUT]; +static const struct stm32gpio_info_s g_gpio_outputs[BOARD_NGPIO_OUT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_OUT + { .pin = GPIO_A0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_OUT + { .pin = GPIO_A1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_OUT + { .pin = GPIO_A2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_OUT + { .pin = GPIO_A3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_OUT + { .pin = GPIO_A4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_OUT + { .pin = GPIO_A5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_OUT + { .pin = GPIO_A6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_OUT + { .pin = GPIO_A7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_OUT + { .pin = GPIO_A8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_OUT + { .pin = GPIO_A9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_OUT + { .pin = GPIO_A10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_OUT + { .pin = GPIO_A11_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_OUT + { .pin = GPIO_A12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_OUT + { .pin = GPIO_A15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_OUT + { .pin = GPIO_B0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_OUT + { .pin = GPIO_B1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_OUT + { .pin = GPIO_B2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_OUT + { .pin = GPIO_B3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_OUT + { .pin = GPIO_B4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_OUT + { .pin = GPIO_B5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_OUT + { .pin = GPIO_B6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_OUT + { .pin = GPIO_B7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_OUT + { .pin = GPIO_B8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_OUT + { .pin = GPIO_B9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_OUT + { .pin = GPIO_B10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_OUT + { .pin = GPIO_B12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_OUT + { .pin = GPIO_B13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_OUT + { .pin = GPIO_B14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_OUT + { .pin = GPIO_B15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_OUT + { .pin = GPIO_C13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_OUT + { .pin = GPIO_C14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_OUT + { .pin = GPIO_C15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_OUT > 0 */ + +#if BOARD_NGPIO_INT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIO_INT]; +static const struct stm32gpio_info_s g_gpio_int_inputs[BOARD_NGPIO_INT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_INT + { .pin = GPIO_A0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_INT + { .pin = GPIO_A1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_INT + { .pin = GPIO_A2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_INT + { .pin = GPIO_A3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_INT + { .pin = GPIO_A4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_INT + { .pin = GPIO_A5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_INT + { .pin = GPIO_A6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_INT + { .pin = GPIO_A7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_INT + { .pin = GPIO_A8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_INT + { .pin = GPIO_A9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_INT + { .pin = GPIO_A10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_INT + { .pin = GPIO_A11_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_INT + { .pin = GPIO_A12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_INT + { .pin = GPIO_A15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_INT + { .pin = GPIO_B0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_INT + { .pin = GPIO_B1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_INT + { .pin = GPIO_B2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_INT + { .pin = GPIO_B3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_INT + { .pin = GPIO_B4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_INT + { .pin = GPIO_B5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_INT + { .pin = GPIO_B6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_INT + { .pin = GPIO_B7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_INT + { .pin = GPIO_B8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_INT + { .pin = GPIO_B9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_INT + { .pin = GPIO_B10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_INT + { .pin = GPIO_B12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_INT + { .pin = GPIO_B13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_INT + { .pin = GPIO_B14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_INT + { .pin = GPIO_B15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_INT + { .pin = GPIO_C13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_INT + { .pin = GPIO_C14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_INT + { .pin = GPIO_C15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_INT > 0 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_IN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_inputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_outputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpio_outputs[stm32gpio->id].pin, value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIO_INT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + +#if BOARD_NGPIO_IN > 0 + for (i = 0; i < BOARD_NGPIO_IN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register_byname(&g_gpin[i].gpio, g_gpio_inputs[i].pinname); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpio_inputs[i].pin); + } +#endif + +#if BOARD_NGPIO_OUT > 0 + for (i = 0; i < BOARD_NGPIO_OUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register_byname(&g_gpout[i].gpio, g_gpio_outputs[i].pinname); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpio_outputs[i].pin, 0); + stm32_configgpio(g_gpio_outputs[i].pin); + } +#endif + +#if BOARD_NGPIO_INT > 0 + for (i = 0; i < BOARD_NGPIO_INT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register_byname(&g_gpint[i].stm32gpio.gpio, + g_gpio_int_inputs[i].pinname); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpio_int_inputs[i].pin); + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c new file mode 100644 index 0000000000000..65db25d28fe38 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c new file mode 100644 index 0000000000000..284affc8fbb0e --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f411-minimum has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connect to CN5 just for this purpose: + * + * PB0 ADC12_IN8/TIM3_CH3 + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F411MINIMUM_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F411MINIMUM_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c new file mode 100644 index 0000000000000..e142de19b15eb --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_RGBLED +#endif + +#if CONFIG_STM32_TIM1_CHANNEL != RGBLED_RPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM2_CHANNEL != RGBLED_GPWMCHANNEL +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != RGBLED_BPWMCHANNEL +# undef HAVE_PWM +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Initial for support of a connected RGB LED using PWM. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(RGBLED_RPWMTIMER); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(RGBLED_GPWMTIMER); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(RGBLED_BPWMTIMER); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c new file mode 100644 index 0000000000000..43347015546e1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c @@ -0,0 +1,175 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins + * for the WeAct Studio MiniF4 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI2 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_MTD_W25 + stm32_configgpio(FLASH_SPI1_CS); /* FLASH chip select */ +#endif + +#ifdef CONFIG_MMCSD_SPI + stm32_configgpio(GPIO_SDCARD_CS); /* SD/MMC Card chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2select and stm32_spi1/2status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SDCARD_CS, !selected); + } +#endif + +#ifdef CONFIG_MTD_W25 + stm32_gpiowrite(FLASH_SPI1_CS, !selected); +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_MMCSD_SPI + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, + bool cmd) +{ + return -ENODEV; +} +#endif +#endif + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c new file mode 100644 index 0000000000000..ff842eb11b4d1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c @@ -0,0 +1,329 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f411-minimum.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411MINIMUM_USBHOST_PRIO +# define CONFIG_STM32F411MINIMUM_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE +# define CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_boardinitialize very early in initialization to setup + * USB-related GPIO pins for the WeAct Studio MiniF4 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is + * required + * This board has no connections for VBUS, Power On, or Overcurrent + * GPIOs + */ +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411MINIMUM_USBHOST_PRIO, + CONFIG_STM32F411MINIMUM_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge + * pump or, if 5 V are available on the application board, a basic power + * switch, must be added externally to drive the 5 V VBUS line. The + * external charge pump can be driven by any GPIO output. When the + * application decides to power on VBUS using the chosen GPIO, it must + * also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the + * core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition + * is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..14890201cacb6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_w25initialize(CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c new file mode 100644 index 0000000000000..660ef135af9ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c new file mode 100644 index 0000000000000..e2c0ce64a4715 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_STM32_SPI1 +# include +# include +# include +# include +#endif + +#include "stm32_spi.h" + +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Debug ********************************************************************/ + +/* Non-standard debug that may be enabled just for testing the watchdog + * timer + */ + +#define W25_SPI_PORT 1 + +/* Configuration ************************************************************/ + +/* Can't support the W25 device if it SPI1 or W25 support is not enabled */ + +#define HAVE_W25 1 +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_W25) +# undef HAVE_W25 +#endif + +/* Can't support W25 features if mountpoints are disabled */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) +# undef HAVE_W25 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25initialize + * + * Description: + * Initialize and register the W25 FLASH file system. + * + ****************************************************************************/ + +int stm32_w25initialize(int minor) +{ + int ret; +#ifdef HAVE_W25 + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; + struct mtd_geometry_s geo; +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F411MINIMUM_FLASH_PART_NAMES; +#endif + + /* Get the SPI port */ + + spi = stm32_spibus_initialize(W25_SPI_PORT); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + W25_SPI_PORT); + return -ENODEV; + } + + /* Raise SPI frequency from default 400kHz to something usable + * SPI1 uses PCLK2 of 96MHz with DIV2 = 48Mbps max + * W25Q64 requires more dummy clocks above 26MHz + */ + + SPI_SETFREQUENCY(spi, 24000000); + + /* Now bind the SPI interface to the W25 SPI FLASH driver */ + + mtd = w25_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port %d to the Winbond" + "W25 FLASH driver\n", W25_SPI_PORT); + return -ENODEV; + } + +#ifndef CONFIG_FS_SMARTFS + /* Register the MTD driver */ + + char path[32]; + snprintf(path, sizeof(path), "/dev/mtdblock%d", minor); + ret = register_mtddriver(path, mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the MTD driver %s, ret %d\n", + path, ret); + return ret; + } +#else + /* Initialize to provide SMARTFS on the MTD interface */ + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F411MINIMUM_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_FS_SMARTFS */ +#endif /* HAVE_W25 */ + + return OK; +} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h index 1942732d68269..54b682fa67c7a 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h index 38d62a738ac44..fac30d9a1f9c1 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt new file mode 100644 index 0000000000000..7147e4505e556 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/Kconfig b/boards/arm/stm32f4/stm32f411e-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f411e-disco/Kconfig rename to boards/arm/stm32f4/stm32f411e-disco/Kconfig diff --git a/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..0a887cdf2dd11 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32_SYSCFG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f411e-disco" +CONFIG_ARCH_BOARD_STM32F411E_DISCO=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F411VE=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f411e-disco/include/board.h b/boards/arm/stm32f4/stm32f411e-disco/include/board.h new file mode 100644 index 0000000000000..ce8aadff51251 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/include/board.h @@ -0,0 +1,358 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* System Clock source : PLLCLK (HSE) + * SYSCLK(Hz) : 96000000 Determined by PLL + * configuration + * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSI Frequency(Hz) : 16000000 (nominal) + * PLLM : 4 (STM32_PLLCFG_PLLM) + * PLLN : 192 (STM32_PLLCFG_PLLN) + * PLLP : 4 (STM32_PLLCFG_PLLP) + * PLLQ : 8 (STM32_PLLCFG_PPQ) + * Flash Latency(WS) : 3 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - 8 MHz Crystal + * LSE - not installed + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL + +/* Main PLL Configuration. + * + * Formulae: + * + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 + * + * There is no config for 100 MHz and 48 MHz for usb, + * so we would like to have SYSYCLK=96MHz and we must have the + * USB clock= 48MHz. + * + * PLLQ = 8 PLLP = 4 PLLN=192 PLLM=4 + * + * We will configure like this + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 4) * 192 + * = 384,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 384,000,000 / 4 = 96,000,000 + * USB OTG FS and SDIO Clock + * = PLL_VCO / PLLQ + * = 384,000,000 / 8 = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(192) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8) + +#define STM32_SYSCLK_FREQUENCY 96000000ul + +/* AHB clock (HCLK) is SYSCLK (96MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (24MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +/* REVISIT */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK (48MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +/* REVISIT */ + +#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz + */ + +/* REVISIT */ + +#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz + * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz + */ + +/* REVISIT */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. + * + * SDIO DMA + *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA + *   DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* Need to VERIFY fwb */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * RXD: PA10 CN9 pin 3, CN10 pin 33 + * PB7 CN7 pin 21 + * TXD: PA9 CN5 pin 1, CN10 pin 21 + * PB6 CN5 pin 3, CN10 pin 17 + */ + +#if 1 +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) /* PA9 */ +#else +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) /* PB6 */ +#endif + +/* USART2: + * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 + * PD6 + * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 + * PD5 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_USART2_RTS GPIO_USART2_RTS_2 +#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + +/* USART6: + * RXD: PC7 CN5 pin2, CN10 pin 19 + * PA12 CN10, pin 12 + * TXD: PC6 CN10, pin 4 + * PA11 CN10, pin 14 + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 */ + +/* UART RX DMA configurations */ + +#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 +#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 + +/* I2C + * + * The optional _GPIO configurations allow the I2C driver to manually + * reset the bus to clear stuck slaves. They match the pin configuration, + * but are normally-high GPIOs. + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8) +#define GPIO_I2C1_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9) + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_1|GPIO_SPEED_50MHz) +#define GPIO_I2C2_SCL_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10) +#define GPIO_I2C2_SDA_GPIO \ + (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11) + +/* SPI + * + * There are sensors on SPI1, and SPI2 is connected to the FRAM. + */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz) + +/* LEDs + * + * The STM32F411E Discovery board has four user leds + * LD3 connected to PD13. + * LD4 connected to PD12. + * LD5 connected to PD14. + * LD6 connected to PD15. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LD3 0 +#define BOARD_LD4 1 +#define BOARD_LD5 2 +#define BOARD_LD6 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LD3_BIT (1 << BOARD_LD3) +#define BOARD_LD4_BIT (1 << BOARD_LD4) +#define BOARD_LD5_BIT (1 << BOARD_LD5) +#define BOARD_LD6_BIT (1 << BOARD_LD6) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board. + * The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED + * ------------------- ---------------------------- -------------------- + */ + +#define LED_STARTED 0 /* NuttX has been started None */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON(1), OFF(2) */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF(1), ON(2) */ +#define LED_STACKCREATED 3 /* Idle stack created ON(1), ON(2) */ +#define LED_INIRQ 4 /* In an interrupt (no change) */ +#define LED_SIGNAL 5 /* In a signal handler (no change) */ +#define LED_ASSERTION 6 /* An assertion failed ON(3) */ +#define LED_PANIC 7 /* The system has crashed FLASH(1,2) */ +#define LED_IDLE 8 /* idle loop FLASH(4) */ + +/* Buttons + * + * B1 USER: the user button is connected to the I/O PA0 of the STM32 + * microcontroller. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* USB OTG FS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F411E_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs new file mode 100644 index 0000000000000..6442599a8f6ac --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = f411ve.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld rename to boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld index 4f0e398e08585..a7ae15bdd1af0 100644 --- a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld + * boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..d92b2d6fbc12d --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f411ve.ld") diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs new file mode 100644 index 0000000000000..d979394c3dd7a --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/stm32f4/stm32f411e-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += stm32_autoleds.c +else + CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..532620b9c1434 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f411e-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD4); + stm32_configgpio(GPIO_LD5); + stm32_configgpio(GPIO_LD6); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case LED_HEAPALLOCATE: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, false); + } + break; + + case LED_IRQSENABLED: + { + stm32_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_STACKCREATED: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_ASSERTION: + { + stm32_gpiowrite(GPIO_LD5, true); + } + break; + + case LED_PANIC: + { + stm32_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD4, true); + } + break; + + case LED_IDLE: + { + stm32_gpiowrite(GPIO_LD6, true); + } + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + { + stm32_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD4, false); + } + break; + + case LED_IDLE: + { + stm32_gpiowrite(GPIO_LD6, false); + } + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..ba49ba9262d70 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f411e-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the + * weak function stm32_spidev_initialize() has been brought into the link. + */ + + stm32_spidev_initialize(); +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the OTG FS controller is in the configuration. + * Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also selected. + */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..8d104e05902f9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "stm32.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#include "stm32f411e-disco.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) + /* Initialize USB host operation. stm32_usbhost_initialize() starts + * a thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + ferr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c new file mode 100644 index 0000000000000..458b4443786f6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c @@ -0,0 +1,160 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411e-disco.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c new file mode 100644 index 0000000000000..3434d64f9eb48 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c @@ -0,0 +1,353 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. + * SPDX-FileCopyrightText: 2017 Brian Webb. All rights reserved. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: Brian Webb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f411e-disco.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV) && !defined(CONFIG_USBHOST) +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_PRIO +# define CONFIG_STM32F411DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F411DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F411DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F411 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F411DISCO_USBHOST_PRIO, + CONFIG_STM32F411DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c new file mode 100644 index 0000000000000..7a080b429835e --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411e-disco.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LD3, + GPIO_LD4, + GPIO_LD5, + GPIO_LD6, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED GPIOs for output */ + + for (i = 0; i < BOARD_NLEDS; i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h similarity index 99% rename from boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h index 993efb33dd7ba..625a7d463f336 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h + * boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt new file mode 100644 index 0000000000000..581e2ba994ac2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/Kconfig b/boards/arm/stm32f4/stm32f429i-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f429i-disco/Kconfig rename to boards/arm/stm32f4/stm32f429i-disco/Kconfig diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig new file mode 100644 index 0000000000000..7a06ad371b54a --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_CCMEXCLUDE is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig new file mode 100644 index 0000000000000..5610e2c3f0611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FBOVERLAY=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY_BLIT=y +CONFIG_FB_SYNC=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=7774208 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=128 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MAXARGUMENTS=17 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y +CONFIG_VIDEO_FB_SPLASHSCREEN=y +CONFIG_VIDEO_FB_SPLASHSCREEN_BPP16=y +CONFIG_VIDEO_FB_SPLASHSCREEN_DISP_TIME=2 diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig new file mode 100644 index 0000000000000..f35ce2450e611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MTD_CONFIG=y +CONFIG_MTD_CONFIG_RAM_CONSOLIDATE=y +CONFIG_MTD_PARTITION=y +CONFIG_MTD_PARTITION_NAMES=y +CONFIG_MTD_SMART_SECTOR_SIZE=512 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PLATFORM_CONFIGDATA=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MULTI_ROOT_DIRS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_FLASH=y +CONFIG_STM32F429I_DISCO_FLASH_PART=y +CONFIG_STM32F429I_DISCO_RAMMTD=y +CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig new file mode 100644 index 0000000000000..e61f766cb1fcb --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FBOVERLAY=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY_BLIT=y +CONFIG_FB_SYNC=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=7774208 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=128 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_MAXARGUMENTS=17 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig new file mode 100644 index 0000000000000..f44bd74c69d74 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LIBC_FLOATINGPOINT is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIB_GDBSTUB=y +CONFIG_LIB_GDBSTUB_DEBUG=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_GDBSTUB=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig new file mode 100644 index 0000000000000..24deb19b35120 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_NOOPT=y +CONFIG_HAVE_CXX=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="highpri_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_HIGHPRI=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_EXTSEL=y +CONFIG_STM32_ADC1_INJECTED_CHAN=1 +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_READLINE=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig new file mode 100644 index 0000000000000..dd6fdbb3aab40 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_ILI9341=y +CONFIG_LCD_ILI9341_IFACE0=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NX_BLOCKING=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y +CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig new file mode 100644 index 0000000000000..91927fed1227d --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_LV_BUILD_EXAMPLES is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_LVGLDEMO=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_FB_OVERLAY=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_LVGL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8081408 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y +CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2017 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI5=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig new file mode 100644 index 0000000000000..fec735c9fa5c8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig new file mode 100644 index 0000000000000..de8144a44945c --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FB_CMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEV_LOOP=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=16 +CONFIG_EXAMPLES_NXHELLO_SERVERPRIO=110 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NX_BLOCKING=y +CONFIG_NX_WRITEONLY=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=214688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2019 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA2D=y +CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000 +CONFIG_STM32_DMA2D_FB_SIZE=307200 +CONFIG_STM32_DMA2D_LAYER_PPLINE=240 +CONFIG_STM32_DMA2D_NLAYERS=2 +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD076A000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig new file mode 100644 index 0000000000000..571440c8d6748 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig @@ -0,0 +1,112 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_LTDC_L2 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FB_OVERLAY=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xd0000000 +CONFIG_HEAP2_SIZE=8081408 +CONFIG_INIT_ENTRYPOINT="nxwm_main" +CONFIG_INPUT=y +CONFIG_INPUT_STMPE811=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTERM=y +CONFIG_NXTERM_CACHESIZE=32 +CONFIG_NXTERM_CURSORCHAR=95 +CONFIG_NXTERM_MXCHARS=325 +CONFIG_NXTERM_NXKBDIN=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NXWIDGETS=y +CONFIG_NXWIDGETS_BPP=16 +CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y +CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y +CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb +CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618 +CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e +CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9 +CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf +CONFIG_NXWIDGETS_SIZEOFCHAR=1 +CONFIG_NXWM=y +CONFIG_NXWM_CALIBRATION_AVERAGE=y +CONFIG_NXWM_CALIBRATION_MESSAGES=y +CONFIG_NXWM_CALIBRATION_NSAMPLES=2 +CONFIG_NXWM_HEXCALCULATOR_CUSTOM_FONTID=y +CONFIG_NXWM_HEXCALCULATOR_FONTID=5 +CONFIG_NXWM_KEYBOARD=y +CONFIG_NXWM_TASKBAR_LEFT=y +CONFIG_NXWM_TASKBAR_VSPACING=4 +CONFIG_NXWM_TOUCHSCREEN_LISTENERSTACK=1596 +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_TOUCHSCREEN=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=11 +CONFIG_STM32F429I_DISCO_ILI9341=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xD07B5000 +CONFIG_STM32_LTDC_FB_SIZE=307200 +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STMPE811_ACTIVELOW=y +CONFIG_STMPE811_EDGE=y +CONFIG_STMPE811_THRESHX=39 +CONFIG_STMPE811_THRESHY=51 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig new file mode 100644 index 0000000000000..962af638709ee --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BCH=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRVR_MKRD=y +CONFIG_FRAME_POINTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYNAME="ofloader" +CONFIG_INIT_ENTRYPOINT="ofloader_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_MTD=y +CONFIG_MTD_PROGMEM=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FLASH_CONFIG_I=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_OFLOADER=y +CONFIG_SYSTEM_OFLOADER_BUFFERSIZE=4096 +CONFIG_SYSTEM_OFLOADER_DEBUG=y +CONFIG_SYSTEM_OFLOADER_TABLE="/dev/flash,0x08000000,0x20000" +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig new file mode 100644 index 0000000000000..00451cde08cf0 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INSTRUMENT_ALL=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_STACK_RECORD=32 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig new file mode 100644 index 0000000000000..03aff6f431858 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DRIVERS_NOTERAM is not set +# CONFIG_SERIAL_RTT_CONSOLE is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_NOTE=y +CONFIG_DRIVERS_NOTE_TASKNAME_BUFSIZE=0 +CONFIG_EXAMPLES_NOTEPRINTF=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_DUMP=y +CONFIG_SCHED_INSTRUMENTATION_HEAP=y +CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER=y +CONFIG_SCHED_INSTRUMENTATION_SWITCH=y +CONFIG_SCHED_INSTRUMENTATION_WDOG=y +CONFIG_SEGGER_SYSVIEW=y +CONFIG_SERIAL_RTT0=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_RTT=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TASK_NAME_SIZE=16 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..7e6ab150d4a6e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_STM32_FLASH_PREFETCH is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..0a13ff515396f --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f429i-disco" +CONFIG_ARCH_BOARD_STM32F429I_DISCO=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEV_LOOP=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP2_BASE=0xD0000000 +CONFIG_HEAP2_SIZE=8388608 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=3 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_RAMTEST=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f429i-disco/include/board.h b/boards/arm/stm32f4/stm32f429i-disco/include/board.h new file mode 100644 index 0000000000000..8d06febb0a6ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/include/board.h @@ -0,0 +1,540 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* DO NOT include STM32 internal header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F429I-DISCO board features a single 8MHz crystal. + * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 180000000 Determined by PLL + * configuration + * HCLK(Hz) : 180000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_NLEDS 2 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f429i-disco. + * The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F429I-DISCO supports one button: */ + +#define BUTTON_USER 0 + +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART1: + * + * The STM32F429I-DISCO has no on-board serial devices, but the console is + * brought out to PA9 (TX) and PA10 (RX) for connection to an external serial + * device. + */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_100MHz) + +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) + +/* CAN: */ + +#define GPIO_CAN1_RX (GPIO_CAN1_RX_2|GPIO_SPEED_50MHz) +#define GPIO_CAN1_TX (GPIO_CAN1_TX_2|GPIO_SPEED_50MHz) + +/* PWM + * + * The STM32F429I-DISCO has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2|GPIO_SPEED_50MHz) /* PE13 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ + +/* I2C - There is a STMPE811 TouchPanel on I2C3 using these pins: */ + +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_1|GPIO_SPEED_50MHz) + +/* SPI - There is a MEMS device on SPI5 using these pins: */ + +#define GPIO_SPI5_MISO (GPIO_SPI5_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI5_MOSI (GPIO_SPI5_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI5_SCK (GPIO_SPI5_SCK_1|GPIO_SPEED_50MHz) + +/* SPI - External SPI flash may be connected on SPI4: */ + +#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz) + +/* FMC - SDRAM */ + +#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz) + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +#ifdef CONFIG_STM32_LTDC +# ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + +/* LCD + * + * The STM32F429I-DISCO board contains an onboard TFT LCD connected to the + * LTDC interface of the uC. + * The LCD is 240x320 pixels. + * Define the parameters of the LCD and the interface here. + */ + +/* Panel configuration + * + * LCD Panel is Saef Technology Limited (SF-TC240T-9229A2-T) with integrated + * Ilitek ILI9341 LCD Single Chip Driver (240RGBx320) + * + * PLLSAI settings + * PLLSAIN : 192 + * PLLSAIR : 4 + * PLLSAIQ : 7 + * PLLSAIDIVR : 8 + * + * Timings + * Horizontal Front Porch : 10 (STM32_LTDC_HFP) + * Horizontal Back Porch : 20 (STM32_LTDC_HBP) + * Vertical Front Porch : 4 (STM32_LTDC_VFP) + * Vertical Back Porch : 2 (STM32_LTDC_VBP) + * + * Horizontal Sync : 10 (STM32_LTDC_HSYNC) + * Vertical Sync : 4 (STM32_LTDC_VSYNC) + * + * Active Width : 240 (STM32_LTDC_ACTIVEW) + * Active Height : 320 (STM32_LTDC_ACTIVEH) + */ + +/* LTDC PLL configuration + * + * PLLSAI_VCO = STM32_HSE_FREQUENCY / PLLM + * = 8000000ul / 8 + * = 1,000,000 + * + * PLL LCD clock output + * = PLLSAI_VCO * PLLSAIN / PLLSAIR / PLLSAIDIVR + * = 1,000,000 * 192 / 4 /8 + * = 6,000,000 + */ + +/* Defined panel settings */ + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ + defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) +# define BOARD_LTDC_WIDTH 320 +# define BOARD_LTDC_HEIGHT 240 +#else +# define BOARD_LTDC_WIDTH 240 +# define BOARD_LTDC_HEIGHT 320 +#endif + +#define BOARD_LTDC_OUTPUT_BPP 16 +#define BOARD_LTDC_HFP 10 +#define BOARD_LTDC_HBP 20 +#define BOARD_LTDC_VFP 4 +#define BOARD_LTDC_VBP 2 +#define BOARD_LTDC_HSYNC 10 +#define BOARD_LTDC_VSYNC 2 + +#define BOARD_LTDC_PLLSAIN 192 +#define BOARD_LTDC_PLLSAIR 4 +#define BOARD_LTDC_PLLSAIQ 7 + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_DIV8 + +/* Pixel Clock Polarity */ + +#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ + +/* Data Enable Polarity */ + +#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ + +/* Vertical Sync Polarity */ + +#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ + +/* Horizontal Sync Polarity */ + +#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ + +/* GPIO pinset */ + +#define GPIO_LTDC_PINS 18 /* 18-bit display */ + +#define GPIO_LTDC_R2 (GPIO_LTDC_R2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R3 (GPIO_LTDC_R3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R4 (GPIO_LTDC_R4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R5 (GPIO_LTDC_R5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R6 (GPIO_LTDC_R6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_R7 (GPIO_LTDC_R7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_G2 (GPIO_LTDC_G2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G3 (GPIO_LTDC_G3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G4 (GPIO_LTDC_G4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G5 (GPIO_LTDC_G5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G6 (GPIO_LTDC_G6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_G7 (GPIO_LTDC_G7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_B2 (GPIO_LTDC_B2_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B3 (GPIO_LTDC_B3_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B4 (GPIO_LTDC_B4_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B5 (GPIO_LTDC_B5_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B6 (GPIO_LTDC_B6_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_B7 (GPIO_LTDC_B7_1|GPIO_SPEED_100MHz) + +#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_1 +#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_1 +#define GPIO_LTDC_DE (GPIO_LTDC_DE_1|GPIO_SPEED_100MHz) +#define GPIO_LTDC_CLK GPIO_LTDC_CLK_1 + +#else +/* Custom LCD display configuration */ + +# define BOARD_LTDC_WIDTH ??? +# define BOARD_LTDC_HEIGHT ??? + +#define BOARD_LTDC_HFP ??? +#define BOARD_LTDC_HBP ??? +#define BOARD_LTDC_VFP ??? +#define BOARD_LTDC_VBP ??? +#define BOARD_LTDC_HSYNC ??? +#define BOARD_LTDC_VSYNC ??? + +#define BOARD_LTDC_PLLSAIN ??? +#define BOARD_LTDC_PLLSAIR ??? +#define BOARD_LTDC_PLLSAIQ ??? + +/* Division factor for LCD clock */ + +#define STM32_RCC_DCKCFGR_PLLSAIDIVR ??? + +/* Pixel Clock Polarity */ + +#define BOARD_LTDC_GCR_PCPOL ??? + +/* Data Enable Polarity */ + +#define BOARD_LTDC_GCR_DEPOL ??? + +/* Vertical Sync Polarity */ + +#define BOARD_LTDC_GCR_VSPOL ??? + +/* Horizontal Sync Polarity */ + +#define BOARD_LTDC_GCR_HSPOL ??? + +/* GPIO pinset */ + +#define GPIO_LTDC_PINS ??? + +#define GPIO_LTDC_R2 ??? +#define GPIO_LTDC_R3 ??? +#define GPIO_LTDC_R4 ??? +#define GPIO_LTDC_R5 ??? +#define GPIO_LTDC_R6 ??? +#define GPIO_LTDC_R7 ??? + +#define GPIO_LTDC_G2 ??? +#define GPIO_LTDC_G3 ??? +#define GPIO_LTDC_G4 ??? +#define GPIO_LTDC_G5 ??? +#define GPIO_LTDC_G6 ??? +#define GPIO_LTDC_G7 ??? + +#define GPIO_LTDC_B2 ??? +#define GPIO_LTDC_B3 ??? +#define GPIO_LTDC_B4 ??? +#define GPIO_LTDC_B5 ??? +#define GPIO_LTDC_B6 ??? +#define GPIO_LTDC_B7 ??? + +#define GPIO_LTDC_VSYNC ??? +#define GPIO_LTDC_HSYNC ??? +#define GPIO_LTDC_DE ??? +#define GPIO_LTDC_CLK ??? + +#endif /* Custom LCD display */ + +/* Configure PLLSAI */ + +#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN) +#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(BOARD_LTDC_PLLSAIQ) + +#endif /* CONFIG_STM32_LTDC */ + +/* L3GD20 MEMS */ + +#define GPIO_L3GD20_DREADY (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN2) +#define L3GD20_IRQ (2 + STM32_IRQ_EXTI0) + +#define BOARD_L3GD20_GPIO_DREADY GPIO_L3GD20_DREADY +#define BOARD_L3GD20_IRQ L3GD20_IRQ + +#define GPIO_LIS3DSH_EXT0 \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 + +/* DMA **********************************************************************/ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + +/* USB OTG FS / OTG HS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DM (GPIO_OTGHS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_DP (GPIO_OTGHS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHS_ID GPIO_OTGHS_ID_0 +#define GPIO_OTGHS_SOF GPIO_OTGHS_SOF_0 + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* FMC SDRAM pins (referenced by board src) */ + +#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz) +#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz) + +/* USB OTGHSFS (HS in FS mode) */ + +#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F429I_DISCO_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs new file mode 100644 index 0000000000000..5ecd6c7d19450 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_SYSTEM_OFLOADER),y) +LDSCRIPT = ofloader.ld +else +LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld new file mode 100644 index 0000000000000..b03d51ac65f8d --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script new file mode 100644 index 0000000000000..349f486d473a5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT6 has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld new file mode 100644 index 0000000000000..75cf8f18e6ebd --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F429ZIT has 2048Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld index ab7554dc716ec..10857b3f77c73 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld new file mode 100644 index 0000000000000..9830e4080570a --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt new file mode 100644 index 0000000000000..c4b340d84d8d9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_extmem.c) +endif() + +if(CONFIG_STM32_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_INPUT_STMPE811) + list(APPEND SRCS stm32_stmpe811.c) +endif() + +if(CONFIG_STM32F429I_DISCO_ILI9341) + list(APPEND SRCS stm32_ili93414ws.c) +endif() + +if(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE + AND CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + AND CONFIG_STM32_LTDC) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32F429I_DISCO_HIGHPRI) + list(APPEND SRCS stm32_highpri.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs new file mode 100644 index 0000000000000..a5df5de7384ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs @@ -0,0 +1,82 @@ +############################################################################ +# boards/arm/stm32f4/stm32f429i-disco/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_INPUT_STMPE811),y) +CSRCS += stm32_stmpe811.c +endif + +ifeq ($(CONFIG_STM32F429I_DISCO_ILI9341),y) +CSRCS += stm32_ili93414ws.c +endif + +ifeq ($(and \ + $(CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE), \ + $(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE), \ + $(CONFIG_STM32_LTDC)),) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32F429I_DISCO_HIGHPRI),y) +CSRCS += stm32_highpri.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c new file mode 100644 index 0000000000000..d7a1d4b33bed5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c @@ -0,0 +1,237 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +/* TODO DMA */ + +#define ADC1_NCHANNELS 2 +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[2] = +{ + 5, + 13, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[2] = +{ + GPIO_ADC1_IN5_0, /* PA5 */ + GPIO_ADC1_IN13_0, /* PC3 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[1] = +{ + 4, +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[1] = +{ + GPIO_ADC3_IN4_0, /* PF6 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 9, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN8_0, /* PD11/A3 */ + GPIO_ADC3_IN9_0, /* PD12/A4 */ + GPIO_ADC3_IN10_0, /* PD13/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c new file mode 100644 index 0000000000000..be4ca27083ea1 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM32F4_LED1 (1 << 0) +#define STM32F4_LED2 (1 << 1) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c new file mode 100644 index 0000000000000..60fa8e9a75de2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32f429i-disco.h" +#include "stm32_ccm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) + + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGHS + /* Initialize USB if the 1) OTG HS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_STM32_FMC + stm32_sdram_initialize(); +#endif + +#ifdef HAVE_CCM_HEAP + /* Initialize CCM allocator */ + + ccm_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c new file mode 100644 index 0000000000000..5b59f2dcf00c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c @@ -0,0 +1,429 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_STM32_SPI4 +# include +#endif + +#if defined(CONFIG_MTD_SST25XX) || defined(CONFIG_MTD_PROGMEM) +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR +#define CONFIG_STM32F429I_DISCO_FLASH_MINOR 0 +#endif + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART +#ifdef CONFIG_PLATFORM_CONFIGDATA +# include +#endif +#endif + +#ifdef CONFIG_STM32_OTGHS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_INPUT_BUTTONS_LOWER +# include +#endif + +#ifdef CONFIG_SENSORS_L3GD20 +#include "stm32_l3gd20.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#if defined(CONFIG_STM32_SPI4) + struct spi_dev_s *spi; +#endif +#if defined(CONFIG_MTD) + struct mtd_dev_s *mtd; +#if defined (CONFIG_MTD_SST25XX) + struct mtd_geometry_s geo; +#endif +#endif +#if defined(CONFIG_MTD_PARTITION_NAMES) + const char *partname = CONFIG_STM32F429I_DISCO_FLASH_PART_NAMES; +#endif + int ret; + +#ifdef HAVE_PROC + /* mount the proc filesystem */ + + ret = nx_mount(NULL, CONFIG_NSH_PROC_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + return ret; + } +#endif + + /* Configure SPI-based devices */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PROGMEM) + mtd = progmem_initialize(); + if (mtd == NULL) + { + syslog(LOG_ERR, "ERROR: progmem_initialize\n"); + } + + ret = register_mtddriver("/dev/flash", mtd, 0, mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: register_mtddriver() failed: %d\n", ret); + } + +#endif + +#ifdef CONFIG_STM32_SPI4 + /* Get the SPI port */ + + syslog(LOG_INFO, "Initializing SPI port 4\n"); + + spi = stm32_spibus_initialize(4); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port 4\n"); + return -ENODEV; + } + + syslog(LOG_INFO, "Successfully initialized SPI port 4\n"); + + /* Now bind the SPI interface to the SST25F064 SPI FLASH driver. This + * is a FLASH device that has been added external to the board (i.e. + * the board does not ship from STM with any on-board FLASH. + */ + +#if defined(CONFIG_MTD) && defined(CONFIG_MTD_SST25XX) + syslog(LOG_INFO, "Bind SPI to the SPI flash driver\n"); + + mtd = sst25xx_initialize(spi); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port 4 to the SPI FLASH" + " driver\n"); + } + else + { + syslog(LOG_INFO, "Successfully bound SPI port 4 to the SPI FLASH" + " driver\n"); + + /* Get the geometry of the FLASH device */ + + ret = mtd->ioctl(mtd, MTDIOC_GEOMETRY, + (unsigned long)((uintptr_t)&geo)); + if (ret < 0) + { + ferr("ERROR: mtd->ioctl failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_PART + { + int partno; + int partsize; + int partoffset; + int partszbytes; + int erasesize; + const char *partstring = CONFIG_STM32F429I_DISCO_FLASH_PART_LIST; + const char *ptr; + struct mtd_dev_s *mtd_part; + char partref[16]; + + /* Now create a partition on the FLASH device */ + + partno = 0; + ptr = partstring; + partoffset = 0; + + /* Get the Flash erase size */ + + erasesize = geo.erasesize; + + while (*ptr != '\0') + { + /* Get the partition size */ + + partsize = atoi(ptr); + partszbytes = (partsize << 10); /* partsize is defined in KB */ + + /* Check if partition size is bigger then erase block */ + + if (partszbytes < erasesize) + { + ferr("ERROR: Partition size is lesser than erasesize!\n"); + return -1; + } + + /* Check if partition size is multiple of erase block */ + + if ((partszbytes % erasesize) != 0) + { + ferr("ERROR: Partition size is not multiple of" + " erasesize!\n"); + return -1; + } + + mtd_part = mtd_partition(mtd, partoffset, + partszbytes / erasesize); + partoffset += partszbytes / erasesize; + +#ifdef CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART + /* Test if this is the config partition */ + + if (CONFIG_STM32F429I_DISCO_FLASH_CONFIG_PART_NUMBER == partno) + { + /* Register the partition as the config device */ + + mtdconfig_register(mtd_part); + } + else +#endif + { + /* Now initialize a SMART Flash block device and bind it + * to the MTD device. + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + snprintf(partref, sizeof(partref), "p%d", partno); + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, + mtd_part, partref); +#endif + } + +#if defined(CONFIG_MTD_PARTITION_NAMES) + /* Set the partition name */ + + if (mtd_part == NULL) + { + ferr("ERROR: failed to create partition %s\n", partname); + return -1; + } + + mtd_setpartitionname(mtd_part, partname); + + /* Now skip to next name. We don't need to split the string + * here because the MTD partition logic will only display names + * up to the comma, thus allowing us to use a single static + * name in the code. + */ + + while (*partname != ',' && *partname != '\0') + { + /* Skip to next ',' */ + + partname++; + } + + if (*partname == ',') + { + partname++; + } +#endif + + /* Update the pointer to point to the next size in the list */ + + while ((*ptr >= '0') && (*ptr <= '9')) + { + ptr++; + } + + if (*ptr == ',') + { + ptr++; + } + + /* Increment the part number */ + + partno++; + } + } +#else /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + + /* Configure the device with no partition support */ + + smart_initialize(CONFIG_STM32F429I_DISCO_FLASH_MINOR, mtd, NULL); + +#endif /* CONFIG_STM32F429I_DISCO_FLASH_PART */ + } + +#endif /* CONFIG_MTD */ +#endif /* CONFIG_STM32_SPI4 */ + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_RAMMTD) && defined(CONFIG_STM32F429I_DISCO_RAMMTD) + /* Create a RAM MTD device if configured */ + + { + uint8_t *start = + kmm_malloc(CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd = rammtd_initialize(start, + CONFIG_STM32F429I_DISCO_RAMMTD_SIZE * 1024); + mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + + /* Now initialize a SMART Flash block device and bind it to the MTD + * device + */ + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + smart_initialize(CONFIG_STM32F429I_DISCO_RAMMTD_MINOR, mtd, NULL); +#endif + } + +#endif /* CONFIG_RAMMTD && CONFIG_STM32F429I_DISCO_RAMMTD */ + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ + +#ifdef CONFIG_INPUT_STMPE811 + /* Initialize the touchscreen */ + + ret = stm32_tsc_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_tsc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_L3GD20 + ret = board_l3gd20_initialize(0, 5); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize l3gd20 sensor:" + " %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC device. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c new file mode 100644 index 0000000000000..80439363c1a2e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32f429i-disco.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c new file mode 100644 index 0000000000000..565420489dcd3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c new file mode 100644 index 0000000000000..d0f2faf088d0b --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c @@ -0,0 +1,178 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FMC +#warning "FMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +#error "Required GPIO ports not enabled" +#endif + +#define STM32_SDRAM_CLKEN FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2 + +#define STM32_SDRAM_PALL FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2 + +#define STM32_SDRAM_REFRESH FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\ + FMC_SDCMR_NRFS(4) + +#define STM32_SDRAM_MODEREG FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\ + FMC_SDCMR_MDR_BURST_LENGTH_2 | \ + FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\ + FMC_SDCMR_MDR_CAS_LATENCY_3 |\ + FMC_SDCMR_MDR_WBL_SINGLE + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_sdram_config[] = +{ + /* 16 data lines */ + + GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, + GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, + GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, + GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, + + /* 12 address lines */ + + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, + GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, + GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + + /* control lines */ + + GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0, + GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, + GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS, +}; + +#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdram_initialize + * + * Description: + * Called from stm32_bringup to initialize external SDRAM access. + * + ****************************************************************************/ + +void stm32_sdram_initialize(void) +{ + uint32_t val; + int i; + volatile int count; + + /* Enable GPIOs as FMC / memory pins */ + + for (i = 0; i < NUM_SDRAM_GPIOS; i++) + { + stm32_configgpio(g_sdram_config[i]); + } + + /* Enable AHB clocking to the FMC */ + + stm32_fmc_enable(); + + /* Configure and enable the SDRAM bank1 + * + * FMC clock = 180MHz/2 = 90MHz + * 90MHz = 11,11 ns + * All timings from the datasheet for Speedgrade -7 (=7ns) + */ + + val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ + FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ + FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */ + FMC_SDCR_NBANKS_4 | /* 4 internal banks */ + FMC_SDCR_WIDTH_16 | /* width = 16 bits */ + FMC_SDCR_ROWS_12 | /* numrows = 12 */ + FMC_SDCR_COLS_8; /* numcols = 8 bits */ + stm32_fmc_sdram_set_control(1, val); + stm32_fmc_sdram_set_control(2, val); + + val = FMC_SDTR_TRCD(3) | /* tRCD min = 15ns */ + FMC_SDTR_TRP(3) | /* tRP min = 15ns */ + FMC_SDTR_TWR(3) | /* tWR = 2CLK */ + FMC_SDTR_TRC(8) | /* tRC min = 63ns */ + FMC_SDTR_TRAS(5) | /* tRAS min = 42ns */ + FMC_SDTR_TXSR(8) | /* tXSR min = 70ns */ + FMC_SDTR_TMRD(3); /* tMRD = 2CLK */ + stm32_fmc_sdram_set_timing(2, val); + + /* SDRAM Initialization sequence */ + + stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */ + for (count = 0; count < 10000; count++); /* Delay */ + stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */ + stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */ + stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */ + + /* Set refresh count + * + * FMC_CLK = 90MHz + * Refresh_Rate = 7.81us + * Counter = (FMC_CLK * Refresh_Rate) - 20 + */ + + stm32_fmc_sdram_set_refresh_rate(683); + + /* Disable write protection */ + + /* stm32_fmc_sdram_write_protect(2, false); */ +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c new file mode 100644 index 0000000000000..66ec057d07c5b --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c @@ -0,0 +1,535 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32_dma.h" + +#include +#ifdef CONFIG_STM32F429I_DISCO_HIGHPRI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#ifdef CONFIG_STM32_ADC1_DMA +# if defined(CONFIG_STM32_TIM1_PWM) +# define HIGHPRI_HAVE_TIM1 +# endif +# if (CONFIG_STM32_ADC1_DMA_CFG != 1) +# error ADC1 DMA must be configured in Circular Mode +# endif +# if !defined(HIGHPRI_HAVE_TIM1) +# error "Needs TIM1 to trigger ADC DMA" +# endif +#endif + +#if (CONFIG_STM32_ADC1_INJECTED_CHAN > 0) +# if (CONFIG_STM32_ADC1_INJECTED_CHAN > 1) +# error Max 1 injected channels supported for now +# else +# define HIGHPRI_HAVE_INJECTED +# endif +#endif + +#ifdef HIGHPRI_HAVE_INJECTED +# define INJ_NCHANNELS CONFIG_STM32_ADC1_INJECTED_CHAN +#else +# define INJ_NCHANNELS (0) +#endif + +#ifndef CONFIG_STM32_ADC1_DMA +# define REG_NCHANNELS (1) +#else +# define REG_NCHANNELS (1) +#endif + +#define ADC1_NCHANNELS (REG_NCHANNELS + INJ_NCHANNELS) + +#define DEV1_PORT (1) +#define DEV1_NCHANNELS ADC1_NCHANNELS +#define ADC_REF_VOLTAGE (3.3f) +#define ADC_VAL_MAX (4095) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* High priority example private data */ + +struct highpri_s +{ + struct stm32_adc_dev_s *adc1; +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm; +#endif + volatile uint32_t cntr1; + volatile uint32_t cntr2; + volatile uint8_t current; + uint16_t r_val[REG_NCHANNELS]; + float r_volt[REG_NCHANNELS]; +#ifdef HIGHPRI_HAVE_INJECTED + uint16_t j_val[INJ_NCHANNELS]; + float j_volt[INJ_NCHANNELS]; +#endif + bool lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC channel list */ + +static const uint8_t g_chanlist1[DEV1_NCHANNELS] = +{ + 5, +#if INJ_NCHANNELS > 0 + 13, +#endif +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_pinlist1[DEV1_NCHANNELS] = +{ + GPIO_ADC1_IN5_0, /* PA5 */ +#if INJ_NCHANNELS > 0 + GPIO_ADC1_IN13_0, /* PC3 */ +#endif +}; + +static struct highpri_s g_highpri; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adc12_handler + * + * Description: + * This is the handler for the high speed ADC interrupt. + * + ****************************************************************************/ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) +void adc_handler(void) +{ + struct stm32_adc_dev_s *adc = g_highpri.adc1; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint32_t pending; +#ifdef HIGHPRI_HAVE_INJECTED + int i = 0; +#endif + + /* Get pending ADC1 interrupts */ + + pending = STM32_ADC_INT_GET(adc); + + if (g_highpri.lock == true) + { + goto irq_out; + } + +#ifndef CONFIG_STM32_ADC1_DMA + /* Regular channel end of conversion */ + + if (pending & ADC_ISR_EOC) + { + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + /* Get regular data */ + + g_highpri.r_val[g_highpri.current] = STM32_ADC_REGDATA_GET(adc); + + /* Do some floating point operations */ + + g_highpri.r_volt[g_highpri.current] = + (float)g_highpri.r_val[g_highpri.current] * ref / bit; + + if (g_highpri.current >= REG_NCHANNELS - 1) + { + g_highpri.current = 0; + } + else + { + g_highpri.current += 1; + } + } +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Injected channel end of sequence */ + + if (pending & ADC_ISR_JEOC) + { + /* Increase injected sequence counter */ + + g_highpri.cntr2 += 1; + + /* Get injected channels */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_val[i] = STM32_ADC_INJDATA_GET(adc, i); + } + + /* Do some floating point operations */ + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + g_highpri.j_volt[i] = (float)g_highpri.j_val[i] * ref / bit; + } + } +#endif + +irq_out: + + /* Clear ADC pending interrupts */ + + STM32_ADC_INT_ACK(adc, pending); +} +#endif + +/**************************************************************************** + * Name: dma2s0_handler + * + * Description: + * This is the handler for the high speed ADC interrupt using DMA transfer. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_ADC1_DMA +void dma2s0_handler(void) +{ + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + uint8_t pending; + int i; + + pending = stm32_dma_intget(DMA2, DMA_STREAM0); + + if (g_highpri.lock == true) + { + goto irq_out; + } + + /* Increase regular sequence counter */ + + g_highpri.cntr1 += 1; + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + /* Do some floating point operations */ + + g_highpri.r_volt[i] = (float)g_highpri.r_val[i] * ref / bit; + } + +irq_out: + + /* Clear DMA pending interrupts */ + + stm32_dma_intack(DMA2, DMA_STREAM0, pending); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: highpri_main + * + * Description: + * Main entry point in into the high priority interrupt test. + * + ****************************************************************************/ + +int highpri_main(int argc, char *argv[]) +{ +#ifdef HIGHPRI_HAVE_TIM1 + struct stm32_pwm_dev_s *pwm1; +#endif + struct adc_dev_s *adc1; + struct highpri_s *highpri; + int ret; + int i; + + highpri = &g_highpri; + + /* Initialize highpri structure */ + + memset(highpri, 0, sizeof(struct highpri_s)); + + printf("\nhighpri_main: Started\n"); + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Initialize ADC driver */ + + adc1 = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc1 == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->adc1 = (struct stm32_adc_dev_s *)adc1->ad_priv; + +#ifdef HIGHPRI_HAVE_TIM1 + /* Initialize TIM1 */ + + pwm1 = (struct stm32_pwm_dev_s *) stm32_pwminitialize(1); + if (pwm1 == NULL) + { + printf("ERROR: Failed to get PWM1 interface\n"); + ret = EXIT_FAILURE; + goto errout; + } + + highpri->pwm = pwm1; + + /* Setup PWM device */ + + PWM_SETUP(pwm1); + + /* Set timer frequency */ + + PWM_FREQ_UPDATE(pwm1, 1000); + + /* Set CCR1 */ + + PWM_CCR_UPDATE(pwm1, 1, 0x0f00); + + /* Enable TIM1 OUT1 */ + + PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true); + +#ifdef CONFIG_DEBUG_PWM_INFO + /* Print debug */ + + PWM_DUMP_REGS(pwm1); +#endif + +#endif /* HIGHPRI_HAVE_TIM1 */ + +#if !defined(CONFIG_STM32_ADC1_DMA) || defined(HIGHPRI_HAVE_INJECTED) + /* Attach ADC ram vector if no DMA or injected channels support */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC, adc_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_ADC); +#endif + +#ifdef CONFIG_STM32_ADC1_DMA + /* Attach DMA2 STREAM0 ram vector if DMA */ + + ret = arm_ramvec_attach(STM32_IRQ_DMA2S0, dma2s0_handler); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: arm_ramvec_attach failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the DMA2 STREAM0 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_DMA2S0, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + fprintf(stderr, "highpri_main: ERROR: up_prioritize_irq failed: %d\n", + ret); + ret = EXIT_FAILURE; + goto errout; + } + + up_enable_irq(STM32_IRQ_DMA2S0); +#endif + + /* Setup ADC hardware */ + + adc1->ad_ops->ao_setup(adc1); + + /* Configure regular channels trigger to T1CC1 */ + + STM32_ADC_EXTCFG_SET(highpri->adc1, + ADC1_EXTSEL_T1CC1 | ADC_EXTREG_EXTEN_DEFAULT); + +#ifndef CONFIG_STM32_ADC1_DMA + /* Enable ADC regular conversion interrupts if no DMA */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_EOC); +#else + /* Note: ADC and DMA must be reset after overrun occurs. + * For this example we assume that overrun will not occur. + * This is true only if DMA and ADC trigger are properly configured. + * DMA configuration must be done before ADC trigger starts! + */ + + /* Register ADC buffer for DMA transfer */ + + STM32_ADC_REGBUF_REGISTER(highpri->adc1, g_highpri.r_val, REG_NCHANNELS); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Enable ADC injected channels end of conversion interrupts */ + + STM32_ADC_INT_ENABLE(highpri->adc1, ADC_IER_JEOC); +#endif + +#ifdef HIGHPRI_HAVE_TIM1 + /* Enable timer counter after ADC and DMA configuration */ + + PWM_TIM_ENABLE(pwm1, true); +#endif + + while (1) + { +#ifndef CONFIG_STM32_ADC1_DMA + /* Software trigger for regular sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0); + + nxsched_usleep(100); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Software trigger for injected sequence */ + + adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0); + + nxsched_usleep(100); +#endif + /* Lock global data */ + + g_highpri.lock = true; + +#ifndef CONFIG_STM32_ADC1_DMA + printf("%" PRId32 " [%d] %0.3fV\n", g_highpri.cntr1, g_highpri.current, + g_highpri.r_volt[g_highpri.current]); +#else + printf("%" PRId32 " ", g_highpri.cntr1); + + for (i = 0; i < REG_NCHANNELS; i += 1) + { + printf("r:[%d] %0.3fV, ", i, g_highpri.r_volt[i]); + } + + printf("\n"); +#endif + +#ifdef HIGHPRI_HAVE_INJECTED + /* Print data from injected channels */ + + printf("%" PRId32 " ", g_highpri.cntr2); + + for (i = 0; i < INJ_NCHANNELS; i += 1) + { + printf("j:[%d] %0.3fV, ", i, g_highpri.j_volt[i]); + } + + printf("\n"); +#endif + /* Unlock global data */ + + g_highpri.lock = false; + + nxsched_sleep(1); + } + +errout: + return ret; +} + +#endif /* CONFIG_STM32F429I_DISCO_HIGHPRI */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c new file mode 100644 index 0000000000000..16b818e188a77 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ +#ifdef CONFIG_RTC_ALARM + struct timespec alarmtime; +#endif + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: stm32_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_RTC_ALARM) +static void stm32_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c index 2171493eb4b9c..84c83f2113f32 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ #define ILI93414WS_SPI_DEVICE 5 -/* spi frequency based on arch/arm/src/stm32/stm32_spi.c */ +/* spi frequency based on arch/arm/src/common/stm32/stm32_spi.h */ #ifndef CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY # define CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY 20000000 @@ -209,7 +209,7 @@ struct ili93414ws_lcd_s g_lcddev; * * Description: * Clear and set bits in the CR register (based on - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). * * Input Parameters: * reg - register to set @@ -951,14 +951,14 @@ static void stm32_ili93414ws_deselect(struct ili9341_lcd_s *lcd) /* Restore cr1 and cr2 register to be sure they will be usable * by default spi interface structure. (This is an important workaround as * long as half duplex mode is not supported by the spi interface in - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ putreg16(priv->cr2, ILI93414WS_SPI_CR2); putreg16(priv->cr1, ILI93414WS_SPI_CR1); /* Enable spi device is default for initialized spi ports (see - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ stm32_ili93414ws_spienable(); diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c new file mode 100644 index 0000000000000..28e8c772a62e5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c @@ -0,0 +1,576 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32f429i-disco.h" +#include "stm32_ltdc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE +# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE +#else +# define ILI9341_LCD_DEVICE 0 +#endif + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + +/* Display settings */ + +/* Pixel Format Set (COLMOD) + * + * Note! RGB interface settings (DPI) is unimportant for the MCU interface + * mode but set the register to the defined state equal to the MCU interface + * pixel format. + * + * 16 Bit MCU: 01100101 / h65 + * + * DPI: 6 (RGB18-666 RGB interface) + * DBI: 5 (RGB16-565 MCU interface, not used set to default) + */ + +#define STM32_ILI9341_PIXSET_PARAM (ILI9341_PIXEL_FORMAT_SET_DPI(6) | \ + ILI9341_PIXEL_FORMAT_SET_DBI(5)) + +/* DE Mode RCM = 2, Sync Mode RCM = 3 + * Interface Mode Control + * + * EPL: 0 High enable for RGB interface + * DPL: 1 data fetched at the falling time + * HSPL: 0 Low level sync clock + * VSPL: 0 Low level sync clock + * RCM: 2 (DE Mode) + * ByPass_Mode: 1 (Memory) + */ + +#define STM32_ILI9341_IFMODE_PARAM (ILI9341_INTERFACE_CONTROL_DPL | \ + ILI9341_INTERFACE_CONTROL_RCM(2) | \ + ILI9341_INTERFACE_CONTROL_BPASS) + +/* Interface control (IFCTL) + * + * Parameter 1: 0x0001 + * MY_EOR: 0 + * MX_EOR: 0 + * MV_EOR: 0 + * BGR_EOR: 0 + * WEMODE: 1 Reset column and page if data transfer exceeds + */ + +#define STM32_ILI9341_IFCTL_PARAM1 (ILI9341_INTERFACE_CONTROL_WEMODE) + +/* Parameter 2: 0x0000 + * + * EPF: 0 65k color format for RGB interface + * MDT: 0 Display data transfer mode + * + */ +#define STM32_ILI9341_IFCTL_PARAM2 (ILI9341_INTERFACE_CONTROL_MDT(0) | \ + ILI9341_INTERFACE_CONTROL_EPF(0)) + +/* Parameter 3: 0x0000/0x0020 + * + * ENDIAN: 0 Big endian + * DM: 1 RGB Interface Mode + * RM: 1 RGB interface + * RIM: 0 18-bit 1 transfer/pixel RGB interface mode + * + */ +#define STM32_ILI9341_IFCTL_PARAM3 (ILI9341_INTERFACE_CONTROL_RM | \ + ILI9341_INTERFACE_CONTROL_DM(1)) + +/* Memory access control (MADCTL) */ + +/* Landscape: 00100000 / 00101000 / h28 + * + * MY: 0 + * MX: 0 + * MV: 1 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_LANDSCAPE_MY 0 +#define ILI9341_MADCTL_LANDSCAPE_MX 0 +#define ILI9341_MADCTL_LANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV +#define ILI9341_MADCTL_LANDSCAPE_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_LANDSCAPE_BGR 0 +#else +# define ILI9341_MADCTL_LANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_LANDSCAPE_MH 0 + +#define ILI9341_MADCTL_LANDSCAPE_PARAM1 (ILI9341_MADCTL_LANDSCAPE_MY | \ + ILI9341_MADCTL_LANDSCAPE_MX | \ + ILI9341_MADCTL_LANDSCAPE_MV | \ + ILI9341_MADCTL_LANDSCAPE_ML | \ + ILI9341_MADCTL_LANDSCAPE_BGR | \ + ILI9341_MADCTL_LANDSCAPE_MH) + +/* Portrait: 00000000 / 00001000 / h08 + * + * MY: 0 + * MX: 0 + * MV: 0 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_PORTRAIT_MY 0 +#define ILI9341_MADCTL_PORTRAIT_MX ILI9341_MEMORY_ACCESS_CONTROL_MX +#define ILI9341_MADCTL_PORTRAIT_MV 0 +#define ILI9341_MADCTL_PORTRAIT_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_PORTRAIT_BGR 0 +#else +# define ILI9341_MADCTL_PORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_PORTRAIT_MH 0 + +#define ILI9341_MADCTL_PORTRAIT_PARAM1 (ILI9341_MADCTL_PORTRAIT_MY | \ + ILI9341_MADCTL_PORTRAIT_MX | \ + ILI9341_MADCTL_PORTRAIT_MV | \ + ILI9341_MADCTL_PORTRAIT_ML | \ + ILI9341_MADCTL_PORTRAIT_BGR | \ + ILI9341_MADCTL_PORTRAIT_MH) + +/* RLandscape: 01100000 / 01101000 / h68 + * + * MY: 0 + * MX: 1 + * MV: 1 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + */ + +#define ILI9341_MADCTL_RLANDSCAPE_MY 0 +#define ILI9341_MADCTL_RLANDSCAPE_MX ILI9341_MEMORY_ACCESS_CONTROL_MX +#define ILI9341_MADCTL_RLANDSCAPE_MV ILI9341_MEMORY_ACCESS_CONTROL_MV +#define ILI9341_MADCTL_RLANDSCAPE_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_RLANDSCAPE_BGR 0 +#else +# define ILI9341_MADCTL_RLANDSCAPE_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_RLANDSCAPE_MH 0 + +#define ILI9341_MADCTL_RLANDSCAPE_PARAM1 \ + (ILI9341_MADCTL_RLANDSCAPE_MY | \ + ILI9341_MADCTL_RLANDSCAPE_MX | \ + ILI9341_MADCTL_RLANDSCAPE_MV | \ + ILI9341_MADCTL_RLANDSCAPE_ML | \ + ILI9341_MADCTL_RLANDSCAPE_BGR | \ + ILI9341_MADCTL_RLANDSCAPE_MH) + +/* RPortrait: 11000000 / 11001000 / hc8 + * + * MY: 1 + * MX: 1 + * MV: 0 + * ML: 0 + * BGR: 0/1 Depending on endian mode of the mcu? + * MH: 0 + * + */ + +#define ILI9341_MADCTL_RPORTRAIT_MY ILI9341_MEMORY_ACCESS_CONTROL_MY +#define ILI9341_MADCTL_RPORTRAIT_MX 0 +#define ILI9341_MADCTL_RPORTRAIT_MV 0 +#define ILI9341_MADCTL_RPORTRAIT_ML 0 +#ifdef CONFIG_ENDIAN_BIG +# define ILI9341_MADCTL_RPORTRAIT_BGR 0 +#else +# define ILI9341_MADCTL_RPORTRAIT_BGR ILI9341_MEMORY_ACCESS_CONTROL_BGR +#endif +#define ILI9341_MADCTL_RPORTRAIT_MH 0 + +#define ILI9341_MADCTL_RPORTRAIT_PARAM1 (ILI9341_MADCTL_RPORTRAIT_MY | \ + ILI9341_MADCTL_RPORTRAIT_MX | \ + ILI9341_MADCTL_RPORTRAIT_MV | \ + ILI9341_MADCTL_RPORTRAIT_ML | \ + ILI9341_MADCTL_RPORTRAIT_BGR | \ + ILI9341_MADCTL_RPORTRAIT_MH) + +/* Set the display orientation */ + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 +# warning "ILI9341 doesn't support full landscape with RGB interface" +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_PORTRAIT) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 +# warning "ILI9341 doesn't support full landscape with RGB interface" +#elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RPORTRAIT) +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 +#else +# error "display orientation not defined" +#endif + +#define ILI9341_XRES BOARD_LTDC_WIDTH +#define ILI9341_YRES BOARD_LTDC_HEIGHT +#endif /* CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE +struct lcd_dev_s *g_lcd = NULL; +#endif + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE +struct ili9341_lcd_s *g_ltdc = NULL; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE +/**************************************************************************** + * Name: stm32_ili9341_initialize + * + * Description: + * Initialize the ili9341 LCD controller to the RGB interface mode. + * + ****************************************************************************/ + +static int stm32_ili9341_initialize(void) +{ + struct ili9341_lcd_s *lcd = g_ltdc; + + lcd = stm32_ili93414ws_initialize(); + + if (lcd == NULL) + { + return ENODEV; + } + + /* Select spi device */ + + lcdinfo("Initialize ili9341 lcd driver\n"); + lcd->select(lcd); + +#ifdef CONFIG_DEBUG_LCD_INFO + /* Read display identification */ + + uint8_t param; + lcd->sendcmd(lcd, ILI9341_READ_ID1); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules manufacturer ID: %d\n", param); + + lcd->sendcmd(lcd, ILI9341_READ_ID2); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules driver version ID: %d\n", param); + + lcd->sendcmd(lcd, ILI9341_READ_ID3); + lcd->recvparam(lcd, ¶m); + lcdinfo("ili9341 LCD driver: LCD modules driver ID: %d\n", param); +#endif + + /* Reset the lcd display to the default state */ + + lcdinfo("ili9341 LCD driver: Software Reset\n"); + lcd->sendcmd(lcd, ILI9341_SOFTWARE_RESET); + up_mdelay(5); + + lcdinfo("ili9341 LCD driver: set Memory Access Control %08x\n", + STM32_ILI9341_MADCTL_PARAM); + lcd->sendcmd(lcd, ILI9341_MEMORY_ACCESS_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_MADCTL_PARAM); + + /* Pixel Format */ + + lcdinfo("ili9341 LCD driver: Set Pixel Format: %02x\n", + STM32_ILI9341_PIXSET_PARAM); + lcd->sendcmd(lcd, ILI9341_PIXEL_FORMAT_SET); + lcd->sendparam(lcd, STM32_ILI9341_PIXSET_PARAM); + + /* Select column */ + + lcdinfo("ili9341 LCD driver: Set Column Address\n"); + lcd->sendcmd(lcd, ILI9341_COLUMN_ADDRESS_SET); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, (ILI9341_XRES >> 8)); + lcd->sendparam(lcd, (ILI9341_XRES & 0xff)); + + /* Select page */ + + lcdinfo("ili9341 LCD driver: Set Page Address\n"); + lcd->sendcmd(lcd, ILI9341_PAGE_ADDRESS_SET); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, 0); + lcd->sendparam(lcd, (ILI9341_YRES >> 8)); + lcd->sendparam(lcd, (ILI9341_YRES & 0xff)); + + /* RGB Interface signal control */ + + lcdinfo("ili9341 LCD driver: Set RGB Interface signal control: %02x\n", + STM32_ILI9341_IFMODE_PARAM); + lcd->sendcmd(lcd, ILI9341_RGB_SIGNAL_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_IFMODE_PARAM); + + /* Interface control */ + + lcdinfo("ili9341 LCD driver: Set Interface control: %d:%d:%d\n", + STM32_ILI9341_IFCTL_PARAM1, + STM32_ILI9341_IFCTL_PARAM2, + STM32_ILI9341_IFCTL_PARAM3); + + lcd->sendcmd(lcd, ILI9341_INTERFACE_CONTROL); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM1); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM2); + lcd->sendparam(lcd, STM32_ILI9341_IFCTL_PARAM3); + + /* Sleep out set to the end */ + + lcdinfo("ili9341 LCD driver: Sleep Out\n"); + lcd->sendcmd(lcd, ILI9341_SLEEP_OUT); + up_mdelay(5); /* 120? */ + + /* Display on */ + + lcdinfo("ili9341 LCD driver: Display On\n"); + lcd->sendcmd(lcd, ILI9341_DISPLAY_ON); + + /* Deselect spi device */ + + lcd->deselect(lcd); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD Device. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Set display off */ + + g_lcd->setpower(g_lcd, 0); + + g_lcd = NULL; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a reference to the LCD object for the specified LCD Device. + * This allows support for multiple LCD devices. + * + * Input Parameters: + * lcddev - Number of the LDC Device. + * + * Returned Value: + * Reference to the LCD object if exist otherwise NULL + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + if (lcddev == ILI9341_LCD_DEVICE) + { + return g_lcd; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, but + * with the power setting at 0 (full off). + * + * Input Parameters: + * + * Returned Value: + * On success - Ok + * On error - Error Code + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* check if always initialized */ + + if (!g_lcd) + { + /* Initialize the sub driver structure */ + + struct ili9341_lcd_s *dev = stm32_ili93414ws_initialize(); + + /* Initialize public lcd driver structure */ + + if (dev) + { + /* Get a reference to valid lcd driver structure to avoid repeated + * initialization of the LCD Device. Also enables uninitializing of + * the LCD Device. + */ + + g_lcd = ili9341_initialize(dev, ILI9341_LCD_DEVICE); + if (g_lcd) + { + return OK; + } + } + + return -ENODEV; + } + + return OK; +} +#endif /* CONFIG_STM32F429I_DISCO_ILI9341_LCDIFACE */ + +#ifdef CONFIG_STM32_LTDC +/**************************************************************************** + * Name: up_fbinitialize + * + * Description: + * Initialize the framebuffer video hardware associated with the display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +int up_fbinitialize(int display) +{ + static bool initialized = false; + int ret = OK; + + if (!initialized) + { +#ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE + /* Initialize the ili9341 LCD controller */ + + ret = stm32_ili9341_initialize(); + if (ret >= OK) + { + ret = stm32_ltdcinitialize(); + } + +#else + /* Custom LCD display with RGB interface */ + + ret = stm32_ltdcinitialize(); +#endif + + initialized = (ret >= OK); + } + + return ret; +} + +/**************************************************************************** + * Name: up_fbgetvplane + * + * Description: + * Return a a reference to the framebuffer object for the specified video + * plane of the specified plane. + * Many OSDs support multiple planes of video. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * vplane - Identifies the plane being queried. + * + * Returned Value: + * A non-NULL pointer to the frame buffer access structure is returned on + * success; NULL is returned on any failure. + * + ****************************************************************************/ + +struct fb_vtable_s *up_fbgetvplane(int display, int vplane) +{ + return stm32_ltdcgetvplane(vplane); +} + +/**************************************************************************** + * Name: up_fbuninitialize + * + * Description: + * Uninitialize the framebuffer support for the specified display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_fbuninitialize(int display) +{ + stm32_ltdcuninitialize(); +} +#endif /* CONFIG_STM32_LTDC */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c new file mode 100644 index 0000000000000..318fe6a8521b5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f429i-disco.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM Timer */ + +#define STM32F429IDISCO_PWMTIMER 1 + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F429IDISCO_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c new file mode 100644 index 0000000000000..b45295dbf242e --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) ||\ + defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI5 +struct spi_dev_s *g_spidev5 = NULL; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f429i-disco + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI5 + stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ + stm32_configgpio(GPIO_CS_LCD); /* LCD chip select */ + stm32_configgpio(GPIO_LCD_DC); /* LCD Data/Command select */ + stm32_configgpio(GPIO_LCD_ENABLE); /* LCD enable select */ +#endif +#if defined(CONFIG_STM32_SPI4) && defined(CONFIG_MTD_SST25XX) + stm32_configgpio(GPIO_CS_SST25); /* SST25 FLASH chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ +#if defined(CONFIG_MTD_SST25XX) + if (devid == SPIDEV_FLASH(0)) + { + stm32_gpiowrite(GPIO_CS_SST25, !selected); + } +#endif +} + +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + +#if defined(CONFIG_STM32F429I_DISCO_ILI9341) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_CS_LCD, !selected); + } + else +#endif + + { + stm32_gpiowrite(GPIO_CS_MEMS, !selected); + } +} + +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI4 +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI5 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_STM32F429I_DISCO_ILI9341) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(GPIO_LCD_DC, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +/**************************************************************************** + * Name: stm32_spi5initialize + * + * Description: + * Initialize the selected SPI port. + * As long as the method stm32_spibus_initialize recognized the initialized + * state of the spi device by the spi enable flag of the cr1 register, it + * isn't safe to disable the spi device outside of the nuttx spi interface + * structure. But this has to be done as long as the nuttx spi interface + * doesn't support bidirectional data transfer for multiple devices share + * one spi bus. This wrapper does nothing else than store the initialized + * state of the spi device after the first initializing and should be used + * by each driver who shares the spi5 bus. + * + * Input Parameters: + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI5 +struct spi_dev_s *stm32_spi5initialize(void) +{ + if (!g_spidev5) + { + g_spidev5 = stm32_spibus_initialize(5); + } + + return g_spidev5; +} +#endif +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c new file mode 100644 index 0000000000000..e6733b6f56921 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c @@ -0,0 +1,337 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32.h" +#include "stm32f429i-disco.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifdef CONFIG_INPUT_STMPE811 +#ifndef CONFIG_INPUT +# error "STMPE811 support requires CONFIG_INPUT" +#endif + +#ifndef CONFIG_STM32_I2C3 +# error "STMPE811 support requires CONFIG_STM32_I2C3" +#endif + +#ifndef CONFIG_STMPE811_I2C +# error "Only the STMPE811 I2C interface is supported" +#endif + +#ifdef CONFIG_STMPE811_SPI +# error "Only the STMPE811 SPI interface is supported" +#endif + +#ifndef CONFIG_STMPE811_FREQUENCY +# define CONFIG_STMPE811_FREQUENCY 100000 +#endif + +#ifndef CONFIG_STMPE811_I2CDEV +# define CONFIG_STMPE811_I2CDEV 3 +#endif + +#if CONFIG_STMPE811_I2CDEV != 3 +# error "CONFIG_STMPE811_I2CDEV must be three" +#endif + +#ifndef CONFIG_STMPE811_DEVMINOR +# define CONFIG_STMPE811_DEVMINOR 0 +#endif + +/* Board definitions ********************************************************/ + +/* The STM3240G-EVAL has two STMPE811QTR I/O expanders on board both + * connected to the STM32 via I2C1. They share a common interrupt line: PI2. + * + * STMPE811 U24, I2C address 0x41 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- TouchScreen_Y- LCD Connector XL + * X- TouchScreen_X- LCD Connector XR + * Y+ TouchScreen_Y+ LCD Connector XD + * X+ TouchScreen_X+ LCD Connector XU + * IN3 EXP_IO9 + * IN2 EXP_IO10 + * IN1 EXP_IO11 + * IN0 EXP_IO12 + * + * STMPE811 U29, I2C address 0x44 (7-bit) + * ------ ---- ---------------- -------------------------------------------- + * STPE11 PIN BOARD SIGNAL BOARD CONNECTION + * ------ ---- ---------------- -------------------------------------------- + * Y- EXP_IO1 + * X- EXP_IO2 + * Y+ EXP_IO3 + * X+ EXP_IO4 + * IN3 EXP_IO5 + * IN2 EXP_IO6 + * IN1 EXP_IO7 + * IN0 EXP_IO8 + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_stmpe811config_s +{ + /* Configuration structure as seen by the STMPE811 driver */ + + struct stmpe811_config_s config; + + /* Additional private definitions only known to this driver */ + + STMPE811_HANDLE handle; /* The STMPE811 driver handle */ + xcpt_t handler; /* The STMPE811 interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs.* so that contact and loss- + * of-contact events can be detected. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg); +static void stmpe811_enable(struct stmpe811_config_s *state, + bool enable); +static void stmpe811_clear(struct stmpe811_config_s *state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the STMPE811 + * driver. This structure provides information about the configuration + * of the STMPE811 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +#ifndef CONFIG_STMPE811_TSC_DISABLE +static struct stm32_stmpe811config_s g_stmpe811config = +{ + .config = + { +#ifdef CONFIG_STMPE811_I2C + .address = STMPE811_ADDR1, +#endif + .frequency = CONFIG_STMPE811_FREQUENCY, + +#ifdef CONFIG_STMPE811_MULTIPLE + .irq = STM32_IRQ_EXTI2, +#endif + .ctrl1 = (ADC_CTRL1_SAMPLE_TIME_80 | ADC_CTRL1_MOD_12B), + .ctrl2 = ADC_CTRL2_ADC_FREQ_3p25, + + .attach = stmpe811_attach, + .enable = stmpe811_enable, + .clear = stmpe811_clear, + }, + .handler = NULL, + .arg = NULL, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the STMPE811 driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the STMPE811 interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + * clear - Acknowledge/clear any pending GPIO interrupt + */ + +static int stmpe811_attach(struct stmpe811_config_s *state, xcpt_t isr, + void *arg) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + + iinfo("Saving handler %p\n", isr); + DEBUGASSERT(priv); + + /* Just save the handler. We will use it when EXTI interruptsare enabled */ + + priv->handler = isr; + priv->arg = arg; + return OK; +} + +static void stmpe811_enable(struct stmpe811_config_s *state, bool enable) +{ + struct stm32_stmpe811config_s *priv = + (struct stm32_stmpe811config_s *)state; + irqstate_t flags; + + /* Attach and enable, or detach and disable. Enabling and disabling GPIO + * interrupts is a multi-step process so the safest thing is to keep + * interrupts disabled during the reconfiguration. + */ + + flags = enter_critical_section(); + if (enable) + { + /* Configure the EXTI interrupt using the SAVED handler */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, true, true, true, + priv->handler, priv->arg); + } + else + { + /* Configure the EXTI interrupt with a NULL handler to disable it */ + + stm32_gpiosetevent(GPIO_IO_EXPANDER, false, false, false, + NULL, NULL); + } + + leave_critical_section(flags); +} + +static void stmpe811_clear(struct stmpe811_config_s *state) +{ + /* Does nothing */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_tsc_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * touchscreen device. This function will register the driver as + * /dev/inputN where N is the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_tsc_setup(int minor) +{ +#ifndef CONFIG_STMPE811_TSC_DISABLE + struct i2c_master_s *dev; + int ret; + + iinfo("minor %d\n", minor); + DEBUGASSERT(minor == 0); + + /* Check if we are already initialized */ + + if (!g_stmpe811config.handle) + { + iinfo("Initializing\n"); + + /* Configure the STMPE811 interrupt pin as an input */ + + stm32_configgpio(GPIO_IO_EXPANDER); + + /* Get an instance of the I2C interface */ + + dev = stm32_i2cbus_initialize(CONFIG_STMPE811_I2CDEV); + if (!dev) + { + ierr("ERROR: Failed to initialize I2C bus %d\n", + CONFIG_STMPE811_I2CDEV); + return -ENODEV; + } + + /* Instantiate the STMPE811 driver */ + + g_stmpe811config.handle = + stmpe811_instantiate(dev, + (struct stmpe811_config_s *)&g_stmpe811config); + if (!g_stmpe811config.handle) + { + ierr("ERROR: Failed to instantiate the STMPE811 driver\n"); + return -ENODEV; + } + + /* Initialize and register the I2C touchscreen device */ + + ret = stmpe811_register(g_stmpe811config.handle, + CONFIG_STMPE811_DEVMINOR); + if (ret < 0) + { + ierr("ERROR: Failed to register STMPE driver: %d\n", ret); + + /* stm32_i2cbus_uninitialize(dev); */ + + return -ENODEV; + } + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_INPUT_STMPE811 */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c new file mode 100644 index 0000000000000..64d1ec5758e37 --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c @@ -0,0 +1,310 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otghs.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_STM32_OTGHS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F429IDISCO_USBHOST_PRIO +# define CONFIG_STM32F429IDISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGHS + stm32_configgpio(GPIO_OTGHS_VBUS); + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otghshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F429IDISCO_USBHOST_PRIO, + CONFIG_STM32F429IDISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGHS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGHS */ diff --git a/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c new file mode 100644 index 0000000000000..9ba0c74b5a5ab --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c @@ -0,0 +1,211 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f429i-disco.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_ledpminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_ledpminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h index 121f0380a7355..a9f7d7a5d6af3 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h + * boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #endif -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh rename to boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh index d871b35a27d0f..b2df4b4f3b069 100755 --- a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh +++ b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash ############################################################################# - # boards/arm/stm32/stm32f429-disco/tools/fbcalc.sh + # boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt new file mode 100644 index 0000000000000..3aee03875c31f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt @@ -0,0 +1,30 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) + +if(NOT CONFIG_BUILD_FLAT) + add_subdirectory(kernel) + set_property( + GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld + ${CMAKE_CURRENT_LIST_DIR}/scripts/user-space.ld) +endif() diff --git a/boards/arm/stm32/stm32f4discovery/Kconfig b/boards/arm/stm32f4/stm32f4discovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f4discovery/Kconfig rename to boards/arm/stm32f4/stm32f4discovery/Kconfig diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig new file mode 100644 index 0000000000000..493408723d332 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ADBD_FILE_SERVICE=y +CONFIG_ADBD_SHELL_SERVICE=y +CONFIG_ADBD_USB_SERVER=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_URANDOM=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBUV=y +CONFIG_LINE_MAX=128 +CONFIG_MMCSD=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2020 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_ADBD=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBADB=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig new file mode 100644 index 0000000000000..aec03f8df55f2 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig @@ -0,0 +1,75 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_AUDIO=y +CONFIG_AUDIO_CS43L22=y +CONFIG_AUDIO_CUSTOM_DEV_PATH=y +CONFIG_AUDIO_EXCLUDE_TONE=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_DRIVER=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/music" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2S3=y +CONFIG_STM32_I2S3_TX=y +CONFIG_STM32_I2S_MCK=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_SOFINTR=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USBHOST=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USBHOST_ISOC_DISABLE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig new file mode 100644 index 0000000000000..0580be8f51bd9 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_APDS9960=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_FB_STACKSIZE=16000 +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_LARGEFILE=y +CONFIG_FS_PROCFS=y +CONFIG_GAMES_BRICKMATCH=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_APA102=y +CONFIG_LCD_APA102_FREQUENCY=10000000 +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_APDS9960=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig new file mode 100644 index 0000000000000..6b7b18cc1b123 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_LIBDRONECAN=y +CONFIG_CAN_EXTID=y +CONFIG_EXAMPLES_DRONECAN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig new file mode 100644 index 0000000000000..51f162f19cf6e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig @@ -0,0 +1,100 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_COMPOSITE_IAD=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=128 +CONFIG_MMCSD=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFS=y +CONFIG_NFS_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/nfs/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RNDIS_COMPOSITE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig new file mode 100644 index 0000000000000..c76721660ac5d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CXX_EXCEPTION=y +CONFIG_CXX_STANDARD="c++17" +CONFIG_DRVR_MKRD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_NONE=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXXTOOLCHAIN=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig new file mode 100644 index 0000000000000..e08ad78e23dad --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ALLOW_GPL_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_HAVE_CXX=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="cxxtest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=2 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TESTING_CXXTEST=y +CONFIG_UCLIBCXX=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig new file mode 100644 index 0000000000000..5d723c21b0b27 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_ELF_STACKSIZE=4096 +CONFIG_EXAMPLES_ELF=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="elf_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_MM_REGIONS=2 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig new file mode 100644 index 0000000000000..34aeeb9e313c4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETINIT_DRIPADDR=0xc0a80001 +CONFIG_NETINIT_IPADDR=0xc0a80010 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_MAX_LISTENPORTS=16 +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_PREALLOC_CONNS=16 +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NET_W5500=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig new file mode 100644 index 0000000000000..0a856c6e1657d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETINIT_IPv6NETMASK_8=0xff80 +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_NEIGHBOR=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_SOLINGER=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32F4DISBB=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_USART6_RXBUFSIZE=64 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs new file mode 100644 index 0000000000000..8c981466a321e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT1 = memory.ld +LDSCRIPT2 = kernel-space.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT1) +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT2) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig new file mode 100644 index 0000000000000..f24a077cc43d3 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARM_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILD_PROTECTED=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="ostest_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_KERNEL_HEAPSIZE=16384 +CONFIG_MM_REGIONS=2 +CONFIG_NUTTX_USERSPACE=0x08020000 +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=22 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2013 +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_NBARRIER_THREADS=3 +CONFIG_TESTING_OSTEST_STACKSIZE=2048 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig new file mode 100644 index 0000000000000..90156f132df87 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD_BACKPACK=y +CONFIG_LCD_LCD1602=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig new file mode 100644 index 0000000000000..5f14cb57fe770 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LWL_CONSOLE=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig new file mode 100644 index 0000000000000..098729374157a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MAX31855=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MAX31855=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig new file mode 100644 index 0000000000000..bee74446f04bc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_FS_PROCFS_INCLUDE_PROGMEM is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CMP is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_SEMICOLON is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_NX_DISABLE_1BPP is not set +# CONFIG_NX_WRITEONLY is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_NXHELLO=y +CONFIG_EXAMPLES_NXHELLO_BPP=1 +CONFIG_EXAMPLES_NXHELLO_LISTENER_STACKSIZE=1536 +CONFIG_EXAMPLES_NXHELLO_STACKSIZE=1536 +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_MAX7219=y +CONFIG_LCD_NOGETRUN=y +CONFIG_MAX7219_NHORIZONTALBLKS=4 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXSTART_SERVERSTACK=1536 +CONFIG_NX_BLOCKING=y +CONFIG_NX_MXCLIENTMSGS=32 +CONFIG_PREALLOC_MQ_MSGS=16 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=21 +CONFIG_START_MONTH=4 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig new file mode 100644 index 0000000000000..905b47c6c4eca --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_STM32_CCMEXCLUDE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MM_REGIONS=2 +CONFIG_NETUTILS_CODECS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=30 +CONFIG_SCHED_WAITPID=y +CONFIG_SENDFILE_BUFSIZE=1024 +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig new file mode 100644 index 0000000000000..9ca17e59aa35a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_TCP_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_MODBUS=y +CONFIG_EXAMPLES_MODBUS_PORT=1 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INDUSTRY_MODBUS=y +CONFIG_INDUSTRY_MODBUS_SLAVE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART1_BAUD=38400 +CONFIG_USART1_PARITY=2 +CONFIG_USART1_RS485=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig new file mode 100644 index 0000000000000..187cc9545643e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MODULE=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig new file mode 100644 index 0000000000000..ed7c5122192d4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_KEYBOARD=y +CONFIG_EXAMPLES_KEYBOARD_DEVPATH="/dev/keypad0" +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_MPR121_KEYPAD=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig new file mode 100644 index 0000000000000..54d22a0a69b4e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEBUG_ERROR is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SENSORS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_MT6816=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig new file mode 100644 index 0000000000000..e18237614b4f4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_HOSTNAME="STM32F4-Discovery" +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MMCSD_MULTIBLOCK_LIMIT=1 +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_SOLINGER=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32F4DISBB=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_EXTCLK=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART6_RXBUFSIZE=64 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=64 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..f81f20eeb8072 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig new file mode 100644 index 0000000000000..b52478393f047 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set +# CONFIG_NXFONTS_DISABLE_16BPP is not set +# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set +# CONFIG_NX_DISABLE_16BPP is not set +# CONFIG_NX_PACKEDMSFIRST is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_EXAMPLES_NXLINES=y +CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320 +CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0 +CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4 +CONFIG_EXAMPLES_NXLINES_BPP=16 +CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb +CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0 +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nxlines_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_MAXCONTRAST=1 +CONFIG_LCD_MAXPOWER=255 +CONFIG_LCD_SSD1289=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LIBRARY=y +CONFIG_NSH_READLINE=y +CONFIG_NX=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NXTK_BORDERCOLOR1=0x5cb7 +CONFIG_NXTK_BORDERCOLOR2=0x21c9 +CONFIG_NXTK_BORDERCOLOR3=0xffdf +CONFIG_NX_BLOCKING=y +CONFIG_NX_KBD=y +CONFIG_NX_XYINPUT_MOUSE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_FSMC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig new file mode 100644 index 0000000000000..44b4599511611 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_MKRD=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=2048 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_NXSCOPE=y +CONFIG_EXAMPLES_NXSCOPE_CDCACM=y +CONFIG_EXAMPLES_NXSCOPE_SERIAL_PATH="/dev/ttyACM0" +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nxscope_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LOGGING_NXSCOPE=y +CONFIG_LOGGING_NXSCOPE_ACKFRAMES=y +CONFIG_LOGGING_NXSCOPE_DIVIDER=y +CONFIG_LOGGING_NXSCOPE_INTF_SERIAL=y +CONFIG_MM_REGIONS=2 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_READLINE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig new file mode 100644 index 0000000000000..baab23750c31e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_LEDS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_CUSTOM_PMINIT=y +CONFIG_ARCH_IDLE_CUSTOM=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PM=y +CONFIG_PM_BUTTONS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_HPWORKSTACKSIZE=1024 +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig new file mode 100644 index 0000000000000..71f4c3468486c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_CONSTRUCTORS=y +CONFIG_BOARDCTL=y +CONFIG_BOARDCTL_APP_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_CONSOLE_SYSLOG=y +CONFIG_ELF=y +CONFIG_EXAMPLES_POSIXSPAWN=y +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_NSYMBOLS_VAR="g_spawn_nexports" +CONFIG_EXECFUNCS_SYMTAB_ARRAY="g_spawn_exports" +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="posix_spawn_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_MM_REGIONS=2 +CONFIG_PATH_INITIAL="/mnt/romfs" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_START_DAY=26 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig new file mode 100644 index 0000000000000..2571bb23113bc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_PTYTEST=y +CONFIG_EXAMPLES_PTYTEST_POLL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig new file mode 100644 index 0000000000000..37c135b2c6f2d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_RGBLED=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="rgbled_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RGBLED=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_CH2OUT=y +CONFIG_STM32_TIM2_CHANNEL=2 +CONFIG_STM32_TIM2_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CHANNEL=3 +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig new file mode 100644 index 0000000000000..dafce58d6125d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig @@ -0,0 +1,93 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=128 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFS=y +CONFIG_NFS_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/nfs/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_START_DAY=13 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2014 +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig new file mode 100644 index 0000000000000..569b7f230ceff --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_ASSERTIONS_FILENAME is not set +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_KEYBOARD=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_SBUTTON=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig new file mode 100644 index 0000000000000..5c8b151be4f70 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_SPORADIC=y +CONFIG_SCHED_SPORADIC_MAXREPL=5 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2021 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART6_RXBUFSIZE=128 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART6_TXBUFSIZE=128 +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig new file mode 100644 index 0000000000000..c76f9ac1a12f6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig @@ -0,0 +1,63 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_ST7567=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig new file mode 100644 index 0000000000000..2e36dbdc267c6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LCD_ST7789=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS_DISABLE_1BPP=y +CONFIG_NXFONTS_DISABLE_24BPP=y +CONFIG_NXFONTS_DISABLE_2BPP=y +CONFIG_NXFONTS_DISABLE_32BPP=y +CONFIG_NXFONTS_DISABLE_4BPP=y +CONFIG_NXFONTS_DISABLE_8BPP=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig new file mode 100644 index 0000000000000..938dcea494fd6 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CXX_LOCALIZATION=y +CONFIG_CXX_WCHAR=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_HAVE_CXX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_LOCALE=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LIBC_MAX_EXITFUNS=4 +CONFIG_LIBM=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=2 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2012 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TLS_NELEM=16 +CONFIG_TLS_TASK_NELEM=8 +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..65c89a22460f8 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSLOG_CHAR=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 +CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/ram0" +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..167fbd097ef5a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_BUFSIZE=4096 +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig new file mode 100644 index 0000000000000..673265e3c7724 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig @@ -0,0 +1,103 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_CARDDETECT is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_NET_ARP is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SPI_CALLBACK is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_CODECS_HASH_MD5=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_WEBSERVER=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HEAP_COLORATION=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LINE_MAX=64 +CONFIG_MMCSD=y +CONFIG_MM_IOB=y +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETUTILS_CODECS=y +CONFIG_NETUTILS_FTPC=y +CONFIG_NETUTILS_HTTPD_DIRLIST=y +CONFIG_NETUTILS_HTTPD_SENDFILE=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NETUTILS_WEBSERVER=y +CONFIG_NET_USRSOCK=y +CONFIG_NET_USRSOCK_PREALLOC_CONNS=16 +CONFIG_NET_USRSOCK_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_SYMTAB=y +CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" +CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" +CONFIG_PATH_INITIAL="/mnt/sd0/bin" +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORKPRIORITY=30 +CONFIG_SCHED_WAITPID=y +CONFIG_SENDFILE_BUFSIZE=1024 +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=22 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2019 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI2_DMA=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SPI3_DMA=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NTPC=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_WIRELESS_GS2200M=y +CONFIG_WL_GS2200M=y +CONFIG_WL_GS2200M_DISABLE_DHCPC=y +CONFIG_WL_GS2200M_SPI_FREQUENCY=10000000 diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig new file mode 100644 index 0000000000000..c7a5839e069aa --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32f4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_XEN1210=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=8 +CONFIG_START_YEAR=2016 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXBUFSIZE=128 diff --git a/boards/arm/stm32f4/stm32f4discovery/include/board.h b/boards/arm/stm32f4/stm32f4discovery/include/board.h new file mode 100644 index 0000000000000..d8bebb7ef980d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/include/board.h @@ -0,0 +1,650 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/* Do not include STM32-specific header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The STM32F4 Discovery board features a single 8MHz crystal. + * Space is provided for a 32kHz RTC backup crystal, but it is not stuffed. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL + * configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC + * HSE - On-board crystal frequency is 8MHz + * LSE - 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (8,000,000 / 8) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY + +/* SDIO dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz + */ + +#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz + * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT) +#else +# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) +#endif + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_ORANGE BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 +#define BOARD_LED_BLUE BOARD_LED4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the stm32f4discovery. The following definitions describe how NuttX + * controls the LEDs: + */ + +#define LED_STARTED 0 /* LED1 */ +#define LED_HEAPALLOCATE 1 /* LED2 */ +#define LED_IRQSENABLED 2 /* LED1 + LED2 */ +#define LED_STACKCREATED 3 /* LED3 */ +#define LED_INIRQ 4 /* LED1 + LED3 */ +#define LED_SIGNAL 5 /* LED2 + LED3 */ +#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ +#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ + +/* Button definitions *******************************************************/ + +/* The STM32F4 Discovery supports one button: */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* CAN */ + +#ifndef CONFIG_STM32_FSMC +# define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) +# define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) +#endif + +#ifndef CONFIG_STM32_ETHMAC +# define GPIO_CAN2_RX (GPIO_CAN2_RX_1|GPIO_SPEED_50MHz) +# define GPIO_CAN2_TX (GPIO_CAN2_TX_1|GPIO_SPEED_50MHz) +#endif + +/* USART1 */ + +#ifdef CONFIG_USART1_RS485 + /* Lets use for RS485 on pins: PB6 and PB7 */ + +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_100MHz) +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_100MHz) + + /* RS485 DIR pin: PA15 */ + +# define GPIO_USART1_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN15) + +#endif + +/* USART2: + * + * The STM32F4 Discovery has no on-board serial devices, but the console is + * brought out to PA2 (TX) and PA3 (RX) for connection to an external serial + * device. + * + * These pins selections, however, conflict with pin usage on the + * STM32F4DIS-BB. + */ + +#ifndef CONFIG_STM32F4DISBB +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_100MHz) /* PA3, P1 pin 13 */ +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_100MHz) /* PA2, P1 pin 14 */ +# define GPIO_USART2_CTS GPIO_USART2_CTS_1 /* PA0, P1 pin 11 */ +# define GPIO_USART2_RTS GPIO_USART2_RTS_1 /* PA1, P1 pin 12 (conflict with USER button) */ +#endif + +/* USART3: + * + * Used in pseudoterm configuration and also with the BT860 HCI UART. + * RTS/CTS Flow control support is needed by the HCI UART. + * + * There are conflicts with the STM32F4DIS-BB Ethernet in this configuration + * when Ethernet is enabled: + * + * PB-11 conflicts with Ethernet TXEN + * PB-13 conflicts with Ethernet TXD1 + * + * UART3 TXD and RXD are available on CON4 PD8 and PD8 of the STM32F4DIS-BB, + * respectively, but not CTS or RTS. For now we assume that Ethernet is not + * enabled if USART3 is used in a configuration with the STM32F4DIS-BB. + */ + +#define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_100MHz) /* PB10, P1 pin 34 (also MP45DT02 CLK_IN) */ +#define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_100MHz) /* PB11, P1 pin 35 */ +#define GPIO_USART3_CTS GPIO_USART3_CTS_1 /* PB13, P1 pin 37 */ +#define GPIO_USART3_RTS GPIO_USART3_RTS_1 /* PB14, P1 pin 38 */ + +/* USART6: + * + * The STM32F4DIS-BB base board provides RS-232 drivers and a DB9 connector + * for USART6. This is the preferred serial console for use with the + * STM32F4DIS-BB. + * + * NOTE: CTS and RTS are not brought out to the RS-232 connector on the + * baseboard. + */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_1|GPIO_SPEED_100MHz) /* PC7 (also I2S3_MCK and P2 pin 48) */ +#define GPIO_USART6_TX (GPIO_USART6_TX_1|GPIO_SPEED_100MHz) /* PC6 (also P2 pin 47) */ + +/* PWM + * + * The STM32F4 Discovery has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM4 CH2 on PD13. + */ + +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_2|GPIO_SPEED_50MHz) + +/* Capture + * + * The STM32F4 Discovery has no real on-board pwm capture devices, but the + * board can be configured to capture pwm using TIM3 CH2 PB5. + */ + +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) + +/* RGB LED + * + * R = TIM1 CH1 on PE9 | G = TIM2 CH2 on PA1 | B = TIM3 CH3 on PB0 + */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2OUT (GPIO_TIM2_CH2OUT_1|GPIO_SPEED_50MHz) +#define GPIO_TIM3_CH3OUT (GPIO_TIM3_CH3OUT_1|GPIO_SPEED_50MHz) + +/* SPI - There is a MEMS device on SPI1 using these pins: */ + +#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz) + +/* SPI DMA -- As used for I2S DMA transfer with the audio configuration */ + +#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 +#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 + +/* SPI2 - Test MAX31855 on SPI2 PB10 = SCK, PB14 = MISO */ + +#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_1|GPIO_SPEED_50MHz) + +/* SPI2 DMA -- As used for MMC/SD SPI */ + +#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX +#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX + +/* SPI3 DMA -- As used for I2S DMA transfer with the audio configuration */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_1|GPIO_SPEED_50MHz) +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1|GPIO_SPEED_50MHz) + +#define DMACHAN_SPI3_RX DMAMAP_SPI3_RX_1 +#define DMACHAN_SPI3_TX DMAMAP_SPI3_TX_1 + +/* I2S3 - CS43L22 configuration uses I2S3 */ + +#define GPIO_I2S3_SD GPIO_I2S3_SD_2 +#define GPIO_I2S3_CK GPIO_I2S3_CK_2 +#define GPIO_I2S3_WS GPIO_I2S3_WS_1 + +#define DMACHAN_I2S3_RX DMAMAP_SPI3_RX_2 +#define DMACHAN_I2S3_TX DMAMAP_SPI3_TX_2 + +/* I2C. Only I2C1 is available on the stm32f4discovery. I2C1_SCL and + * I2C1_SDA are available on the following pins: + * + * - PB6 is I2C1_SCL + * - PB9 is I2C1_SDA + */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_50MHz) + +/* Timer Inputs/Outputs */ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2|GPIO_SPEED_50MHz) +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1|GPIO_SPEED_50MHz) + +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1|GPIO_SPEED_50MHz) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1|GPIO_SPEED_50MHz) + +/* Ethernet *****************************************************************/ + +#if defined(CONFIG_STM32F4DISBB) && defined(CONFIG_STM32_ETHMAC) + /* RMII interface to the LAN8720 PHY */ + +# ifndef CONFIG_STM32_RMII +# error CONFIG_STM32_RMII must be defined +# endif + + /* Clocking is provided by an external 25Mhz XTAL */ + +# ifndef CONFIG_STM32_RMII_EXTCLK +# error CONFIG_STM32_RMII_EXTCLK must be defined +# endif + + /* Pin disambiguation */ + +# define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1|GPIO_SPEED_100MHz) +# define GPIO_ETH_PPS_OUT (GPIO_ETH_PPS_OUT_1|GPIO_SPEED_100MHz) + +#endif + +#ifdef CONFIG_MMCSD_SPI +#define GPIO_MMCSD_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12) + +#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTC | GPIO_PIN1) +#endif + +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. + * + * SDIO DMA + * DMAMAP_SDIO_1 = Channel 4, Stream 3 + * DMAMAP_SDIO_2 = Channel 4, Stream 6 + */ + +#define DMAMAP_SDIO DMAMAP_SDIO_1 + +/* ZERO CROSS pin definition */ + +#define BOARD_ZEROCROSS_GPIO \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN0) + +/* Pin for APDS-9960 sensor */ + +#define GPIO_APDS9960_INT \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_APDS9960_GPIO_INT GPIO_APDS9960_INT + +/* IRQ Pin for MPR121 Capacitive Keypad */ + +#define GPIO_MPR121_INT \ + (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTB|GPIO_PIN0) + +#define BOARD_MPR121_GPIO_INT GPIO_MPR121_INT + +/* Pin for Magnetic Encoder MT6816 */ + +#define GPIO_CS_MT6816 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) + +/* LIS3DSH */ + +#define GPIO_LIS3DSH_EXT0 \ + (GPIO_INPUT|GPIO_FLOAT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN0) + +#define BOARD_LIS3DSH_GPIO_EXT0 GPIO_LIS3DSH_EXT0 + +/* XEN1210 magnetic sensor */ + +#define GPIO_XEN1210_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN5) + +#define GPIO_CS_XEN1210 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) + +#define BOARD_XEN1210_GPIO_INT GPIO_XEN1210_INT + +#define BOARD_SBUTTON_GPIO_INT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN0) + +/* Define what timer to use as XEN1210 CLK (will use channel 1) */ + +#define BOARD_XEN1210_PWMTIMER 1 + +/* Keyboard Matrix Configuration */ + +/* Define keyboard matrix row pins (outputs) */ + +#define GPIO_KMATRIX_ROW0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN7) +#define GPIO_KMATRIX_ROW1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN8) +#define GPIO_KMATRIX_ROW2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) +#define GPIO_KMATRIX_ROW3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN10) + +/* Row pins as inputs with pull-up for early diagnostics */ + +#define GPIO_KMATRIX_ROW0_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN7) +#define GPIO_KMATRIX_ROW1_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN8) +#define GPIO_KMATRIX_ROW2_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN9) +#define GPIO_KMATRIX_ROW3_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN10) + +/* Define keyboard matrix column pins (inputs) */ + +#define GPIO_KMATRIX_COL0 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN11) +#define GPIO_KMATRIX_COL1 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN13) +#define GPIO_KMATRIX_COL2 (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|\ + GPIO_PORTE|GPIO_PIN14) + +/* Column pins as outputs for diagnostics only */ + +#define GPIO_KMATRIX_COL0_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) +#define GPIO_KMATRIX_COL1_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN13) +#define GPIO_KMATRIX_COL2_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) + +/* Board-level KMATRIX pin definitions */ + +#define BOARD_KMATRIX_ROW0 GPIO_KMATRIX_ROW0 +#define BOARD_KMATRIX_ROW1 GPIO_KMATRIX_ROW1 +#define BOARD_KMATRIX_ROW2 GPIO_KMATRIX_ROW2 +#define BOARD_KMATRIX_ROW3 GPIO_KMATRIX_ROW3 + +#define BOARD_KMATRIX_ROW0_IN GPIO_KMATRIX_ROW0_IN +#define BOARD_KMATRIX_ROW1_IN GPIO_KMATRIX_ROW1_IN +#define BOARD_KMATRIX_ROW2_IN GPIO_KMATRIX_ROW2_IN +#define BOARD_KMATRIX_ROW3_IN GPIO_KMATRIX_ROW3_IN + +#define BOARD_KMATRIX_COL0 GPIO_KMATRIX_COL0 +#define BOARD_KMATRIX_COL1 GPIO_KMATRIX_COL1 +#define BOARD_KMATRIX_COL2 GPIO_KMATRIX_COL2 + +#define BOARD_KMATRIX_COL0_OUT GPIO_KMATRIX_COL0_OUT +#define BOARD_KMATRIX_COL1_OUT GPIO_KMATRIX_COL1_OUT +#define BOARD_KMATRIX_COL2_OUT GPIO_KMATRIX_COL2_OUT + +#ifdef CONFIG_INPUT_KMATRIX +int board_kmatrix_diag(int loops, int delay_ms); +#endif + +/* Keyboard Matrix I2C Configuration */ + +#define CONFIG_STM32_KMATRIX_I2C_BUS 1 /* I2C1 */ +#define CONFIG_STM32_KMATRIX_I2C_ADDR 0x20 /* MCP23X08/PCA9538 address */ +#define CONFIG_STM32_KMATRIX_I2C_FREQ 400000 /* 400 kHz */ + +/* MCO and ETH inputs (referenced by arch/eth driver) */ + +#define GPIO_MCO1 (GPIO_MCO1_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) + +/* SDIO */ + +#define GPIO_SDIO_CK (GPIO_SDIO_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_CMD (GPIO_SDIO_CMD_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D0 (GPIO_SDIO_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D1 (GPIO_SDIO_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D2 (GPIO_SDIO_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDIO_D3 (GPIO_SDIO_D3_0|GPIO_SPEED_50MHz) + +/* USB OTG FS / OTG HS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_SOF (GPIO_OTGFS_SOF_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DM (GPIO_OTGHSFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_DP (GPIO_OTGHSFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGHSFS_ID (GPIO_OTGHSFS_ID_0|GPIO_SPEED_100MHz) + +/* DAC */ + +#define GPIO_DAC1_OUT1 GPIO_DAC1_OUT1_0 +#define GPIO_DAC1_OUT2 GPIO_DAC1_OUT2_0 + +/* I2S3 MCK (referenced by audio driver) */ + +#define GPIO_I2S3_MCK GPIO_I2S3_MCK_0 + +/* FSMC SRAM/LCD pins */ + +#define GPIO_FSMC_A0 (GPIO_FSMC_A0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A1 (GPIO_FSMC_A1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A2 (GPIO_FSMC_A2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A3 (GPIO_FSMC_A3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A4 (GPIO_FSMC_A4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A5 (GPIO_FSMC_A5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A6 (GPIO_FSMC_A6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A7 (GPIO_FSMC_A7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A8 (GPIO_FSMC_A8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A9 (GPIO_FSMC_A9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A10 (GPIO_FSMC_A10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A11 (GPIO_FSMC_A11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A12 (GPIO_FSMC_A12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A13 (GPIO_FSMC_A13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A14 (GPIO_FSMC_A14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A15 (GPIO_FSMC_A15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A16 (GPIO_FSMC_A16_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A17 (GPIO_FSMC_A17_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A18 (GPIO_FSMC_A18_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A19 (GPIO_FSMC_A19_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A20 (GPIO_FSMC_A20_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A21 (GPIO_FSMC_A21_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A22 (GPIO_FSMC_A22_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A23 (GPIO_FSMC_A23_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A24 (GPIO_FSMC_A24_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_A25 (GPIO_FSMC_A25_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D0 (GPIO_FSMC_D0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D1 (GPIO_FSMC_D1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D2 (GPIO_FSMC_D2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D3 (GPIO_FSMC_D3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D4 (GPIO_FSMC_D4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D5 (GPIO_FSMC_D5_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D6 (GPIO_FSMC_D6_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D7 (GPIO_FSMC_D7_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D8 (GPIO_FSMC_D8_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D9 (GPIO_FSMC_D9_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D10 (GPIO_FSMC_D10_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D11 (GPIO_FSMC_D11_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D12 (GPIO_FSMC_D12_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D13 (GPIO_FSMC_D13_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D14 (GPIO_FSMC_D14_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_D15 (GPIO_FSMC_D15_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NOE (GPIO_FSMC_NOE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NWE (GPIO_FSMC_NWE_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE1 (GPIO_FSMC_NE1_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE2 (GPIO_FSMC_NE2_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE3 (GPIO_FSMC_NE3_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NE4 (GPIO_FSMC_NE4_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL0 (GPIO_FSMC_NBL0_0|GPIO_SPEED_100MHz) +#define GPIO_FSMC_NBL1 (GPIO_FSMC_NBL1_0|GPIO_SPEED_100MHz) + +#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt new file mode 100644 index 0000000000000..7edffd00c7c5e --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_sources(nuttx_user PRIVATE stm32_userspace.c) diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile new file mode 100644 index 0000000000000..94250906043bb --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) $(USER_LIBGCC) --end-group + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c new file mode 100644 index 0000000000000..6bcb1ee9edf26 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct userspace_data_s g_userspace_data = +{ + .us_heap = &g_mmheap, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* User data memory structure */ + + .us_data = &g_userspace_data, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs new file mode 100644 index 0000000000000..9b89de7ed1c56 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld new file mode 100644 index 0000000000000..b6fff76f8b944 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld @@ -0,0 +1,99 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script new file mode 100644 index 0000000000000..d51d0c7f6b291 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld new file mode 100644 index 0000000000000..0d1eadb712dcf --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32F407VG has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into three blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of CCM SRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed (See + * also boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld). Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x2000 0000: Kernel .data region. Typical size: 0.1KB + * ------ ---- Kernel .bss region. Typical size: 1.8KB + * 0x2000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------ ---- Padded to 8KB + * 0x2000 2000: User .data region. Size is variable. + * ------ ---- User .bss region Size is variable. + * 0x2000 4000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE which must be set to 16Kb. + * 0x2000 8000: Beginning of 32Kb user heap. + * 0x2001 0000: The remainder of SRAM is, unfortunately, wasted. + * 0x2001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x20004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x20008000, LENGTH = 80K +} diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld new file mode 100644 index 0000000000000..24c62636c4680 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + KEEP(*(.userspace)) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..f65fa366811b4 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -0,0 +1,234 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_AUDIO_CS43L22) + list(APPEND SRCS stm32_cs43l22.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_LCD_ST7567) + list(APPEND SRCS stm32_st7567.c) +endif() + +if(CONFIG_ENC28J60) + list(APPEND SRCS stm32_enc28j60.c) +endif() + +if(CONFIG_LPWAN_SX127X) + list(APPEND SRCS stm32_sx127x.c) +endif() + +if(CONFIG_LCD_MAX7219) + list(APPEND SRCS stm32_max7219.c) +endif() + +if(CONFIG_LCD_ST7032) + list(APPEND SRCS stm32_st7032.c) +endif() + +if(CONFIG_PCA9635PW) + list(APPEND SRCS stm32_pca9635.c) +endif() + +if(CONFIG_STM32_SDIO) + list(APPEND SRCS stm32_sdio.c) +endif() + +if(CONFIG_STM32_ETHMAC) + list(APPEND SRCS stm32_ethernet.c) +endif() + +if(CONFIG_LEDS_MAX7219) + list(APPEND SRCS stm32_max7219_leds.c) +endif() + +if(CONFIG_RGBLED) + list(APPEND SRCS stm32_rgbled.c) +endif() + +if(CONFIG_RTC_DS1307) + list(APPEND SRCS stm32_ds1307.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pm.c) +endif() + +if(CONFIG_PM_BUTTONS) + list(APPEND SRCS stm32_pmbuttons.c) +endif() + +if(CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle.c) +endif() + +if(CONFIG_STM32_FSMC) + list(APPEND SRCS stm32_extmem.c) + + if(CONFIG_LCD_SSD1289) + list(APPEND SRCS stm32_ssd1289.c) + endif() +endif() + +if(CONFIG_LCD_SSD1351) + list(APPEND SRCS stm32_ssd1351.c) +endif() + +if(CONFIG_LCD_UG2864AMBAG01) + list(APPEND SRCS stm32_ug2864ambag01.c) +endif() + +if(CONFIG_LCD_UG2864HSWEG01) + list(APPEND SRCS stm32_ug2864hsweg01.c) +endif() + +if(CONFIG_TIMER) + list(APPEND SRCS stm32_timer.c) +endif() + +if(CONFIG_STM32_HCIUART) + if(CONFIG_BLUETOOTH_UART) + list(APPEND SRCS stm32_hciuart.c) + endif() +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(NOT CONFIG_STM32_ETHMAC) + if(CONFIG_NETDEVICES) + list(APPEND SRCS stm32_netinit.c) + endif() +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_mmcsd.c) +endif() + +if(CONFIG_WL_GS2200M) + list(APPEND SRCS stm32_gs2200m.c) +endif() + +if(CONFIG_LCD_ST7789) + list(APPEND SRCS stm32_st7789.c) +endif() + +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +# Set linker script based on build type +if(CONFIG_BUILD_PROTECTED) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/memory.ld" + "${NUTTX_BOARD_DIR}/scripts/kernel-space.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") +endif() + +# TODO:move this to appropriate arch/toolchain level +set_property( + GLOBAL APPEND + PROPERTY COMPILE_OPTIONS $<$:-fno-strict-aliasing + -fomit-frame-pointer>) + +# TODO: see where to put pic flags set_property(TARGET nuttx APPEND PROPERTY +# NUTTX_COMPILE_OPTIONS $<$>:-fpic -msingle-pic-base +# -mpic-register=r10>) + +# ifeq ($(CONFIG_ARMV7M_TOOLCHAIN_CLANGL),y) ARCHCFLAGS += -nostdlib +# -ffreestanding ARCHCXXFLAGS += -nostdlib -ffreestanding else ARCHCFLAGS += +# -funwind-tables ARCHCXXFLAGS += -fno-rtti -funwind-tables ifneq +# ($(CONFIG_DEBUG_NOOPT),y) ARCHOPTIMIZATION += -fno-strength-reduce endif endif + +if(CONFIG_UNWINDER_ARM) + set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_COMPILE_OPTIONS -funwind-tables) + set_property(GLOBAL APPEND PROPERTY COMPILE_OPTIONS -fno-strength-reduce) +endif() + +# TODO: nxflat NXFLATLDFLAGS1 = -r -d -warn-common NXFLATLDFLAGS2 = +# $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld +# -no-check-sections LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_MODULE_COMPILE_OPTIONS -mlong-calls) +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_MODULE_LINK_OPTIONS -r -e module_initialize -T + ${NUTTX_DIR}/libs/libc/elf/gnu-elf.ld) + +# ELF module definitions + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_APP_COMPILE_OPTIONS -mlong-calls) +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_ELF_APP_LINK_OPTIONS -r -e main + -T${NUTTX_BOARD_DIR}/scripts/gnu-elf.ld) diff --git a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs new file mode 100644 index 0000000000000..bb7e1b041232a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -0,0 +1,195 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_AUDIO_CS43L22),y) +CSRCS += stm32_cs43l22.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_LCD_ST7567),y) +CSRCS += stm32_st7567.c +endif + +ifeq ($(CONFIG_ENC28J60),y) +CSRCS += stm32_enc28j60.c +endif + +ifeq ($(CONFIG_NET_W5500),y) +CSRCS += stm32_w5500.c +endif + +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + +ifeq ($(CONFIG_LCD_MAX7219),y) +CSRCS += stm32_max7219.c +endif + +ifeq ($(CONFIG_LCD_ST7032),y) +CSRCS += stm32_st7032.c +endif + +ifeq ($(CONFIG_PCA9635PW),y) +CSRCS += stm32_pca9635.c +endif + +ifeq ($(CONFIG_STM32_SDIO),y) +CSRCS += stm32_sdio.c +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +CSRCS += stm32_ethernet.c +endif + +ifeq ($(CONFIG_LEDS_MAX7219),y) +CSRCS += stm32_max7219_leds.c +endif + +ifeq ($(CONFIG_RGBLED),y) +CSRCS += stm32_rgbled.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_CAPTURE),y) +CSRCS += stm32_capture.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CSRCS += stm32_pm.c +endif + +ifeq ($(CONFIG_PM_BUTTONS),y) +CSRCS += stm32_pmbuttons.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c + +ifeq ($(CONFIG_LCD_SSD1289),y) +CSRCS += stm32_ssd1289.c +endif +endif + +ifeq ($(CONFIG_LCD_APA102),y) +CSRCS += stm32_apa102.c +endif + +ifeq ($(CONFIG_LCD_SSD1351),y) +CSRCS += stm32_ssd1351.c +endif + +ifeq ($(CONFIG_LCD_UG2864AMBAG01),y) +CSRCS += stm32_ug2864ambag01.c +endif + +ifeq ($(CONFIG_LCD_UG2864HSWEG01),y) +CSRCS += stm32_ug2864hsweg01.c +endif + +ifeq ($(CONFIG_TIMER),y) +CSRCS += stm32_timer.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +ifeq ($(CONFIG_BLUETOOTH_UART),y) +CSRCS += stm32_hciuart.c +endif +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) +CSRCS += stm32_romfs_initialize.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifneq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_NETDEVICES),y) +CSRCS += stm32_netinit.c +endif +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_mmcsd.c +endif + +ifeq ($(CONFIG_WL_GS2200M),y) +CSRCS += stm32_gs2200m.c +endif + +ifeq ($(CONFIG_LCD_ST7789),y) +CSRCS += stm32_st7789.c +endif + +ifeq ($(CONFIG_INPUT_DJOYSTICK),y) + CSRCS += stm32_djoystick.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) + CSRCS += stm32_composite.c +endif + +ifeq ($(CONFIG_ADC_HX711),y) +CSRCS += stm32_hx711.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c index 340db0bae338a..ee6b826ed9609 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c * * SPDX-License-Identifier: Apache-2.0 * @@ -108,4 +108,3 @@ void board_lcd_uninitialize(void) { /* TO-FIX */ } - diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..ef69cc6c3ab7a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c @@ -0,0 +1,232 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following definitions map the encoded LED setting to GPIO settings */ + +#define STM32F4_LED1 (1 << 0) +#define STM32F4_LED2 (1 << 1) +#define STM32F4_LED3 (1 << 2) +#define STM32F4_LED4 (1 << 3) + +#define ON_SETBITS_SHIFT (0) +#define ON_CLRBITS_SHIFT (4) +#define OFF_SETBITS_SHIFT (8) +#define OFF_CLRBITS_SHIFT (12) + +#define ON_BITS(v) ((v) & 0xff) +#define OFF_BITS(v) (((v) >> 8) & 0x0ff) +#define SETBITS(b) ((b) & 0x0f) +#define CLRBITS(b) (((b) >> 4) & 0x0f) + +#define ON_SETBITS(v) (SETBITS(ON_BITS(v)) +#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v)) +#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v)) +#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v)) + +#define LED_STARTED_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_STARTED_ON_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT) +#define LED_STARTED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_HEAPALLOCATE_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_SETBITS ((STM32F4_LED1) << OFF_SETBITS_SHIFT) +#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM32F4_LED2|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_IRQSENABLED_ON_SETBITS ((STM32F4_LED1|STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_IRQSENABLED_ON_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_IRQSENABLED_OFF_SETBITS ((STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_IRQSENABLED_OFF_CLRBITS ((STM32F4_LED1|STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_STACKCREATED_ON_SETBITS ((STM32F4_LED3) << ON_SETBITS_SHIFT) +#define LED_STACKCREATED_ON_CLRBITS ((STM32F4_LED1|STM32F4_LED2|STM32F4_LED4) << ON_CLRBITS_SHIFT) +#define LED_STACKCREATED_OFF_SETBITS ((STM32F4_LED1|STM32F4_LED2) << OFF_SETBITS_SHIFT) +#define LED_STACKCREATED_OFF_CLRBITS ((STM32F4_LED3|STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_INIRQ_ON_SETBITS ((STM32F4_LED1) << ON_SETBITS_SHIFT) +#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_INIRQ_OFF_CLRBITS ((STM32F4_LED1) << OFF_CLRBITS_SHIFT) + +#define LED_SIGNAL_ON_SETBITS ((STM32F4_LED2) << ON_SETBITS_SHIFT) +#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_SIGNAL_OFF_CLRBITS ((STM32F4_LED2) << OFF_CLRBITS_SHIFT) + +#define LED_ASSERTION_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_ASSERTION_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +#define LED_PANIC_ON_SETBITS ((STM32F4_LED4) << ON_SETBITS_SHIFT) +#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT) +#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT) +#define LED_PANIC_OFF_CLRBITS ((STM32F4_LED4) << OFF_CLRBITS_SHIFT) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_ledbits[8] = +{ + (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + + (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + + (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + + (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + + (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + + (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + + (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + + (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void led_clrbits(unsigned int clrbits) +{ + if ((clrbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, false); + } + + if ((clrbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, false); + } + + if ((clrbits & STM32F4_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, false); + } + + if ((clrbits & STM32F4_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, false); + } +} + +static inline void led_setbits(unsigned int setbits) +{ + if ((setbits & STM32F4_LED1) != 0) + { + stm32_gpiowrite(GPIO_LED1, true); + } + + if ((setbits & STM32F4_LED2) != 0) + { + stm32_gpiowrite(GPIO_LED2, true); + } + + if ((setbits & STM32F4_LED3) != 0) + { + stm32_gpiowrite(GPIO_LED3, true); + } + + if ((setbits & STM32F4_LED4) != 0) + { + stm32_gpiowrite(GPIO_LED4, true); + } +} + +static void led_setonoff(unsigned int bits) +{ + led_clrbits(CLRBITS(bits)); + led_setbits(SETBITS(bits)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + led_setonoff(ON_BITS(g_ledbits[led])); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + led_setonoff(OFF_BITS(g_ledbits[led])); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c new file mode 100644 index 0000000000000..1ea43384fbf18 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "itm.h" + +#include "stm32.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + +#ifdef CONFIG_STM32_OTGFS + /* Initialize USB if the 1) OTG FS controller is in the configuration and + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. Presumably either CONFIG_USBDEV or + * CONFIG_USBHOST is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef HAVE_NETMONITOR + /* Configure board resources to support networking. */ + + if (stm32_netinitialize) + { + stm32_netinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..a9ea083a7065c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c @@ -0,0 +1,704 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#include "stm32.h" +#include "stm32_romfs.h" + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_SENSORS_APDS9960 +#include "stm32_apds9960.h" +#endif + +#ifdef CONFIG_SENSORS_MT6816 +#include "stm32_mt6816.h" +#endif + +#ifdef CONFIG_INPUT_MPR121_KEYPAD +#include "stm32_mpr121.h" +#endif + +#ifdef CONFIG_CL_MFRC522 +#include "stm32_mfrc522.h" +#endif + +#include "stm32f4discovery.h" + +/* Conditional logic in stm32f4discovery.h will determine if certain features + * are supported. Tests for these features need to be made after including + * stm32f4discovery.h. + */ + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +/* The following are includes from board-common logic */ + +#ifdef CONFIG_SENSORS_BMP180 +#include "stm32_bmp180.h" +#endif + +#ifdef CONFIG_RTC_DS1307 +#include "stm32_ds1307.h" +#endif + +#ifdef CONFIG_SENSORS_MS56XX +#include "stm32_ms5611.h" +#endif + +#ifdef CONFIG_SENSORS_MAX6675 +#include "stm32_max6675.h" +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK +#include "stm32_nunchuck.h" +#endif + +#ifdef CONFIG_INPUT_SBUTTON +#include "board_sbutton.h" +#endif + +#ifdef CONFIG_INPUT_KMATRIX +#include "stm32_kmatrix_gpio.h" +#endif + +#ifdef CONFIG_INPUT_KMATRIX_I2C +#include "stm32_kmatrix_i2c.h" +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS +#include "stm32_zerocross.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_BH1750FVI +#include "stm32_bh1750.h" +#endif + +#ifdef CONFIG_LIS3DSH +#include "stm32_lis3dsh.h" +#endif + +#ifdef CONFIG_LCD_BACKPACK +#include "stm32_lcd_backpack.h" +#endif + +#ifdef CONFIG_SENSORS_MAX31855 +#include "stm32_max31855.h" +#endif + +#ifdef CONFIG_SENSORS_MLX90614 +#include "stm32_mlx90614.h" +#endif + +#ifdef CONFIG_SENSORS_XEN1210 +#include "stm32_xen1210.h" +#endif + +#ifdef CONFIG_USBADB +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ + stm32_i2c_register(1); +#if 0 + stm32_i2c_register(1); + stm32_i2c_register(2); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + int ret = OK; + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Initialize the BMP180 pressure sensor. */ + + ret = board_bmp180_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_MS56XX + /* Initialize the MS5611 pressure sensor. */ + + ret = board_ms5611_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MS5611, error %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_BH1750FVI + ret = board_bh1750_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_bh1750initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_ZEROCROSS + /* Configure the zero-crossing driver */ + + board_zerocross_initialize(0); +#endif + +#ifdef CONFIG_SENSORS_MT6816 + /* Initialize MT6816 as /dev/qe0 on SPI1 */ + + ret = board_mt6816_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_mt6816_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LEDS_MAX7219 + ret = stm32_max7219init("/dev/numdisp0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: max7219_leds_register failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_MPR121_KEYPAD + /* Initialize MPR121 using I2C1 bus to /dev/keypad0 */ + + ret = board_mpr121_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_mpr121_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_ST7032 + ret = stm32_st7032init("/dev/slcd0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: st7032_register failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RGBLED + /* Configure the RGB LED driver */ + + stm32_rgbled_setup(); +#endif + +#if defined(CONFIG_PCA9635PW) + /* Initialize the PCA9635 chip */ + + ret = stm32_pca9635_initialize(); + if (ret < 0) + { + serr("ERROR: stm32_pca9635_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LCD_BACKPACK + /* slcd:0, i2c:1, rows=2, cols=16 */ + + ret = board_lcd_backpack_init(0, 1, 2, 16); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize PCF8574 LCD, error %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret != OK) + { + ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Initialize the MMC/SD SPI driver (SPI2 is used) */ + + ret = stm32_mmcsd_initialize(2, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + uerr("ERROR: Failed to start USB monitor: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + /* Initialize TIMER and register the TIMER device. */ + + ret = stm32_timer_driver_setup("/dev/timer0", CONFIG_STM32F4DISCO_TIMER); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_timer_driver_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAPTURE + /* Initialize Capture and register the Capture driver. */ + + ret = stm32_capture_setup("/dev/capture0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_capture_setup failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_DJOYSTICK + ret = stm32_djoy_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to register djoystick driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_KMATRIX + /* Initialize and register the keyboard matrix driver */ + + ret = board_kmatrix_initialize(CONFIG_INPUT_KMATRIX_DEVPATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_kmatrix_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_KMATRIX_I2C + /* Initialize and register the keyboard matrix driver via I2C expander */ + + ret = board_kmatrix_i2c_initialize("/dev/kbd0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_kmatrix_i2c_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_INPUT_NUNCHUCK + /* Register the Nunchuck driver */ + + ret = board_nunchuck_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nunchuck_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MLX90614 + ret = board_mlx90614_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MLX90614, error %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32_QE) && defined(CONFIG_SENSORS_QENCODER) + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32F4DISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_SBUTTON + /* Register the Single Button Dual Action driver */ + + ret = board_sbutton_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_sbtn_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_APDS9960 + /* Register the APDS-9960 gesture sensor */ + + ret = board_apds9960_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_RTC_DS1307 + ret = board_ds1307_initialize(1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize DS1307 RTC driver: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + serr("ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + +#ifdef HAVE_CS43L22 + /* Configure CS43L22 audio */ + + ret = stm32_cs43l22_initialize(1); + if (ret != OK) + { + serr("Failed to initialize CS43L22 audio: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX31855 + /* Register device 0 on spi channel 2 */ + + ret = board_max31855_initialize(0, 2); + if (ret < 0) + { + serr("ERROR: stm32_max31855initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MAX6675 + ret = board_max6675_initialize(0, 2); + if (ret < 0) + { + serr("ERROR: stm32_max6675initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_STM32_ROMFS + ret = stm32_romfs_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_SENSORS_XEN1210 + ret = board_xen1210_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: xen1210_archinitialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_LIS3DSH + /* Create a lis3dsh driver instance fitting the chip built into + * stm32f4discovery + */ + + ret = board_lis3dsh_initialize(0, 1); + if (ret < 0) + { + serr("ERROR: Failed to initialize LIS3DSH driver: %d\n", ret); + } +#endif + +#ifdef HAVE_HCIUART + ret = hciuart_dev_initialize(); + if (ret < 0) + { + serr("ERROR: Failed to initialize HCI UART driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_WL_GS2200M + ret = stm32_gs2200m_initialize("/dev/gs2200m", 3); + if (ret < 0) + { + serr("ERROR: Failed to initialize GS2200M: %d\n", ret); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver:" + " %d\n", ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + +#ifdef CONFIG_USBADB + usbdev_adb_initialize(); +#endif + +#ifdef CONFIG_CL_MFRC522 + ret = stm32_mfrc522initialize("/dev/rfid0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..db8e7e3f5e0ad --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F4 Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c new file mode 100644 index 0000000000000..18a72d54f8a30 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_capture.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c index df94bdee2a6e1..f3e15b471d022 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_capture.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c new file mode 100644 index 0000000000000..55103ee912e34 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c @@ -0,0 +1,349 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_otgfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define COMPOSITE0_DEV (3) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instance previously given to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite0_connect(int port) +{ + struct composite_devdesc_s dev[COMPOSITE0_DEV]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int dev_idx = 0; + int epin = 1; + int epout = 1; + +#ifdef CONFIG_RNDIS_COMPOSITE + /* Configure the RNDIS USB device */ + + /* Ask the rndis driver to fill in the constants we didn't + * know here. + */ + + usbdev_rndis_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; + dev[dev_idx].minor = 0; + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[dev_idx].classobject = board_mscclassobject; + dev[dev_idx].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[dev_idx].classobject = cdcacm_classobject; + dev[dev_idx].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Sanity checks */ + + DEBUGASSERT(epin < STM32_NENDPOINTS); + DEBUGASSERT(epout < STM32_NENDPOINTS); + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + else + { + return NULL; + } +} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c index 32949202cf499..a50ef41c344b6 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c new file mode 100644 index 0000000000000..aa9fe97748a12 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c @@ -0,0 +1,299 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_INPUT_DJOYSTICK + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of Joystick discretes 5-WAY */ + +#define DJOY_NGPIOS 5 + +/* Bitset of supported Joystick discretes */ + +#define DJOY_SUPPORTED (DJOY_UP_BIT | DJOY_DOWN_BIT | DJOY_LEFT_BIT | \ + DJOY_RIGHT_BIT | DJOY_BUTTON_SELECT_BIT) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower); +static djoy_buttonset_t + djoy_sample(const struct djoy_lowerhalf_s *lower); +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg); + +static void djoy_disable(void); +static int djoy_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each Olimex-P407 joystick "button." Index using + * DJOY_* definitions in include/nuttx/input/djoystick.h. + */ + +static const uint16_t g_joygpio[DJOY_NGPIOS] = +{ + GPIO_JOY_UP, GPIO_JOY_DOWN, GPIO_JOY_LEFT, GPIO_JOY_RIGHT, GPIO_JOY_CENTER +}; + +/* Current interrupt handler and argument */ + +static djoy_interrupt_t g_djoyhandler; +static void *g_djoyarg; + +/* This is the discrete joystick lower half driver interface */ + +static const struct djoy_lowerhalf_s g_djoylower = +{ + .dl_supported = djoy_supported, + .dl_sample = djoy_sample, + .dl_enable = djoy_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: djoy_supported + * + * Description: + * Return the set of buttons supported on the discrete joystick device + * + ****************************************************************************/ + +static djoy_buttonset_t + djoy_supported(const struct djoy_lowerhalf_s *lower) +{ + iinfo("Supported: %02x\n", DJOY_SUPPORTED); + return (djoy_buttonset_t)DJOY_SUPPORTED; +} + +/**************************************************************************** + * Name: djoy_sample + * + * Description: + * Return the current state of all discrete joystick buttons + * + ****************************************************************************/ + +static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) +{ + djoy_buttonset_t ret = 0; + int i; + + /* Read each joystick GPIO value */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + bool released = stm32_gpioread(g_joygpio[i]); + if (!released) + { + ret |= (1 << i); + } + } + + iinfo("Retuning: %02x\n", DJOY_SUPPORTED); + return ret; +} + +/**************************************************************************** + * Name: djoy_enable + * + * Description: + * Enable interrupts on the selected set of joystick buttons. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void djoy_enable(const struct djoy_lowerhalf_s *lower, + djoy_buttonset_t press, djoy_buttonset_t release, + djoy_interrupt_t handler, void *arg) +{ + irqstate_t flags; + djoy_buttonset_t either = press | release; + djoy_buttonset_t bit; + bool rising; + bool falling; + int i; + + /* Start with all interrupts disabled */ + + flags = enter_critical_section(); + djoy_disable(); + + iinfo("press: %02x release: %02x handler: %p arg: %p\n", + press, release, handler, arg); + + /* If no events are indicated or if no handler is provided, then this + * must really be a request to disable interrupts. + */ + + if (either && handler) + { + /* Save the new the handler and argument */ + + g_djoyhandler = handler; + g_djoyarg = arg; + + /* Check each GPIO. */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + /* Enable interrupts on each pin that has either a press or + * release event associated with it. + */ + + bit = (1 << i); + if ((either & bit) != 0) + { + /* Active low so a press corresponds to a falling edge and + * a release corresponds to a rising edge. + */ + + falling = ((press & bit) != 0); + rising = ((release & bit) != 0); + + iinfo("GPIO %d: rising: %d falling: %d\n", + i, rising, falling); + + stm32_gpiosetevent(g_joygpio[i], rising, falling, + true, djoy_interrupt, NULL); + } + } + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: djoy_disable + * + * Description: + * Disable all joystick interrupts + * + ****************************************************************************/ + +static void djoy_disable(void) +{ + irqstate_t flags; + int i; + + /* Disable each joystick interrupt */ + + flags = enter_critical_section(); + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + } + + leave_critical_section(flags); + + /* Nullify the handler and argument */ + + g_djoyhandler = NULL; + g_djoyarg = NULL; +} + +/**************************************************************************** + * Name: djoy_interrupt + * + * Description: + * Discrete joystick interrupt handler + * + ****************************************************************************/ + +static int djoy_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_djoyhandler); + if (g_djoyhandler) + { + g_djoyhandler(&g_djoylower, g_djoyarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_djoy_initialize + * + * Description: + * Initialize and register the discrete joystick driver + * + ****************************************************************************/ + +int stm32_djoy_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE: This is unnecessary for + * interrupting pins since it will also be done by stm32_gpiosetevent(). + */ + + for (i = 0; i < DJOY_NGPIOS; i++) + { + stm32_configgpio(g_joygpio[i]); + } + + /* Make sure that all interrupts are disabled */ + + djoy_disable(); + + /* Register the joystick device as /dev/djoy0 */ + + return djoy_register("/dev/djoy0", &g_djoylower); +} + +#endif /* CONFIG_INPUT_DJOYSTICK */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c new file mode 100644 index 0000000000000..1f81619aed881 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c @@ -0,0 +1,219 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* 2MBit SPI FLASH OR ENC28J60 + * + * -- ---- ------------ ----------------------------------------------------- + * PIN NAME SIGNAL NOTES + * -- ---- ------------ ----------------------------------------------------- + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_spi.h" + +#include "stm32f4discovery.h" + +#ifdef CONFIG_ENC28J60 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* ENC28J60 + * + * --- ------ -------------- ------------------------------------------------ + * PIN NAME SIGNAL NOTES + * --- ------ -------------- ------------------------------------------------ + * + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, + * 10Mbit EN28J60 Reset + * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt + */ + +/* ENC28J60 is on SPI1 */ + +#ifndef CONFIG_STM32_SPI1 +# error "Need CONFIG_STM32_SPI1 in the configuration" +#endif + +/* SPI Assumptions **********************************************************/ + +#define ENC28J60_SPI_PORTNO 1 /* On SPI1 */ +#define ENC28J60_DEVNO 0 /* Only one ENC28J60 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_lower_s +{ + const struct enc_lower_s lower; /* Low-level MCU interface */ + xcpt_t handler; /* ENC28J60 interrupt handler */ + void *arg; /* Argument that accompanies the interrupt */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg); +static void up_enable(const struct enc_lower_s *lower); +static void up_disable(const struct enc_lower_s *lower); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The ENC28J60 normal provides interrupts to the MCU via a GPIO pin. The + * following structure provides an MCU-independent mechanixm for controlling + * the ENC28J60 GPIO interrupt. + */ + +static struct stm32_lower_s g_enclower = +{ + .lower = + { + .attach = up_attach, + .enable = up_enable, + .disable = up_disable + }, + .handler = NULL, + .arg = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: struct enc_lower_s methods + ****************************************************************************/ + +static int up_attach(const struct enc_lower_s *lower, xcpt_t handler, + void *arg) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +static void up_enable(const struct enc_lower_s *lower) +{ + struct stm32_lower_s *priv = (struct stm32_lower_s *)lower; + + DEBUGASSERT(priv->handler); + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + priv->handler, priv->arg); +} + +/* REVISIT: Since the interrupt is completely torn down, not just disabled, + * in interrupt requests that occurs while the interrupt is disabled will be + * lost. + */ + +static void up_disable(const struct enc_lower_s *lower) +{ + stm32_gpiosetevent(GPIO_ENC28J60_INTR, false, true, true, + NULL, NULL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +void arm_netinitialize(void) +{ + struct spi_dev_s *spi; + int ret; + + /* Assumptions: + * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. + */ + + spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); + if (!spi) + { + nerr("ERROR: Failed to initialize SPI port %d\n", ENC28J60_SPI_PORTNO); + return; + } + + /* Take ENC28J60 out of reset (active low) */ + + stm32_gpiowrite(GPIO_ENC28J60_RESET, true); + + /* Bind the SPI port to the ENC28J60 driver */ + + ret = enc_initialize(spi, &g_enclower.lower, ENC28J60_DEVNO); + if (ret < 0) + { + nerr("ERROR: Failed to bind SPI port %d ENC28J60 device %d: %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO, ret); + return; + } + + ninfo("Bound SPI port %d to ENC28J60 device %d\n", + ENC28J60_SPI_PORTNO, ENC28J60_DEVNO); +} + +#endif /* CONFIG_ENC28J60 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c index 88cf550586e01..7907bedf1a2b9 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c new file mode 100644 index 0000000000000..5342769613125 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# warning "FSMC is not enabled" +#endif + +#if STM32_NGPIO_PORTS < 6 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FSMC_NADDRCONFIGS 26 +#define STM32_FSMC_NDATACONFIGS 16 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] = +{ + GPIO_FSMC_A0, GPIO_FSMC_A1, GPIO_FSMC_A2, + GPIO_FSMC_A3, GPIO_FSMC_A4, GPIO_FSMC_A5, + GPIO_FSMC_A6, GPIO_FSMC_A7, GPIO_FSMC_A8, + GPIO_FSMC_A9, GPIO_FSMC_A10, GPIO_FSMC_A11, + GPIO_FSMC_A12, GPIO_FSMC_A13, GPIO_FSMC_A14, + GPIO_FSMC_A15, GPIO_FSMC_A16, GPIO_FSMC_A17, + GPIO_FSMC_A18, GPIO_FSMC_A19, GPIO_FSMC_A20, + GPIO_FSMC_A21, GPIO_FSMC_A22, GPIO_FSMC_A23, + GPIO_FSMC_A24, GPIO_FSMC_A25 +}; + +static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] = +{ + GPIO_FSMC_D0, GPIO_FSMC_D1, GPIO_FSMC_D2, + GPIO_FSMC_D3, GPIO_FSMC_D4, GPIO_FSMC_D5, + GPIO_FSMC_D6, GPIO_FSMC_D7, GPIO_FSMC_D8, + GPIO_FSMC_D9, GPIO_FSMC_D10, GPIO_FSMC_D11, + GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, + GPIO_FSMC_D15 +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ****************************************************************************/ + +void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/**************************************************************************** + * Name: stm32_extmemaddr + * + * Description: + * Initialize address line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemaddr(int naddrs) +{ + stm32_extmemgpios(g_addressconfig, naddrs); +} + +/**************************************************************************** + * Name: stm32_extmemdata + * + * Description: + * Initialize data line GPIOs for external memory access + * + ****************************************************************************/ + +void stm32_extmemdata(int ndata) +{ + stm32_extmemgpios(g_dataconfig, ndata); +} diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c index e53aba34f5b9e..44a5d77c1d835 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c index 899face28a1df..12ac1ef084b75 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c new file mode 100644 index 0000000000000..17a22bd612563 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c new file mode 100644 index 0000000000000..b32240a9bdc24 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c @@ -0,0 +1,260 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32_rcc.h" +#include "stm32_exti.h" + +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode */ + +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 3 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void stm32_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + sinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + flags = enter_critical_section(); + + /* Force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + + /* No state change... */ + + goto errout; + } + + /* Then perform board-specific, state-dependent logic here */ + + switch (newstate) + { + case PM_NORMAL: + { + } + break; + + case PM_IDLE: + { + } + break; + + case PM_STANDBY: + { +#ifdef CONFIG_RTC_ALARM + /* Disable RTC Alarm interrupt */ + +#warning "missing logic" + + /* Configure the RTC alarm to Auto Wake the system */ + +#warning "missing logic" + + /* The tv_nsec value must not exceed 1,000,000,000. That + * would be an invalid time. + */ + +#warning "missing logic" + + /* Set the alarm */ + +#warning "missing logic" +#endif + /* Call the STM32 stop mode */ + + stm32_pmstop(true); + + /* We have been re-awakened by some even: A button press? + * An alarm? Cancel any pending alarm and resume the normal + * operation. + */ + +#ifdef CONFIG_RTC_ALARM +#warning "missing logic" +#endif + /* Resume normal operation */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); + newstate = PM_NORMAL; + } + break; + + case PM_SLEEP: + { + /* We should not return from standby mode. The only way out + * of standby is via the reset path. + */ + + stm32_pmstandby(); + } + break; + + default: + break; + } + + /* Save the new state */ + + oldstate = newstate; + +errout: + leave_critical_section(flags); + } +} +#else +# define stm32_idlepm() +#endif + +/**************************************************************************** + * Name: up_alarmcb + * + * Description: + * RTC alarm service routine + * + ****************************************************************************/ + +#if 0 /* Not used */ +static void up_alarmcb(void) +{ + /* This alarm occurs because there wasn't any EXTI interrupt during the + * PM_STANDBY period. So just go to sleep. + */ + + pm_changestate(PM_IDLE_DOMAIN, PM_SLEEP); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + BEGIN_IDLE(); + stm32_idlepm(); + END_IDLE(); +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c new file mode 100644 index 0000000000000..b3cd7b43f6c55 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_NX_LCDDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LCD_SPI_PORTNO 1 /* On SPI1 */ + +#ifndef CONFIG_LCD_CONTRAST +# define CONFIG_LCD_CONTRAST 60 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct spi_dev_s *g_spidev; +struct lcd_dev_s *g_lcddev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); + + if (g_spidev == NULL) + { + lcderr("ERROR: Failed to initialize SPI port %d\n", LCD_SPI_PORTNO); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + g_lcddev = max7219_initialize(g_spidev, lcddev); + if (!g_lcddev) + { + lcderr("ERROR: Failed to bind SPI port 1 to LCD %d\n", lcddev); + } + else + { + lcdinfo("SPI port 1 bound to LCD %d\n", lcddev); + + return g_lcddev; + } + + return NULL; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} + +#endif /* CONFIG_NX_LCDDRIVER */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c index de429e9f91a13..4062a4006ba0a 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c new file mode 100644 index 0000000000000..1118bb880c6ed --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spi1register + * + * Description: + * Registers media change callback + ****************************************************************************/ + +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, + void *arg) +{ + /* TODO: media change callback */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_mmcsd_initialize + * + * Description: + * Initialize SPI-based SD card and card detect thread. + ****************************************************************************/ + +int stm32_mmcsd_initialize(int port, int minor) +{ + struct spi_dev_s *spi; + int rv; + + stm32_configgpio(GPIO_MMCSD_NCD); /* Assign SD_DET */ + stm32_configgpio(GPIO_MMCSD_NSS); /* Assign CS */ + stm32_gpiowrite(GPIO_MMCSD_NSS, 1); /* Ensure the CS is inactive */ + + mcinfo("INFO: Initializing mmcsd port %d minor %d\n", + port, minor); + + spi = stm32_spibus_initialize(port); + if (spi == NULL) + { + mcerr("ERROR: Failed to initialize SPI port %d\n", port); + return -ENODEV; + } + + rv = mmcsd_spislotinitialize(minor, minor, spi); + if (rv < 0) + { + mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n", + port, minor); + return rv; + } + + spiinfo("INFO: mmcsd card has been initialized successfully\n"); + return OK; +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c new file mode 100644 index 0000000000000..12e0b8aa0d9c0 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c @@ -0,0 +1,41 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + ****************************************************************************/ + +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +} +#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c index b5f8c9935abd6..fabe0a26b574f 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c new file mode 100644 index 0000000000000..1a490e035955f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "stm32_pm.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pminitialize + * + * Description: + * This function is called by MCU-specific logic at power-on reset in + * order to provide one-time initialization the power management subsystem. + * This function must be called *very* early in the initialization sequence + * *before* any other device drivers are initialized (since they may + * attempt to register with the power management subsystem). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void arm_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); + +#if defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + /* Initialize the buttons to wake up the system from low power modes */ + + stm32_pm_buttons(); +#endif + + /* Initialize the LED PM */ + + stm32_led_pminitialize(); +} + +#endif /* CONFIG_PM */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c new file mode 100644 index 0000000000000..bde3abd4658d5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "nvic.h" +#include "stm32_pwr.h" +#include "stm32_pm.h" +#include "stm32f4discovery.h" + +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_IDLE_CUSTOM) && defined(CONFIG_PM_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_ARCH_BUTTONS +# error "CONFIG_ARCH_BUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_ARCH_IRQBUTTONS +# warning "CONFIG_ARCH_IRQBUTTONS is not defined in the configuration" +#endif + +#ifndef CONFIG_PM_BUTTON_ACTIVITY +# define CONFIG_PM_BUTTON_ACTIVITY 10 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +static int button_handler(int irq, void *context, void *arg); +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: button_handler + * + * Description: + * Handle a button wake-up interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +static int button_handler(int irq, void *context, void *arg) +{ + /* At this point the MCU should have already awakened. The state + * change will be handled in the IDLE loop when the system is re-awakened + * The button interrupt handler should be totally ignorant of the PM + * activities and should report button activity as if nothing + * special happened. + */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_PM_BUTTON_ACTIVITY); + return OK; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pm_buttons + * + * Description: + * Configure the user button of the STM32f4discovery board as EXTI, + * so it is able to wakeup the MCU from the PM_STANDBY mode + * + ****************************************************************************/ + +void stm32_pm_buttons(void) +{ + /* Initialize the button GPIOs */ + + board_button_initialize(); + +#ifdef CONFIG_ARCH_IRQBUTTONS + board_button_irq(0, button_handler, NULL); +#endif +} + +#endif /* CONFIG_PM && CONFIG_ARCH_IDLE_CUSTOM && CONFIG_PM_BUTTONS)*/ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..29fe4fe38db82 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32f4discovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. This pin is used by + * FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM4_CHANNEL) || CONFIG_STM32_TIM4_CHANNEL != STM32F4DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F4DISCOVERY_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c new file mode 100644 index 0000000000000..8381b158e684b --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c new file mode 100644 index 0000000000000..dc245cd37389f --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f4discovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_RGBLED 1 + +#ifndef CONFIG_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM2_PWM +# undef HAVE_RGBLED +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_RGBLED +#endif + +#ifdef HAVE_RGBLED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rgbled_setup + * + * Description: + * Configure the RGB LED. + * + ****************************************************************************/ + +int stm32_rgbled_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *ledr; + struct pwm_lowerhalf_s *ledg; + struct pwm_lowerhalf_s *ledb; + struct pwm_info_s info; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledr = stm32_pwminitialize(1); + if (!ledr) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDR\n"); + return -ENODEV; + } + + /* Define frequency and duty cycle */ + + info.frequency = 100; + info.channels[0].duty = 0; + + /* Initialize LED R */ + + ledr->ops->setup(ledr); + ledr->ops->start(ledr, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledg = stm32_pwminitialize(2); + if (!ledg) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDG\n"); + return -ENODEV; + } + + /* Initialize LED G */ + + ledg->ops->setup(ledg); + ledg->ops->start(ledg, &info); + + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + ledb = stm32_pwminitialize(3); + if (!ledb) + { + lederr("ERROR: Failed to get the STM32 PWM lower half to LEDB\n"); + return -ENODEV; + } + + /* Initialize LED B */ + + ledb->ops->setup(ledb); + ledb->ops->start(ledb, &info); + + /* Register the RGB LED diver at "/dev/rgbled0" */ + + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + 1, CONFIG_STM32_TIM2_CHANNEL, + CONFIG_STM32_TIM3_CHANNEL); + if (ret < 0) + { + lederr("ERROR: rgbled_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#else +# error "HAVE_RGBLED is undefined" +#endif /* HAVE_RGBLED */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h new file mode 100644 index 0000000000000..7cfb268ae3d6d --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H +#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_STM32_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void); + +#endif /* CONFIG_STM32_ROMFS */ + +#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c new file mode 100644 index 0000000000000..2814a9eb8e1bd --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c + * This file provides contents of an optional ROMFS volume, mounted at boot. + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. + * SPDX-FileContributor: Tomasz Wozniak + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "stm32_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" +#else + +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + ".section .rodata, \"a\"\n" + ".balign 16\n" + ".globl romfs_data_begin\n" +"romfs_data_begin:\n" + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ + \ + ".balign " STR(ROMFS_SECTOR_SIZE) "\n" + ".globl romfs_data_end\n" +"romfs_data_end:\n"); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above (l. 84). + * + ****************************************************************************/ + +int stm32_romfs_initialize(void) +{ + size_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c new file mode 100644 index 0000000000000..a65801e5b3451 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c @@ -0,0 +1,161 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef HAVE_SDIO + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *arg) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* HAVE_SDIO */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c new file mode 100644 index 0000000000000..dac42a7b178c5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c @@ -0,0 +1,376 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" + +#include "stm32f4discovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f4discovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_ENC28J60 + stm32_configgpio(GPIO_ENC28J60_CS); + stm32_configgpio(GPIO_ENC28J60_RESET); + stm32_configgpio(GPIO_ENC28J60_INTR); +#endif + +#ifdef CONFIG_NET_W5500 + stm32_configgpio(GPIO_W5500_CS); + stm32_configgpio(GPIO_W5500_RESET); + stm32_configgpio(GPIO_W5500_INTR); +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_LIS3MDL) + stm32_configgpio(GPIO_CS_MEMS); /* MEMS chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_CL_MFRC522) + stm32_configgpio(GPIO_CS_MFRC522); /* MFRC522 chip select */ +#endif + +#if defined(CONFIG_STM32_SPI1) && defined(CONFIG_SENSORS_MT6816) + stm32_configgpio(GPIO_CS_MT6816); +#endif + +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX31855) + stm32_configgpio(GPIO_MAX31855_CS); /* MAX31855 chip select */ +#endif +#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) + stm32_configgpio(GPIO_MAX7219_CS); /* MAX7219 chip select */ +#endif +#ifdef CONFIG_LPWAN_SX127X + stm32_configgpio(GPIO_SX127X_CS); /* SX127x chip select */ +#endif + +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7567) + stm32_configgpio(STM32_LCD_CS); /* ST7567/ST7789 chip select */ +#endif +#if defined(CONFIG_STM32_SPI2) && defined(CONFIG_SENSORS_MAX6675) + stm32_configgpio(GPIO_MAX6675_CS); /* MAX6675 chip select */ +#endif +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ +# if defined(CONFIG_LCD_UG2864AMBAG01) + stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) + stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ +# endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#ifdef CONFIG_ENC28J60 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_ENC28J60_CS, !selected); + } +#endif + +#ifdef CONFIG_NET_W5500 + if (devid == SPIDEV_ETHERNET(0)) + { + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_W5500_CS, !selected); + } +#endif + +#ifdef CONFIG_LPWAN_SX127X + if (devid == SPIDEV_LPWAN(0)) + { + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(STM32_LCD_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_MAX7219) || defined(CONFIG_LEDS_MAX7219) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_MAX7219_CS, !selected); + } +#endif + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + stm32_gpiowrite(GPIO_OLED_CS, !selected); + } +#endif + +#if defined (CONFIG_SENSORS_LIS3MDL) + if (devid == SPIDEV_ACCELEROMETER(0)) + { + stm32_gpiowrite(GPIO_CS_MEMS, !selected); + } +#endif + +#if defined (CONFIG_SENSORS_MT6816) + if (devid == SPIDEV_MAG_ENCODER(0)) + { + stm32_gpiowrite(GPIO_CS_MT6816, !selected); + } +#endif + +#if defined(CONFIG_CL_MFRC522) + if (devid == SPIDEV_CONTACTLESS(0)) + { + stm32_gpiowrite(GPIO_CS_MFRC522, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + +#ifdef CONFIG_LPWAN_SX127X + if (devid == SPIDEV_LPWAN(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_SENSORS_MAX31855) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX31855_CS, !selected); + } +#endif + +#if defined(CONFIG_SENSORS_MAX6675) + if (devid == SPIDEV_TEMPERATURE(0)) + { + stm32_gpiowrite(GPIO_MAX6675_CS, !selected); + } +#endif + +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_MMCSD_NSS, !selected); + } +#endif +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t ret = 0; +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + /* Note: SD_DET is pulled high when there's no SD card present. */ + + ret = stm32_gpioread(GPIO_MMCSD_NCD) ? 0 : 1; + } +#endif + + return ret; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_WL_GS2200M) + if (devid == SPIDEV_WIRELESS(0)) + { + stm32_gpiowrite(GPIO_GS2200M_CS, !selected); + } +#endif +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_ST7567) || defined(CONFIG_LCD_ST7789) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(STM32_LCD_RS, !cmd); + + return OK; + } +#endif + +#if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ + defined(CONFIG_LCD_SSD1351) + if (devid == SPIDEV_DISPLAY(0)) + { + /* "This is the Data/Command control pad which determines whether the + * data bits are data or a command. + * + * A0 = "H": the inputs at D0 to D7 are treated as display data. + * A0 = "L": the inputs at D0 to D7 are transferred to the command + * registers." + */ + +# if defined(CONFIG_LCD_UG2864AMBAG01) + stm32_gpiowrite(GPIO_OLED_A0, !cmd); +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) + stm32_gpiowrite(GPIO_OLED_DC, !cmd); +# endif + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c new file mode 100644 index 0000000000000..f01e75e149434 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c @@ -0,0 +1,390 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_LCD_SSD1289 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_FSMC +# error "CONFIG_STM32_FSMC is required to use the LCD" +#endif + +/* STM32F4Discovery LCD Hardware Definitions ********************************/ + +/* LCD /CS is CE1 == NOR/SRAM Bank 1 + * + * Bank 1 = 0x60000000 | 0x00000000 + * Bank 2 = 0x60000000 | 0x04000000 + * Bank 3 = 0x60000000 | 0x08000000 + * Bank 4 = 0x60000000 | 0x0c000000 + * + * FSMC address bit 16 is used to distinguish command and data. + * FSMC address bits 0-24 correspond to ARM address bits 1-25. + */ + +#define STM32_LCDBASE ((uintptr_t)(0x60000000 | 0x00000000)) +#define LCD_INDEX (STM32_LCDBASE) +#define LCD_DATA (STM32_LCDBASE + 0x00020000) + +/* SRAM pin definitions */ + +#define LCD_NADDRLINES 1 /* A16 */ +#define LCD_NDATALINES 16 /* D0-15 */ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Low Level LCD access */ + +static void stm32_select(struct ssd1289_lcd_s *dev); +static void stm32_deselect(struct ssd1289_lcd_s *dev); +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index); +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev); +#endif +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data); +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LCD pin mapping + * MAPPING TO STM32 F4: + * + * ---------------- ------------- ---------------------------------- + * STM32 FUNCTION LCD PIN STM32F4Discovery PIN + * ---------------- ------------- ---------------------------------- + * FSMC_D0 D0 pin 4 PD14 P1 pin 46 Conflict (Note 1) + * FSMC_D1 D1 pin 3 PD15 P1 pin 47 Conflict (Note 2) + * FSMC_D2 D2 pin 6 PD0 P2 pin 36 Free I/O + * FSMC_D3 D3 pin 5 PD1 P2 pin 33 Free I/O + * FSMC_D4 D4 pin 8 PE7 P1 pin 25 Free I/O + * FSMC_D5 D5 pin 7 PE8 P1 pin 26 Free I/O + * FSMC_D6 D6 pin 10 PE9 P1 pin 27 Free I/O + * FSMC_D7 D7 pin 9 PE10 P1 pin 28 Free I/O + * FSMC_D8 D8 pin 12 PE11 P1 pin 29 Free I/O + * FSMC_D9 D9 pin 11 PE12 P1 pin 30 Free I/O + * FSMC_D10 D10 pin 14 PE13 P1 pin 31 Free I/O + * FSMC_D11 D11 pin 13 PE14 P1 pin 32 Free I/O + * FSMC_D12 D12 pin 16 PE15 P1 pin 33 Free I/O + * FSMC_D13 D13 pin 15 PD8 P1 pin 40 Free I/O + * FSMC_D14 D14 pin 18 PD9 P1 pin 41 Free I/O + * FSMC_D15 D15 pin 17 PD10 P1 pin 42 Free I/O + * FSMC_A16 RS pin 19 PD11 P1 pin 27 Free I/O + * FSMC_NE1 ~CS pin 10 PD7 P2 pin 27 Free I/O + * FSMC_NWE ~WR pin 22 PD5 P2 pin 29 Conflict (Note 3) + * FSMC_NOE ~RD pin 21 PD4 P2 pin 32 Conflict (Note 4) + * PC6 RESET pin 24 PC6 P2 pin 47 Free I/O + * ---------------- ------------- ---------------------------------- + * + * 1 Used for the RED LED + * 2 Used for the BLUE LED + * 3 Used for the RED LED and for OTG FS Overcurrent. It may be okay to + * use for the parallel interface if PC0 is held high (or floating). + * PC0 enables the STMPS2141STR IC power switch that drives the OTG FS + * host VBUS. + * 4 Also the reset pin for the CS43L22 audio Codec. + */ + +#define GPIO_LCD_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6) + +/* GPIO configurations unique to the LCD */ + +static const uint32_t g_lcdconfig[] = +{ + /* PC6(RESET), FSMC_A16, FSMC_NOE, FSMC_NWE, and FSMC_NE1 */ + + GPIO_LCD_RESET, GPIO_FSMC_A16, GPIO_FSMC_NOE, GPIO_FSMC_NWE, GPIO_FSMC_NE1 +}; +#define NLCD_CONFIG (sizeof(g_lcdconfig)/sizeof(uint32_t)) + +/* This is the driver state structure + * (there is no retained state information) + */ + +static struct ssd1289_lcd_s g_ssd1289 = +{ + .select = stm32_select, + .deselect = stm32_deselect, + .index = stm32_index, +#ifndef CONFIG_SSD1289_WRONLY + .read = stm32_read, +#endif + .write = stm32_write, + .backlight = stm32_backlight +}; + +/* The saved instance of the LCD driver */ + +static struct lcd_dev_s *g_ssd1289drvr; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_select + * + * Description: + * Select the LCD device + * + ****************************************************************************/ + +static void stm32_select(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * De-select the LCD device + * + ****************************************************************************/ + +static void stm32_deselect(struct ssd1289_lcd_s *dev) +{ + /* Does not apply to this hardware */ +} + +/**************************************************************************** + * Name: stm32_deselect + * + * Description: + * Set the index register + * + ****************************************************************************/ + +static void stm32_index(struct ssd1289_lcd_s *dev, uint8_t index) +{ + putreg16((uint16_t)index, LCD_INDEX); +} + +/**************************************************************************** + * Name: stm32_read + * + * Description: + * Read LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +#ifndef CONFIG_SSD1289_WRONLY +static uint16_t stm32_read(struct ssd1289_lcd_s *dev) +{ + return getreg16(LCD_DATA); +} +#endif + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_write(struct ssd1289_lcd_s *dev, uint16_t data) +{ + putreg16((uint16_t)data, LCD_DATA); +} + +/**************************************************************************** + * Name: stm32_write + * + * Description: + * Write LCD data (GRAM data or register contents) + * + ****************************************************************************/ + +static void stm32_backlight(struct ssd1289_lcd_s *dev, int power) +{ +#warning "Missing logic" +} + +/**************************************************************************** + * Name: stm32_selectlcd + * + * Description: + * Initialize to the LCD + * + ****************************************************************************/ + +void stm32_selectlcd(void) +{ + /* Configure GPIO pins */ + + stm32_extmemdata(LCD_NDATALINES); /* Common data lines: D0-D15 */ + stm32_extmemgpios(g_lcdconfig, NLCD_CONFIG); /* LCD-specific control lines */ + + /* Enable AHB clocking to the FSMC */ + + stm32_fsmc_enable(); + + /* Color LCD configuration (LCD configured as follow): + * + * - Data/Address MUX = Disable "FSMC_BCR_MUXEN" just not enable it. + * - Extended Mode = Disable "FSMC_BCR_EXTMOD" + * - Memory Type = SRAM "FSMC_BCR_SRAM" + * - Data Width = 16bit "FSMC_BCR_MWID16" + * - Write Operation = Enable "FSMC_BCR_WREN" + * - Asynchronous Wait = Disable + */ + + /* Bank1 NOR/SRAM control register configuration */ + + putreg32(FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); + + /* Bank1 NOR/SRAM timing register configuration */ + + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(1) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(1) | + FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); + + putreg32(0xffffffff, STM32_FSMC_BWTR1); + + /* Enable the bank by setting the MBKEN bit */ + + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR1); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + * + * Description: + * Initialize the LCD video hardware. The initial state of the LCD is fully + * initialized, display memory cleared, and the LCD ready to use, but with + * the power setting at 0 (full off). + * + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + /* Only initialize the driver once */ + + if (!g_ssd1289drvr) + { + lcdinfo("Initializing\n"); + + /* Configure GPIO pins and configure the FSMC to support the LCD */ + + stm32_selectlcd(); + + /* Reset the LCD (active low) */ + + stm32_gpiowrite(GPIO_LCD_RESET, false); + up_mdelay(5); + stm32_gpiowrite(GPIO_LCD_RESET, true); + + /* Configure and enable the LCD */ + + up_mdelay(50); + g_ssd1289drvr = ssd1289_lcdinitialize(&g_ssd1289); + if (!g_ssd1289drvr) + { + lcderr("ERROR: ssd1289_lcdinitialize failed\n"); + return -ENODEV; + } + } + + /* Clear the display (setting it to the color 0=black) */ + +#if 0 /* Already done in the driver */ + ssd1289_clear(g_ssd1289drvr, 0); +#endif + + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + * + * Description: + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. + * + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int lcddev) +{ + DEBUGASSERT(lcddev == 0); + return g_ssd1289drvr; +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + * + * Description: + * Uninitialize the LCD support + * + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* Turn the display off */ + + g_ssd1289drvr->setpower(g_ssd1289drvr, 0); +} + +#endif /* CONFIG_LCD_SSD1289 */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c new file mode 100644 index 0000000000000..d11616999a4fc --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "stm32f4discovery.h" + +#ifdef CONFIG_LCD_SSD1351 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* The pin configurations here require that SPI1 is selected */ + +#ifndef CONFIG_STM32_SPI1 +# error "The OLED driver requires CONFIG_STM32_SPI1 in the configuration" +#endif + +#ifndef CONFIG_SSD1351_SPI4WIRE +# error "The configuration requires the SPI 4-wire interface" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_graphics_setup + * + * Description: + * Called by NX initialization logic to configure the OLED. + * + ****************************************************************************/ + +struct lcd_dev_s *board_graphics_setup(unsigned int devno) +{ + struct spi_dev_s *spi; + struct lcd_dev_s *dev; + + /* Configure the OLED GPIOs. This initial configuration is RESET low, + * putting the OLED into reset state. + */ + + stm32_configgpio(GPIO_OLED_RESET); + + /* Wait a bit then release the OLED from the reset state */ + + up_mdelay(20); + stm32_gpiowrite(GPIO_OLED_RESET, true); + + /* Get the SPI1 port interface */ + + spi = stm32_spibus_initialize(1); + if (spi == NULL) + { + lcderr("ERROR: Failed to initialize SPI port 1\n"); + } + else + { + /* Bind the SPI port to the OLED */ + + dev = ssd1351_initialize(spi, devno); + if (dev == NULL) + { + lcderr("ERROR: Failed to bind SPI port 1 to OLED %d\n", devno); + } + else + { + lcdinfo("Bound SPI port 1 to OLED %d\n", devno); + + /* And turn the OLED on */ + + dev->setpower(dev, LCD_FULL_ON); + return dev; + } + } + + return NULL; +} + +#endif /* CONFIG_LCD_SSD1351 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c index 6334b89e2ff61..24f3975ba30c6 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c index ec7a72af4bd41..8ce4280fa7099 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c index 79d9586028d12..43820a435bc1d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c index 95dfed45d00d4..162d349a3fce1 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c new file mode 100644 index 0000000000000..4b89cf2f84487 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "stm32_tim.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_TIMER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_timer_driver_setup + * + * Description: + * Configure the timer driver. + * + * Input Parameters: + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 + * timer - The timer's number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int stm32_timer_driver_setup(const char *devpath, int timer) +{ + return stm32_timer_initialize(devpath, timer); +} + +#endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c index 76be6cf99e1bf..17badadd6d0be 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c index e9d2fb8771ede..4b4d62620c907 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c new file mode 100644 index 0000000000000..65bbd76240920 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c new file mode 100644 index 0000000000000..34f386343430c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "stm32f4discovery.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the STM32F4Discovery board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_XBOXCONTROLLER + /* Initialize the HID mouse class */ + + ret = usbhost_xboxcontroller_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the XBox Controller class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and + * status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, + * and the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..327275dd7fee7 --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized. + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_mmcsd_initialize(2, CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..289923108252a --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32f4discovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, GPIO_LED2, GPIO_LED3, GPIO_LED4 +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case PM_NORMAL: + { + /* Restore normal LEDs operation */ + } + break; + + case PM_IDLE: + { + /* Entering IDLE mode - Turn leds off */ + } + break; + + case PM_STANDBY: + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case PM_SLEEP: + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +/**************************************************************************** + * Name: stm32_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c index 210b7cb9e6042..1524ec0f16b4d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h rename to boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h index ef99b4a2fa74a..2989dc8bc336c 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h + * boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt new file mode 100644 index 0000000000000..c06c5331c111b --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32g4/b-g431b-esc1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/Kconfig rename to boards/arm/stm32g4/b-g431b-esc1/Kconfig diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig new file mode 100644 index 0000000000000..87e330cdcf3b0 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=23 +CONFIG_STM32_FDCAN1_NTSEG2=8 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig new file mode 100644 index 0000000000000..320b24936f0a3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=10 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=23 +CONFIG_STM32_FDCAN1_NTSEG2=8 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig new file mode 100644 index 0000000000000..d24c0ae4314ba --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig new file mode 100644 index 0000000000000..b8a719cfc1ca3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_BG431BESC1_FOC_POT=y +CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=200000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=200000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=10400 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_SHUNTS=2 +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig new file mode 100644 index 0000000000000..89e273fb43927 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g431b-esc1" +CONFIG_ARCH_BOARD_B_G431B_ESC1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g431b-esc1/include/board.h b/boards/arm/stm32g4/b-g431b-esc1/include/board.h new file mode 100644 index 0000000000000..006e80f98f3c8 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/include/board.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define STM32_BOARD_XTAL 8000000 /* 8MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL /* Y2 on board */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSI + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSI */ + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE + +/* Main PLL Configuration. + * + * PLL source is HSE = 8MHz + * PLLN = 85, PLLM = 2, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 8MHz x 85 / 2 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(2) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_STM32_BG431BESC1_USE_HSE */ + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +#ifdef CONFIG_STM32_FDCAN +# ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE +# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) +# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) +# else +# error For now FDCAN supported only if HSE enabled +# endif +#endif + +/* LED definitions **********************************************************/ + +/* The B-G431B-ESC1 has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G431RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The B-G431B-ESC supports one buttons controllabe by software: + * + * B1 USER: user button connected to the I/O PC10. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* ADC1 */ + +#define GPIO_ADC1_IN1 GPIO_ADC1_IN1_0 /* PA0 */ +#define GPIO_ADC1_IN2 GPIO_ADC1_IN2_0 /* PA1 */ +#define GPIO_ADC1_IN3 GPIO_ADC1_IN3_0 /* PA2 */ +#define GPIO_ADC1_IN4 GPIO_ADC1_IN4_0 /* PA3 */ +#define GPIO_ADC1_IN5 GPIO_ADC1_IN5_0 /* PB14 */ +#define GPIO_ADC1_IN10 GPIO_ADC1_IN10_0 /* PF0 */ +#define GPIO_ADC1_IN11 GPIO_ADC1_IN11_0 /* PB12 */ +#define GPIO_ADC1_IN12 GPIO_ADC1_IN12_0 /* PB1 */ +#define GPIO_ADC1_IN14 GPIO_ADC1_IN14_0 /* PB11 */ +#define GPIO_ADC1_IN15 GPIO_ADC1_IN15_0 /* PB0 */ + +/* USART2 (ST LINK Virtual Console and J3 pads) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */ +#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */ + +/* TIM1 configuration *******************************************************/ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_0 | GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_4 | GPIO_SPEED_50MHz) /* TIM1 CH1N - PC13 - U low */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1 | GPIO_SPEED_50MHz) /* TIM1 CH2N - PA12 - V low */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3 | GPIO_SPEED_50MHz) /* TIM1 CH3N - PB15 - W low */ + +/* TIM4 QE configuration ****************************************************/ + +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH1 - PB6 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2 | GPIO_SPEED_50MHz) /* TIM4 CH2 - PB7 */ + +/* OPAMP configuration ******************************************************/ + +#define GPIO_OPAMP1_VINM0 (GPIO_OPAMP1_VINM0_0) /* PA3 */ +#define GPIO_OPAMP1_VINP0 (GPIO_OPAMP1_VINP0_0) /* PA1 */ +#define GPIO_OPAMP1_VOUT (GPIO_OPAMP1_VOUT_0) /* PA2 */ + +#define GPIO_OPAMP2_VINM0 (GPIO_OPAMP2_VINM0_0) /* PA5 */ +#define GPIO_OPAMP2_VINP0 (GPIO_OPAMP2_VINP0_0) /* PA7 */ +#define GPIO_OPAMP2_VOUT (GPIO_OPAMP2_VOUT_0) /* PA6 */ + +#define GPIO_OPAMP3_VINM0 (GPIO_OPAMP3_VINM0_0) /* PB2 */ +#define GPIO_OPAMP3_VINP0 (GPIO_OPAMP3_VINP0_0) /* PB0 */ +#define GPIO_OPAMP3_VOUT (GPIO_OPAMP3_VOUT_0) /* PB1 */ + +/* CAN configuration ********************************************************/ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_1 | GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2 | GPIO_SPEED_50MHz) /* PB9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32_B_G431B_ESC1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs new file mode 100644 index 0000000000000..79f59cc5dc22e --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script new file mode 100644 index 0000000000000..6eecf3272e4c6 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431CB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431CB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/b-g431b-esc1/src/.gitignore b/boards/arm/stm32g4/b-g431b-esc1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/src/.gitignore rename to boards/arm/stm32g4/b-g431b-esc1/src/.gitignore diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt new file mode 100644 index 0000000000000..3c5362a634c68 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt @@ -0,0 +1,50 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc.c) +endif() + +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs new file mode 100644 index 0000000000000..04209293fc896 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm/stm32g4/b-g431b-esc1/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CSRCS += stm32_foc.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h similarity index 99% rename from boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h rename to boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h index 40e7863bd06f5..708c07fdbd26f 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h +++ b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h + * boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c new file mode 100644 index 0000000000000..23784ea51aa1b --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c new file mode 100644 index 0000000000000..09acc6b61f631 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c new file mode 100644 index 0000000000000..8a4aed406f078 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE +# include "board_hall3ph.h" +#endif + +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device - must be before ADC setup */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver - TIM4 */ + + ret = board_qencoder_initialize(0, 4); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_HALL3PHASE + /* Initialize and register the 3-phase Hall effect sensor driver */ + + ret = board_hall3ph_initialize(0, GPIO_HALL_PHA, GPIO_HALL_PHB, + GPIO_HALL_PHC); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the hall : %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c new file mode 100644 index 0000000000000..ac13875fa0cbe --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c new file mode 100644 index 0000000000000..7061003ba9098 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_fdcan.h" +#include "b-g431b-esc1.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM +# define BG431BESC1_CANTERM (true) +#else +# define BG431BESC1_CANTERM (false) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ + + can = stm32_fdcaninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + /* Configure CAN_TERM pin for output */ + + stm32_configgpio(GPIO_CANTERM); + + /* Set CAN_TERM pin high or low */ + + stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); + + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c new file mode 100644 index 0000000000000..eb0d3acfdf26f --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_CANTERM +# define BG431BESC1_CANTERM (true) +#else +# define BG431BESC1_CANTERM (false) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ + + ret = stm32_fdcansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get FDCAN interface %d\n", ret); + return ret; + } + + /* Configure CAN_TERM pin for output */ + + stm32_configgpio(GPIO_CANTERM); + + /* Set CAN_TERM pin high or low */ + + stm32_gpiowrite(GPIO_CANTERM, BG431BESC1_CANTERM); + + return OK; +} diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c new file mode 100644 index 0000000000000..c20d43a435e53 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c @@ -0,0 +1,766 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "hardware/stm32g4xxxx_opamp.h" + +#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) +# include "hardware/stm32g4xxxx_pwr.h" +#endif + +#include "stm32_foc.h" + +#ifdef CONFIG_SENSORS_QENCODER +# include "stm32_qencoder.h" +#endif + +#include "arm_internal.h" +#include "b-g431b-esc1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* We don't use phase 2 feedback as it is no connected to ADC1 */ + +#if CONFIG_MOTOR_FOC_SHUNTS != 2 +# error Only 2-shunts configuration is supported +#endif + +/* Configuration specific for L6387ED: + * 1. PWM channels must have positive polarity + * 2. PWM complementary channels must have positive polarity + */ + +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY +# error +#endif + +#if CONFIG_STM32_TIM1_CH1POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3POL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH1NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH2NPOL != 0 +# error +#endif +#if CONFIG_STM32_TIM1_CH3NPOL != 0 +# error +#endif + +/* SYSCFG must be enabled for OPAMP */ + +#ifndef CONFIG_STM32_SYSCFG +# error +#endif + +/* Aux ADC needs DMA enabled and workaround for G4 ADC CHAN0 enabled */ + +#ifdef CONFIG_ADC +# ifndef CONFIG_STM32_ADC1_DMA +# error +# endif +# ifndef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# error +# endif +#endif + +/* REVISIT: */ + +#define PWM_DEADTIME (20) +#define PWM_DEADTIME_NS (500) + +/* Devpath for FOC driver */ + +#define FOC_DEVPATH "/dev/foc0" + +/* Board parameters: + * Current shunt resistance = 0.003 + * PGA gain = 16 + * Current sense gain = -9.14 (inverted current) + * Vbus sense gain = 0.0962 + * Vbus min = 7V + * Vbus max = 25V (6S LiPo battery pack) + * Iout max = 40A peak + * IPHASE_RATIO = 1/(R_shunt*gain) = -36.47 + * ADC_REF_VOLTAGE = 3.3 + * ADC_VAL_MAX = 4095 + * ADC_TO_VOLT = ADC_REF_VOLTAGE / ADC_VAL_MAX + * IPHASE_ADC = IPHASE_RATIO * ADC_TO_VOLT = -0.02939 + * VBUS_RATIO = 1/VBUS_gain = 10.4 + */ + +/* OPAMP gain */ + +#define CURRENT_PGA_GAIN 16 + +/* Center-aligned PWM duty cycle limits */ + +#define MAX_DUTY_B16 ftob16(0.95f) + +/* ADC sample time */ + +#define CURRENT_SAMPLE_TIME ADC_SMPR_2p5 +#define VOLTAGE_SAMPLE_TIME ADC_SMPR_2p5 +#define VBUS_SAMPLE_TIME ADC_SMPR_640p5 +#define POT_SAMPLE_TIME ADC_SMPR_640p5 + +/* ADC1 channels used in this example */ + +#define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS +# define BG431BESC1_FOC_VBUS 1 +#else +# define BG431BESC1_FOC_VBUS 0 +#endif + +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT +# define BG431BESC1_FOC_POT 1 +#else +# define BG431BESC1_FOC_POT 0 +#endif + +#define ADC1_REGULAR (BG431BESC1_FOC_VBUS + BG431BESC1_FOC_POT) +#define ADC1_NCHANNELS (ADC1_INJECTED + ADC1_REGULAR) + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +/* ADC2 channels used for BEMF sensing */ + +# define ADC2_INJECTED (CONFIG_MOTOR_FOC_PHASES) +# define ADC2_REGULAR (0) +# define ADC2_NCHANNELS (ADC2_INJECTED + ADC2_REGULAR) +#endif + +/* Check ADC1 configuration */ + +#ifdef CONFIG_STM32_FOC_G4_ADCCHAN0_WORKAROUND +# if ADC1_INJECTED != (CONFIG_STM32_ADC1_INJECTED_CHAN - 1) +# error +# endif +#else +# if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN +# error +# endif +#endif + +#if CONFIG_STM32_ADC1_RESOLUTION != 0 +# error +#endif + +/* Qenco configuration - only TIM4 */ + +#ifdef CONFIG_SENSORS_QENCODER +# ifndef CONFIG_STM32_TIM4_QE +# error +# endif +# if CONFIG_STM32_TIM4_QEPSC != 0 +# error +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev); +static int board_foc_shutdown(struct foc_dev_s *dev); +static int board_foc_calibration(struct foc_dev_s *dev, bool state); +static int board_foc_fault_clear(struct foc_dev_s *dev); +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state); +static int board_foc_current_get(struct foc_dev_s *dev, + int16_t *curr_raw, + foc_current_t *curr); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +static int board_foc_voltage_get(struct foc_dev_s *dev, + int16_t *volt_raw, + foc_voltage_t *volt); +#endif +static int board_foc_info_get(struct foc_dev_s *dev, + struct foc_info_s *info); +#ifdef CONFIG_MOTOR_FOC_TRACE +static int board_foc_trace_init(struct foc_dev_s *dev); +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* OPAMP configuration: + * - connected with ADC through output pin (OPAINTOEN=0) + * - Current U+ - OPAMP1_VINP0 (PA1) + * - Current U- - OPAMP1_VINP0 (PA3) + * - Current V+ - OPAMP2_VINP0 (PA7) + * - Current V- - OPAMP2_VINP0 (PA5) + * - Current W+ - OPAMP3_VINP0 (PB0) + * - Current W- - OPAMP3_VINP0 (PB2) + * + * ADC configuration: + * - Current Phase V -> ADC1 INJ1 -> ADC1_IN3 (OPAMP1_VOUT/PA2) + * - Current Phase U -> Not used, no ADC1 connection + * - Current Phase W -> ADC1 INJ2 -> ADC1_IN12 (OPAMP3_VOUT/PB12) + * optional: + * - VBUS -> ADC1 REG -> ADC1_IN1 (PA0) + * - POT -> ADC1 REG -> ADC1_IN11 (PB12) + * + * TIM1 PWM configuration: + * - Phase U high -> TIM1_CH1 (PA8) + * - Phase U low -> TIM1_CH1N (PC13) + * - Phase V high -> TIM1_CH2 (PA9) + * - Phase V low -> TIM1_CH2N (PA12) + * - Phase W high -> TIM1_CH3 (PA10) + * - Phase W low -> TIM1_CH3N (PB15) + */ + +static uint8_t g_adc1_chan[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + 1, /* ADC1 REG - VBUS */ +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + 11, /* ADC1 REG - POT */ +#endif + 3, /* ADC1 INJ1 - PHASE 1 */ + 12, /* ADC1 INJ2 - PHASE 3 */ +}; + +static uint32_t g_adc1_pins[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + GPIO_ADC1_IN1, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + GPIO_ADC1_IN11, +#endif + GPIO_ADC1_IN3, + GPIO_ADC1_IN12, +}; + +/* ADC1 sample time configuration */ + +static adc_channel_t g_adc1_stime[] = +{ +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_VBUS + { + .channel = 1, + .sample_time = VBUS_SAMPLE_TIME + }, +#endif +#ifdef CONFIG_BOARD_STM32_BG431BESC1_FOC_POT + { + .channel = 11, + .sample_time = POT_SAMPLE_TIME + }, +#endif + { + .channel = 3, + .sample_time = CURRENT_SAMPLE_TIME + }, + { + .channel = 12, + .sample_time = CURRENT_SAMPLE_TIME + }, +}; + +/* Board specific ADC configuration for FOC */ + +static struct stm32_foc_adc_s g_adc_cfg = +{ + .chan = g_adc1_chan, + .pins = g_adc1_pins, + .stime = g_adc1_stime, + .nchan = ADC1_NCHANNELS, + .regch = ADC1_REGULAR, + .intf = 1 +}; + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +static uint8_t g_adc2_chan[] = +{ + 17, /* ADC2 INJ1 - PHASE 1 */ + 5, /* ADC2 INJ2 - PHASE 2 */ + 14, /* ADC2 INJ3 - PHASE 3 */ +}; + +static uint32_t g_adc2_pins[] = +{ + GPIO_ADC2_IN17, + GPIO_ADC2_IN5, + GPIO_ADC2_IN14, +}; + +/* ADC2 sample time configuration */ + +static adc_channel_t g_adc2_stime[] = +{ + { + .channel = 17, + .sample_time = VOLTAGE_SAMPLE_TIME + }, + { + .channel = 5, + .sample_time = VOLTAGE_SAMPLE_TIME + }, + { + .channel = 14, + .sample_time = VOLTAGE_SAMPLE_TIME + }, +}; + +/* Board specific ADC configuration for BEMF */ + +static struct stm32_foc_adc_s g_vadc_cfg = +{ + .chan = g_adc2_chan, + .pins = g_adc2_pins, + .stime = g_adc2_stime, + .nchan = ADC2_NCHANNELS, + .regch = ADC2_REGULAR, + .intf = 2 +}; +#endif + +/* Board specific ops */ + +static struct stm32_foc_board_ops_s g_stm32_foc_board_ops = +{ + .setup = board_foc_setup, + .shutdown = board_foc_shutdown, + .calibration = board_foc_calibration, + .fault_clear = board_foc_fault_clear, + .pwm_start = board_foc_pwm_start, + .current_get = board_foc_current_get, +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + .voltage_get = board_foc_voltage_get, +#endif + .info_get = board_foc_info_get, +#ifdef CONFIG_MOTOR_FOC_TRACE + .trace_init = board_foc_trace_init, + .trace = board_foc_trace +#endif +}; + +/* Board specific data */ + +static struct stm32_foc_board_data_s g_stm32_foc_board_data = +{ + .adc_cfg = &g_adc_cfg, +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + .vadc_cfg = &g_vadc_cfg, +#endif + .pwm_dt = PWM_DEADTIME +}; + +/* Board specific configuration */ + +static struct stm32_foc_board_s g_stm32_foc_board = +{ + .data = &g_stm32_foc_board_data, + .ops = &g_stm32_foc_board_ops, +}; + +/* Global pointer to the upper FOC driver */ + +static struct foc_dev_s *g_foc_dev = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_foc_setup + ****************************************************************************/ + +static int board_foc_setup(struct foc_dev_s *dev) +{ + uint32_t regval = 0; + + DEBUGASSERT(dev); + + UNUSED(dev); + + /* OPAMP1/2/3 pins: + * OPAMP1_VINM - PA3 (VINM0) + * OPAMP1_VINP - PA1 (VINP0) + * OPAMP2_VINM - PA5 (VINM0) + * OPAMP2_VINP - PA7 (VINP0) + * OPAMP3_VINM - PB2 (VINM0) + * OPAMP3_VINP - PB0 (VINP0) + */ + + /* Configure GPIO */ + + stm32_configgpio(GPIO_OPAMP1_VINM0); + stm32_configgpio(GPIO_OPAMP1_VINP0); + stm32_configgpio(GPIO_OPAMP1_VOUT); + stm32_configgpio(GPIO_OPAMP2_VINM0); + stm32_configgpio(GPIO_OPAMP2_VINP0); + stm32_configgpio(GPIO_OPAMP2_VOUT); + stm32_configgpio(GPIO_OPAMP3_VINM0); + stm32_configgpio(GPIO_OPAMP3_VINP0); + stm32_configgpio(GPIO_OPAMP3_VOUT); +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + stm32_configgpio(GPIO_GPIOBEMF); +#endif + + /* Configure OPAMP inputs */ + + regval += (OPAMP_CSR_VPSEL_VINP0 | OPAMP_CSR_VMSEL_PGA); + + /* PGA mode, non-inverting configuration with external bias on VINM0 */ + +#if CURRENT_PGA_GAIN == 16 + regval += ((0b01011 << OPAMP_CSR_PGAGAIN_SHIFT) & OPAMP_CSR_PGAGAIN_MASK); +#else +# error Not supported +#endif + + /* Enable high-speed mode */ + + regval += OPAMP_CSR_OPAHSM; + + /* Write configuration */ + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + + /* Enable OPAMPs in separate write */ + + regval += OPAMP_CSR_OPAMPEN; + + putreg32(regval, STM32_OPAMP1_CSR); + putreg32(regval, STM32_OPAMP2_CSR); + putreg32(regval, STM32_OPAMP3_CSR); + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + /* Keep GPIO_BEMF low to create BEMF voltage divider */ + + stm32_gpiowrite(GPIO_GPIOBEMF, false); +#endif + + return OK; +} + +/**************************************************************************** + * Name: board_foc_shutdown + ****************************************************************************/ + +static int board_foc_shutdown(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_calibration + ****************************************************************************/ + +static int board_foc_calibration(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_fault_clear + ****************************************************************************/ + +static int board_foc_fault_clear(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_pwm_start + ****************************************************************************/ + +static int board_foc_pwm_start(struct foc_dev_s *dev, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + return OK; +} + +/**************************************************************************** + * Name: board_foc_current_get + ****************************************************************************/ + +static int board_foc_current_get(struct foc_dev_s *dev, + int16_t *curr_raw, + foc_current_t *curr) +{ + DEBUGASSERT(dev); + DEBUGASSERT(curr_raw); + DEBUGASSERT(curr); + + /* Get currents */ + + curr[0] = curr_raw[0]; + curr[2] = curr_raw[1]; + + /* Phase 2 reconstruction */ + + curr[1] = -(curr_raw[0] + curr_raw[1]); + + return OK; +} + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE +/**************************************************************************** + * Name: board_foc_voltage_get + ****************************************************************************/ + +static int board_foc_voltage_get(struct foc_dev_s *dev, + int16_t *volt_raw, + foc_voltage_t *volt) +{ + DEBUGASSERT(dev); + DEBUGASSERT(volt_raw); + DEBUGASSERT(volt); + + /* Get voltages */ + + volt[0] = volt_raw[0]; + volt[1] = volt_raw[1]; + volt[2] = volt_raw[2]; + + return OK; +} +#endif + +/**************************************************************************** + * Name: board_foc_info_get + ****************************************************************************/ + +static int board_foc_info_get(struct foc_dev_s *dev, struct foc_info_s *info) +{ + DEBUGASSERT(dev); + DEBUGASSERT(info); + + UNUSED(dev); + + /* PWM */ + + info->hw_cfg.pwm_dt_ns = PWM_DEADTIME_NS; + info->hw_cfg.pwm_max = MAX_DUTY_B16; + + /* ADC BEMF */ + +#ifdef CONFIG_MOTOR_FOC_BEMF_SENSE + info->hw_cfg.bemf_scale = 0; /* TODO */ +#endif + + /* ADC Current - dynamic current scale not supported */ + + info->hw_cfg.iphase_max = 40000; + info->hw_cfg.iphase_scale = -2939; + + return OK; +} + +#ifdef CONFIG_MOTOR_FOC_TRACE +/**************************************************************************** + * Name: board_foc_trace_init + ****************************************************************************/ + +static int board_foc_trace_init(struct foc_dev_s *dev) +{ + DEBUGASSERT(dev); + + UNUSED(dev); + + /* Not supported */ + + return -1; +} + +/**************************************************************************** + * Name: board_foc_trace + ****************************************************************************/ + +static void board_foc_trace(struct foc_dev_s *dev, int type, bool state) +{ + DEBUGASSERT(dev); + + UNUSED(dev); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_foc_setup + * + * Description: + * Initialize FOC driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_foc_setup(void) +{ + struct foc_dev_s *foc = NULL; + int ret = OK; + + /* Initialize only once */ + + if (g_foc_dev == NULL) + { +#if defined(CONFIG_SENSORS_QENCODER) || defined(CONFIG_SENSORS_HALL3PHASE) + /* Disable USB Type-C and Power Delivery Dead Battery */ + + modifyreg32(STM32_PWR_CR3, 0, PWR_CR3_UCPD1_DBDIS); +#endif + +#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_STM32_QENCODER_INDEX_PIN) + /* Configure encoder index GPIO */ + + ret = stm32_qe_index_init(4, QENCODER_TIM4_INDEX_GPIO); + if (ret < 0) + { + mtrerr("Failed to register encoder index pin %d\n", ret); + ret = -EACCES; + goto errout; + } +#endif + + /* Initialize arch specific FOC lower-half */ + + foc = stm32_foc_initialize(0, &g_stm32_foc_board); + if (foc == NULL) + { + ret = -errno; + mtrerr("Failed to initialize STM32 FOC: %d\n", ret); + goto errout; + } + + DEBUGASSERT(foc->lower); + + /* Register FOC device */ + + ret = foc_register(FOC_DEVPATH, foc); + if (ret < 0) + { + mtrerr("Failed to register FOC device: %d\n", ret); + goto errout; + } + + /* Store pointer to driver */ + + g_foc_dev = foc; + } + +errout: + return ret; +} + +#ifdef CONFIG_ADC +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc = NULL; + int ret = OK; + static bool initialized = false; + + /* Initialize only once */ + + if (initialized == false) + { + if (g_foc_dev == NULL) + { + mtrerr("Failed to get g_foc_dev device\n"); + ret = -EACCES; + goto errout; + } + + /* Register regular channel ADC */ + + adc = stm32_foc_adcget(g_foc_dev); + if (adc == NULL) + { + mtrerr("Failed to get ADC device: %d\n", ret); + goto errout; + } + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + mtrerr("adc_register failed: %d\n", ret); + goto errout; + } + + initialized = true; + } + +errout: + return ret; +} +#endif diff --git a/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c new file mode 100644 index 0000000000000..debdfde7e98d3 --- /dev/null +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "b-g431b-esc1.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt new file mode 100644 index 0000000000000..d5b7816aff587 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/b-g474e-dpow1/Kconfig b/boards/arm/stm32g4/b-g474e-dpow1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/Kconfig rename to boards/arm/stm32g4/b-g474e-dpow1/Kconfig diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig new file mode 100644 index 0000000000000..9bc515466ce87 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_DRIVERS_SMPS=y +CONFIG_EXAMPLES_SMPS=y +CONFIG_EXAMPLES_SMPS_DEVPATH="/dev/smps0" +CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_POWER_LIMIT=100 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_DEFAULT=5000 +CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT=10000 +CONFIG_EXAMPLES_SMPS_TIME_DEFAULT=10 +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBDSP=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMPS_HAVE_INPUT_VOLTAGE=y +CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STDIO_BUFFER_SIZE=128 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_INJECTED_CHAN=2 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_NOIRQ=y +CONFIG_STM32_CCMEXCLUDE=y +CONFIG_STM32_HRTIM1=y +CONFIG_STM32_HRTIM_ADC1_TRG2=y +CONFIG_STM32_HRTIM_ADC=y +CONFIG_STM32_HRTIM_DEADTIME=y +CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y +CONFIG_STM32_HRTIM_PWM=y +CONFIG_STM32_HRTIM_TIMC=y +CONFIG_STM32_HRTIM_TIMC_DT=y +CONFIG_STM32_HRTIM_TIMC_PWM=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMC_PWM_CH2=y +CONFIG_STM32_HRTIM_TIMD=y +CONFIG_STM32_HRTIM_TIMD_DT=y +CONFIG_STM32_HRTIM_TIMD_PWM=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH1=y +CONFIG_STM32_HRTIM_TIMD_PWM_CH2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig new file mode 100644 index 0000000000000..f2c942f86dbcd --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig new file mode 100644 index 0000000000000..de16a9a8cabcb --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="b-g474e-dpow1" +CONFIG_ARCH_BOARD_B_G474E_DPOW1=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/b-g474e-dpow1/include/board.h b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h new file mode 100644 index 0000000000000..d06e0188bf6d9 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h @@ -0,0 +1,256 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#undef STM32_BOARD_XTAL /* Not installed by default */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#undef STM32_HSE_FREQUENCY /* Not installed by default */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The B-G474E-DPOW1 Discovery kit has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 (Blue) */ +#define BOARD_LED2 1 /* User LD3 (Orange) */ +#define BOARD_LED3 2 /* User LD4 (Green) */ +#define BOARD_LED4 3 /* User LD5 (Red)*/ +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs + * on the board. The following definitions describe how NuttX controls the + * LEDs: + * + * |--------------------|-------------------------|------------| + * | SYMBOL | Meaning | LED states | + * |--------------------|-------------------------|------------| + * | LED_STARTED | NuttX has been started | 0 0 0 0 | + * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | + * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | + * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | + * | LED_INIRQ | In an interrupt | No change | + * | LED_SIGNAL | In a signal handler | No change | + * | LED_ASSERTION | An assertion failed | No change | + * | LED_PANIC | The system has crashed | 0 B 0 0 | + * | LED_IDLE | STM32 is in sleep mode | Not used | + * |--------------------|-------------------------|------------| + * + * LED states legend: + * 0 = off + * 1 = on + * B = blink + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* Alternate function pin selections ****************************************/ + +/* USART3 (ST LINK V3E Virtual Console) */ + +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ + +/* Board configuration for SMPS example: + * PB12 - HRTIM1_CHC1 + * PB13 - HRTIM1_CHC2 + * PB14 - HRTIM1_CHD1 + * PB15 - HRTIM1_CHD2 + * VIN - ADC Channel 2 (PA1) + * VOUT - ADC Channel 4 (PA3) + */ + +#if defined(CONFIG_EXAMPLES_SMPS) + +/* HRTIM configuration ******************************************************/ + +/* Timer C configuration - Buck operations */ + +#define HRTIM_TIMC_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMC_MODE HRTIM_MODE_CONT +#define HRTIM_TIMC_UPDATE 0 +#define HRTIM_TIMC_RESET 0 + +#define HRTIM_TIMC_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMC_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMC_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMC_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMC_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMC_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMC_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMC_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMC_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMC_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMC_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +/* Timer D configuration - Boost operations */ + +#define HRTIM_TIMD_PRESCALER HRTIM_PRESCALER_1 +#define HRTIM_TIMD_MODE HRTIM_MODE_CONT +#define HRTIM_TIMD_UPDATE 0 +#define HRTIM_TIMD_RESET 0 + +#define HRTIM_TIMD_CH1_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMD_CH1_RST HRTIM_OUT_RST_NONE +#define HRTIM_TIMD_CH2_SET HRTIM_OUT_SET_NONE +#define HRTIM_TIMD_CH2_RST HRTIM_OUT_RST_NONE + +#define HRTIM_TIMD_DT_FSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMD_DT_RSLOCK HRTIM_DT_LOCK +#define HRTIM_TIMD_DT_FVLOCK HRTIM_DT_RW +#define HRTIM_TIMD_DT_RVLOCK HRTIM_DT_RW +#define HRTIM_TIMD_DT_FSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMD_DT_RSIGN HRTIM_DT_SIGN_POSITIVE +#define HRTIM_TIMD_DT_PRESCALER HRTIM_DEADTIME_PRESCALER_1 + +#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_CC4 + +/* DMA channels *************************************************************/ + +#endif /* CONFIG_EXAMPLES_SMPS */ + +/* HRTIM */ + +#define GPIO_HRTIM1_CHC1 GPIO_HRTIM1_CHC1_0 +#define GPIO_HRTIM1_CHC2 GPIO_HRTIM1_CHC2_0 +#define GPIO_HRTIM1_CHD1 GPIO_HRTIM1_CHD1_0 +#define GPIO_HRTIM1_CHD2 GPIO_HRTIM1_CHD2_0 + +#endif /* __BOARDS_ARM_STM32_B_G474E_DPOW1_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs new file mode 100644 index 0000000000000..a70ca28ceb57f --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script new file mode 100644 index 0000000000000..94b8086bd4903 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu new file mode 100644 index 0000000000000..bef0887a3a80d --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. The FLASH bootloader is located there and + * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k + * if dual bank mode), so our executable will begin at 0x0800:6000, leaving + * 488KiB. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/b-g474e-dpow1/src/.gitignore b/boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/src/.gitignore rename to boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt new file mode 100644 index 0000000000000..5a6c304b0f2de --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_DRIVERS_SMPS) + list(APPEND SRCS stm32_smps.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs new file mode 100644 index 0000000000000..172dcb8b09960 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_DRIVERS_SMPS),y) +CSRCS += stm32_smps.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h rename to boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h index f7c09937e7f69..f981e5ed105b6 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h + * boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c new file mode 100644 index 0000000000000..41f87f2130b06 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "b-g474e-dpow1.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, true); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, true); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, true); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, false); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, false); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, false); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c new file mode 100644 index 0000000000000..a7bbb7138b0be --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "b-g474e-dpow1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_ARCH_LEDS) + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_DRIVERS_SMPS + /* Initialize smps and register the smps driver */ + + ret = stm32_smps_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c new file mode 100644 index 0000000000000..9a51ba2908446 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c @@ -0,0 +1,1262 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "ram_vectors.h" + +#include "stm32_hrtim.h" +#include "stm32_adc.h" + +#include + +#if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) + +#ifndef CONFIG_LIBDSP +# error CONFIG_LIBDSP is required +#endif + +#ifndef CONFIG_ARCH_HIPRI_INTERRUPT +# error CONFIG_ARCH_HIPRI_INTERRUPT is required +#endif + +#ifndef CONFIG_ARCH_RAMVECTORS +# error CONFIG_ARCH_RAMVECTORS is required +#endif + +#ifndef CONFIG_ARCH_IRQPRIO +# error CONFIG_ARCH_IRQPRIO is required +#endif + +#ifndef CONFIG_ARCH_FPU +# warning Set CONFIG_ARCH_FPU for hardware FPU support +#endif + +#if !defined(CONFIG_STM32_HRTIM1) || !defined(CONFIG_STM32_HRTIM) +# error "SMPS example requires HRTIM1 support" +#endif + +#if !defined(CONFIG_STM32_ADC1) || !defined(CONFIG_ADC) +# error "SMPS example requires ADC1 support" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC1 channels used in this example */ + +#define ADC1_NCHANNELS 2 + +/* ADC1 injected channels numeration */ + +#define V_IN_ADC_INJ_CHANNEL 0 +#define V_OUT_ADC_INJ_CHANNEL 1 + +/* Voltage reference for ADC */ + +#define ADC_REF_VOLTAGE ((float)3.3) + +/* ADC resolution */ + +#define ADC_VAL_MAX 4095 + +/* Input voltage conversion ratio - 6.8k/(6.8k + 27k) */ + +#define V_IN_RATIO (float)((float)(6800+27000)/(float)6800) + +/* Output voltage conversion ratio - 3.3k/(3.3k + 13.3k) */ + +#define V_OUT_RATIO (float)((float)(3300+13300)/(float)3300) + +/* Some absolute limits */ + +#define SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA 250 +#define SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV 15000 +#define SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV 15000 + +#if CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT > SMPS_ABSOLUTE_OUT_CURRENT_LIMIT_mA +# error "Output current limit great than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT > SMPS_ABSOLUTE_OUT_VOLTAGE_LIMIT_mV +# error "Output voltage limit greater than absolute limit!" +#endif +#if CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT > SMPS_ABSOLUTE_IN_VOLTAGE_LIMIT_mV +# error "Input voltage limit greater than absolute limit!" +#endif + +/* Maximum output voltage for boost converter in float */ + +#define BOOST_VOLT_MAX ((float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT/1000.0) + +/* At this time only PID controller implemented */ + +#define SMPS_CONTROLLER_PID 1 + +/* Converter's finite accuracy */ + +#define SMPS_VOLTAGE_ACCURACY ((float)0.01) + +/* Buck-boost mode threshold */ + +#define SMPS_BUCKBOOST_RANGE ((float)0.5) + +/* PID controller configuration */ + +#define PID_KP ((float)1.0) +#define PID_KI ((float)0.1) +#define PID_KD ((float)0.0) + +/* Converter frequencies: + * - TIMC_PWM_FREQ - buck converter 250kHz + * - TIMD_PWM_FREQ - boost converter 250kHz + */ + +#define TIMC_PWM_FREQ 250000 +#define TIMD_PWM_FREQ 250000 + +/* Deadtime configuration */ + +#define DT_RISING 0x0B0 +#define DT_FALLING 0x0B0 + +/* Helper macros */ + +#define HRTIM_ALL_OUTPUTS_ENABLE(hrtim, state) \ + HRTIM_OUTPUTS_ENABLE(hrtim, HRTIM_OUT_TIMC_CH1|HRTIM_OUT_TIMC_CH2| \ + HRTIM_OUT_TIMD_CH1|HRTIM_OUT_TIMD_CH2, state); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Current converter mode */ + +enum converter_mode_e +{ + CONVERTER_MODE_INIT, /* Initial mode */ + CONVERTER_MODE_BUCK, /* Buck mode operations (V_in > V_out) */ + CONVERTER_MODE_BOOST, /* Boost mode operations (V_in < V_out) */ + CONVERTER_MODE_BUCKBOOST, /* Buck-boost operations (V_in near V_out) */ +}; + +/* SMPS lower drivers structure */ + +struct smps_lower_dev_s +{ + struct hrtim_dev_s *hrtim; /* PWM generation */ + struct stm32_adc_dev_s *adc; /* input and output voltage sense */ + struct comp_dev_s *comp; /* not used in this demo - only as reference */ + struct dac_dev_s *dac; /* not used in this demo - only as reference */ + struct opamp_dev_s *opamp; /* not used in this demo - only as reference */ +}; + +/* Private data for smps */ + +struct smps_priv_s +{ + uint8_t conv_mode; /* Converter mode */ + uint16_t v_in_raw; /* Voltage input RAW value */ + uint16_t v_out_raw; /* Voltage output RAW value */ + float v_in; /* Voltage input real value in V */ + float v_out; /* Voltage output real value in V */ + bool running; /* Running flag */ + pid_controller_f32_t pid; /* PID controller */ + float *c_limit_tab; /* Current limit tab */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev); +static int smps_shutdown(struct smps_dev_s *dev); +static int smps_start(struct smps_dev_s *dev); +static int smps_stop(struct smps_dev_s *dev); +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param); +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode); +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits); +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state); +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault); +static int smps_fault_get(struct smps_dev_s *dev, + uint8_t *fault); +static int smps_fault_clean(struct smps_dev_s *dev, + uint8_t fault); +static int smps_ioctl(struct smps_dev_s *dev, int cmd, + unsigned long arg); + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct smps_lower_dev_s g_smps_lower; +struct smps_priv_s g_smps_priv; +struct smps_s g_smps; + +struct smps_ops_s g_smps_ops = +{ + .setup = smps_setup, + .shutdown = smps_shutdown, + .start = smps_start, + .stop = smps_stop, + .params_set = smps_params_set, + .mode_set = smps_mode_set, + .limits_set = smps_limits_set, + .fault_set = smps_fault_set, + .state_get = smps_state_get, + .fault_get = smps_fault_get, + .fault_clean = smps_fault_clean, + .ioctl = smps_ioctl +}; + +struct smps_dev_s g_smps_dev = +{ + .ops = &g_smps_ops, + .priv = &g_smps, + .lower = NULL +}; + +/* ADC configuration: + * - Input voltage (V_IN) - ADC1 Channel 2 (PA1) + * - Output voltage (V_OUT) - ADC1 Channel 4 (PA3) + * + * ADC channels configured in injected mode. + * + * Transistors configuration in buck mode: + * - T6 - ON + * - T2 - OFF + * - T5 and T1 - buck operation + * Transistors configuration in boost mode: + * - T5 - ON + * - T1 - OFF + * - T6 and T2 - boost operation + * Transistors configuration in buck-boost mode: + * - T5 and T1 - buck operation + * - T6 and T2 - boost operation + * + * HRTIM outputs configuration: + * - T5 -> PB12 -> HRTIM_CHC1 + * - T6 -> PB14 -> HRTIM_CHD1 + * - T1 -> PB13 -> HRTIM_CHC2 + * - T2 -> PB15 -> HRTIM_CHD2 + */ + +/* ADC channel list */ + +static const uint8_t g_adc1chan[ADC1_NCHANNELS] = +{ + 2, + 4 +}; + +/* Configurations of pins used by ADC channel */ + +static const uint32_t g_adc1pins[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN2_0, /* PA1 - V_IN */ + GPIO_ADC1_IN4_0, /* PA3 - V_OUT */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: smps_setup + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_setup(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct hrtim_dev_s *hrtim = NULL; + struct stm32_adc_dev_s *adc = NULL; + struct smps_priv_s *priv; + struct adc_channel_s channels[ADC1_NCHANNELS]; + struct adc_sample_time_s stime; + int ret = OK; + int i = 0; + + /* Initialize smps structure */ + + smps->opmode = SMPS_OPMODE_INIT; + smps->state.state = SMPS_STATE_INIT; + smps->priv = &g_smps_priv; + + /* Check lower half drivers */ + + hrtim = lower->hrtim; + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get hrtim "); + ret = ERROR; + goto errout; + } + + adc = lower->adc; + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC lower level interface"); + ret = ERROR; + goto errout; + } + + /* Update ADC sample time */ + + for (i = 0; i < ADC1_NCHANNELS; i += 1) + { + channels[i].sample_time = ADC_SMPR_92p5; + channels[i].channel = g_adc1chan[i]; + } + + memset(&stime, 0, sizeof(struct adc_sample_time_s)); + + stime.channels_nbr = ADC1_NCHANNELS; + stime.channel = channels; + + STM32_ADC_SAMPLETIME_SET(adc, &stime); + STM32_ADC_SAMPLETIME_WRITE(adc); + + /* TODO: create current limit table */ + + UNUSED(priv); + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_shutdown + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_shutdown(struct smps_dev_s *dev) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + + /* Stop smps if running */ + + if (priv->running == true) + { + smps_stop(dev); + } + + /* Reset smps structure */ + + memset(smps, 0, sizeof(struct smps_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_start + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_start(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + volatile uint64_t per = 0; + uint64_t fclk = 0; + int ret = OK; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Reset SMPS private structure */ + + memset(priv, 0, sizeof(struct smps_priv_s)); + +#ifdef SMPS_CONTROLLER_PID + /* Initialize PID controller */ + + pid_controller_init(&priv->pid, PID_KP, PID_KI, PID_KD); + + /* Set PID controller saturation */ + + pid_saturation_set(&priv->pid, 0.0, BOOST_VOLT_MAX); + + /* Reset PI integral if saturated */ + + pi_ireset_enable(&priv->pid, true); +#endif + + /* Get TIMC period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMC); + per = fclk / TIMC_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timc pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMC_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMC period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMC, (uint16_t)per); + + /* Get TIMD period value for given frequency */ + + fclk = HRTIM_FCLK_GET(hrtim, HRTIM_TIMER_TIMD); + per = fclk / TIMD_PWM_FREQ; + if (per > HRTIM_PER_MAX) + { + pwrerr("ERROR: Can not achieve timd pwm " + "freq=%" PRIu32 " if fclk=%" PRIu64 "\n", + (uint32_t)TIMD_PWM_FREQ, fclk); + ret = -EINVAL; + goto errout; + } + + /* Set TIMD period value */ + + HRTIM_PER_SET(hrtim, HRTIM_TIMER_TIMD, (uint16_t)per); + + /* ADC trigger on TIMC CMP4 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP4, 10000); + + /* Configure TIMER C and TIMER D deadtime mode + * + * NOTE: In deadtime mode we have to configure output 1 only + * (SETx1, RSTx1), output 2 configuration is not significant. + */ + + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMC, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_RISING, + DT_RISING); + HRTIM_DEADTIME_UPDATE(hrtim, HRTIM_TIMER_TIMD, HRTIM_DT_EDGE_FALLING, + DT_FALLING); + + /* Set T5 and T2 to a low state. + * Deadtime mode force T1 and T6 to a high state. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, HRTIM_OUT_RST_PER); + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, HRTIM_OUT_RST_PER); + + /* Set running flag */ + + priv->running = true; + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); + + /* Enable ADC JEOS interrupts */ + + STM32_ADC_INT_ENABLE(adc, ADC_INT_JEOS); + + /* Enable ADC12 interrupts */ + + up_enable_irq(STM32_IRQ_ADC12); + + /* Start injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, true); + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_stop + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_stop(struct smps_dev_s *dev) +{ + struct smps_lower_dev_s *lower = dev->lower; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct hrtim_dev_s *hrtim = lower->hrtim; + struct stm32_adc_dev_s *adc = lower->adc; + + /* Disable HRTIM outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + /* Stop injected conversion */ + + STM32_ADC_INJ_STARTCONV(adc, false); + + /* Disable ADC JEOS interrupts */ + + STM32_ADC_INT_DISABLE(adc, ADC_INT_JEOS); + + /* Disable ADC12 interrupts */ + + up_disable_irq(STM32_IRQ_ADC12); + + /* Reset running flag */ + + priv->running = false; + + return OK; +} + +/**************************************************************************** + * Name: smps_params_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_params_set(struct smps_dev_s *dev, + struct smps_params_s *param) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only output voltage */ + + smps->param.v_out = param->v_out; + + /* REVISIT: use current and power parameters ? */ + + if (param->i_out > 0) + { + pwrwarn("WARNING: Output current parameters not used in this demo\n"); + } + + if (param->p_out > 0) + { + pwrwarn("WARNING: Output power parameters not used in this demo\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: smps_mode_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_mode_set(struct smps_dev_s *dev, uint8_t mode) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Only constant voltage mode supported */ + + if (mode == SMPS_OPMODE_CV) + { + smps->opmode = mode; + } + else + { + pwrerr("ERROR: Unsupported SMPS mode %d!\n", mode); + ret = ERROR; + goto errout; + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_limits_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_limits_set(struct smps_dev_s *dev, + struct smps_limits_s *limits) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + int ret = OK; + + /* Some assertions */ + + if (limits->v_out <= 0) + { + pwrerr("ERROR: Output voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_in <= 0) + { + pwrerr("ERROR: Input voltage limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->i_out <= 0) + { + pwrerr("ERROR: Output current limit must be set!\n"); + ret = ERROR; + goto errout; + } + + if (limits->v_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT) + { + limits->v_out = (float)CONFIG_EXAMPLES_SMPS_OUT_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output voltage limiit > SMPS absolute output voltage " + "limit. Set output voltage limit to %.2f.\n", + limits->v_out); + } + + if (limits->v_in * 1000 > CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT) + { + limits->v_in = (float)CONFIG_EXAMPLES_SMPS_IN_VOLTAGE_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS input voltage limiit > SMPS absolute input voltage " + "limit. Set input voltage limit to %.2f.\n", + limits->v_in); + } + + if (limits->i_out * 1000 > CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT) + { + limits->i_out = (float)CONFIG_EXAMPLES_SMPS_OUT_CURRENT_LIMIT / 1000.0; + pwrwarn("WARNING: " + "SMPS output current limiit > SMPS absolute output current " + "limit. Set output current limit to %.2f.\n", + limits->i_out); + } + + /* Set output voltage limit */ + + smps->limits.v_out = limits->v_out; + + /* Set input voltage limit */ + + smps->limits.v_in = limits->v_in; + + /* Set current limit */ + + smps->limits.i_out = limits->i_out; + + /* Lock limits */ + + smps->limits.lock = true; + +errout: + return ret; +} + +/**************************************************************************** + * Name: smps_state_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_state_get(struct smps_dev_s *dev, + struct smps_state_s *state) +{ + struct smps_s *smps = (struct smps_s *)dev->priv; + + /* Copy locally stored feedbacks data to status structure */ + + smps->state.fb.v_in = g_smps_priv.v_in; + smps->state.fb.v_out = g_smps_priv.v_out; + + /* Return state structure to caller */ + + memcpy(state, &smps->state, sizeof(struct smps_state_s)); + + return OK; +} + +/**************************************************************************** + * Name: smps_fault_set + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_set(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_fault_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_get(struct smps_dev_s *dev, uint8_t *fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_fault_clean + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_fault_clean(struct smps_dev_s *dev, uint8_t fault) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_state_get + * + * Description: + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +static int smps_ioctl(struct smps_dev_s *dev, int cmd, unsigned long arg) +{ + return OK; +} + +/**************************************************************************** + * Name: smps_controller + * + * Description: + * + * Returned Value: + * + ****************************************************************************/ + +static float smps_controller(struct smps_priv_s *priv, float err) +{ + float out = 0.0; + +#ifdef SMPS_CONTROLLER_PID + out = pid_controller(&priv->pid, err); +#else +# error "At this time only PID controller implemented" +#endif + + return out; +} + +/**************************************************************************** + * Name: smps_duty_set + * + * Description: + * + * Returned Value: + * + ****************************************************************************/ + +static void smps_duty_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + float out) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + uint8_t mode = priv->conv_mode; + uint16_t cmp = 0; + float duty = 0.0; + uint16_t per = 0; + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + /* Do nothing */ + + break; + } + + case CONVERTER_MODE_BUCK: + { + if (out >= priv->v_in) out = priv->v_in; + if (out < 0.0) out = 0.0; + + duty = out / priv->v_in; + +#warning TODO: current limit in buck mode + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + cmp = (uint16_t)(per * duty); + + if (cmp > per - 30) cmp = per - 30; + + /* Set T5 duty cycle. T1 is complementary to T5 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BOOST: + { + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T2 duty cycle. T6 is complementary to T2 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Buck converter is set to fixed duty cycle (80%). + * Now we need set boost converter + */ + + per = HRTIM_PER_GET(hrtim, HRTIM_TIMER_TIMC); + + if (out < priv->v_in) out = priv->v_in; + if (out >= BOOST_VOLT_MAX) out = BOOST_VOLT_MAX; + + duty = 1.0 - priv->v_in / out; + +#warning TODO: current limit in buck boost mode + + cmp = (uint16_t)(per * duty); + + /* Set T2 duty cycle. T6 is complementary to T2 */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMD, HRTIM_CMP1, cmp); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } +} + +/**************************************************************************** + * Name: smps_conv_mode_set + * + * Description: + * Change converter mode (buck/boost/buck-boost). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void smps_conv_mode_set(struct smps_priv_s *priv, + struct smps_lower_dev_s *lower, + uint8_t mode) +{ + struct hrtim_dev_s *hrtim = lower->hrtim; + + /* Disable all outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, false); + + switch (mode) + { + case CONVERTER_MODE_INIT: + { + break; + } + + case CONVERTER_MODE_BUCK: + { + /* Set T2 low (T6 high) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_NONE); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_PER); + + /* Set T5 to a high state on PER and reset on CMP1. + * T1 is complementary to T5. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BOOST: + { + /* Set T4 high (T11 low) on the next PER */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_NONE); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_CMP1); + + break; + } + + case CONVERTER_MODE_BUCKBOOST: + { + /* Set T4 to a high state on PER and reset on CMP1. + * T11 is complementary to T4. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMC_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set T12 to a high state on PER and reset on CMP1. + * T5 is complementary to T12. + */ + + HRTIM_OUTPUT_SET_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_SET_PER); + HRTIM_OUTPUT_RST_SET(hrtim, HRTIM_OUT_TIMD_CH1, + HRTIM_OUT_RST_CMP1); + + /* Set fixed duty cycle (80%) on buck converter (T4 and T11) */ + + HRTIM_CMP_SET(hrtim, HRTIM_TIMER_TIMC, HRTIM_CMP1, + 0.8 * ((uint16_t)HRTIM_PER_GET(hrtim, + HRTIM_TIMER_TIMC))); + + break; + } + + default: + { + pwrerr("ERROR: Unknown converter mode %d!\n", mode); + break; + } + } + + /* Set mode in private data */ + + priv->conv_mode = mode; + + /* Enable outputs */ + + HRTIM_ALL_OUTPUTS_ENABLE(hrtim, true); +} + +/**************************************************************************** + * Name: adc12_handler + ****************************************************************************/ + +static void adc12_handler(void) +{ + struct smps_dev_s *dev = &g_smps_dev; + struct smps_s *smps = (struct smps_s *)dev->priv; + struct smps_priv_s *priv = (struct smps_priv_s *)smps->priv; + struct smps_lower_dev_s *lower = dev->lower; + struct stm32_adc_dev_s *adc = lower->adc; + uint32_t pending; + float ref = ADC_REF_VOLTAGE; + float bit = ADC_VAL_MAX; + float err; + float out; + uint8_t mode; + + pending = STM32_ADC_INT_GET(adc); + + if (pending & ADC_INT_JEOC && priv->running == true) + { + /* Get raw ADC values */ + + priv->v_out_raw = STM32_ADC_INJDATA_GET(adc, V_OUT_ADC_INJ_CHANNEL); + priv->v_in_raw = STM32_ADC_INJDATA_GET(adc, V_IN_ADC_INJ_CHANNEL); + + /* Convert raw values to real values */ + + priv->v_out = (priv->v_out_raw * ref / bit) * V_OUT_RATIO; + priv->v_in = (priv->v_in_raw * ref / bit) * V_IN_RATIO; + + /* According to measured voltages we set converter + * in appropriate mode + */ + + if (smps->param.v_out > (priv->v_in + SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage greater than input voltage - set + * boost converter + */ + + mode = CONVERTER_MODE_BOOST; + } + + else if (smps->param.v_out < (priv->v_in - SMPS_BUCKBOOST_RANGE)) + { + /* Desired output voltage lower than input voltage - set + * buck converter + */ + + mode = CONVERTER_MODE_BUCK; + } + + else + { + /* Desired output voltage close to input voltage - set + * buck-boost converter + */ + + mode = CONVERTER_MODE_BUCKBOOST; + } + + /* Configure converter to the new mode if needed */ + + if (priv->conv_mode != mode) + { + smps_conv_mode_set(priv, lower, mode); + } + + /* Get regulator error */ + + err = smps->param.v_out - priv->v_out; + + if (err >= SMPS_VOLTAGE_ACCURACY || err <= (-SMPS_VOLTAGE_ACCURACY)) + { + /* PID controller */ + + out = smps_controller(priv, err); + + /* Update duty cycle */ + + smps_duty_set(priv, lower, out); + } + } + + /* Clear pending */ + + STM32_ADC_INT_ACK(adc, pending); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_smps_setup + * + * Description: + * Initialize SMPS driver. + * + * Returned Value: + * 0 on success, a negated errno value on failure + * + ****************************************************************************/ + +int stm32_smps_setup(void) +{ + struct smps_lower_dev_s *lower = &g_smps_lower; + struct smps_dev_s *smps = &g_smps_dev; + struct hrtim_dev_s *hrtim = NULL; + struct adc_dev_s *adc = NULL; + static bool initialized = false; + int ret = OK; + int i; + + /* Initialize only once */ + + if (!initialized) + { + /* Get the HRTIM interface */ + + hrtim = stm32_hrtiminitialize(); + if (hrtim == NULL) + { + pwrerr("ERROR: Failed to get HRTIM1 interface\n"); + return -ENODEV; + } + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1pins[i]); + } + + /* Get the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1chan, ADC1_NCHANNELS); + if (adc == NULL) + { + pwrerr("ERROR: Failed to get ADC %d interface\n", 1); + return -ENODEV; + } + + /* Initialize SMPS lower driver interfaces */ + + lower->hrtim = hrtim; + lower->adc = adc->ad_priv; + lower->comp = NULL; + lower->dac = NULL; + lower->opamp = NULL; + + /* Attach ADC12 ram vector */ + + ret = arm_ramvec_attach(STM32_IRQ_ADC12, adc12_handler); + if (ret < 0) + { + pwrerr("ERROR: arm_ramvec_attach failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Set the priority of the ADC12 interrupt vector */ + + ret = up_prioritize_irq(STM32_IRQ_ADC12, NVIC_SYSH_HIGH_PRIORITY); + if (ret < 0) + { + pwrerr("ERROR: up_prioritize_irq failed: %d\n", ret); + ret = EXIT_FAILURE; + goto errout; + } + + /* Setup ADC hardware */ + + adc->ad_ops->ao_setup(adc); + + /* We do not need register character drivers for SMPS lower + * peripherals. All control should be done via SMPS character + * driver. + */ + + ret = smps_register(CONFIG_EXAMPLES_SMPS_DEVPATH, smps, (void *)lower); + if (ret < 0) + { + pwrerr("ERROR: smps_register failed: %d\n", ret); + return ret; + } + + initialized = true; + } + +errout: + return ret; +} + +#endif /* CONFIG_EXAMPLE_SMPS && CONFIG_DRIVERS_SMPS*/ diff --git a/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c new file mode 100644 index 0000000000000..c96b727857092 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "b-g474e-dpow1.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * Initialize the user LEDs before use. Note: For this function to be + * available to user application logic, CONFIG_ARCH_LEDS must not be + * defined. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Allow user application logic to control LEDs one at a time. Note: For + * this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * led: Index to the LED, which may be one of the defines BOARD_LED1, + * BOARD_LED2, BOARD_LED3, or BOARD_LED4. + * ledon: true to turn the LED on, false to turn it off. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, ledon); + break; + + case BOARD_LED2: + stm32_gpiowrite(GPIO_LED2, ledon); + break; + + case BOARD_LED3: + stm32_gpiowrite(GPIO_LED3, ledon); + break; + + case BOARD_LED4: + stm32_gpiowrite(GPIO_LED4, ledon); + break; + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Allow user application logic to control all LEDs in one function call. + * Note: For this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * ledset: Bitmask indicating the new state for all LEDs, where a set bit + * indicates LED on and a clear bit indicates LED off. To + * construct the bitmask, using a bitwise OR of the defines + * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or + * BOARD_LED4_BIT. + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED4, (ledset & BOARD_LED4_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/common/CMakeLists.txt b/boards/arm/stm32g4/common/CMakeLists.txt new file mode 100644 index 0000000000000..ad0187882181e --- /dev/null +++ b/boards/arm/stm32g4/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32g4/common/Kconfig b/boards/arm/stm32g4/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32g4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g4/common/Makefile b/boards/arm/stm32g4/common/Makefile new file mode 100644 index 0000000000000..e43e0794f5af3 --- /dev/null +++ b/boards/arm/stm32g4/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32g4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt new file mode 100644 index 0000000000000..2b117337231c6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/Kconfig b/boards/arm/stm32g4/nucleo-g431kb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/Kconfig rename to boards/arm/stm32g4/nucleo-g431kb/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig new file mode 100644 index 0000000000000..d47e5c3e774e0 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_COMP=y +CONFIG_DAC=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_DAC=y +CONFIG_EXAMPLES_DAC_DEVPATH="/dev/dac5" +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=15 +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2021 +CONFIG_STM32_COMP2=y +CONFIG_STM32_COMP2_HYST=3 +CONFIG_STM32_COMP2_INM=4 +CONFIG_STM32_COMP2_OUT=y +CONFIG_STM32_DAC3=y +CONFIG_STM32_DAC3CH2=y +CONFIG_STM32_DAC3CH2_MODE=3 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig new file mode 100644 index 0000000000000..e848946ed7e20 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig new file mode 100644 index 0000000000000..8fbb0dc6b8760 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig @@ -0,0 +1,41 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431kb" +CONFIG_ARCH_BOARD_NUCLEO_G431KB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PWM=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_YEAR=2021 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431kb/include/board.h b/boards/arm/stm32g4/nucleo-g431kb/include/board.h new file mode 100644 index 0000000000000..c3a80f1c3122c --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/include/board.h @@ -0,0 +1,258 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Nucleo-G431KB supports four ways to configure high-speed clock + * + * - HSI configuration (default): 16 MHz high-speed internal RC oscillator. + * - HSE bypass configuration (from ST-LINK): The input clock is the + * ST-LINK MCO output. The frequency is fixed to 25 MHz, and connected + * to the PF0-OSC_IN of the STM32G4 microcontroller. + * - HSE bypass configuration (from ARDUINO D7): The clock is coming from + * an external oscillator through the pin PF0 (ARDUINO D7 pin 10 of the + * CN4 connector). + * - HSE oscillator configuration: The clock is provided by an external + * 24MHz crystal (X2) available in the PCB. + */ + +#define STM32_BOARD_XTAL 24000000ul /* 24MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The Nucleo-G431KB board has only one user LED, LD2. LD2 is a green LED + * connected to the following STM32G4 pins + * - PB8 (default) + * - PB3 + * It is also connected to Arduino signal D13. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control this LED in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED2 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo-G431KB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431KB don't have buttons that are controllable by software: + * + * B1 RESET: push button connected to NRST is used to RESET the + * STM32G431KB. + */ + +/* Alternate function pin selections ****************************************/ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ + +/* Comparators configuration ************************************************/ + +#define GPIO_COMP2_OUT GPIO_COMP2_OUT_3 /* PA12 */ +#define GPIO_COMP2_INP GPIO_COMP2_INP_2 /* PA7 */ +#define GPIO_COMP2_INM GPIO_COMP2_INM_2 /* PA5 check solder bridge SB2 */ + +/* DMA channels *************************************************************/ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431KB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs new file mode 100644 index 0000000000000..0018145617a8a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script new file mode 100644 index 0000000000000..4c8eebff5b13b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431KB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431KB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431kb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431kb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431kb/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt new file mode 100644 index 0000000000000..eb079f995679d --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_STM32_COMP) + list(APPEND SRCS stm32_comp.c) +endif() + +if(CONFIG_STM32_DAC) + list(APPEND SRCS stm32_dac.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs new file mode 100644 index 0000000000000..d0b9afc162954 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431kb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_STM32_COMP),y) +CSRCS += stm32_comp.c +endif + +ifeq ($(CONFIG_STM32_DAC),y) +CSRCS += stm32_dac.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h rename to boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h index 147f4c3479d1f..79f0f56b4726d 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h +++ b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h + * boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..918b2ad9fbf72 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED2) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c new file mode 100644 index 0000000000000..3b9024b9b1f76 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c new file mode 100644 index 0000000000000..c20ef2f5cdd78 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_COMP + /* Initialize and register the COMP driver. */ + + ret = stm32_comp_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DAC + /* Initialize and register the DAC driver. */ + + ret = stm32_dac_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c new file mode 100644 index 0000000000000..17cb1960b994a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_STM32_COMP) && (defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4)) + +#ifdef CONFIG_STM32_COMP1 +# if defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP2 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP3) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP3 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP4) +# error "Currently only one COMP device supported" +# endif +#elif CONFIG_STM32_COMP4 +# if defined(CONFIG_STM32_COMP1) || \ + defined(CONFIG_STM32_COMP2) || \ + defined(CONFIG_STM32_COMP3) +# error "Currently only one COMP device supported" +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_comp_setup + * + * Description: + * Initialize COMP + * + ****************************************************************************/ + +int stm32_comp_setup(void) +{ + static bool initialized = false; + struct comp_dev_s *comp = NULL; + int ret = OK; + + if (!initialized) + { + /* Get the comparator interface */ + +#ifdef CONFIG_STM32_COMP1 + comp = stm32_compinitialize(1); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 1); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP2 + comp = stm32_compinitialize(2); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 2); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP3 + comp = stm32_compinitialize(3); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 3); + return -ENODEV; + } +#endif + +#ifdef CONFIG_STM32_COMP4 + comp = stm32_compinitialize(4); + if (comp == NULL) + { + aerr("ERROR: Failed to get COMP%d interface\n", 4); + return -ENODEV; + } +#endif + +#ifdef CONFIG_COMP + + /* Register the comparator character driver at /dev/comp0 */ + + ret = comp_register("/dev/comp0", comp); + if (ret < 0) + { + aerr("ERROR: comp_register failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return ret; +} + +#endif /* CONFIG_COMP && (CONFIG_STM32_COMP1 || + * CONFIG_STM32_COMP2 || + * CONFIG_STM32_COMP3 || + * CONFIG_STM32_COMP4) */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c new file mode 100644 index 0000000000000..c67d3d78edf43 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c @@ -0,0 +1,114 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "stm32_dac.h" +#include "nucleo-g431kb.h" + +#ifdef CONFIG_DAC + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32_DAC1CH1 +static struct dac_dev_s *g_dac1; +#endif + +#ifdef CONFIG_STM32_DAC3CH2 +static struct dac_dev_s *g_dac5; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dac_setup + * + * Description: + * Initialize and register the DAC driver. + * + * Input parameters: + * devpath - The full path to the driver to register. E.g., "/dev/dac0" + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int stm32_dac_setup(void) +{ + int ret; +#ifdef CONFIG_STM32_DAC1CH1 + g_dac1 = stm32_dacinitialize(1); + if (g_dac1 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac0" */ + + ret = dac_register("/dev/dac0", g_dac1); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif + +#ifdef CONFIG_STM32_DAC3CH2 + g_dac5 = stm32_dacinitialize(5); + if (g_dac5 == NULL) + { + aerr("ERROR: Failed to get DAC interface\n"); + return -ENODEV; + } + + /* Register the DAC driver at "/dev/dac5" */ + + ret = dac_register("/dev/dac5", g_dac5); + if (ret < 0) + { + aerr("ERROR: dac_register() failed: %d\n", ret); + return ret; + } + +#endif + + UNUSED(ret); + return OK; +} + +#endif /* CONFIG_DAC */ diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c new file mode 100644 index 0000000000000..b20b3c2dcad68 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-g431kb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOG431KB_PWM_TIMER); + if (!pwm) + { + tmrerr("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register(NUCLEOG431KB_PWM_PATH, pwm); + if (ret < 0) + { + tmrerr("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c new file mode 100644 index 0000000000000..2d20146d07ef7 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431kb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt new file mode 100644 index 0000000000000..bc497249c8354 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32g4/nucleo-g431rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/Kconfig rename to boards/arm/stm32g4/nucleo-g431rb/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig new file mode 100644 index 0000000000000..2154e927ac434 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_SYSTEM_DD is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PTHREAD=y +CONFIG_FDCLONE_STDIO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1024 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NAME_MAX=16 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_BASENAME=y +CONFIG_NSH_DISABLE_CAT=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CMP=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_DF=y +CONFIG_NSH_DISABLE_DIRNAME=y +CONFIG_NSH_DISABLE_EXEC=y +CONFIG_NSH_DISABLE_EXIT=y +CONFIG_NSH_DISABLE_GET=y +CONFIG_NSH_DISABLE_HEXDUMP=y +CONFIG_NSH_DISABLE_KILL=y +CONFIG_NSH_DISABLE_LOSETUP=y +CONFIG_NSH_DISABLE_LS=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_MKRD=y +CONFIG_NSH_DISABLE_MOUNT=y +CONFIG_NSH_DISABLE_MV=y +CONFIG_NSH_DISABLE_PUT=y +CONFIG_NSH_DISABLE_PWD=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_SET=y +CONFIG_NSH_DISABLE_SLEEP=y +CONFIG_NSH_DISABLE_SOURCE=y +CONFIG_NSH_DISABLE_TEST=y +CONFIG_NSH_DISABLE_TIME=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_DISABLE_UNAME=y +CONFIG_NSH_DISABLE_UNSET=y +CONFIG_NSH_DISABLE_USLEEP=y +CONFIG_NSH_DISABLE_WGET=y +CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_FILEIOSIZE=256 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=512 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig new file mode 100644 index 0000000000000..2aa1ede955e72 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CAN_ERRORS=y +CONFIG_CAN_EXTID=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STDIO_BUFFER_SIZE=512 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=71 +CONFIG_STM32_FDCAN1_NTSEG2=24 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig new file mode 100644 index 0000000000000..c139bf6d9b5dc --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_NUCLEO_G431RB_USE_HSE=y +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CANUTILS_LIBCANUTILS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_BUFSIZE=128 +CONFIG_IOB_NBUFFERS=10 +CONFIG_LINE_MAX=64 +CONFIG_NET=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=71 +CONFIG_STM32_FDCAN1_NTSEG2=24 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig new file mode 100644 index 0000000000000..1490159995b5a --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_CORDIC=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LINE_MAX=64 +CONFIG_MATH_CORDIC=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_CORDIC=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig new file mode 100644 index 0000000000000..ded5f303e7c78 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM16M1=y +CONFIG_BOARD_STM32_IHM16M1_POT=y +CONFIG_BOARD_STM32_IHM16M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FIXED16_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FIXED16=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig new file mode 100644 index 0000000000000..d70d9724fe0e9 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -0,0 +1,88 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_PTHREAD is not set +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=3 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARMV7M_LIBM=y +CONFIG_BOARDCTL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BOARD_STM32_IHM16M1=y +CONFIG_BOARD_STM32_IHM16M1_POT=y +CONFIG_BOARD_STM32_IHM16M1_VBUS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_EXAMPLES_FOC=y +CONFIG_EXAMPLES_FOC_ADC_MAX=4095 +CONFIG_EXAMPLES_FOC_ADC_VREF=3300 +CONFIG_EXAMPLES_FOC_CONTROL_STACKSIZE=2048 +CONFIG_EXAMPLES_FOC_FLOAT_INST=1 +CONFIG_EXAMPLES_FOC_HAVE_BUTTON=y +CONFIG_EXAMPLES_FOC_NOTIFIER_FREQ=10000 +CONFIG_EXAMPLES_FOC_PWM_FREQ=20000 +CONFIG_EXAMPLES_FOC_RAMP_ACC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_DEC=1000000 +CONFIG_EXAMPLES_FOC_RAMP_THR=10000 +CONFIG_EXAMPLES_FOC_SETPOINT_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_ADC=y +CONFIG_EXAMPLES_FOC_VBUS_SCALE=16000 +CONFIG_INDUSTRY_FOC=y +CONFIG_INDUSTRY_FOC_FLOAT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MOTOR=y +CONFIG_MOTOR_FOC=y +CONFIG_MOTOR_FOC_TRACE=y +CONFIG_MQ_MAXMSGSIZE=5 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1_CH1MODE=0 +CONFIG_STM32_TIM1_CH2MODE=0 +CONFIG_STM32_TIM1_CH3MODE=0 +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART2_TXDMA=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig new file mode 100644 index 0000000000000..2741f79a4ff4b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_LTO_FULL=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_OSTEST_STACKSIZE=1024 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig new file mode 100644 index 0000000000000..7bb17b75b5be1 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=80 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig new file mode 100644 index 0000000000000..f593ed1dac3d3 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g431rb" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NUCLEO_G431RB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_QENCODER=y +CONFIG_EXAMPLES_QENCODER_HAVE_MAXPOS=y +CONFIG_EXAMPLES_QENCODER_MAXPOS=8192 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=22528 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=10 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS=y +CONFIG_STM32_QENCODER_SAMPLE_FDTS_2=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_QE=y +CONFIG_STM32_TIM2_QEPSC=0 +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32g4/nucleo-g431rb/include/board.h b/boards/arm/stm32g4/nucleo-g431rb/include/board.h new file mode 100644 index 0000000000000..75cc137c57439 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/include/board.h @@ -0,0 +1,399 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define STM32_BOARD_XTAL 24000000 /* 8MHz */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSI + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSI */ + +#ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE + +/* Main PLL Configuration. + * + * PLL source is HSE = 24MHz + * PLLN = 86, PLLM = 6, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSE x PLLN / PLLM + * = 24MHz x 86 / 6 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSE +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(86) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(6) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +#endif /* CONFIG_BOARD_NUCLEO_G431RB_USE_HSE */ + +/* APB2 timers 1, 8, 20 and 15-17 will receive PCLK2. */ + +/* Timers driven from APB2 will be PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 timers 2-7 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* USB divider -- Divide PLL clock by 1.5 */ + +#define STM32_CFGR_USBPRE 0 + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + */ + +#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) +#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) + +#ifdef CONFIG_STM32_FDCAN +# ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE +# define STM32_CCIPR_FDCANSRC (RCC_CCIPR_FDCANSEL_HSE) +# define STM32_FDCAN_FREQUENCY (STM32_HSE_FREQUENCY) +# else +# error For now FDCAN supported only if HSE enabled +# endif +#endif + +/* LED definitions **********************************************************/ + +/* The NUCLEO-G431RB has four user LEDs. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo G431RB. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo G431RB supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32G431RB. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32G431RB. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* TIM2 input ***************************************************************/ + +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_3 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PA15 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_2 | GPIO_PULLUP | GPIO_SPEED_50MHz) /* PB3 */ + +/* USART2 (STLINK Virtual COM Port) */ + +#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ + +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* PA8 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_2|GPIO_SPEED_50MHz) /* PA11 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* PA9 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_1|GPIO_SPEED_50MHz) /* PA12 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* PA10 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_1|GPIO_SPEED_50MHz) /* PB1 */ +#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2|GPIO_SPEED_50MHz) /* PC3 */ + +/* CAN configuration ********************************************************/ + +#define GPIO_FDCAN1_RX (GPIO_FDCAN1_RX_2|GPIO_SPEED_50MHz) /* PB8 */ +#define GPIO_FDCAN1_TX (GPIO_FDCAN1_TX_2|GPIO_SPEED_50MHz) /* PB9 */ + +/* DMA channels *************************************************************/ + +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_DMA12_ADC1_0 /* DMA1 */ + +/* USART2 */ + +#define DMACHAN_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1 */ +#define DMACHAN_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1 */ + +#ifdef CONFIG_BOARD_STM32_IHM16M1 + +/* Configuration specific for the X-NUCLEO-IHM16M1 expansion board with + * the STSPIN830 driver. + */ + +/* TIM1 configuration *******************************************************/ + +# define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH1 - PA8 - U high */ +# define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH2 - PA9 - V high */ +# define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_1|GPIO_SPEED_50MHz) /* TIM1 CH3 - PA10 - W high */ +# define GPIO_TIM1_CH4OUT 0 /* not used as output */ + +/* UVW ENABLE */ + +# define GPIO_FOC_EN_U (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13) +# define GPIO_FOC_EN_V (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN14) +# define GPIO_FOC_EN_W (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN15) + +/* EN_FAULT */ + +# define GPIO_FOC_ENFAULT (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12) + +/* Debug pins */ + +# define GPIO_FOC_DEBUG0 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +# define GPIO_FOC_DEBUG1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9) +# define GPIO_FOC_DEBUG2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) +# define GPIO_FOC_DEBUG3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \ + GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN12) + +#endif /* CONFIG_BOARD_STM32_IHM16M1 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G431RB_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs new file mode 100644 index 0000000000000..2eb0f2b84635d --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script new file mode 100644 index 0000000000000..bd82a15d578b7 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G431RB has 128 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G431RB has a total of 32 KiB of SRAM in three separate areas: + * + * 1) 16 KiB SRAM1 mapped at 0x2000:0000 thru 0x2000:3fff. + * 2) 6 KiB SRAM2 mapped at 0x2000:4000 thru 0x2000:57ff. + * + * CCM SRAM (Routine Booster): + * + * 3) 10 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:27ff + * but also aliased at at 0x2000:5800 thru 0x2000:7fff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 22K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431rb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431rb/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt new file mode 100644 index 0000000000000..21262028d4494 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt @@ -0,0 +1,64 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(NOT CONFIG_STM32_FOC) + if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) + endif() + + if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) + endif() +endif() + +if(CONFIG_BOARD_STM32_IHM16M1) + list(APPEND SRCS stm32_foc_ihm16m1.c) +endif() + +if(CONFIG_MATH_CORDIC) + list(APPEND SRCS stm32_cordic.c) +endif() + +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_cansock.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs new file mode 100644 index 0000000000000..17328e8d98967 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs @@ -0,0 +1,67 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g431rb/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifneq ($(CONFIG_STM32_FOC),y) +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif +endif + +ifeq ($(CONFIG_BOARD_STM32_IHM16M1),y) +CSRCS += stm32_foc_ihm16m1.c +endif + +ifeq ($(CONFIG_MATH_CORDIC),y) +CSRCS += stm32_cordic.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CSRCS += stm32_cansock.c +endif +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h similarity index 99% rename from boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h rename to boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h index a00571f7c2ead..c1aab3f25c279 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h +++ b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h + * boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c new file mode 100644 index 0000000000000..23dcbdf7b6e57 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c @@ -0,0 +1,240 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 1, + 2, + 15 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN1_0, /* PA0/A0 */ + GPIO_ADC1_IN2_0, /* PA1/A1 */ + GPIO_ADC1_IN15_0, /* PB0/A3 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 17, + 7, + 6 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC2_IN17_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 17, + 7, + 6 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC2_IN17_0, /* PA4/A2 */ + GPIO_ADC2_IN7_0, /* PC1/A4 */ + GPIO_ADC2_IN6_0, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c new file mode 100644 index 0000000000000..74c7bf61f79cf --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c new file mode 100644 index 0000000000000..8f5ac067df973 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c new file mode 100644 index 0000000000000..82b3a8be71f0b --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FOC + /* Initialize and register the FOC device - must be before ADC setup */ + + ret = stm32_foc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_foc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_MATH_CORDIC + /* Initialize CORDIC and register the CORDIC driver. */ + + ret = stm32_cordic_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cordic_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_NUCLEO_G431RB_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_fdcan_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET + /* Initialize CAN socket interface */ + + ret = stm32_cansock_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_cansock_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c new file mode 100644 index 0000000000000..f6bf2f0c90ff9 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A HIGH value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c new file mode 100644 index 0000000000000..5a91c6e2fe0f6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_fdcan.h" +#include "nucleo-g431rb.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if !defined(CONFIG_STM32_FDCAN1) +# error "No CAN is enable. Please enable at least one CAN device" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ + struct can_dev_s *can; + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the CAN interface */ + + can = stm32_fdcaninitialize(1); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c new file mode 100644 index 0000000000000..c76c3ce5b2add --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "stm32_fdcan.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cansock_setup + * + * Description: + * Initialize CAN socket interface + * + ****************************************************************************/ + +int stm32_cansock_setup(void) +{ + int ret; + + /* Call stm32_fdcaninitialize() to get an instance of the FDCAN interface */ + + ret = stm32_fdcansockinitialize(1); + if (ret < 0) + { + canerr("ERROR: Failed to get FDCAN interface %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c index aa3a53201768c..9318847fd2d55 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c index 73316003dd0e7..bf5f99735eb70 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c new file mode 100644 index 0000000000000..c91702c323e3e --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-g431rb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOG431RB_PWMTIMER); + if (!pwm) + { + tmrerr("Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c new file mode 100644 index 0000000000000..6d6bc7e72b0da --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g431rb.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt new file mode 100644 index 0000000000000..4f4bba4b7afca --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/Kconfig b/boards/arm/stm32g4/nucleo-g474re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g474re/Kconfig rename to boards/arm/stm32g4/nucleo-g474re/Kconfig diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig new file mode 100644 index 0000000000000..ee2a8c2db94c2 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMAMUX1=y +CONFIG_STM32_FLASH_CONFIG_E=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig new file mode 100644 index 0000000000000..6a8c6317f5719 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig new file mode 100644 index 0000000000000..405eabc8cdb02 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_DISABLE_OS_API is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-g474re" +CONFIG_ARCH_BOARD_NUCLEO_G474RE=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32g4" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y +CONFIG_ARCH_HIPRI_INTERRUPT=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_LIBM=y +CONFIG_ARMV7M_MEMCPY=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_CDCACM=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_HARDFAULT_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USB=y +CONFIG_DEBUG_USB_ERROR=y +CONFIG_DEBUG_USB_WARN=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS=y +CONFIG_SYSTEM_NSH=y +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBDEV_BUSPOWERED=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_ISOCHRONOUS=y +CONFIG_USBDEV_MAXPOWER=500 +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32g4/nucleo-g474re/include/board.h b/boards/arm/stm32g4/nucleo-g474re/include/board.h new file mode 100644 index 0000000000000..8fbf7924c8ee6 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/include/board.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEO-G474RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#undef STM32_BOARD_XTAL /* Not installed by default */ + +#define STM32_HSI_FREQUENCY 16000000ul /* 16MHz */ +#define STM32_LSI_FREQUENCY 32000 /* 32kHz */ +#undef STM32_HSE_FREQUENCY /* Not installed by default */ +#undef STM32_LSE_FREQUENCY /* Not available on this board */ + +/* Main PLL Configuration. + * + * PLL source is HSI = 16MHz + * PLLN = 85, PLLM = 4, PLLP = 10, PLLQ = 2, PLLR = 2 + * + * f(VCO Clock) = f(PLL Clock Input) x (PLLN / PLLM) + * f(PLL_P) = f(VCO Clock) / PLLP + * f(PLL_Q) = f(VCO Clock) / PLLQ + * f(PLL_R) = f(VCO Clock) / PLLR + * + * Where: + * 8 <= PLLN <= 127 + * 1 <= PLLM <= 16 + * PLLP = 2 through 31 + * PLLQ = 2, 4, 6, or 8 + * PLLR = 2, 4, 6, or 8 + * + * Do not exceed 170MHz on f(PLL_P), f(PLL_Q), or f(PLL_R). + * 64MHz <= f(VCO Clock) <= 344MHz. + * + * Given the above: + * + * f(VCO Clock) = HSI x PLLN / PLLM + * = 16MHz x 85 / 4 + * = 340MHz + * + * PLLPCLK = f(VCO Clock) / PLLP + * = 340MHz / 10 + * = 34MHz + * (May be used for ADC) + * + * PLLQCLK = f(VCO Clock) / PLLQ + * = 340MHz / 2 + * = 170MHz + * (May be used for QUADSPI, FDCAN, SAI1, I2S3. If set to + * 48MHz, may be used for USB, RNG.) + * + * PLLRCLK = f(VCO Clock) / PLLR + * = 340MHz / 2 + * = 170MHz + * (May be used for SYSCLK and most peripherals.) + */ + +#define STM32_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_HSI +#define STM32_PLLCFGR_PLLCFG (RCC_PLLCFGR_PLLPEN | \ + RCC_PLLCFGR_PLLQEN | \ + RCC_PLLCFGR_PLLREN) + +#define STM32_PLLCFGR_PLLN RCC_PLLCFGR_PLLN(85) +#define STM32_PLLCFGR_PLLM RCC_PLLCFGR_PLLM(4) +#define STM32_PLLCFGR_PLLP RCC_PLLCFGR_PLLPDIV(10) +#define STM32_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_2 +#define STM32_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_2 + +#define STM32_VCO_FREQUENCY ((STM32_HSI_FREQUENCY / 4) * 85) +#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 10) +#define STM32_PLLQ_FREQUENCY (STM32_VCO_FREQUENCY / 2) +#define STM32_PLLR_FREQUENCY (STM32_VCO_FREQUENCY / 2) + +/* Use the PLL and set the SYSCLK source to be PLLR (170MHz) */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY STM32_PLLR_FREQUENCY + +/* AHB clock (HCLK) is SYSCLK (170MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (170MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The NucleoG474RE board has one user LED. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* LD2 (Green) */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 user LEDs + * on the board. The following definitions describe how NuttX controls the + * LEDs: + * + * |--------------------|-------------------------|------------| + * | SYMBOL | Meaning | LED states | + * |--------------------|-------------------------|------------| + * | LED_STARTED | NuttX has been started | 0 0 0 0 | + * | LED_HEAPALLOCATE | Heap has been allocated | 0 0 0 0 | + * | LED_IRQSENABLED | Interrupts enabled | 0 0 0 0 | + * | LED_STACKCREATED | Idle stack created | 1 0 0 0 | + * | LED_INIRQ | In an interrupt | No change | + * | LED_SIGNAL | In a signal handler | No change | + * | LED_ASSERTION | An assertion failed | No change | + * | LED_PANIC | The system has crashed | 0 B 0 0 | + * | LED_IDLE | STM32 is in sleep mode | Not used | + * |--------------------|-------------------------|------------| + * + * LED states legend: + * 0 = off + * 1 = on + * B = blink + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* Alternate function pin selections ****************************************/ + +/* LPUART1 (ST LINK V3E Virtual Console) */ +#define GPIO_LPUART1_TX GPIO_LPUART1_TX_1 /* PA2 */ +#define GPIO_LPUART1_RX GPIO_LPUART1_RX_1 /* PA3 */ +#define GPIO_LPUART1_CTS GPIO_LPUART1_CTS_1 /* PA6 */ +#define GPIO_LPUART1_RTS GPIO_LPUART1_RTS_1 /* PB1 */ + +/* USART3 Pins CN7 Pins 1 and 2 */ +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PC10 */ +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PC11 */ + +/* Pin Multiplexing Disambiguation ******************************************/ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_G474RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs new file mode 100644 index 0000000000000..1ab6247f01c1c --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script new file mode 100644 index 0000000000000..4aca8670722cb --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script @@ -0,0 +1,139 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu new file mode 100644 index 0000000000000..152d9a3852f63 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu @@ -0,0 +1,142 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32G474RE has 512 KiB of FLASH beginning at address 0x0800:0000. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. The FLASH bootloader is located there and + * allocated up to 24KiB (6 pages of 4k if single bank mode or 12 pages of 2k + * if dual bank mode), so our executable will begin at 0x0800:6000, leaving + * 488KiB. + * + * The STM32G474RE has a total of 128 KiB of SRAM in three separate areas: + * + * 1) 80 KiB SRAM1 mapped at 0x2000:0000 thru 0x2001:3fff. + * 2) 16 KiB SRAM2 mapped at 0x2001:4000 thru 0x2001:7fff. + * + * CCM SRAM (Routine Booster): + * + * 3) 32 KiB CCM SRAM mapped at 0x1000:0000 thru 0x1000:7fff + * but also aliased at at 0x2001:8000 thru 0x2001:ffff to be contiguous + * with the SRAM1 and SRAM2. + * + * Because SRAM1 and SRAM2 are contiguous, they are treated as one region + * by this logic. + * + * CCM SRAM is also contiguous to SRAM1 and SRAM2, however it is excluded + * from this linker script, to keep it reserved for special uses in code. + * REVISIT: Is this the correct way to handle CCM SRAM? + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08006000, LENGTH = 488K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/nucleo-g474re/src/.gitignore b/boards/arm/stm32g4/nucleo-g474re/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g474re/src/.gitignore rename to boards/arm/stm32g4/nucleo-g474re/src/.gitignore diff --git a/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt new file mode 100644 index 0000000000000..494c3bcb57767 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_usbdev.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32g4/nucleo-g474re/src/Make.defs b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs new file mode 100644 index 0000000000000..7d2f9725ab003 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs @@ -0,0 +1,40 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g474re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_USBDEV),y) + CSRCS += stm32_usbdev.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h rename to boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h index 3609b90e7e581..e50ff639c455d 100644 --- a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h +++ b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h + * boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..28380bf71d735 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-g474re.h" + +#if defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c new file mode 100644 index 0000000000000..9b8eced144d8e --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-g474re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_ARCH_LEDS) + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. + * This additional initialization phase may be used, for example, to + * initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c new file mode 100644 index 0000000000000..89d86a499fe21 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nucleo-g474re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret; + +#if defined(HAVE_LEDS) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize CDCACM */ + + syslog(LOG_INFO, "Initialize CDCACM device\n"); + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c new file mode 100644 index 0000000000000..389fb718f11d3 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32.h" +#include "nucleo-g474re.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} diff --git a/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c new file mode 100644 index 0000000000000..16dcca37aee5f --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-g474re.h" + +#if !defined(CONFIG_ARCH_LEDS) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * Initialize the user LEDs before use. Note: For this function to be + * available to user application logic, CONFIG_ARCH_LEDS must not be + * defined. + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * Allow user application logic to control LEDs one at a time. Note: For + * this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * led: Index to the LED, which may be one of the defines BOARD_LED1, + * BOARD_LED2, BOARD_LED3, or BOARD_LED4. + * ledon: true to turn the LED on, false to turn it off. + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + switch (led) + { + case BOARD_LED1: + stm32_gpiowrite(GPIO_LED1, ledon); + break; + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * Allow user application logic to control all LEDs in one function call. + * Note: For this function to be available to user application logic, + * CONFIG_ARCH_LEDS must not be defined. + * + * Parameters: + * ledset: Bitmask indicating the new state for all LEDs, where a set bit + * indicates LED on and a clear bit indicates LED off. To + * construct the bitmask, using a bitwise OR of the defines + * BOARD_LED1_BIT, BOARD_LED2_BIT, BOARD_LED3_BIT, and/or + * BOARD_LED4_BIT. + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/common/CMakeLists.txt b/boards/arm/stm32l1/common/CMakeLists.txt new file mode 100644 index 0000000000000..92e3c5d09db04 --- /dev/null +++ b/boards/arm/stm32l1/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l1/common/Kconfig b/boards/arm/stm32l1/common/Kconfig new file mode 100644 index 0000000000000..5c48f62a0258b --- /dev/null +++ b/boards/arm/stm32l1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l1/common/Makefile b/boards/arm/stm32l1/common/Makefile new file mode 100644 index 0000000000000..8217b07f906ae --- /dev/null +++ b/boards/arm/stm32l1/common/Makefile @@ -0,0 +1,39 @@ +############################################################################# +# boards/arm/stm32l1/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt new file mode 100644 index 0000000000000..199de2f567a0c --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/Kconfig b/boards/arm/stm32l1/nucleo-l152re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-l152re/Kconfig rename to boards/arm/stm32l1/nucleo-l152re/Kconfig diff --git a/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig new file mode 100644 index 0000000000000..73ee4c8eb4ec2 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NX_DISABLE_16BPP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l152re" +CONFIG_ARCH_BOARD_NUCLEO_L152RE=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_NX=y +CONFIG_EXAMPLES_NXDEMO=y +CONFIG_EXAMPLES_NXDEMO_BPP=16 +CONFIG_EXAMPLES_NX_BPP=16 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_EXTERNINIT=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_ILI9341=y +CONFIG_LCD_ILI9341_IFACE0=y +CONFIG_LCD_ILI9341_IFACE0_PORTRAIT=y +CONFIG_LCD_PORTRAIT=y +CONFIG_LINE_MAX=64 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_NX=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_NXFONT_SANS22X29B=y +CONFIG_NXFONT_SANS23X27=y +CONFIG_NX_BLOCKING=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=81920 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig new file mode 100644 index 0000000000000..3b73a53c8df5c --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-l152re" +CONFIG_ARCH_BOARD_NUCLEO_L152RE=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_MUTEX_UNSAFE=y +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=81920 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l1/nucleo-l152re/include/board.h b/boards/arm/stm32l1/nucleo-l152re/include/board.h new file mode 100644 index 0000000000000..a8e89cabee046 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/include/board.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_NUCLEOL152RE_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 16 MHz RC oscillator + * - HSE high-speed external oscillator clock. 8 MHz from MCO output of + * ST-LINK. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. + * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, + * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) + * and 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSE -> 8MHz + * - PLL multiplier is 12 -> 96MHz PLL VCO clock output + * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output + * + * Resulting SYSCLK frequency is 8MHz x 12 / 3 = 32MHz + * + * USB/SDIO: + * If the USB or SDIO interface is used in the application, the PLL VCO + * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 + * MHz frequency. This is required to provide a 48 MHz clock to the USB or + * SDIO (SDIOCLK or USBCLK = PLLVCO/2). + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * 24 MHz when the product is in range 3 (1.2V). + * Output division to avoid exceeding 32 MHz as SYSCLK. + * The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#if 1 +#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC /* PLL clocked by the HSE */ +#define STM32_HSEBYP_ENABLE 1 +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +#define STM32_PLL_FREQUENCY (12*STM32_BOARD_XTAL) /* PLL VCO Frequency is 96MHz */ +#else +#define STM32_CFGR_PLLSRC 0 /* PLL clocked by the HSI RC */ +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ +#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN STM32_PCLK2_FREQUENCY + +/* APB1 clock (PCLK1) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY + +/* TODO: Timers */ + +/* LED definitions **********************************************************/ + +/* The Nucleo L152RE board has three LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD1 default status is red. LD1 turns to green to indicate that + * communications are in progress between the PC and the + * ST-LINK/V2-1. + * LD3 PWR: red LED indicates that the board is powered. + * + * And one can be controlled by software: + * + * User LD2: green LED is a user LED connected to the I/O PA5 of the + * STM32L152RET6. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in + * any way. The following definition is used to access the LED. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD2 */ +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Nucleo L152RE. The following definitions describe how NuttX controls + * the LED: + * + * SYMBOL Meaning LED1 state + * ------------------ ----------------------- ---------- + * LED_STARTED NuttX has been started OFF + * LED_HEAPALLOCATE Heap has been allocated OFF + * LED_IRQSENABLED Interrupts enabled OFF + * LED_STACKCREATED Idle stack created ON + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 1 + +/* Button definitions *******************************************************/ + +/* The Nucleo L152RE supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user button connected to the I/O PC13 of the STM32L152RET6. + * B2 RESET: push button connected to NRST is used to RESET the + * STM32L152RET6. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* USART */ + +/* By default the USART2 is connected to STLINK Virtual COM Port: + * USART2_RX - PA3 + * USART2_TX - PA2 + */ + +#define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ +#define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ + +/* SPI1 */ + +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 + +/* I2C1 */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2|GPIO_SPEED_40MHz) /* PB8 CN5 pin 10, D15 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2|GPIO_SPEED_40MHz) /* PB9 CN5 pin 9, D14 */ + +#endif /* __BOARDS_ARM_STM32_NUCLEO_L152RE_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs new file mode 100644 index 0000000000000..656e9afe07095 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script new file mode 100644 index 0000000000000..747f91401b8a1 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/scripts/ld.script + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32L152RET6 has 512Kb of FLASH beginning at address 0x0800:0000, + * 80Kb of SRAM, and 16Kb of EEPROM. + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 512K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 80K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt new file mode 100644 index 0000000000000..9177895b7e42f --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_LCD_ILI9341) + list(APPEND SRCS stm32_ili93418b.c) +endif() + +if(CONFIG_MMCSD_SPI) + list(APPEND SRCS stm32_spisd.c) +endif() + +if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32l1/nucleo-l152re/src/Make.defs b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs new file mode 100644 index 0000000000000..b1d374b5b3ed6 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32l1/nucleo-l152re/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_LCD_ILI9341),y) +CSRCS += stm32_ili93418b.c +endif + +ifeq ($(CONFIG_MMCSD_SPI),y) +CSRCS += stm32_spisd.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CSRCS += stm32_spi.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h rename to boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h index dbdcb8cbf1ad8..7533f5860f92f 100644 --- a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h +++ b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h + * boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c new file mode 100644 index 0000000000000..dcab65cab6df1 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, true); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c new file mode 100644 index 0000000000000..3545cdbafa058 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_i2c.h" + +#include "nucleo-l152re.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_LEDS +#undef HAVE_DAC + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) +# define HAVE_LEDS 1 +#endif + +#if defined(CONFIG_DAC) +# define HAVE_DAC 1 +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + int ret; +#ifdef CONFIG_STM32_I2C1 + struct i2c_master_s *i2c1; +#endif +#ifdef CONFIG_STM32_I2C2 + struct i2c_master_s *i2c2; +#endif + +#ifdef CONFIG_STM32_I2C1 + /* Get the I2C lower half instance */ + + i2c1 = stm32_i2cbus_initialize(1); + if (i2c1 == NULL) + { + i2cerr("ERROR: Initialize I2C1: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c1, 1); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C1 device: %d\n", ret); + } + } +#endif + +#ifdef CONFIG_STM32_I2C2 + /* Get the I2C lower half instance */ + + i2c2 = stm32_i2cbus_initialize(2); + if (i2c2 == NULL) + { + i2cerr("ERROR: Initialize I2C2: %d\n", ret); + } + else + { + /* Register the I2C character driver */ + + ret = i2c_register(i2c2, 2); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C2 device: %d\n", ret); + } + } +#endif + +#ifdef CONFIG_STM32_SPI + stm32_spiinitialize(); +#endif + +#ifdef HAVE_LEDS + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + return; + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(0, STM32_PROCFS_MOUNTPOINT, "procfs", 0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + STM32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_MMCSD_SPI + + /* Initialize the MMC/SD SPI driver (SPI1 is used) */ + + ret = stm32_spisd_initialize(1, CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + + UNUSED(ret); +} +#endif diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c new file mode 100644 index 0000000000000..645eac093f85a --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the single button as an input. NOTE that EXTI interrupts are + * also configured for the pin. + */ + + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit unsigned integer with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + /* Check the state of the USER button. A LOW value means that the key is + * pressed. + */ + + return stm32_gpioread(GPIO_BTN_USER) ? 0 : BUTTON_USER_BIT; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of the + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + arg); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c index 7b8052671c0c5..a07de22023d63 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c new file mode 100644 index 0000000000000..66b5dae214d76 --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-l152re.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global driver instances */ + +#ifdef CONFIG_STM32_SPI1 + struct spi_dev_s *g_spi1; +#endif +#ifdef CONFIG_STM32_SPI2 + struct spi_dev_s *g_spi2; +#endif +#ifdef CONFIG_STM32_SPI3 + struct spi_dev_s *g_spi3; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spiinitialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + ****************************************************************************/ + +void weak_function stm32_spiinitialize(void) +{ + int ret; +#ifdef CONFIG_STM32_SPI1 + /* Initialize the SPI1 bus */ + + g_spi1 = stm32_spibus_initialize(1); + if (g_spi1 == NULL) + { + spierr("ERROR: Initialize SPI1: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI1 character driver */ + + ret = spi_register(g_spi1, 1); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI1 device: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_STM32_SPI2 + /* Initialize the SPI2 bus */ + + g_spi2 = stm32_spibus_initialize(2); + if (g_spi2 == NULL) + { + spierr("ERROR: Initialize SPI2: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI2 character driver */ + + ret = spi_register(g_spi2, 2); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI2 device: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_STM32_SPI3 + /* Initialize the SPI3 bus */ + + g_spi3 = stm32_spibus_initialize(3); + if (g_spi3 == NULL) + { + spierr("ERROR: Initialize SPI3: \n"); + } + +#ifdef CONFIG_SPI_DRIVER + /* Register the SPI3 character driver */ + + ret = spi_register(g_spi3, 3); + if (ret < 0) + { + spierr("ERROR: Failed to register SPI3 device: %d\n", ret); + } +#endif +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); + +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + stm32_gpiowrite(GPIO_SPI1_CS, !selected); + } +#endif +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; +#if defined(CONFIG_MMCSD_SPI) + if (devid == SPIDEV_MMCSD(0)) + { + status |= SPI_STATUS_PRESENT; + } +#endif + + return status; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : + "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c index c08c068b2fb90..9683f10cc4c87 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c new file mode 100644 index 0000000000000..bb9d60e5a2c0b --- /dev/null +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" +#include "nucleo-l152re.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1 GPIO for output */ + + stm32_configgpio(GPIO_LED1); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + stm32_gpiowrite(GPIO_LED1, ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt new file mode 100644 index 0000000000000..86a0d6e5493ff --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32ldiscovery/Kconfig b/boards/arm/stm32l1/stm32ldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32ldiscovery/Kconfig rename to boards/arm/stm32l1/stm32ldiscovery/Kconfig diff --git a/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig new file mode 100644 index 0000000000000..c965f4dc993bf --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +# CONFIG_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32ldiscovery" +CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_BUILTIN=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_ENABLE_ALL_SIGNALS=y +CONFIG_EXAMPLES_CHRONO=y +CONFIG_EXAMPLES_SLCD=y +CONFIG_FILE_STREAM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LIBC_SLCDCODEC=y +CONFIG_LWL_CONSOLE=y +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_DATETIME=y +CONFIG_SCHED_WAITPID=y +CONFIG_SLCD=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_LCD=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig new file mode 100644 index 0000000000000..e07f7bfeadc46 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32ldiscovery" +CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y +CONFIG_ARCH_CHIP="stm32l1" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=2796 +CONFIG_DEFAULT_SMALL=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_HOST_WINDOWS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NUNGET_CHARS=0 +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=19 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_BAUD=57600 +CONFIG_USART1_RXBUFSIZE=64 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART1_TXBUFSIZE=64 diff --git a/boards/arm/stm32l1/stm32ldiscovery/include/board.h b/boards/arm/stm32l1/stm32ldiscovery/include/board.h new file mode 100644 index 0000000000000..9e1c58d534cde --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/include/board.h @@ -0,0 +1,307 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* Four different clock sources can be used to drive the system clock + * (SYSCLK): + * + * - HSI high-speed internal oscillator clock + * Generated from an internal 16 MHz RC oscillator + * - HSE high-speed external oscillator clock + * Normally driven by an external crystal (X3). However, this crystal is + * not fitted on the STM32L-Discovery board. + * - PLL clock + * - MSI multispeed internal oscillator clock + * The MSI clock signal is generated from an internal RC oscillator. + * Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, + * 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and + * 4.194 MHz. + * + * The devices have the following two secondary clock sources + * - LSI low-speed internal RC clock + * Drives the watchdog and RTC. Approximately 37KHz + * - LSE low-speed external oscillator clock + * Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins. + */ + +#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/ + +#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */ +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */ +#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */ +#define STM32_LSE_FREQUENCY 32768 /* X2 on board */ + +/* PLL Configuration + * + * - PLL source is HSI -> 16MHz input (nominal) + * - PLL multiplier is 6 -> 96MHz PLL VCO clock output (for USB) + * - PLL output divider 3 -> 32MHz divided down PLL VCO clock output + * + * Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz + * + * USB/SDIO: + * If the USB or SDIO interface is used in the application, the PLL VCO + * clock (defined by STM32_CFGR_PLLMUL) must be programmed to output a 96 + * MHz frequency. This is required to provide a 48 MHz clock to the USB or + * SDIO (SDIOCLK or USBCLK = PLLVCO/2). + * SYSCLK + * The system clock is derived from the PLL VCO divided by the output + * division factor. + * Limitations: + * 96 MHz as PLLVCO when the product is in range 1 (1.8V), + * 48 MHz as PLLVCO when the product is in range 2 (1.5V), + * 24 MHz when the product is in range 3 (1.2V). + * Output division to avoid exceeding 32 MHz as SYSCLK. + * The minimum input clock frequency for PLL is 2 MHz (when using HSE as + * PLL source). + */ + +#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */ +#ifdef CONFIG_STM32_USB +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */ +# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */ +#else +# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */ +# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */ +# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */ +#endif + +/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO + * output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value). + */ + +#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ +#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL +#ifdef CONFIG_STM32_USB +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequency is 96MHz/PLLDIV = 32MHz */ +#else +# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequency is 64MHz/PLLDIV = 32MHz */ +#endif + +/* AHB clock (HCLK) is SYSCLK (32MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK +#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB2 timers 9, 10, and 11 will receive PCLK2. */ + +#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 clock (PCLK1) is HCLK (32MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY) + +/* APB1 timers 2-7 will receive PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + +/* LED definitions **********************************************************/ + +/* The STM32L-Discovery board has four LEDs. Two of these are controlled by + * logic on the board and are not available for software control: + * + * LD1 COM: LD2 default status is red. LD2 turns to green to indicate + * that communications are in progress between the PC and the + * ST-LINK/V2. + * LD2 PWR: Red LED indicates that the board is powered. + * + * And two LEDs can be controlled by software: + * + * User LD3: Green LED is a user LED connected to the I/O PB7 of the + * STM32L152 MCU. + * User LD4: Blue LED is a user LED connected to the I/O PB6 of the + * STM32L152 MCU. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 /* User LD3 */ +#define BOARD_LED2 1 /* User LD4 */ +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) + +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +#define LED_STARTED 0 +#define LED_HEAPALLOCATE 0 +#define LED_IRQSENABLED 0 +#define LED_STACKCREATED 1 +#define LED_INIRQ 2 +#define LED_SIGNAL 2 +#define LED_ASSERTION 2 +#define LED_PANIC 3 + +/* Button definitions *******************************************************/ + +/* The STM32L-Discovery supports two buttons; only one button is controllable + * by software: + * + * B1 USER: user and wake-up button connected to the I/O PA0 of the + * STM32L152. + * B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 + +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate Pin Functions **************************************************/ + +/* The STM32L-Discovery has no on-board RS-232 driver. Further, there + * are no USART pins that do not conflict with the on board resources, in + * particular, the LCD. Most USART pins are available if the LCD is enabled; + * USART2 may be used if either the LCD or the on-board LEDs are disabled. + * + * PA9 USART1_TX LCD glass COM1 P2, pin 22 + * PA10 USART1_RX LCD glass COM2 P2, pin 21 + * PB6 USART1_TX LED Blue P2, pin 8 + * PB7 USART1_RX LED Green P2, pin 7 + * + * PA2 USART2_TX LCD SEG1 P1, pin 17 + * PA3 USART2_RX LCD SEG2 P1, pin 18 + * + * PB10 USART3_TX LCD SEG6 P1, pin 22 + * PB11 USART3_RX LCD SEG7 P1, pin 23 + * PC10 USART3_TX LCD SEG22 P2, pin 15 + * PC11 USART3_RX LCD SEG23 P2, pin 14 + */ + +#if !defined(CONFIG_STM32_LCD) +/* Select PA9 and PA10 if the LCD is not enabled */ + +# define GPIO_USART1_RX (GPIO_USART1_RX_1|GPIO_SPEED_40MHz) /* PA10 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_1|GPIO_SPEED_40MHz) /* PA9 */ + +/* This there are no other options for USART1 on this part */ + +# define GPIO_USART2_RX (GPIO_USART2_RX_1|GPIO_SPEED_40MHz) /* PA3 */ +# define GPIO_USART2_TX (GPIO_USART2_TX_1|GPIO_SPEED_40MHz) /* PA2 */ + +/* Arbitrarily select PB10 and PB11 */ + +# define GPIO_USART3_RX (GPIO_USART3_RX_1|GPIO_SPEED_40MHz) /* PB11 */ +# define GPIO_USART3_TX (GPIO_USART3_TX_1|GPIO_SPEED_40MHz) /* PB10 */ + +#elif !defined(CONFIG_ARCH_LEDS) + +/* Select PB6 and PB7 if the LEDs are not enabled */ + +# define GPIO_USART1_RX (GPIO_USART1_RX_2|GPIO_SPEED_40MHz) /* PB7 */ +# define GPIO_USART1_TX (GPIO_USART1_TX_2|GPIO_SPEED_40MHz) /* PB6 */ + +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_slcd_initialize + * + * Description: + * Initialize the STM32L-Discovery LCD hardware and register the character + * driver as /dev/slcd0. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_LCD +int stm32_slcd_initialize(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32_STM32LDISCOVERY_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs new file mode 100644 index 0000000000000..ac42a7137153e --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_ARCH_CHIP_STM32L152RB),y) + LDSCRIPT = stm32l152rb.ld +else ifeq ($(CONFIG_ARCH_CHIP_STM32L152RC),y) + LDSCRIPT = stm32l152rc.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld index bb8c62933c6cf..184ed2885092f 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld index 81b7157ce808e..d295e75c07a35 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt new file mode 100644 index 0000000000000..a496f64f86b20 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ############################################################################## +# boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32_LCD) + list(APPEND SRCS stm32_lcd.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_STM32L152RB) + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32l152rb.ld") +else() + set_property(GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/stm32l152rc.ld") +endif() diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs new file mode 100644 index 0000000000000..f483afc2b244c --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32l1/stm32ldiscovery/src/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32_LCD),y) +CSRCS += stm32_lcd.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c new file mode 100644 index 0000000000000..e62f9ed148452 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If CONFIG_ARCH_LEDS is defined, then NuttX will control the 2 LEDs on + * board the STM32L-Discovery. The following definitions describe how NuttX + * controls the LEDs: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------- ----------------------- -------- -------- + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed OFF Blinking + * LED_IDLE STM32 is in sleep mode Not used + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool led1on = false; + bool led2on = false; + + switch (led) + { + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + break; + + case 1: /* LED_STACKCREATED */ + led1on = true; + break; + + default: + case 2: /* LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ + return; + + case 3: /* LED_PANIC */ + led2on = true; + break; + } + + stm32_gpiowrite(GPIO_LED1, led1on); + stm32_gpiowrite(GPIO_LED2, led2on); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led != 2) + { + stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED2, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c new file mode 100644 index 0000000000000..751e937f7996c --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c @@ -0,0 +1,91 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32ldiscovery.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + if (stm32_spidev_initialize) + { + stm32_spidev_initialize(); + } +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c new file mode 100644 index 0000000000000..ee512f314b309 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32ldiscovery.h" + +#ifdef CONFIG_SENSORS_QENCODER +# include "board_qencoder.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +#ifdef CONFIG_USERLED_LOWER + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable USER LED support for some other purpose */ + + board_userled_initialize(); +#endif /* CONFIG_USERLED_LOWER */ +#endif /* CONFIG_USERLED && !CONFIG_ARCH_LEDS */ + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#ifdef CONFIG_STM32_LCD + /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */ + + ret = stm32_slcd_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, CONFIG_STM32LDISCO_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + } +#endif + + return ret; +} diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c new file mode 100644 index 0000000000000..3f0e1ffb3311d --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32ldiscovery.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Pin configuration for each STM32F3Discovery button. This array is indexed + * by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = stm32_gpioread(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. See + * the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c new file mode 100644 index 0000000000000..379abcfa7bdb2 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c @@ -0,0 +1,1599 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* References: + * - Based on the NuttX LCD1602 driver. + * - "STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced + * ARM-based 32-bit MCUs", STMicroelectronics, RM0038 + * - "STM32L1 discovery kits: STM32L-DISCOVERY and 32L152CDISCOVERY," + * STMicroelectronics, UM1079 + * - STM32L-Discovery Firmware Pack V1.0.2 (for character encoding) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "hardware/stm32_lcd.h" + +#include "stm32ldiscovery.h" + +#ifdef CONFIG_STM32_LCD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Define CONFIG_DEBUG_LCD_INFO to enable detailed LCD debug output. */ + +#ifndef CONFIG_LIBC_SLCDCODEC +# error "This SLCD driver requires CONFIG_LIBC_SLCDCODEC" +#endif + +/* LCD **********************************************************************/ + +/* LCD. The STM32L152RBT6 supports either a 4x32 or 8x28. The STM32L- + * Discovery has an LCD 24 segments, 4 commons. See stm32ldiscovery.h for + * the pin mapping. + */ + +/* Macro to convert an LCD register offset and bit number into a bit-band + * address: + */ + +#define SLCD_OFFSET (STM32_LCD_BASE - STM32_PERIPH_BASE) +#define SLCD_BBADDR(o,b) (STM32_PERIPHBB_BASE + ((SLCD_OFFSET + (o)) << 5) + ((b) << 2)) + +/* Some useful bit-band addresses */ + +#define SLCD_CR_LCDEN_BB SLCD_BBADDR(STM32_LCD_CR_OFFSET,0) +#define SLCD_SR_UDR_BB SLCD_BBADDR(STM32_LCD_SR_OFFSET,2) + +/* LCD characteristics */ + +#define SLCD_NROWS 1 +#define SLCD_NCHARS 6 +#define SLCD_MAXCONTRAST 7 + +/* An ASCII character may need to be decorated with a colon or decimal + * point + */ + +#define SLCD_DP 0x01 +#define SLCD_COLON 0x02 +#define SLCD_NBARS 4 + +/* Macros used for set/reset the LCD bar */ + +#define SLCD_BAR0_ON g_slcdstate.bar[1] |= 8 +#define SLCD_BAR0_OFF g_slcdstate.bar[1] &= ~8 +#define SLCD_BAR1_ON g_slcdstate.bar[0] |= 8 +#define SLCD_BAR1_OFF g_slcdstate.bar[0] &= ~8 +#define SLCD_BAR2_ON g_slcdstate.bar[1] |= 2 +#define SLCD_BAR2_OFF g_slcdstate.bar[1] &= ~2 +#define SLCD_BAR3_ON g_slcdstate.bar[0] |= 2 +#define SLCD_BAR3_OFF g_slcdstate.bar[0] &= ~2 + +/* These definitions support the logic of slcd_writemem() + * + * ---------- ----- ----- ----- ----- ------- + * LCD SIGNAL COM3 COM2 COM1 COM0 RAM BIT + * + * ---------- ----- ----- ----- ----- ------- + * LCD SEG0 1N 1P 1D 1E Bit 0 + * LCD SEG1 1DP 1COL 1C 1M Bit 1 + * LCD SEG2 2N 2P 2D 2E Bit 2 + * LCD SEG3 2DP 2COL 2C 2M Bit 7 + * LCD SEG4 3N 3P 3D 3E Bit 8 + * LCD SEG5 3DP 3COL 3C 3M Bit 9 + * LCD SEG6 4N 4P 4D 4E Bit 10 + * LCD SEG7 4DP 4COL 4C 4M Bit 11 + * LCD SEG8 5N 5P 5D 5E Bit 12 + * LCD SEG9 BAR2 BAR3 5C 5M Bit 13 + * LCD SEG10 6N 6P 6D 6E Bit 14 + * LCD SEG11 BAR0 BAR1 6C 6M Bit 15 + * LCD SEG12 6J 6K 6A 6B Bit 16 + * LCD SEG13 6H 6Q 6F 6G Bit 17 + * LCD SEG14 5J 5K 5A 5B Bit 18 + * LCD SEG15 5H 5Q 5F 5G Bit 19 + * LCD SEG16 4J 4K 4A 4B Bit 20 + * LCD SEG17 4H 4Q 4F 4G Bit 21 + * LCD SEG18 3J 3K 3A 3B Bit 24 + * LCD SEG19 3H 3Q 3F 3G Bit 25 + * LCD SEG20 2J 2K 2A 2B Bit 26 + * LCD SEG21 2H 2Q 2F 2G Bit 27 + * LCD SEG22 1J 1K 1A 1B Bit 28 + * LCD SEG23 1H 1Q 1F 1G Bit 29 + * ---------- ----- ----- ----- ----- -------- + + * ---------------- ------ ------ ------ ------- ------- -------------------- + * LCD CHAR 1 CHAR 2 CHAR 3 CHAR 4 CHAR 5 CHAR 6 MASKS + * SIGNAL 3210 3210 3210 3210 32 10 32 10 + * --------- ------ ------ ------ ------ -- --- -- --- -------------------- + * LCD SEG0 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG1 0 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG2 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG3 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG4 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG5 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG6 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG7 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG8 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG9 0 0 0 0 0 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG10 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG11 0 0 0 0 0 0 0 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG12 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG13 0 0 0 0 0 0 1 1 CHAR 6: 0xfffc3fff/ + * 0xfffcbfff + * LCD SEG14 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG15 0 0 0 0 1 1 0 0 CHAR 5: 0xfff3cfff/ + * 0xfff3efff + * LCD SEG16 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG17 0 0 0 1 0 0 0 0 CHAR 4: 0xffcff3ff + * LCD SEG18 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG19 0 0 1 0 0 0 0 0 CHAR 3: 0xfcfffcff + * LCD SEG20 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG21 0 1 0 0 0 0 0 0 CHAR 2: 0xf3ffff7b + * LCD SEG22 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * LCD SEG23 1 0 0 0 0 0 0 0 CHAR 1: 0xcffffffc + * --------- ------ ------ ------ ------- ------- --------------------------- + */ + +/* SLCD_CHAR1_MASK COM0-3 0xcffffffc ..11 .... .... .... .... .... .... ..11 + */ + +#define SLCD_CHAR1_MASK0 0xcffffffc +#define SLCD_CHAR1_MASK1 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_MASK2 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_MASK3 SLCD_CHAR1_MASK0 +#define SLCD_CHAR1_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 26) | \ + ((uint32_t)(s) & 0x03) +#define SLCD_CHAR1_UPDATE1(s) SLCD_CHAR1_UPDATE0(s) +#define SLCD_CHAR1_UPDATE2(s) SLCD_CHAR1_UPDATE0(s) +#define SLCD_CHAR1_UPDATE3(s) SLCD_CHAR1_UPDATE0(s) + +/* SLCD_CHAR2_MASK COM0-3 0xf3ffff03 .... 22.. .... .... .... .... 2... .2.. + */ + +#define SLCD_CHAR2_MASK0 0xf3ffff7b +#define SLCD_CHAR2_MASK1 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_MASK2 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_MASK3 SLCD_CHAR2_MASK0 +#define SLCD_CHAR2_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 24) | \ + (((uint32_t)(s) & 0x02) << 6) | \ + (((uint32_t)(s) & 0x01) << 2) +#define SLCD_CHAR2_UPDATE1(s) SLCD_CHAR2_UPDATE0(s) +#define SLCD_CHAR2_UPDATE2(s) SLCD_CHAR2_UPDATE0(s) +#define SLCD_CHAR2_UPDATE3(s) SLCD_CHAR2_UPDATE0(s) + +/* SLCD_CHAR3_MASK COM0-3 0xfcfffcff .... ..33 .... .... .... ..33 .... .... + */ + +#define SLCD_CHAR3_MASK0 0xfcfffcff +#define SLCD_CHAR3_MASK1 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_MASK2 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_MASK3 SLCD_CHAR3_MASK0 +#define SLCD_CHAR3_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 22) | \ + (((uint32_t)(s) & 0x03) << 8) +#define SLCD_CHAR3_UPDATE1(s) SLCD_CHAR3_UPDATE0(s) +#define SLCD_CHAR3_UPDATE2(s) SLCD_CHAR3_UPDATE0(s) +#define SLCD_CHAR3_UPDATE3(s) SLCD_CHAR3_UPDATE0(s) + +/* SLCD_CHAR4_MASK COM0-3 0xffcff3ff .... .... ..44 .... .... 44.. .... .... + */ + +#define SLCD_CHAR4_MASK0 0xffcff3ff +#define SLCD_CHAR4_MASK1 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_MASK2 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_MASK3 SLCD_CHAR4_MASK0 +#define SLCD_CHAR4_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 18) | \ + (((uint32_t)(s) & 0x03) << 10) +#define SLCD_CHAR4_UPDATE1(s) SLCD_CHAR4_UPDATE0(s) +#define SLCD_CHAR4_UPDATE2(s) SLCD_CHAR4_UPDATE0(s) +#define SLCD_CHAR4_UPDATE3(s) SLCD_CHAR4_UPDATE0(s) + +/* SLCD_CHAR5_MASK COM0-1 0xfff3cfff .... .... .... 55.. ..55 .... .... .... + * COM2-3 0xfff3efff .... .... .... 55.. ...5 .... .... .... + */ + +#define SLCD_CHAR5_MASK0 0xfff3cfff +#define SLCD_CHAR5_MASK1 SLCD_CHAR5_MASK0 +#define SLCD_CHAR5_MASK2 0xfff3efff +#define SLCD_CHAR5_MASK3 SLCD_CHAR5_MASK2 +#define SLCD_CHAR5_UPDATE0(s) (((uint32_t)(s) & 0x0c) << 16) | \ + (((uint32_t)(s) & 0x03) << 12) +#define SLCD_CHAR5_UPDATE1(s) SLCD_CHAR5_UPDATE0(s) +#define SLCD_CHAR5_UPDATE2(s) (((uint32_t)(s) & 0x0c) << 16) | \ + (((uint32_t)(s) & 0x01) << 12) +#define SLCD_CHAR5_UPDATE3(s) SLCD_CHAR5_UPDATE2(s) + +/* SLCD_CHAR6_MASK COM0-1 0xfffc3fff .... .... .... ..66 66.. .... .... .... + * COM2-3 0xfffc3fff .... .... .... ..66 .6.. .... .... .... + */ + +#define SLCD_CHAR6_MASK0 0xfffc3fff +#define SLCD_CHAR6_MASK1 SLCD_CHAR6_MASK0 +#define SLCD_CHAR6_MASK2 0xfffcbfff +#define SLCD_CHAR6_MASK3 SLCD_CHAR6_MASK2 +#define SLCD_CHAR6_UPDATE0(s) (((uint32_t)(s) & 0x04) << 15) | \ + (((uint32_t)(s) & 0x08) << 13) | \ + (((uint32_t)(s) & 0x03) << 14) +#define SLCD_CHAR6_UPDATE1(s) SLCD_CHAR6_UPDATE0(s) +#define SLCD_CHAR6_UPDATE2(s) (((uint32_t)(s) & 0x04) << 15) | \ + (((uint32_t)(s) & 0x08) << 13) | \ + (((uint32_t)(s) & 0x03) << 14) +#define SLCD_CHAR6_UPDATE3(s) SLCD_CHAR6_UPDATE2(s) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Global SLCD state */ + +struct stm32_slcdstate_s +{ + bool initialized; /* True: Completed initialization sequence */ + uint8_t curpos; /* The current cursor position */ + uint8_t buffer[SLCD_NCHARS]; /* SLCD ASCII content */ + uint8_t options[SLCD_NCHARS]; /* With colon or decimal point decoration */ + uint8_t bar[2]; /* Controls the bars on the far right of the SLCD */ +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* Debug */ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpstate(const char *msg); +static void slcd_dumpslcd(const char *msg); +#else +# define slcd_dumpstate(msg) +# define slcd_dumpslcd(msg) +#endif + +/* Internal utilities */ + +static void slcd_clear(void); +static uint8_t slcd_getcontrast(void); +static int slcd_setcontrast(uint8_t contrast); +static void slcd_writebar(void); +static inline uint16_t slcd_mapch(uint8_t ch); +static inline void slcd_writemem(uint16_t segset, int curpos); +static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options); +static void slcd_appendch(uint8_t ch, uint8_t options); +static void slcd_action(enum slcdcode_e code, uint8_t count); + +/* Character driver methods */ + +static ssize_t slcd_read(struct file *, char *, size_t); +static ssize_t slcd_write(struct file *, const char *, size_t); +static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg); +static int slcd_poll(struct file *filep, struct pollfd *fds, + bool setup); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the driver state structure (there is no retained state + * information) + */ + +static const struct file_operations g_slcdops = +{ + NULL, /* open */ + NULL, /* close */ + slcd_read, /* read */ + slcd_write, /* write */ + NULL, /* seek */ + slcd_ioctl, /* ioctl */ + NULL, /* mmap */ + NULL, /* truncate */ + slcd_poll /* poll */ +}; + +/* LCD state data */ + +static struct stm32_slcdstate_s g_slcdstate; + +/* LCD Mapping + * + * A + * --------- _ + * |\ |J /| |_| COL + * F| H | K |B + * | \ | / | _ + * --G-- --M-+ |_| COL + * | /| \ | + * E| Q | N |C + * | / |P \| _ + * --------- |_| DP + * D + * + * LCD character 16-bit-encoding: + * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } + */ + +#warning "Encodings for all punctuation are incomplete" + +/* Space and ASCII punctuation: 0x20-0x2f */ + +static const uint16_t g_slcdpunct1[ASCII_0 - ASCII_SPACE] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* ! " # $ % & ' */ + 0x0000, 0x0000, 0xa0dd, 0x0000, 0x0000, 0xa000, 0x0000, 0x00c0 /* () * + , - . / */ +}; + +/* ASCII numerals 0-9: 0x30-0x39 */ + +static const uint16_t g_slcdnummap[ASCII_COLON - ASCII_0] = +{ + 0x5f00, 0x4200, 0xf500, 0x6700, 0xea00, 0xaf00, 0xbf00, 0x4600, /* 0-7 */ + 0xff00, 0xef00 /* 8-9 */ +}; + +/* ASCII punctuation: 0x3a-0x40 */ + +static const uint16_t g_slcdpunct2[ASCII_A - ASCII_COLON] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* : ; < = > ? @ */ +}; + +/* Upper case letters A-Z: 0x41-0x5a. Also lower case letters a-z: + * 0x61-0x7a + */ + +static const uint16_t g_slcdalphamap[ASCII_LBRACKET - ASCII_A] = +{ + 0xfe00, 0x6714, 0x1d00, 0x4714, 0x9d00, 0x9c00, 0x3f00, 0xfa00, /* A-H */ + 0x0014, 0x5300, 0x9841, 0x1900, 0x5a48, 0x5a09, 0x5f00, 0xfc00, /* I-P */ + 0x5f01, 0xfc01, 0xaf00, 0x0414, 0x5b00, 0x18c0, 0x5a81, 0x00c9, /* Q-X */ + 0x0058, 0x05c0 /* y-Z */ +}; + +/* ASCII punctuation: 0x5b-0x60 */ + +static const uint16_t g_slcdpunct3[ASCII_a - ASCII_LBRACKET] = +{ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /* [ \ ] ^ _ */ +}; + +/* ASCII punctuation: 0x7b-0x7e */ + +static const uint16_t g_slcdpunct4[ASCII_DEL - ASCII_LBRACE] = +{ + 0x0000, 0x0000, 0x0000, 0x0000 /* { | } ~ */ +}; + +/* All GPIOs that need to be configured for the STM32L-Discovery LCD */ + +static uint32_t g_slcdgpio[BOARD_SLCD_NGPIOS] = +{ + BOARD_SLCD_COM0, BOARD_SLCD_COM1, BOARD_SLCD_COM2, BOARD_SLCD_COM3, + + BOARD_SLCD_SEG0, BOARD_SLCD_SEG1, BOARD_SLCD_SEG2, BOARD_SLCD_SEG3, + BOARD_SLCD_SEG4, BOARD_SLCD_SEG5, BOARD_SLCD_SEG6, BOARD_SLCD_SEG7, + BOARD_SLCD_SEG8, BOARD_SLCD_SEG9, BOARD_SLCD_SEG10, BOARD_SLCD_SEG11, + BOARD_SLCD_SEG12, BOARD_SLCD_SEG13, BOARD_SLCD_SEG14, BOARD_SLCD_SEG15, + BOARD_SLCD_SEG16, BOARD_SLCD_SEG17, BOARD_SLCD_SEG18, BOARD_SLCD_SEG19, + BOARD_SLCD_SEG20, BOARD_SLCD_SEG21, BOARD_SLCD_SEG22, BOARD_SLCD_SEG23 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: slcd_dumpstate + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpstate(const char *msg) +{ + lcdinfo("%s:\n", msg); + lcdinfo(" curpos: %d\n", + g_slcdstate.curpos); + lcdinfo(" Display: [%c%c%c%c%c%c]\n", + g_slcdstate.buffer[0], g_slcdstate.buffer[1], + g_slcdstate.buffer[2], g_slcdstate.buffer[3], + g_slcdstate.buffer[4], g_slcdstate.buffer[5]); + lcdinfo(" Options: [%d%d%d%d%d%d]\n", + g_slcdstate.options[0], g_slcdstate.options[1], + g_slcdstate.options[2], g_slcdstate.options[3], + g_slcdstate.options[4], g_slcdstate.options[5]); + lcdinfo(" Bar: %02x %02x\n", + g_slcdstate.bar[0], g_slcdstate.bar[1]); +} +#endif + +/**************************************************************************** + * Name: slcd_dumpslcd + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_LCD_INFO +static void slcd_dumpslcd(const char *msg) +{ + lcdinfo("%s:\n", msg); + lcdinfo(" CR: %08x FCR: %08x SR: %08x CLR: %08x\n", + getreg32(STM32_LCD_CR), getreg32(STM32_LCD_FCR), + getreg32(STM32_LCD_SR), getreg32(STM32_LCD_CLR)); + lcdinfo(" RAM0L: %08x RAM1L: %08x RAM2L: %08x RAM3L: %08x\n", + getreg32(STM32_LCD_RAM0L), getreg32(STM32_LCD_RAM1L), + getreg32(STM32_LCD_RAM2L), getreg32(STM32_LCD_RAM3L)); +} +#endif + +/**************************************************************************** + * Name: slcd_clear + ****************************************************************************/ + +static void slcd_clear(void) +{ + uint32_t regaddr; + + linfo("Clearing\n"); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Write all zerios in to the LCD RAM */ + + for (regaddr = STM32_LCD_RAML(0); regaddr <= STM32_LCD_RAMH(7); regaddr++) + { + putreg32(0, regaddr); + } + + /* Set all buffered data to undecorated spaces and home the cursor */ + + memset(g_slcdstate.buffer, ' ', SLCD_NCHARS); + memset(g_slcdstate.options, 0, SLCD_NCHARS); + g_slcdstate.curpos = 0; + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); +} + +/**************************************************************************** + * Name: slcd_getcontrast + ****************************************************************************/ + +static uint8_t slcd_getcontrast(void) +{ + return (getreg32(STM32_LCD_FCR) & LCD_FCR_CC_MASK) >> LCD_FCR_CC_SHIFT; +} + +/**************************************************************************** + * Name: slcd_setcontrast + ****************************************************************************/ + +static int slcd_setcontrast(uint8_t contrast) +{ + uint32_t regval; + int ret = OK; + + /* Make sure that the contrast setting is within range */ + + if (contrast > 7) + { + contrast = 7; + ret = -ERANGE; + } + + regval = getreg32(STM32_LCD_FCR); + regval &= ~LCD_FCR_CC_MASK; + regval |= contrast << LCD_FCR_CC_SHIFT; + putreg32(regval, STM32_LCD_FCR); + + lcdinfo("contrast: %" PRId32 " FCR: %08x\n", + getreg32(STM32_LCD_FCR), contrast); + + return ret; +} + +/**************************************************************************** + * Name: slcd_writebar + ****************************************************************************/ + +static void slcd_writebar(void) +{ + uint32_t regval; + + lcdinfo("bar: %02x %02x\n", g_slcdstate.bar[0], g_slcdstate.bar[1]); + slcd_dumpslcd("BEFORE WRITE"); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Update the BAR */ + + regval = getreg32(STM32_LCD_RAM2L); + regval &= 0xffff5fff; + regval |= (uint32_t)(g_slcdstate.bar[0] << 12); + putreg32(regval, STM32_LCD_RAM2L); + + regval = getreg32(STM32_LCD_RAM3L); + regval &= 0xffff5fff; + regval |= (uint32_t)(g_slcdstate.bar[1] << 12); + putreg32(regval, STM32_LCD_RAM3L); + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); + slcd_dumpslcd("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_mapch + ****************************************************************************/ + +static inline uint16_t slcd_mapch(uint8_t ch) +{ + /* ASCII control characters, the forward delete character, period, colon, + * and all 8-bit ASCII character have already been handled prior to this + * function. + */ + + /* Return spaces all control characters (this should not happen) */ + + if (ch < ASCII_SPACE) + { + return 0x0000; + } + + /* Handle space and the first block of punctuation */ + + if (ch < ASCII_0) + { + return g_slcdpunct1[(int)ch - ASCII_SPACE]; + } + + /* Handle numbers */ + + else if (ch < ASCII_COLON) + { + return g_slcdnummap[(int)ch - ASCII_0]; + } + + /* Handle the next block of punctuation */ + + else if (ch < ASCII_A) + { + return g_slcdpunct2[(int)ch - ASCII_COLON]; + } + + /* Handle upper case letters */ + + else if (ch < ASCII_LBRACKET) + { + return g_slcdalphamap[(int)ch - ASCII_A]; + } + + /* Handle the next block of punctuation */ + + else if (ch < ASCII_a) + { + return g_slcdpunct3[(int)ch - ASCII_LBRACKET]; + } + + /* Handle lower case letters (by mapping them to upper case */ + + else if (ch < ASCII_LBRACE) + { + return g_slcdalphamap[(int)ch - ASCII_a]; + } + + /* Handle the final block of punctuation */ + + else if (ch < ASCII_DEL) + { + return g_slcdpunct4[(int)ch - ASCII_LBRACE]; + } + + /* Ignore 8-bit ASCII and DEL (this should not happen) */ + + return 0x0000; +} + +/**************************************************************************** + * Name: slcd_writemem + ****************************************************************************/ + +static inline void slcd_writemem(uint16_t segset, int curpos) +{ + uint8_t segments[4]; + uint32_t ram0; + uint32_t ram1; + uint32_t ram2; + uint32_t ram3; + int i; + int j; + + lcdinfo("segset: %04x curpos: %d\n", segset, curpos); + slcd_dumpslcd("BEFORE WRITE"); + + /* Isolate the least significant bits + * + * LCD character 16-bit-encoding: + * { E , D , P , N, M , C , COL , DP, B , A , K , J, G , F , Q , H } + * + * segments[0] = { E , D , P , N } + * segments[1] = { M , C , COL , DP } + * segments[2] = { B , A , K , J } + * segments[3] = { G , F , Q , H } + */ + + for (i = 12, j = 0; j < 4; i -= 4, j++) + { + segments[j] = (segset >> i) & 0x0f; + } + + lcdinfo("segments: %02x %02x %02x %02x\n", + segments[0], segments[1], segments[2], segments[3]); + + /* Make sure that any previous transfer is complete. The firmware sets + * the UDR each it modifies the LCD_RAM. The UDR bit stays set until the + * end of the update. During this time the LCD_RAM is write protected. + */ + + while ((getreg32(STM32_LCD_SR) & LCD_SR_UDR) != 0); + + /* Now update the SLCD memory for the character at this cursor position by + * decoding the bit-mapped value + */ + + ram0 = getreg32(STM32_LCD_RAM0L); + ram1 = getreg32(STM32_LCD_RAM1L); + ram2 = getreg32(STM32_LCD_RAM2L); + ram3 = getreg32(STM32_LCD_RAM3L); + + switch (curpos) + { + case 0: + ram0 &= SLCD_CHAR1_MASK0; + ram0 |= SLCD_CHAR1_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR1_MASK1; + ram1 |= SLCD_CHAR1_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR1_MASK2; + ram2 |= SLCD_CHAR1_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR1_MASK3; + ram3 |= SLCD_CHAR1_UPDATE3(segments[3]); + break; + + case 1: + ram0 &= SLCD_CHAR2_MASK0; + ram0 |= SLCD_CHAR2_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR2_MASK1; + ram1 |= SLCD_CHAR2_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR2_MASK2; + ram2 |= SLCD_CHAR2_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR2_MASK3; + ram3 |= SLCD_CHAR2_UPDATE3(segments[3]); + break; + + case 2: + ram0 &= SLCD_CHAR3_MASK0; + ram0 |= SLCD_CHAR3_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR3_MASK1; + ram1 |= SLCD_CHAR3_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR3_MASK2; + ram2 |= SLCD_CHAR3_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR3_MASK3; + ram3 |= SLCD_CHAR3_UPDATE3(segments[3]); + break; + + case 3: + ram0 &= SLCD_CHAR4_MASK0; + ram0 |= SLCD_CHAR4_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR4_MASK1; + ram1 |= SLCD_CHAR4_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR4_MASK2; + ram2 |= SLCD_CHAR4_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR4_MASK3; + ram3 |= SLCD_CHAR4_UPDATE3(segments[3]); + break; + + case 4: + ram0 &= SLCD_CHAR5_MASK0; + ram0 |= SLCD_CHAR5_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR5_MASK1; + ram1 |= SLCD_CHAR5_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR5_MASK2; + ram2 |= SLCD_CHAR5_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR5_MASK3; + ram3 |= SLCD_CHAR5_UPDATE3(segments[3]); + break; + + case 5: + ram0 &= SLCD_CHAR6_MASK0; + ram0 |= SLCD_CHAR6_UPDATE0(segments[0]); + + ram1 &= SLCD_CHAR6_MASK1; + ram1 |= SLCD_CHAR6_UPDATE1(segments[1]); + + ram2 &= SLCD_CHAR6_MASK2; + ram2 |= SLCD_CHAR6_UPDATE2(segments[2]); + + ram3 &= SLCD_CHAR6_MASK3; + ram3 |= SLCD_CHAR6_UPDATE3(segments[3]); + break; + + default: + return; + } + + putreg32(ram0, STM32_LCD_RAM0L); + putreg32(ram1, STM32_LCD_RAM1L); + putreg32(ram2, STM32_LCD_RAM2L); + putreg32(ram3, STM32_LCD_RAM3L); + + /* Set the UDR bit to transfer the updated data to the second level + * buffer. + */ + + putreg32(1, SLCD_SR_UDR_BB); + slcd_dumpslcd("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_writech + ****************************************************************************/ + +static void slcd_writech(uint8_t ch, uint8_t curpos, uint8_t options) +{ + uint16_t segset; + + /* Map the character code to a 16-bit encoded value */ + + segset = slcd_mapch(ch); + + /* Check if the character should be decorated with a decimal point or + * colon + */ + + if ((options & SLCD_DP) != 0) + { + segset |= 0x0002; + } + else if ((options & SLCD_COLON) != 0) + { + segset |= 0x0020; + } + + lcdinfo("ch: [%c] options: %02x segset: %04x\n", ch, options, segset); + + /* Decode the value and write it to the SLCD segment memory */ + + slcd_writemem(segset, curpos); + + /* Save these values in the state structure */ + + g_slcdstate.buffer[curpos] = ch; + g_slcdstate.options[curpos] = options; + + slcd_dumpstate("AFTER WRITE"); +} + +/**************************************************************************** + * Name: slcd_appendch + ****************************************************************************/ + +static void slcd_appendch(uint8_t ch, uint8_t options) +{ + lcdinfo("ch: [%c] options: %02x\n", ch, options); + + /* Write the character at the current cursor position */ + + slcd_writech(ch, g_slcdstate.curpos, options); + if (g_slcdstate.curpos < (SLCD_NCHARS - 1)) + { + g_slcdstate.curpos++; + } + + slcd_dumpstate("AFTER APPEND"); +} + +/**************************************************************************** + * Name: slcd_action + ****************************************************************************/ + +static void slcd_action(enum slcdcode_e code, uint8_t count) +{ + lcdinfo("Action: %d count: %d\n", code, count); + slcd_dumpstate("BEFORE ACTION"); + + switch (code) + { + /* Erasure */ + + case SLCDCODE_BACKDEL: /* Backspace (backward delete) N characters */ + { + int tmp; + + /* If we are at the home position or if the count is zero, then + * ignore the action + */ + + if (g_slcdstate.curpos < 1 || count < 1) + { + break; + } + + /* Otherwise, BACKDEL is like moving the cursor back N characters + * then doing a forward deletion. Decrement the cursor position + * and fall through. + */ + + tmp = (int)g_slcdstate.curpos - count; + if (tmp < 0) + { + tmp = 0; + count = g_slcdstate.curpos; + } + + /* Save the updated cursor positions */ + + g_slcdstate.curpos = tmp; + } + + case SLCDCODE_FWDDEL: /* DELete (forward delete) N characters moving text */ + if (count > 0) + { + int nchars; + int nmove; + int i; + + /* How many characters are to the right of the cursor position + * (including the one at the cursor position)? Then get the + * number of characters to move. + */ + + nchars = SLCD_NCHARS - g_slcdstate.curpos; + nmove = MIN(nchars, count) - 1; + + /* Move all characters after the current cursor position left + * by 'nmove' characters + */ + + for (i = g_slcdstate.curpos + nmove; i < SLCD_NCHARS - 1; i++) + { + slcd_writech(g_slcdstate.buffer[i - nmove], i, + g_slcdstate.options[i - nmove]); + } + + /* Erase the last 'nmove' characters on the display */ + + for (i = SLCD_NCHARS - nmove; i < SLCD_NCHARS; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + case SLCDCODE_ERASE: /* Erase N characters from the cursor position */ + if (count > 0) + { + int last; + int i; + + /* Get the last position to clear and make sure that the last + * position is on the SLCD. + */ + + last = g_slcdstate.curpos + count - 1; + if (last >= SLCD_NCHARS) + { + last = SLCD_NCHARS - 1; + } + + /* Erase N characters after the current cursor position left by + * one + */ + + for (i = g_slcdstate.curpos; i < last; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + case SLCDCODE_CLEAR: /* Home the cursor and erase the entire display */ + { + /* This is like HOME followed by ERASEEOL. Home the cursor and + * fall through. + */ + + g_slcdstate.curpos = 0; + } + + case SLCDCODE_ERASEEOL: /* Erase from the cursor position to the end of line */ + { + int i; + + /* Erase characters after the current cursor position to the end + * of the line + */ + + for (i = g_slcdstate.curpos; i < SLCD_NCHARS; i++) + { + slcd_writech(' ', i, 0); + } + } + break; + + /* Cursor movement */ + + case SLCDCODE_HOME: /* Cursor home */ + { + g_slcdstate.curpos = 0; + } + break; + + case SLCDCODE_END: /* Cursor end */ + { + g_slcdstate.curpos = SLCD_NCHARS - 1; + } + break; + + case SLCDCODE_LEFT: /* Cursor left by N characters */ + { + int tmp = (int)g_slcdstate.curpos - count; + + /* Don't permit movement past the beginning of the SLCD */ + + if (tmp < 0) + { + tmp = 0; + } + + /* Save the new cursor position */ + + g_slcdstate.curpos = (uint8_t)tmp; + } + break; + + case SLCDCODE_RIGHT: /* Cursor right by N characters */ + { + int tmp = (int)g_slcdstate.curpos + count; + + /* Don't permit movement past the end of the SLCD */ + + if (tmp >= SLCD_NCHARS) + { + tmp = SLCD_NCHARS - 1; + } + + /* Save the new cursor position */ + + g_slcdstate.curpos = (uint8_t)tmp; + } + break; + + case SLCDCODE_UP: /* Cursor up by N lines */ + case SLCDCODE_DOWN: /* Cursor down by N lines */ + case SLCDCODE_PAGEUP: /* Cursor up by N pages */ + case SLCDCODE_PAGEDOWN: /* Cursor down by N pages */ + break; /* Not supportable on this SLCD */ + + /* Blinking */ + + case SLCDCODE_BLINKSTART: /* Start blinking with current cursor position */ + case SLCDCODE_BLINKEND: /* End blinking after the current cursor position */ + case SLCDCODE_BLINKOFF: /* Turn blinking off */ + break; /* Not implemented */ + + /* These are actually unreportable errors */ + + default: + case SLCDCODE_NORMAL: /* Not a special keycode */ + break; + } + + slcd_dumpstate("AFTER ACTION"); +} + +/**************************************************************************** + * Name: slcd_read + ****************************************************************************/ + +static ssize_t slcd_read(struct file *filep, char *buffer, + size_t len) +{ + int ret = 0; + int i; + + /* Try to read the entire display. Notice that the seek offset + * (filep->f_pos) is ignored. It probably should be taken into account + * and also updated after each read and write. + */ + + for (i = 0; i < SLCD_NCHARS && ret < len; i++) + { + /* Return the character */ + + *buffer++ = g_slcdstate.buffer[i]; + ret++; + + /* Check if the character is decorated with a following period or + * colon + */ + + if (ret < len && g_slcdstate.buffer[i] != 0) + { + if ((g_slcdstate.buffer[i] & SLCD_DP) != 0) + { + *buffer++ = '.'; + ret++; + } + else if ((g_slcdstate.buffer[i] & SLCD_COLON) != 0) + { + *buffer++ = ':'; + ret++; + } + } + } + + slcd_dumpstate("READ"); + return ret; +} + +/**************************************************************************** + * Name: slcd_write + ****************************************************************************/ + +static ssize_t slcd_write(struct file *filep, + const char *buffer, size_t len) +{ + struct lib_meminstream_s instream; + struct slcdstate_s state; + enum slcdret_e result; + uint8_t ch; + uint8_t count; + uint8_t prev = ' '; + bool valid = false; + + /* Initialize the stream for use with the SLCD CODEC */ + + lib_meminstream(&instream, buffer, len); + + /* Prime the pump. This is messy, but necessary to handle decoration on a + * character based on any following period or colon. + */ + + memset(&state, 0, sizeof(struct slcdstate_s)); + result = slcd_decode(&instream.common, &state, &prev, &count); + + lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", + result, prev, count); + + switch (result) + { + case SLCDRET_CHAR: + valid = true; + break; + + case SLCDRET_SPEC: + { + slcd_action((enum slcdcode_e)prev, count); + prev = ' '; + } + break; + + case SLCDRET_EOF: + return 0; + } + + /* Now decode and process every byte in the input buffer */ + + while ((result = slcd_decode(&instream.common, + &state, &ch, &count)) != SLCDRET_EOF) + { + lcdinfo("slcd_decode returned result=%d char=%d count=%d\n", + result, ch, count); + + if (result == SLCDRET_CHAR) /* A normal character was returned */ + { + /* Check for ASCII control characters */ + + if (ch < ASCII_SPACE) + { + /* All are ignored except for backspace and carriage return */ + + if (ch == ASCII_BS) + { + /* If there is a pending character, then output it now + * before performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the backward deletion */ + + slcd_action(SLCDCODE_BACKDEL, 1); + } + else if (ch == ASCII_CR) + { + /* If there is a pending character, then output it now + * before performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the carriage return */ + + slcd_action(SLCDCODE_HOME, 0); + } + } + + /* Handle characters decoreated with a period or a colon */ + + else if (ch == '.') + { + /* Write the previous character with the decimal point + * appended + */ + + slcd_appendch(prev, SLCD_DP); + prev = ' '; + valid = false; + } + else if (ch == ':') + { + /* Write the previous character with the colon appended */ + + slcd_appendch(prev, SLCD_COLON); + prev = ' '; + valid = false; + } + + /* Handle ASCII_DEL */ + + else if (ch == ASCII_DEL) + { + /* If there is a pending character, then output it now before + * performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the forward deletion */ + + slcd_action(SLCDCODE_FWDDEL, 1); + } + + /* The rest of the 7-bit ASCII characters are fair game */ + + else if (ch < 128) + { + /* Write the previous character if it valid */ + + if (valid) + { + slcd_appendch(prev, 0); + } + + /* There is now a valid output character */ + + prev = ch; + valid = true; + } + } + else /* (result == SLCDRET_SPEC) */ /* A special SLCD action was returned */ + { + /* If there is a pending character, then output it now before + * performing the action. + */ + + if (valid) + { + slcd_appendch(prev, 0); + prev = ' '; + valid = false; + } + + /* Then perform the action */ + + slcd_action((enum slcdcode_e)ch, count); + } + } + + /* Handle any unfinished output */ + + if (valid) + { + slcd_appendch(prev, 0); + } + + /* Assume that the entire input buffer was processed */ + + return (ssize_t)len; +} + +/**************************************************************************** + * Name: slcd_poll + ****************************************************************************/ + +static int slcd_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + switch (cmd) + { + /* SLCDIOC_GETATTRIBUTES: Get the attributes of the SLCD + * + * argument: Pointer to struct slcd_attributes_s in which values + * will be returned + */ + + case SLCDIOC_GETATTRIBUTES: + { + struct slcd_attributes_s *attr = + (struct slcd_attributes_s *)((uintptr_t)arg); + + lcdinfo("SLCDIOC_GETATTRIBUTES:\n"); + + if (!attr) + { + return -EINVAL; + } + + attr->nrows = SLCD_NROWS; + attr->ncolumns = SLCD_NCHARS; + attr->nbars = SLCD_NBARS; + attr->maxcontrast = SLCD_MAXCONTRAST; + attr->maxbrightness = 0; + } + break; + + /* SLCDIOC_CURPOS: Get the SLCD cursor positioni (rows x characters) + * + * argument: Pointer to struct slcd_curpos_s in which values will be + * returned + */ + + case SLCDIOC_CURPOS: + { + struct slcd_curpos_s *curpos = + (struct slcd_curpos_s *)((uintptr_t)arg); + + lcdinfo("SLCDIOC_CURPOS: row=0 column=%d\n", g_slcdstate.curpos); + + if (!curpos) + { + return -EINVAL; + } + + curpos->row = 0; + curpos->column = g_slcdstate.curpos; + } + break; + + /* SLCDIOC_SETBAR: Set bars on a bar display + * + * argument: 32-bit bitset, with each bit corresponding to one bar. + */ + + case SLCDIOC_SETBAR: + { + lcdinfo("SLCDIOC_SETBAR: arg=0x%02lx\n", arg); + + /* Format the bar */ + + g_slcdstate.bar[0] = 0; + g_slcdstate.bar[1] = 0; + + if ((arg & 1) != 0) + { + SLCD_BAR0_ON; + } + + if ((arg & 2) != 0) + { + SLCD_BAR1_ON; + } + + if ((arg & 4) != 0) + { + SLCD_BAR2_ON; + } + + if ((arg & 8) != 0) + { + SLCD_BAR3_ON; + } + + /* Write the bar to SLCD memory */ + + slcd_writebar(); + } + break; + + /* SLCDIOC_GETCONTRAST: Get the current contrast setting + * + * argument: Pointer type int that will receive the current contrast + * setting + */ + + case SLCDIOC_GETCONTRAST: + { + int *contrast = (int *)((uintptr_t)arg); + if (!contrast) + { + return -EINVAL; + } + + *contrast = (int)slcd_getcontrast(); + lcdinfo("SLCDIOC_GETCONTRAST: contrast=%d\n", *contrast); + } + break; + + /* SLCDIOC_SETCONTRAST: Set the contrast to a new value + * + * argument: The new contrast value + */ + + case SLCDIOC_SETCONTRAST: + { + lcdinfo("SLCDIOC_SETCONTRAST: arg=%ld\n", arg); + + if (arg > SLCD_MAXCONTRAST) + { + return -ERANGE; + } + + return slcd_setcontrast((uint8_t)arg); + } + break; + + case SLCDIOC_GETBRIGHTNESS: /* Get the current brightness setting */ + case SLCDIOC_SETBRIGHTNESS: /* Set the brightness to a new value */ + default: + return -ENOTTY; + } + + return OK; +} + +/**************************************************************************** + * Name: slcd_poll + ****************************************************************************/ + +static int slcd_poll(struct file *filep, struct pollfd *fds, + bool setup) +{ + if (setup) + { + /* Data is always available to be read / Data can always be written */ + + poll_notify(&fds, 1, POLLIN | POLLOUT); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_slcd_initialize + * + * Description: + * Initialize the STM32L-Discovery LCD hardware and register the character + * driver as /dev/slcd0. + * + ****************************************************************************/ + +int stm32_slcd_initialize(void) +{ + uint32_t regval; + int ret = OK; + int i; + + /* Only initialize the driver once. */ + + if (!g_slcdstate.initialized) + { + lcdinfo("Initializing\n"); + + /* Configure LCD GPIO pins */ + + for (i = 0; i < BOARD_SLCD_NGPIOS; i++) + { + stm32_configgpio(g_slcdgpio[i]); + } + + /* Enable the External Low-Speed (LSE) oscillator and select it as the + * LCD clock source. + * + * NOTE: LCD clocking should already be enabled in the RCC APB1ENR + * register. + */ + + stm32_rcc_enablelse(); + + lcdinfo("APB1ENR: %08" PRIx32 " CSR: %08" PRIx32 "\n", + getreg32(STM32_RCC_APB1ENR), getreg32(STM32_RCC_CSR)); + + /* Set the LCD prescaler and divider values */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~(LCD_FCR_DIV_MASK | LCD_FCR_PS_MASK); + regval |= (LCD_FCR_PS_DIV1 | LCD_FCR_DIV(31)); + putreg32(regval, STM32_LCD_FCR); + + /* Wait for the FCRSF flag to be set */ + + lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); + + /* Set the duty (1/4), bias (1/3), and the internal voltage source + * (VSEL=0) + */ + + regval = getreg32(STM32_LCD_CR); + regval &= ~(LCD_CR_BIAS_MASK | LCD_CR_DUTY_MASK | LCD_CR_VSEL); + regval |= (LCD_CR_DUTY_1TO4 | LCD_CR_BIAS_1TO3); + putreg32(regval, STM32_LCD_CR); + + /* SEG[31:28] are multiplexed with SEG[43:40] */ + + regval |= LCD_CR_MUX_SEG; + putreg32(regval, STM32_LCD_CR); + + /* Set the contrast to the mean value */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~LCD_FCR_CC_MASK; + regval |= LCD_FCR_CC_VLCD(4); + putreg32(regval, STM32_LCD_FCR); + + /* No dead time */ + + regval &= ~LCD_FCR_DEAD_MASK; + putreg32(regval, STM32_LCD_FCR); + + /* Set the pulse-on duration to 4/ck_ps */ + + regval &= ~LCD_FCR_PON_MASK; + regval |= LCD_FCR_PON(4); + putreg32(regval, STM32_LCD_FCR); + + /* Wait Until the LCD FCR register is synchronized */ + + lcdinfo("Wait for FCRSF, FSR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_FCR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & LCD_SR_FCRSF) == 0); + + /* Enable LCD peripheral */ + + putreg32(1, SLCD_CR_LCDEN_BB); + + /* Wait Until the LCD is enabled and the LCD booster is ready */ + + lcdinfo("Wait for LCD_SR_ENS and LCD_SR_RDY, " + "CR: %08" PRIx32 " SR: %08" PRIx32 "\n", + getreg32(STM32_LCD_CR), getreg32(STM32_LCD_SR)); + + while ((getreg32(STM32_LCD_SR) & (LCD_SR_ENS | LCD_SR_RDY)) != + (LCD_SR_ENS | LCD_SR_RDY)); + + /* Disable blinking */ + + regval = getreg32(STM32_LCD_FCR); + regval &= ~(LCD_FCR_BLINKF_MASK | LCD_FCR_BLINK_MASK); + regval |= (LCD_FCR_BLINK_DISABLE | LCD_FCR_BLINKF_DIV32); + putreg32(regval, STM32_LCD_FCR); + + slcd_dumpslcd("AFTER INITIALIZATION"); + + /* Register the LCD device driver */ + + ret = register_driver("/dev/slcd0", &g_slcdops, 0644, &g_slcdstate); + g_slcdstate.initialized = true; + + /* Then clear the display */ + + slcd_clear(); + slcd_dumpstate("AFTER INITIALIZATION"); + } + + return ret; +} + +#endif /* CONFIG_STM32_LCD */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c new file mode 100644 index 0000000000000..d18d9278bddcd --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32ldiscovery.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The stm32ldiscovery has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM4 CH2. + * This pin is used by FSMC is connected to CN5 just for this purpose: + * + * PD13 FSMC_A18 / MC_TIM4_CH2OUT pin 33 (EnB) + * + * FSMC must be disabled in this case! + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM4_PWM +# undef HAVE_PWM +#endif + +#if CONFIG_STM32_TIM4_CHANNEL != STM32F3DISCOVERY_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F3DISCOVERY_PWMTIMER); + if (!pwm) + { + _err("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c new file mode 100644 index 0000000000000..3066e34f1d6bb --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c @@ -0,0 +1,182 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32ldiscovery + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_MEMS_CS); /* MEMS chip select */ + stm32_configgpio(GPIO_MEMS_INT1); /* MEMS interrupts */ + stm32_configgpio(GPIO_MEMS_INT2); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + stm32_gpiowrite(GPIO_MEMS_CS, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c new file mode 100644 index 0000000000000..5c6555da52100 --- /dev/null +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32ldiscovery.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED1) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED2) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + stm32_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, ledon); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h index a3ef72b726591..7f1afcb12f970 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h + * boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/tools/ci/testlist/arm-08.dat b/tools/ci/testlist/arm-08.dat index dda347b33d86d..b6354c5200c45 100644 --- a/tools/ci/testlist/arm-08.dat +++ b/tools/ci/testlist/arm-08.dat @@ -1,10 +1,25 @@ -/arm/stm32/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI - -/arm/stm32/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG - -/arm/stm32/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG - -/arm/stm32/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32c0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32h7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32u5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32wb/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI + +/arm/stm32f1/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG + +/arm/stm32f2/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG + +/arm/stm32f3/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-09.dat b/tools/ci/testlist/arm-09.dat index cd9c27d5fdb28..82448d0a9ab47 100644 --- a/tools/ci/testlist/arm-09.dat +++ b/tools/ci/testlist/arm-09.dat @@ -1,12 +1,18 @@ -/arm/stm32/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l0/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l4/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l5/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-10.dat b/tools/ci/testlist/arm-10.dat index 1e45e9365cdc2..30d56951ccd7e 100644 --- a/tools/ci/testlist/arm-10.dat +++ b/tools/ci/testlist/arm-10.dat @@ -1,15 +1,15 @@ -/arm/stm32/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG -shenzhou:thttpd -/arm/stm32/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm3240g-eval:knxwm diff --git a/tools/ci/testlist/arm-11.dat b/tools/ci/testlist/arm-11.dat index 6af3cdbfa51ad..2564b8be8e00e 100644 --- a/tools/ci/testlist/arm-11.dat +++ b/tools/ci/testlist/arm-11.dat @@ -1,18 +1,18 @@ -/arm/stm32/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake diff --git a/tools/ci/testlist/arm-12.dat b/tools/ci/testlist/arm-12.dat index caf7755437587..e9e1aa7a42b30 100644 --- a/tools/ci/testlist/arm-12.dat +++ b/tools/ci/testlist/arm-12.dat @@ -1,11 +1,11 @@ -/arm/stm32/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm32f4discovery:winbuild -/arm/stm32/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG # cURL error 60 SSL certificate expired -stm32f4discovery:cxxtest diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 70c05ee29dbcf..6c442b5026a20 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -3,7 +3,7 @@ # ARM -/arm/stm32/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/msys2.dat b/tools/ci/testlist/msys2.dat index 542b59af41900..1996dff9c3c68 100644 --- a/tools/ci/testlist/msys2.dat +++ b/tools/ci/testlist/msys2.dat @@ -3,9 +3,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/windows.dat b/tools/ci/testlist/windows.dat index ec54d4f82bb57..15d7c21b1ae7b 100644 --- a/tools/ci/testlist/windows.dat +++ b/tools/ci/testlist/windows.dat @@ -2,9 +2,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG /arm/rp2040/raspberrypi-pico/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI From cc00c538fd6de49854888dd105bdf8fb142b0c7c Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 09:51:49 +0200 Subject: [PATCH 31/52] boards: fix various stm32 boards errors fix various stm32 boards errors found by CI Signed-off-by: raiden00pl --- boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c | 2 ++ boards/arm/stm32f2/emw3162/src/stm32_wlan.c | 2 +- boards/arm/stm32f2/photon/src/stm32_wlan.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c index b392a99ddf8c2..3150b338e9261 100644 --- a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c @@ -106,6 +106,8 @@ void board_late_initialize(void) { int ret = OK; + UNUSED(ret); + #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c index ff0e8ccaf1de5..4396b94401a04 100644 --- a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c @@ -142,7 +142,7 @@ bool bcmf_board_etheraddr(struct ether_addr *ethaddr) * Name: emw3162_wlan_initialize ****************************************************************************/ -int emw3162_wlan_initialize() +int emw3162_wlan_initialize(void) { int ret; diff --git a/boards/arm/stm32f2/photon/src/stm32_wlan.c b/boards/arm/stm32f2/photon/src/stm32_wlan.c index 88bfa4561e9cf..f1548ca8a858f 100644 --- a/boards/arm/stm32f2/photon/src/stm32_wlan.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan.c @@ -123,7 +123,7 @@ bool bcmf_board_etheraddr(struct ether_addr *ethaddr) * Name: photon_wlan_initialize ****************************************************************************/ -int photon_wlan_initialize() +int photon_wlan_initialize(void) { int ret; From 873226a60017dfaf0fbb347adf8b4b67582286f2 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 09:52:32 +0200 Subject: [PATCH 32/52] ci/arm-13.dat: update targets update arm-13.dat build targets so they match state before stm32 split Signed-off-by: raiden00pl --- tools/ci/testlist/arm-13.dat | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/ci/testlist/arm-13.dat b/tools/ci/testlist/arm-13.dat index ed3b7bb940144..411f2ed1ea230 100644 --- a/tools/ci/testlist/arm-13.dat +++ b/tools/ci/testlist/arm-13.dat @@ -1,6 +1,7 @@ -/arm/stm32f*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f7,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32h*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h5,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h7,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake From 603ff6816d3464589c4eb0f7b2779b7bed45e708 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 26 May 2026 13:34:34 +0200 Subject: [PATCH 33/52] Documentation: add STM32 porting guide add STM32 porting guide Signed-off-by: raiden00pl --- Documentation/guides/index.rst | 1 + Documentation/guides/stm32_ports.rst | 899 +++++++++++++++++++++++++++ 2 files changed, 900 insertions(+) create mode 100644 Documentation/guides/stm32_ports.rst diff --git a/Documentation/guides/index.rst b/Documentation/guides/index.rst index f1e11bc9a456b..acbb2a118b554 100644 --- a/Documentation/guides/index.rst +++ b/Documentation/guides/index.rst @@ -61,4 +61,5 @@ Guides optee.rst qemu_tips.rst lwl.rst + stm32_ports.rst diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst new file mode 100644 index 0000000000000..8121a5c241b3c --- /dev/null +++ b/Documentation/guides/stm32_ports.rst @@ -0,0 +1,899 @@ +=========== +STM32 ports +=========== + +This page records the STM32 families supported by the NuttX ARM port and the +peripheral IP-core selections used by the common STM32 implementation. The +goal of this inventory is to keep shared STM32 code selected by peripheral IP +version, not by family name. + +Family status +============= + +============ ================ =========== =========================== +Family CPU core Status NuttX source directory +============ ================ =========== =========================== +STM32C0 Cortex-M0+ supported ``arch/arm/src/stm32c0`` +STM32C5 Cortex-M33 unsupported none +STM32F0 Cortex-M0 supported ``arch/arm/src/stm32f0`` +STM32F1 Cortex-M3 supported ``arch/arm/src/stm32f1`` +STM32F2 Cortex-M3 supported ``arch/arm/src/stm32f2`` +STM32F3 Cortex-M4 supported ``arch/arm/src/stm32f3`` +STM32F4 Cortex-M4 supported ``arch/arm/src/stm32f4`` +STM32F7 Cortex-M7 supported ``arch/arm/src/stm32f7`` +STM32G0 Cortex-M0+ supported ``arch/arm/src/stm32g0`` +STM32G4 Cortex-M4 supported ``arch/arm/src/stm32g4`` +STM32H5 Cortex-M33 supported ``arch/arm/src/stm32h5`` +STM32H7 Cortex-M7 supported ``arch/arm/src/stm32h7`` +STM32L0 Cortex-M0+ supported ``arch/arm/src/stm32l0`` +STM32L1 Cortex-M3 supported ``arch/arm/src/stm32l1`` +STM32L4 Cortex-M4 supported ``arch/arm/src/stm32l4`` +STM32L5 Cortex-M33 supported ``arch/arm/src/stm32l5`` +STM32MP1 Cortex-A7 unsupported none +STM32MP1 Cortex-M4 unsupported none +STM32MP2 Cortex-A35 unsupported none +STM32MP2 Cortex-M33 unsupported none +STM32N6 Cortex-M55 supported ``arch/arm/src/stm32n6`` +STM32U0 Cortex-M0+ unsupported none +STM32U3 Cortex-M33 unsupported none +STM32U5 Cortex-M33 supported ``arch/arm/src/stm32u5`` +STM32WB Cortex-M4 supported ``arch/arm/src/stm32wb`` +STM32WB Cortex-M0+ unsupported none +STM32WB0 Cortex-M0+ unsupported none +STM32WBA Cortex-M33 unsupported none +STM32WL3 Cortex-M0+ unsupported none +STM32WL5 Cortex-M4 supported ``arch/arm/src/stm32wl5`` +STM32WL5 Cortex-M0+ unsupported none +STM32WLE Cortex-M4 unsupported none +============ ================ =========== =========================== + +Normalized common IP-core selections +==================================== + +Common STM32 code is selected by ``STM32_HAVE_IP_*`` Kconfig symbols. The +selector names describe the common implementation or hardware register layout; +they must not encode a composite family name. A family not listed for an IP +core does not currently select that normalized common IP flag. + +============ ============================================================== +Peripheral Common IP-core selectors +============ ============================================================== +ADC ``STM32_HAVE_IP_ADC_M3M4_V1``, + ``STM32_HAVE_IP_ADC_M3M4_V1_BASIC``, + ``STM32_HAVE_IP_ADC_M3M4_V2``, + ``STM32_HAVE_IP_ADC_M3M4_V2_BASIC``, + ``STM32_HAVE_IP_ADC_M0_V1``, ``STM32_HAVE_IP_SDADC_M3M4_V1`` +AES/CRYP ``STM32_HAVE_IP_AES_M0_V1``, ``STM32_HAVE_IP_AES_M3M4_V1``, + ``STM32_HAVE_IP_CRYPTO_M3M4_V1`` +Backup SRAM ``STM32_HAVE_IP_BBSRAM_M3M4_V1``, + ``STM32_HAVE_IP_BKP_M3M4_V1`` +CAN/FDCAN ``STM32_HAVE_IP_CAN_BXCAN_M0_V1``, + ``STM32_HAVE_IP_CAN_BXCAN_M3M4_V1``, + ``STM32_HAVE_IP_FDCAN_MCAN_M0_V1``, + ``STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1`` +CCM ``STM32_HAVE_IP_CCM_M3M4_V1`` +COMP ``STM32_HAVE_IP_COMP_M0_V1``, ``STM32_HAVE_IP_COMP_M3M4_V1``, + ``STM32_HAVE_IP_COMP_M3M4_V2`` +CORDIC ``STM32_HAVE_IP_CORDIC_M3M4_V1`` +DAC ``STM32_HAVE_IP_DAC_M0_V1``, ``STM32_HAVE_IP_DAC_M3M4_V1``, + ``STM32_HAVE_IP_DAC_M3M4_V2`` +DBGMCU ``STM32_HAVE_IP_DBGMCU_M0_V1``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V1``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V2``, + ``STM32_HAVE_IP_DBGMCU_M3M4_V3`` +DCMI ``STM32_HAVE_IP_DCMI_V1`` +DMA ``STM32_HAVE_IP_DMA_V1``, ``STM32_HAVE_IP_DMA_V1_7CH``, + ``STM32_HAVE_IP_DMA_V1_7CH_DMAMUX``, + ``STM32_HAVE_IP_DMA_V1_8CH``, + ``STM32_HAVE_IP_DMA_V1_8CH_DMAMUX``, ``STM32_HAVE_IP_DMA_V2``, + ``STM32_HAVE_IP_DMA_V2_STREAM`` +DMA2D ``STM32_HAVE_IP_DMA2D_M3M4_V1`` +ETH ``STM32_HAVE_IP_ETHMAC_M3M4_V1`` +EXTI ``STM32_HAVE_IP_EXTI_V1``, ``STM32_HAVE_IP_EXTI_V2`` +FLASH ``STM32_HAVE_IP_FLASH_M0_V1``, + ``STM32_HAVE_IP_FLASH_M3M4_V1``, + ``STM32_HAVE_IP_FLASH_M0_G0C0``, + ``STM32_HAVE_IP_FLASH_M3M4_L1``, + ``STM32_HAVE_IP_FLASH_M3M4_F1F3``, + ``STM32_HAVE_IP_FLASH_M3M4_F2F4``, + ``STM32_HAVE_IP_FLASH_M3M4_G4`` +FMC/FSMC ``STM32_HAVE_IP_FMC_M3M4_V1``, ``STM32_HAVE_IP_FSMC_M3M4_V1`` +GPIO ``STM32_HAVE_IP_GPIO_M0_V1``, ``STM32_HAVE_IP_GPIO_M3M4_V1`` +I2C ``STM32_HAVE_IP_I2C_M0_V1``, ``STM32_HAVE_IP_I2C_M3M4_V1``, + ``STM32_HAVE_IP_I2C_M3M4_V2`` +I2S ``STM32_HAVE_IP_I2S_M3M4_V1`` +LTDC ``STM32_HAVE_IP_LTDC_M3M4_V1`` +OPAMP ``STM32_HAVE_IP_OPAMP_M3M4_V1`` +Power ``STM32_HAVE_IP_PWR_M0_V1``, ``STM32_HAVE_IP_PWR_G0``, + ``STM32_HAVE_IP_PWR_M3M4_V1`` +RNG ``STM32_HAVE_IP_RNG_M0_V1``, ``STM32_HAVE_IP_RNG_M3M4_V1`` +RTC ``STM32_HAVE_IP_RTC_COUNTER_M3M4_V1``, + ``STM32_HAVE_IP_RTCC_M0_V1``, ``STM32_HAVE_IP_RTCC_M3M4_V1``, + ``STM32_HAVE_IP_RTCC_M3M4_L1``, + ``STM32_HAVE_IP_RTCC_M3M4_F4``, ``STM32_HAVE_IP_RTC_M3M4_V1`` +SDIO ``STM32_HAVE_IP_SDIO_M3M4_V1`` +SPI ``STM32_HAVE_IP_SPI_V1``, ``STM32_HAVE_IP_SPI_V2``, + ``STM32_HAVE_IP_SPI_V3``, ``STM32_HAVE_IP_SPI_V4`` +System ``STM32_HAVE_IP_DFUMODE_M3M4_V1``, + ``STM32_HAVE_IP_HSI48_M0_V1``, + ``STM32_HAVE_IP_SYSCFG_M3M4_V1`` +TIM ``STM32_HAVE_IP_TIMERS_M0_V1``, + ``STM32_HAVE_IP_TIMERS_M3M4_V1``, + ``STM32_HAVE_IP_TIMERS_M3M4_V2``, + ``STM32_HAVE_IP_TIMERS_M3M4_V3``, + ``STM32_HAVE_IP_HRTIM_M3M4_V1``, + ``STM32_HAVE_IP_ONESHOT_M3M4_V1``, + ``STM32_HAVE_IP_FREERUN_M3M4_V1`` +USART/LPUART ``STM32_HAVE_IP_USART_V1``, ``STM32_HAVE_IP_USART_V2``, + ``STM32_HAVE_IP_USART_V3``, ``STM32_HAVE_IP_USART_V4`` +USB ``STM32_HAVE_IP_USBDEV_M0_V1``, + ``STM32_HAVE_IP_USBDEV_M3M4_V1``, + ``STM32_HAVE_IP_USBFS_M3M4_V1``, + ``STM32_HAVE_IP_OTGFS_M3M4_V1``, + ``STM32_HAVE_IP_OTGHS_M3M4_V1`` +Watchdog ``STM32_HAVE_IP_WDG_M0_V1``, ``STM32_HAVE_IP_WDG_M3M4_V1`` +============ ============================================================== + +DMA public interfaces are shared by channel and stream DMA; register maps and +request mappings stay split by hardware shape. + +Kconfig option organization +=========================== + +STM32 common Kconfig symbols are split into three layers, each with a fixed +home so contributors always know where a given option belongs: + +================================= ============================ ==================== +Layer Symbol form File +================================= ============================ ==================== +Capability flags (hidden) ``STM32_HAVE_*`` ``Kconfig.have`` +Instance feature flags (hidden) ``STM32__HAVE_*`` ``Kconfig.`` +Peripheral selection ``STM32_`` ``Kconfig.periph`` +Peripheral options ``STM32__*`` ``Kconfig.`` +================================= ============================ ==================== + +All ``STM32_HAVE_*`` and ``STM32_HAVE_IP_*`` symbols are defined in the single +file ``arch/arm/src/common/stm32/Kconfig.have`` — the authoritative description +of what hardware exists. The ``STM32_HAVE_IP_*`` selectors listed above are a +subset of it. The rules for these capability flags are: + +* They are prompt-less ``bool`` symbols, defined exactly once. Never give a + capability flag a prompt. +* Family Kconfig files (``arch/arm/src/stm32/Kconfig``) ``select`` these + symbols to describe the silicon of each chip. +* Presence and feature flags may use ``default y if `` so + the right instances and features light up automatically once a family selects + its IP-core version. +* User-visible options in ``Kconfig.periph`` and ``Kconfig.`` should + ``depends on`` the capability flags rather than on family names. + +The ``STM32_HAVE_`` prefix is reserved for **chip capabilities** — things the +silicon *has*, independent of any single peripheral instance. Those live in +``Kconfig.have``. A flag that instead describes a feature of one **specific +peripheral instance** ("ADC3 *has* a DMA path", "USART1 *supports* RX DMA") is +not a chip capability: it must be named ``STM32__HAVE_`` +(``HAVE`` *after* the instance) and defined in that peripheral's +``Kconfig.`` file, never in ``Kconfig.have``. It is still a prompt-less +``bool`` ``select``-ed by the family Kconfig files, just homed with the rest of +its peripheral's options. For example: + +============================ ============================ ==================== +Wrong (chip-capability form) Correct (instance-feature) Home +============================ ============================ ==================== +``STM32_HAVE_ADC3_DMA`` ``STM32_ADC3_HAVE_DMA`` ``Kconfig.adc`` +``STM32_HAVE_SDADC1_DMA`` ``STM32_SDADC1_HAVE_DMA`` ``Kconfig.sdadc`` +``STM32_HAVE_USART1_RXDMA`` ``STM32_USART1_HAVE_RXDMA`` ``Kconfig.uart`` +``STM32_HAVE_PHY_POLLED`` ``STM32_PHY_HAVE_POLLED`` ``Kconfig.eth`` +============================ ============================ ==================== + +Capability-flag naming: + +* IP-core version selectors: ``STM32_HAVE_IP___V`` (see + `IP-core naming convention`_; the version number resets per core). +* Per-instance presence: ``STM32_HAVE_`` (for example + ``STM32_HAVE_ADC2`` or ``STM32_HAVE_USART3``). +* Feature capability (chip-wide, **no** instance number): ``STM32_HAVE_`` + (for example ``STM32_HAVE_ADC_OVERSAMPLE``). A feature tied to a specific + instance is **not** written this way — see ``STM32__HAVE_`` + above. +* Per-instance feature: ``STM32__HAVE_`` (for example + ``STM32_ADC3_HAVE_DMA``), defined in ``Kconfig.``. + +Family peripheral inventory +=========================== + +Each family table records every peripheral group currently tracked by this +inventory. ``unsupported`` means the peripheral is not available in that +family or is intentionally not implemented by the NuttX family port. +``to be done`` means the peripheral exists or needs confirmation, but the +exact IP core version has not been documented yet. + +STM32C0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES/CRYP v1 unsupported +CAN/FDCAN FDCAN supported +CRC to be done unsupported +DAC v1 unsupported +DBGMCU v1 supported +DMA v1 supported +DMAMUX v1 7ch supported +EXTI v2 supported +FLASH G0/C0 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR G0 supported +RCC to be done supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done unsupported +TIM v1 supported +USART/LPUART v4 supported +USB device unsupported +WWDG v1 supported +============ ============ ============ + +STM32F0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN unsupported +CRC to be done unsupported +DAC v1 unsupported +DMA v1 supported +EXTI v1 supported +FLASH M0 v1 unsupported +GPIO v1 supported +HDMI-CEC to be done unsupported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done supported +TIM v1 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32F1 +------- + +============ ============= ============ +Peripheral Core version NuttX status +============ ============= ============ +ADC v1 basic supported +CAN/FDCAN bxCAN supported +CRC to be done unsupported +DAC v1 supported +DBGMCU v1 supported +DMA v1 supported +ETH to be done supported +EXTI v1 supported +FLASH F1/F3 supported +FSMC v1 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RTC counter supported +SDIO v1 supported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v1 supported +USB device/OTG FS supported +WWDG v1 supported +============ ============= ============ + +STM32F2 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN supported +CRYP v1 supported +DAC v1 supported +DMA v2 supported +ETH to be done supported +EXTI v1 supported +FLASH F2/F4 supported +FSMC v1 supported +GPIO v1 supported +HASH to be done to be done +I2C v1 supported +IWDG v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC v1 supported +SDIO v1 supported +SPI/I2S v2 supported +TIM v1 supported +USART/LPUART v2 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32F3 +------- + +============ ============== ============ +Peripheral Core version NuttX status +============ ============== ============ +ADC v1 basic or v2 supported +CAN/FDCAN bxCAN supported +COMP v1 supported +DAC v1 supported +DBGMCU v2 supported +DMA v1 supported +EXTI v1 supported +FLASH F1/F3 supported +GPIO v1 supported +HRTIM v1 supported +I2C v2 supported +IWDG v1 supported +OPAMP v1 supported +RCC to be done supported +RTC RTCC v1 supported +SDADC v1 supported +SPI/I2S v3 supported +SYSCFG v1 supported +TIM v1 or v2 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============== ============ + +STM32F4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +CAN/FDCAN bxCAN supported +CRYP v1 supported +DAC v1 supported +DMA v2 supported +DMA2D v1 supported +ETH to be done supported +EXTI v1 supported +FLASH F2/F4 supported +FMC/FSMC v1 supported +GPIO v1 supported +HASH to be done to be done +I2C v1 supported +IWDG v1 supported +LTDC v1 supported +QUADSPI to be done supported +RCC to be done supported +RNG v1 supported +RTC RTCC F4 supported +SDIO v1 supported +SPI/I2S v2 supported +TIM v1 supported +USART/LPUART v2 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32G4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v2 supported +AES v1 supported +CAN/FDCAN FDCAN supported +COMP v2 supported +CORDIC v1 supported +DAC v2 supported +DMA v1 supported +DMAMUX v1 8ch supported +EXTI v2 supported +FLASH G4 supported +GPIO v1 supported +HRTIM v1 supported +I2C v2 supported +IWDG v1 supported +OPAMP v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC v1 supported +SPI/I2S v3 supported +TIM v3 supported +USART/LPUART v4 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L4 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +CAN/FDCAN bxCAN supported +COMP to be done supported +DAC to be done supported +DFSDM to be done supported +DMA v1+DMAMUX supported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done supported +IWDG v1 supported +LPTIM to be done supported +PWR to be done supported +QSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SAI to be done supported +SDMMC to be done supported +SPI/I2S to be done supported +TIM to be done supported +USART/LPUART v3 supported +USB OTG FS supported +============ ============ ============ + +STM32F7 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +CAN/FDCAN bxCAN supported +DAC to be done supported +DMA v2 style supported +DMA2D v1 supported +ETH to be done supported +EXTI to be done supported +FLASH to be done supported +FMC/FSMC to be done supported +GPIO to be done supported +I2C to be done supported +IWDG v1 supported +LTDC to be done supported +PWR to be done to be done +QUADSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SDMMC to be done supported +SPI/I2S to be done to be done +TIM to be done supported +USART/LPUART v3 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32G0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 supported +CAN/FDCAN FDCAN unsupported +DAC v1 unsupported +DMA v1 supported +DMAMUX v1 7ch supported +EXTI v2 supported +FLASH G0/C0 unsupported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR G0 unsupported +RCC to be done supported +RNG v1 supported +RTC RTCC M0 unsupported +SPI/I2S v2 supported +SYSCFG to be done supported +TIM v1 supported +USART/LPUART v4 supported +USB device to be done +WWDG v1 supported +============ ============ ============ + +STM32H5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +AES/CRYP to be done unsupported +CAN/FDCAN FDCAN supported +DAC to be done unsupported +DTS to be done supported +ETH to be done supported +EXTI to be done unsupported +FLASH to be done supported +GPIO to be done supported +GPDMA to be done supported +I2C to be done supported +ICACHE to be done supported +OCTOSPI to be done supported +PWR to be done supported +RCC to be done supported +SPI/I2S to be done supported +TIM to be done supported +USART/LPUART v3 supported +USB FS supported +============ ============ ============ + +STM32H7 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +BDMA to be done supported +CAN/FDCAN FDCAN supported +DAC to be done supported +DMA v2 style supported +DMA2D to be done supported +ETH to be done supported +EXTI to be done supported +FLASH to be done supported +FMC/FSMC to be done supported +GPIO to be done supported +HSEM to be done supported +I2C to be done supported +IWDG v1 supported +LTDC to be done supported +MDMA to be done to be done +PWR to be done to be done +QUADSPI to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SDMMC to be done supported +SPI/I2S to be done to be done +TIM to be done supported +USART/LPUART v4 supported +USB OTG FS/HS supported +WWDG v1 supported +============ ============ ============ + +STM32L0 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 supported +CAN/FDCAN to be done unsupported +DAC v1 unsupported +DMA v1 supported +EXTI v1 supported +FLASH M0 v1 unsupported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +PWR v1 supported +RCC to be done supported +RNG v1 supported +RTC RTCC M0 unsupported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v3 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L1 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC v1 supported +AES v1 to be done +CAN/FDCAN bxCAN unsupported +DAC v1 supported +DBGMCU v2 supported +DMA v1 supported +EXTI v1 supported +FLASH L1 supported +FSMC v1 supported +GPIO v1 supported +I2C v1 supported +IWDG v1 supported +LCD to be done to be done +PWR v1 supported +RCC to be done supported +RTC RTCC L1 supported +SDIO v1 supported +SPI/I2S v1 supported +TIM v1 supported +USART/LPUART v2 supported +USB device supported +WWDG v1 supported +============ ============ ============ + +STM32L5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +DAC to be done unsupported +DMA/DMAMUX to be done unsupported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +GTZC to be done unsupported +HASH to be done unsupported +I2C to be done unsupported +OCTOSPI to be done unsupported +PWR to be done supported +RCC to be done supported +RNG to be done unsupported +RTC to be done unsupported +SDMMC to be done unsupported +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB device unsupported +============ ============ ============ + +STM32N6 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +CAN/FDCAN to be done unsupported +DAC to be done unsupported +ETH to be done unsupported +EXTI to be done supported +GPIO to be done supported +GPDMA to be done unsupported +I2C to be done unsupported +PWR to be done supported +RCC to be done supported +SPI/I2S to be done unsupported +TIM to be done supported +USART/LPUART v4 supported +USB device unsupported +XSPI to be done unsupported +============ ============ ============ + +STM32U5 +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done unsupported +CAN/FDCAN FDCAN unsupported +DAC to be done unsupported +DCACHE to be done unsupported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +GPDMA to be done unsupported +HASH to be done unsupported +I2C to be done supported +ICACHE to be done unsupported +OCTOSPI to be done unsupported +PWR to be done supported +RCC to be done supported +RNG to be done unsupported +RTC to be done unsupported +SAES/AES to be done unsupported +SDMMC to be done unsupported +SPI/I2S to be done supported +TAMP to be done unsupported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB device supported +============ ============ ============ + +STM32WB +------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done supported +AES to be done supported +CAN/FDCAN to be done unsupported +DAC to be done unsupported +DMA to be done supported +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done supported +IPCC to be done supported +PWR to be done supported +Radio to be done supported +RCC to be done supported +RNG to be done supported +RTC to be done supported +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v4 supported +USB device supported +============ ============ ============ + +STM32WL/WL5 +----------- + +============ ============ ============ +Peripheral Core version NuttX status +============ ============ ============ +ADC to be done to be done +AES to be done to be done +CAN/FDCAN to be done unsupported +DAC to be done unsupported +DMA to be done to be done +EXTI to be done supported +FLASH to be done supported +GPIO to be done supported +I2C to be done to be done +IPCC to be done supported +PWR to be done supported +Radio to be done to be done +RCC to be done supported +RNG to be done to be done +RTC to be done to be done +SPI/I2S to be done supported +TIM/LPTIM to be done supported +USART/LPUART v3 supported +USB to be done unsupported +============ ============ ============ + +Source naming rules +=================== + +IP-core naming convention +------------------------- + +STM32 common files use a ``_`` naming convention that +encodes the CPU core family and peripheral IP version in filenames and +Kconfig symbols. Version numbers are reset per core: the first version +of a peripheral on a given core is ``V1``. + +**Header file naming** (under ``arch/arm/src/common/stm32/``): + +- Facade headers: ``stm32_.h`` — dispatch on Kconfig IP symbols +- M0-core variants: ``stm32__m0_v1.h`` +- M3/M4-core variants: ``stm32__m3m4_v1.h``, ``stm32__m3m4_v2.h`` +- Combined variants: ``stm32__m3m4_v1v2.h``, ``stm32__m3m4_v1v2v3.h`` + +**Source file naming** (``.c`` files): + +- Follow the same convention as headers: ``stm32_gpio_m3m4_v1v2.c``, + ``stm32_adc_m0_v1.c``, ``stm32_tim_m0_v1.c``, ``stm32_pwm_m3m4_v1v2v3.c`` + +**Kconfig symbol naming** (``CONFIG_STM32_HAVE_IP___``): + +- M0: ``CONFIG_STM32_HAVE_IP_GPIO_M0_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M0_V1`` +- M3/M4: ``CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1``, + ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3`` + +Note that in the future the core prefix may be dropped and a single +version number space used across all cores. For now the core prefix is +kept to make migration of families into common code simpler. + +Common STM32 files should follow these rules: + +* Files shared by more than one family are placed under + ``arch/arm/src/common/stm32``. +* Board-facing public headers use stable peripheral names such as + ``stm32_adc.h``, ``stm32_gpio.h``, and ``stm32_uart.h``. Boards and + drivers should not include IP-versioned public headers directly. +* Public STM32 symbols must use canonical ``stm32_*`` names, not + family-prefixed names (for example, use ``stm32_tim_init``, + ``stm32_dmachannel``, and ``stm32_caninitialize`` rather than + ``stm32l4_*``/``stm32h7_*`` forms). +* Public API-facing type names must also use canonical ``stm32_*`` forms + (for example, ``struct stm32_tim_dev_s``, ``struct stm32_dmaregs_s``, + and ``struct stm32_freerun_s``). +* When an equivalent STM32 API already exists, new family code must reuse + the exact public function name and compatible prototype/type signature. +* Family root aggregation headers should use ``stm32.h`` and family code + should include ```` for that root header include path. +* Hardware register selectors keep the ``hardware/stm32_.h`` + public name and may include hardware-version headers when those headers + describe real register layouts. +* Private common implementation selectors may be split only when the API, + register map, or reusable hardware shape really differs. Prefer capability + names over family names for these splits. +* Common STM32 source and hardware header names must not encode composite + family groups. If a reusable distinction is still named after a family, the + next cleanup step is to map that distinction to an IP-core version or a + hardware feature. +* Public compatibility selectors such as ``stm32_adc.h`` and + ``hardware/stm32_adc.h`` keep their public include names while selecting the + proper common implementation internally. + +Hardware definition naming convention +-------------------------------------- + +All STM32 hardware definitions (IRQ vectors, peripheral counts, SRAM sizes) +must use the standard ``STM32_`` prefix rather than family-specific prefixes. +Family-specific prefixes prevent common code from referencing hardware +definitions across families and create unnecessary differences between ports. + +**IRQ vectors** must use ``STM32_IRQ_`` (not ``STM32L4_IRQ_``, +``STM32WB_IRQ_``, etc.). + +**Peripheral count macros** (``NATIM``, ``NADC``, ``NSPI``, etc.) and SRAM +size macros must use ``STM32_`` prefix (not ``STM32F7_``, ``STM32H5_``, etc.). + +**Per-family hardware register definitions** (in ``arch/arm/src//hardware/``) +must use ``STM32_XXX_`` (not ``STM32L4_XXX_``, ``STM32WB4_XXX_``, etc.). + +Next steps +========== + +The goal is for all STM32 families to follow the rules above, so that shared +code is selected by peripheral IP version instead of family name and code +duplication is limited. The remaining work is: + +Architecture +------------ + +* Migrate the remaining families to use the common ``arch/arm/src/common/stm32`` + code. +* Review every family's selectors so they use the correct IP cores and select + only the peripherals each family actually supports. +* Remove all family-specific options that were left for later, and simplify the + complex Kconfig conditions. +* Unify the remaining peripheral-driver public headers so the API is the same + for all families. +* Better organize the CMake and Make build files for common STM32. Now it's a mess. +* Unify all supported features across families. + +Boards +------ + +* Move all families to shared ``boards/common/stm32`` board code, including + boards that do not yet use the recently added common code. +* Unify all supported features across boards of the same class (such as the + Nucleo boards) so they follow the same patterns. + +Kconfig simplification +---------------------- + +Many Kconfig conditions are still long, mix normalized ``STM32_HAVE_IP_*`` +flags with family names, and rely on composite family-group symbols +(``STM32_COMMON_LEGACY``, ``STM32_COMMON_F7_H7``, ``STM32_COMMON_L4_L5_U5``, +``STM32_COMMON_L4_H5_L5_U5``, …) that the naming rules forbid. These are the +most likely to need rework and should be reduced to depend on capability flags +only: + +* ``Kconfig.tim`` and ``Kconfig.uart`` hold the bulk of the family-name + conditions (hundreds of lines each) and are the biggest cleanup. +* ``Kconfig.adc``, ``Kconfig.periph`` and ``Kconfig.have`` carry many mixed + family/IP ``||`` chains (for example ``(STM32_HAVE_IP_ADC_M3M4_V1 || + STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7``), where F7/H5/L4 are patched + in by family name only because they have no IP flag yet. +* Replace the composite ``STM32_COMMON_*`` family-group symbols with per-IP-core + or per-feature flags. From 44a853e9591f0aa8151eafc261e04fcf375cedba Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 30 May 2026 18:13:45 +0200 Subject: [PATCH 34/52] arch/stm32: Commonize stm32_waste across all STM32 families. Remove the six family-local *_waste.c/.h copies (stm32l4, stm32l5, stm32wb, stm32wl5, stm32u5, stm32f7) and to common implementation. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 12 ++-- arch/arm/src/common/stm32/Make.defs | 5 +- .../{stm32f7 => common/stm32}/stm32_waste.c | 2 +- .../src/common/stm32/stm32_waste_m3m4_v1.c | 44 ------------- arch/arm/src/stm32f7/CMakeLists.txt | 5 +- arch/arm/src/stm32f7/Make.defs | 5 +- arch/arm/src/stm32f7/stm32_waste.h | 66 ------------------- arch/arm/src/stm32l4/CMakeLists.txt | 3 +- arch/arm/src/stm32l4/Make.defs | 5 +- arch/arm/src/stm32l4/stm32l4_flash.c | 2 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 2 +- arch/arm/src/stm32l4/stm32l4_lse.c | 2 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 2 +- arch/arm/src/stm32l4/stm32l4_waste.c | 44 ------------- arch/arm/src/stm32l4/stm32l4_waste.h | 66 ------------------- arch/arm/src/stm32l5/CMakeLists.txt | 3 +- arch/arm/src/stm32l5/Make.defs | 5 +- arch/arm/src/stm32l5/stm32l5_flash.c | 2 +- arch/arm/src/stm32l5/stm32l5_lse.c | 2 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 2 +- arch/arm/src/stm32l5/stm32l5_waste.c | 44 ------------- arch/arm/src/stm32l5/stm32l5_waste.h | 66 ------------------- arch/arm/src/stm32u5/CMakeLists.txt | 3 +- arch/arm/src/stm32u5/Make.defs | 5 +- arch/arm/src/stm32u5/stm32_waste.c | 44 ------------- arch/arm/src/stm32u5/stm32_waste.h | 66 ------------------- arch/arm/src/stm32wb/CMakeLists.txt | 3 +- arch/arm/src/stm32wb/Make.defs | 5 +- arch/arm/src/stm32wb/stm32wb_flash.c | 2 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 2 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 2 +- arch/arm/src/stm32wb/stm32wb_waste.c | 46 ------------- arch/arm/src/stm32wb/stm32wb_waste.h | 66 ------------------- arch/arm/src/stm32wl5/CMakeLists.txt | 3 +- arch/arm/src/stm32wl5/Make.defs | 5 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_lse.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_waste.c | 44 ------------- arch/arm/src/stm32wl5/stm32wl5_waste.h | 65 ------------------ 40 files changed, 57 insertions(+), 699 deletions(-) rename arch/arm/src/{stm32f7 => common/stm32}/stm32_waste.c (97%) delete mode 100644 arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c delete mode 100644 arch/arm/src/stm32f7/stm32_waste.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_waste.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_waste.h delete mode 100644 arch/arm/src/stm32l5/stm32l5_waste.c delete mode 100644 arch/arm/src/stm32l5/stm32l5_waste.h delete mode 100644 arch/arm/src/stm32u5/stm32_waste.c delete mode 100644 arch/arm/src/stm32u5/stm32_waste.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_waste.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_waste.h delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_waste.c delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_waste.h diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index f7b24554c0f19..81e217620151d 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -29,6 +29,10 @@ endif() set(SRCS) +# Architecture-neutral sources used by every STM32 family + +list(APPEND SRCS stm32_waste.c) + if(CONFIG_STM32_COMMON_LEGACY) list( APPEND @@ -38,7 +42,6 @@ if(CONFIG_STM32_COMMON_LEGACY) stm32_lse_m3m4_v1.c stm32_lsi_m3m4_v1.c stm32_irq_m3m4_v1.c - stm32_waste_m3m4_v1.c stm32_capture_m3m4_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) @@ -373,9 +376,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_exti_gpio_m0_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_UID_M0_V1) - list(APPEND SRCS stm32_uid_m0_v1.c) - endif() if(CONFIG_STM32_HAVE_IP_USART_V3) list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) @@ -383,6 +383,10 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) endif() + if(CONFIG_STM32_HAVE_IP_UID_M0_V1) + list(APPEND SRCS stm32_uid_m0_v1.c) + endif() + if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse_m0_v1.c) endif() diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 1e51e18175506..e358dc3ace319 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -37,6 +37,10 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) # the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include # this file too but provide their own implementation. +# Architecture-neutral sources used by every STM32 family + +CHIP_CSRCS += stm32_waste.c + ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c @@ -81,7 +85,6 @@ endif ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c endif -CHIP_CSRCS += stm32_waste_m3m4_v1.c ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) CHIP_CSRCS += stm32_ccm_m3m4_v1.c endif diff --git a/arch/arm/src/stm32f7/stm32_waste.c b/arch/arm/src/common/stm32/stm32_waste.c similarity index 97% rename from arch/arm/src/stm32f7/stm32_waste.c rename to arch/arm/src/common/stm32/stm32_waste.c index 5bbc052d872bd..afe7b82661972 100644 --- a/arch/arm/src/stm32f7/stm32_waste.c +++ b/arch/arm/src/common/stm32/stm32_waste.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/stm32_waste.c + * arch/arm/src/common/stm32/stm32_waste.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c deleted file mode 100644 index b689d1d91b040..0000000000000 --- a/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 76b478bf67fcb..119432b95e2d0 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -34,8 +34,7 @@ list( stm32_serial.c stm32_start.c stm32_capture.c - stm32_uid.c - stm32_waste.c) + stm32_uid.c) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) @@ -195,3 +194,5 @@ if(CONFIG_STM32_FOC) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 7136cf42a7006..05298970a76b0 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M7 files include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32F7 files -CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c +CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c -CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_uid.c stm32_waste.c +CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_uid.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_timerisr.c diff --git a/arch/arm/src/stm32f7/stm32_waste.h b/arch/arm/src/stm32f7/stm32_waste.h deleted file mode 100644 index 62ec787da8a65..0000000000000 --- a/arch/arm/src/stm32f7/stm32_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index f27e4933b240e..672fa1cf49b53 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -33,7 +33,6 @@ list( stm32l4_rcc.c stm32l4_serial.c stm32l4_start.c - stm32l4_waste.c stm32l4_uid.c stm32l4_spi.c stm32l4_i2c.c @@ -197,3 +196,5 @@ if(CONFIG_STM32_1WIREDRIVER) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index d7609705c50fb..05a5f41906477 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32L4 files -CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c +CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c -CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c stm32l4_uid.c +CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_uid.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index 6905cd47afe73..299199b5bb52b 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -46,7 +46,7 @@ #include #include "stm32l4_rcc.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" #include "stm32l4_flash.h" #include "arm_internal.h" diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index a7ad24d641699..235ae86b9ff65 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -268,7 +268,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_rcc.h" #include "stm32l4_i2c.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" /* At least one I2C peripheral must be enabled */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index c273c49d3e832..bd434cf69f307 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -29,7 +29,7 @@ #include "arm_internal.h" #include "stm32l4_pwr.h" #include "stm32l4_rcc.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 26830f433d553..f50e55aa0c793 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -38,7 +38,7 @@ #include "stm32l4_rcc.h" #include "stm32l4_flash.h" #include "stm32.h" -#include "stm32l4_waste.h" +#include "stm32_waste.h" #include "stm32l4_rtc.h" /* Include chip-specific clocking initialization logic */ diff --git a/arch/arm/src/stm32l4/stm32l4_waste.c b/arch/arm/src/stm32l4/stm32l4_waste.c deleted file mode 100644 index 97750308cebde..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32l4_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h deleted file mode 100644 index 0f128b24a8b4c..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a - * measure of badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index 4f10e5e8aa18e..0e2a8694a9218 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -33,7 +33,6 @@ list( stm32l5_rcc.c stm32l5_serial.c stm32l5_start.c - stm32l5_waste.c stm32l5_uid.c stm32l5_spi.c stm32l5_lse.c @@ -66,3 +65,5 @@ if(CONFIG_STM32_STM32L562XX) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index 4c69a8265bc2b..80d2655d84d13 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -28,13 +28,14 @@ HEAD_ASRC = # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv8-m/Make.defs +include common/stm32/Make.defs # Required STM32L5 files CHIP_ASRCS = -CHIP_CSRCS = stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c +CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c -CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_waste.c stm32l5_uid.c +CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_uid.c CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index f4182f8239aa8..78d9e669f16fb 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -46,7 +46,7 @@ #include #include "stm32l5_rcc.h" -#include "stm32l5_waste.h" +#include "stm32_waste.h" #include "stm32l5_flash.h" #include "arm_internal.h" diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index 0a18e77e62733..88a4c676ea101 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "stm32l5_pwr.h" #include "stm32l5_rcc.h" -#include "stm32l5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index b624e1aed3d01..bf74e79a0c4c6 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -38,7 +38,7 @@ #include "stm32l5_rcc.h" #include "stm32l5_flash.h" #include "stm32.h" -#include "stm32l5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l5/stm32l5_waste.c b/arch/arm/src/stm32l5/stm32l5_waste.c deleted file mode 100644 index 3706b18e216db..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32l5_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h deleted file mode 100644 index 55daea18a6641..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of badly - * written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 73e7173695091..1fd0658ffbee7 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -30,7 +30,6 @@ set(SRCS stm32_i2c.c stm32_serial.c stm32_start.c - stm32_waste.c stm32_uid.c stm32_spi.c stm32_lse.c @@ -62,3 +61,5 @@ if(CONFIG_USBDEV) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index 5247b22d5d5e5..de127a904765b 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -28,13 +28,14 @@ HEAD_ASRC = # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv8-m/Make.defs +include common/stm32/Make.defs # Required STM32U5 files CHIP_ASRCS = -CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c +CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c -CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_waste.c stm32_uid.c +CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_uid.c CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c diff --git a/arch/arm/src/stm32u5/stm32_waste.c b/arch/arm/src/stm32u5/stm32_waste.c deleted file mode 100644 index da56c6755eec1..0000000000000 --- a/arch/arm/src/stm32u5/stm32_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32u5/stm32_waste.h b/arch/arm/src/stm32u5/stm32_waste.h deleted file mode 100644 index ab5a5c8a89bc8..0000000000000 --- a/arch/arm/src/stm32u5/stm32_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of badly - * written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index c9646782740b8..a4942012d1cec 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -33,7 +33,6 @@ set(SRCS stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c - stm32wb_waste.c stm32wb_rcc_lse.c stm32wb_rcc_lsi.c stm32wb_pwr.c @@ -117,3 +116,5 @@ if(CONFIG_DEBUG_FEATURES) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 2bf29ecfd1414..304e8bd6b3616 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32WB files -CHIP_CSRCS = stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c +CHIP_CSRCS += stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c -CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c stm32wb_waste.c +CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c CHIP_CSRCS += stm32wb_flash.c stm32wb_uid.c diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 4b1baf8a7ae9c..e3d1b28d1eba3 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -45,7 +45,7 @@ #include "arm_internal.h" #include "stm32wb_rcc.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" #include "stm32wb_flash.h" #if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 50fdb01b3fde5..e2c67abe444af 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -186,7 +186,7 @@ #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" #include "stm32wb_i2c.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" /* At least one I2C peripheral must be enabled */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 8a830216564f3..f5af711a996aa 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -29,7 +29,7 @@ #include "arm_internal.h" #include "stm32wb_pwr.h" #include "stm32wb_rcc.h" -#include "stm32wb_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wb/stm32wb_waste.c b/arch/arm/src/stm32wb/stm32wb_waste.c deleted file mode 100644 index ec2fc9d9c510c..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_waste.c +++ /dev/null @@ -1,46 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "stm32wb_waste.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -uint32_t g_waste_counter; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - g_waste_counter++; -} diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h deleted file mode 100644 index 64e7e6b0943fa..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a - * measure of badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index cfee3e8c42e38..a0fbfdb8ca038 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -31,7 +31,6 @@ set(SRCS stm32wl5_rcc.c stm32wl5_serial.c stm32wl5_start.c - stm32wl5_waste.c stm32wl5_uid.c stm32wl5_lse.c stm32wl5_lsi.c @@ -47,3 +46,5 @@ if(CONFIG_STM32_IPCC) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index e0df51091d07c..05dfb1790b639 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -26,12 +26,13 @@ # Common ARM and Cortex-M4 files (copied from stm32/Make.defs) include armv7-m/Make.defs +include common/stm32/Make.defs # Required STM32WL5 files -CHIP_CSRCS = stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c +CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c -CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c stm32wl5_waste.c stm32wl5_uid.c +CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c stm32wl5_uid.c CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 40737cbe8012c..4c251c982dca4 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -46,7 +46,7 @@ #include #include "stm32wl5_rcc.h" -#include "stm32wl5_waste.h" +#include "stm32_waste.h" #include "stm32wl5_flash.h" #include "arm_internal.h" diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 4ab6997b283c8..50857241ebc3b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -32,7 +32,7 @@ #include "stm32wl5_pwr.h" #include "stm32wl5_rcc.h" -#include "stm32wl5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 37174ffbf6b19..d3e4786f5ee95 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -39,7 +39,7 @@ #include "stm32wl5_rcc.h" #include "stm32wl5_flash.h" #include "stm32.h" -#include "stm32wl5_waste.h" +#include "stm32_waste.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.c b/arch/arm/src/stm32wl5/stm32wl5_waste.c deleted file mode 100644 index 7b2ddbf141ebf..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32_waste.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include "stm32wl5_waste.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -uint32_t idle_wastecounter = 0; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_waste(void) -{ - idle_wastecounter++; -} diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.h b/arch/arm/src/stm32wl5/stm32wl5_waste.h deleted file mode 100644 index 974f59745d9a3..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_waste.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H - -/* Waste CPU Time */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of - * kernel or user-app is polling some register or similar, waiting for - * desired status. This time is wasted away. This function offers a measure - * of badly written piece of software or some undesired behavior. At - * the same time this function adds to some IDLE time which portion cannot - * be used for other purposes (yet). - */ - -void stm32_waste(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_WASTE_H */ From b194d7dd27dd1adcc442b80680bf927d0c3f8290 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 30 May 2026 18:15:27 +0200 Subject: [PATCH 35/52] !arch/stm32: Unify and commonize stm32_uid for all STM32 families. Replace the per-family stm32_get_uniqueid() implementations and the two IP-versioned common variants with a single generic byte-array reader, arch/arm/src/common/stm32/stm32_uid.c. BREAKING CHANGE: stm32_get_uniqueid() now always takes a uint8_t[12] buffer. Out-of-tree Cortex-M0 code that used the previous prototype "void stm32_get_uniqueid(uint32_t *uid)" must change its buffer to "uint8_t uniqueid[12]". Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 27 ++------ arch/arm/src/common/stm32/Kconfig.have | 8 --- arch/arm/src/common/stm32/Make.defs | 7 +- .../src/{stm32f7 => common/stm32}/stm32_uid.c | 7 +- arch/arm/src/common/stm32/stm32_uid.h | 8 +-- arch/arm/src/common/stm32/stm32_uid_m0_v1.c | 47 ------------- .../src/common/stm32/stm32_uid_m3m4_v1v2.c | 62 ----------------- arch/arm/src/stm32c0/Kconfig | 1 - arch/arm/src/stm32f0/Kconfig | 1 - arch/arm/src/stm32f1/Kconfig | 1 - arch/arm/src/stm32f2/Kconfig | 1 - arch/arm/src/stm32f3/Kconfig | 3 - arch/arm/src/stm32f4/Kconfig | 1 - arch/arm/src/stm32f7/CMakeLists.txt | 3 +- arch/arm/src/stm32f7/Make.defs | 2 +- arch/arm/src/stm32f7/stm32_uid.h | 52 --------------- arch/arm/src/stm32g0/Kconfig | 1 - arch/arm/src/stm32g4/Kconfig | 1 - arch/arm/src/stm32h5/CMakeLists.txt | 5 +- arch/arm/src/stm32h5/Make.defs | 2 +- arch/arm/src/stm32h5/stm32_uid.c | 66 ------------------- arch/arm/src/stm32h5/stm32_uid.h | 53 --------------- arch/arm/src/stm32h7/CMakeLists.txt | 5 +- arch/arm/src/stm32h7/Make.defs | 2 +- arch/arm/src/stm32h7/stm32_uid.c | 64 ------------------ arch/arm/src/stm32h7/stm32_uid.h | 53 --------------- arch/arm/src/stm32l0/Kconfig | 1 - arch/arm/src/stm32l1/Kconfig | 1 - arch/arm/src/stm32l4/CMakeLists.txt | 1 - arch/arm/src/stm32l4/Make.defs | 2 +- arch/arm/src/stm32l4/stm32l4_uid.c | 63 ------------------ arch/arm/src/stm32l4/stm32l4_uid.h | 53 --------------- arch/arm/src/stm32l5/CMakeLists.txt | 1 - arch/arm/src/stm32l5/Make.defs | 2 +- arch/arm/src/stm32l5/stm32l5_uid.c | 48 -------------- arch/arm/src/stm32l5/stm32l5_uid.h | 38 ----------- arch/arm/src/stm32u5/CMakeLists.txt | 1 - arch/arm/src/stm32u5/Make.defs | 2 +- arch/arm/src/stm32u5/stm32_uid.c | 48 -------------- arch/arm/src/stm32u5/stm32_uid.h | 38 ----------- arch/arm/src/stm32wb/CMakeLists.txt | 3 +- arch/arm/src/stm32wb/Make.defs | 2 +- arch/arm/src/stm32wb/stm32wb_uid.c | 48 -------------- arch/arm/src/stm32wb/stm32wb_uid.h | 38 ----------- arch/arm/src/stm32wl5/CMakeLists.txt | 1 - arch/arm/src/stm32wl5/Make.defs | 2 +- arch/arm/src/stm32wl5/stm32wl5_uid.c | 63 ------------------ arch/arm/src/stm32wl5/stm32wl5_uid.h | 53 --------------- .../arm/stm32l4/nucleo-l432kc/src/stm32_uid.c | 2 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_uid.c | 2 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_uid.c | 2 +- .../stm32l4/stm32l476-mdk/src/stm32_boot.c | 2 +- .../stm32l476vg-disco/src/stm32_bringup.c | 2 +- .../stm32l4/stm32l476vg-disco/src/stm32_uid.c | 2 +- .../stm32l4r9ai-disco/src/stm32_bringup.c | 2 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_uid.c | 2 +- 56 files changed, 38 insertions(+), 970 deletions(-) rename arch/arm/src/{stm32f7 => common/stm32}/stm32_uid.c (95%) delete mode 100644 arch/arm/src/common/stm32/stm32_uid_m0_v1.c delete mode 100644 arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c delete mode 100644 arch/arm/src/stm32f7/stm32_uid.h delete mode 100644 arch/arm/src/stm32h5/stm32_uid.c delete mode 100644 arch/arm/src/stm32h5/stm32_uid.h delete mode 100644 arch/arm/src/stm32h7/stm32_uid.c delete mode 100644 arch/arm/src/stm32h7/stm32_uid.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_uid.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_uid.h delete mode 100644 arch/arm/src/stm32l5/stm32l5_uid.c delete mode 100644 arch/arm/src/stm32l5/stm32l5_uid.h delete mode 100644 arch/arm/src/stm32u5/stm32_uid.c delete mode 100644 arch/arm/src/stm32u5/stm32_uid.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_uid.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_uid.h delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_uid.c delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_uid.h diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 81e217620151d..427254933245d 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -32,6 +32,7 @@ set(SRCS) # Architecture-neutral sources used by every STM32 family list(APPEND SRCS stm32_waste.c) +list(APPEND SRCS stm32_uid.c) if(CONFIG_STM32_COMMON_LEGACY) list( @@ -75,10 +76,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_ccm_m3m4_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) - list(APPEND SRCS stm32_uid_m3m4_v1v2.c) - endif() - if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) list(APPEND SRCS stm32_dfumode_m3m4_v1.c) endif() @@ -230,9 +227,8 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_STM32_ADC - AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + if(CONFIG_STM32_ADC AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) list(APPEND SRCS stm32_adc_m3m4_v1v2.c) endif() @@ -240,9 +236,8 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdadc_m3m4_v1.c) endif() - if(CONFIG_STM32_DAC - AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + if(CONFIG_STM32_DAC AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) list(APPEND SRCS stm32_dac_m3m4_v1.c) endif() @@ -361,12 +356,7 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() if(CONFIG_ARCH_CORTEXM0) - list( - APPEND - SRCS - stm32_irq_m0_v1.c - stm32_start_m0_v1.c - stm32_lsi_m0_v1.c) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) list(APPEND SRCS stm32_gpio_m0_v1.c) @@ -376,17 +366,12 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_exti_gpio_m0_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_USART_V3) list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) elseif(CONFIG_STM32_HAVE_IP_USART_V4) list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) endif() - if(CONFIG_STM32_HAVE_IP_UID_M0_V1) - list(APPEND SRCS stm32_uid_m0_v1.c) - endif() - if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse_m0_v1.c) endif() diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index 781558cae1d30..b7845fd96f313 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -1070,14 +1070,6 @@ config STM32_HAVE_UART12 config STM32_HAVE_USART1 bool -# UID capabilities - -config STM32_HAVE_IP_UID_M0_V1 - bool - -config STM32_HAVE_IP_UID_M3M4_V1 - bool - # USB capabilities config STM32_HAVE_USBFS_MODE diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index e358dc3ace319..e932e3a46033e 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -40,6 +40,7 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) # Architecture-neutral sources used by every STM32 family CHIP_CSRCS += stm32_waste.c +CHIP_CSRCS += stm32_uid.c ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) @@ -88,9 +89,6 @@ endif ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) CHIP_CSRCS += stm32_ccm_m3m4_v1.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_UID_M3M4_V1),y) -CHIP_CSRCS += stm32_uid_m3m4_v1v2.c -endif CHIP_CSRCS += stm32_capture_m3m4_v1.c ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y) CHIP_CSRCS += stm32_dfumode_m3m4_v1.c @@ -422,9 +420,6 @@ CHIP_CSRCS += stm32_serial_m0_v3.c else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) CHIP_CSRCS += stm32_serial_m0_v4.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_UID_M0_V1),y) -CHIP_CSRCS += stm32_uid_m0_v1.c -endif ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse_m0_v1.c diff --git a/arch/arm/src/stm32f7/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid.c similarity index 95% rename from arch/arm/src/stm32f7/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid.c index e1f64404cd856..190f38b975ff1 100644 --- a/arch/arm/src/stm32f7/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. @@ -40,11 +40,10 @@ #include -#include "hardware/stm32_memorymap.h" - +#include "chip.h" #include "stm32_uid.h" -#ifdef STM32_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /* Not defined for some STM32 parts */ /**************************************************************************** * Public Functions diff --git a/arch/arm/src/common/stm32/stm32_uid.h b/arch/arm/src/common/stm32/stm32_uid.h index e925374353edd..7bf3119bbcbef 100644 --- a/arch/arm/src/common/stm32/stm32_uid.h +++ b/arch/arm/src/common/stm32/stm32_uid.h @@ -35,10 +35,10 @@ * Public Function Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_IP_UID_M0_V1) -void stm32_get_uniqueid(uint32_t *uid); -#elif defined(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) +/* Read the 96-bit STM32 unique device ID into a 12-byte buffer. This + * interface is common to all STM32 families. + */ + void stm32_get_uniqueid(uint8_t uniqueid[12]); -#endif #endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H */ diff --git a/arch/arm/src/common/stm32/stm32_uid_m0_v1.c b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c deleted file mode 100644 index 9f9be6610a7ab..0000000000000 --- a/arch/arm/src/common/stm32/stm32_uid_m0_v1.c +++ /dev/null @@ -1,47 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_uid_m0_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - **************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint32_t *uid) -{ - int i; - - for (i = 0; i < 3; i++) - { - *(uid + i) = *((uint32_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c deleted file mode 100644 index 9986db93d7c39..0000000000000 --- a/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c +++ /dev/null @@ -1,62 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID /* Not defined for the STM32L */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32c0/Kconfig b/arch/arm/src/stm32c0/Kconfig index 9b90ec49a16be..c8f8b5164c77f 100644 --- a/arch/arm/src/stm32c0/Kconfig +++ b/arch/arm/src/stm32c0/Kconfig @@ -249,7 +249,6 @@ config STM32_STM32C0 select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_IP_UID_M0_V1 select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig index 3d54d04029757..d3c7b58ba6341 100644 --- a/arch/arm/src/stm32f0/Kconfig +++ b/arch/arm/src/stm32f0/Kconfig @@ -491,7 +491,6 @@ config STM32_STM32F0 select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_IP_UID_M0_V1 select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 diff --git a/arch/arm/src/stm32f1/Kconfig b/arch/arm/src/stm32f1/Kconfig index a7281777268bc..43349d58bce89 100644 --- a/arch/arm/src/stm32f1/Kconfig +++ b/arch/arm/src/stm32f1/Kconfig @@ -334,7 +334,6 @@ config STM32_STM32F10XX select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig index 2b99327b6dbf0..139cff56f9059 100644 --- a/arch/arm/src/stm32f2/Kconfig +++ b/arch/arm/src/stm32f2/Kconfig @@ -162,7 +162,6 @@ config STM32_STM32F20XX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig index 5fd4db20b0185..ace83673f311d 100644 --- a/arch/arm/src/stm32f3/Kconfig +++ b/arch/arm/src/stm32f3/Kconfig @@ -445,7 +445,6 @@ config STM32_STM32F30XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -535,7 +534,6 @@ config STM32_STM32F33XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -606,7 +604,6 @@ config STM32_STM32F37XX select STM32_HAVE_IP_SDIO_M3M4_V1 select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index c7dc917898e57..698e52b602f85 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -276,7 +276,6 @@ config STM32_STM32F4XXX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 119432b95e2d0..bc870799cdd66 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -33,8 +33,7 @@ list( stm32_rcc.c stm32_serial.c stm32_start.c - stm32_capture.c - stm32_uid.c) + stm32_capture.c) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 05298970a76b0..9a6d59e952187 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -32,7 +32,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c -CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_uid.c +CHIP_CSRCS += stm32_start.c stm32_capture.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_timerisr.c diff --git a/arch/arm/src/stm32f7/stm32_uid.h b/arch/arm/src/stm32f7/stm32_uid.h deleted file mode 100644 index 8e92f0219a7aa..0000000000000 --- a/arch/arm/src/stm32f7/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F7_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UID_H */ diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig index bbee5cd55826b..29f751b93534b 100644 --- a/arch/arm/src/stm32g0/Kconfig +++ b/arch/arm/src/stm32g0/Kconfig @@ -236,7 +236,6 @@ config STM32_STM32G0 select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_IP_UID_M0_V1 select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV select STM32_HAVE_TIM1 select STM32_HAVE_TIM3 diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index 627f83754ce15..b46ea854ddfe0 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -127,7 +127,6 @@ config STM32_STM32G4XXX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V3 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 854b218996875..f413964d7b898 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -41,8 +41,7 @@ list( stm32_pwr.c stm32_timerisr.c stm32_lse.c - stm32_lsi.c - stm32_uid.c) + stm32_lsi.c) if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) @@ -127,3 +126,5 @@ if(CONFIG_STM32_STM32H5XXXX) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index 2b6cb685043ef..ec8db4beccfab 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -28,6 +28,7 @@ HEAD_ASRC = # Common ARM and Cortex-M33 files include armv8-m/Make.defs +include common/stm32/Make.defs ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c @@ -38,7 +39,6 @@ endif CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c CHIP_CSRCS += stm32_lse.c stm32_lsi.c -CHIP_CSRCS += stm32_uid.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c diff --git a/arch/arm/src/stm32h5/stm32_uid.c b/arch/arm/src/stm32h5/stm32_uid.c deleted file mode 100644 index bda001d2760b6..0000000000000 --- a/arch/arm/src/stm32h5/stm32_uid.c +++ /dev/null @@ -1,66 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_uid.c - * - * Copyright (C) 2015 Marawan Ragab. All rights reserved. - * Authors: Marawan Ragab - * David Sidrane - * Modified for STM32H5 by Tyler Bennett - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - uint32_t *uid = (uint32_t *) uniqueid; - - for (i = 0; i < 3; i++) - { - *uid = *((uint32_t *)(STM32_SYSMEM_UID) + i); - uid++; - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32h5/stm32_uid.h b/arch/arm/src/stm32h5/stm32_uid.h deleted file mode 100644 index d63e07e6c9087..0000000000000 --- a/arch/arm/src/stm32h5/stm32_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_uid.h - * - * Copyright (C) 2015 Marawan Ragab. All rights reserved. - * Authors: Marawan Ragab - * David Sidrane - * Modified for STM32H5 by Tyler Bennett - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32H5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_UID_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index b226502c0931c..5f6e1f9800f86 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -32,8 +32,7 @@ list( stm32_start.c stm32_rcc.c stm32_lowputc.c - stm32_serial.c - stm32_uid.c) + stm32_serial.c) if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) @@ -225,3 +224,5 @@ if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) endif() target_sources(arch PRIVATE ${SRCS}) + +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index e8fb7d38e3a13..298f6da5b5c62 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -26,6 +26,7 @@ # Common ARM and Cortex-M7 files include armv7-m/Make.defs +include common/stm32/Make.defs ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c @@ -47,7 +48,6 @@ endif CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c -CHIP_CSRCS += stm32_uid.c ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_tickless.c diff --git a/arch/arm/src/stm32h7/stm32_uid.c b/arch/arm/src/stm32h7/stm32_uid.c deleted file mode 100644 index a69edbe3898d4..0000000000000 --- a/arch/arm/src/stm32h7/stm32_uid.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" - -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32h7/stm32_uid.h b/arch/arm/src/stm32h7/stm32_uid.h deleted file mode 100644 index 4946a910bed97..0000000000000 --- a/arch/arm/src/stm32h7/stm32_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: David Sidrane - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_UID_H -#define __ARCH_ARM_SRC_STM32H7_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_UID_H */ diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig index e98b00f1cefd7..db1311b2b7d14 100644 --- a/arch/arm/src/stm32l0/Kconfig +++ b/arch/arm/src/stm32l0/Kconfig @@ -225,7 +225,6 @@ config STM32_STM32L0 select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_IP_UID_M0_V1 select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG select STM32_HAVE_IP_RTCC_M0_V1 select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig index 5b185142fa864..1fdceba40c2bd 100644 --- a/arch/arm/src/stm32l1/Kconfig +++ b/arch/arm/src/stm32l1/Kconfig @@ -292,7 +292,6 @@ config STM32_STM32L15XX select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_UID_M3M4_V1 select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 672fa1cf49b53..9ea2ec8809a94 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -33,7 +33,6 @@ list( stm32l4_rcc.c stm32l4_serial.c stm32l4_start.c - stm32l4_uid.c stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 05a5f41906477..8149af37b753f 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -32,7 +32,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c -CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_uid.c +CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c deleted file mode 100644 index 20c63b2751a0e..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32l4_memorymap.h" -#include "stm32l4_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h deleted file mode 100644 index 628e62290a946..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_UID_H -#define __ARCH_ARM_SRC_STM32L4_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_UID_H */ diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index 0e2a8694a9218..cfd801d08ab3e 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -33,7 +33,6 @@ list( stm32l5_rcc.c stm32l5_serial.c stm32l5_start.c - stm32l5_uid.c stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index 80d2655d84d13..b01e736c4c8f7 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -35,7 +35,7 @@ include common/stm32/Make.defs CHIP_ASRCS = CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c -CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c stm32l5_uid.c +CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c deleted file mode 100644 index 29f68da29bb4b..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32l5_memorymap.h" -#include "stm32l5_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h deleted file mode 100644 index 782e85bda4af5..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32L5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32L5_STM32_UID_H */ diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 1fd0658ffbee7..70f5a875c1306 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -30,7 +30,6 @@ set(SRCS stm32_i2c.c stm32_serial.c stm32_start.c - stm32_uid.c stm32_spi.c stm32_lse.c stm32_lsi.c diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index de127a904765b..a884bf0cbf33a 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -35,7 +35,7 @@ include common/stm32/Make.defs CHIP_ASRCS = CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c -CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_uid.c +CHIP_CSRCS += stm32_serial.c stm32_start.c CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c deleted file mode 100644 index 479826dafd2a5..0000000000000 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32_memorymap.h" -#include "stm32_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32u5/stm32_uid.h b/arch/arm/src/stm32u5/stm32_uid.h deleted file mode 100644 index f306f2759a98a..0000000000000 --- a/arch/arm/src/stm32u5/stm32_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32U5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_UID_H */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index a4942012d1cec..03f9157eed58e 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -37,8 +37,7 @@ set(SRCS stm32wb_rcc_lsi.c stm32wb_pwr.c stm32wb_tim.c - stm32wb_flash.c - stm32wb_uid.c) + stm32wb_flash.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32wb_idle.c) diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 304e8bd6b3616..5a4bdcdb88e24 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -35,7 +35,7 @@ CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c -CHIP_CSRCS += stm32wb_flash.c stm32wb_uid.c +CHIP_CSRCS += stm32wb_flash.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32wb_idle.c diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c deleted file mode 100644 index e63d65cd6407a..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ /dev/null @@ -1,48 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32_uid.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32wb_memorymap.h" -#include "stm32wb_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h deleted file mode 100644 index 6710825385010..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_uid.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_UID_H -#define __ARCH_ARM_SRC_STM32WB_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_UID_H */ diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index a0fbfdb8ca038..b13a427ce34d6 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -31,7 +31,6 @@ set(SRCS stm32wl5_rcc.c stm32wl5_serial.c stm32wl5_start.c - stm32wl5_uid.c stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index 05dfb1790b639..d61921e8c127b 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -32,7 +32,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c -CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c stm32wl5_uid.c +CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c deleted file mode 100644 index 763fd031ccb7e..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32_uid.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "hardware/stm32wl5_memorymap.h" -#include "stm32wl5_uid.h" - -#ifdef STM32_SYSMEM_UID - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]) -{ - int i; - - for (i = 0; i < 12; i++) - { - uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); - } -} - -#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.h b/arch/arm/src/stm32wl5/stm32wl5_uid.h deleted file mode 100644 index 22d6f4dbcc28f..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * SPDX-FileContributor: dev@ziggurat9.com - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_UID_H -#define __ARCH_ARM_SRC_STM32WL5_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_UID_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c index 848add8c3b7e2..6e55610c9f034 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-l432kc.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c index 15536f8784beb..ee1dedd051040 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-l476rg.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c index 13d47f603d6c3..399675787a61c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "nucleo-144.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c index 9600a50507a94..98d872dd6dd6b 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c @@ -44,7 +44,7 @@ #include "arm_internal.h" #include "stm32.h" -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "stm32l476-mdk.h" /* Conditional logic in stm32l476-mdk.h will determine if certain features diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c index f3137ceb23211..d2dc6b3d08a9d 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c index 60809d9a07f55..6f48da0eaa377 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "stm32l476vg-disco.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index ecbd830baddb5..bc90f98987735 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c index 94a5221d7efce..d0ee15fcd0e0d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c @@ -38,7 +38,7 @@ #include -#include "stm32l4_uid.h" +#include "stm32_uid.h" #include "stm32l4r9ai-disco.h" /**************************************************************************** From 57a04aa30c07a56acfba009fbac6ea7932f1daf7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 10:49:16 +0200 Subject: [PATCH 36/52] arch/arm/stm32f3/stm32f33xxx_pinmap.h: fix compilation fix compilation error Signed-off-by: raiden00pl --- arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h index e5e55225381b2..d26376e3af588 100644 --- a/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h @@ -150,7 +150,7 @@ /* JTAG/SWD */ #define GPIO_JTDI_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) -#define GPIO_JTDO_TRACES_WO_0GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTDO_TRACES_WO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) #define GPIO_NJTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) #define GPIO_SWCLK_JTCK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) #define GPIO_SWDIO_JTMS_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) From 8fb3cf63966f145de04a2b274ac10943a2603db5 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 10:49:16 +0200 Subject: [PATCH 37/52] boards/arm/stm32f4/stm32f401rc-rs485: fix compilation fix compilation error Signed-off-by: raiden00pl --- boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c index 538937c28d15d..f9140a1421b46 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c @@ -66,8 +66,8 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = { - GPIO_ADC\1_IN\2_0, - GPIO_ADC\1_IN\2_0 + GPIO_ADC1_IN0_0, + GPIO_ADC1_IN4_0 }; /**************************************************************************** From 97692437908bc6d390757daf85a0705f96c639e2 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 17:00:47 +0200 Subject: [PATCH 38/52] arch/arm/stm32f7: add stm32.h peripheral header Add arch/arm/src/stm32f7/stm32.h modeled on stm32f4/stm32.h, using the STM32F7 header names. Signed-off-by: raiden00pl --- arch/arm/src/stm32f7/stm32.h | 60 ++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/arm/src/stm32f7/stm32.h diff --git a/arch/arm/src/stm32f7/stm32.h b/arch/arm/src/stm32f7/stm32.h new file mode 100644 index 0000000000000..99c030c63377e --- /dev/null +++ b/arch/arm/src/stm32f7/stm32.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_H +#define __ARCH_ARM_SRC_STM32F7_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_exti.h" +#include "stm32_fmc.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdmmc.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_ethernet.h" + +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_H */ From 18f3f2b6ccfc5ca99bfec373eb64a5c1ed375308 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 17:00:56 +0200 Subject: [PATCH 39/52] boards/arm/stm32f4: drop duplicated STM32_ROMFS, use common board logic stm32f4discovery, nucleo-f446re and omnibusf4 each declared their own STM32_ROMFS Kconfig options and carried a near-identical copy of stm32_romfs_initialize.c. Signed-off-by: raiden00pl --- boards/arm/stm32f4/nucleo-f446re/Kconfig | 22 --- .../stm32f4/nucleo-f446re/src/CMakeLists.txt | 4 - .../arm/stm32f4/nucleo-f446re/src/Make.defs | 4 - .../stm32f4/nucleo-f446re/src/stm32_bringup.c | 4 +- .../stm32f4/nucleo-f446re/src/stm32_romfs.h | 63 ------- .../src/stm32_romfs_initialize.c | 141 ---------------- boards/arm/stm32f4/omnibusf4/Kconfig | 22 --- .../arm/stm32f4/omnibusf4/src/CMakeLists.txt | 4 - boards/arm/stm32f4/omnibusf4/src/Make.defs | 4 - .../arm/stm32f4/omnibusf4/src/stm32_bringup.c | 4 +- .../arm/stm32f4/omnibusf4/src/stm32_romfs.h | 77 --------- .../omnibusf4/src/stm32_romfs_initialize.c | 153 ----------------- boards/arm/stm32f4/stm32f4discovery/Kconfig | 22 --- .../stm32f4discovery/src/CMakeLists.txt | 4 - .../stm32f4/stm32f4discovery/src/Make.defs | 4 - .../stm32f4discovery/src/stm32_bringup.c | 4 +- .../stm32f4discovery/src/stm32_romfs.h | 77 --------- .../src/stm32_romfs_initialize.c | 154 ------------------ 18 files changed, 9 insertions(+), 758 deletions(-) delete mode 100644 boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h delete mode 100644 boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c delete mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h delete mode 100644 boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c delete mode 100644 boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h delete mode 100644 boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c diff --git a/boards/arm/stm32f4/nucleo-f446re/Kconfig b/boards/arm/stm32f4/nucleo-f446re/Kconfig index 1e2e8b8e8b756..1007c8b531564 100644 --- a/boards/arm/stm32f4/nucleo-f446re/Kconfig +++ b/boards/arm/stm32f4/nucleo-f446re/Kconfig @@ -30,26 +30,4 @@ config NUCLEO_F446RE_AJOY_MINBUTTONS minimal set: SELECT (joystick down), FIRE (BUTTON B), and JUMP (BUTTON A). -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - endif # ARCH_BOARD_NUCLEO_F446RE diff --git a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt index 25458b16ff5ca..610cad1a6c0d2 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt @@ -70,10 +70,6 @@ if(CONFIG_BOARD_STM32_IHM08M1) list(APPEND SRCS stm32_foc_ihm08m1.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/f446re.ld") diff --git a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs index f861a66574e08..f4f9c4ec5ce29 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs @@ -72,10 +72,6 @@ ifeq ($(CONFIG_BOARD_STM32_IHM08M1),y) CSRCS += stm32_foc_ihm08m1.c endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c index 94dd44f58397a..13cf8656c7ca4 100644 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c @@ -64,7 +64,9 @@ # include #endif -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #include "nucleo-f446re.h" /**************************************************************************** diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h deleted file mode 100644 index fa4e75ddadddf..0000000000000 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_F446RE_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c deleted file mode 100644 index f1fe6d0806254..0000000000000 --- a/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [&romfs_data_begin .. &romfs_data_begin) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - uintptr_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = (uintptr_t)romfs_data_end - (uintptr_t)romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/omnibusf4/Kconfig b/boards/arm/stm32f4/omnibusf4/Kconfig index ba690b483338e..bb0e7ff53b936 100644 --- a/boards/arm/stm32f4/omnibusf4/Kconfig +++ b/boards/arm/stm32f4/omnibusf4/Kconfig @@ -5,26 +5,4 @@ if ARCH_BOARD_OMNIBUSF4 -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - endif diff --git a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt index 531c7feb5d6f6..e7c271fa8e38b 100644 --- a/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt +++ b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt @@ -62,10 +62,6 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_timer.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() diff --git a/boards/arm/stm32f4/omnibusf4/src/Make.defs b/boards/arm/stm32f4/omnibusf4/src/Make.defs index b0c74f55cdee9..8cea316c75d79 100644 --- a/boards/arm/stm32f4/omnibusf4/src/Make.defs +++ b/boards/arm/stm32f4/omnibusf4/src/Make.defs @@ -63,10 +63,6 @@ ifeq ($(CONFIG_TIMER),y) CSRCS += stm32_timer.c endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c index 59aa712f47fda..a8d3e5d7a4a8e 100644 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c @@ -38,7 +38,9 @@ #endif #include "stm32.h" -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h deleted file mode 100644 index b1376c031e76b..0000000000000 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c deleted file mode 100644 index 8c5d8069a9522..0000000000000 --- a/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,153 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/stm32f4discovery/Kconfig b/boards/arm/stm32f4/stm32f4discovery/Kconfig index 084ab04bc12b9..8dfe3c0fc7940 100644 --- a/boards/arm/stm32f4/stm32f4discovery/Kconfig +++ b/boards/arm/stm32f4/stm32f4discovery/Kconfig @@ -12,28 +12,6 @@ config STM32F4DISBB Select if you are using the STM32F4DIS-BB base board with the STM32F4Discovery. -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../../../rom.img" - config STM32F4DISCO_USBHOST_STACKSIZE int "USB host waiter stack size" default 1024 diff --git a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt index f65fa366811b4..159610236d3fa 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -138,10 +138,6 @@ if(CONFIG_STM32_HCIUART) endif() endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() diff --git a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs index bb7e1b041232a..98f0bd99b475a 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -148,10 +148,6 @@ CSRCS += stm32_hciuart.c endif endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c index a9ea083a7065c..16d4cbc15f25d 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c @@ -39,7 +39,9 @@ #endif #include "stm32.h" -#include "stm32_romfs.h" +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif #ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h deleted file mode 100644 index 7cfb268ae3d6d..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_STM32F4DISCOVERY_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c deleted file mode 100644 index 2814a9eb8e1bd..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,154 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c - * This file provides contents of an optional ROMFS volume, mounted at boot. - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. - * SPDX-FileContributor: Tomasz Wozniak - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - ".section .rodata, \"a\"\n" - ".balign 16\n" - ".globl romfs_data_begin\n" -"romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ - \ - ".balign " STR(ROMFS_SECTOR_SIZE) "\n" - ".globl romfs_data_end\n" -"romfs_data_end:\n"); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ From 3c3ce5a13f25495d340d927ad77b603710259055 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 17:01:08 +0200 Subject: [PATCH 40/52] boards/arm/stm32f7: switch board common to boards/arm/common/stm32 switch stm32f7 board common to boards/arm/common/stm32. Move the STM32F7-only board-common features into the shared directory so they are available to every STM32 family: - bmi270, cs4344, can_setup, cansock_setup, reset, romfs_initialize and spitest - the duplicate stm32_bh1750 is removed (already present in common). Signed-off-by: raiden00pl --- boards/Kconfig | 5 +- boards/arm/common/stm32/Kconfig | 176 +++++++++++++++++ .../stm32}/include/stm32_bmi270.h | 8 +- .../stm32}/include/stm32_can_setup.h | 8 +- .../stm32}/include/stm32_cansock_setup.h | 8 +- .../stm32}/include/stm32_cs4344.h | 8 +- .../stm32}/include/stm32_romfs.h | 8 +- .../stm32}/include/stm32_spitest.h | 8 +- boards/arm/common/stm32/src/CMakeLists.txt | 29 +++ boards/arm/common/stm32/src/Make.defs | 29 +++ .../stm32}/src/stm32_bmi270.c | 2 +- .../stm32}/src/stm32_can_setup.c | 2 +- .../stm32}/src/stm32_cansock_setup.c | 2 +- .../stm32}/src/stm32_cs4344.c | 2 +- .../common => common/stm32}/src/stm32_reset.c | 2 +- .../stm32}/src/stm32_romfs_initialize.c | 2 +- .../stm32}/src/stm32_spitest.c | 2 +- boards/arm/stm32f7/common/CMakeLists.txt | 3 +- boards/arm/stm32f7/common/Kconfig | 180 ------------------ boards/arm/stm32f7/common/Makefile | 5 +- .../arm/stm32f7/common/include/stm32_bh1750.h | 82 -------- boards/arm/stm32f7/common/src/CMakeLists.txt | 58 ------ boards/arm/stm32f7/common/src/Make.defs | 62 ------ boards/arm/stm32f7/common/src/stm32_bh1750.c | 89 --------- 24 files changed, 270 insertions(+), 510 deletions(-) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_bmi270.h (92%) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_can_setup.h (91%) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_cansock_setup.h (90%) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_cs4344.h (92%) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_romfs.h (93%) rename boards/arm/{stm32f7/common => common/stm32}/include/stm32_spitest.h (91%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_bmi270.c (98%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_can_setup.c (98%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_cansock_setup.c (97%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_cs4344.c (99%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_reset.c (98%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_romfs_initialize.c (98%) rename boards/arm/{stm32f7/common => common/stm32}/src/stm32_spitest.c (99%) delete mode 100644 boards/arm/stm32f7/common/Kconfig delete mode 100644 boards/arm/stm32f7/common/include/stm32_bh1750.h delete mode 100644 boards/arm/stm32f7/common/src/CMakeLists.txt delete mode 100644 boards/arm/stm32f7/common/src/Make.defs delete mode 100644 boards/arm/stm32f7/common/src/stm32_bh1750.c diff --git a/boards/Kconfig b/boards/Kconfig index ba2cb60b87f05..69b09c9382ab2 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5206,10 +5206,7 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32F7 -source "boards/arm/stm32f7/common/Kconfig" -endif -if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 diff --git a/boards/arm/common/stm32/Kconfig b/boards/arm/common/stm32/Kconfig index 3e611724880f7..1c025f51839dc 100644 --- a/boards/arm/common/stm32/Kconfig +++ b/boards/arm/common/stm32/Kconfig @@ -69,3 +69,179 @@ config BOARD_STM32_HALL3PHASE_SAMPLES default 10 endif # SENSORS_HALL3PHASE + +config STM32_ROMFS + bool "Automount baked-in ROMFS image" + default n + depends on FS_ROMFS + ---help--- + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT + +config STM32_ROMFS_DEV_MINOR + int "Minor for the block device backing the data" + depends on STM32_ROMFS + default 64 + +config STM32_ROMFS_MOUNTPOINT + string "Mountpoint of the custom romfs image" + depends on STM32_ROMFS + default "/rom" + +config STM32_ROMFS_IMAGEFILE + string "ROMFS image file to include into build" + depends on STM32_ROMFS + default "../../../rom.img" + +config STM32_SPI_TEST + bool "Enable SPI test" + default n + ---help--- + Enable Spi test - initialize and configure SPI to send + STM32_SPI_TEST_MESSAGE text. The text is sent on the + selected SPI Buses with the configured parameters. + Note the CS lines will not be asserted. + +if STM32_SPI_TEST + +config STM32_SPI_TEST_MESSAGE + string "Text to Send on SPI Bus(es)" + default "Hello World" + depends on STM32_SPI_TEST + ---help--- + Text to sent on SPI bus(es) + +config STM32_SPI1_TEST + bool "Test SPI bus 1" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 1 + +if STM32_SPI1_TEST + +config STM32_SPI1_TEST_FREQ + int "SPI 1 Clock Freq in Hz" + default 1000000 + depends on STM32_SPI1_TEST + ---help--- + Sets SPI 1 Clock Freq + +config STM32_SPI1_TEST_BITS + int "SPI 1 number of bits" + default 8 + depends on STM32_SPI1_TEST + ---help--- + Sets SPI 1 bit length + +choice + prompt "SPI BUS 1 Clock Mode" + default STM32_SPI1_TEST_MODE3 + ---help--- + Sets SPI 1 clock mode + +config STM32_SPI1_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI1_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI1_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI1_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 1 Clock Mode" + +endif # STM32_SPI1_TEST + +config STM32_SPI2_TEST + bool "Test SPI bus 2" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 2 + +if STM32_SPI2_TEST + +config STM32_SPI2_TEST_FREQ + int "SPI 2 Clock Freq in Hz" + default 12000000 + depends on STM32_SPI2_TEST + ---help--- + Sets SPI 2 Clock Freq + +config STM32_SPI2_TEST_BITS + int "SPI 2 number of bits" + default 8 + depends on STM32_SPI2_TEST + ---help--- + Sets SPI 2 bit length + +choice + prompt "SPI BUS 2 Clock Mode" + default STM32_SPI2_TEST_MODE3 + ---help--- + Sets SPI 2 clock mode + +config STM32_SPI2_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI2_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI2_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI2_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 2 Clock Mode" + +endif # STM32_SPI2_TEST + +config STM32_SPI3_TEST + bool "Test SPI bus 3" + default n + depends on STM32_SPI_TEST + ---help--- + Enable Spi test - on SPI BUS 3 + +if STM32_SPI3_TEST + +config STM32_SPI3_TEST_FREQ + int "SPI 3 Clock Freq in Hz" + default 40000000 + depends on STM32_SPI3_TEST + ---help--- + Sets SPI 3 Clock Freq + +config STM32_SPI3_TEST_BITS + int "SPI 3 number of bits" + default 8 + depends on STM32_SPI3_TEST + ---help--- + Sets SPI 3 bit length + +choice + prompt "SPI BUS 3 Clock Mode" + default STM32_SPI3_TEST_MODE3 + ---help--- + Sets SPI 3 clock mode + +config STM32_SPI3_TEST_MODE0 + bool "CPOL=0 CPHA=0" + +config STM32_SPI3_TEST_MODE1 + bool "CPOL=0 CPHA=1" + +config STM32_SPI3_TEST_MODE2 + bool "CPOL=1 CPHA=0" + +config STM32_SPI3_TEST_MODE3 + bool "CPOL=1 CPHA=1" + +endchoice # "SPI BUS 3 Clock Mode" + +endif # STM32_SPI3_TEST +endif # STM32_SPI_TEST diff --git a/boards/arm/stm32f7/common/include/stm32_bmi270.h b/boards/arm/common/stm32/include/stm32_bmi270.h similarity index 92% rename from boards/arm/stm32f7/common/include/stm32_bmi270.h rename to boards/arm/common/stm32/include/stm32_bmi270.h index 6873857d8729f..8b3d23c9a06ea 100644 --- a/boards/arm/stm32f7/common/include/stm32_bmi270.h +++ b/boards/arm/common/stm32/include/stm32_bmi270.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_bmi270.h + * boards/arm/common/stm32/include/stm32_bmi270.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bmi270_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMI270_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMI270_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_can_setup.h b/boards/arm/common/stm32/include/stm32_can_setup.h similarity index 91% rename from boards/arm/stm32f7/common/include/stm32_can_setup.h rename to boards/arm/common/stm32/include/stm32_can_setup.h index 1f43512e3e0a0..9cd211d05b98b 100644 --- a/boards/arm/stm32f7/common/include/stm32_can_setup.h +++ b/boards/arm/common/stm32/include/stm32_can_setup.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_can_setup.h + * boards/arm/common/stm32/include/stm32_can_setup.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H /**************************************************************************** * Included Files @@ -70,4 +70,4 @@ int stm32_can_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CAN_SETUP_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CAN_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h b/boards/arm/common/stm32/include/stm32_cansock_setup.h similarity index 90% rename from boards/arm/stm32f7/common/include/stm32_cansock_setup.h rename to boards/arm/common/stm32/include/stm32_cansock_setup.h index c902ac7ea45b7..77a41b66574fa 100644 --- a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h +++ b/boards/arm/common/stm32/include/stm32_cansock_setup.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_cansock_setup.h + * boards/arm/common/stm32/include/stm32_cansock_setup.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H /**************************************************************************** * Included Files @@ -70,4 +70,4 @@ int stm32_cansock_setup(void); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CANSOCK_SETUP_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CANSOCK_SETUP_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_cs4344.h b/boards/arm/common/stm32/include/stm32_cs4344.h similarity index 92% rename from boards/arm/stm32f7/common/include/stm32_cs4344.h rename to boards/arm/common/stm32/include/stm32_cs4344.h index aab46ba3c5103..eb84188d0380e 100644 --- a/boards/arm/stm32f7/common/include/stm32_cs4344.h +++ b/boards/arm/common/stm32/include/stm32_cs4344.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_cs4344.h + * boards/arm/common/stm32/include/stm32_cs4344.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H /**************************************************************************** * Included Files @@ -81,4 +81,4 @@ int board_cs4344_initialize(int devno, int port); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_CS4344_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_CS4344_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_romfs.h b/boards/arm/common/stm32/include/stm32_romfs.h similarity index 93% rename from boards/arm/stm32f7/common/include/stm32_romfs.h rename to boards/arm/common/stm32/include/stm32_romfs.h index d07d56ef2b3e6..cbb982ebb5cf1 100644 --- a/boards/arm/stm32f7/common/include/stm32_romfs.h +++ b/boards/arm/common/stm32/include/stm32_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_romfs.h + * boards/arm/common/stm32/include/stm32_romfs.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H /**************************************************************************** * Included Files @@ -74,4 +74,4 @@ int stm32_romfs_initialize(void); #endif /* CONFIG_STM32_ROMFS */ -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ROMFS_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/common/stm32/include/stm32_spitest.h similarity index 91% rename from boards/arm/stm32f7/common/include/stm32_spitest.h rename to boards/arm/common/stm32/include/stm32_spitest.h index 326c2cc04d0f8..29efe4880af6a 100644 --- a/boards/arm/stm32f7/common/include/stm32_spitest.h +++ b/boards/arm/common/stm32/include/stm32_spitest.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_spitest.h + * boards/arm/common/stm32/include/stm32_spitest.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H /**************************************************************************** * Included Files @@ -73,4 +73,4 @@ int stm32_spidev_bus_test(void); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SPITEST_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SPITEST_H */ diff --git a/boards/arm/common/stm32/src/CMakeLists.txt b/boards/arm/common/stm32/src/CMakeLists.txt index 1f9b383736821..7f55789437062 100644 --- a/boards/arm/common/stm32/src/CMakeLists.txt +++ b/boards/arm/common/stm32/src/CMakeLists.txt @@ -180,4 +180,33 @@ if(CONFIG_INPUT_MPR121_KEYPAD) list(APPEND SRCS stm32_mpr121.c) endif() +if(CONFIG_SENSORS_BMI270_I2C) + list(APPEND SRCS stm32_bmi270.c) +endif() + +if(CONFIG_AUDIO_CS4344) + list(APPEND SRCS stm32_cs4344.c) +endif() + +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_setup.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_cansock_setup.c) + endif() +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +if(CONFIG_STM32_ROMFS) + list(APPEND SRCS stm32_romfs_initialize.c) +endif() + +if(CONFIG_STM32_SPI_TEST) + list(APPEND SRCS stm32_spitest.c) +endif() + target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/common/stm32/src/Make.defs b/boards/arm/common/stm32/src/Make.defs index 9470fe63aac34..95482c114898f 100644 --- a/boards/arm/common/stm32/src/Make.defs +++ b/boards/arm/common/stm32/src/Make.defs @@ -192,6 +192,35 @@ ifeq ($(CONFIG_INPUT_KMATRIX_I2C),y) CSRCS += stm32_kmatrix_i2c.c endif +ifeq ($(CONFIG_SENSORS_BMI270_I2C),y) + CSRCS += stm32_bmi270.c +endif + +ifeq ($(CONFIG_AUDIO_CS4344),y) + CSRCS += stm32_cs4344.c +endif + +ifeq ($(CONFIG_STM32_CAN),y) + ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) + CSRCS += stm32_can_setup.c + endif + ifeq ($(CONFIG_STM32_CAN_SOCKET),y) + CSRCS += stm32_cansock_setup.c + endif +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += stm32_reset.c +endif + +ifeq ($(CONFIG_STM32_ROMFS),y) + CSRCS += stm32_romfs_initialize.c +endif + +ifeq ($(CONFIG_STM32_SPI_TEST),y) + CSRCS += stm32_spitest.c +endif + DEPPATH += --dep-path $(STM32_BOARD_COMMON_DIR)$(DELIM)src VPATH += :$(STM32_BOARD_COMMON_DIR)$(DELIM)src CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)include diff --git a/boards/arm/stm32f7/common/src/stm32_bmi270.c b/boards/arm/common/stm32/src/stm32_bmi270.c similarity index 98% rename from boards/arm/stm32f7/common/src/stm32_bmi270.c rename to boards/arm/common/stm32/src/stm32_bmi270.c index 8ebe848cb39c1..8c0ac8fcdc03d 100644 --- a/boards/arm/stm32f7/common/src/stm32_bmi270.c +++ b/boards/arm/common/stm32/src/stm32_bmi270.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_bmi270.c + * boards/arm/common/stm32/src/stm32_bmi270.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_can_setup.c b/boards/arm/common/stm32/src/stm32_can_setup.c similarity index 98% rename from boards/arm/stm32f7/common/src/stm32_can_setup.c rename to boards/arm/common/stm32/src/stm32_can_setup.c index 2eedf06992ea8..bad1ffbc2d6fd 100644 --- a/boards/arm/stm32f7/common/src/stm32_can_setup.c +++ b/boards/arm/common/stm32/src/stm32_can_setup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_can_setup.c + * boards/arm/common/stm32/src/stm32_can_setup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/common/stm32/src/stm32_cansock_setup.c similarity index 97% rename from boards/arm/stm32f7/common/src/stm32_cansock_setup.c rename to boards/arm/common/stm32/src/stm32_cansock_setup.c index 58dbf738cfe70..aad7a7df26de5 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/common/stm32/src/stm32_cansock_setup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_cansock_setup.c + * boards/arm/common/stm32/src/stm32_cansock_setup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_cs4344.c b/boards/arm/common/stm32/src/stm32_cs4344.c similarity index 99% rename from boards/arm/stm32f7/common/src/stm32_cs4344.c rename to boards/arm/common/stm32/src/stm32_cs4344.c index 88debb7a9c585..64f8ee946a881 100644 --- a/boards/arm/stm32f7/common/src/stm32_cs4344.c +++ b/boards/arm/common/stm32/src/stm32_cs4344.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_cs4344.c + * boards/arm/common/stm32/src/stm32_cs4344.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_reset.c b/boards/arm/common/stm32/src/stm32_reset.c similarity index 98% rename from boards/arm/stm32f7/common/src/stm32_reset.c rename to boards/arm/common/stm32/src/stm32_reset.c index 1eaa28fe9c7cd..ea664e886151f 100644 --- a/boards/arm/stm32f7/common/src/stm32_reset.c +++ b/boards/arm/common/stm32/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_reset.c + * boards/arm/common/stm32/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c b/boards/arm/common/stm32/src/stm32_romfs_initialize.c similarity index 98% rename from boards/arm/stm32f7/common/src/stm32_romfs_initialize.c rename to boards/arm/common/stm32/src/stm32_romfs_initialize.c index 1d105e29b0e09..37690d7c9c769 100644 --- a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c +++ b/boards/arm/common/stm32/src/stm32_romfs_initialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_romfs_initialize.c + * boards/arm/common/stm32/src/stm32_romfs_initialize.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Tomasz Wozniak. All rights reserved. diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/common/stm32/src/stm32_spitest.c similarity index 99% rename from boards/arm/stm32f7/common/src/stm32_spitest.c rename to boards/arm/common/stm32/src/stm32_spitest.c index ccdffbcbc11b3..f5c628d00a5b0 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/common/stm32/src/stm32_spitest.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_spitest.c + * boards/arm/common/stm32/src/stm32_spitest.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f7/common/CMakeLists.txt b/boards/arm/stm32f7/common/CMakeLists.txt index 91bb41fe7fe51..4f86eab35f4d4 100644 --- a/boards/arm/stm32f7/common/CMakeLists.txt +++ b/boards/arm/stm32f7/common/CMakeLists.txt @@ -20,5 +20,4 @@ # # ############################################################################## -add_subdirectory(src) -target_include_directories(board PRIVATE include) +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig deleted file mode 100644 index 8be75fe61735a..0000000000000 --- a/boards/arm/stm32f7/common/Kconfig +++ /dev/null @@ -1,180 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -config STM32_ROMFS - bool "Automount baked-in ROMFS image" - default n - depends on FS_ROMFS - ---help--- - Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT - -config STM32_ROMFS_DEV_MINOR - int "Minor for the block device backing the data" - depends on STM32_ROMFS - default 64 - -config STM32_ROMFS_MOUNTPOINT - string "Mountpoint of the custom romfs image" - depends on STM32_ROMFS - default "/rom" - -config STM32_ROMFS_IMAGEFILE - string "ROMFS image file to include into build" - depends on STM32_ROMFS - default "../../../rom.img" - -config STM32_SPI_TEST - bool "Enable SPI test" - default n - ---help--- - Enable Spi test - initialize and configure SPI to send - STM32_SPI_TEST_MESSAGE text. The text is sent on the - selected SPI Buses with the configured parameters. - Note the CS lines will not be asserted. - -if STM32_SPI_TEST - -config STM32_SPI_TEST_MESSAGE - string "Text to Send on SPI Bus(es)" - default "Hello World" - depends on STM32_SPI_TEST - ---help--- - Text to sent on SPI bus(es) - -config STM32_SPI1_TEST - bool "Test SPI bus 1" - default n - depends on STM32_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 1 - -if STM32_SPI1_TEST - -config STM32_SPI1_TEST_FREQ - int "SPI 1 Clock Freq in Hz" - default 1000000 - depends on STM32_SPI1_TEST - ---help--- - Sets SPI 1 Clock Freq - -config STM32_SPI1_TEST_BITS - int "SPI 1 number of bits" - default 8 - depends on STM32_SPI1_TEST - ---help--- - Sets SPI 1 bit length - -choice - prompt "SPI BUS 1 Clock Mode" - default STM32_SPI1_TEST_MODE3 - ---help--- - Sets SPI 1 clock mode - -config STM32_SPI1_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32_SPI1_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32_SPI1_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32_SPI1_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 1 Clock Mode" - -endif # STM32_SPI1_TEST - -config STM32_SPI2_TEST - bool "Test SPI bus 2" - default n - depends on STM32_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 2 - -if STM32_SPI2_TEST - -config STM32_SPI2_TEST_FREQ - int "SPI 2 Clock Freq in Hz" - default 12000000 - depends on STM32_SPI2_TEST - ---help--- - Sets SPI 2 Clock Freq - -config STM32_SPI2_TEST_BITS - int "SPI 2 number of bits" - default 8 - depends on STM32_SPI2_TEST - ---help--- - Sets SPI 2 bit length - -choice - prompt "SPI BUS 2 Clock Mode" - default STM32_SPI2_TEST_MODE3 - ---help--- - Sets SPI 2 clock mode - -config STM32_SPI2_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32_SPI2_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32_SPI2_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32_SPI2_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 2 Clock Mode" - -endif # STM32_SPI2_TEST - -config STM32_SPI3_TEST - bool "Test SPI bus 3" - default n - depends on STM32_SPI_TEST - ---help--- - Enable Spi test - on SPI BUS 3 - -if STM32_SPI3_TEST - -config STM32_SPI3_TEST_FREQ - int "SPI 3 Clock Freq in Hz" - default 40000000 - depends on STM32_SPI3_TEST - ---help--- - Sets SPI 3 Clock Freq - -config STM32_SPI3_TEST_BITS - int "SPI 3 number of bits" - default 8 - depends on STM32_SPI3_TEST - ---help--- - Sets SPI 3 bit length - -choice - prompt "SPI BUS 3 Clock Mode" - default STM32_SPI3_TEST_MODE3 - ---help--- - Sets SPI 3 clock mode - -config STM32_SPI3_TEST_MODE0 - bool "CPOL=0 CPHA=0" - -config STM32_SPI3_TEST_MODE1 - bool "CPOL=0 CPHA=1" - -config STM32_SPI3_TEST_MODE2 - bool "CPOL=1 CPHA=0" - -config STM32_SPI3_TEST_MODE3 - bool "CPOL=1 CPHA=1" - -endchoice # "SPI BUS 3 Clock Mode" - -endif # STM32_SPI3_TEST -endif # STM32_SPI_TEST diff --git a/boards/arm/stm32f7/common/Makefile b/boards/arm/stm32f7/common/Makefile index 7e0b3fe6cf5d5..ab1a17894f5d6 100644 --- a/boards/arm/stm32f7/common/Makefile +++ b/boards/arm/stm32f7/common/Makefile @@ -22,11 +22,12 @@ include $(TOPDIR)/Make.defs +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + include board/Make.defs -include src/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs DEPPATH += --dep-path board -DEPPATH += --dep-path src include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32f7/common/include/stm32_bh1750.h b/boards/arm/stm32f7/common/include/stm32_bh1750.h deleted file mode 100644 index 486468d9a0a02..0000000000000 --- a/boards/arm/stm32f7/common/include/stm32_bh1750.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/include/stm32_bh1750.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_bh1750_initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt deleted file mode 100644 index d4b612a0f4b2c..0000000000000 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ /dev/null @@ -1,58 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f7/common/src/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -if(CONFIG_SENSORS_BH1750FVI) - list(APPEND SRCS stm32_bh1750.c) -endif() - -if(CONFIG_SENSORS_BMI270_I2C) - list(APPEND SRCS stm32_bmi270.c) -endif() - -if(CONFIG_AUDIO_CS4344) - list(APPEND SRCS stm32_cs4344.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can_setup.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_cansock_setup.c) - endif() -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32_SPI_TEST) - list(APPEND SRCS stm32_spitest.c) -endif() - -target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs deleted file mode 100644 index 0a4f96c20c4eb..0000000000000 --- a/boards/arm/stm32f7/common/src/Make.defs +++ /dev/null @@ -1,62 +0,0 @@ -############################################################################# -# boards/arm/stm32f7/common/src/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_SENSORS_BH1750FVI),y) - CSRCS += stm32_bh1750.c -endif - -ifeq ($(CONFIG_SENSORS_BMI270_I2C),y) - CSRCS += stm32_bmi270.c -endif - -ifeq ($(CONFIG_AUDIO_CS4344),y) - CSRCS += stm32_cs4344.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CSRCS += stm32_can_setup.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CSRCS += stm32_cansock_setup.c -endif -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32_SPI_TEST),y) -CSRCS += stm32_spitest.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif diff --git a/boards/arm/stm32f7/common/src/stm32_bh1750.c b/boards/arm/stm32f7/common/src/stm32_bh1750.c deleted file mode 100644 index 7267173ec412a..0000000000000 --- a/boards/arm/stm32f7/common/src/stm32_bh1750.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f7/common/src/stm32_bh1750.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_bh1750initialize - * - * Description: - * Initialize and register the BH1750FVI Ambient Light driver. - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/lightN - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_bh1750_initialize(int devno, int busno) -{ - struct i2c_master_s *i2c; - char devpath[16]; - int ret; - - sninfo("Initializing BH1750FVI!\n"); - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - return -ENODEV; - } - - /* Then register the ambient light sensor */ - - snprintf(devpath, sizeof(devpath), "/dev/light%d", devno); - ret = bh1750fvi_register(devpath, i2c, BH1750FVI_I2C_ADDR); - if (ret < 0) - { - snerr("ERROR: Error registering BH1750FVI\n"); - } - - return ret; -} - From 5fa8b8d97399f163b0163a5385704bc61cbb650a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 11:47:56 +0200 Subject: [PATCH 41/52] boards/arm/stm32{f1,f4}: drop duplicated reset.c/romfs, use common board logic The board-common stm32_reset.c and stm32_romfs_initialize.c are already provided by boards/arm/common/stm32. Remove the redundant local copies from stm32f103-minimum, nucleo-f429zi, stm32f401rc-rs485 and stm32f4discovery. Enable CONFIG_ARCH_BOARD_COMMON=y in the stm32f4discovery and stm32f401rc-rs485 configs that use CONFIG_BOARDCTL_RESET so board_reset() is pulled from the shared directory. The omnibusf4 reset.c is kept local (genuine DFU-mode reset). Signed-off-by: raiden00pl --- .../stm32f103-minimum/src/CMakeLists.txt | 4 - .../stm32f1/stm32f103-minimum/src/Make.defs | 4 - .../stm32f103-minimum/src/stm32_reset.c | 65 -------- .../stm32f4/nucleo-f429zi/src/CMakeLists.txt | 8 - .../arm/stm32f4/nucleo-f429zi/src/Make.defs | 8 - .../stm32f4/nucleo-f429zi/src/stm32_reset.c | 64 -------- .../src/stm32_romfs_initialize.c | 141 ------------------ .../configs/telnetd/defconfig | 1 + .../stm32f401rc-rs485/src/CMakeLists.txt | 4 - .../stm32f4/stm32f401rc-rs485/src/Make.defs | 4 - .../stm32f401rc-rs485/src/stm32_reset.c | 64 -------- .../stm32f4discovery/configs/adb/defconfig | 1 + .../configs/composite/defconfig | 1 + .../configs/mmcsdspi/defconfig | 1 + .../stm32f4discovery/configs/netnsh/defconfig | 1 + .../stm32f4discovery/configs/rndis/defconfig | 1 + .../stm32f4discovery/configs/wifi/defconfig | 1 + .../stm32f4discovery/src/CMakeLists.txt | 4 - .../stm32f4/stm32f4discovery/src/Make.defs | 4 - .../stm32f4discovery/src/stm32_reset.c | 64 -------- 20 files changed, 7 insertions(+), 438 deletions(-) delete mode 100644 boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c delete mode 100644 boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c delete mode 100644 boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c delete mode 100644 boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c delete mode 100644 boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt index 20cf639591054..98249b1b9fcb3 100644 --- a/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt @@ -22,10 +22,6 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs index c704b2c356464..b65b48862a135 100644 --- a/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs +++ b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs @@ -24,10 +24,6 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif diff --git a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c deleted file mode 100644 index 886ca544518ed..0000000000000 --- a/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ -#ifdef CONFIG_STM32_DFU - /* TODO handle reboot to bootloader */ - -#endif - - up_systemreset(); - return 0; -} diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt index 1f6f30ca92b66..3977def05e600 100644 --- a/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt @@ -60,14 +60,6 @@ if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs index 22ef4de2cdd6e..b5de1a7ff7ee6 100644 --- a/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs @@ -62,14 +62,6 @@ ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c deleted file mode 100644 index c17caaa874e35..0000000000000 --- a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c deleted file mode 100644 index 8eaaf58c73dc1..0000000000000 --- a/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file provides contents of an optional ROMFS volume, mounted at boot */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig index 303875d809fa1..b29a0ff745914 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig @@ -11,6 +11,7 @@ # CONFIG_SYSTEM_TELNETD is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt index 64b46b4813d14..968d1e9dd9244 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt @@ -30,10 +30,6 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs index 04f89e99e4f6d..cc672de33d24d 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs @@ -41,10 +41,6 @@ ifeq ($(CONFIG_USERLED),y) CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c deleted file mode 100644 index 5e24309298006..0000000000000 --- a/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig index 493408723d332..3edc516822576 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig @@ -13,6 +13,7 @@ CONFIG_ADBD_SHELL_SERVICE=y CONFIG_ADBD_USB_SERVER=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig index 51f162f19cf6e..6125b59ae1516 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig @@ -12,6 +12,7 @@ CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig index 905b47c6c4eca..91350175be5b3 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig @@ -14,6 +14,7 @@ # CONFIG_STM32_CCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig index e18237614b4f4..e7e4cc4c09599 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig @@ -12,6 +12,7 @@ # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig index dafce58d6125d..f57a05ca6c5bc 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig @@ -11,6 +11,7 @@ CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig index 673265e3c7724..73a18bd96ac3f 100644 --- a/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig @@ -13,6 +13,7 @@ # CONFIG_SPI_CALLBACK is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f4" diff --git a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt index 159610236d3fa..36cebfbb8cf77 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -92,10 +92,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_CUSTOM_PMINIT) list(APPEND SRCS stm32_pm.c) endif() diff --git a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs index 98f0bd99b475a..78fe9c2a0afc2 100644 --- a/boards/arm/stm32f4/stm32f4discovery/src/Make.defs +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -98,10 +98,6 @@ ifeq ($(CONFIG_CAPTURE),y) CSRCS += stm32_capture.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CSRCS += stm32_pm.c endif diff --git a/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c deleted file mode 100644 index 8381b158e684b..0000000000000 --- a/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ From 5bc1cb4bc3bc23f6adc2bced8e62c0329b1b3ff9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 11:52:39 +0200 Subject: [PATCH 42/52] boards/arm/stm32h5: switch board common to boards/arm/common/stm32 No functional change: the single board does not yet use any shared driver, but the shared board-common features are now available to the family. Signed-off-by: raiden00pl --- boards/Kconfig | 2 +- boards/arm/stm32h5/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32h5/common/Makefile | 36 +++++++++++++++++++ .../nucleo-h563zi/src/{Makefile => Make.defs} | 13 +++---- 4 files changed, 67 insertions(+), 7 deletions(-) create mode 100644 boards/arm/stm32h5/common/CMakeLists.txt create mode 100644 boards/arm/stm32h5/common/Makefile rename boards/arm/stm32h5/nucleo-h563zi/src/{Makefile => Make.defs} (85%) diff --git a/boards/Kconfig b/boards/Kconfig index 69b09c9382ab2..865152a617729 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5206,7 +5206,7 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 diff --git a/boards/arm/stm32h5/common/CMakeLists.txt b/boards/arm/stm32h5/common/CMakeLists.txt new file mode 100644 index 0000000000000..4e3c35d7a99d1 --- /dev/null +++ b/boards/arm/stm32h5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32h5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32h5/common/Makefile b/boards/arm/stm32h5/common/Makefile new file mode 100644 index 0000000000000..943009ffb04f5 --- /dev/null +++ b/boards/arm/stm32h5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32h5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs similarity index 85% rename from boards/arm/stm32h5/nucleo-h563zi/src/Makefile rename to boards/arm/stm32h5/nucleo-h563zi/src/Make.defs index bf97497b3048a..58888944b0f4f 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Make.defs @@ -1,5 +1,5 @@ -############################################################################## -# boards/arm/stm32h5/nucleo-h563zi/src/Makefile +############################################################################ +# boards/arm/stm32h5/nucleo-h563zi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -18,11 +18,10 @@ # License for the specific language governing permissions and limitations # under the License. # -############################################################################## +############################################################################ --include $(TOPDIR)/Make.defs +include $(TOPDIR)/Make.defs -ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c ifeq ($(CONFIG_ARCH_LEDS),y) @@ -55,4 +54,6 @@ ifeq ($(CONFIG_STM32_USBFS_HOST),y) CSRCS += stm32_usb.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board From 09919f02f055deafb2e07514c99683b73f3d365e Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 12:07:10 +0200 Subject: [PATCH 43/52] boards/arm/stm32h7: switch board common to boards/arm/common/stm32 Wire the STM32H7 family to the shared boards/arm/common/stm32 board-common directory. Drop the local copies that are already provided by the shared directory: - stm32_reset.c from nucleo-h723zg, nucleo-h743zi, nucleo-h743zi2, nucleo-h753zi, stm32h745i-disco and stm32h750b-dk - stm32_romfs_initialize.c and stm32_romfs.h from nucleo-h743zi (identical to the shared versions) Enable CONFIG_ARCH_BOARD_COMMON=y in the configs that use CONFIG_BOARDCTL_RESET or CONFIG_STM32_ROMFS so board_reset()/romfs are pulled from the shared directory. Signed-off-by: raiden00pl --- boards/Kconfig | 2 +- boards/arm/stm32h7/common/CMakeLists.txt | 23 +++ boards/arm/stm32h7/common/Makefile | 36 +++++ .../src/{Makefile => Make.defs} | 6 +- .../stm32h7/nucleo-h723zg/src/CMakeLists.txt | 4 - .../nucleo-h723zg/src/{Makefile => Make.defs} | 10 +- .../stm32h7/nucleo-h723zg/src/stm32_reset.c | 64 -------- .../nucleo-h743zi/configs/elf/defconfig | 1 + .../configs/mcuboot-app/defconfig | 1 + .../configs/mcuboot-loader/defconfig | 1 + .../configs/nxboot-app/defconfig | 1 + .../configs/nxboot-loader/defconfig | 1 + .../stm32h7/nucleo-h743zi/src/CMakeLists.txt | 8 - .../nucleo-h743zi/src/{Makefile => Make.defs} | 14 +- .../stm32h7/nucleo-h743zi/src/stm32_reset.c | 64 -------- .../stm32h7/nucleo-h743zi/src/stm32_romfs.h | 63 -------- .../src/stm32_romfs_initialize.c | 139 ------------------ .../nucleo-h743zi2/configs/jumbo/defconfig | 1 + .../stm32h7/nucleo-h743zi2/src/CMakeLists.txt | 4 - .../src/{Makefile => Make.defs} | 10 +- .../stm32h7/nucleo-h743zi2/src/stm32_reset.c | 64 -------- .../nucleo-h745zi/src/{Makefile => Make.defs} | 10 +- .../nucleo-h753zi/configs/jumbo/defconfig | 1 + .../stm32h7/nucleo-h753zi/src/CMakeLists.txt | 4 - .../nucleo-h753zi/src/{Makefile => Make.defs} | 10 +- .../stm32h7/nucleo-h753zi/src/stm32_reset.c | 64 -------- .../openh743i/src/{Makefile => Make.defs} | 6 +- .../portenta-h7/src/{Makefile => Make.defs} | 6 +- .../stm32h745i-disco/src/CMakeLists.txt | 4 - .../src/{Makefile => Make.defs} | 10 +- .../stm32h745i-disco/src/stm32_reset.c | 64 -------- .../src/{Makefile => Make.defs} | 6 +- .../stm32h7/stm32h750b-dk/src/CMakeLists.txt | 4 - .../stm32h750b-dk/src/{Makefile => Make.defs} | 10 +- .../stm32h7/stm32h750b-dk/src/stm32_reset.c | 62 -------- .../src/{Makefile => Make.defs} | 6 +- .../src/{Makefile => Make.defs} | 6 +- 37 files changed, 119 insertions(+), 671 deletions(-) create mode 100644 boards/arm/stm32h7/common/CMakeLists.txt create mode 100644 boards/arm/stm32h7/common/Makefile rename boards/arm/stm32h7/linum-stm32h753bi/src/{Makefile => Make.defs} (90%) rename boards/arm/stm32h7/nucleo-h723zg/src/{Makefile => Make.defs} (88%) delete mode 100644 boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c rename boards/arm/stm32h7/nucleo-h743zi/src/{Makefile => Make.defs} (91%) delete mode 100644 boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c delete mode 100644 boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h delete mode 100644 boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c rename boards/arm/stm32h7/nucleo-h743zi2/src/{Makefile => Make.defs} (88%) delete mode 100644 boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c rename boards/arm/stm32h7/nucleo-h745zi/src/{Makefile => Make.defs} (87%) rename boards/arm/stm32h7/nucleo-h753zi/src/{Makefile => Make.defs} (88%) delete mode 100644 boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c rename boards/arm/stm32h7/openh743i/src/{Makefile => Make.defs} (87%) rename boards/arm/stm32h7/portenta-h7/src/{Makefile => Make.defs} (84%) rename boards/arm/stm32h7/stm32h745i-disco/src/{Makefile => Make.defs} (87%) delete mode 100644 boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c rename boards/arm/stm32h7/stm32h747i-disco/src/{Makefile => Make.defs} (88%) rename boards/arm/stm32h7/stm32h750b-dk/src/{Makefile => Make.defs} (87%) delete mode 100644 boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c rename boards/arm/stm32h7/weact-stm32h743/src/{Makefile => Make.defs} (87%) rename boards/arm/stm32h7/weact-stm32h750/src/{Makefile => Make.defs} (87%) diff --git a/boards/Kconfig b/boards/Kconfig index 865152a617729..e2fc2f2050c82 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5206,7 +5206,7 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32H7 source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 diff --git a/boards/arm/stm32h7/common/CMakeLists.txt b/boards/arm/stm32h7/common/CMakeLists.txt new file mode 100644 index 0000000000000..cad2f907e57fe --- /dev/null +++ b/boards/arm/stm32h7/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32h7/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32h7/common/Makefile b/boards/arm/stm32h7/common/Makefile new file mode 100644 index 0000000000000..dd26b60c33f68 --- /dev/null +++ b/boards/arm/stm32h7/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32h7/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs similarity index 90% rename from boards/arm/stm32h7/linum-stm32h753bi/src/Makefile rename to boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs index 56336dc4c5ab3..84da9cb175914 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +# boards/arm/stm32h7/linum-stm32h753bi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -80,4 +80,6 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_touchscreen.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt index 45813c92cc5f6..95677ecec03e2 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -56,10 +56,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_NET_OA_TC6) list(APPEND SRCS stm32_oa_tc6.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Make.defs similarity index 88% rename from boards/arm/stm32h7/nucleo-h723zg/src/Makefile rename to boards/arm/stm32h7/nucleo-h723zg/src/Make.defs index f57fd57f3068b..21b86d15ae5d5 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h723zg/src/Makefile +# boards/arm/stm32h7/nucleo-h723zg/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -58,12 +58,10 @@ ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_NET_OA_TC6),y) CSRCS += stm32_oa_tc6.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c deleted file mode 100644 index 63b6ff97c8639..0000000000000 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 27247352da03f..f21cc7d12f1b9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -11,6 +11,7 @@ # CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" CONFIG_ARCH_CHIP_STM32=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index 9be0478f7eafb..dd7faf05d87b3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -8,6 +8,7 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" CONFIG_ARCH_CHIP_STM32=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index ac1dce20115d1..42e24eaed4c3c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -7,6 +7,7 @@ # CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" CONFIG_ARCH_CHIP_STM32=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 8d9cdb06d9a01..ce2e87133e261 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -8,6 +8,7 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" CONFIG_ARCH_CHIP_STM32=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index ceb8ba55d3581..ec79fa1b09cfc 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -7,6 +7,7 @@ # CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" CONFIG_ARCH_CHIP_STM32=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt index 4967d7e733d79..6fed42e117649 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt @@ -36,10 +36,6 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32_ROMFS) - list(APPEND SRCS stm32_romfs_initialize.c) -endif() - if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -88,10 +84,6 @@ if(CONFIG_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_BOARDCTL_BOOT_IMAGE) list(APPEND SRCS stm32_boot_image.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Make.defs similarity index 91% rename from boards/arm/stm32h7/nucleo-h743zi/src/Makefile rename to boards/arm/stm32h7/nucleo-h743zi/src/Make.defs index bf54e0db6ef46..b1afe513ef8f6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h743zi/src/Makefile +# boards/arm/stm32h7/nucleo-h743zi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -38,10 +38,6 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32_ROMFS),y) -CSRCS += stm32_romfs_initialize.c -endif - ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif @@ -90,10 +86,6 @@ ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_BOARDCTL_BOOT_IMAGE),y) CSRCS += stm32_boot_image.c endif @@ -110,4 +102,6 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_mmcsd.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c deleted file mode 100644 index be800712641cb..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h deleted file mode 100644 index fe0ccc5070dde..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H -#define __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_STM32_ROMFS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ROMFS_SECTOR_SIZE 64 - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers built-in ROMFS image as block device and mounts it. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void); - -#endif /* CONFIG_STM32_ROMFS */ - -#endif /* __BOARDS_ARM_STM32_NUCLEO_H743ZI_SRC_STM32_ROMFS_H */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c deleted file mode 100644 index 414b734317442..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c +++ /dev/null @@ -1,139 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi/src/stm32_romfs_initialize.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include "stm32_romfs.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_STM32_ROMFS -# error "CONFIG_STM32_ROMFS must be defined" -#else - -#ifndef CONFIG_STM32_ROMFS_IMAGEFILE -# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_DEV_MINOR -# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" -#endif - -#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT -# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" -#endif - -#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) - -#define STR2(m) #m -#define STR(m) STR2(m) - -#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -__asm__ ( - " .section .rodata, \"a\" \n" - " .balign 16 \n" - " .globl romfs_data_begin \n" - "romfs_data_begin: \n" - " .incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE)"\n" - " .balign " STR(ROMFS_SECTOR_SIZE) "\n" - " .globl romfs_data_end \n" - "romfs_data_end: \n" - ); - -extern const uint8_t romfs_data_begin[]; -extern const uint8_t romfs_data_end[]; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_romfs_initialize - * - * Description: - * Registers the aboveincluded binary file as block device. - * Then mounts the block device as ROMFS filesystems. - * - * Returned Value: - * Zero (OK) on success, a negated errno value on error. - * - * Assumptions/Limitations: - * Memory addresses [romfs_data_begin .. romfs_data_end) should contain - * ROMFS volume data, as included in the assembly snippet above (l. 84). - * - ****************************************************************************/ - -int stm32_romfs_initialize(void) -{ - size_t romfs_data_len; - int ret; - - /* Create a ROM disk for the /etc filesystem */ - - romfs_data_len = romfs_data_end - romfs_data_begin; - - ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, - NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); - if (ret < 0) - { - ferr("ERROR: romdisk_register failed: %d\n", -ret); - return ret; - } - - /* Mount the file system */ - - finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, - "romfs", MS_RDONLY, NULL); - if (ret < 0) - { - ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); - return ret; - } - - return OK; -} - -#endif /* CONFIG_STM32_ROMFS */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index 436b8c8c378d4..f6ea962097980 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -9,6 +9,7 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt index 1d7544f8cdba1..1b725d66c14d7 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt @@ -48,10 +48,6 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs similarity index 88% rename from boards/arm/stm32h7/nucleo-h743zi2/src/Makefile rename to boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs index f05dd5b891c96..eb387e1868145 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +# boards/arm/stm32h7/nucleo-h743zi2/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -54,8 +54,6 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c deleted file mode 100644 index 5ed1e65ea63d4..0000000000000 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h743zi2/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/nucleo-h745zi/src/Makefile rename to boards/arm/stm32h7/nucleo-h745zi/src/Make.defs index 37c9b6b815dc6..51e5d21b913fc 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h745zi/src/Makefile +# boards/arm/stm32h7/nucleo-h745zi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -50,8 +50,6 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig index 64f82396477a6..798c4794b4c76 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig @@ -9,6 +9,7 @@ # CONFIG_STANDARD_SERIAL is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" +CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt index 8e61aeb5382f1..97d733a628051 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt @@ -48,10 +48,6 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile b/boards/arm/stm32h7/nucleo-h753zi/src/Make.defs similarity index 88% rename from boards/arm/stm32h7/nucleo-h753zi/src/Makefile rename to boards/arm/stm32h7/nucleo-h753zi/src/Make.defs index e310e6c8a8efa..9e33e8b94802a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h753zi/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h753zi/src/Makefile +# boards/arm/stm32h7/nucleo-h753zi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -54,8 +54,6 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c deleted file mode 100644 index 5eb902c30fc6d..0000000000000 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/nucleo-h753zi/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/openh743i/src/Makefile rename to boards/arm/stm32h7/openh743i/src/Make.defs index c9f0115dbabde..bd6094b33ab27 100644 --- a/boards/arm/stm32h7/openh743i/src/Makefile +++ b/boards/arm/stm32h7/openh743i/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/openh743i/src/Makefile +# boards/arm/stm32h7/openh743i/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -42,4 +42,6 @@ ifeq ($(CONFIG_USBDEV_COMPOSITE),y) CSRCS += stm32_composite.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/portenta-h7/src/Makefile b/boards/arm/stm32h7/portenta-h7/src/Make.defs similarity index 84% rename from boards/arm/stm32h7/portenta-h7/src/Makefile rename to boards/arm/stm32h7/portenta-h7/src/Make.defs index adca38bed3e6c..90dbd1710370f 100644 --- a/boards/arm/stm32h7/portenta-h7/src/Makefile +++ b/boards/arm/stm32h7/portenta-h7/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/portenta-h7/src/Makefile +# boards/arm/stm32h7/portenta-h7/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -28,4 +28,6 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt index bb605d54ac719..276181929cc37 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt @@ -36,10 +36,6 @@ if(CONFIG_TESTING_OSTEST) list(APPEND SRCS stm32_ostest.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile b/boards/arm/stm32h7/stm32h745i-disco/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/stm32h745i-disco/src/Makefile rename to boards/arm/stm32h7/stm32h745i-disco/src/Make.defs index 13359572cb5d9..dfa13ad3ab285 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h745i-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/stm32h745i-disco/src/Makefile +# boards/arm/stm32h7/stm32h745i-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -38,10 +38,6 @@ ifeq ($(CONFIG_TESTING_OSTEST),y) CSRCS += stm32_ostest.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif @@ -50,4 +46,6 @@ ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c deleted file mode 100644 index ed84aebc4db21..0000000000000 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/stm32h745i-disco/src/stm32_reset.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile b/boards/arm/stm32h7/stm32h747i-disco/src/Make.defs similarity index 88% rename from boards/arm/stm32h7/stm32h747i-disco/src/Makefile rename to boards/arm/stm32h7/stm32h747i-disco/src/Make.defs index 2f0eaeee20ff8..d25798a6cbeb8 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h747i-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/stm32h747i-disco/src/Makefile +# boards/arm/stm32h7/stm32h747i-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -58,4 +58,6 @@ ifeq ($(CONFIG_FAT_DMAMEMORY),y) CSRCS += stm32_dma_alloc.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt index 4424e92766119..1e00764ac9ce7 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt @@ -34,10 +34,6 @@ if(CONFIG_TESTING_OSTEST) list(APPEND SRCS stm32_ostest.c) endif() -if(CONFIG_BOARDCTL_RESET) - list(APPEND SRCS stm32_reset.c) -endif() - if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile b/boards/arm/stm32h7/stm32h750b-dk/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/stm32h750b-dk/src/Makefile rename to boards/arm/stm32h7/stm32h750b-dk/src/Make.defs index 942bfb9fd3e9e..4fc260f6b9152 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile +++ b/boards/arm/stm32h7/stm32h750b-dk/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/stm32h750b-dk/src/Makefile +# boards/arm/stm32h7/stm32h750b-dk/src/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -36,10 +36,6 @@ ifeq ($(CONFIG_TESTING_OSTEST),y) CSRCS += stm32_ostest.c endif -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += stm32_reset.c -endif - ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif @@ -48,4 +44,6 @@ ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c deleted file mode 100644 index 7bb3feed5f531..0000000000000 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c +++ /dev/null @@ -1,62 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32h7/stm32h750b-dk/src/stm32_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value int this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/weact-stm32h743/src/Makefile rename to boards/arm/stm32h7/weact-stm32h743/src/Make.defs index 0bbd3d18694dd..4aac69d54d0c5 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h743/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/weact-stm32h743/src/Makefile +# boards/arm/stm32h7/weact-stm32h743/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -44,4 +44,6 @@ ifeq ($(CONFIG_FAT_DMAMEMORY),y) CSRCS += stm32_dma_alloc.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Makefile b/boards/arm/stm32h7/weact-stm32h750/src/Make.defs similarity index 87% rename from boards/arm/stm32h7/weact-stm32h750/src/Makefile rename to boards/arm/stm32h7/weact-stm32h750/src/Make.defs index 083f46024de37..b9296329d36a6 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h750/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/weact-stm32h750/src/Makefile +# boards/arm/stm32h7/weact-stm32h750/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -44,4 +44,6 @@ ifeq ($(CONFIG_FAT_DMAMEMORY),y) CSRCS += stm32_dma_alloc.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board From 3b16e69ebaa6a622fe7c69754ff47fd5ccd6c404 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 12:10:07 +0200 Subject: [PATCH 44/52] boards/arm/stm32{l5,u5,wb,wl5,n6}: switch board common to stm32 common Wire the remaining STM32 families (L5, U5, WB, WL5, N6) to the shared boards/arm/common/stm32 board-common directory. No functional change: these boards do not yet use any shared driver, but the shared board-common features are now available to the families. Signed-off-by: raiden00pl --- boards/Kconfig | 2 +- boards/arm/stm32l5/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32l5/common/Makefile | 36 +++++++++++++++++++ .../nucleo-l552ze/src/{Makefile => Make.defs} | 6 ++-- .../stm32l562e-dk/src/{Makefile => Make.defs} | 6 ++-- boards/arm/stm32n6/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32n6/common/Makefile | 36 +++++++++++++++++++ .../src/{Makefile => Make.defs} | 6 ++-- .../src/{Makefile => Make.defs} | 6 ++-- boards/arm/stm32u5/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32u5/common/Makefile | 36 +++++++++++++++++++ .../src/{Makefile => Make.defs} | 6 ++-- boards/arm/stm32wb/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32wb/common/Makefile | 36 +++++++++++++++++++ .../flipperzero/src/{Makefile => Make.defs} | 6 ++-- .../nucleo-wb55rg/src/{Makefile => Make.defs} | 6 ++-- boards/arm/stm32wl5/common/CMakeLists.txt | 23 ++++++++++++ boards/arm/stm32wl5/common/Makefile | 36 +++++++++++++++++++ .../nucleo-wl55jc/src/{Makefile => Make.defs} | 6 ++-- 19 files changed, 328 insertions(+), 17 deletions(-) create mode 100644 boards/arm/stm32l5/common/CMakeLists.txt create mode 100644 boards/arm/stm32l5/common/Makefile rename boards/arm/stm32l5/nucleo-l552ze/src/{Makefile => Make.defs} (85%) rename boards/arm/stm32l5/stm32l562e-dk/src/{Makefile => Make.defs} (86%) create mode 100644 boards/arm/stm32n6/common/CMakeLists.txt create mode 100644 boards/arm/stm32n6/common/Makefile rename boards/arm/stm32n6/nucleo-n657x0-q/src/{Makefile => Make.defs} (85%) rename boards/arm/stm32u5/b-u585i-iot02a/src/{Makefile => Make.defs} (85%) create mode 100644 boards/arm/stm32u5/common/CMakeLists.txt create mode 100644 boards/arm/stm32u5/common/Makefile rename boards/arm/stm32u5/nucleo-u5a5zj-q/src/{Makefile => Make.defs} (85%) create mode 100644 boards/arm/stm32wb/common/CMakeLists.txt create mode 100644 boards/arm/stm32wb/common/Makefile rename boards/arm/stm32wb/flipperzero/src/{Makefile => Make.defs} (85%) rename boards/arm/stm32wb/nucleo-wb55rg/src/{Makefile => Make.defs} (84%) create mode 100644 boards/arm/stm32wl5/common/CMakeLists.txt create mode 100644 boards/arm/stm32wl5/common/Makefile rename boards/arm/stm32wl5/nucleo-wl55jc/src/{Makefile => Make.defs} (87%) diff --git a/boards/Kconfig b/boards/Kconfig index e2fc2f2050c82..9ebfc82638982 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5206,7 +5206,7 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32H7 +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32N6 source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 diff --git a/boards/arm/stm32l5/common/CMakeLists.txt b/boards/arm/stm32l5/common/CMakeLists.txt new file mode 100644 index 0000000000000..98744875f50f2 --- /dev/null +++ b/boards/arm/stm32l5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32l5/common/Makefile b/boards/arm/stm32l5/common/Makefile new file mode 100644 index 0000000000000..263bee9b75e73 --- /dev/null +++ b/boards/arm/stm32l5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32l5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/Makefile b/boards/arm/stm32l5/nucleo-l552ze/src/Make.defs similarity index 85% rename from boards/arm/stm32l5/nucleo-l552ze/src/Makefile rename to boards/arm/stm32l5/nucleo-l552ze/src/Make.defs index 28cdefc9f468d..ae55afd1c34b0 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/Makefile +++ b/boards/arm/stm32l5/nucleo-l552ze/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32l5/nucleo-l552ze/src/Makefile +# boards/arm/stm32l5/nucleo-l552ze/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -35,4 +35,6 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/Makefile b/boards/arm/stm32l5/stm32l562e-dk/src/Make.defs similarity index 86% rename from boards/arm/stm32l5/stm32l562e-dk/src/Makefile rename to boards/arm/stm32l5/stm32l562e-dk/src/Make.defs index aa38e15db504a..b0fef85b2252f 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/Makefile +++ b/boards/arm/stm32l5/stm32l562e-dk/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32l5/stm32l562e-dk/src/Makefile +# boards/arm/stm32l5/stm32l562e-dk/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -35,4 +35,6 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32n6/common/CMakeLists.txt b/boards/arm/stm32n6/common/CMakeLists.txt new file mode 100644 index 0000000000000..1a0aba1198dee --- /dev/null +++ b/boards/arm/stm32n6/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32n6/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32n6/common/Makefile b/boards/arm/stm32n6/common/Makefile new file mode 100644 index 0000000000000..7026a5e5312d4 --- /dev/null +++ b/boards/arm/stm32n6/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32n6/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile b/boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs similarity index 85% rename from boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile rename to boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs index 74f826721e4f7..794c50d1b24d1 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile +++ b/boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32n6/nucleo-n657x0-q/src/Makefile +# boards/arm/stm32n6/nucleo-n657x0-q/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -31,4 +31,6 @@ else CSRCS += stm32_userleds.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile b/boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs similarity index 85% rename from boards/arm/stm32u5/b-u585i-iot02a/src/Makefile rename to boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs index 915275f7e6f75..f17f63d09794b 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +# boards/arm/stm32u5/b-u585i-iot02a/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -29,4 +29,6 @@ ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32u5/common/CMakeLists.txt b/boards/arm/stm32u5/common/CMakeLists.txt new file mode 100644 index 0000000000000..aac8d57d3e903 --- /dev/null +++ b/boards/arm/stm32u5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32u5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32u5/common/Makefile b/boards/arm/stm32u5/common/Makefile new file mode 100644 index 0000000000000..9688ec685c992 --- /dev/null +++ b/boards/arm/stm32u5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32u5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs similarity index 85% rename from boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile rename to boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs index 93d9723add326..4f7e99fa88e4f 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +# boards/arm/stm32u5/nucleo-u5a5zj-q/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -33,4 +33,6 @@ ifeq ($(CONFIG_USBDEV),y) CSRCS += stm32_usb.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wb/common/CMakeLists.txt b/boards/arm/stm32wb/common/CMakeLists.txt new file mode 100644 index 0000000000000..db8921e4f1c9d --- /dev/null +++ b/boards/arm/stm32wb/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32wb/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32wb/common/Makefile b/boards/arm/stm32wb/common/Makefile new file mode 100644 index 0000000000000..37068a4128551 --- /dev/null +++ b/boards/arm/stm32wb/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32wb/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32wb/flipperzero/src/Makefile b/boards/arm/stm32wb/flipperzero/src/Make.defs similarity index 85% rename from boards/arm/stm32wb/flipperzero/src/Makefile rename to boards/arm/stm32wb/flipperzero/src/Make.defs index 716d6b290016b..08de31cb0ab35 100644 --- a/boards/arm/stm32wb/flipperzero/src/Makefile +++ b/boards/arm/stm32wb/flipperzero/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32wb/flipperzero/src/Makefile +# boards/arm/stm32wb/flipperzero/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -32,4 +32,6 @@ ifeq ($(CONFIG_LCD_ST7565),y) CSRCS += stm32_lcd_st7565.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/Makefile b/boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs similarity index 84% rename from boards/arm/stm32wb/nucleo-wb55rg/src/Makefile rename to boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs index 11d004aa68c5c..6b303424bf7dd 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/Makefile +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32wb/nucleo-wb55rg/src/Makefile +# boards/arm/stm32wb/nucleo-wb55rg/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -30,4 +30,6 @@ else CSRCS += stm32_userleds.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32wl5/common/CMakeLists.txt b/boards/arm/stm32wl5/common/CMakeLists.txt new file mode 100644 index 0000000000000..1d22b5ae29426 --- /dev/null +++ b/boards/arm/stm32wl5/common/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32wl5/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) diff --git a/boards/arm/stm32wl5/common/Makefile b/boards/arm/stm32wl5/common/Makefile new file mode 100644 index 0000000000000..6eef4c90d504f --- /dev/null +++ b/boards/arm/stm32wl5/common/Makefile @@ -0,0 +1,36 @@ +############################################################################# +# boards/arm/stm32wl5/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile b/boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs similarity index 87% rename from boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile rename to boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs index 1c280874bc539..6f8be0ff7f864 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32wl5/nucleo-wl55jc/src/Makefile +# boards/arm/stm32wl5/nucleo-wl55jc/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -37,4 +37,6 @@ endif CSRCS += $(CSRCS-y) -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board From f3136b27a536e5218935b7299dd384b9c71191d3 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 3 Jun 2026 12:29:40 +0200 Subject: [PATCH 45/52] arch/arm/src/stm32: unify pulse count driver into common/stm32 Merge the six near-identical pulse count drivers (two common, plus the F7/H7/H5/L4 copies) into a single common/stm32/stm32_pulsecount.c that pulls register definitions through the per-family "stm32.h" umbrella. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 3 +- arch/arm/src/common/stm32/CMakeLists.txt | 12 +- arch/arm/src/common/stm32/Kconfig.tim | 3 - arch/arm/src/common/stm32/Make.defs | 14 +- .../stm32}/stm32_pulsecount.c | 62 +- .../src/common/stm32/stm32_pulsecount_m0_v1.c | 1277 ------------ .../stm32/stm32_pulsecount_m3m4_v1v2v3.c | 1775 ---------------- arch/arm/src/stm32c0/stm32.h | 1 + arch/arm/src/stm32f0/stm32.h | 1 + arch/arm/src/stm32f7/CMakeLists.txt | 4 - arch/arm/src/stm32f7/Make.defs | 4 - arch/arm/src/stm32f7/stm32_pulsecount.h | 39 - arch/arm/src/stm32g0/stm32.h | 1 + arch/arm/src/stm32h5/CMakeLists.txt | 4 - arch/arm/src/stm32h5/Make.defs | 4 - arch/arm/src/stm32h5/stm32.h | 1 + arch/arm/src/stm32h5/stm32_pulsecount.c | 1792 ---------------- arch/arm/src/stm32h5/stm32_pulsecount.h | 39 - arch/arm/src/stm32h7/CMakeLists.txt | 4 - arch/arm/src/stm32h7/Make.defs | 4 - arch/arm/src/stm32h7/stm32.h | 1 + arch/arm/src/stm32h7/stm32_pulsecount.c | 1813 ----------------- arch/arm/src/stm32l0/stm32.h | 1 + arch/arm/src/stm32l4/CMakeLists.txt | 4 - arch/arm/src/stm32l4/Make.defs | 4 - arch/arm/src/stm32l4/stm32l4_pulsecount.c | 1657 --------------- arch/arm/src/stm32l4/stm32l4_pulsecount.h | 39 - 27 files changed, 67 insertions(+), 8496 deletions(-) rename arch/arm/src/{stm32f7 => common/stm32}/stm32_pulsecount.c (96%) delete mode 100644 arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c delete mode 100644 arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c delete mode 100644 arch/arm/src/stm32f7/stm32_pulsecount.h delete mode 100644 arch/arm/src/stm32h5/stm32_pulsecount.c delete mode 100644 arch/arm/src/stm32h5/stm32_pulsecount.h delete mode 100644 arch/arm/src/stm32h7/stm32_pulsecount.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_pulsecount.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_pulsecount.h diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 3528e51466d19..6389d90e48035 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -1820,9 +1820,8 @@ arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c alin.jerpelea@sony.com ju arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c alin.jerpelea@sony.com juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me xiaoxiang@xiaomi.com arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me xiaoxiang@xiaomi.com arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me +arch/arm/src/common/stm32/stm32_pulsecount.c raiden00@railab.me arch/arm/src/common/stm32/stm32_pulsecount.h alin.jerpelea@sony.com raiden00@railab.me moura.fmo@gmail.com xiaoxiang@xiaomi.com -arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c raiden00@railab.me -arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c raiden00@railab.me arch/arm/src/common/stm32/stm32_pwm.h alin.jerpelea@sony.com raiden00@railab.me arch/arm/src/common/stm32/stm32_pwm_m0_v1.c paul-a.patience@polymtl.ca dev@ziggurat29.com dpo@certi.org.br raiden00@railab.me gvr@certi.org.br arch/arm/src/common/stm32/stm32_pwm_m0_v1.h raiden00@railab.me dpo@certi.org.br alin.jerpelea@sony.com gvr@certi.org.br anchao@xiaomi.com diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 427254933245d..8ab65ba855020 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -34,6 +34,10 @@ set(SRCS) list(APPEND SRCS stm32_waste.c) list(APPEND SRCS stm32_uid.c) +if(CONFIG_STM32_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount.c) +endif() + if(CONFIG_STM32_COMMON_LEGACY) list( APPEND @@ -281,10 +285,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c) endif() - if(CONFIG_STM32_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c) - endif() - if(CONFIG_STM32_CAP) list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) endif() @@ -444,10 +444,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_pwm_m0_v1.c) endif() - if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount_m0_v1.c) - endif() - if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1) list(APPEND SRCS stm32_adc_m0_v1.c) endif() diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim index 05d214b4c6833..d1c8f06461d30 100644 --- a/arch/arm/src/common/stm32/Kconfig.tim +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -2767,7 +2767,6 @@ config STM32_TIM1_PULSECOUNT_TDTS int "TIM1 pulse count clock division" default 0 range 0 2 - depends on !STM32_HAVE_IP_TIMERS config STM32_TIM1_PULSECOUNT_CHANNEL int "TIM1 pulse count channel" @@ -2780,13 +2779,11 @@ config STM32_TIM1_PULSECOUNT_POL int "TIM1 pulse count output polarity" default 0 range 0 1 - depends on !STM32_HAVE_IP_TIMERS config STM32_TIM1_PULSECOUNT_IDLE int "TIM1 pulse count idle state" default 0 range 0 1 - depends on !STM32_HAVE_IP_TIMERS endif # STM32_TIM1_PULSECOUNT diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index e932e3a46033e..82be1b7ca0ef5 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -42,6 +42,10 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) CHIP_CSRCS += stm32_waste.c CHIP_CSRCS += stm32_uid.c +ifeq ($(CONFIG_STM32_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount.c +endif + ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c @@ -314,10 +318,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c endif -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c -endif - ifeq ($(CONFIG_STM32_CAP),y) CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c endif @@ -495,12 +495,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm_m0_v1.c endif -ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount_m0_v1.c -endif -endif - ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy) CHIP_CSRCS += stm32_adc_m0_v1.c endif diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount.c similarity index 96% rename from arch/arm/src/stm32f7/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount.c index 664dd33dabd54..fd98e42ef061a 100644 --- a/arch/arm/src/stm32f7/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount.c * * SPDX-License-Identifier: Apache-2.0 * @@ -39,9 +39,9 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_pulsecount.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" +#include "stm32.h" + +/* Generalized pulse count support for all STM32 families */ /**************************************************************************** * Pre-processor Definitions @@ -70,9 +70,31 @@ #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +/* The TIM1/TIM8 update-event interrupt vector is named differently across + * families + */ + +#if defined(STM32_IRQ_TIM1UP) +# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1UP +#elif defined(STM32_IRQ_TIM1_UP) +# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_UP +#elif defined(STM32_IRQ_TIM1_BRK) +# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_BRK +#endif + +#if defined(STM32_IRQ_TIM8UP) +# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8UP +#elif defined(STM32_IRQ_TIM8_UP) +# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8_UP +#endif + /* Default GPIO pins state */ -#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) +#if defined(CONFIG_STM32_STM32F10XX) +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) +#else +# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) +#endif #define PULSECOUNT_POL_NEG 1 #define PULSECOUNT_IDLE_ACTIVE 1 @@ -247,7 +269,7 @@ static struct stm32_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1UP, + .irq = PULSECOUNT_TIM1_IRQ, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; @@ -298,7 +320,7 @@ static struct stm32_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8UP, + .irq = PULSECOUNT_TIM8_IRQ, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; @@ -342,6 +364,11 @@ static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) { bool ret = false; + /* TODO: If all the advanced-timer registers are safely word-accessible + * then this helper could be dropped and every access made 32-bit. + * This is NOT verified yet. + */ + if (timtype == TIMTYPE_ADVANCED) { if (offset == STM32_ATIM_CR2_OFFSET || @@ -807,10 +834,17 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 3: { ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE | ATIM_CCMR1_OC1M); + ATIM_CCMR1_OC1PE); ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); ocmode |= ATIM_CCMR1_OC1PE; +#ifdef ATIM_CCMR1_OC1M + /* Clear the extended (bit 3) output-compare-mode bit on the timer + * IP versions that have it. + */ + + ccmr &= ~(ATIM_CCMR1_OC1M); +#endif break; } @@ -820,10 +854,17 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 4: { ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE | ATIM_CCMR1_OC2M); + ATIM_CCMR1_OC2PE); ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); ocmode |= ATIM_CCMR1_OC2PE; +#ifdef ATIM_CCMR1_OC2M + /* Clear the extended (bit 3) output-compare-mode bit on the timer + * IP versions that have it. + */ + + ccmr &= ~(ATIM_CCMR1_OC2M); +#endif break; } } @@ -1672,7 +1713,8 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, if (info->count > 0) { - /* Only the advanced timers (TIM1,8 can support the pulse counting) */ + /* Only the advanced timers (TIM1,8 can support the pulse counting) + */ if (priv->timtype != TIMTYPE_ADVANCED) { diff --git a/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c deleted file mode 100644 index e64d5be88fedf..0000000000000 --- a/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c +++ /dev/null @@ -1,1277 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_gpio.h" -#include "stm32_pulsecount.h" -#include "stm32_rcc.h" -#include "stm32_tim.h" - -/* This module only supports pulse count on advanced timers. */ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pulse count is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1 */ -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED - -#define HAVE_IP_TIMERS_V2 1 - -/* CCMR2 */ - -#define HAVE_CCMR2 1 - -#ifdef STM32_APB2_TIM1_CLKIN -# define PULSECOUNT_TIM1_CLKIN STM32_APB2_TIM1_CLKIN -#else -# define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN -#endif - -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 -# define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT -#else -# error Unsupported TIM1 pulse count channel -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) -# warning "pulsecount_dumpgpio not implemented" -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct stm32_pulsecountchan_s -{ - uint8_t channel; - uint32_t pincfg; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_pulsecounttimer_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_pulsecountchan_s channel; - uint8_t timid; - uint8_t timtype; - uint8_t irq; - uint32_t prev; - uint32_t curr; - uint32_t count; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t stm32pulsecount_getreg(struct stm32_pulsecounttimer_s *priv, - int offset); -static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, - int offset, uint32_t value); -static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, - const char *msg); -#else -# define stm32pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int -stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, - uint8_t channel); -static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, - const struct pulsecount_info_s *info); -static void stm32pulsecount_setapbclock( - struct stm32_pulsecounttimer_s *priv, bool on); -static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv); -static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg); -static uint32_t stm32pulsecount_pulsecount(uint32_t count); - -/* Pulsecount driver methods */ - -static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); - -static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* This is the list of lower half pulsecount driver methods used by the upper - * half driver. - */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = stm32pulsecount_setup, - .shutdown = stm32pulsecount_shutdown, - .start = stm32pulsecount_start, - .stop = stm32pulsecount_stop, - .ioctl = stm32pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecounttimer_s g_pulsecount1dev = -{ - .ops = &g_pulsecountops, - .timid = 1, - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, - .pincfg = PULSECOUNT_TIM1_CHCFG, - }, - .timtype = TIMTYPE_TIM1, - .irq = STM32_IRQ_TIM1_BRK, - .base = STM32_TIM1_BASE, - .pclk = PULSECOUNT_TIM1_CLKIN, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32pulsecount_reg_is_32bit - * - * Description: - * Verify whether the timer register is 32bit or not. - * - * Input Parameters: - * timtype - The type of the timer. See the TIMTYPE_* definitions - * offset - The offset to the register to read - * - * Returned Value: - * Return true for 32 bits register; false otherwise. - * - ****************************************************************************/ - -static bool stm32pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET || - offset == STM32_ATIM_DMAR_OFFSET || - offset == STM32_ATIM_AF1_OFFSET || - offset == STM32_ATIM_TISEL_OFFSET) - { - return true; - } - } - - return false; -} - -/**************************************************************************** - * Name: stm32pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32pulsecount_getreg( - struct stm32_pulsecounttimer_s *priv, int offset) -{ - uint32_t retval; - - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: stm32pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_putreg(struct stm32_pulsecounttimer_s *priv, - int offset, uint32_t value) -{ - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_modifyreg(struct stm32_pulsecounttimer_s *priv, - uint32_t offset, uint32_t clearbits, - uint32_t setbits) -{ - if (stm32pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, clearbits, setbits); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * msg - A message to be printed on the screen - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void stm32pulsecount_dumpregs(struct stm32_pulsecounttimer_s *priv, - const char *msg) -{ - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - stm32pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->timtype == TIMTYPE_ADVANCED) - { - _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); - - _info(" AF1: %04x TISEL: %04x\n", - stm32pulsecount_getreg(priv, STM32_ATIM_AF1_OFFSET), - stm32pulsecount_getreg(priv, STM32_ATIM_TISEL_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - * Input Parameters: - * priv - A reference to the pulsecount timer status - * channel - Timer output channel - * - * Returned Value: - * Zero on success; - ****************************************************************************/ - -static int -stm32pulsecount_output_configure(struct stm32_pulsecounttimer_s *priv, - uint8_t channel) -{ - uint32_t cr2; - uint32_t ccer; - - /* Get current registers state */ - - cr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = stm32pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Reset the output polarity level of all channels (selects high - * polarity) - */ - - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - - /* Enable the output state of the selected channels */ - - ccer |= (GTIM_CCER_CC1E << ((channel - 1) * 4)); - - if (priv->timtype == TIMTYPE_ADVANCED) - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - - stm32pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - stm32pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * priv - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_timer(struct stm32_pulsecounttimer_s *priv, - const struct pulsecount_info_s *info) -{ - /* Calculated values */ - - uint32_t prescaler; - uint32_t timclk; - uint32_t reload; - uint32_t ccr; - ub16_t duty; - uint32_t chanmode = GTIM_CCMR_MODE_PWM1; - uint8_t channel; - - /* Register contents */ - - uint32_t cr1; - uint32_t ccmr1; -#if defined(HAVE_CCMR2) - uint32_t ccmr2; - uint32_t ocmode2; -#endif - - /* New timer register bit settings */ - - uint32_t ocmode1; - - DEBUGASSERT(priv != NULL && info != NULL); - - ccmr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET); - -#if defined(HAVE_CCMR2) - ccmr2 = stm32pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET); -#endif - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Disable all interrupts and DMA requests, clear all pending status */ - - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / pulsecount_frequency(info) + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / pulsecount_frequency(info); - - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " " - "TIMCLK: %" PRIu32 " prescaler: %" PRIu32 - " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, pulsecount_frequency(info), timclk, - prescaler, reload); - - /* Set up the timer CR1 register: - * - * 1,8 CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN - * 2-5 CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN - * 6-7 ARPE OPM URS UDIS CEN - * 9-14 CKD[1:0] ARPE URS UDIS CEN - * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN - */ - - cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Disable the timer until we get it configured */ - - cr1 &= ~GTIM_CR1_CEN; - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - - cr1 |= GTIM_CR1_EDGE; - - /* Set the clock division to zero for all (but the basic timers, but there - * should be no basic timers in this context - */ - - cr1 &= ~GTIM_CR1_CKD_MASK; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the reload and prescaler values */ - - stm32pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - stm32pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (prescaler - 1)); - - /* Set the advanced timer's repetition counter */ - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1. stm32pulsecount_start() has - * already assured us that the count value is within range. - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = stm32pulsecount_pulsecount(info->count); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = stm32pulsecount_pulsecount(info->count - - priv->prev); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - stm32pulsecount_putreg(priv, STM32_ATIM_EGR_OFFSET, ATIM_EGR_UG); - } - } - - /* Handle channel specific setup */ - - ocmode1 = 0; -#if defined(HAVE_CCMR2) - ocmode2 = 0; -#endif - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - switch (channel) - { - case 1: - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC1S_SHIFT) | - (chanmode << GTIM_CCMR1_OC1M_SHIFT) | - GTIM_CCMR1_OC1PE; - stm32pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, ccr); - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_OC1M_MASK | - GTIM_CCMR1_OC1PE | GTIM_CCMR1_OC1M); - break; - - case 2: - ocmode1 |= (GTIM_CCMR_CCS_CCOUT << GTIM_CCMR1_CC2S_SHIFT) | - (chanmode << GTIM_CCMR1_OC2M_SHIFT) | - GTIM_CCMR1_OC2PE; - stm32pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, ccr); - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_OC2M_MASK | - GTIM_CCMR1_OC2PE | GTIM_CCMR1_OC2M); - break; - - case 3: - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) | - (chanmode << ATIM_CCMR2_OC3M_SHIFT) | - ATIM_CCMR2_OC3PE; - stm32pulsecount_putreg(priv, STM32_ATIM_CCR3_OFFSET, ccr); - ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | - ATIM_CCMR2_OC3PE | ATIM_CCMR2_OC3M); - break; - - case 4: - ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) | - (chanmode << ATIM_CCMR2_OC4M_SHIFT) | - ATIM_CCMR2_OC4PE; - stm32pulsecount_putreg(priv, STM32_ATIM_CCR4_OFFSET, ccr); - ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | - ATIM_CCMR2_OC4PE | ATIM_CCMR2_OC4M); - break; - - default: - _err("ERROR: No such channel: %u\n", channel); - return -EINVAL; - } - - stm32pulsecount_output_configure(priv, channel); - - ccmr1 |= ocmode1; -#if defined(HAVE_CCMR2) - ccmr2 |= ocmode2; -#endif - - if (priv->timtype == TIMTYPE_ADVANCED) - { - uint32_t bdtr; - - /* Get current register state */ - - bdtr = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); - - bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR); - bdtr |= ATIM_BDTR_MOE; - - stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); - } - - /* Save the modified register values */ - - putreg32(ccmr1, priv->base + STM32_GTIM_CCMR1_OFFSET); -#if defined(HAVE_CCMR2) - putreg32(ccmr2, priv->base + STM32_ATIM_CCMR2_OFFSET); -#endif - - /* Set the ARR Preload Bit */ - - cr1 = stm32pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_ARPE; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that stm32pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - cr1 |= GTIM_CR1_CEN; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - else - { - /* Just enable the timer, leaving all interrupts disabled */ - - cr1 |= GTIM_CR1_CEN; - stm32pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - } - - stm32pulsecount_dumpregs(priv, "After starting"); - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * priv - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - ****************************************************************************/ - -static int stm32pulsecount_interrupt(struct stm32_pulsecounttimer_s *priv) -{ - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the mast output to stop the output as - * quickly as possible. - */ - - regval = stm32pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); - regval &= ~ATIM_BDTR_MOE; - stm32pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); - - /* Disable first interrupts, stop and reset the timer */ - - stm32pulsecount_stop((struct pulsecount_lowerhalf_s *)priv); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = stm32pulsecount_pulsecount(priv->count - priv->prev); - stm32pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output - */ - - _info("Update interrupt SR: %04x prev: %" PRIu32 " curr: %" PRIu32 - " count: %" PRIu32 "\n", - regval, priv->prev, priv->curr, priv->count); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_tim1interrupt - * - * Description: - * Handle timer 1 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return stm32pulsecount_interrupt(&g_pulsecount1dev); -} - -/**************************************************************************** - * Name: stm32pulsecount_pulsecount - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint32_t stm32pulsecount_pulsecount(uint32_t count) -{ - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (ATIM_RCR_REP_MAX + 1) >> 1; - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: stm32pulsecount_setapbclock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32pulsecount_setapbclock( - struct stm32_pulsecounttimer_s *priv, bool on) -{ - uint32_t en_bit; - uint32_t regaddr; - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM1EN; - break; -#endif - default: - return; - } - - /* Enable/disable APB 1/2 clock for timer */ - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } -} - -/**************************************************************************** - * Name: stm32pulsecount_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int stm32pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t pincfg; - - _info("TIM%u\n", priv->timid); - stm32pulsecount_dumpregs(priv, "Initially"); - - /* Enable APB1/2 clocking for timer. */ - - stm32pulsecount_setapbclock(priv, true); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - pincfg = priv->channel.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - } - - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t pincfg; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - stm32pulsecount_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - stm32pulsecount_setapbclock(priv, false); - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; - - stm32_configgpio(pincfg); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_start - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - - /* Check if a pulsecount has been selected */ - - if (info->count > 0) - { - /* Only the advanced timers (TIM1,8 can support the pulse counting) */ - - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - /* Save the handle */ - - priv->handle = handle; - - /* Start the time */ - - return stm32pulsecount_timer(priv, info); -} - -/**************************************************************************** - * Name: stm32pulsecount_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - uint32_t resetbit; - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - _info("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - stm32pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif - - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32pulsecount_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32pulsecount_dumpregs(priv, "After stop"); - return OK; -} - -/**************************************************************************** - * Name: stm32pulsecount_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int stm32pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_pulsecounttimer_s *priv = - (struct stm32_pulsecounttimer_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pulsecountinitialize - * - * Description: - * Initialize one timer for use with the upper-level pulsecount driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family. This pulsecount driver - * supports TIM1 only on STM32F0/L0/G0. - * - * Returned Value: - * On success, a pointer to the STM32 lower half pulsecount driver is - * returned. NULL is returned on any failure. - * - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecounttimer_s *lower; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - lower = &g_pulsecount1dev; - - /* Attach but disable the TIM1 update interrupt */ - - irq_attach(lower->irq, stm32pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->irq); - break; -#endif - - default: - _err("ERROR: No such timer configured\n"); - return NULL; - } - - return (struct pulsecount_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32_TIMx_PULSECOUNT */ diff --git a/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c deleted file mode 100644 index d73a83d002294..0000000000000 --- a/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c +++ /dev/null @@ -1,1775 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_pulsecount.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the pulsecount upper half driver. - * - * It implements support for both: - * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 - * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Definitions ********************************************************/ - -/* Pulsecount is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 5 -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED - -/* Advanced timer clock source, RCC EN offset, enable bit, - * RCC RST offset, reset bit to use - */ - -# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -/* Default GPIO pins state */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32L15XX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) -#else -# error "Unrecognized STM32 chip" -#endif - -#define PULSECOUNT_POL_NEG 1 -#define PULSECOUNT_IDLE_ACTIVE 1 - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Pulsecount output configuration */ - -struct stm32_out_s -{ - uint8_t in_use:1; - uint8_t pol:1; - uint8_t idle:1; - uint8_t _res:5; - uint32_t pincfg; -}; - -/* Pulsecount channel configuration */ - -struct stm32_chan_s -{ - uint8_t channel; - struct stm32_out_s out1; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_tim_s -{ - struct stm32_chan_s channel; - uint8_t timid:5; - uint8_t timtype:3; - uint8_t t_dts:3; - uint8_t _res:5; - uint8_t irq; - uint8_t prev; - uint8_t curr; - uint32_t count; - uint32_t frequency; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -struct stm32_pulsecount_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_tim_s *timer; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value); -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg); -#else -# define pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty); -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency); -static int pulsecount_timer_configure(struct stm32_tim_s *priv); -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel); -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan); -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state); -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable); -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info); -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg); -# endif -# ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg); -# endif -static uint8_t pulsecount_count(uint32_t count); - -/* Pulsecount driver methods */ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -static struct stm32_tim_s g_pulsecount1dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH1OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH2OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH3OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH4OUT, - }, -#endif - }, - .timid = 1, - .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1UP, - .base = STM32_TIM1_BASE, - .pclk = TIMCLK_TIM1, -}; - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - -static struct stm32_tim_s g_pulsecount8dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH1OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH2OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH3OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH4OUT, - }, -#endif - }, - .timid = 8, - .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8UP, - .base = STM32_TIM8_BASE, - .pclk = TIMCLK_TIM8, -}; - -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = pulsecount_setup, - .shutdown = pulsecount_shutdown, - .start = pulsecount_start, - .stop = pulsecount_stop, - .ioctl = pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount1lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount1dev, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount8lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount8dev, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pulsecount_reg_is_32bit - ****************************************************************************/ - -static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - bool ret = false; - - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET) - { - ret = true; - } - } - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) -{ - uint32_t retval = 0; - - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); - } -} - -/**************************************************************************** - * Name: pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - - if (priv->timid == 1 || priv->timid == 8) - { - _info(" RCR: %04x BDTR: %04x\n", - pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET)); - } - - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - - _info(" DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DMAR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: pulsecount_ccr_update - ****************************************************************************/ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t offset = 0; - - /* CCR channel indices are one-based to match timer channel numbers. */ - - switch (index) - { - case 1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case 2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case 3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case 4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - - default: - { - _err("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pulsecount_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - _info("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - return pulsecount_ccr_update(dev, channel, ccr); -} - -/**************************************************************************** - * Name: pulsecount_frequency_update - * - * Description: - * Update a pulsecount timer frequency - * - ****************************************************************************/ - -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32" frequency: %" PRIu32 - " TIMCLK: %" PRIu32 " " - "prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_timer_configure - * - * Description: - * Initial configuration for pulsecount timer - * - ****************************************************************************/ - -static int pulsecount_timer_configure(struct stm32_tim_s *priv) -{ - uint16_t cr1 = 0; - - /* Set up the advanced timer CR1 register. */ - - cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Pulsecount always uses edge-aligned up-counting mode. */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; - cr1 &= ~GTIM_CR1_CKD_MASK; - cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; - - /* Enable ARR preload to preserve the previous pulsecount behavior. */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_channel_configure - * - * Description: - * Configure pulsecount output compare for a channel - * - ****************************************************************************/ - -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; - - /* Configure output compare mode */ - - chanmode = GTIM_CCMR_MODE_PWM1; - - /* Get CCMR offset */ - - switch (channel) - { - case 1: - case 2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case 3: - case 4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - - default: - { - _err("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pulsecount_getreg(priv, offset); - - /* output compare configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3 */ - - case 1: - case 3: - { - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - ocmode |= ATIM_CCMR1_OC1PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC1M); -#endif - break; - } - - /* Configure channel 2/4 */ - - case 2: - case 4: - { - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - ocmode |= ATIM_CCMR1_OC2PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC2M); -#endif - break; - } - } - - /* Set the selected output compare configuration */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pulsecount_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - ****************************************************************************/ - -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - uint8_t channel = 0; - - /* Get channel */ - - channel = chan->channel; - - /* Get current registers state */ - - cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx | IDLE | advanced timers | CR2 register - * | CCxP | POL | all pulsecount timers | CCER register - */ - - /* Configure output polarity (all pulsecount timers) */ - - if (chan->out1.pol == PULSECOUNT_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* Configure output IDLE State */ - - if (chan->out1.idle == PULSECOUNT_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - } - - /* Write registers */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_outputs_enable - * - * Description: - * Enable/disable given timer pulsecount outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_moe_enable - ****************************************************************************/ - -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - if (enable) - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - else - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } -} - -/**************************************************************************** - * Name: pulsecount_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the pulsecount timer state - * - ****************************************************************************/ - -static uint16_t -pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) -{ - uint16_t outputs = 0; - uint8_t channel; - - channel = priv->channel.channel; - - if (channel != 0 && (selected == 0 || channel == selected) && - priv->channel.out1.in_use == 1) - { - outputs = (1 << ((channel - 1) * 2)); - } - - return outputs; -} - -/**************************************************************************** - * Name: pulsecount_configure - * - * Description: - * Configure pulsecount timer in PULSECOUNT mode - * - ****************************************************************************/ - -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Disable the timer until we get it configured */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, 0); - - /* Disable configured outputs before the timer is reconfigured. */ - - ret = pulsecount_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Initial timer configuration */ - - ret = pulsecount_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Disable software break (enable outputs) */ - - pulsecount_moe_enable(dev, true); - - /* Configure timer channels */ - - if (priv->channel.channel != 0) - { - pulsecount_channel_configure(dev, priv->channel.channel); - pulsecount_output_configure(priv, &priv->channel); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * This split keeps pulsecount as the existing single-channel mode. - * - ****************************************************************************/ - -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - ub16_t duty = 0; - uint8_t channel = 0; - uint16_t outputs = 0; - int ret = OK; - - /* If we got here then the timer instance supports pulsecount output. */ - - DEBUGASSERT(priv != NULL && info != NULL); - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Channel specific setup */ - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Disable all interrupts and DMA requests, clear all pending status */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Set timer frequency */ - - ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); - if (ret < 0) - { - goto errout; - } - - /* Update duty cycle */ - - ret = pulsecount_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pulsecount_start() has already - * assured us that the count value is within range). - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, channel); - - /* Enable output */ - - ret = pulsecount_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - - pulsecount_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the master output to stop the output as - * quickly as possible. - */ - - pulsecount_moe_enable(dev, false); - - /* Disable first interrupts, stop and reset the timer */ - - pulsecount_ll_stop(dev); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output. - */ - - _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" - " count: %" PRIu32 "\n", - regval, (unsigned int)priv->prev, (unsigned int)priv->curr, - priv->count); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount1dev); -} -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount8dev); -} -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -/**************************************************************************** - * Name: pulsecount_count - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint8_t pulsecount_count(uint32_t count) -{ - /* Use the advanced-timer repetition counter limit. */ - - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return (uint8_t)count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return (uint8_t)ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: pulsecount_set_apb_clock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) -{ - uint32_t en_bit = 0; - uint32_t regaddr = 0; - int ret = OK; - - _info("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCEN_TIM1; - en_bit = TIMEN_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCEN_TIM8; - en_bit = TIMEN_TIM8; - break; - } -#endif - - default: - { - _err("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - _info("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", - regaddr, en_bit); - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, true); - if (ret < 0) - { - goto errout; - } - - pulsecount_dumpregs(dev, "Initially"); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - if (priv->channel.out1.in_use == 1) - { - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pulsecount_ll_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - irqstate_t flags = 0; - uint16_t outputs = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Stopped so frequency is zero */ - - priv->frequency = 0; - - /* Disable further interrupts and stop the timer */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Disable the timer and timer outputs */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - outputs = pulsecount_outputs_from_channels(priv, 0); - ret = pulsecount_outputs_enable(dev, outputs, false); - - /* Clear all channels */ - - pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); - - leave_critical_section(flags); - - pulsecount_dumpregs(dev, "After stop"); - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - int ret; - - ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); - if (ret < 0) - { - return ret; - } - - return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) - pulse->timer); -} - -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - struct stm32_tim_s *priv = pulse->timer; - - /* Check if a pulsecount has been selected */ - - if (info->count > 0) - { - /* Only the advanced timers (TIM1,8 can support the pulse counting) - */ - - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - /* Save the handle */ - - priv->handle = handle; - - /* Start the time */ - - return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); -} - -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, - cmd, arg); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecount_s *lower = NULL; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - lower = &g_pulsecount1lower; - irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - lower = &g_pulsecount8lower; - irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - - default: - { - _err("ERROR: TIM%d does not support pulse count\n", timer); - return NULL; - } - } - - return (struct pulsecount_lowerhalf_s *)lower; -} diff --git a/arch/arm/src/stm32c0/stm32.h b/arch/arm/src/stm32c0/stm32.h index 7d1c5ae34764f..b12ea4f456513 100644 --- a/arch/arm/src/stm32c0/stm32.h +++ b/arch/arm/src/stm32c0/stm32.h @@ -43,6 +43,7 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" +#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f0/stm32.h b/arch/arm/src/stm32f0/stm32.h index fabdd48a6255b..bd3ce82e9d74e 100644 --- a/arch/arm/src/stm32f0/stm32.h +++ b/arch/arm/src/stm32f0/stm32.h @@ -43,6 +43,7 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" +#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index bc870799cdd66..94d52db4e7854 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -184,10 +184,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 9a6d59e952187..a3a7082a0c898 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -185,10 +185,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - ifeq ($(CONFIG_STM32_FOC),y) CHIP_CSRCS += stm32_foc.c endif diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.h b/arch/arm/src/stm32f7/stm32_pulsecount.h deleted file mode 100644 index 7261a99c491e4..0000000000000 --- a/arch/arm/src/stm32f7/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h index 9e70f1bf95f02..243e25e7d3915 100644 --- a/arch/arm/src/stm32g0/stm32.h +++ b/arch/arm/src/stm32g0/stm32.h @@ -43,6 +43,7 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" +#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index f413964d7b898..249a64c3136a3 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -115,10 +115,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - # Required chip type specific files if(CONFIG_STM32_STM32H5XXXX) diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index ec8db4beccfab..fd569978cb47f 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -112,10 +112,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - # Required chip type specific files ifeq ($(CONFIG_STM32_STM32H5XXXX),y) diff --git a/arch/arm/src/stm32h5/stm32.h b/arch/arm/src/stm32h5/stm32.h index 7011cf4f5d2ee..25d810170aae5 100644 --- a/arch/arm/src/stm32h5/stm32.h +++ b/arch/arm/src/stm32h5/stm32.h @@ -47,6 +47,7 @@ #include "stm32_lowputc.h" #include "stm32_pwr.h" #include "stm32_rcc.h" +#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_usbfs.h" diff --git a/arch/arm/src/stm32h5/stm32_pulsecount.c b/arch/arm/src/stm32h5/stm32_pulsecount.c deleted file mode 100644 index d002444cd7a5a..0000000000000 --- a/arch/arm/src/stm32h5/stm32_pulsecount.c +++ /dev/null @@ -1,1792 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_pulsecount.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_pulsecount.h" -#include "stm32.h" -#include "stm32_tim.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the pulsecount upper half driver. - * - * It implements support for both: - * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 - * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+, H5 - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Definitions ********************************************************/ - -/* Pulsecount is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 5 -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED - -/* Advanced timer clock source, RCC EN offset, enable bit, - * RCC RST offset, reset bit to use - */ - -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN -#define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -#define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -#define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -#define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN -#define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -#define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -#define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -#define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -/* Default GPIO pins state */ - -#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) - -/* Synchronisation support */ - -#define PULSECOUNT_POL_NEG 1 -#define PULSECOUNT_IDLE_ACTIVE 1 - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Pulsecount output configuration */ - -struct stm32_out_s -{ - uint8_t in_use:1; - uint8_t pol:1; - uint8_t idle:1; - uint8_t _res:5; - uint32_t pincfg; -}; - -/* Pulsecount channel configuration */ - -struct stm32_chan_s -{ - uint8_t channel; - struct stm32_out_s out1; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_tim_s -{ - struct stm32_chan_s channel; - uint8_t timid:5; - uint8_t timtype:3; - uint8_t t_dts:3; - uint8_t _res:5; - uint8_t irq; - uint8_t prev; - uint8_t curr; - uint32_t count; - uint32_t frequency; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -struct stm32_pulsecount_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_tim_s *timer; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value); -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg); -#else -# define pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty); -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency); -static int pulsecount_timer_configure(struct stm32_tim_s *priv); -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel); -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan); -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state); -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable); -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info); -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg); -# endif -# ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg); -# endif -static uint8_t pulsecount_count(uint32_t count); - -/* Pulsecount driver methods */ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -static struct stm32_tim_s g_pulsecount1dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH1OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH2OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH3OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH4OUT, - }, -#endif - }, - .timid = 1, - .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1_UP, - .base = STM32_TIM1_BASE, - .pclk = TIMCLK_TIM1, -}; - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - -static struct stm32_tim_s g_pulsecount8dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH1OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH2OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH3OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH4OUT, - }, -#endif - }, - .timid = 8, - .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8_UP, - .base = STM32_TIM8_BASE, - .pclk = TIMCLK_TIM8, -}; - -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = pulsecount_setup, - .shutdown = pulsecount_shutdown, - .start = pulsecount_start, - .stop = pulsecount_stop, - .ioctl = pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount1lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount1dev, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount8lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount8dev, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pulsecount_reg_is_32bit - ****************************************************************************/ - -static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - bool ret = false; - - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET) - { - ret = true; - } - } - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) -{ - uint32_t retval = 0; - - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); - } -} - -/**************************************************************************** - * Name: pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - - if (priv->timid == 1 || priv->timid == 8) - { - _info(" RCR: %04x BDTR: %04x\n", - pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET)); - } - - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - - _info(" DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DMAR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: pulsecount_ccr_update - ****************************************************************************/ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t offset = 0; - - switch (index) - { - case 1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case 2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case 3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case 4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - - default: - { - _err("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pulsecount_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - _info("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - return pulsecount_ccr_update(dev, channel, ccr); -} - -/**************************************************************************** - * Name: pulsecount_frequency_update - * - * Description: - * Update a pulsecount timer frequency - * - ****************************************************************************/ - -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 - " TIMCLK: %" PRIu32 - " prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_timer_configure - * - * Description: - * Initial configuration for pulsecount timer - * - ****************************************************************************/ - -static int pulsecount_timer_configure(struct stm32_tim_s *priv) -{ - uint16_t cr1 = 0; - - /* Set up the advanced timer CR1 register. */ - - cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Pulsecount always uses edge-aligned up-counting mode. */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; - cr1 &= ~GTIM_CR1_CKD_MASK; - cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; - - /* Enable ARR preload to preserve the previous pulsecount behavior. */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_channel_configure - * - * Description: - * Configure pulsecount output compare for a channel - * - ****************************************************************************/ - -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; - - /* Configure output compare mode */ - - chanmode = GTIM_CCMR_MODE_PWM1; - - /* Get CCMR offset */ - - switch (channel) - { - case 1: - case 2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case 3: - case 4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - - default: - { - _err("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pulsecount_getreg(priv, offset); - - /* output compare configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3 */ - - case 1: - case 3: - { - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - ocmode |= ATIM_CCMR1_OC1PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC1M); -#endif - break; - } - - /* Configure channel 2/4 */ - - case 2: - case 4: - { - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - ocmode |= ATIM_CCMR1_OC2PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC2M); -#endif - break; - } - } - - /* Set the selected output compare configuration */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pulsecount_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - ****************************************************************************/ - -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - uint8_t channel = 0; - - /* Get channel */ - - channel = chan->channel; - - /* Get current registers state */ - - cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx | IDLE | advanced timers | CR2 register - * | CCxP | POL | all pulsecount timers | CCER register - */ - - /* Configure output polarity (all pulsecount timers) */ - - if (chan->out1.pol == PULSECOUNT_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* Configure output IDLE State */ - - if (chan->out1.idle == PULSECOUNT_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - } - - /* Write registers */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_outputs_enable - * - * Description: - * Enable/disable given timer pulsecount outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_moe_enable - ****************************************************************************/ - -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - if (enable) - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - else - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } -} - -/**************************************************************************** - * Name: pulsecount_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the pulsecount timer state - * - ****************************************************************************/ - -static uint16_t -pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) -{ - uint16_t outputs = 0; - uint8_t channel; - - channel = priv->channel.channel; - - if (channel != 0 && (selected == 0 || channel == selected) && - priv->channel.out1.in_use == 1) - { - outputs = (1 << ((channel - 1) * 2)); - } - - return outputs; -} - -/**************************************************************************** - * Name: pulsecount_configure - * - * Description: - * Configure pulsecount timer in PULSECOUNT mode - * - ****************************************************************************/ - -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - UNUSED(priv); - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Disable the timer until we get it configured */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, 0); - - /* Disable configured outputs before the timer is reconfigured. */ - - ret = pulsecount_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Initial timer configuration */ - - ret = pulsecount_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Disable software break (enable outputs) */ - - pulsecount_moe_enable(dev, true); - - /* Configure timer channels */ - - if (priv->channel.channel != 0) - { - pulsecount_channel_configure(dev, priv->channel.channel); - pulsecount_output_configure(priv, &priv->channel); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * This split keeps pulsecount as the existing single-channel mode. - * - ****************************************************************************/ - -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - ub16_t duty = 0; - uint8_t channel = 0; - uint16_t outputs = 0; - int ret = OK; - - /* If we got here then the timer instance supports pulsecount output. */ - - DEBUGASSERT(priv != NULL && info != NULL); - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Channel specific setup */ - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Disable all interrupts and DMA requests, clear all pending status */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Set timer frequency */ - - ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); - if (ret < 0) - { - goto errout; - } - - /* Update duty cycle */ - - ret = pulsecount_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pulsecount_start() has already - * assured us that the count value is within range). - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, channel); - - /* Enable output */ - - ret = pulsecount_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - - pulsecount_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the master output to stop the output as - * quickly as possible. - */ - - pulsecount_moe_enable(dev, false); - - /* Disable first interrupts, stop and reset the timer */ - - pulsecount_ll_stop(dev); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output. - */ - - _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" - " count: %" PRIu32 "\n", - regval, (unsigned int)priv->prev, (unsigned int)priv->curr, - priv->count); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount1dev); -} -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount8dev); -} -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -/**************************************************************************** - * Name: pulsecount_count - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint8_t pulsecount_count(uint32_t count) -{ - /* Use the advanced-timer repetition counter limit. */ - - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return (uint8_t)count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return (uint8_t)ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: pulsecount_set_apb_clock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) -{ - uint32_t en_bit = 0; - uint32_t regaddr = 0; - int ret = OK; - - _info("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCEN_TIM1; - en_bit = TIMEN_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCEN_TIM8; - en_bit = TIMEN_TIM8; - break; - } -#endif - - default: - { - _err("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - _info("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", - regaddr, en_bit); - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, true); - if (ret < 0) - { - goto errout; - } - - pulsecount_dumpregs(dev, "Initially"); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - if (priv->channel.out1.in_use == 1) - { - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pulsecount_ll_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - irqstate_t flags = 0; - uint32_t resetbit = 0; - uint32_t regaddr = 0; - uint32_t regval = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCRST_TIM1; - resetbit = TIMRST_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCRST_TIM8; - resetbit = TIMRST_TIM8; - break; - } -#endif - - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Reset the timer - stopping the output and putting the timer back - * into a state where pulsecount_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - - /* Clear all channels */ - - pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); - - leave_critical_section(flags); - - _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - pulsecount_dumpregs(dev, "After stop"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - int ret; - - ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); - if (ret < 0) - { - return ret; - } - - return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) - pulse->timer); -} - -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - struct stm32_tim_s *priv = pulse->timer; - - if (info->count > 0) - { - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - priv->handle = handle; - return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); -} - -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, - cmd, arg); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecount_s *lower = NULL; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - lower = &g_pulsecount1lower; - irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - lower = &g_pulsecount8lower; - irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - - default: - { - _err("ERROR: TIM%d does not support pulse count\n", timer); - return NULL; - } - } - - return (struct pulsecount_lowerhalf_s *)lower; -} diff --git a/arch/arm/src/stm32h5/stm32_pulsecount.h b/arch/arm/src/stm32h5/stm32_pulsecount.h deleted file mode 100644 index e236340ff6265..0000000000000 --- a/arch/arm/src/stm32h5/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 5f6e1f9800f86..7965169017968 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -184,10 +184,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 298f6da5b5c62..e1f6fd958b949 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -183,10 +183,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif diff --git a/arch/arm/src/stm32h7/stm32.h b/arch/arm/src/stm32h7/stm32.h index fa614de2da3d9..a6d99c1774357 100644 --- a/arch/arm/src/stm32h7/stm32.h +++ b/arch/arm/src/stm32h7/stm32.h @@ -43,6 +43,7 @@ #include "stm32_i2c.h" #include "stm32_spi.h" #include "stm32_rcc.h" +#include "stm32_tim.h" #include "stm32_lowputc.h" #endif /* __ARCH_ARM_SRC_STM32H7_STM32_H */ diff --git a/arch/arm/src/stm32h7/stm32_pulsecount.c b/arch/arm/src/stm32h7/stm32_pulsecount.c deleted file mode 100644 index b963fbf02cd4c..0000000000000 --- a/arch/arm/src/stm32h7/stm32_pulsecount.c +++ /dev/null @@ -1,1813 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_pulsecount.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_pulsecount.h" -#include "stm32.h" -#include "stm32_tim.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the pulsecount upper half driver. - * - * It implements support for both: - * 1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1 - * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ - */ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Definitions ********************************************************/ - -/* Pulsecount is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 5 -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED - -/* Advanced timer clock source, RCC EN offset, enable bit, - * RCC RST offset, reset bit to use - */ - -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN -#define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -#define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -#define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -#define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN -#define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -#define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -#define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -#define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -/* Default GPIO pins state */ - -#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT) - -/* Advanced timer support */ - -# if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) -# endif - -/* Synchronisation support */ - -#define PULSECOUNT_POL_NEG 1 -#define PULSECOUNT_IDLE_ACTIVE 1 - -#ifndef STM32_GTIM_RCR_OFFSET -# define STM32_GTIM_RCR_OFFSET STM32_ATIM_RCR_OFFSET -#endif - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Pulsecount output configuration */ - -struct stm32_out_s -{ - uint8_t in_use:1; - uint8_t pol:1; - uint8_t idle:1; - uint8_t _res:5; - uint32_t pincfg; -}; - -/* Pulsecount channel configuration */ - -struct stm32_chan_s -{ - uint8_t channel; - struct stm32_out_s out1; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_tim_s -{ - struct stm32_chan_s channel; - uint8_t timid:5; - uint8_t timtype:3; - uint8_t t_dts:3; - uint8_t _res:5; - uint8_t irq; - uint8_t prev; - uint8_t curr; - uint32_t count; - uint32_t frequency; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -struct stm32_pulsecount_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_tim_s *timer; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value); -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg); -#else -# define pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty); -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency); -static int pulsecount_timer_configure(struct stm32_tim_s *priv); -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel); -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan); -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state); -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable); -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info); -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg); -# endif -# ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg); -# endif -static uint8_t pulsecount_count(uint32_t count); - -/* Pulsecount driver methods */ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -static struct stm32_tim_s g_pulsecount1dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH1OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH2OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH3OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH4OUT, - }, -#endif - }, - .timid = 1, - .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1UP, - .base = STM32_TIM1_BASE, - .pclk = TIMCLK_TIM1, -}; - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - -static struct stm32_tim_s g_pulsecount8dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH1OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH2OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH3OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH4OUT, - }, -#endif - }, - .timid = 8, - .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8UP, - .base = STM32_TIM8_BASE, - .pclk = TIMCLK_TIM8, -}; - -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = pulsecount_setup, - .shutdown = pulsecount_shutdown, - .start = pulsecount_start, - .stop = pulsecount_stop, - .ioctl = pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount1lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount1dev, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount8lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount8dev, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pulsecount_reg_is_32bit - ****************************************************************************/ - -static bool pulsecount_reg_is_32bit(uint8_t timtype, uint32_t offset) -{ - bool ret = false; - - if (timtype == TIMTYPE_ADVANCED) - { - if (offset == STM32_ATIM_CR2_OFFSET || - offset == STM32_ATIM_CCMR1_OFFSET || - offset == STM32_ATIM_CCMR2_OFFSET || - offset == STM32_ATIM_CCER_OFFSET || - offset == STM32_ATIM_BDTR_OFFSET) - { - ret = true; - } - } - - return ret; -} - -/**************************************************************************** - * Name: pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) -{ - uint32_t retval = 0; - - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - retval = getreg32(priv->base + offset); - } - else - { - /* 16-bit register */ - - retval = getreg16(priv->base + offset); - } - - /* Return 32-bit value */ - - return retval; -} - -/**************************************************************************** - * Name: pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint32_t value) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - putreg32(value, priv->base + offset); - } - else - { - /* 16-bit register */ - - putreg16((uint16_t)value, priv->base + offset); - } -} - -/**************************************************************************** - * Name: pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - if (pulsecount_reg_is_32bit(priv->timtype, offset) == true) - { - /* 32-bit register */ - - modifyreg32(priv->base + offset, clearbits, setbits); - } - else - { - /* 16-bit register */ - - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); - } -} - -/**************************************************************************** - * Name: pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - - if (priv->timid == 1 || priv->timid == 8) - { - _info(" RCR: %04x BDTR: %04x\n", - pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET)); - } - - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - - _info(" DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DMAR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: pulsecount_ccr_update - ****************************************************************************/ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t offset = 0; - - /* CCR channel indices are one-based to match timer channel numbers. */ - - switch (index) - { - case 1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case 2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case 3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case 4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - - default: - { - _err("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pulsecount_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - _info("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - return pulsecount_ccr_update(dev, channel, ccr); -} - -/**************************************************************************** - * Name: pulsecount_frequency_update - * - * Description: - * Update a pulsecount timer frequency - * - ****************************************************************************/ - -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 - " TIMCLK: %" PRIu32 - " prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_timer_configure - * - * Description: - * Initial configuration for pulsecount timer - * - ****************************************************************************/ - -static int pulsecount_timer_configure(struct stm32_tim_s *priv) -{ - uint16_t cr1 = 0; - - /* Set up the advanced timer CR1 register. */ - - cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Pulsecount always uses edge-aligned up-counting mode. */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; - cr1 &= ~GTIM_CR1_CKD_MASK; - cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; - - /* Enable ARR preload to preserve the previous pulsecount behavior. */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_channel_configure - * - * Description: - * Configure pulsecount output compare for a channel - * - ****************************************************************************/ - -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; - - /* Configure output compare mode */ - - chanmode = GTIM_CCMR_MODE_PWM1; - - /* Get CCMR offset */ - - switch (channel) - { - case 1: - case 2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case 3: - case 4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - - default: - { - _err("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pulsecount_getreg(priv, offset); - - /* output compare configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3 */ - - case 1: - case 3: - { - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - ocmode |= ATIM_CCMR1_OC1PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC1M); -#endif - break; - } - - /* Configure channel 2/4 */ - - case 2: - case 4: - { - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - ocmode |= ATIM_CCMR1_OC2PE; -#ifdef HAVE_IP_TIMERS_V2 - ccmr &= ~(ATIM_CCMR1_OC2M); -#endif - break; - } - } - - /* Set the selected output compare configuration */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pulsecount_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - ****************************************************************************/ - -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - uint8_t channel = 0; - - /* Get channel */ - - channel = chan->channel; - - /* Get current registers state */ - - cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx | IDLE | advanced timers | CR2 register - * | CCxP | POL | all pulsecount timers | CCER register - */ - - /* Configure output polarity (all pulsecount timers) */ - - if (chan->out1.pol == PULSECOUNT_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* Configure output IDLE State */ - - if (chan->out1.idle == PULSECOUNT_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - } - - /* Write registers */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_outputs_enable - * - * Description: - * Enable/disable given timer pulsecount outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_moe_enable - ****************************************************************************/ - -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - if (enable) - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - else - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } -} - -/**************************************************************************** - * Name: pulsecount_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the pulsecount timer state - * - ****************************************************************************/ - -static uint16_t -pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) -{ - uint16_t outputs = 0; - uint8_t channel; - - channel = priv->channel.channel; - - if (channel != 0 && (selected == 0 || channel == selected) && - priv->channel.out1.in_use == 1) - { - outputs = (1 << ((channel - 1) * 2)); - } - - return outputs; -} - -/**************************************************************************** - * Name: pulsecount_configure - * - * Description: - * Configure pulsecount timer in PULSECOUNT mode - * - ****************************************************************************/ - -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - UNUSED(priv); - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Disable the timer until we get it configured */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, 0); - - /* Disable configured outputs before the timer is reconfigured. */ - - ret = pulsecount_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Initial timer configuration */ - - ret = pulsecount_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Disable software break (enable outputs) */ - - pulsecount_moe_enable(dev, true); - - /* Configure timer channels */ - - if (priv->channel.channel != 0) - { - pulsecount_channel_configure(dev, priv->channel.channel); - pulsecount_output_configure(priv, &priv->channel); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * This split keeps pulsecount as the existing single-channel mode. - * - ****************************************************************************/ - -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - ub16_t duty = 0; - uint8_t channel = 0; - uint16_t outputs = 0; - int ret = OK; - - /* If we got here then the timer instance supports pulsecount output. */ - - DEBUGASSERT(priv != NULL && info != NULL); - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Channel specific setup */ - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Disable all interrupts and DMA requests, clear all pending status */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Set timer frequency */ - - ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); - if (ret < 0) - { - goto errout; - } - - /* Update duty cycle */ - - ret = pulsecount_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pulsecount_start() has already - * assured us that the count value is within range). - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, channel); - - /* Enable output */ - - ret = pulsecount_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - - pulsecount_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF)); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the master output to stop the output as - * quickly as possible. - */ - - pulsecount_moe_enable(dev, false); - - /* Disable first interrupts, stop and reset the timer */ - - pulsecount_ll_stop(dev); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output. - */ - - _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" - " count: %" PRIu32 "\n", - regval, (unsigned int)priv->prev, (unsigned int)priv->curr, - priv->count); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount1dev); -} -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount8dev); -} -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -/**************************************************************************** - * Name: pulsecount_count - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint8_t pulsecount_count(uint32_t count) -{ - /* Use the advanced-timer repetition counter limit. */ - - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return (uint8_t)count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return (uint8_t)ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: pulsecount_set_apb_clock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) -{ - uint32_t en_bit = 0; - uint32_t regaddr = 0; - int ret = OK; - - _info("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0); - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCEN_TIM1; - en_bit = TIMEN_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCEN_TIM8; - en_bit = TIMEN_TIM8; - break; - } -#endif - - default: - { - _err("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - _info("RCC_APBxENR base: %08" PRIx32 " bits: %04" PRIx32 "\n", - regaddr, en_bit); - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, true); - if (ret < 0) - { - goto errout; - } - - pulsecount_dumpregs(dev, "Initially"); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - if (priv->channel.out1.in_use == 1) - { - /* Do not configure the pin if pincfg is not specified. - * This prevents overwriting the PA0 configuration if the - * channel is used internally. - */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - } - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pulsecount_ll_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pulsecount_set_apb_clock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= PINCFG_DEFAULT; - - stm32_configgpio(pincfg); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - irqstate_t flags = 0; - uint32_t resetbit = 0; - uint32_t regaddr = 0; - uint32_t regval = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = TIMRCCRST_TIM1; - resetbit = TIMRST_TIM1; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = TIMRCCRST_TIM8; - resetbit = TIMRST_TIM8; - break; - } -#endif - - default: - { - ret = -EINVAL; - goto errout; - } - } - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Reset the timer - stopping the output and putting the timer back - * into a state where pulsecount_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - - /* Clear all channels */ - - pulsecount_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); - - leave_critical_section(flags); - - _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - pulsecount_dumpregs(dev, "After stop"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - int ret; - - ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); - if (ret < 0) - { - return ret; - } - - return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) - pulse->timer); -} - -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - struct stm32_tim_s *priv = pulse->timer; - - /* Check if a pulsecount has been selected */ - - if (info->count > 0) - { - /* Only the advanced timers (TIM1,8 can support the pulse counting) - */ - - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - /* Save the handle */ - - priv->handle = handle; - - /* Start the time */ - - return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); -} - -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, - cmd, arg); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecount_s *lower = NULL; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - lower = &g_pulsecount1lower; - irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - lower = &g_pulsecount8lower; - irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - - default: - { - _err("ERROR: TIM%d does not support pulse count\n", timer); - return NULL; - } - } - - return (struct pulsecount_lowerhalf_s *)lower; -} diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h index cdcdb2d4aa714..5b77af6b01b83 100644 --- a/arch/arm/src/stm32l0/stm32.h +++ b/arch/arm/src/stm32l0/stm32.h @@ -43,6 +43,7 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" +#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 9ea2ec8809a94..0d2406e409557 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -162,10 +162,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32l4_pulsecount.c) -endif() - if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32l4_qencoder.c) endif() diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 8149af37b753f..d62701c5fc459 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -158,10 +158,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32l4_pulsecount.c -endif - ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32l4_qencoder.c endif diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c deleted file mode 100644 index 14704082eb707..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ /dev/null @@ -1,1657 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_pulsecount.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32l4_pulsecount.h" -#include "stm32.h" -#include "stm32l4_tim.h" - -/* This module then only compiles if there is at least one enabled timer - * intended for use with the pulsecount upper half driver. - */ - -#if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer Definitions ********************************************************/ - -/* Pulsecount is supported by advanced timers only. */ - -#define TIMTYPE_ADVANCED 5 -#define TIMTYPE_TIM1 TIMTYPE_ADVANCED -#define TIMTYPE_TIM8 TIMTYPE_ADVANCED - -#define PULSECOUNT_POL_NEG 1 -#define PULSECOUNT_IDLE_ACTIVE 1 - -/* Debug ********************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) -#else -# define pulsecount_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Pulsecount output configuration */ - -struct stm32_out_s -{ - uint8_t in_use:1; - uint8_t pol:1; - uint8_t idle:1; - uint8_t _res:5; - uint32_t pincfg; -}; - -/* Pulsecount channel configuration */ - -struct stm32_chan_s -{ - uint8_t channel; - struct stm32_out_s out1; -}; - -/* This structure represents the state of one pulsecount timer */ - -struct stm32_tim_s -{ - struct stm32_chan_s channel; - uint8_t timid:5; - uint8_t timtype:3; - uint8_t t_dts:3; - uint8_t _res:5; - uint8_t irq; - uint8_t prev; - uint8_t curr; - uint32_t count; - uint32_t frequency; - uint32_t base; - uint32_t pclk; - void *handle; -}; - -struct stm32_pulsecount_s -{ - const struct pulsecount_ops_s *ops; - struct stm32_tim_s *timer; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Register access */ - -static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint16_t value); -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits); - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg); -#else -# define pulsecount_dumpregs(priv,msg) -#endif - -/* Timer management */ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr); -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty); -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency); -static int pulsecount_timer_configure(struct stm32_tim_s *priv); -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel); -static int pulsecount_output_configure(struct stm32_tim_s *priv, - struct stm32_chan_s *chan); -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state); -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable); -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info); -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg); -# endif -# ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg); -# endif -static uint8_t pulsecount_count(uint32_t count); - -/* Pulsecount driver methods */ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev); - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle); -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev); -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - -static struct stm32_tim_s g_pulsecount1dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH1OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH2OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH3OUT, - }, -#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM1_CH4OUT, - }, -#endif - }, - .timid = 1, - .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM1UP, - .base = STM32_TIM1_BASE, - .pclk = STM32_APB2_TIM1_CLKIN, -}; - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - -static struct stm32_tim_s g_pulsecount8dev = -{ - .channel = - { - .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH1OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH2OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH3OUT, - }, -#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 - .out1 = - { - .in_use = 1, - .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, - .pincfg = GPIO_TIM8_CH4OUT, - }, -#endif - }, - .timid = 8, - .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = STM32_IRQ_TIM8UP, - .base = STM32_TIM8_BASE, - .pclk = STM32_APB2_TIM8_CLKIN, -}; - -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -static const struct pulsecount_ops_s g_pulsecountops = -{ - .setup = pulsecount_setup, - .shutdown = pulsecount_shutdown, - .start = pulsecount_start, - .stop = pulsecount_stop, - .ioctl = pulsecount_ioctl, -}; - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount1lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount1dev, -}; -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static struct stm32_pulsecount_s g_pulsecount8lower = -{ - .ops = &g_pulsecountops, - .timer = &g_pulsecount8dev, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pulsecount_getreg - * - * Description: - * Read the value of an pulsecount timer register. - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) -{ - return getreg16(priv->base + offset); -} - -/**************************************************************************** - * Name: pulsecount_putreg - * - * Description: - * Read the value of an pulsecount timer register. - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->base + offset); -} - -/**************************************************************************** - * Name: pulsecount_modifyreg - * - * Description: - * Modify timer register (32-bit or 16-bit) - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * offset - The offset to the register to read - * clrbits - The bits to clear - * setbits - The bits to set - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, - uint32_t clearbits, uint32_t setbits) -{ - modifyreg16(priv->base + offset, (uint16_t)clearbits, - (uint16_t)setbits); -} - -/**************************************************************************** - * Name: pulsecount_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the pulsecount block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_TIMER_INFO -static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, - const char *msg) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - _info("%s:\n", msg); - _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); - _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); - _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); - _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); -} -#endif - -/**************************************************************************** - * Name: pulsecount_ccr_update - ****************************************************************************/ - -static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, - uint8_t index, uint32_t ccr) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t offset = 0; - - /* CCR channel indices are one-based to match timer channel numbers. */ - - switch (index) - { - case 1: - { - offset = STM32_GTIM_CCR1_OFFSET; - break; - } - - case 2: - { - offset = STM32_GTIM_CCR2_OFFSET; - break; - } - - case 3: - { - offset = STM32_GTIM_CCR3_OFFSET; - break; - } - - case 4: - { - offset = STM32_GTIM_CCR4_OFFSET; - break; - } - - default: - { - _err("ERROR: No such CCR: %u\n", index); - return -EINVAL; - } - } - - /* Update CCR register */ - - pulsecount_putreg(priv, offset, ccr); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_duty_update - * - * Description: - * Try to change only channel duty - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * channel - Channel to by updated - * duty - New duty - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, - uint8_t channel, ub16_t duty) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t ccr = 0; - - /* We don't want compilation warnings if no DEBUGASSERT */ - - UNUSED(priv); - - DEBUGASSERT(priv != NULL); - - _info("TIM%u channel: %u duty: %08" PRIx32 "\n", - priv->timid, channel, duty); - - /* Get the reload values */ - - reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); - - /* Duty cycle: - * - * duty cycle = ccr / reload (fractional value) - */ - - ccr = b16toi(duty * reload + b16HALF); - - _info("ccr: %" PRIu32 "\n", ccr); - - /* Write corresponding CCR register */ - - return pulsecount_ccr_update(dev, channel, ccr); -} - -/**************************************************************************** - * Name: pulsecount_frequency_update - * - * Description: - * Update a pulsecount timer frequency - * - ****************************************************************************/ - -static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, - uint32_t frequency) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t reload = 0; - uint32_t timclk = 0; - uint32_t prescaler = 0; - - /* Calculate optimal values for the timer prescaler and for the timer - * reload register. If 'frequency' is the desired frequency, then - * - * reload = timclk / frequency - * timclk = pclk / presc - * - * Or, - * - * reload = pclk / presc / frequency - * - * There are many solutions to this, but the best solution will be the one - * that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= presc <= 65536 - * 1 <= reload <= 65535 - * - * So presc = pclk / 65535 / frequency would be optimal. - * - * Example: - * - * pclk = 42 MHz - * frequency = 100 Hz - * - * prescaler = 42,000,000 / 65,535 / 100 - * = 6.4 (or 7 -- taking the ceiling always) - * timclk = 42,000,000 / 7 - * = 6,000,000 - * reload = 6,000,000 / 100 - * = 60,000 - */ - - prescaler = (priv->pclk / frequency + 65534) / 65535; - if (prescaler < 1) - { - prescaler = 1; - } - else if (prescaler > 65536) - { - prescaler = 65536; - } - - timclk = priv->pclk / prescaler; - - reload = timclk / frequency; - if (reload < 2) - { - reload = 1; - } - else if (reload > 65535) - { - reload = 65535; - } - else - { - reload--; - } - - _info("TIM%u PCLK: %" PRIu32 " frequency: %" PRIu32 " TIMCLK: %" PRIu32 - " prescaler: %" PRIu32 " reload: %" PRIu32 "\n", - priv->timid, priv->pclk, frequency, timclk, prescaler, reload); - - /* Set the reload and prescaler values */ - - pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, - (uint16_t)(prescaler - 1)); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_timer_configure - * - * Description: - * Initial configuration for pulsecount timer - * - ****************************************************************************/ - -static int pulsecount_timer_configure(struct stm32_tim_s *priv) -{ - uint16_t cr1 = 0; - - /* Set up the advanced timer CR1 register. */ - - cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); - - /* Pulsecount always uses edge-aligned up-counting mode. */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - cr1 |= GTIM_CR1_EDGE; - cr1 &= ~GTIM_CR1_CKD_MASK; - cr1 |= priv->t_dts << GTIM_CR1_CKD_SHIFT; - - /* Enable ARR preload to preserve the previous pulsecount behavior. */ - - cr1 |= GTIM_CR1_ARPE; - - /* Write CR1 */ - - pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_channel_configure - * - * Description: - * Configure pulsecount output compare for a channel - * - ****************************************************************************/ - -static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, - uint8_t channel) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t chanmode = 0; - uint32_t ocmode = 0; - uint32_t ccmr = 0; - uint32_t offset = 0; - int ret = OK; - - /* Configure output compare mode */ - - chanmode = GTIM_CCMR_MODE_PWM1; - - /* output compare configuration */ - - switch (channel) - { - /* Get CCMR offset */ - - case 1: - case 2: - { - offset = STM32_GTIM_CCMR1_OFFSET; - break; - } - - case 3: - case 4: - { - offset = STM32_GTIM_CCMR2_OFFSET; - break; - } - - default: - { - _err("ERROR: No such channel: %u\n", channel); - ret = -EINVAL; - goto errout; - } - } - - /* Get current registers */ - - ccmr = pulsecount_getreg(priv, offset); - - /* output compare configuration. - * NOTE: The CCMRx registers are identical if the channels are outputs. - */ - - switch (channel) - { - /* Configure channel 1/3 */ - - case 1: - case 3: - { - ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | - ATIM_CCMR1_OC1PE | ATIM_CCMR1_OC1M); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT); - ocmode |= ATIM_CCMR1_OC1PE; - break; - } - - /* Configure channel 2/4 */ - - case 2: - case 4: - { - ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | - ATIM_CCMR1_OC2PE | ATIM_CCMR1_OC2M); - ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT); - ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT); - ocmode |= ATIM_CCMR1_OC2PE; - break; - } - } - - /* Set the selected output compare configuration */ - - ccmr |= ocmode; - - /* Write CCMRx registers */ - - pulsecount_putreg(priv, offset, ccmr); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_output_configure - * - * Description: - * Configure pulsecount output for given channel - * - ****************************************************************************/ - -static int pulsecount_output_configure(struct stm32_tim_s *priv, - uint8_t channel) -{ - uint32_t cr2 = 0; - uint32_t ccer = 0; - - /* Get current registers state */ - - cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* | OISx | IDLE | advanced timers | CR2 register - * | CCxP | POL | all pulsecount timers | CCER register - */ - - /* Configure output polarity (all pulsecount timers) */ - - if (priv->channel.out1.pol == PULSECOUNT_POL_NEG) - { - ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - else - { - ccer &= ~(GTIM_CCER_CC1P << ((channel - 1) * 4)); - } - - if (priv->timtype == TIMTYPE_ADVANCED) - { - /* Configure output IDLE State */ - - if (priv->channel.out1.idle == PULSECOUNT_IDLE_ACTIVE) - { - cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - else - { - cr2 &= ~(ATIM_CR2_OIS1 << ((channel - 1) * 2)); - } - } - - /* Write registers */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_outputs_enable - * - * Description: - * Enable/disable given timer pulsecount outputs. - * - * NOTE: This is bulk operation - we can enable/disable many outputs - * at one time - * - * Input Parameters: - * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) - * state - Enable/disable operation - * - ****************************************************************************/ - -static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, - uint16_t outputs, bool state) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t ccer = 0; - uint32_t regval = 0; - - /* Get current register state */ - - ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); - - /* Get outputs configuration */ - - regval |= ((outputs & (1 << 0)) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & (1 << 2)) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & (1 << 4)) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & (1 << 6)) ? GTIM_CCER_CC4E : 0); - - /* NOTE: CC4N does not exist, but some docs show configuration bits for it - */ - - if (state == true) - { - /* Enable outputs - set bits */ - - ccer |= regval; - } - else - { - /* Disable outputs - reset bits */ - - ccer &= ~regval; - } - - /* Write register */ - - pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_moe_enable - ****************************************************************************/ - -static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, - bool enable) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - if (enable) - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - else - { - pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); - } -} - -/**************************************************************************** - * Name: pulsecount_outputs_from_channels - * - * Description: - * Get enabled outputs configuration from the pulsecount timer state - * - ****************************************************************************/ - -static uint16_t -pulsecount_outputs_from_channels(struct stm32_tim_s *priv, - uint8_t selected) -{ - uint16_t outputs = 0; - uint8_t channel; - - channel = priv->channel.channel; - - if (channel != 0 && (selected == 0 || channel == selected) && - priv->channel.out1.in_use == 1) - { - outputs = (1 << ((channel - 1) * 2)); - } - - return outputs; -} - -/**************************************************************************** - * Name: pulsecount_configure - * - * Description: - * Configure pulsecount timer for pulse output - * - ****************************************************************************/ - -static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t outputs = 0; - int ret = OK; - - /* NOTE: leave timer counter disabled and all outputs disabled! */ - - /* Disable the timer until we get it configured */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, 0); - - /* Disable configured outputs before the timer is reconfigured. */ - - ret = pulsecount_outputs_enable(dev, outputs, false); - if (ret < 0) - { - goto errout; - } - - /* Initial timer configuration */ - - ret = pulsecount_timer_configure(priv); - if (ret < 0) - { - goto errout; - } - - /* Disable software break (enable outputs) */ - - pulsecount_moe_enable(dev, true); - - /* Configure timer channel */ - - if (priv->channel.channel != 0) - { - pulsecount_channel_configure(dev, priv->channel.channel); - pulsecount_output_configure(priv, priv->channel.channel); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_timer - * - * Description: - * (Re-)initialize the timer resources and start the pulsed output - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * info - A reference to the characteristics of the pulsed output - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * This split keeps pulsecount as the existing single-channel mode. - * - ****************************************************************************/ - -static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - ub16_t duty = 0; - uint8_t channel = 0; - uint16_t outputs = 0; - int ret = OK; - - /* If we got here then the timer instance supports pulsecount output. */ - - DEBUGASSERT(priv != NULL && info != NULL); - - _info("TIM%u channel: %u high: %" PRIu32 " ns low: %" PRIu32 - " ns count: %" PRIu32 "\n", - priv->timid, priv->channel.channel, info->high_ns, - info->low_ns, info->count); - - DEBUGASSERT(pulsecount_frequency(info) > 0); - - /* Channel specific setup */ - - duty = pulsecount_duty(info); - channel = priv->channel.channel; - - /* Disable all interrupts and DMA requests, clear all pending status */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Set timer frequency */ - - ret = pulsecount_frequency_update(dev, pulsecount_frequency(info)); - if (ret < 0) - { - goto errout; - } - - /* Update duty cycle */ - - ret = pulsecount_duty_update(dev, channel, duty); - if (ret < 0) - { - goto errout; - } - - /* If a non-zero repetition count has been selected, then set the - * repetition counter to the count-1 (pulsecount_start() has already - * assured us that the count value is within range). - */ - - if (info->count > 0) - { - /* Save the remaining count and the number of counts that will have - * elapsed on the first interrupt. - */ - - /* If the first interrupt occurs at the end end of the first - * repetition count, then the count will be the same as the RCR - * value. - */ - - priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->prev - 1); - - /* Generate an update event to reload the prescaler. This should - * preload the RCR into active repetition counter. - */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* Now set the value of the RCR that will be loaded on the next - * update event. - */ - - priv->count = info->count; - priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Otherwise, just clear the repetition counter */ - - else - { - /* Set the repetition counter to zero */ - - pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); - - /* Generate an update event to reload the prescaler */ - - pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - } - - /* Get configured outputs */ - - outputs = pulsecount_outputs_from_channels(priv, channel); - - /* Enable output */ - - ret = pulsecount_outputs_enable(dev, outputs, true); - if (ret < 0) - { - goto errout; - } - - /* Setup update interrupt. If info->count is > 0, then we can - * be assured that pulsecount_start() has already verified: (1) that - * this is an advanced timer, and that (2) the repetition count is within - * range. - */ - - if (info->count > 0) - { - /* Clear all pending interrupts and enable the update interrupt. */ - - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); - - /* Enable the timer */ - - pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); - - /* And enable timer interrupts at the NVIC */ - - up_enable_irq(priv->irq); - } - - pulsecount_dumpregs(dev, "After starting"); - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_interrupt - * - * Description: - * Handle timer interrupts. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint16_t regval; - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); - - /* Calculate the new count by subtracting the number of pulses - * since the last interrupt. - */ - - if (priv->count <= priv->prev) - { - /* We are finished. Turn off the mast output to stop the output as - * quickly as possible. - */ - - regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); - regval &= ~ATIM_BDTR_MOE; - pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); - - /* Disable first interrupts, stop and reset the timer */ - - pulsecount_ll_stop(dev); - - /* Then perform the callback into the upper half driver */ - - pulsecount_expired(priv->handle); - - priv->handle = NULL; - priv->count = 0; - priv->prev = 0; - priv->curr = 0; - } - else - { - /* Decrement the count of pulses remaining using the number of - * pulses generated since the last interrupt. - */ - - priv->count -= priv->prev; - - /* Set up the next RCR. Set 'prev' to the value of the RCR that - * was loaded when the update occurred (just before this interrupt) - * and set 'curr' to the current value of the RCR register (which - * will bet loaded on the next update event). - */ - - priv->prev = priv->curr; - priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, - (uint16_t)priv->curr - 1); - } - - /* Now all of the time critical stuff is done so we can do some debug - * output - */ - - _info("Update interrupt SR: %04" PRIx16 " prev: %u curr: %u" - " count: %" PRIu32 "\n", - regval, (unsigned int)priv->prev, (unsigned int)priv->curr, - priv->count); - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_tim1/8interrupt - * - * Description: - * Handle timer 1 and 8 interrupts. - * - * Input Parameters: - * Standard NuttX interrupt inputs - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_TIM1_PULSECOUNT -static int pulsecount_tim1interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount1dev); -} -#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT -static int pulsecount_tim8interrupt(int irq, void *context, void *arg) -{ - return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) - &g_pulsecount8dev); -} -#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ - -/**************************************************************************** - * Name: pulsecount_count - * - * Description: - * Pick an optimal pulse count to program the RCR. - * - * Input Parameters: - * count - The total count remaining - * - * Returned Value: - * The recommended pulse count - * - ****************************************************************************/ - -static uint8_t pulsecount_count(uint32_t count) -{ - /* The the remaining pulse count is less than or equal to the maximum, the - * just return the count. - */ - - if (count <= ATIM_RCR_REP_MAX) - { - return (uint8_t)count; - } - - /* Otherwise, we have to be careful. We do not want a small number of - * counts at the end because we might have trouble responding fast enough. - * If the remaining count is less than 150% of the maximum, then return - * half of the maximum. In this case the final sequence will be between 64 - * and 128. - */ - - else if (count < (3 * ATIM_RCR_REP_MAX / 2)) - { - return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1); - } - - /* Otherwise, return the maximum. The final count will be 64 or more */ - - else - { - return (uint8_t)ATIM_RCR_REP_MAX; - } -} - -/**************************************************************************** - * Name: pulsecount_setapbclock - * - * Description: - * Enable or disable APB clock for the timer peripheral - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static int pulsecount_setapbclock(struct stm32_tim_s *priv, - bool on) -{ - uint32_t en_bit; - uint32_t regaddr; - int ret = OK; - - /* Determine which timer to configure */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM1EN; - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - regaddr = STM32_RCC_APB2ENR; - en_bit = RCC_APB2ENR_TIM8EN; - break; - } -#endif - - default: - { - _err("ERROR: No such timer configured %d\n", priv->timid); - ret = -EINVAL; - goto errout; - } - } - - /* Enable/disable APB 1/2 clock for timer */ - - if (on) - { - modifyreg32(regaddr, 0, en_bit); - } - else - { - modifyreg32(regaddr, en_bit, 0); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * It should not, however, output pulses until the start method is called. - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * APB1 or 2 clocking for the GPIOs has already been configured by the RCC - * logic at power up. - * - ****************************************************************************/ - -static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg; - - _info("TIM%u\n", priv->timid); - - /* Enable APB1/2 clocking for timer. */ - - pulsecount_setapbclock(priv, true); - - pulsecount_dumpregs(dev, "Initially"); - - /* Configure the pulsecount output pins, but do not start the timer yet */ - - if (priv->channel.out1.in_use == 1) - { - pincfg = priv->channel.out1.pincfg; - _info("pincfg: %08" PRIx32 "\n", pincfg); - - stm32_configgpio(pincfg); - pulsecount_dumpgpio(pincfg, "pulsecount setup"); - } - - return OK; -} - -/**************************************************************************** - * Name: pulsecount_ll_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * stop pulsed output, free any resources, disable the timer hardware, and - * put the system into the lowest possible power usage state - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t pincfg = 0; - int ret = OK; - - _info("TIM%u\n", priv->timid); - - /* Make sure that the output has been stopped */ - - pulsecount_ll_stop(dev); - - /* Disable APB1/2 clocking for timer. */ - - ret = pulsecount_setapbclock(priv, false); - if (ret < 0) - { - goto errout; - } - - /* Then put the GPIO pins back to the default state */ - - pincfg = priv->channel.out1.pincfg; - if (pincfg != 0) - { - _info("pincfg: %08" PRIx32 "\n", pincfg); - - pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= GPIO_INPUT | GPIO_FLOAT; - - stm32_configgpio(pincfg); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: pulsecount_ll_stop - * - * Description: - * Stop the pulsed output and reset the timer resources - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - * Assumptions: - * This function is called to stop the pulsed output at anytime. This - * method is also called from the timer interrupt handler when a repetition - * count expires... automatically stopping the timer. - * - ****************************************************************************/ - -static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - uint32_t resetbit = 0; - uint32_t regaddr; - uint32_t regval; - irqstate_t flags; - - _info("TIM%u\n", priv->timid); - - /* Determine which timer to reset */ - - switch (priv->timid) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - return -EINVAL; - } - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - flags = enter_critical_section(); - - /* Disable further interrupts and stop the timer */ - - pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Reset the timer - stopping the output and putting the timer back - * into a state where pulsecount_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - _info("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - pulsecount_dumpregs(dev, "After stop"); - return OK; -} - -/**************************************************************************** - * Name: pulsecount_ll_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - * Input Parameters: - * dev - A reference to the lower half pulsecount driver state structure - * cmd - The ioctl command - * arg - The argument accompanying the ioctl command - * - * Returned Value: - * Zero on success; a negated errno value on failure - * - ****************************************************************************/ - -static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, - unsigned long arg) -{ -#ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; - - /* There are no platform-specific ioctl commands */ - - _info("TIM%u\n", priv->timid); -#endif - return -ENOTTY; -} - -static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - int ret; - - ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); - if (ret < 0) - { - return ret; - } - - return pulsecount_configure((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) - pulse->timer); -} - -static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, - const struct pulsecount_info_s *info, - void *handle) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - struct stm32_tim_s *priv = pulse->timer; - - if (info->count > 0) - { - if (priv->timtype != TIMTYPE_ADVANCED) - { - _err("ERROR: TIM%u cannot support pulse count: %" PRIu32 "\n", - priv->timid, info->count); - return -EPERM; - } - } - - priv->handle = handle; - return pulsecount_timer((struct pulsecount_lowerhalf_s *)priv, info); -} - -static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); -} - -static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, - int cmd, unsigned long arg) -{ - struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; - return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, - cmd, arg); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) -{ - struct stm32_pulsecount_s *lower = NULL; - - _info("TIM%u\n", timer); - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1_PULSECOUNT - case 1: - { - lower = &g_pulsecount1lower; - irq_attach(lower->timer->irq, pulsecount_tim1interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - -#ifdef CONFIG_STM32_TIM8_PULSECOUNT - case 8: - { - lower = &g_pulsecount8lower; - irq_attach(lower->timer->irq, pulsecount_tim8interrupt, NULL); - up_disable_irq(lower->timer->irq); - break; - } -#endif - - default: - { - _err("ERROR: TIM%d does not support pulse count\n", timer); - return NULL; - } - } - - return (struct pulsecount_lowerhalf_s *)lower; -} - -#endif /* CONFIG_STM32_TIM1_PULSECOUNT || CONFIG_STM32_TIM8_PULSECOUNT */ diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.h b/arch/arm/src/stm32l4/stm32l4_pulsecount.h deleted file mode 100644 index 1e0fd8667a5a7..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_PULSECOUNT_H */ From cf83121a60e6f88c5a7595dd3e97dba1ce05b278 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 3 Jun 2026 19:17:38 +0200 Subject: [PATCH 46/52] arch/arm/src/stm32l4: use common/stm32 1-Wire driver Drop the L4 1-Wire copy and build the shared common/stm32/stm32_1wire_m3m4_v1.c for L4. L4's USART is the standard V3 IP, so make its headers follow the same conventions the common families already use: alias the legacy SR status names onto ISR (as stm32_uart_v3.h does) and add the canonical APB1ENR clock-enable aliases (as the G4 RCC header does). The shared driver then needs no per-chip special-casing. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 2 - arch/arm/src/common/stm32/CMakeLists.txt | 8 +- arch/arm/src/common/stm32/Make.defs | 8 +- arch/arm/src/common/stm32/stm32_1wire.h | 2 - .../src/common/stm32/stm32_1wire_m3m4_v1.c | 158 +- arch/arm/src/stm32l4/CMakeLists.txt | 4 - arch/arm/src/stm32l4/Make.defs | 4 - arch/arm/src/stm32l4/hardware/stm32l4_uart.h | 20 + arch/arm/src/stm32l4/stm32l4_1wire.c | 1271 ----------------- arch/arm/src/stm32l4/stm32l4_1wire.h | 74 - arch/arm/src/stm32l4/stm32l4_rcc.h | 11 + 11 files changed, 181 insertions(+), 1381 deletions(-) delete mode 100644 arch/arm/src/stm32l4/stm32l4_1wire.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_1wire.h diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 6389d90e48035..ab0a3ce2e222a 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -4405,8 +4405,6 @@ arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap_legacy.h David.Sidrane@NscDg.co arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h alin.jerpelea@sony.com s.nikitenko@me.com juha.niskanen@haltian.com shen497@purdue.edu arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h alin.jerpelea@sony.com arch/arm/src/stm32l4/stm32l4.h sebastien@lorquet.fr alin.jerpelea@sony.com miha.vrhovnik@gmail.com pekka.ervasti@haltian.com -arch/arm/src/stm32l4/stm32l4_1wire.c juha.niskanen@haltian.com anjiahao@xiaomi.com abdelatif.guettouche@gmail.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com -arch/arm/src/stm32l4/stm32l4_1wire.h juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_adc.c juha.niskanen@haltian.com danieloak@gmail.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com raiden00@railab.me arch/arm/src/stm32l4/stm32l4_adc.h danieloak@gmail.com juha.niskanen@haltian.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32l4/stm32l4_allocateheap.c sebastien@lorquet.fr juha.niskanen@haltian.com alin.jerpelea@sony.com dev@ziggurat29.com xiaoxiang@xiaomi.com diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 8ab65ba855020..3d5bc5f2074ee 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -38,6 +38,10 @@ if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() +if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) +endif() + if(CONFIG_STM32_COMMON_LEGACY) list( APPEND @@ -261,10 +265,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_hrtim_m3m4_v1.c) endif() - if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire_m3m4_v1.c) - endif() - if(CONFIG_STM32_HCIUART) list(APPEND SRCS stm32_hciuart_m3m4_v1.c) endif() diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 82be1b7ca0ef5..f8ea27cc99b41 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -46,6 +46,10 @@ ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c @@ -290,10 +294,6 @@ CHIP_CSRCS += stm32_hrtim_m3m4_v1.c endif endif -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire_m3m4_v1.c -endif - ifeq ($(CONFIG_STM32_HCIUART),y) CHIP_CSRCS += stm32_hciuart_m3m4_v1.c endif diff --git a/arch/arm/src/common/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h index 79f9f6d47e46f..d125a4c1b6960 100644 --- a/arch/arm/src/common/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -31,8 +31,6 @@ #include -#include "stm32_uart.h" - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c index 595136c6c65d0..b5d0fad9b36e9 100644 --- a/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -45,16 +46,15 @@ #include #include #include +#include #include #include #include "arm_internal.h" -#include "stm32_rcc.h" +#include "chip.h" +#include "stm32.h" #include "stm32_1wire.h" -#include "stm32_rcc.h" - -#ifdef HAVE_1WIREDRIVER /**************************************************************************** * Pre-processor Definitions @@ -126,6 +126,9 @@ struct stm32_1wire_priv_s uint8_t *byte; /* Current byte */ uint8_t bit; /* Current bit */ volatile int result; /* Exchange result */ +#ifdef CONFIG_PM + struct pm_callback_s pm_cb; /* PM callbacks */ +#endif }; /* 1-Wire device, Instance */ @@ -166,6 +169,10 @@ static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, static int stm32_1wire_writebit(struct onewire_dev_s *dev, const uint8_t *bit); static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); +#ifdef CONFIG_PM +static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif /**************************************************************************** * Private Data @@ -189,7 +196,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -210,7 +220,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -231,7 +244,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -252,7 +268,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -273,7 +292,10 @@ static struct stm32_1wire_priv_s stm32_1wire5_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -294,7 +316,10 @@ static struct stm32_1wire_priv_s stm32_1wire6_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -315,7 +340,10 @@ static struct stm32_1wire_priv_s stm32_1wire7_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -336,7 +364,10 @@ static struct stm32_1wire_priv_s stm32_1wire8_priv = .refs = 0, .lock = NXMUTEX_INITIALIZER, .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL + .msgs = NULL, +#ifdef CONFIG_PM + .pm_cb.prepare = stm32_1wire_pm_prepare, +#endif }; #endif @@ -634,7 +665,11 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M); + USART_CR1_PCE | USART_CR1_PS | USART_CR1_M +#ifdef USART_CR1_M1 + | USART_CR1_M1 +#endif + ); regval |= USART_CR1_RXNEIE; stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); @@ -937,7 +972,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0) { -#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) +#ifdef STM32_USART_ICR_OFFSET /* These errors are cleared by writing the corresponding bit to the * interrupt clear register (ICR). */ @@ -968,8 +1003,16 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_SR_LBD) != 0) { +#ifdef STM32_USART_ICR_OFFSET + /* The LIN break flag is cleared by writing LBDCF to the interrupt + * clear register (ICR); the status register is read-only. + */ + + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); +#else sr &= ~USART_SR_LBD; stm32_1wire_out(priv, STM32_USART_SR_OFFSET, sr); +#endif if (priv->msgs != NULL) { @@ -1143,6 +1186,78 @@ static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) return stm32_1wire_process(priv, msgs, 1); } +/**************************************************************************** + * Name: stm32_1wire_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a + * warning that the system is about to enter into a new power state. The + * driver should begin whatever operations that may be required to enter + * power state. The driver may abort the state change mode by returning + * a non-zero value from the callback function. + * + * Input Parameters: + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state + * data at the end of the structure. + * domain - Identifies the activity domain of the state change + * pmstate - Identifies the new PM state + * + * Returned Value: + * 0 (OK) means the event was successfully processed and that the driver + * is prepared for the PM state change. Non-zero means that the driver + * is not prepared to perform the tasks needed achieve this power setting + * and will cause the state change to be aborted. NOTE: The prepare + * method will also be recalled when reverting from lower back to higher + * power consumption modes (say because another driver refused a lower + * power state change). Drivers are not permitted to return non-zero + * values when reverting back to higher power consumption modes! + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + struct stm32_1wire_priv_s *priv = + (struct stm32_1wire_priv_s *)((char *)cb - + offsetof(struct stm32_1wire_priv_s, pm_cb)); + + /* Logic to prepare for a reduced power state goes here. */ + + switch (pmstate) + { + case PM_NORMAL: + case PM_IDLE: + break; + + case PM_STANDBY: + case PM_SLEEP: + + /* Check if exclusive lock for 1-Wire bus is held. */ + + if (nxmutex_is_locked(&priv->lock)) + { + /* Exclusive lock is held, do not allow entry to deeper PM + * states. + */ + + return -EBUSY; + } + + break; + + default: + + /* Should not get here */ + + break; + } + + return OK; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -1238,6 +1353,12 @@ struct onewire_dev_s *stm32_1wireinitialize(int port) if (priv->refs++ == 0) { stm32_1wire_init(priv); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + DEBUGVERIFY(pm_register(&priv->pm_cb)); +#endif } nxmutex_unlock(&priv->lock); @@ -1282,6 +1403,13 @@ int stm32_1wireuninitialize(struct onewire_dev_s *dev) /* Disable power and other HW resource (GPIO's) */ stm32_1wire_deinit(priv); + +#ifdef CONFIG_PM + /* Unregister power management callbacks */ + + pm_unregister(&priv->pm_cb); +#endif + nxmutex_unlock(&priv->lock); /* Free instance */ @@ -1289,5 +1417,3 @@ int stm32_1wireuninitialize(struct onewire_dev_s *dev) kmm_free(dev); return OK; } - -#endif /* HAVE_1WIREDRIVER */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 0d2406e409557..4683bf3f08207 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -186,10 +186,6 @@ if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32l4_sdmmc.c) endif() -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32l4_1wire.c) -endif() - target_sources(arch PRIVATE ${SRCS}) add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index d62701c5fc459..a073cf3e87a4a 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -181,7 +181,3 @@ endif ifeq ($(CONFIG_STM32_SDMMC1),y) CHIP_CSRCS += stm32l4_sdmmc.c endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32l4_1wire.c -endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index cf3135593e540..e5c2455e2f52f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -296,6 +296,26 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 drivers keep working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_CR1_M USART_CR1_M0 + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c deleted file mode 100644 index d22c0e8d5a9e4..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ /dev/null @@ -1,1271 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_1wire.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Links: - * https://www.maximintegrated.com/en/app-notes/index.mvp/id/214 - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "stm32l4_rcc.h" -#include "stm32l4_gpio.h" -#include "stm32l4_1wire.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BUS_TIMEOUT 5 /* tv_sec */ - -#define RESET_BAUD 9600 -#define RESET_TX 0xF0 -#define TIMESLOT_BAUD 115200 -#define READ_TX 0xFF -#define READ_RX1 0xFF -#define WRITE_TX0 0x00 -#define WRITE_TX1 0xFF - -#define PIN_OPENDRAIN(gpio) ((gpio) | GPIO_OPENDRAIN) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* 1-Wire bus task */ - -enum stm32_1wire_msg_e -{ - ONEWIRETASK_NONE = 0, - ONEWIRETASK_RESET, - ONEWIRETASK_WRITE, - ONEWIRETASK_READ, - ONEWIRETASK_WRITEBIT, - ONEWIRETASK_READBIT -}; - -struct stm32_1wire_msg_s -{ - enum stm32_1wire_msg_e task; /* Task */ - uint8_t *buffer; /* Task buffer */ - int buflen; /* Buffer length */ -}; - -/* 1-Wire device hardware configuration */ - -struct stm32_1wire_config_s -{ - const uint32_t usartbase; /* Base address of USART registers */ - const uint32_t apbclock; /* PCLK 1 or 2 frequency */ - const uint32_t data_pin; /* GPIO configuration for DATA */ - const uint8_t irq; /* IRQ associated with this USART */ -}; - -/* 1-Wire device Private Data */ - -struct stm32_1wire_priv_s -{ - const struct stm32_1wire_config_s *config; /* Port configuration */ - volatile int refs; /* Reference count */ - mutex_t lock; /* Mutual exclusion mutex */ - sem_t sem_isr; /* Interrupt wait semaphore */ - int baud; /* Baud rate */ - const struct stm32_1wire_msg_s *msgs; /* Messages data */ - uint8_t *byte; /* Current byte */ - uint8_t bit; /* Current bit */ - volatile int result; /* Exchange result */ -#ifdef CONFIG_PM - struct pm_callback_s pm_cb; /* PM callbacks */ -#endif -}; - -/* 1-Wire device, Instance */ - -struct stm32_1wire_inst_s -{ - const struct onewire_ops_s *ops; /* Standard 1-Wire operations */ - struct stm32_1wire_priv_s *priv; /* Common driver private data structure */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset); -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value); -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch); -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv); -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on); -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv); -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count); -static int stm32_1wire_isr(int irq, void *context, void *arg); -static int stm32_1wire_reset(struct onewire_dev_s *dev); -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, int buflen); -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen); -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen); -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit); -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit); -#ifdef CONFIG_PM -static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* 1-Wire device structures */ - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire1_config = -{ - .usartbase = STM32_USART1_BASE, - .apbclock = STM32_PCLK2_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32_IRQ_USART1, -}; - -static struct stm32_1wire_priv_s stm32_1wire1_priv = -{ - .config = &stm32_1wire1_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire2_config = -{ - .usartbase = STM32_USART2_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32_IRQ_USART2, -}; - -static struct stm32_1wire_priv_s stm32_1wire2_priv = -{ - .config = &stm32_1wire2_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire3_config = -{ - .usartbase = STM32_USART3_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32_IRQ_USART3, -}; - -static struct stm32_1wire_priv_s stm32_1wire3_priv = -{ - .config = &stm32_1wire3_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire4_config = -{ - .usartbase = STM32_UART4_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32_IRQ_UART4, -}; - -static struct stm32_1wire_priv_s stm32_1wire4_priv = -{ - .config = &stm32_1wire4_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - -static const struct stm32_1wire_config_s stm32_1wire5_config = -{ - .usartbase = STM32_UART5_BASE, - .apbclock = STM32_PCLK1_FREQUENCY, - .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32_IRQ_UART5, -}; - -static struct stm32_1wire_priv_s stm32_1wire5_priv = -{ - .config = &stm32_1wire5_config, - .refs = 0, - .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), - .msgs = NULL, -#ifdef CONFIG_PM - .pm_cb.prepare = stm32_1wire_pm_prepare, -#endif -}; - -#endif - -/* Device Structures, Instantiation */ - -static const struct onewire_ops_s stm32_1wire_ops = -{ - .reset = stm32_1wire_reset, - .write = stm32_1wire_write, - .read = stm32_1wire_read, - .exchange = stm32_1wire_exchange, - .writebit = stm32_1wire_writebit, - .readbit = stm32_1wire_readbit -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wire_in - ****************************************************************************/ - -static inline uint32_t stm32_1wire_in(struct stm32_1wire_priv_s *priv, - int offset) -{ - return getreg32(priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_out - ****************************************************************************/ - -static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, - int offset, uint32_t value) -{ - putreg32(value, priv->config->usartbase + offset); -} - -/**************************************************************************** - * Name: stm32_1wire_recv - * - * Description: - * This method will recv one byte on the USART - * - ****************************************************************************/ - -static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) -{ - return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; -} - -/**************************************************************************** - * Name: stm32_1wire_send - * - * Description: - * This method will send one byte on the USART - * - ****************************************************************************/ - -static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) -{ - stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); -} - -/**************************************************************************** - * Name: stm32_1wire_set_baud - * - * Description: - * Set the serial line baud. - * - ****************************************************************************/ - -static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) -{ - /* This first implementation is for U[S]ARTs that support oversampling - * by 8 in additional to the standard oversampling by 16. - */ - - uint32_t usartdiv8; - uint32_t cr1; - uint32_t brr; - bool enabled; - - /* If UART was enabled (UE was set), temporarily disable it - * for baud changing. - */ - - cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - - enabled = cr1 & USART_CR1_UE; - if (enabled) - { - cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - } - - /* In case of oversampling by 8, the equation is: - * - * baud = 2 * fCK / usartdiv8 - * usartdiv8 = 2 * fCK / baud - */ - - usartdiv8 = ((priv->config->apbclock << 1) + (priv->baud >> 1)) / - priv->baud; - - /* Baud rate for standard USART (SPI mode included): - * - * In case of oversampling by 16, the equation is: - * baud = fCK / usartdiv16 - * usartdiv16 = fCK / baud - * = 2 * usartdiv8 - */ - - /* Use oversample by 8 only if the divisor is small. But what is small? */ - - if (usartdiv8 > 100) - { - /* Use usartdiv16 */ - - brr = (usartdiv8 + 1) >> 1; - - /* Clear oversampling by 8 to enable oversampling by 16 */ - - cr1 &= ~USART_CR1_OVER8; - } - else - { - DEBUGASSERT(usartdiv8 >= 8); - - /* Perform mysterious operations on bits 0-3 */ - - brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1)); - - /* Set oversampling by 8 */ - - cr1 |= USART_CR1_OVER8; - } - - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); - - if (enabled) - { - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); - } -} - -/**************************************************************************** - * Name: stm32_1wire_set_apb_clock - * - * Description: - * Enable or disable APB clock for the USART peripheral - * - * Input Parameters: - * priv - A reference to the 1-Wire driver state structure - * on - Enable clock if 'on' is 'true' and disable if 'false' - * - ****************************************************************************/ - -static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, - bool on) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t rcc_en; - uint32_t regaddr; - - /* Determine which USART to configure */ - - switch (config->usartbase) - { - default: - return; - -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case STM32_USART1_BASE: - rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32_RCC_APB2ENR; - break; -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case STM32_USART2_BASE: - rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case STM32_USART3_BASE: - rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case STM32_UART4_BASE: - rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case STM32_UART5_BASE: - rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32_RCC_APB1ENR1; - break; -#endif - } - - /* Enable/disable APB 1/2 clock for USART */ - - if (on) - { - modifyreg32(regaddr, 0, rcc_en); - } - else - { - modifyreg32(regaddr, rcc_en, 0); - } -} - -/**************************************************************************** - * Name: stm32_1wire_init - * - * Description: - * Setup the 1-Wire hardware, ready for operation with defaults - * - ****************************************************************************/ - -static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - int ret; - - /* Enable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, true); - - /* Configure CR2 - * Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits - * Set LBDIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | - USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); - regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Configure CR1 - * Clear TE, REm, all interrupt enable bits, PCE, PS and M - * Set RXNEIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | - USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); - regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure CR3 - * Clear CTSE, RTSE, and all interrupt enable bits - * Set ONEBIT, HDSEL and EIE - */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | - USART_CR3_EIE); - regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Enable Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Configure pins for USART use */ - - stm32_configgpio(config->data_pin); - - ret = irq_attach(config->irq, stm32_1wire_isr, priv); - if (ret == OK) - { - up_enable_irq(config->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_deinit - * - * Description: - * Shutdown the 1-Wire hardware - * - ****************************************************************************/ - -static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) -{ - const struct stm32_1wire_config_s *config = priv->config; - uint32_t regval; - - up_disable_irq(config->irq); - irq_detach(config->irq); - - /* Unconfigure GPIO pins */ - - stm32_unconfiggpio(config->data_pin); - - /* Disable RXNEIE, Rx, Tx, and the USART */ - - regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); - regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); - - /* Clear LBDIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); - regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); - - /* Clear ONEBIT, HDSEL and EIE */ - - regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); - regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); - - /* Disable USART APB1/2 clock */ - - stm32_1wire_set_apb_clock(priv, false); - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_exec - * - * Description: - * Execute 1-Wire task - ****************************************************************************/ - -static int stm32_1wire_process(struct stm32_1wire_priv_s *priv, - const struct stm32_1wire_msg_s *msgs, - int count) -{ - irqstate_t irqs; - int index; - int ret; - - /* Lock out other clients */ - - ret = nxmutex_lock(&priv->lock); - if (ret < 0) - { - return ret; - } - - priv->result = ERROR; - - for (index = 0; index < count; index++) - { - switch (msgs[index].task) - { - case ONEWIRETASK_NONE: - priv->result = OK; - break; - - case ONEWIRETASK_RESET: - - /* Set baud rate */ - - priv->baud = RESET_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - stm32_1wire_send(priv, RESET_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_WRITE: - case ONEWIRETASK_WRITEBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - - case ONEWIRETASK_READ: - case ONEWIRETASK_READBIT: - - /* Set baud rate */ - - priv->baud = TIMESLOT_BAUD; - stm32_1wire_set_baud(priv); - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = &msgs[index]; - priv->byte = priv->msgs->buffer; - priv->bit = 0; - stm32_1wire_send(priv, READ_TX); - leave_critical_section(irqs); - - /* Wait. Break on timeout if TX line closed to GND */ - - nxsem_tickwait(&priv->sem_isr, SEC2TICK(BUS_TIMEOUT)); - break; - } - - if (priv->result != OK) /* break if error */ - { - break; - } - } - - /* Atomic */ - - irqs = enter_critical_section(); - priv->msgs = NULL; - ret = priv->result; - leave_critical_section(irqs); - - /* Release the port for reuse by other clients */ - - nxmutex_unlock(&priv->lock); - return ret; -} - -/**************************************************************************** - * Name: stm32_1wire_isr - * - * Description: - * Common Interrupt Service Routine - ****************************************************************************/ - -static int stm32_1wire_isr(int irq, void *context, void *arg) -{ - struct stm32_1wire_priv_s *priv = (struct stm32_1wire_priv_s *)arg; - uint32_t sr; - uint32_t dr; - - DEBUGASSERT(priv != NULL); - - /* Get the masked USART status word. */ - - sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); - - /* Receive loop */ - - if ((sr & USART_ISR_RXNE) != 0) - { - dr = stm32_1wire_recv(priv); - - if (priv->msgs != NULL) - { - switch (priv->msgs->task) - { - case ONEWIRETASK_NONE: - break; - - case ONEWIRETASK_RESET: - priv->msgs = NULL; - priv->result = (dr != RESET_TX) ? OK : -ENODEV; /* if read RESET_TX then no slave */ - nxsem_post(&priv->sem_isr); - break; - - case ONEWIRETASK_WRITE: - if (++priv->bit >= 8) - { - priv->bit = 0; - - /* Done? */ - - if (++priv->byte >= - (priv->msgs->buffer + priv->msgs->buflen)) - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Send next bit */ - - stm32_1wire_send(priv, (*priv->byte & (1 << priv->bit)) ? - WRITE_TX1 : WRITE_TX0); - break; - - case ONEWIRETASK_READ: - if (dr == READ_RX1) - { - *priv->byte |= (1 << priv->bit); - } - else - { - *priv->byte &= ~(1 << priv->bit); - } - - if (++priv->bit >= 8) - { - priv->bit = 0; - if (++priv->byte >= (priv->msgs->buffer + priv->msgs->buflen)) /* Done? */ - { - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - - /* Recv next bit */ - - stm32_1wire_send(priv, READ_TX); - break; - - case ONEWIRETASK_READBIT: - *priv->byte = (dr == READ_RX1) ? 1 : 0; - - /* Fall through */ - - case ONEWIRETASK_WRITEBIT: - priv->msgs = NULL; - priv->result = OK; - nxsem_post(&priv->sem_isr); - break; - } - } - } - - /* Bounce check. */ - - if ((sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) - { - /* These errors are cleared by writing the corresponding bit to the - * interrupt clear register (ICR). - */ - - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, - (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - /* Bounce check. LIN break detection */ - - if ((sr & USART_ISR_LBDF) != 0) - { - stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); - - if (priv->msgs != NULL) - { - priv->msgs = NULL; - priv->result = ERROR; - nxsem_post(&priv->sem_isr); - } - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_1wire_reset - * - * Description: - * 1-Wire reset pulse and presence detect. - * - ****************************************************************************/ - -static int stm32_1wire_reset(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_RESET - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_write - * - * Description: - * Write 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_write(struct onewire_dev_s *dev, - const uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_read - * - * Description: - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_read(struct onewire_dev_s *dev, uint8_t *buffer, - int buflen) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READ, - [0].buffer = buffer, - [0].buflen = buflen - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_exchange - * - * Description: - * 1-Wire reset pulse and presence detect, - * Write 1-Wire data, - * Read 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_exchange(struct onewire_dev_s *dev, bool reset, - const uint8_t *txbuffer, int txbuflen, - uint8_t *rxbuffer, int rxbuflen) -{ - int result = ERROR; - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - if (reset) - { - const struct stm32_1wire_msg_s msgs[3] = - { - [0].task = ONEWIRETASK_RESET, - - [1].task = ONEWIRETASK_WRITE, - [1].buffer = (uint8_t *)txbuffer, - [1].buflen = txbuflen, - - [2].task = ONEWIRETASK_READ, - [2].buffer = rxbuffer, - [2].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 3); - } - else - { - const struct stm32_1wire_msg_s msgs[2] = - { - [0].task = ONEWIRETASK_WRITE, - [0].buffer = (uint8_t *)txbuffer, - [0].buflen = txbuflen, - - [1].task = ONEWIRETASK_READ, - [1].buffer = rxbuffer, - [1].buflen = rxbuflen - }; - - result = stm32_1wire_process(priv, msgs, 2); - } - - return result; -} - -/**************************************************************************** - * Name: stm32_1wire_writebit - * - * Description: - * Write one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_writebit(struct onewire_dev_s *dev, - const uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_WRITEBIT, - [0].buffer = (uint8_t *)bit, - [0].buflen = 1 - }; - - DEBUGASSERT(*bit == 0 || *bit == 1); - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_readbit - * - * Description: - * Sample one bit of 1-Wire data - * - ****************************************************************************/ - -static int stm32_1wire_readbit(struct onewire_dev_s *dev, uint8_t *bit) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - const struct stm32_1wire_msg_s msgs[1] = - { - [0].task = ONEWIRETASK_READBIT, - [0].buffer = bit, - [0].buflen = 1 - }; - - return stm32_1wire_process(priv, msgs, 1); -} - -/**************************************************************************** - * Name: stm32_1wire_pm_prepare - * - * Description: - * Request the driver to prepare for a new power state. This is a - * warning that the system is about to enter into a new power state. The - * driver should begin whatever operations that may be required to enter - * power state. The driver may abort the state change mode by returning - * a non-zero value from the callback function. - * - * Input Parameters: - * cb - Returned to the driver. The driver version of the callback - * structure may include additional, driver-specific state - * data at the end of the structure. - * domain - Identifies the activity domain of the state change - * pmstate - Identifies the new PM state - * - * Returned Value: - * 0 (OK) means the event was successfully processed and that the driver - * is prepared for the PM state change. Non-zero means that the driver - * is not prepared to perform the tasks needed achieve this power setting - * and will cause the state change to be aborted. NOTE: The prepare - * method will also be recalled when reverting from lower back to higher - * power consumption modes (say because another driver refused a lower - * power state change). Drivers are not permitted to return non-zero - * values when reverting back to higher power consumption modes! - * - ****************************************************************************/ - -#ifdef CONFIG_PM -static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, - enum pm_state_e pmstate) -{ - struct stm32_1wire_priv_s *priv = - (struct stm32_1wire_priv_s *)((char *)cb - - offsetof(struct stm32_1wire_priv_s, pm_cb)); - - /* Logic to prepare for a reduced power state goes here. */ - - switch (pmstate) - { - case PM_NORMAL: - case PM_IDLE: - break; - - case PM_STANDBY: - case PM_SLEEP: - - /* Check if exclusive lock for 1-Wire bus is held. */ - - if (nxmutex_is_locked(&priv->lock)) - { - /* Exclusive lock is held, do not allow entry to deeper PM - * states. - */ - - return -EBUSY; - } - - break; - - default: - - /* Should not get here */ - - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wireinitialize - * - * Description: - * Initialize the selected 1-Wire port. And return a unique instance of - * struct onewire_dev_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple 1-Wire interfaces) - * - * Returned Value: - * Valid 1-Wire device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct onewire_dev_s *stm32_1wireinitialize(int port) -{ - struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ - struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ - - /* Get 1-Wire private structure */ - - switch (port) - { -#ifdef CONFIG_STM32_USART1_1WIREDRIVER - case 1: - priv = &stm32_1wire1_priv; - break; -#endif - -#ifdef CONFIG_STM32_USART2_1WIREDRIVER - case 2: - priv = &stm32_1wire2_priv; - break; -#endif - -#ifdef CONFIG_STM32_USART3_1WIREDRIVER - case 3: - priv = &stm32_1wire3_priv; - break; -#endif - -#ifdef CONFIG_STM32_UART4_1WIREDRIVER - case 4: - priv = &stm32_1wire4_priv; - break; -#endif - -#ifdef CONFIG_STM32_UART5_1WIREDRIVER - case 5: - priv = &stm32_1wire5_priv; - break; -#endif - - default: - return NULL; - } - - /* Allocate instance */ - - inst = kmm_malloc(sizeof(*inst)); - if (inst == NULL) - { - return NULL; - } - - /* Initialize instance */ - - inst->ops = &stm32_1wire_ops; - inst->priv = priv; - - /* Initialize private data for the first time, increment reference count, - * power-up hardware and configure GPIOs. - */ - - nxmutex_lock(&priv->lock); - if (priv->refs++ == 0) - { - stm32_1wire_init(priv); - -#ifdef CONFIG_PM - /* Register to receive power management callbacks */ - - DEBUGVERIFY(pm_register(&priv->pm_cb)); -#endif - } - - nxmutex_unlock(&priv->lock); - return (struct onewire_dev_s *)inst; -} - -/**************************************************************************** - * Name: stm32_1wireuninitialize - * - * Description: - * De-initialize the selected 1-Wire port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_1wireinitialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_1wireuninitialize(struct onewire_dev_s *dev) -{ - struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; - - DEBUGASSERT(priv != NULL); - - /* Decrement reference count and check for underflow */ - - if (priv->refs == 0) - { - return ERROR; - } - - nxmutex_lock(&priv->lock); - if (--priv->refs) - { - nxmutex_unlock(&priv->lock); - kmm_free(priv); - return OK; - } - -#ifdef CONFIG_PM - /* Unregister power management callbacks */ - - pm_unregister(&priv->pm_cb); -#endif - - /* Disable power and other HW resource (GPIO's) */ - - stm32_1wire_deinit(priv); - nxmutex_unlock(&priv->lock); - - /* Free instance */ - - kmm_free(dev); - return OK; -} diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h deleted file mode 100644 index 9cb407b6ac401..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_1wire.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "stm32l4_uart.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_1wireinitialize - * - * Description: - * Initialize the selected 1-Wire port. And return a unique instance of - * struct struct onewire_dev_s. This function may be called to obtain - * multiple instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple 1-Wire interfaces) - * - * Returned Value: - * Valid 1-Wire device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct onewire_dev_s *stm32_1wireinitialize(int port); - -/**************************************************************************** - * Name: stm32_1wireuninitialize - * - * Description: - * De-initialize the selected 1-Wire port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_1wireinitialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_1wireuninitialize(struct onewire_dev_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 624a25ec93391..62639351de111 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -44,6 +44,17 @@ # error "Unsupported STM32L4 chip" #endif +/* Compatibility with the single APB1ENR clock-enable register of F1/F2/F4. + * This part splits APB1ENR into APB1ENR1/APB1ENR2; alias the legacy APB1ENR + * USART clock-enable names so the shared M3/M4 drivers keep working. + */ + +#define STM32_RCC_APB1ENR STM32_RCC_APB1ENR1 +#define RCC_APB1ENR_USART2EN RCC_APB1ENR1_USART2EN +#define RCC_APB1ENR_USART3EN RCC_APB1ENR1_USART3EN +#define RCC_APB1ENR_UART4EN RCC_APB1ENR1_UART4EN +#define RCC_APB1ENR_UART5EN RCC_APB1ENR1_UART5EN + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ From 438655e4342193f2d308caecd9837f92ec05a1df Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 3 Jun 2026 22:04:26 +0200 Subject: [PATCH 47/52] arch/arm/src/stm32: unify LSI driver and make RCC headers per-family Merge the per-family LSI oscillator drivers into a single core-agnostic common/stm32/stm32_lsi.c. To let a common/stm32 driver resolve RCC register definitions for every family without a central chip enumeration, the common/stm32/hardware/stm32_rcc.h dispatcher is removed and each family now provides its own hardware/stm32_rcc.h. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 4 +- arch/arm/src/common/stm32/Make.defs | 3 +- .../arm/src/common/stm32/hardware/stm32_rcc.h | 69 - .../src/common/stm32/stm32_hrtim_m3m4_v1.h | 2 +- .../stm32/{stm32_lsi_m0_v1.c => stm32_lsi.c} | 58 +- arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c | 94 -- .../hardware/{stm32c0_rcc.h => stm32_rcc.h} | 8 +- .../hardware/{stm32f0_rcc.h => stm32_rcc.h} | 8 +- .../{stm32f10xxx_rcc.h => stm32_rcc.h} | 8 +- .../{stm32f20xxx_rcc.h => stm32_rcc.h} | 8 +- arch/arm/src/stm32f3/hardware/stm32_rcc.h | 44 + .../{stm32f40xxx_rcc.h => stm32_rcc.h} | 8 +- arch/arm/src/stm32f7/CMakeLists.txt | 4 - arch/arm/src/stm32f7/Make.defs | 4 - arch/arm/src/stm32f7/stm32_lsi.c | 74 - .../hardware/{stm32g0_rcc.h => stm32_rcc.h} | 8 +- .../{stm32g4xxxx_rcc.h => stm32_rcc.h} | 8 +- arch/arm/src/stm32h5/CMakeLists.txt | 3 +- arch/arm/src/stm32h5/Make.defs | 2 +- arch/arm/src/stm32h5/hardware/stm32_rcc.h | 1222 +++++++++++++++- .../arm/src/stm32h5/hardware/stm32h5xxx_rcc.h | 1246 ----------------- arch/arm/src/stm32h5/stm32_lsi.c | 73 - arch/arm/src/stm32h5/stm32_usbdrdhost.c | 2 +- arch/arm/src/stm32h7/CMakeLists.txt | 4 - arch/arm/src/stm32h7/Make.defs | 4 - arch/arm/src/stm32h7/hardware/stm32_rcc.h | 1142 ++++++++++++++- .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 1161 --------------- arch/arm/src/stm32h7/stm32_lsi.c | 74 - .../hardware/{stm32l0_rcc.h => stm32_rcc.h} | 8 +- .../{stm32l15xxx_rcc.h => stm32_rcc.h} | 8 +- arch/arm/src/stm32l4/CMakeLists.txt | 1 - arch/arm/src/stm32l4/Make.defs | 2 +- arch/arm/src/stm32l4/hardware/stm32_rcc.h | 44 + arch/arm/src/stm32l4/stm32l4_lsi.c | 73 - arch/arm/src/stm32l5/CMakeLists.txt | 1 - arch/arm/src/stm32l5/Make.defs | 2 +- .../{stm32l562xx_rcc.h => stm32_rcc.h} | 8 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 73 - arch/arm/src/stm32l5/stm32l5_rcc.h | 2 +- arch/arm/src/stm32u5/CMakeLists.txt | 1 - arch/arm/src/stm32u5/Make.defs | 2 +- .../hardware/{stm32u5xx_rcc.h => stm32_rcc.h} | 6 +- arch/arm/src/stm32u5/stm32_lsi.c | 73 - arch/arm/src/stm32u5/stm32_rcc.h | 2 +- arch/arm/src/stm32wb/CMakeLists.txt | 1 - arch/arm/src/stm32wb/Make.defs | 2 +- .../hardware/{stm32wb_rcc.h => stm32_rcc.h} | 2 +- arch/arm/src/stm32wb/stm32wb_ipcc.c | 2 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 2 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 10 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 74 - arch/arm/src/stm32wl5/CMakeLists.txt | 1 - arch/arm/src/stm32wl5/Make.defs | 2 +- .../hardware/{stm32wl5_rcc.h => stm32_rcc.h} | 2 +- arch/arm/src/stm32wl5/stm32wl5_lsi.c | 73 - arch/arm/src/stm32wl5/stm32wl5_rcc.h | 2 +- 56 files changed, 2533 insertions(+), 3291 deletions(-) delete mode 100644 arch/arm/src/common/stm32/hardware/stm32_rcc.h rename arch/arm/src/common/stm32/{stm32_lsi_m0_v1.c => stm32_lsi.c} (60%) delete mode 100644 arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c rename arch/arm/src/stm32c0/hardware/{stm32c0_rcc.h => stm32_rcc.h} (99%) rename arch/arm/src/stm32f0/hardware/{stm32f0_rcc.h => stm32_rcc.h} (99%) rename arch/arm/src/stm32f1/hardware/{stm32f10xxx_rcc.h => stm32_rcc.h} (99%) rename arch/arm/src/stm32f2/hardware/{stm32f20xxx_rcc.h => stm32_rcc.h} (99%) create mode 100644 arch/arm/src/stm32f3/hardware/stm32_rcc.h rename arch/arm/src/stm32f4/hardware/{stm32f40xxx_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32f7/stm32_lsi.c rename arch/arm/src/stm32g0/hardware/{stm32g0_rcc.h => stm32_rcc.h} (99%) rename arch/arm/src/stm32g4/hardware/{stm32g4xxxx_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h delete mode 100644 arch/arm/src/stm32h5/stm32_lsi.c delete mode 100644 arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h delete mode 100644 arch/arm/src/stm32h7/stm32_lsi.c rename arch/arm/src/stm32l0/hardware/{stm32l0_rcc.h => stm32_rcc.h} (99%) rename arch/arm/src/stm32l1/hardware/{stm32l15xxx_rcc.h => stm32_rcc.h} (99%) create mode 100644 arch/arm/src/stm32l4/hardware/stm32_rcc.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_lsi.c rename arch/arm/src/stm32l5/hardware/{stm32l562xx_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32l5/stm32l5_lsi.c rename arch/arm/src/stm32u5/hardware/{stm32u5xx_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32u5/stm32_lsi.c rename arch/arm/src/stm32wb/hardware/{stm32wb_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32wb/stm32wb_rcc_lsi.c rename arch/arm/src/stm32wl5/hardware/{stm32wl5_rcc.h => stm32_rcc.h} (99%) delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_lsi.c diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 3d5bc5f2074ee..2a13abd4ace44 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -33,6 +33,7 @@ set(SRCS) list(APPEND SRCS stm32_waste.c) list(APPEND SRCS stm32_uid.c) +list(APPEND SRCS stm32_lsi.c) if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) @@ -49,7 +50,6 @@ if(CONFIG_STM32_COMMON_LEGACY) stm32_allocateheap_m3m4_v1.c stm32_start_m3m4_v1.c stm32_lse_m3m4_v1.c - stm32_lsi_m3m4_v1.c stm32_irq_m3m4_v1.c stm32_capture_m3m4_v1.c) @@ -356,7 +356,7 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() if(CONFIG_ARCH_CORTEXM0) - list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) list(APPEND SRCS stm32_gpio_m0_v1.c) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index f8ea27cc99b41..c1b981d38a514 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -41,6 +41,7 @@ ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) CHIP_CSRCS += stm32_waste.c CHIP_CSRCS += stm32_uid.c +CHIP_CSRCS += stm32_lsi.c ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c @@ -55,7 +56,6 @@ ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c CHIP_CSRCS += stm32_start_m3m4_v1.c CHIP_CSRCS += stm32_lse_m3m4_v1.c -CHIP_CSRCS += stm32_lsi_m3m4_v1.c CHIP_CSRCS += stm32_irq_m3m4_v1.c ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ $(CONFIG_STM32_HAVE_IP_USART_V2) \ @@ -407,7 +407,6 @@ else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c endif CHIP_CSRCS += stm32_start_m0_v1.c -CHIP_CSRCS += stm32_lsi_m0_v1.c ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) CHIP_CSRCS += stm32_gpio_m0_v1.c endif diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h deleted file mode 100644 index 308cd4d9df954..0000000000000 --- a/arch/arm/src/common/stm32/hardware/stm32_rcc.h +++ /dev/null @@ -1,69 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/hardware/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F1) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F2) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32F3) -# if defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F302X8) || \ - defined(CONFIG_STM32_STM32F302XC) || \ - defined(CONFIG_STM32_STM32F303XC) || \ - defined(CONFIG_STM32_STM32F303XE) -# include "hardware/stm32f30xxx_rcc.h" -# elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -# elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -# else -# error "Unsupported STM32F3 RCC" -# endif -#elif defined(CONFIG_ARCH_CHIP_STM32F4) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G4) -# include "hardware/stm32g4xxxx_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L1) -# include "hardware/stm32l15xxx_rcc.h" -#else -# error "Unsupported STM32 RCC" -#endif - -#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h index 026c6e2e7f310..d6580e8b3d323 100644 --- a/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -40,7 +40,7 @@ # include "hardware/stm32f33xxx_rcc.h" #elif defined(CONFIG_STM32_STM32G47XX) # include "hardware/stm32g47xxx_hrtim.h" -# include "hardware/stm32g4xxxx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error #endif diff --git a/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c b/arch/arm/src/common/stm32/stm32_lsi.c similarity index 60% rename from arch/arm/src/common/stm32/stm32_lsi_m0_v1.c rename to arch/arm/src/common/stm32/stm32_lsi.c index 19aa04dd4f037..d9fcc98322f06 100644 --- a/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_lsi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c + * arch/arm/src/common/stm32/stm32_lsi.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,22 +33,36 @@ * Pre-processor Definitions ****************************************************************************/ -/* STM32C0 uses the second CSR register for LSI. */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION -# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +/* The LSI enable/disable sequence is identical on every STM32, regardless of + * the CPU core. Only the register/bits that carry LSION/LSIRDY differ: + * + * - most families : RCC_CSR (LSION/LSIRDY) + * - STM32C0 : RCC_CSR2 (LSION/LSIRDY) + * - STM32WB : RCC_CSR (LSI1ON/LSI1RDY) + * - STM32H5/U5 : RCC_BDCR (LSION/LSIRDY) + * + * A single driver therefore serves all of them, selecting the register with + * the preprocessor below. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32H5) || defined(CONFIG_ARCH_CHIP_STM32U5) +# define STM32_RCC_LSI_REG STM32_RCC_BDCR +# define RCC_LSI_LSION RCC_BDCR_LSION +# define RCC_LSI_LSIRDY RCC_BDCR_LSIRDY +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# define STM32_RCC_LSI_REG STM32_RCC_CSR2 +# define RCC_LSI_LSION RCC_CSR2_LSION +# define RCC_LSI_LSIRDY RCC_CSR2_LSIRDY +#elif defined(CONFIG_ARCH_CHIP_STM32WB) +# define STM32_RCC_LSI_REG STM32_RCC_CSR +# define RCC_LSI_LSION RCC_CSR_LSI1ON +# define RCC_LSI_LSIRDY RCC_CSR_LSI1RDY +#else +# define STM32_RCC_LSI_REG STM32_RCC_CSR +# define RCC_LSI_LSION RCC_CSR_LSION +# define RCC_LSI_LSIRDY RCC_CSR_LSIRDY #endif -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -64,14 +78,14 @@ void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. + * bit in the controlling RCC register. */ - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_LSI_REG, 0, RCC_LSI_LSION); - /* Wait for the internal RC 40 kHz oscillator to be stable. */ + /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_LSI_REG) & RCC_LSI_LSIRDY) == 0); } /**************************************************************************** @@ -84,11 +98,11 @@ void stm32_rcc_enablelsi(void) void stm32_rcc_disablelsi(void) { - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. + /* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the + * LSION bit in the controlling RCC register. */ - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_LSI_REG, RCC_LSI_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c deleted file mode 100644 index 97ae757a001b7..0000000000000 --- a/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* STM32C0 uses the second CSR register for LSI. */ - -#ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION -# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit in the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32c0/hardware/stm32c0_rcc.h rename to arch/arm/src/stm32c0/hardware/stm32_rcc.h index 9784111a9b184..420831e39fc88 100644 --- a/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32c0/hardware/stm32c0_rcc.h + * arch/arm/src/stm32c0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H -#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -394,4 +394,4 @@ #define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0/hardware/stm32_rcc.h index 3bd0a3dab1763..8c257d1639776 100644 --- a/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h b/arch/arm/src/stm32f1/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h rename to arch/arm/src/stm32f1/hardware/stm32_rcc.h index 54828425c3c5e..87a2d7096caf2 100644 --- a/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h +++ b/arch/arm/src/stm32f1/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h + * arch/arm/src/stm32f1/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -471,4 +471,4 @@ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h b/arch/arm/src/stm32f2/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h rename to arch/arm/src/stm32f2/hardware/stm32_rcc.h index 31af35f07a1bf..b5d0597e006a2 100644 --- a/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h +++ b/arch/arm/src/stm32f2/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h + * arch/arm/src/stm32f2/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -503,4 +503,4 @@ #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28) /* Bits 28-30: PLLI2S division factor for I2S clocks */ #define RCC_PLLI2SCFGR_PLLI2SR_MASK (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_rcc.h b/arch/arm/src/stm32f3/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..6a18a3dea3f99 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_rcc.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +#else +# error "Unsupported STM32 F3 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32f4/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h rename to arch/arm/src/stm32f4/hardware/stm32_rcc.h index d4e56f3f29654..1fd8fa4670f6f 100644 --- a/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h + * arch/arm/src/stm32f4/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -937,4 +937,4 @@ # define RCC_DCKCFGR2_SPDIFRXSEL_PLLI2S (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLLI2S clock is selected as SPDIF-Rx clock */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 94d52db4e7854..518e0b6997f0e 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -85,10 +85,6 @@ if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) - list(APPEND SRCS stm32_lsi.c) -endif() - if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index a3a7082a0c898..b10e4068ae5b7 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -84,10 +84,6 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) -CHIP_CSRCS += stm32_lsi.c -endif - ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif diff --git a/arch/arm/src/stm32f7/stm32_lsi.c b/arch/arm/src/stm32f7/stm32_lsi.c deleted file mode 100644 index cc5e46b4fba92..0000000000000 --- a/arch/arm/src/stm32f7/stm32_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32g0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32g0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32g0/hardware/stm32_rcc.h index 3c5f8ca45217e..2f7100afd2302 100644 --- a/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32g0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32g0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -363,4 +363,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h b/arch/arm/src/stm32g4/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h rename to arch/arm/src/stm32g4/hardware/stm32_rcc.h index 6070eeea00fb7..bc4647691ca5f 100644 --- a/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h +++ b/arch/arm/src/stm32g4/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h + * arch/arm/src/stm32g4/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -689,4 +689,4 @@ #define RCC_APB1ENR_TIM4EN RCC_APB1ENR1_TIM4EN #define RCC_APB1ENR_TIM5EN RCC_APB1ENR1_TIM5EN -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 249a64c3136a3..8d6fa1308f51e 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -40,8 +40,7 @@ list( stm32_start.c stm32_pwr.c stm32_timerisr.c - stm32_lse.c - stm32_lsi.c) + stm32_lse.c) if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index fd569978cb47f..e48727247eee3 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -38,7 +38,7 @@ endif CHIP_CSRCS += stm32_gpio.c stm32_irq.c stm32_lowputc.c stm32_rcc.c CHIP_CSRCS += stm32_start.c stm32_pwr.c stm32_timerisr.c -CHIP_CSRCS += stm32_lse.c stm32_lsi.c +CHIP_CSRCS += stm32_lse.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index ecfa04f7d52db..eb2c965d7b5ff 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -28,13 +28,1219 @@ ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_STM32H52XXX) || defined(CONFIG_STM32_STM32H53XXX) || \ - defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX) -# include "hardware/stm32h5xxx_rcc.h" -#else -# error "Unsupported STM32 H5 rcc" -#endif +#if defined(CONFIG_STM32_STM32H5XXXX) -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H */ \ No newline at end of file +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_HSICFGR_OFFSET 0x0010 /* HSI Calibration Register */ +#define STM32_RCC_CRRCR_OFFSET 0x0014 /* RCC clock recovery RC register */ +#define STM32_RCC_CFGR1_OFFSET 0x001c /* RCC clock configuration register 1 */ +#define STM32_RCC_CFGR2_OFFSET 0x0020 /* RCC clock configuration register 2 */ +#define STM32_RCC_PLL1CFGR_OFFSET 0x0028 /* RCC PLL1 configuration register */ +#define STM32_RCC_PLL2CFGR_OFFSET 0x002c /* RCC PLL2 configuration register */ +#define STM32_RCC_PLL3CFGR_OFFSET 0x0030 /* RCC PLL3 configuration register */ +#define STM32_RCC_PLL1DIVR_OFFSET 0x0034 /* RCC PLL1 dividers register */ +#define STM32_RCC_PLL1FRACR_OFFSET 0x0038 /* RCC PLL1 fractional divider register */ +#define STM32_RCC_PLL2DIVR_OFFSET 0x003c /* RCC PLL2 dividers register */ +#define STM32_RCC_PLL2FRACR_OFFSET 0x0040 /* RCC PLL2 fractional divider register */ +#define STM32_RCC_PLL3DIVR_OFFSET 0x0044 /* RCC PLL3 dividers register */ +#define STM32_RCC_PLL3FRACR_OFFSET 0x0048 /* RCC PLL3 fractional divider register */ +#define STM32_RCC_CIER_OFFSET 0x0050 /* RCC clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x0054 /* RCC clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0058 /* RCC clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0060 /* RCC AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0064 /* RCC AHB2 peripheral reset register 1 */ +#define STM32_RCC_AHB4RSTR_OFFSET 0x006c /* RCC AHB4 peripheral reset register*/ +#define STM32_RCC_APB1LRSTR_OFFSET 0x0074 /* RCC APB1 peripheral reset register 1 */ +#define STM32_RCC_APB1HRSTR_OFFSET 0x0078 /* RCC APB1 peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x007c /* RCC APB2 peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0080 /* RCC APB3 peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0088 /* RCC AHB1 peripheral clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x008c /* RCC AHB2 peripheral clock enable register */ +#define STM32_RCC_AHB4ENR_OFFSET 0x0094 /* RCC AHB4 peripheral clock enable register */ +#define STM32_RCC_APB1LENR_OFFSET 0x009c /* RCC APB1 peripheral clock enable register 1 */ +#define STM32_RCC_APB1HENR_OFFSET 0x00a0 /* RCC APB1 peripheral clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x00a4 /* RCC APB2 peripheral clock enable register */ +#define STM32_RCC_APB3ENR_OFFSET 0x00a8 /* RCC APB3 peripheral clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x00b0 /* RCC AHB1 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x00b4 /* RCC AHB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_AHB4LPENR_OFFSET 0x00bc /* RCC AHB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_APB1LPENR1_OFFSET 0x00c4 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 */ +#define STM32_RCC_APB1LPENR2_OFFSET 0x00c8 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 */ +#define STM32_RCC_APB2LPENR_OFFSET 0x00cc /* RCC APB2 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_APB3LPENR_OFFSET 0x00d0 /* RCC APB3 peripheral clocks enable in Sleep and Stop modes register */ +#define STM32_RCC_CCIPR1_OFFSET 0x00d8 /* RCC peripherals independent clock configuration register 1 */ +#define STM32_RCC_CCIPR2_OFFSET 0x00dc /* RCC peripherals independent clock configuration register 2 */ +#define STM32_RCC_CCIPR3_OFFSET 0x00e0 /* RCC peripherals independent clock configuration register 3 */ +#define STM32_RCC_CCIPR4_OFFSET 0x00e4 /* RCC peripherals independent clock configuration register 5 */ +#define STM32_RCC_CCIPR5_OFFSET 0x00e8 /* RCC peripherals independent clock configuration register 5 */ +#define STM32_RCC_BDCR_OFFSET 0x00f0 /* RCC Backup domain control register */ +#define STM32_RCC_RSR_OFFSET 0x00f4 /* RCC control/status register */ /* TODO: CSR in U5 */ +#define STM32_RCC_SECCFGR_OFFSET 0x0110 /* RCC secure configuration register */ +#define STM32_RCC_PRIVCFGR_OFFSET 0x0114 /* RCC privilege configuration register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_HSICFGR (STM32_RCC_BASE + STM32_RCC_HSICFGR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CFGR1 (STM32_RCC_BASE + STM32_RCC_CFGR1_OFFSET) +#define STM32_RCC_CFGR2 (STM32_RCC_BASE + STM32_RCC_CFGR2_OFFSET) +#define STM32_RCC_PLL1CFGR (STM32_RCC_BASE + STM32_RCC_PLL1CFGR_OFFSET) +#define STM32_RCC_PLL2CFGR (STM32_RCC_BASE + STM32_RCC_PLL2CFGR_OFFSET) +#define STM32_RCC_PLL3CFGR (STM32_RCC_BASE + STM32_RCC_PLL3CFGR_OFFSET) +#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) +#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) +#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) +#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) +#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) +#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) +#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) +#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) +#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) +#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) +#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) +#define STM32_RCC_APB1LPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR1_OFFSET) +#define STM32_RCC_APB1HPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR2_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) +#define STM32_RCC_CCIPR1 (STM32_RCC_BASE + STM32_RCC_CCIPR1_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CCIPR3 (STM32_RCC_BASE + STM32_RCC_CCIPR3_OFFSET) +#define STM32_RCC_CCIPR4 (STM32_RCC_BASE + STM32_RCC_CCIPR4_OFFSET) +#define STM32_RCC_CCIPR5 (STM32_RCC_BASE + STM32_RCC_CCIPR5_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_PRIVCFGR (STM32_RCC_BASE + STM32_RCC_PRIVCFGR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Clock control register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ +#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */ +#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK)) +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */ + +#define RCC_CR_CSION (1 << 8) /* Bit 8: CSI clock enable */ +#define RCC_CR_CSIRDY (1 << 9) /* Bit 9: CSI clock ready flag */ +#define RCC_CR_CSIKERON (1 << 10) /* Bit 10: CSI clock enable in Stop mode */ + +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready flag */ + +#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ +#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */ +#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock + * type in bypass mode */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: PLL2 enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: PLL2 clock ready flag */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: PLL3 enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: PLL3 clock ready flag */ + +/* HSI Calibration register */ + +#define RCC_HSICFGR_HSITRIM_SHIFT (16) /* Bits 22-16: Internal High Speed clock trimming */ +#define RCC_HSICFGR_HSITRIM_MASK (0x7f << RCC_HSICFGR_HSITRIM_SHIFT) +#define RCC_HSICFGR_HSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_HSICFGR_HSICAL_MASK (0xfff << RCC_HSICFGR_HSICAL_SHIFT) + +/* Clock Recovery RC register */ + +#define RCC_CRRCR_HSI48CAL_SHIFT (0) /* Bits 9-0: Internal RC 48MHz Clock Calibration */ +#define RCC_CRRCR_HSI48CAL_MASK (0x3ff << RCC_CRRCR_HSI48CAL_SHIFT) + +/* CSI Calibration register */ + +#define RCC_CSICFGR_CSITRIM_SHIFT (16) /* Bits 21-16: Internal High Speed clock trimming */ +#define RCC_CSICFGR_CSITRIM_MASK (0x3f << RCC_CSICFGR_CSITRIM_SHIFT) +#define RCC_CSICFGR_CSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ +#define RCC_CSICFGR_CSICAL_MASK (0xff << RCC_CSICFGR_CSICAL_SHIFT) + +/* Clock configuration register 1 */ + +#define RCC_CFGR1_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ +#define RCC_CFGR1_SW_MASK (3 << RCC_CFGR1_SW_SHIFT) +# define RCC_CFGR1_SW_MSI (0 << RCC_CFGR1_SW_SHIFT) /* 00: MSI selected as system clock */ +# define RCC_CFGR1_SW_HSI16 (1 << RCC_CFGR1_SW_SHIFT) /* 00: HSI16 selected as system clock */ +# define RCC_CFGR1_SW_HSE (2 << RCC_CFGR1_SW_SHIFT) /* 01: HSE selected as system clock */ +# define RCC_CFGR1_SW_PLL (3 << RCC_CFGR1_SW_SHIFT) /* 10: PLL selected as system clock */ + +#define RCC_CFGR1_SWS_SHIFT (3) /* Bits 3-4: System Clock Switch Status */ +#define RCC_CFGR1_SWS_MASK (3 << RCC_CFGR1_SWS_SHIFT) +# define RCC_CFGR1_SWS_MSI (0 << RCC_CFGR1_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSI16 (1 << RCC_CFGR1_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */ +# define RCC_CFGR1_SWS_HSE (2 << RCC_CFGR1_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ +# define RCC_CFGR1_SWS_PLL (3 << RCC_CFGR1_SWS_SHIFT) /* 10: PLL used as system clock */ + +#define RCC_CFGR1_STOPWUCK (1 << 6) /* System clock selection after a wakeup from system stop */ +#define RCC_CFGR1_STOPKERWUCK (1 << 7) /* Kernel clock selection after a wakeup from system stop */ + +#define RCC_CFGR1_RTCPRE_SHIFT (8) /* Bits 13-8: RTC prescaler */ +#define RCC_CFGR1_RTCPRE_MASK (0x3f << RCC_CFGR1_RTCPRE_SHIFT) +# define RCC_CFGR1_RTCPRE_HSE (0 << RCC_CFGR1_RTCPRE_SHIFT) /* 0xxx: HSE not divided */ +# define RCC_CFGR1_RTCPRE_HSEd2 (2 << RCC_CFGR1_RTCPRE_SHIFT) /* 10: HSE divided by 2 */ +# define RCC_CFGR1_RTCPRE_HSEd4 (4 << RCC_CFGR1_RTCPRE_SHIFT) /* 100: HSE divided by 4 */ +# define RCC_CFGR1_RTCPRE_HSEd8 (8 << RCC_CFGR1_RTCPRE_SHIFT) /* 1000: HSE divided by 8 */ +# define RCC_CFGR1_RTCPRE_HSEd16 (16 << RCC_CFGR1_RTCPRE_SHIFT) /* 10000: HSE divided by 16 */ +# define RCC_CFGR1_RTCPRE_HSEd32 (32 << RCC_CFGR1_RTCPRE_SHIFT) /* 100000: HSE divided by 32 */ +# define RCC_CFGR1_RTCPRE_HSEd63 (63 << RCC_CFGR1_RTCPRE_SHIFT) /* 111111: HSE divided by 63 */ + +#define RCC_CFGR1_TIMPRE (1 << 15) /* timers clocks prescaler selection */ + +#define RCC_CFGR1_MCO1PRE_SHIFT (18) /* Bits 21-18: MCO1 Prescaler */ +#define RCC_CFGR1_MCO1PRE_MASK (0xf << RCC_CFGR1_MCO1PRE_SHIFT) +# define RCC_CFGR1_MCO1PRE_MCO1 (0 << RCC_CFGR1_MCO1PRE_SHIFT) /* 0xx: MCO1 not divided */ +# define RCC_CFGR1_MCO1PRE_MCO1d2 (2 << RCC_CFGR1_MCO1PRE_SHIFT) /* 10: MCO1 divided by 2 */ +# define RCC_CFGR1_MCO1PRE_MCO1d4 (4 << RCC_CFGR1_MCO1PRE_SHIFT) /* 100: MCO1 divided by 4 */ +# define RCC_CFGR1_MCO1PRE_MCO1d8 (8 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1000: MCO1 divided by 8 */ +# define RCC_CFGR1_MCO1PRE_MCO1d15 (15 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1111: MCO1 divided by 15 */ + +#define RCC_CFGR1_MCO1SEL_SHIFT (22) /* Bits 24-22: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO1SEL_MASK (0x7 << RCC_CFGR1_MCO1SEL_SHIFT) +# define RCC_CFGR1_MCO1SEL_HSI (0 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0000: HSI clock selected */ +# define RCC_CFGR1_MCO1SEL_LSE (1 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0001: LSE clock selected */ +# define RCC_CFGR1_MCO1SEL_HSE (2 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO1SEL_PLL1 (3 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO1SEL_HSI48 (4 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0100: HSI48 clock selected */ + +#define RCC_CFGR1_MCO2PRE_SHIFT (25) /* Bits 28-25: MCO2 Prescaler */ +#define RCC_CFGR1_MCO2PRE_MASK (0xf << RCC_CFGR1_MCO2PRE_SHIFT) +# define RCC_CFGR1_MCO2PRE_MCO2 (0 << RCC_CFGR1_MCO2PRE_SHIFT) /* 0xx: MCO2 not divided */ +# define RCC_CFGR1_MCO2PRE_MCO2d2 (2 << RCC_CFGR1_MCO2PRE_SHIFT) /* 10: MCO2 divided by 2 */ +# define RCC_CFGR1_MCO2PRE_MCO2d4 (4 << RCC_CFGR1_MCO2PRE_SHIFT) /* 100: MCO2 divided by 4 */ +# define RCC_CFGR1_MCO2PRE_MCO2d8 (8 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1000: MCO2 divided by 8 */ +# define RCC_CFGR1_MCO2PRE_MCO2d15 (15 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1111: MCO2 divided by 15 */ + +#define RCC_CFGR1_MCO2SEL_SHIFT (29) /* Bits 31-29: Microcontroller Clock Output1 */ +#define RCC_CFGR1_MCO2SEL_MASK (0x7 << RCC_CFGR1_MCO2SEL_SHIFT) +# define RCC_CFGR1_MCO2SEL_SYSCLLK (0 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0000: Main SYSCLLK selected */ +# define RCC_CFGR1_MCO2SEL_PLL2 (1 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0001: Main PLL2 selected */ +# define RCC_CFGR1_MCO2SEL_HSE (2 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0010: HSE clock selected */ +# define RCC_CFGR1_MCO2SEL_PLL1 (3 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0011: Main PLL1 selected */ +# define RCC_CFGR1_MCO2SEL_CSI (4 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0100: CSI clock selected */ +# define RCC_CFGR1_MCO2SEL_LSI (5 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0101: LSI clock selected */ + +/* Clock configuration register 2 */ + +#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 3-0: HPRE Prescaler */ +#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT) +# define RCC_CFGR2_HPRE_SYSCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xx: SYSCLK not divided */ +# define RCC_CFGR2_HPRE_SYSCLKd2 (8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ +# define RCC_CFGR2_HPRE_SYSCLKd4 (9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ +# define RCC_CFGR2_HPRE_SYSCLKd8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ +# define RCC_CFGR2_HPRE_SYSCLKd16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ +# define RCC_CFGR2_HPRE_SYSCLKd64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ +# define RCC_CFGR2_HPRE_SYSCLKd128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ +# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ +# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ + +#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 6-4: PPRE1 Prescaler */ +#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT) +# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */ +#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT) +# define RCC_CFGR2_PPRE2_HCLK1 (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE2_HCLK1d2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE2_HCLK1d4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE2_HCLK1d8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE2_HCLK1d16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK1 divided by 16 */ + +#define RCC_CFGR2_PPRE3_SHIFT (12) /* Bits 14-12: PPRE3 Prescaler */ +#define RCC_CFGR2_PPRE3_MASK (0x7 << RCC_CFGR2_PPRE3_SHIFT) +# define RCC_CFGR2_PPRE3_HCLK1 (0 << RCC_CFGR2_PPRE3_SHIFT) /* 0xx: HCLK1 not divided */ +# define RCC_CFGR2_PPRE3_HCLK1d2 (4 << RCC_CFGR2_PPRE3_SHIFT) /* 100: HCLK1 divided by 2 */ +# define RCC_CFGR2_PPRE3_HCLK1d4 (5 << RCC_CFGR2_PPRE3_SHIFT) /* 101: HCLK1 divided by 4 */ +# define RCC_CFGR2_PPRE3_HCLK1d8 (6 << RCC_CFGR2_PPRE3_SHIFT) /* 110: HCLK1 divided by 8 */ +# define RCC_CFGR2_PPRE3_HCLK1d16 (7 << RCC_CFGR2_PPRE3_SHIFT) /* 111: HCLK1 divided by 16 */ + +#define RCC_CFGR2_AHB1DIS (1 << 16) /* AHB1 clock disable */ +#define RCC_CFGR2_AHB2DIS (1 << 17) /* AHB2 clock disable */ +#define RCC_CFGR2_AHB4DIS (1 << 19) /* AHB4 clock disable */ +#define RCC_CFGR2_APB1DIS (1 << 20) /* APB1 clock disable */ +#define RCC_CFGR2_APB2DIS (1 << 21) /* APB2 clock disable */ +#define RCC_CFGR2_APB3DIS (1 << 22) /* APB3 clock disable */ + +/* PLL1 configuration register */ + +#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL1CFGR_PLL1SRC_MASK (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) +# define RCC_PLL1CFGR_PLL1SRC_NONE (0 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL1CFGR_PLL1SRC_HSI (1 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_CSI (2 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL1CFGR_PLL1SRC_HSE (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) +# define RCC_PLL1CFGR_PLL1RGE_1_2M (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_2_4M (1 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL1CFGR_PLL1RGE_4_8M (2 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL1CFGR_PLL1RGE_8_16M (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* PLL1 Fractional Latch Enable */ +#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5) /* PLL1 VCO Selection */ + +#define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL1CFGR_PLL1M_MASK (0x3f << RCC_PLL1CFGR_PLL1M_SHIFT) +# define RCC_PLL1CFGR_PLL1M(n) ((n) << RCC_PLL1CFGR_PLL1M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL1CFGR_PLL1PEN (1 << 16) /* PLL1 DIVP divder output enable */ +#define RCC_PLL1CFGR_PLL1QEN (1 << 17) /* PLL1 DIVQ divder output enable */ +#define RCC_PLL1CFGR_PLL1REN (1 << 18) /* PLL1 DIVR divder output enable */ + +/* PLL2 configuration register */ + +#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL2CFGR_PLL2SRC_MASK (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) +# define RCC_PLL2CFGR_PLL2SRC_NONE (0 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL2CFGR_PLL2SRC_HSI (1 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_CSI (2 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL2CFGR_PLL2SRC_HSE (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL2CFGR_PLL2RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL2CFGR_PLL2RGE_MASK (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) +# define RCC_PLL2CFGR_PLL2RGE_1_2M (0 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_2_4M (1 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_4_8M (2 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz */ +# define RCC_PLL2CFGR_PLL2RGE_8_16M (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz */ + +#define RCC_PLL2CFGR_PLL2FRACEN (1 << 4) /* PLL2 Fractional Latch Enable */ +#define RCC_PLL2CFGR_PLL2VCOSEL (1 << 5) /* PLL2 VCO Selection */ + +#define RCC_PLL2CFGR_PLL2M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL2CFGR_PLL2M_MASK (0x3f << RCC_PLL2CFGR_PLL2M_SHIFT) +# define RCC_PLL2CFGR_PLL2M(n) ((n) << RCC_PLL2CFGR_PLL2M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL2CFGR_PLL2PEN (1 << 16) /* PLL2 DIVP divder output enable */ +#define RCC_PLL2CFGR_PLL2QEN (1 << 17) /* PLL2 DIVQ divder output enable */ +#define RCC_PLL2CFGR_PLL2REN (1 << 18) /* PLL2 DIVR divder output enable */ + +/* PLL3 configuration register */ + +#define RCC_PLL3CFGR_PLL3SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) + * entry clock source */ +#define RCC_PLL3CFGR_PLL3SRC_MASK (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) +# define RCC_PLL3CFGR_PLL3SRC_NONE (0 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 000: No clock sent to PLLs */ +# define RCC_PLL3CFGR_PLL3SRC_HSI (1 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 001: HSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_CSI (2 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 010: CSI selected as PLL source */ +# define RCC_PLL3CFGR_PLL3SRC_HSE (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 011: HSE selected as PLL source */ + +#define RCC_PLL3CFGR_PLL3RGE_SHIFT (2) /* Bit 3-2: */ +#define RCC_PLL3CFGR_PLL3RGE_MASK (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) +# define RCC_PLL3CFGR_PLL3RGE_1_2M (0 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_2_4M (1 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ +# define RCC_PLL3CFGR_PLL3RGE_4_8M (2 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ +# define RCC_PLL3CFGR_PLL3RGE_8_16M (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ + +#define RCC_PLL3CFGR_PLL3FRACEN (1 << 4) /* PLL3 Fractional Latch Enable */ +#define RCC_PLL3CFGR_PLL3VCOSEL (1 << 5) /* PLL3 VCO Selection */ + +#define RCC_PLL3CFGR_PLL3M_SHIFT (8) /* Bit 13-8: */ +#define RCC_PLL3CFGR_PLL3M_MASK (0x3f << RCC_PLL3CFGR_PLL3M_SHIFT) +# define RCC_PLL3CFGR_PLL3M(n) ((n) << RCC_PLL3CFGR_PLL3M_SHIFT) /* m = 1..63 */ + +#define RCC_PLL3CFGR_PLL3PEN (1 << 16) /* PLL3 DIVP divder output enable */ +#define RCC_PLL3CFGR_PLL3QEN (1 << 17) /* PLL3 DIVQ divder output enable */ +#define RCC_PLL3CFGR_PLL3REN (1 << 18) /* PLL3 DIVR divder output enable */ + +/* PLL1 dividers register */ + +#define RCC_PLL1DIVR_PLL1N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL1DIVR_PLL1N_MASK (0x1ff << RCC_PLL1DIVR_PLL1N_SHIFT) +# define RCC_PLL1DIVR_PLL1N(n) ((n-1) << RCC_PLL1DIVR_PLL1N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL1DIVR_PLL1P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL1DIVR_PLL1P_MASK (0x7f << RCC_PLL1DIVR_PLL1P_SHIFT) +# define RCC_PLL1DIVR_PLL1P(n) ((n-1) << RCC_PLL1DIVR_PLL1P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL1DIVR_PLL1Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL1DIVR_PLL1Q_MASK (0x7f << RCC_PLL1DIVR_PLL1Q_SHIFT) +# define RCC_PLL1DIVR_PLL1Q(n) ((n-1) << RCC_PLL1DIVR_PLL1Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL1DIVR_PLL1R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL1DIVR_PLL1R_MASK (0x7f << RCC_PLL1DIVR_PLL1R_SHIFT) +# define RCC_PLL1DIVR_PLL1R(n) ((n-1) << RCC_PLL1DIVR_PLL1R_SHIFT) /* m = 1..128 */ + +/* PLL1 fractional divider register */ + +#define RCC_PLL1FRACR_PLL1FRACN_SHIFT (3) +#define RCC_PLL1FRACR_PLL1FRACN_MASK (0x1fff << RCC_PLL1FRACR_PLL1FRACN_SHIFT) +#define RCC_PLL1FRACR_PLL1FRACN(n) (n << RCC_PLL1FRACR_PLL1FRACN_SHIFT) /* m = 0..8192 */ + +/* PLL2 dividers register */ + +#define RCC_PLL2DIVR_PLL2N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL2DIVR_PLL2N_MASK (0x1ff << RCC_PLL2DIVR_PLL2N_SHIFT) +# define RCC_PLL2DIVR_PLL2N(n) ((n-1) << RCC_PLL2DIVR_PLL2N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL2DIVR_PLL2P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL2DIVR_PLL2P_MASK (0x7f << RCC_PLL2DIVR_PLL2P_SHIFT) +# define RCC_PLL2DIVR_PLL2P(n) ((n-1) << RCC_PLL2DIVR_PLL2P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL2DIVR_PLL2Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL2DIVR_PLL2Q_MASK (0x7f << RCC_PLL2DIVR_PLL2Q_SHIFT) +# define RCC_PLL2DIVR_PLL2Q(n) ((n-1) << RCC_PLL2DIVR_PLL2Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL2DIVR_PLL2R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL2DIVR_PLL2R_MASK (0x7f << RCC_PLL2DIVR_PLL2R_SHIFT) +# define RCC_PLL2DIVR_PLL2R(n) ((n-1) << RCC_PLL2DIVR_PLL2R_SHIFT) /* m = 1..128 */ + +/* PLL2 fractional divider register */ + +#define RCC_PLL2FRACR_PLL2FRACN_SHIFT (3) +#define RCC_PLL2FRACR_PLL2FRACN_MASK (0x1fff << RCC_PLL2FRACR_PLL2FRACN_SHIFT) +#define RCC_PLL2FRACR_PLL2FRACN(n) (n << RCC_PLL2FRACR_PLL2FRACN_SHIFT) /* m = 0..8192 */ + +/* PLL3 dividers register */ + +#define RCC_PLL3DIVR_PLL3N_SHIFT (0) /* Bits 8-0: */ +#define RCC_PLL3DIVR_PLL3N_MASK (0x1ff << RCC_PLL3DIVR_PLL3N_SHIFT) +# define RCC_PLL3DIVR_PLL3N(n) ((n-1) << RCC_PLL3DIVR_PLL3N_SHIFT) /* m = 4..512 */ + +#define RCC_PLL3DIVR_PLL3P_SHIFT (9) /* Bits 15-9: */ +#define RCC_PLL3DIVR_PLL3P_MASK (0x7f << RCC_PLL3DIVR_PLL3P_SHIFT) +# define RCC_PLL3DIVR_PLL3P(n) ((n-1) << RCC_PLL3DIVR_PLL3P_SHIFT) /* m = 2..128 evens */ + +#define RCC_PLL3DIVR_PLL3Q_SHIFT (16) /* Bits 22-16: */ +#define RCC_PLL3DIVR_PLL3Q_MASK (0x7f << RCC_PLL3DIVR_PLL3Q_SHIFT) +# define RCC_PLL3DIVR_PLL3Q(n) ((n-1) << RCC_PLL3DIVR_PLL3Q_SHIFT) /* m = 1..128 */ + +#define RCC_PLL3DIVR_PLL3R_SHIFT (24) /* Bits 30-24: */ +#define RCC_PLL3DIVR_PLL3R_MASK (0x7f << RCC_PLL3DIVR_PLL3R_SHIFT) +# define RCC_PLL3DIVR_PLL3R(n) ((n-1) << RCC_PLL3DIVR_PLL3R_SHIFT) /* m = 1..128 */ + +/* PLL3 fractional divider register */ + +#define RCC_PLL3FRACR_PLL3FRACN_SHIFT (3) +#define RCC_PLL3FRACR_PLL3FRACN_MASK (0x1fff << RCC_PLL3FRACR_PLL3FRACN_SHIFT) +#define RCC_PLL3FRACR_PLL3FRACN(n) (n << RCC_PLL3FRACR_PLL3FRACN_SHIFT) /* m = 0..8192 */ + +/* Clock interrupt enable register */ + +#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */ +#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */ +#define RCC_CIER_CSIRDYIE (1 << 2) /* Bit 2: CSI Ready Interrupt Enable */ +#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */ +#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */ +#define RCC_CIER_HSI48RDYIE (1 << 5) /* Bit 5: HSI48 Ready Interrupt Enable */ +#define RCC_CIER_PLL1RDYIE (1 << 6) /* Bit 6: PLL1 Ready Interrupt Enable */ +#define RCC_CIER_PLL2RDYIE (1 << 7) /* Bit 7: PLL2 Ready Interrupt Enable */ +#define RCC_CIER_PLL3RDYIE (1 << 8) /* Bit 8: PLL3 Ready Interrupt Enable */ + +/* Clock interrupt flag register */ + +#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CIFR_CSIRDYF (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CIFR_HSI48RDYF (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CIFR_PLL1RDYF (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CIFR_PLL2RDYF (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CIFR_PLL3RDYF (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CIFR_HSECSSF (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* Clock interrupt clear register */ + +#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ +#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ +#define RCC_CICR_CSIRDYC (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ +#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ +#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ +#define RCC_CICR_HSI48RDYC (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ +#define RCC_CICR_PLL1RDYC (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ +#define RCC_CICR_PLL2RDYC (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ +#define RCC_CICR_PLL3RDYC (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ +#define RCC_CICR_HSECSSC (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_GPDMA1RST (1 << 0) /* Bit 0: GPDMA1 reset */ +#define RCC_AHB1RSTR_GPDMA2RST (1 << 1) /* Bit 1: GPDMA2 reset */ +#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ +#define RCC_AHB1RSTR_CORDICRST (1 << 14) /* Bit 14: CORDIC reset */ +#define RCC_AHB1RSTR_FMACRST (1 << 15) /* Bit 15: FMAC reset */ +#define RCC_AHB1RSTR_RAMCFGRST (1 << 17) /* Bit 17: RAMCFG reset */ +#define RCC_AHB1RSTR_ETHRST (1 << 19) /* Bit 19: ETH reset */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_GPIORST(n) (1 << (n)) +#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ +#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ +#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ +#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ +#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ +#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ +#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ +#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ +#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ +#define RCC_AHB2RSTR_ADCRST (1 << 10) /* Bit 10: ADC interface reset (common to all ADCs) */ +#define RCC_AHB2RSTR_DACRST (1 << 11) /* Bit 11: DAC Block reset */ +#define RCC_AHB2RSTR_DCMI_PSSIRST (1 << 12) /* Bit 12: Digital Camera Interface block reset */ +#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */ +#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH block reset */ +#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */ +#define RCC_AHB2RSTR_PKARST (1 << 19) /* Bit 19: Public Key Accelerator module reset */ +#define RCC_AHB2RSTR_SAESRST (1 << 20) /* Bit 20: SAES block reset */ + +/* AHB4 peripheral reset register */ + +#define RCC_AHB4RSTR_OTFDEC1RST (1 << 7) /* Bit 0: OTFDEC1 block reset */ +#define RCC_AHB4RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1RST blocks reset */ +#define RCC_AHB4RSTR_SDMMC2RST (1 << 12) /* Bit 12: SDMMC2RST blocks reset */ +#define RCC_AHB4RSTR_FMCRST (1 << 16) /* Bit 16: FMC block reset */ +#define RCC_AHB4RSTR_OSPI1RST (1 << 20) /* Bit 20: OCTOSPI1 block reset */ + +/* APB1 Peripheral reset register 1 */ + +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 5: TIM12 reset */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 5: TIM13 reset */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 5: TIM14 reset */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* Bit 19: UART4 reset */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* Bit 20: UART5 reset */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ +#define RCC_APB1LRSTR_I3C1RST (1 << 23) /* Bit 23: I3C1 reset */ +#define RCC_APB1LRSTR_CRSRST (1 << 24) /* Bit 24: CRS reset */ +#define RCC_APB1LRSTR_USART6RST (1 << 25) /* Bit 25: USART6 reset */ +#define RCC_APB1LRSTR_USART10RST (1 << 26) /* Bit 26: USART10 reset */ +#define RCC_APB1LRSTR_USART11RST (1 << 27) /* Bit 27: USART11 reset */ +#define RCC_APB1LRSTR_CECRST (1 << 28) /* Bit 28: CEC reset */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* Bit 30: UART7 reset */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* Bit 31: UART8 reset */ + +/* APB1 Peripheral reset register 2 */ + +#define RCC_APB1HRSTR_UART9RST (1 << 0) /* Bit 0: UART9 reset */ +#define RCC_APB1HRSTR_UART12RST (1 << 1) /* Bit 1: UART12 reset */ +#define RCC_APB1HRSTR_DTSRST (1 << 3) /* Bit 3: DTS reset */ +#define RCC_APB1HRSTR_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */ +#define RCC_APB1HRSTR_FDCANRST (1 << 9) /* Bit 9: FDCAN reset */ +#define RCC_APB1HRSTR_UCPD1RST (1 << 23) /* Bit 23: UCPD1 reset */ + +/* APB2 Peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */ +#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ +#define RCC_APB2RSTR_SPI4RST (1 << 19) /* Bit 19: SPI4 reset */ +#define RCC_APB2RSTR_SPI67RST (1 << 20) /* Bit 20: SPI6 reset */ +#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ +#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ +#define RCC_APB2RSTR_USBRST (1 << 24) /* Bit 24: USB reset */ + +/* APB3 Peripheral reset register */ + +#define RCC_APB3RSTR_SPI5RST (1 << 5) /* Bit 5: SPI5 reset */ +#define RCC_APB3RSTR_LPUART1RST (1 << 6) /* Bit 6: LPUART1 reset */ +#define RCC_APB3RSTR_I2C3RST (1 << 7) /* Bit 7: I2C3 reset */ +#define RCC_APB3RSTR_I2C4RST (1 << 8) /* Bit 8: I2C4 reset */ +#define RCC_APB3RSTR_I3C2RST (1 << 9) /* Bit 9: I3C2 reset */ +#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ +#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ +#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ +#define RCC_APB3RSTR_LPTIM5RST (1 << 14) /* Bit 14: LPTIM5 reset */ +#define RCC_APB3RSTR_LPTIM6RST (1 << 15) /* Bit 15: LPTIM6 reset */ +#define RCC_APB3RSTR_VREFRST (1 << 20) /* Bit 20: VREF reset */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ +#define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ +#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interface clock enable */ +#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ +#define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ +#define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ +#define RCC_AHB1ENR_RAMCFGEN (1 << 17) /* Bit 17: RAMCFG clock enable */ +#define RCC_AHB1ENR_ETHEN (1 << 19) /* Bit 19: ETH clock enable */ +#define RCC_AHB1ENR_ETHTXEN (1 << 20) /* Bit 20: ETH TX clock enable */ +#define RCC_AHB1ENR_ETHRXEN (1 << 21) /* Bit 21: ETH RX clock enable */ +#define RCC_AHB1ENR_TZSC1EN (1 << 24) /* Bit 24: TZSC1 clock enable */ +#define RCC_AHB1ENR_BKPRAMEN (1 << 28) /* Bit 28: BKPRAM clock enable */ +#define RCC_AHB1ENR_DCACHEEN (1 << 30) /* Bit 25: DCACHE clock enable */ +#define RCC_AHB1ENR_SRAM1EN (1 << 31) /* Bit 25: SRAM1 clock enable */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_GPIOEN(n) (1 << (n)) +#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */ +#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */ +#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */ +#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */ +#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */ +#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */ +#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */ +#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */ +#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */ +#define RCC_AHB2ENR_ADCEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2ENR_DAC1EN (1 << 11) /* Bit 11: DAC clock enable */ +#define RCC_AHB2ENR_DCMI_PSSIEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2ENR_PKAEN (1 << 19) /* Bit 19: PKA clock enable */ +#define RCC_AHB2ENR_SAESEN (1 << 20) /* Bit 20: SAES clock enable */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* Bit 30: SRAM2 clock enable */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* Bit 30: SRAM2 clock enable */ + +/* AHB4 Peripheral Clock enable register */ + +#define RCC_AHB4ENR_OTFDEC1EN (1 << 7) /* Bit 7: On-the-fly decryption module clock enable */ +#define RCC_AHB4ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC1 clock enable */ +#define RCC_AHB4ENR_SDMMC2EN (1 << 12) /* Bit 12: SDMMC2 clock enable */ +#define RCC_AHB4ENR_FMCEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4ENR_OSPI1EN (1 << 20) /* Bit 20: OCTOSPI1 module enable */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 5: TIM12 clock enable */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 5: TIM13 clock enable */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 5: TIM14 clock enable */ +#define RCC_APB1LENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ +#define RCC_APB1LENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ +#define RCC_APB1LENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ +#define RCC_APB1LENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ +#define RCC_APB1LENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */ +#define RCC_APB1LENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */ +#define RCC_APB1LENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ +#define RCC_APB1LENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ +#define RCC_APB1LENR_I3C1EN (1 << 23) /* Bit 23: I3C1 clock enable */ +#define RCC_APB1LENR_CRSEN (1 << 24) /* Bit 24: CRS clock enable */ +#define RCC_APB1LENR_USART6EN (1 << 25) /* Bit 25: USART6 clock enable */ +#define RCC_APB1LENR_USART10EN (1 << 26) /* Bit 26: USART10 clock enable */ +#define RCC_APB1LENR_USART11EN (1 << 27) /* Bit 27: USART11 clock enable */ +#define RCC_APB1LENR_CECEN (1 << 28) /* Bit 28: CEC clock enable */ +#define RCC_APB1LENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ +#define RCC_APB1LENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HENR_UART9EN (1 << 0) /* Bit 0: UART9 clock enable */ +#define RCC_APB1HENR_UART12EN (1 << 1) /* Bit 1: UART12 clock enable */ +#define RCC_APB1HENR_DTSEN (1 << 3) /* Bit 3: DTS clock enable */ +#define RCC_APB1HENR_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable */ +#define RCC_APB1HENR_FDCANEN (1 << 9) /* Bit 9: FDCAN clock enable */ +#define RCC_APB1HENR_UCPD1EN (1 << 23) /* Bit 23: UCPD1 clock enable */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ +#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 clock enable */ +#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ +#define RCC_APB2ENR_SPI4EN (1 << 19) /* Bit 19: SPI4 clock enable */ +#define RCC_APB2ENR_SPI67EN (1 << 20) /* Bit 20: SPI6 clock enable */ +#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 clock enable */ +#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 clock enable */ +#define RCC_APB2ENR_USBEN (1 << 24) /* Bit 24: USB clock enable */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3ENR_SBSEN (1 << 1) /* Bit 1: SBS clock enable */ +#define RCC_APB3ENR_SPI5EN (1 << 5) /* Bit 5: SPI5 clock enable */ +#define RCC_APB3ENR_LPUART1EN (1 << 6) /* Bit 6: LPUART1 clock enable */ +#define RCC_APB3ENR_I2C3EN (1 << 7) /* Bit 7: I2C3 clock enable */ +#define RCC_APB3ENR_I2C4EN (1 << 8) /* Bit 8: I2C4 clock enable */ +#define RCC_APB3ENR_I3C2EN (1 << 9) /* Bit 9: I3C2 clock enable */ +#define RCC_APB3ENR_LPTIM1EN (1 << 11) /* Bit 11: LPTIM1 clock enable */ +#define RCC_APB3ENR_LPTIM3EN (1 << 12) /* Bit 12: LPTIM3 clock enable */ +#define RCC_APB3ENR_LPTIM4EN (1 << 13) /* Bit 13: LPTIM4 clock enable */ +#define RCC_APB3ENR_LPTIM5EN (1 << 14) /* Bit 14: LPTIM5 clock enable */ +#define RCC_APB3ENR_LPTIM6EN (1 << 15) /* Bit 15: LPTIM6 clock enable */ +#define RCC_APB3ENR_VREFEN (1 << 20) /* Bit 20: VREF clock enable */ +#define RCC_APB3ENR_RTCAPBEN (1 << 21) /* Bit 21: RTCABP clock enable */ + +/* RCC AHB1 Sleep and Stop modes peripheral clock enable register */ + +#define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ +#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interface clock enable during sleep mode */ +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ +#define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ +#define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ +#define RCC_AHB1LPENR_RAMCFGLPEN (1 << 17) /* Bit 17: RAMCFG clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHLPEN (1 << 19) /* Bit 19: ETH clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHTXLPEN (1 << 20) /* Bit 20: ETH TX clock enable during sleep mode */ +#define RCC_AHB1LPENR_ETHRXLPEN (1 << 21) /* Bit 21: ETH RX clock enable during sleep mode */ +#define RCC_AHB1LPENR_TZSC1LPEN (1 << 24) /* Bit 24: TZSC1 clock enable during sleep mode */ +#define RCC_AHB1LPENR_BKPRAMLPEN (1 << 28) /* Bit 28: BKPRAM clock enable during sleep mode */ +#define RCC_AHB1LPENR_DCACHELPEN (1 << 30) /* Bit 25: DCACHE clock enable during sleep mode */ +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 31) /* Bit 25: SRAM1 clock enable during sleep mode */ + +/* RCC AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during sleep mode */ +#define RCC_AHB2LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during sleep mode */ +#define RCC_AHB2LPENR_ADCLPEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ +#define RCC_AHB2LPENR_DAC1LPEN (1 << 11) /* Bit 11: DAC clock enable during sleep mode */ +#define RCC_AHB2LPENR_DCMI_PSSILPEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ +#define RCC_AHB2LPENR_AESLPEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 17) /* Bit 17: HASH module enable */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 18) /* Bit 18: Random number generator module enable */ +#define RCC_AHB2LPENR_PKALPEN (1 << 19) /* Bit 19: PKA clock enable during sleep mode */ +#define RCC_AHB2LPENR_SAESLPEN (1 << 20) /* Bit 20: SAES clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* Bit 30: SRAM2 clock enable during sleep mode */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* Bit 30: SRAM2 clock enable during sleep mode */ + +/* RCC AHB4 low power mode peripheral clock enable register */ + +#define RCC_AHB4LPENR_OTFDEC1LPEN (1 << 7) /* Bit 7: OTFDEC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC1 clock enable during sleep mode */ +#define RCC_AHB4LPENR_SDMMC2LPEN (1 << 12) /* Bit 12: SDMMC2 clock enable during sleep mode */ +#define RCC_AHB4LPENR_FMCLPEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ +#define RCC_AHB4LPENR_OSPI1LPEN (1 << 20) /* Bit 20: OCTOSPI1 module clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 1 */ + +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during sleep mode */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during sleep mode */ +#define RCC_APB1LLPENR_WWDGLPEN (1 << 11) /* Bit 11: WWDG clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* Bit 17: USART2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during sleep mode */ +#define RCC_APB1LLPENR_I3C1LPEN (1 << 23) /* Bit 23: I3C1 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CRSLPEN (1 << 24) /* Bit 24: CRS clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART6LPEN (1 << 25) /* Bit 25: USART6 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART10LPEN (1 << 26) /* Bit 26: USART10 clock enable during sleep mode */ +#define RCC_APB1LLPENR_USART11LPEN (1 << 27) /* Bit 27: USART11 clock enable during sleep mode */ +#define RCC_APB1LLPENR_CECLPEN (1 << 28) /* Bit 28: CEC clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during sleep mode */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during sleep mode */ + +/* APB1 Peripheral clock enable register 2 */ + +#define RCC_APB1HLPENR_UART9LPEN (1 << 0) /* Bit 0: UART9 clock enable during sleep mode */ +#define RCC_APB1HLPENR_UART12LPEN (1 << 1) /* Bit 1: UART12 clock enable during sleep mode */ +#define RCC_APB1HLPENR_DTSLPEN (1 << 3) /* Bit 3: DTS clock enable during sleep mode */ +#define RCC_APB1HLPENR_LPTIM2LPEN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable during sleep mode */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 9) /* Bit 9: FDCAN clock enable during sleep mode */ +#define RCC_APB1HLPENR_UCPD1LPEN (1 << 23) /* Bit 23: UCPD1 clock enable during sleep mode */ + +/* APB2 Peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 11) /* Bit 11: TIM1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 13) /* Bit 13: TIM8 clock enable during sleep mode */ +#define RCC_APB2LPENR_USART1LPEN (1 << 14) /* Bit 14: USART1 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 clock enable during sleep mode */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 19) /* Bit 19: SPI4 clock enable during sleep mode */ +#define RCC_APB2LPENR_SPI67LPEN (1 << 20) /* Bit 20: SPI6 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 clock enable during sleep mode */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 clock enable during sleep mode */ +#define RCC_APB2LPENR_USBLPEN (1 << 24) /* Bit 24: USB clock enable during sleep mode */ + +/* APB3 Peripheral clock enable register */ + +#define RCC_APB3LPENR_SBSLPEN (1 << 1) /* Bit 1: SBS clock enable during sleep mode */ +#define RCC_APB3LPENR_SPI5LPEN (1 << 5) /* Bit 5: SPI5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPUART1LPEN (1 << 6) /* Bit 6: LPUART1 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C3LPEN (1 << 7) /* Bit 7: I2C3 clock enable during sleep mode */ +#define RCC_APB3LPENR_I2C4LPEN (1 << 8) /* Bit 8: I2C4 clock enable during sleep mode */ +#define RCC_APB3LPENR_I3C2LPEN (1 << 9) /* Bit 9: I3C2 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM1LPEN (1 << 11) /* Bit 11: LPTIM1 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM3LPEN (1 << 12) /* Bit 12: LPTIM3 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM4LPEN (1 << 13) /* Bit 13: LPTIM4 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM5LPEN (1 << 14) /* Bit 14: LPTIM5 clock enable during sleep mode */ +#define RCC_APB3LPENR_LPTIM6LPEN (1 << 15) /* Bit 15: LPTIM6 clock enable during sleep mode */ +#define RCC_APB3LPENR_VREFLPEN (1 << 20) /* Bit 20: VREF clock enable during sleep mode */ +#define RCC_APB3LPENR_RTCAPBLPEN (1 << 21) /* Bit 21: RTCABP clock enable during sleep mode */ + +/* Kernel Clock Configuration register 1 */ + +#define RCC_CCIPR1_USART1SEL_SHIFT (0) +#define RCC_CCIPR1_USART1SEL_MASK (7 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL2QCK (1 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_PLL3QCK (2 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_HSIKERCK (3 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_CSIKERCK (4 << RCC_CCIPR1_USART1SEL_SHIFT) +# define RCC_CCIPR1_USART1SEL_LSECK (5 << RCC_CCIPR1_USART1SEL_SHIFT) + +#define RCC_CCIPR1_USART2SEL_SHIFT (3) +#define RCC_CCIPR1_USART2SEL_MASK (7 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL2QCK (1 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_PLL3QCK (2 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_HSIKERCK (3 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_CSIKERCK (4 << RCC_CCIPR1_USART2SEL_SHIFT) +# define RCC_CCIPR1_USART2SEL_LSECK (5 << RCC_CCIPR1_USART2SEL_SHIFT) + +#define RCC_CCIPR1_USART3SEL_SHIFT (6) +#define RCC_CCIPR1_USART3SEL_MASK (7 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL2QCK (1 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_PLL3QCK (2 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_HSIKERCK (3 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_CSIKERCK (4 << RCC_CCIPR1_USART3SEL_SHIFT) +# define RCC_CCIPR1_USART3SEL_LSECK (5 << RCC_CCIPR1_USART3SEL_SHIFT) + +#define RCC_CCIPR1_UART4SEL_SHIFT (9) +#define RCC_CCIPR1_UART4SEL_MASK (7 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL2QCK (1 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_PLL3QCK (2 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_HSIKERCK (3 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_CSIKERCK (4 << RCC_CCIPR1_UART4SEL_SHIFT) +# define RCC_CCIPR1_UART4SEL_LSECK (5 << RCC_CCIPR1_UART4SEL_SHIFT) + +#define RCC_CCIPR1_UART5SEL_SHIFT (12) +#define RCC_CCIPR1_UART5SEL_MASK (7 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL2QCK (1 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_PLL3QCK (2 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_HSIKERCK (3 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_CSIKERCK (4 << RCC_CCIPR1_UART5SEL_SHIFT) +# define RCC_CCIPR1_UART5SEL_LSECK (5 << RCC_CCIPR1_UART5SEL_SHIFT) + +#define RCC_CCIPR1_UART6SEL_SHIFT (15) +#define RCC_CCIPR1_UART6SEL_MASK (7 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL2QCK (1 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_PLL3QCK (2 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_HSIKERCK (3 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_CSIKERCK (4 << RCC_CCIPR1_UART6SEL_SHIFT) +# define RCC_CCIPR1_UART6SEL_LSECK (5 << RCC_CCIPR1_UART6SEL_SHIFT) + +#define RCC_CCIPR1_UART7SEL_SHIFT (18) +#define RCC_CCIPR1_UART7SEL_MASK (7 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL2QCK (1 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_PLL3QCK (2 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_HSIKERCK (3 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_CSIKERCK (4 << RCC_CCIPR1_UART7SEL_SHIFT) +# define RCC_CCIPR1_UART7SEL_LSECK (5 << RCC_CCIPR1_UART7SEL_SHIFT) + +#define RCC_CCIPR1_UART8SEL_SHIFT (21) +#define RCC_CCIPR1_UART8SEL_MASK (7 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL2QCK (1 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_PLL3QCK (2 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_HSIKERCK (3 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_CSIKERCK (4 << RCC_CCIPR1_UART8SEL_SHIFT) +# define RCC_CCIPR1_UART8SEL_LSECK (5 << RCC_CCIPR1_UART8SEL_SHIFT) + +#define RCC_CCIPR1_UART9SEL_SHIFT (24) +#define RCC_CCIPR1_UART9SEL_MASK (7 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL2QCK (1 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_PLL3QCK (2 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_HSIKERCK (3 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_CSIKERCK (4 << RCC_CCIPR1_UART9SEL_SHIFT) +# define RCC_CCIPR1_UART9SEL_LSECK (5 << RCC_CCIPR1_UART9SEL_SHIFT) + +#define RCC_CCIPR1_USART10SEL_SHIFT (27) +#define RCC_CCIPR1_USART10SEL_MASK (7 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL2QCK (1 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_PLL3QCK (2 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_HSIKERCK (3 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_CSIKERCK (4 << RCC_CCIPR1_USART10SEL_SHIFT) +# define RCC_CCIPR1_USART10SEL_LSECK (5 << RCC_CCIPR1_USART10SEL_SHIFT) + +#define RCC_CCIPR1_TIMICSEL (1 << 31) + +/* Kernel Clock Configuration register 2 */ + +#define RCC_CCIPR2_USART11SEL_SHIFT (0) +#define RCC_CCIPR2_USART11SEL_MASK (7 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL2QCK (1 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_PLL3QCK (2 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_HSIKERCK (3 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_CSIKERCK (4 << RCC_CCIPR2_USART11SEL_SHIFT) +# define RCC_CCIPR2_USART11SEL_LSECK (5 << RCC_CCIPR2_USART11SEL_SHIFT) + +#define RCC_CCIPR2_USART12SEL_SHIFT (4) +#define RCC_CCIPR2_USART12SEL_MASK (7 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL2QCK (1 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_PLL3QCK (2 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_HSIKERCK (3 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_CSIKERCK (4 << RCC_CCIPR2_USART12SEL_SHIFT) +# define RCC_CCIPR2_USART12SEL_LSECK (5 << RCC_CCIPR2_USART12SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM1SEL_SHIFT (8) +#define RCC_CCIPR2_LPTIM1SEL_MASK (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM1SEL_SHIFT) +# define RCC_CCIPR2_LPTIM1SEL_LSECK (5 << RCC_CCIPR2_LPTIM1SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM2SEL_SHIFT (12) +#define RCC_CCIPR2_LPTIM2SEL_MASK (7 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_RCCPCLK1 (0 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM2SEL_SHIFT) +# define RCC_CCIPR2_LPTIM2SEL_LSECK (5 << RCC_CCIPR2_LPTIM2SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM3SEL_SHIFT (16) +#define RCC_CCIPR2_LPTIM3SEL_MASK (7 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM3SEL_SHIFT) +# define RCC_CCIPR2_LPTIM3SEL_LSECK (5 << RCC_CCIPR2_LPTIM3SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM4SEL_SHIFT (20) +#define RCC_CCIPR2_LPTIM4SEL_MASK (7 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM4SEL_SHIFT) +# define RCC_CCIPR2_LPTIM4SEL_LSECK (5 << RCC_CCIPR2_LPTIM4SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM5SEL_SHIFT (24) +#define RCC_CCIPR2_LPTIM5SEL_MASK (7 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM5SEL_SHIFT) +# define RCC_CCIPR2_LPTIM5SEL_LSECK (5 << RCC_CCIPR2_LPTIM5SEL_SHIFT) + +#define RCC_CCIPR2_LPTIM6SEL_SHIFT (28) +#define RCC_CCIPR2_LPTIM6SEL_MASK (7 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM6SEL_SHIFT) +# define RCC_CCIPR2_LPTIM6SEL_LSECK (5 << RCC_CCIPR2_LPTIM6SEL_SHIFT) + +/* Kernel Clock Configuration register 3 */ + +#define RCC_CCIPR3_SPI1SEL_SHIFT (0) +#define RCC_CCIPR3_SPI1SEL_MASK (7 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL1QCK (0 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT) +# define RCC_CCIPR3_SPI1SEL_PERCK (4 << RCC_CCIPR3_SPI1SEL_SHIFT) + +#define RCC_CCIPR3_SPI2SEL_SHIFT (3) +#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL1QCK (0 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT) +# define RCC_CCIPR3_SPI2SEL_PERCK (4 << RCC_CCIPR3_SPI2SEL_SHIFT) + +#define RCC_CCIPR3_SPI3SEL_SHIFT (6) +#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL1QCK (0 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT) +# define RCC_CCIPR3_SPI3SEL_PERCK (4 << RCC_CCIPR3_SPI3SEL_SHIFT) + +#define RCC_CCIPR3_SPI4SEL_SHIFT (9) +#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_CSIKERCK (4 << RCC_CCIPR3_SPI4SEL_SHIFT) +# define RCC_CCIPR3_SPI4SEL_HSECK (5 << RCC_CCIPR3_SPI4SEL_SHIFT) + +#define RCC_CCIPR3_SPI5SEL_SHIFT (12) +#define RCC_CCIPR3_SPI5SEL_MASK (7 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_RCCPCLK3 (0 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL2QCK (1 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_PLL3QCK (2 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSIKERCK (3 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_CSIKERCK (4 << RCC_CCIPR3_SPI5SEL_SHIFT) +# define RCC_CCIPR3_SPI5SEL_HSECK (5 << RCC_CCIPR3_SPI5SEL_SHIFT) + +#define RCC_CCIPR3_SPI6SEL_SHIFT (15) +#define RCC_CCIPR3_SPI6SEL_MASK (7 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL2QCK (1 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_PLL3QCK (2 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSIKERCK (3 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_CSIKERCK (4 << RCC_CCIPR3_SPI6SEL_SHIFT) +# define RCC_CCIPR3_SPI6SEL_HSECK (5 << RCC_CCIPR3_SPI6SEL_SHIFT) + +#define RCC_CCIPR3_LPUART1SEL_SHIFT (24) +#define RCC_CCIPR3_LPUART1SEL_MASK (7 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_RCCPCLK3 (0 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL2QCK (1 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_PLL3QCK (2 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_HSIKERCK (3 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_CSIKERCK (4 << RCC_CCIPR3_LPUART1SEL_SHIFT) +# define RCC_CCIPR3_LPUART1SEL_LSECK (5 << RCC_CCIPR3_LPUART1SEL_SHIFT) + +/* Kernel Clock Configuration register 4 */ + +#define RCC_CCIPR4_OCTOSPI1SEL_SHIFT (0) +#define RCC_CCIPR4_OCTOSPI1SEL_MASK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_RCCHCLK4 (0 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL1QCK (1 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PLL2RCK (2 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) +# define RCC_CCIPR4_OCTOSPI1SEL_PERCK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) + +#define RCC_CCIPR4_SYSTICKSEL_SHIFT (2) +#define RCC_CCIPR4_SYSTICKSEL_MASK (3 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_RCCHCLKd8 (0 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSIKERCK1 (1 << RCC_CCIPR4_SYSTICKSEL_SHIFT) +# define RCC_CCIPR4_SYSTICKSEL_LSICK1 (2 << RCC_CCIPR4_SYSTICKSEL_SHIFT) + +#define RCC_CCIPR4_USBSEL_SHIFT (4) +#define RCC_CCIPR4_USBSEL_MASK (3 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_NOCK (0 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL1QCK (1 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_PLL3QCK (2 << RCC_CCIPR4_USBSEL_SHIFT) +# define RCC_CCIPR4_USBSEL_HSI48KERCK (3 << RCC_CCIPR4_USBSEL_SHIFT) + +#define RCC_CCIPR4_SDMMC1SEL (1 << 6) +#define RCC_CCIPR4_SDMMC2SEL (1 << 7) + +#define RCC_CCIPR4_I2C1SEL_SHIFT (16) +#define RCC_CCIPR4_I2C1SEL_MASK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_PLL3RCK (1 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_HSIKERCK (2 << RCC_CCIPR4_I2C1SEL_SHIFT) +# define RCC_CCIPR4_I2C1SEL_CSIKERCK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) + +#define RCC_CCIPR4_I2C2SEL_SHIFT (18) +#define RCC_CCIPR4_I2C2SEL_MASK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_PLL3RCK (1 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_HSIKERCK (2 << RCC_CCIPR4_I2C2SEL_SHIFT) +# define RCC_CCIPR4_I2C2SEL_CSIKERCK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) + +#define RCC_CCIPR4_I2C3SEL_SHIFT (20) +#define RCC_CCIPR4_I2C3SEL_MASK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_PLL3RCK (1 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_HSIKERCK (2 << RCC_CCIPR4_I2C3SEL_SHIFT) +# define RCC_CCIPR4_I2C3SEL_CSIKERCK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) + +#define RCC_CCIPR4_I2C4SEL_SHIFT (22) +#define RCC_CCIPR4_I2C4SEL_MASK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_PLL3RCK (1 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_HSIKERCK (2 << RCC_CCIPR4_I2C4SEL_SHIFT) +# define RCC_CCIPR4_I2C4SEL_CSIKERCK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) + +#define RCC_CCIPR4_I3C1SEL_SHIFT (24) +#define RCC_CCIPR4_I3C1SEL_MASK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_PLL3RCK (1 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_HSIKERCK (2 << RCC_CCIPR4_I3C1SEL_SHIFT) +# define RCC_CCIPR4_I3C1SEL_NOCK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) + +#define RCC_CCIPR4_I3C2SEL_SHIFT (24) +#define RCC_CCIPR4_I3C2SEL_MASK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_PLL3RCK (1 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_HSIKERCK (2 << RCC_CCIPR4_I3C2SEL_SHIFT) +# define RCC_CCIPR4_I3C2SEL_NOCK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) + +/* Kernel Clock Configuration register 5 */ + +#define RCC_CCIPR5_ADCDACSEL_SHIFT (0) +#define RCC_CCIPR5_ADCDACSEL_MASK (7 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_RCCHCLK (0 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_SYSCK (1 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_PLL2RCK (2 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSECK (3 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_HSEKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) +# define RCC_CCIPR5_ADCDACSEL_CSIKERCK (5 << RCC_CCIPR5_ADCDACSEL_SHIFT) + +#define RCC_CCIPR5_DACSEL (1 << 3) + +#define RCC_CCIPR5_RNGSEL_SHIFT (4) +#define RCC_CCIPR5_RNGSEL_MASK (3 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_HSI48KERCK (0 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_PLL1QCK (1 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSECK (2 << RCC_CCIPR5_RNGSEL_SHIFT) +# define RCC_CCIPR5_RNGSEL_LSIKERCK (3 << RCC_CCIPR5_RNGSEL_SHIFT) + +#define RCC_CCIPR5_CECSEL_SHIFT (6) +#define RCC_CCIPR5_CECSEL_MASK (3 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSECK (0 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_LSIKERCK (1 << RCC_CCIPR5_CECSEL_SHIFT) +# define RCC_CCIPR5_CECSEL_CSIKERCKd122 (2 << RCC_CCIPR5_CECSEL_SHIFT) + +#define RCC_CCIPR5_FDCANSEL_SHIFT (8) +#define RCC_CCIPR5_FDCANSEL_MASK (3 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_HSECK (0 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL1QCK (1 << RCC_CCIPR5_FDCANSEL_SHIFT) +# define RCC_CCIPR5_FDCANSEL_PLL2QCK (2 << RCC_CCIPR5_FDCANSEL_SHIFT) + +#define RCC_CCIPR5_SAI1SEL_SHIFT (16) +#define RCC_CCIPR5_SAI1SEL_MASK (7 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL1QCK (0 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL2PCK (1 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PLL3PCK (2 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI1SEL_SHIFT) +# define RCC_CCIPR5_SAI1SEL_PERCK (4 << RCC_CCIPR5_SAI1SEL_SHIFT) + +#define RCC_CCIPR5_SAI2SEL_SHIFT (19) +#define RCC_CCIPR5_SAI2SEL_MASK (7 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL1QCK (0 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL2PCK (1 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PLL3PCK (2 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI2SEL_SHIFT) +# define RCC_CCIPR5_SAI2SEL_PERCK (4 << RCC_CCIPR5_SAI2SEL_SHIFT) + +#define RCC_CCIPR5_CKPERSEL_SHIFT (30) +#define RCC_CCIPR5_CKPERSEL_MASK (3 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSIKERCK (0 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_CSIKERCK (1 << RCC_CCIPR5_CKPERSEL_SHIFT) +# define RCC_CCIPR5_CKPERSEL_HSECK (2 << RCC_CCIPR5_CKPERSEL_SHIFT) + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ + +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ + +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ +#define RCC_BDCR_LSEEXT (1 << 7) /* Bit 7: LSE external clock type in bypass mode */ + +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ + +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_VSWRST (1 << 16) /* Bit 16: VSwitch domain software reset */ +#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ +#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ +# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ +# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ + +#define RCC_BDCR_LSION (1 << 26) /* Bit 26: LSI Oscillator Enable */ +#define RCC_BDCR_LSIRDY (1 << 27) /* Bit 27: LSI Oscillator Ready */ + +/* Reset status register */ + +#define RCC_RSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ +#define RCC_RSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ +#define RCC_RSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ +#define RCC_RSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ +#define RCC_RSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ +#define RCC_RSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ + +/* Secure Configuration Register */ + +#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */ +#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */ +#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */ +#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */ +#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */ +#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */ +#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */ +#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */ +#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */ +#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */ +#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */ +#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */ + +/* Privilege Configuration Register */ + +#define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ +#define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ + +#endif /* CONFIG_STM32_STM32H562XX */ +#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h deleted file mode 100644 index 3e025922ad4a9..0000000000000 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ /dev/null @@ -1,1246 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H -#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#if defined(CONFIG_STM32_STM32H5XXXX) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32_RCC_HSICFGR_OFFSET 0x0010 /* HSI Calibration Register */ -#define STM32_RCC_CRRCR_OFFSET 0x0014 /* RCC clock recovery RC register */ -#define STM32_RCC_CFGR1_OFFSET 0x001c /* RCC clock configuration register 1 */ -#define STM32_RCC_CFGR2_OFFSET 0x0020 /* RCC clock configuration register 2 */ -#define STM32_RCC_PLL1CFGR_OFFSET 0x0028 /* RCC PLL1 configuration register */ -#define STM32_RCC_PLL2CFGR_OFFSET 0x002c /* RCC PLL2 configuration register */ -#define STM32_RCC_PLL3CFGR_OFFSET 0x0030 /* RCC PLL3 configuration register */ -#define STM32_RCC_PLL1DIVR_OFFSET 0x0034 /* RCC PLL1 dividers register */ -#define STM32_RCC_PLL1FRACR_OFFSET 0x0038 /* RCC PLL1 fractional divider register */ -#define STM32_RCC_PLL2DIVR_OFFSET 0x003c /* RCC PLL2 dividers register */ -#define STM32_RCC_PLL2FRACR_OFFSET 0x0040 /* RCC PLL2 fractional divider register */ -#define STM32_RCC_PLL3DIVR_OFFSET 0x0044 /* RCC PLL3 dividers register */ -#define STM32_RCC_PLL3FRACR_OFFSET 0x0048 /* RCC PLL3 fractional divider register */ -#define STM32_RCC_CIER_OFFSET 0x0050 /* RCC clock interrupt enable register */ -#define STM32_RCC_CIFR_OFFSET 0x0054 /* RCC clock interrupt flag register */ -#define STM32_RCC_CICR_OFFSET 0x0058 /* RCC clock interrupt clear register */ -#define STM32_RCC_AHB1RSTR_OFFSET 0x0060 /* RCC AHB1 peripheral reset register */ -#define STM32_RCC_AHB2RSTR_OFFSET 0x0064 /* RCC AHB2 peripheral reset register 1 */ -#define STM32_RCC_AHB4RSTR_OFFSET 0x006c /* RCC AHB4 peripheral reset register*/ -#define STM32_RCC_APB1LRSTR_OFFSET 0x0074 /* RCC APB1 peripheral reset register 1 */ -#define STM32_RCC_APB1HRSTR_OFFSET 0x0078 /* RCC APB1 peripheral reset register 2 */ -#define STM32_RCC_APB2RSTR_OFFSET 0x007c /* RCC APB2 peripheral reset register */ -#define STM32_RCC_APB3RSTR_OFFSET 0x0080 /* RCC APB3 peripheral reset register */ -#define STM32_RCC_AHB1ENR_OFFSET 0x0088 /* RCC AHB1 peripheral clock enable register */ -#define STM32_RCC_AHB2ENR_OFFSET 0x008c /* RCC AHB2 peripheral clock enable register */ -#define STM32_RCC_AHB4ENR_OFFSET 0x0094 /* RCC AHB4 peripheral clock enable register */ -#define STM32_RCC_APB1LENR_OFFSET 0x009c /* RCC APB1 peripheral clock enable register 1 */ -#define STM32_RCC_APB1HENR_OFFSET 0x00a0 /* RCC APB1 peripheral clock enable register 2 */ -#define STM32_RCC_APB2ENR_OFFSET 0x00a4 /* RCC APB2 peripheral clock enable register */ -#define STM32_RCC_APB3ENR_OFFSET 0x00a8 /* RCC APB3 peripheral clock enable register */ -#define STM32_RCC_AHB1LPENR_OFFSET 0x00b0 /* RCC AHB1 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_AHB2LPENR_OFFSET 0x00b4 /* RCC AHB2 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_AHB4LPENR_OFFSET 0x00bc /* RCC AHB3 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_APB1LPENR1_OFFSET 0x00c4 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 */ -#define STM32_RCC_APB1LPENR2_OFFSET 0x00c8 /* RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 */ -#define STM32_RCC_APB2LPENR_OFFSET 0x00cc /* RCC APB2 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_APB3LPENR_OFFSET 0x00d0 /* RCC APB3 peripheral clocks enable in Sleep and Stop modes register */ -#define STM32_RCC_CCIPR1_OFFSET 0x00d8 /* RCC peripherals independent clock configuration register 1 */ -#define STM32_RCC_CCIPR2_OFFSET 0x00dc /* RCC peripherals independent clock configuration register 2 */ -#define STM32_RCC_CCIPR3_OFFSET 0x00e0 /* RCC peripherals independent clock configuration register 3 */ -#define STM32_RCC_CCIPR4_OFFSET 0x00e4 /* RCC peripherals independent clock configuration register 5 */ -#define STM32_RCC_CCIPR5_OFFSET 0x00e8 /* RCC peripherals independent clock configuration register 5 */ -#define STM32_RCC_BDCR_OFFSET 0x00f0 /* RCC Backup domain control register */ -#define STM32_RCC_RSR_OFFSET 0x00f4 /* RCC control/status register */ /* TODO: CSR in U5 */ -#define STM32_RCC_SECCFGR_OFFSET 0x0110 /* RCC secure configuration register */ -#define STM32_RCC_PRIVCFGR_OFFSET 0x0114 /* RCC privilege configuration register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) -#define STM32_RCC_HSICFGR (STM32_RCC_BASE + STM32_RCC_HSICFGR_OFFSET) -#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) -#define STM32_RCC_CFGR1 (STM32_RCC_BASE + STM32_RCC_CFGR1_OFFSET) -#define STM32_RCC_CFGR2 (STM32_RCC_BASE + STM32_RCC_CFGR2_OFFSET) -#define STM32_RCC_PLL1CFGR (STM32_RCC_BASE + STM32_RCC_PLL1CFGR_OFFSET) -#define STM32_RCC_PLL2CFGR (STM32_RCC_BASE + STM32_RCC_PLL2CFGR_OFFSET) -#define STM32_RCC_PLL3CFGR (STM32_RCC_BASE + STM32_RCC_PLL3CFGR_OFFSET) -#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) -#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) -#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) -#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) -#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) -#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) -#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) -#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) -#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) -#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) -#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) -#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) -#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) -#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) -#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) -#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) -#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) -#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) -#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) -#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) -#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) -#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) -#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) -#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) -#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) -#define STM32_RCC_APB1LPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR1_OFFSET) -#define STM32_RCC_APB1HPENR (STM32_RCC_BASE + STM32_RCC_APB1LPENR2_OFFSET) -#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) -#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) -#define STM32_RCC_CCIPR1 (STM32_RCC_BASE + STM32_RCC_CCIPR1_OFFSET) -#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) -#define STM32_RCC_CCIPR3 (STM32_RCC_BASE + STM32_RCC_CCIPR3_OFFSET) -#define STM32_RCC_CCIPR4 (STM32_RCC_BASE + STM32_RCC_CCIPR4_OFFSET) -#define STM32_RCC_CCIPR5 (STM32_RCC_BASE + STM32_RCC_CCIPR5_OFFSET) -#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) -#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) -#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) -#define STM32_RCC_PRIVCFGR (STM32_RCC_BASE + STM32_RCC_PRIVCFGR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Clock control register */ - -#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ -#define RCC_CR_HSIRDY (1 << 1) /* Bit 1: Internal High Speed clock ready flag */ -#define RCC_CR_HSIKERON (1 << 2) /* Bit 2: HSI clock enable in Stop mode */ -#define RCC_CR_HSIDIV_SHIFT (3) /* Bit [4:3] HSI Divider */ -#define RCC_CR_HSIDIV_MASK (0x3 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV(n) (((n) << RCC_CR_HSIDIV_SHIFT & RCC_CR_HSIDIV_MASK)) -#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI divider flag */ - -#define RCC_CR_CSION (1 << 8) /* Bit 8: CSI clock enable */ -#define RCC_CR_CSIRDY (1 << 9) /* Bit 9: CSI clock ready flag */ -#define RCC_CR_CSIKERON (1 << 10) /* Bit 10: CSI clock enable in Stop mode */ - -#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable */ -#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready flag */ - -#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */ -#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */ -#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: HSE clock bypass */ -#define RCC_CR_HSECSSON (1 << 19) /* Bit 19: HSE clock security system enable */ -#define RCC_CR_HSEEXT (1 << 20) /* Bit 20: HSE external high speed clock - * type in bypass mode */ -#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: PLL1 enable */ -#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: PLL1 clock ready flag */ -#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: PLL2 enable */ -#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: PLL2 clock ready flag */ -#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: PLL3 enable */ -#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: PLL3 clock ready flag */ - -/* HSI Calibration register */ - -#define RCC_HSICFGR_HSITRIM_SHIFT (16) /* Bits 22-16: Internal High Speed clock trimming */ -#define RCC_HSICFGR_HSITRIM_MASK (0x7f << RCC_HSICFGR_HSITRIM_SHIFT) -#define RCC_HSICFGR_HSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ -#define RCC_HSICFGR_HSICAL_MASK (0xfff << RCC_HSICFGR_HSICAL_SHIFT) - -/* Clock Recovery RC register */ - -#define RCC_CRRCR_HSI48CAL_SHIFT (0) /* Bits 9-0: Internal RC 48MHz Clock Calibration */ -#define RCC_CRRCR_HSI48CAL_MASK (0x3ff << RCC_CRRCR_HSI48CAL_SHIFT) - -/* CSI Calibration register */ - -#define RCC_CSICFGR_CSITRIM_SHIFT (16) /* Bits 21-16: Internal High Speed clock trimming */ -#define RCC_CSICFGR_CSITRIM_MASK (0x3f << RCC_CSICFGR_CSITRIM_SHIFT) -#define RCC_CSICFGR_CSICAL_SHIFT (0) /* Bits 11-0: Internal High Speed clock Calibration */ -#define RCC_CSICFGR_CSICAL_MASK (0xff << RCC_CSICFGR_CSICAL_SHIFT) - -/* Clock configuration register 1 */ - -#define RCC_CFGR1_SW_SHIFT (0) /* Bits 0-1: System clock Switch */ -#define RCC_CFGR1_SW_MASK (3 << RCC_CFGR1_SW_SHIFT) -# define RCC_CFGR1_SW_MSI (0 << RCC_CFGR1_SW_SHIFT) /* 00: MSI selected as system clock */ -# define RCC_CFGR1_SW_HSI16 (1 << RCC_CFGR1_SW_SHIFT) /* 00: HSI16 selected as system clock */ -# define RCC_CFGR1_SW_HSE (2 << RCC_CFGR1_SW_SHIFT) /* 01: HSE selected as system clock */ -# define RCC_CFGR1_SW_PLL (3 << RCC_CFGR1_SW_SHIFT) /* 10: PLL selected as system clock */ - -#define RCC_CFGR1_SWS_SHIFT (3) /* Bits 3-4: System Clock Switch Status */ -#define RCC_CFGR1_SWS_MASK (3 << RCC_CFGR1_SWS_SHIFT) -# define RCC_CFGR1_SWS_MSI (0 << RCC_CFGR1_SWS_SHIFT) /* 00: MSI oscillator used as system clock */ -# define RCC_CFGR1_SWS_HSI16 (1 << RCC_CFGR1_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */ -# define RCC_CFGR1_SWS_HSE (2 << RCC_CFGR1_SWS_SHIFT) /* 01: HSE oscillator used as system clock */ -# define RCC_CFGR1_SWS_PLL (3 << RCC_CFGR1_SWS_SHIFT) /* 10: PLL used as system clock */ - -#define RCC_CFGR1_STOPWUCK (1 << 6) /* System clock selection after a wakeup from system stop */ -#define RCC_CFGR1_STOPKERWUCK (1 << 7) /* Kernel clock selection after a wakeup from system stop */ - -#define RCC_CFGR1_RTCPRE_SHIFT (8) /* Bits 13-8: RTC prescaler */ -#define RCC_CFGR1_RTCPRE_MASK (0x3f << RCC_CFGR1_RTCPRE_SHIFT) -# define RCC_CFGR1_RTCPRE_HSE (0 << RCC_CFGR1_RTCPRE_SHIFT) /* 0xxx: HSE not divided */ -# define RCC_CFGR1_RTCPRE_HSEd2 (2 << RCC_CFGR1_RTCPRE_SHIFT) /* 10: HSE divided by 2 */ -# define RCC_CFGR1_RTCPRE_HSEd4 (4 << RCC_CFGR1_RTCPRE_SHIFT) /* 100: HSE divided by 4 */ -# define RCC_CFGR1_RTCPRE_HSEd8 (8 << RCC_CFGR1_RTCPRE_SHIFT) /* 1000: HSE divided by 8 */ -# define RCC_CFGR1_RTCPRE_HSEd16 (16 << RCC_CFGR1_RTCPRE_SHIFT) /* 10000: HSE divided by 16 */ -# define RCC_CFGR1_RTCPRE_HSEd32 (32 << RCC_CFGR1_RTCPRE_SHIFT) /* 100000: HSE divided by 32 */ -# define RCC_CFGR1_RTCPRE_HSEd63 (63 << RCC_CFGR1_RTCPRE_SHIFT) /* 111111: HSE divided by 63 */ - -#define RCC_CFGR1_TIMPRE (1 << 15) /* timers clocks prescaler selection */ - -#define RCC_CFGR1_MCO1PRE_SHIFT (18) /* Bits 21-18: MCO1 Prescaler */ -#define RCC_CFGR1_MCO1PRE_MASK (0xf << RCC_CFGR1_MCO1PRE_SHIFT) -# define RCC_CFGR1_MCO1PRE_MCO1 (0 << RCC_CFGR1_MCO1PRE_SHIFT) /* 0xx: MCO1 not divided */ -# define RCC_CFGR1_MCO1PRE_MCO1d2 (2 << RCC_CFGR1_MCO1PRE_SHIFT) /* 10: MCO1 divided by 2 */ -# define RCC_CFGR1_MCO1PRE_MCO1d4 (4 << RCC_CFGR1_MCO1PRE_SHIFT) /* 100: MCO1 divided by 4 */ -# define RCC_CFGR1_MCO1PRE_MCO1d8 (8 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1000: MCO1 divided by 8 */ -# define RCC_CFGR1_MCO1PRE_MCO1d15 (15 << RCC_CFGR1_MCO1PRE_SHIFT) /* 1111: MCO1 divided by 15 */ - -#define RCC_CFGR1_MCO1SEL_SHIFT (22) /* Bits 24-22: Microcontroller Clock Output1 */ -#define RCC_CFGR1_MCO1SEL_MASK (0x7 << RCC_CFGR1_MCO1SEL_SHIFT) -# define RCC_CFGR1_MCO1SEL_HSI (0 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0000: HSI clock selected */ -# define RCC_CFGR1_MCO1SEL_LSE (1 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0001: LSE clock selected */ -# define RCC_CFGR1_MCO1SEL_HSE (2 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0010: HSE clock selected */ -# define RCC_CFGR1_MCO1SEL_PLL1 (3 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0011: Main PLL1 selected */ -# define RCC_CFGR1_MCO1SEL_HSI48 (4 << RCC_CFGR1_MCO1SEL_SHIFT) /* 0100: HSI48 clock selected */ - -#define RCC_CFGR1_MCO2PRE_SHIFT (25) /* Bits 28-25: MCO2 Prescaler */ -#define RCC_CFGR1_MCO2PRE_MASK (0xf << RCC_CFGR1_MCO2PRE_SHIFT) -# define RCC_CFGR1_MCO2PRE_MCO2 (0 << RCC_CFGR1_MCO2PRE_SHIFT) /* 0xx: MCO2 not divided */ -# define RCC_CFGR1_MCO2PRE_MCO2d2 (2 << RCC_CFGR1_MCO2PRE_SHIFT) /* 10: MCO2 divided by 2 */ -# define RCC_CFGR1_MCO2PRE_MCO2d4 (4 << RCC_CFGR1_MCO2PRE_SHIFT) /* 100: MCO2 divided by 4 */ -# define RCC_CFGR1_MCO2PRE_MCO2d8 (8 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1000: MCO2 divided by 8 */ -# define RCC_CFGR1_MCO2PRE_MCO2d15 (15 << RCC_CFGR1_MCO2PRE_SHIFT) /* 1111: MCO2 divided by 15 */ - -#define RCC_CFGR1_MCO2SEL_SHIFT (29) /* Bits 31-29: Microcontroller Clock Output1 */ -#define RCC_CFGR1_MCO2SEL_MASK (0x7 << RCC_CFGR1_MCO2SEL_SHIFT) -# define RCC_CFGR1_MCO2SEL_SYSCLLK (0 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0000: Main SYSCLLK selected */ -# define RCC_CFGR1_MCO2SEL_PLL2 (1 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0001: Main PLL2 selected */ -# define RCC_CFGR1_MCO2SEL_HSE (2 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0010: HSE clock selected */ -# define RCC_CFGR1_MCO2SEL_PLL1 (3 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0011: Main PLL1 selected */ -# define RCC_CFGR1_MCO2SEL_CSI (4 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0100: CSI clock selected */ -# define RCC_CFGR1_MCO2SEL_LSI (5 << RCC_CFGR1_MCO2SEL_SHIFT) /* 0101: LSI clock selected */ - -/* Clock configuration register 2 */ - -#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 3-0: HPRE Prescaler */ -#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT) -# define RCC_CFGR2_HPRE_SYSCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xx: SYSCLK not divided */ -# define RCC_CFGR2_HPRE_SYSCLKd2 (8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */ -# define RCC_CFGR2_HPRE_SYSCLKd4 (9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */ -# define RCC_CFGR2_HPRE_SYSCLKd8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */ -# define RCC_CFGR2_HPRE_SYSCLKd16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */ -# define RCC_CFGR2_HPRE_SYSCLKd64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */ -# define RCC_CFGR2_HPRE_SYSCLKd128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */ -# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */ -# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */ - -#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 6-4: PPRE1 Prescaler */ -#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT) -# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */ - -#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */ -#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT) -# define RCC_CFGR2_PPRE2_HCLK1 (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE2_HCLK1d2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE2_HCLK1d4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE2_HCLK1d8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE2_HCLK1d16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK1 divided by 16 */ - -#define RCC_CFGR2_PPRE3_SHIFT (12) /* Bits 14-12: PPRE3 Prescaler */ -#define RCC_CFGR2_PPRE3_MASK (0x7 << RCC_CFGR2_PPRE3_SHIFT) -# define RCC_CFGR2_PPRE3_HCLK1 (0 << RCC_CFGR2_PPRE3_SHIFT) /* 0xx: HCLK1 not divided */ -# define RCC_CFGR2_PPRE3_HCLK1d2 (4 << RCC_CFGR2_PPRE3_SHIFT) /* 100: HCLK1 divided by 2 */ -# define RCC_CFGR2_PPRE3_HCLK1d4 (5 << RCC_CFGR2_PPRE3_SHIFT) /* 101: HCLK1 divided by 4 */ -# define RCC_CFGR2_PPRE3_HCLK1d8 (6 << RCC_CFGR2_PPRE3_SHIFT) /* 110: HCLK1 divided by 8 */ -# define RCC_CFGR2_PPRE3_HCLK1d16 (7 << RCC_CFGR2_PPRE3_SHIFT) /* 111: HCLK1 divided by 16 */ - -#define RCC_CFGR2_AHB1DIS (1 << 16) /* AHB1 clock disable */ -#define RCC_CFGR2_AHB2DIS (1 << 17) /* AHB2 clock disable */ -#define RCC_CFGR2_AHB4DIS (1 << 19) /* AHB4 clock disable */ -#define RCC_CFGR2_APB1DIS (1 << 20) /* APB1 clock disable */ -#define RCC_CFGR2_APB2DIS (1 << 21) /* APB2 clock disable */ -#define RCC_CFGR2_APB3DIS (1 << 22) /* APB3 clock disable */ - -/* PLL1 configuration register */ - -#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL1CFGR_PLL1SRC_MASK (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) -# define RCC_PLL1CFGR_PLL1SRC_NONE (0 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL1CFGR_PLL1SRC_HSI (1 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL1CFGR_PLL1SRC_CSI (2 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL1CFGR_PLL1SRC_HSE (3 << RCC_PLL1CFGR_PLL1SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL1CFGR_PLL1RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL1CFGR_PLL1RGE_MASK (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) -# define RCC_PLL1CFGR_PLL1RGE_1_2M (0 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL1CFGR_PLL1RGE_2_4M (1 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL1CFGR_PLL1RGE_4_8M (2 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ -# define RCC_PLL1CFGR_PLL1RGE_8_16M (3 << RCC_PLL1CFGR_PLL1RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ - -#define RCC_PLL1CFGR_PLL1FRACEN (1 << 4) /* PLL1 Fractional Latch Enable */ -#define RCC_PLL1CFGR_PLL1VCOSEL (1 << 5) /* PLL1 VCO Selection */ - -#define RCC_PLL1CFGR_PLL1M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL1CFGR_PLL1M_MASK (0x3f << RCC_PLL1CFGR_PLL1M_SHIFT) -# define RCC_PLL1CFGR_PLL1M(n) ((n) << RCC_PLL1CFGR_PLL1M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL1CFGR_PLL1PEN (1 << 16) /* PLL1 DIVP divder output enable */ -#define RCC_PLL1CFGR_PLL1QEN (1 << 17) /* PLL1 DIVQ divder output enable */ -#define RCC_PLL1CFGR_PLL1REN (1 << 18) /* PLL1 DIVR divder output enable */ - -/* PLL2 configuration register */ - -#define RCC_PLL2CFGR_PLL2SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL2CFGR_PLL2SRC_MASK (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) -# define RCC_PLL2CFGR_PLL2SRC_NONE (0 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL2CFGR_PLL2SRC_HSI (1 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL2CFGR_PLL2SRC_CSI (2 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL2CFGR_PLL2SRC_HSE (3 << RCC_PLL2CFGR_PLL2SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL2CFGR_PLL2RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL2CFGR_PLL2RGE_MASK (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) -# define RCC_PLL2CFGR_PLL2RGE_1_2M (0 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_2_4M (1 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_4_8M (2 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz */ -# define RCC_PLL2CFGR_PLL2RGE_8_16M (3 << RCC_PLL2CFGR_PLL2RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz */ - -#define RCC_PLL2CFGR_PLL2FRACEN (1 << 4) /* PLL2 Fractional Latch Enable */ -#define RCC_PLL2CFGR_PLL2VCOSEL (1 << 5) /* PLL2 VCO Selection */ - -#define RCC_PLL2CFGR_PLL2M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL2CFGR_PLL2M_MASK (0x3f << RCC_PLL2CFGR_PLL2M_SHIFT) -# define RCC_PLL2CFGR_PLL2M(n) ((n) << RCC_PLL2CFGR_PLL2M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL2CFGR_PLL2PEN (1 << 16) /* PLL2 DIVP divder output enable */ -#define RCC_PLL2CFGR_PLL2QEN (1 << 17) /* PLL2 DIVQ divder output enable */ -#define RCC_PLL2CFGR_PLL2REN (1 << 18) /* PLL2 DIVR divder output enable */ - -/* PLL3 configuration register */ - -#define RCC_PLL3CFGR_PLL3SRC_SHIFT (0) /* Bits 1-0: Main PLL(PLL) and audio PLLs (PLLSAIx) - * entry clock source */ -#define RCC_PLL3CFGR_PLL3SRC_MASK (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) -# define RCC_PLL3CFGR_PLL3SRC_NONE (0 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 000: No clock sent to PLLs */ -# define RCC_PLL3CFGR_PLL3SRC_HSI (1 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 001: HSI selected as PLL source */ -# define RCC_PLL3CFGR_PLL3SRC_CSI (2 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 010: CSI selected as PLL source */ -# define RCC_PLL3CFGR_PLL3SRC_HSE (3 << RCC_PLL3CFGR_PLL3SRC_SHIFT) /* 011: HSE selected as PLL source */ - -#define RCC_PLL3CFGR_PLL3RGE_SHIFT (2) /* Bit 3-2: */ -#define RCC_PLL3CFGR_PLL3RGE_MASK (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) -# define RCC_PLL3CFGR_PLL3RGE_1_2M (0 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 000: Input Clock Range Frequency 1-2 MHz */ -# define RCC_PLL3CFGR_PLL3RGE_2_4M (1 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 001: Input Clock Range Frequency 2-4 MHz */ -# define RCC_PLL3CFGR_PLL3RGE_4_8M (2 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 010: Input Clock Range Frequency 4-8 MHz **/ -# define RCC_PLL3CFGR_PLL3RGE_8_16M (3 << RCC_PLL3CFGR_PLL3RGE_SHIFT) /* 011: Input Clock Range Frequency 8-16 MHz **/ - -#define RCC_PLL3CFGR_PLL3FRACEN (1 << 4) /* PLL3 Fractional Latch Enable */ -#define RCC_PLL3CFGR_PLL3VCOSEL (1 << 5) /* PLL3 VCO Selection */ - -#define RCC_PLL3CFGR_PLL3M_SHIFT (8) /* Bit 13-8: */ -#define RCC_PLL3CFGR_PLL3M_MASK (0x3f << RCC_PLL3CFGR_PLL3M_SHIFT) -# define RCC_PLL3CFGR_PLL3M(n) ((n) << RCC_PLL3CFGR_PLL3M_SHIFT) /* m = 1..63 */ - -#define RCC_PLL3CFGR_PLL3PEN (1 << 16) /* PLL3 DIVP divder output enable */ -#define RCC_PLL3CFGR_PLL3QEN (1 << 17) /* PLL3 DIVQ divder output enable */ -#define RCC_PLL3CFGR_PLL3REN (1 << 18) /* PLL3 DIVR divder output enable */ - -/* PLL1 dividers register */ - -#define RCC_PLL1DIVR_PLL1N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL1DIVR_PLL1N_MASK (0x1ff << RCC_PLL1DIVR_PLL1N_SHIFT) -# define RCC_PLL1DIVR_PLL1N(n) ((n-1) << RCC_PLL1DIVR_PLL1N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL1DIVR_PLL1P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL1DIVR_PLL1P_MASK (0x7f << RCC_PLL1DIVR_PLL1P_SHIFT) -# define RCC_PLL1DIVR_PLL1P(n) ((n-1) << RCC_PLL1DIVR_PLL1P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL1DIVR_PLL1Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL1DIVR_PLL1Q_MASK (0x7f << RCC_PLL1DIVR_PLL1Q_SHIFT) -# define RCC_PLL1DIVR_PLL1Q(n) ((n-1) << RCC_PLL1DIVR_PLL1Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL1DIVR_PLL1R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL1DIVR_PLL1R_MASK (0x7f << RCC_PLL1DIVR_PLL1R_SHIFT) -# define RCC_PLL1DIVR_PLL1R(n) ((n-1) << RCC_PLL1DIVR_PLL1R_SHIFT) /* m = 1..128 */ - -/* PLL1 fractional divider register */ - -#define RCC_PLL1FRACR_PLL1FRACN_SHIFT (3) -#define RCC_PLL1FRACR_PLL1FRACN_MASK (0x1fff << RCC_PLL1FRACR_PLL1FRACN_SHIFT) -#define RCC_PLL1FRACR_PLL1FRACN(n) (n << RCC_PLL1FRACR_PLL1FRACN_SHIFT) /* m = 0..8192 */ - -/* PLL2 dividers register */ - -#define RCC_PLL2DIVR_PLL2N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL2DIVR_PLL2N_MASK (0x1ff << RCC_PLL2DIVR_PLL2N_SHIFT) -# define RCC_PLL2DIVR_PLL2N(n) ((n-1) << RCC_PLL2DIVR_PLL2N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL2DIVR_PLL2P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL2DIVR_PLL2P_MASK (0x7f << RCC_PLL2DIVR_PLL2P_SHIFT) -# define RCC_PLL2DIVR_PLL2P(n) ((n-1) << RCC_PLL2DIVR_PLL2P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL2DIVR_PLL2Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL2DIVR_PLL2Q_MASK (0x7f << RCC_PLL2DIVR_PLL2Q_SHIFT) -# define RCC_PLL2DIVR_PLL2Q(n) ((n-1) << RCC_PLL2DIVR_PLL2Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL2DIVR_PLL2R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL2DIVR_PLL2R_MASK (0x7f << RCC_PLL2DIVR_PLL2R_SHIFT) -# define RCC_PLL2DIVR_PLL2R(n) ((n-1) << RCC_PLL2DIVR_PLL2R_SHIFT) /* m = 1..128 */ - -/* PLL2 fractional divider register */ - -#define RCC_PLL2FRACR_PLL2FRACN_SHIFT (3) -#define RCC_PLL2FRACR_PLL2FRACN_MASK (0x1fff << RCC_PLL2FRACR_PLL2FRACN_SHIFT) -#define RCC_PLL2FRACR_PLL2FRACN(n) (n << RCC_PLL2FRACR_PLL2FRACN_SHIFT) /* m = 0..8192 */ - -/* PLL3 dividers register */ - -#define RCC_PLL3DIVR_PLL3N_SHIFT (0) /* Bits 8-0: */ -#define RCC_PLL3DIVR_PLL3N_MASK (0x1ff << RCC_PLL3DIVR_PLL3N_SHIFT) -# define RCC_PLL3DIVR_PLL3N(n) ((n-1) << RCC_PLL3DIVR_PLL3N_SHIFT) /* m = 4..512 */ - -#define RCC_PLL3DIVR_PLL3P_SHIFT (9) /* Bits 15-9: */ -#define RCC_PLL3DIVR_PLL3P_MASK (0x7f << RCC_PLL3DIVR_PLL3P_SHIFT) -# define RCC_PLL3DIVR_PLL3P(n) ((n-1) << RCC_PLL3DIVR_PLL3P_SHIFT) /* m = 2..128 evens */ - -#define RCC_PLL3DIVR_PLL3Q_SHIFT (16) /* Bits 22-16: */ -#define RCC_PLL3DIVR_PLL3Q_MASK (0x7f << RCC_PLL3DIVR_PLL3Q_SHIFT) -# define RCC_PLL3DIVR_PLL3Q(n) ((n-1) << RCC_PLL3DIVR_PLL3Q_SHIFT) /* m = 1..128 */ - -#define RCC_PLL3DIVR_PLL3R_SHIFT (24) /* Bits 30-24: */ -#define RCC_PLL3DIVR_PLL3R_MASK (0x7f << RCC_PLL3DIVR_PLL3R_SHIFT) -# define RCC_PLL3DIVR_PLL3R(n) ((n-1) << RCC_PLL3DIVR_PLL3R_SHIFT) /* m = 1..128 */ - -/* PLL3 fractional divider register */ - -#define RCC_PLL3FRACR_PLL3FRACN_SHIFT (3) -#define RCC_PLL3FRACR_PLL3FRACN_MASK (0x1fff << RCC_PLL3FRACR_PLL3FRACN_SHIFT) -#define RCC_PLL3FRACR_PLL3FRACN(n) (n << RCC_PLL3FRACR_PLL3FRACN_SHIFT) /* m = 0..8192 */ - -/* Clock interrupt enable register */ - -#define RCC_CIER_LSIRDYIE (1 << 0) /* Bit 0: LSI Ready Interrupt Enable */ -#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */ -#define RCC_CIER_CSIRDYIE (1 << 2) /* Bit 2: CSI Ready Interrupt Enable */ -#define RCC_CIER_HSIRDYIE (1 << 3) /* Bit 3: HSI Ready Interrupt Enable */ -#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */ -#define RCC_CIER_HSI48RDYIE (1 << 5) /* Bit 5: HSI48 Ready Interrupt Enable */ -#define RCC_CIER_PLL1RDYIE (1 << 6) /* Bit 6: PLL1 Ready Interrupt Enable */ -#define RCC_CIER_PLL2RDYIE (1 << 7) /* Bit 7: PLL2 Ready Interrupt Enable */ -#define RCC_CIER_PLL3RDYIE (1 << 8) /* Bit 8: PLL3 Ready Interrupt Enable */ - -/* Clock interrupt flag register */ - -#define RCC_CIFR_LSIRDYF (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ -#define RCC_CIFR_LSERDYF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ -#define RCC_CIFR_CSIRDYF (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ -#define RCC_CIFR_HSIRDYF (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ -#define RCC_CIFR_HSERDYF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ -#define RCC_CIFR_HSI48RDYF (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ -#define RCC_CIFR_PLL1RDYF (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ -#define RCC_CIFR_PLL2RDYF (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ -#define RCC_CIFR_PLL3RDYF (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ -#define RCC_CIFR_HSECSSF (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ - -/* Clock interrupt clear register */ - -#define RCC_CICR_LSIRDYC (1 << 0) /* Bit 0: LSI Ready Interrupt Flag */ -#define RCC_CICR_LSERDYC (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */ -#define RCC_CICR_CSIRDYC (1 << 2) /* Bit 2: CSI Ready Interrupt Flag */ -#define RCC_CICR_HSIRDYC (1 << 3) /* Bit 3: HSI Ready Interrupt Flag */ -#define RCC_CICR_HSERDYC (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */ -#define RCC_CICR_HSI48RDYC (1 << 5) /* Bit 5: HSI48 Ready Interrupt Flag */ -#define RCC_CICR_PLL1RDYC (1 << 6) /* Bit 6: PLL1 Ready Interrupt Flag */ -#define RCC_CICR_PLL2RDYC (1 << 7) /* Bit 7: PLL2 Ready Interrupt Flag */ -#define RCC_CICR_PLL3RDYC (1 << 8) /* Bit 8: PLL3 Ready Interrupt Flag */ -#define RCC_CICR_HSECSSC (1 << 10) /* Bit 10: HSE Clock Security System Interrupt Flag */ - -/* AHB1 peripheral reset register */ - -#define RCC_AHB1RSTR_GPDMA1RST (1 << 0) /* Bit 0: GPDMA1 reset */ -#define RCC_AHB1RSTR_GPDMA2RST (1 << 1) /* Bit 1: GPDMA2 reset */ -#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */ -#define RCC_AHB1RSTR_CORDICRST (1 << 14) /* Bit 14: CORDIC reset */ -#define RCC_AHB1RSTR_FMACRST (1 << 15) /* Bit 15: FMAC reset */ -#define RCC_AHB1RSTR_RAMCFGRST (1 << 17) /* Bit 17: RAMCFG reset */ -#define RCC_AHB1RSTR_ETHRST (1 << 19) /* Bit 19: ETH reset */ - -/* AHB2 peripheral reset register */ - -#define RCC_AHB2RSTR_GPIORST(n) (1 << (n)) -#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */ -#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */ -#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */ -#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */ -#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */ -#define RCC_AHB2RSTR_GPIOFRST (1 << 5) /* Bit 5: IO port F reset */ -#define RCC_AHB2RSTR_GPIOGRST (1 << 6) /* Bit 6: IO port G reset */ -#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */ -#define RCC_AHB2RSTR_GPIOIRST (1 << 8) /* Bit 8: IO port I reset */ -#define RCC_AHB2RSTR_ADCRST (1 << 10) /* Bit 10: ADC interface reset (common to all ADCs) */ -#define RCC_AHB2RSTR_DACRST (1 << 11) /* Bit 11: DAC Block reset */ -#define RCC_AHB2RSTR_DCMI_PSSIRST (1 << 12) /* Bit 12: Digital Camera Interface block reset */ -#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES Cryptographic module reset */ -#define RCC_AHB2RSTR_HASHRST (1 << 17) /* Bit 17: HASH block reset */ -#define RCC_AHB2RSTR_RNGRST (1 << 18) /* Bit 18: Random number generator module reset */ -#define RCC_AHB2RSTR_PKARST (1 << 19) /* Bit 19: Public Key Accelerator module reset */ -#define RCC_AHB2RSTR_SAESRST (1 << 20) /* Bit 20: SAES block reset */ - -/* AHB4 peripheral reset register */ - -#define RCC_AHB4RSTR_OTFDEC1RST (1 << 7) /* Bit 0: OTFDEC1 block reset */ -#define RCC_AHB4RSTR_SDMMC1RST (1 << 11) /* Bit 11: SDMMC1RST blocks reset */ -#define RCC_AHB4RSTR_SDMMC2RST (1 << 12) /* Bit 12: SDMMC2RST blocks reset */ -#define RCC_AHB4RSTR_FMCRST (1 << 16) /* Bit 16: FMC block reset */ -#define RCC_AHB4RSTR_OSPI1RST (1 << 20) /* Bit 20: OCTOSPI1 block reset */ - -/* APB1 Peripheral reset register 1 */ - -#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */ -#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* Bit 1: TIM3 reset */ -#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* Bit 2: TIM4 reset */ -#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* Bit 3: TIM5 reset */ -#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* Bit 4: TIM6 reset */ -#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* Bit 5: TIM7 reset */ -#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* Bit 5: TIM12 reset */ -#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* Bit 5: TIM13 reset */ -#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* Bit 5: TIM14 reset */ -#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */ -#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* Bit 15: SPI3 reset */ -#define RCC_APB1LRSTR_USART2RST (1 << 17) /* Bit 17: USART2 reset */ -#define RCC_APB1LRSTR_USART3RST (1 << 18) /* Bit 18: USART3 reset */ -#define RCC_APB1LRSTR_UART4RST (1 << 19) /* Bit 19: UART4 reset */ -#define RCC_APB1LRSTR_UART5RST (1 << 20) /* Bit 20: UART5 reset */ -#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */ -#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* Bit 22: I2C2 reset */ -#define RCC_APB1LRSTR_I3C1RST (1 << 23) /* Bit 23: I3C1 reset */ -#define RCC_APB1LRSTR_CRSRST (1 << 24) /* Bit 24: CRS reset */ -#define RCC_APB1LRSTR_USART6RST (1 << 25) /* Bit 25: USART6 reset */ -#define RCC_APB1LRSTR_USART10RST (1 << 26) /* Bit 26: USART10 reset */ -#define RCC_APB1LRSTR_USART11RST (1 << 27) /* Bit 27: USART11 reset */ -#define RCC_APB1LRSTR_CECRST (1 << 28) /* Bit 28: CEC reset */ -#define RCC_APB1LRSTR_UART7RST (1 << 30) /* Bit 30: UART7 reset */ -#define RCC_APB1LRSTR_UART8RST (1 << 31) /* Bit 31: UART8 reset */ - -/* APB1 Peripheral reset register 2 */ - -#define RCC_APB1HRSTR_UART9RST (1 << 0) /* Bit 0: UART9 reset */ -#define RCC_APB1HRSTR_UART12RST (1 << 1) /* Bit 1: UART12 reset */ -#define RCC_APB1HRSTR_DTSRST (1 << 3) /* Bit 3: DTS reset */ -#define RCC_APB1HRSTR_LPTIM2RST (1 << 5) /* Bit 5: Low-power Timer 2 reset */ -#define RCC_APB1HRSTR_FDCANRST (1 << 9) /* Bit 9: FDCAN reset */ -#define RCC_APB1HRSTR_UCPD1RST (1 << 23) /* Bit 23: UCPD1 reset */ - -/* APB2 Peripheral reset register */ - -#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */ -#define RCC_APB2RSTR_TIM8RST (1 << 13) /* Bit 13: TIM8 reset */ -#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ -#define RCC_APB2RSTR_TIM15RST (1 << 16) /* Bit 16: TIM15 reset */ -#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */ -#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */ -#define RCC_APB2RSTR_SPI4RST (1 << 19) /* Bit 19: SPI4 reset */ -#define RCC_APB2RSTR_SPI67RST (1 << 20) /* Bit 20: SPI6 reset */ -#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */ -#define RCC_APB2RSTR_SAI2RST (1 << 22) /* Bit 22: SAI2 reset */ -#define RCC_APB2RSTR_USBRST (1 << 24) /* Bit 24: USB reset */ - -/* APB3 Peripheral reset register */ - -#define RCC_APB3RSTR_SPI5RST (1 << 5) /* Bit 5: SPI5 reset */ -#define RCC_APB3RSTR_LPUART1RST (1 << 6) /* Bit 6: LPUART1 reset */ -#define RCC_APB3RSTR_I2C3RST (1 << 7) /* Bit 7: I2C3 reset */ -#define RCC_APB3RSTR_I2C4RST (1 << 8) /* Bit 8: I2C4 reset */ -#define RCC_APB3RSTR_I3C2RST (1 << 9) /* Bit 9: I3C2 reset */ -#define RCC_APB3RSTR_LPTIM1RST (1 << 11) /* Bit 11: LPTIM1 reset */ -#define RCC_APB3RSTR_LPTIM3RST (1 << 12) /* Bit 12: LPTIM3 reset */ -#define RCC_APB3RSTR_LPTIM4RST (1 << 13) /* Bit 13: LPTIM4 reset */ -#define RCC_APB3RSTR_LPTIM5RST (1 << 14) /* Bit 14: LPTIM5 reset */ -#define RCC_APB3RSTR_LPTIM6RST (1 << 15) /* Bit 15: LPTIM6 reset */ -#define RCC_APB3RSTR_VREFRST (1 << 20) /* Bit 20: VREF reset */ - -/* AHB1 Peripheral Clock enable register */ - -#define RCC_AHB1ENR_GPDMA1EN (1 << 0) /* Bit 0: GPDMA1 clock enable */ -#define RCC_AHB1ENR_GPDMA2EN (1 << 1) /* Bit 1: GPDMA2 clock enable */ -#define RCC_AHB1ENR_FLASHEN (1 << 8) /* Bit 8: Flash Interface clock enable */ -#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */ -#define RCC_AHB1ENR_CORDICEN (1 << 14) /* Bit 14: CORDIC clock enable */ -#define RCC_AHB1ENR_FMACEN (1 << 15) /* Bit 15: FMAC clock enable */ -#define RCC_AHB1ENR_RAMCFGEN (1 << 17) /* Bit 17: RAMCFG clock enable */ -#define RCC_AHB1ENR_ETHEN (1 << 19) /* Bit 19: ETH clock enable */ -#define RCC_AHB1ENR_ETHTXEN (1 << 20) /* Bit 20: ETH TX clock enable */ -#define RCC_AHB1ENR_ETHRXEN (1 << 21) /* Bit 21: ETH RX clock enable */ -#define RCC_AHB1ENR_TZSC1EN (1 << 24) /* Bit 24: TZSC1 clock enable */ -#define RCC_AHB1ENR_BKPRAMEN (1 << 28) /* Bit 28: BKPRAM clock enable */ -#define RCC_AHB1ENR_DCACHEEN (1 << 30) /* Bit 25: DCACHE clock enable */ -#define RCC_AHB1ENR_SRAM1EN (1 << 31) /* Bit 25: SRAM1 clock enable */ - -/* AHB2 Peripheral Clock enable register */ - -#define RCC_AHB2ENR_GPIOEN(n) (1 << (n)) -#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */ -#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */ -#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */ -#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D enable */ -#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E enable */ -#define RCC_AHB2ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F enable */ -#define RCC_AHB2ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G enable */ -#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H enable */ -#define RCC_AHB2ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I enable */ -#define RCC_AHB2ENR_ADCEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ -#define RCC_AHB2ENR_DAC1EN (1 << 11) /* Bit 11: DAC clock enable */ -#define RCC_AHB2ENR_DCMI_PSSIEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ -#define RCC_AHB2ENR_AESEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ -#define RCC_AHB2ENR_HASHEN (1 << 17) /* Bit 17: HASH module enable */ -#define RCC_AHB2ENR_RNGEN (1 << 18) /* Bit 18: Random number generator module enable */ -#define RCC_AHB2ENR_PKAEN (1 << 19) /* Bit 19: PKA clock enable */ -#define RCC_AHB2ENR_SAESEN (1 << 20) /* Bit 20: SAES clock enable */ -#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* Bit 30: SRAM2 clock enable */ -#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* Bit 30: SRAM2 clock enable */ - -/* AHB4 Peripheral Clock enable register */ - -#define RCC_AHB4ENR_OTFDEC1EN (1 << 7) /* Bit 7: On-the-fly decryption module clock enable */ -#define RCC_AHB4ENR_SDMMC1EN (1 << 11) /* Bit 11: SDMMC1 clock enable */ -#define RCC_AHB4ENR_SDMMC2EN (1 << 12) /* Bit 12: SDMMC2 clock enable */ -#define RCC_AHB4ENR_FMCEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ -#define RCC_AHB4ENR_OSPI1EN (1 << 20) /* Bit 20: OCTOSPI1 module enable */ - -/* APB1 Peripheral clock enable register 1 */ - -#define RCC_APB1LENR_TIM2EN (1 << 0) /* Bit 0: TIM2 clock enable */ -#define RCC_APB1LENR_TIM3EN (1 << 1) /* Bit 1: TIM3 clock enable */ -#define RCC_APB1LENR_TIM4EN (1 << 2) /* Bit 2: TIM4 clock enable */ -#define RCC_APB1LENR_TIM5EN (1 << 3) /* Bit 3: TIM5 clock enable */ -#define RCC_APB1LENR_TIM6EN (1 << 4) /* Bit 4: TIM6 clock enable */ -#define RCC_APB1LENR_TIM7EN (1 << 5) /* Bit 5: TIM7 clock enable */ -#define RCC_APB1LENR_TIM12EN (1 << 6) /* Bit 5: TIM12 clock enable */ -#define RCC_APB1LENR_TIM13EN (1 << 7) /* Bit 5: TIM13 clock enable */ -#define RCC_APB1LENR_TIM14EN (1 << 8) /* Bit 5: TIM14 clock enable */ -#define RCC_APB1LENR_SPI2EN (1 << 14) /* Bit 14: SPI2 clock enable */ -#define RCC_APB1LENR_SPI3EN (1 << 15) /* Bit 15: SPI3 clock enable */ -#define RCC_APB1LENR_USART2EN (1 << 17) /* Bit 17: USART2 clock enable */ -#define RCC_APB1LENR_USART3EN (1 << 18) /* Bit 18: USART3 clock enable */ -#define RCC_APB1LENR_UART4EN (1 << 19) /* Bit 19: UART4 clock enable */ -#define RCC_APB1LENR_UART5EN (1 << 20) /* Bit 20: UART5 clock enable */ -#define RCC_APB1LENR_I2C1EN (1 << 21) /* Bit 21: I2C1 clock enable */ -#define RCC_APB1LENR_I2C2EN (1 << 22) /* Bit 22: I2C2 clock enable */ -#define RCC_APB1LENR_I3C1EN (1 << 23) /* Bit 23: I3C1 clock enable */ -#define RCC_APB1LENR_CRSEN (1 << 24) /* Bit 24: CRS clock enable */ -#define RCC_APB1LENR_USART6EN (1 << 25) /* Bit 25: USART6 clock enable */ -#define RCC_APB1LENR_USART10EN (1 << 26) /* Bit 26: USART10 clock enable */ -#define RCC_APB1LENR_USART11EN (1 << 27) /* Bit 27: USART11 clock enable */ -#define RCC_APB1LENR_CECEN (1 << 28) /* Bit 28: CEC clock enable */ -#define RCC_APB1LENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */ -#define RCC_APB1LENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */ - -/* APB1 Peripheral clock enable register 2 */ - -#define RCC_APB1HENR_UART9EN (1 << 0) /* Bit 0: UART9 clock enable */ -#define RCC_APB1HENR_UART12EN (1 << 1) /* Bit 1: UART12 clock enable */ -#define RCC_APB1HENR_DTSEN (1 << 3) /* Bit 3: DTS clock enable */ -#define RCC_APB1HENR_LPTIM2EN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable */ -#define RCC_APB1HENR_FDCANEN (1 << 9) /* Bit 9: FDCAN clock enable */ -#define RCC_APB1HENR_UCPD1EN (1 << 23) /* Bit 23: UCPD1 clock enable */ - -/* APB2 Peripheral clock enable register */ - -#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 clock enable */ -#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */ -#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 clock enable */ -#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ -#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: TIM15 clock enable */ -#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 clock enable */ -#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 clock enable */ -#define RCC_APB2ENR_SPI4EN (1 << 19) /* Bit 19: SPI4 clock enable */ -#define RCC_APB2ENR_SPI67EN (1 << 20) /* Bit 20: SPI6 clock enable */ -#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 clock enable */ -#define RCC_APB2ENR_SAI2EN (1 << 22) /* Bit 22: SAI2 clock enable */ -#define RCC_APB2ENR_USBEN (1 << 24) /* Bit 24: USB clock enable */ - -/* APB3 Peripheral clock enable register */ - -#define RCC_APB3ENR_SBSEN (1 << 1) /* Bit 1: SBS clock enable */ -#define RCC_APB3ENR_SPI5EN (1 << 5) /* Bit 5: SPI5 clock enable */ -#define RCC_APB3ENR_LPUART1EN (1 << 6) /* Bit 6: LPUART1 clock enable */ -#define RCC_APB3ENR_I2C3EN (1 << 7) /* Bit 7: I2C3 clock enable */ -#define RCC_APB3ENR_I2C4EN (1 << 8) /* Bit 8: I2C4 clock enable */ -#define RCC_APB3ENR_I3C2EN (1 << 9) /* Bit 9: I3C2 clock enable */ -#define RCC_APB3ENR_LPTIM1EN (1 << 11) /* Bit 11: LPTIM1 clock enable */ -#define RCC_APB3ENR_LPTIM3EN (1 << 12) /* Bit 12: LPTIM3 clock enable */ -#define RCC_APB3ENR_LPTIM4EN (1 << 13) /* Bit 13: LPTIM4 clock enable */ -#define RCC_APB3ENR_LPTIM5EN (1 << 14) /* Bit 14: LPTIM5 clock enable */ -#define RCC_APB3ENR_LPTIM6EN (1 << 15) /* Bit 15: LPTIM6 clock enable */ -#define RCC_APB3ENR_VREFEN (1 << 20) /* Bit 20: VREF clock enable */ -#define RCC_APB3ENR_RTCAPBEN (1 << 21) /* Bit 21: RTCABP clock enable */ - -/* RCC AHB1 Sleep and Stop modes peripheral clock enable register */ - -#define RCC_AHB1LPENR_GPDMA1LPEN (1 << 0) /* Bit 0: GPDMA1 clock enable during sleep mode */ -#define RCC_AHB1LPENR_GPDMA2LPEN (1 << 1) /* Bit 1: GPDMA2 clock enable during sleep mode */ -#define RCC_AHB1LPENR_FLITFLPEN (1 << 8) /* Bit 8: Flash Interface clock enable during sleep mode */ -#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during sleep mode */ -#define RCC_AHB1LPENR_CORDICLPEN (1 << 14) /* Bit 14: CORDIC clock enable during sleep mode */ -#define RCC_AHB1LPENR_FMACLPEN (1 << 15) /* Bit 15: FMAC clock enable during sleep mode */ -#define RCC_AHB1LPENR_RAMCFGLPEN (1 << 17) /* Bit 17: RAMCFG clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHLPEN (1 << 19) /* Bit 19: ETH clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHTXLPEN (1 << 20) /* Bit 20: ETH TX clock enable during sleep mode */ -#define RCC_AHB1LPENR_ETHRXLPEN (1 << 21) /* Bit 21: ETH RX clock enable during sleep mode */ -#define RCC_AHB1LPENR_TZSC1LPEN (1 << 24) /* Bit 24: TZSC1 clock enable during sleep mode */ -#define RCC_AHB1LPENR_BKPRAMLPEN (1 << 28) /* Bit 28: BKPRAM clock enable during sleep mode */ -#define RCC_AHB1LPENR_DCACHELPEN (1 << 30) /* Bit 25: DCACHE clock enable during sleep mode */ -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 31) /* Bit 25: SRAM1 clock enable during sleep mode */ - -/* RCC AHB2 low power mode peripheral clock enable register */ - -#define RCC_AHB2LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during sleep mode */ -#define RCC_AHB2LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during sleep mode */ -#define RCC_AHB2LPENR_ADCLPEN (1 << 10) /* Bit 10: ADC interface enable (common to all ADCs) */ -#define RCC_AHB2LPENR_DAC1LPEN (1 << 11) /* Bit 11: DAC clock enable during sleep mode */ -#define RCC_AHB2LPENR_DCMI_PSSILPEN (1 << 12) /* Bit 12: Digital Camera Interface Clock Enable */ -#define RCC_AHB2LPENR_AESLPEN (1 << 16) /* Bit 16: AES Cryptographic module enable */ -#define RCC_AHB2LPENR_HASHLPEN (1 << 17) /* Bit 17: HASH module enable */ -#define RCC_AHB2LPENR_RNGLPEN (1 << 18) /* Bit 18: Random number generator module enable */ -#define RCC_AHB2LPENR_PKALPEN (1 << 19) /* Bit 19: PKA clock enable during sleep mode */ -#define RCC_AHB2LPENR_SAESLPEN (1 << 20) /* Bit 20: SAES clock enable during sleep mode */ -#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* Bit 30: SRAM2 clock enable during sleep mode */ -#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* Bit 30: SRAM2 clock enable during sleep mode */ - -/* RCC AHB4 low power mode peripheral clock enable register */ - -#define RCC_AHB4LPENR_OTFDEC1LPEN (1 << 7) /* Bit 7: OTFDEC1 clock enable during sleep mode */ -#define RCC_AHB4LPENR_SDMMC1LPEN (1 << 11) /* Bit 11: SDMMC1 clock enable during sleep mode */ -#define RCC_AHB4LPENR_SDMMC2LPEN (1 << 12) /* Bit 12: SDMMC2 clock enable during sleep mode */ -#define RCC_AHB4LPENR_FMCLPEN (1 << 16) /* Bit 16: Flexible memory controller module enable */ -#define RCC_AHB4LPENR_OSPI1LPEN (1 << 20) /* Bit 20: OCTOSPI1 module clock enable during sleep mode */ - -/* APB1 Peripheral clock enable register 1 */ - -#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* Bit 0: TIM2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* Bit 1: TIM3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* Bit 2: TIM4 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* Bit 3: TIM5 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* Bit 4: TIM6 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* Bit 5: TIM7 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* Bit 6: TIM12 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* Bit 7: TIM13 clock enable during sleep mode */ -#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* Bit 8: TIM14 clock enable during sleep mode */ -#define RCC_APB1LLPENR_WWDGLPEN (1 << 11) /* Bit 11: WWDG clock enable during sleep mode */ -#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* Bit 14: SPI2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* Bit 15: SPI3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* Bit 17: USART2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* Bit 18: USART3 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* Bit 19: UART4 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* Bit 20: UART5 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* Bit 21: I2C1 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* Bit 22: I2C2 clock enable during sleep mode */ -#define RCC_APB1LLPENR_I3C1LPEN (1 << 23) /* Bit 23: I3C1 clock enable during sleep mode */ -#define RCC_APB1LLPENR_CRSLPEN (1 << 24) /* Bit 24: CRS clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART6LPEN (1 << 25) /* Bit 25: USART6 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART10LPEN (1 << 26) /* Bit 26: USART10 clock enable during sleep mode */ -#define RCC_APB1LLPENR_USART11LPEN (1 << 27) /* Bit 27: USART11 clock enable during sleep mode */ -#define RCC_APB1LLPENR_CECLPEN (1 << 28) /* Bit 28: CEC clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during sleep mode */ -#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during sleep mode */ - -/* APB1 Peripheral clock enable register 2 */ - -#define RCC_APB1HLPENR_UART9LPEN (1 << 0) /* Bit 0: UART9 clock enable during sleep mode */ -#define RCC_APB1HLPENR_UART12LPEN (1 << 1) /* Bit 1: UART12 clock enable during sleep mode */ -#define RCC_APB1HLPENR_DTSLPEN (1 << 3) /* Bit 3: DTS clock enable during sleep mode */ -#define RCC_APB1HLPENR_LPTIM2LPEN (1 << 5) /* Bit 5: Low-power Timer 2 clock enable during sleep mode */ -#define RCC_APB1HLPENR_FDCANLPEN (1 << 9) /* Bit 9: FDCAN clock enable during sleep mode */ -#define RCC_APB1HLPENR_UCPD1LPEN (1 << 23) /* Bit 23: UCPD1 clock enable during sleep mode */ - -/* APB2 Peripheral clock enable register */ - -#define RCC_APB2LPENR_TIM1LPEN (1 << 11) /* Bit 11: TIM1 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM8LPEN (1 << 13) /* Bit 13: TIM8 clock enable during sleep mode */ -#define RCC_APB2LPENR_USART1LPEN (1 << 14) /* Bit 14: USART1 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* Bit 16: TIM15 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* Bit 17: TIM16 clock enable during sleep mode */ -#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* Bit 18: TIM17 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI4LPEN (1 << 19) /* Bit 19: SPI4 clock enable during sleep mode */ -#define RCC_APB2LPENR_SPI67LPEN (1 << 20) /* Bit 20: SPI6 clock enable during sleep mode */ -#define RCC_APB2LPENR_SAI1LPEN (1 << 21) /* Bit 21: SAI1 clock enable during sleep mode */ -#define RCC_APB2LPENR_SAI2LPEN (1 << 22) /* Bit 22: SAI2 clock enable during sleep mode */ -#define RCC_APB2LPENR_USBLPEN (1 << 24) /* Bit 24: USB clock enable during sleep mode */ - -/* APB3 Peripheral clock enable register */ - -#define RCC_APB3LPENR_SBSLPEN (1 << 1) /* Bit 1: SBS clock enable during sleep mode */ -#define RCC_APB3LPENR_SPI5LPEN (1 << 5) /* Bit 5: SPI5 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPUART1LPEN (1 << 6) /* Bit 6: LPUART1 clock enable during sleep mode */ -#define RCC_APB3LPENR_I2C3LPEN (1 << 7) /* Bit 7: I2C3 clock enable during sleep mode */ -#define RCC_APB3LPENR_I2C4LPEN (1 << 8) /* Bit 8: I2C4 clock enable during sleep mode */ -#define RCC_APB3LPENR_I3C2LPEN (1 << 9) /* Bit 9: I3C2 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM1LPEN (1 << 11) /* Bit 11: LPTIM1 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM3LPEN (1 << 12) /* Bit 12: LPTIM3 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM4LPEN (1 << 13) /* Bit 13: LPTIM4 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM5LPEN (1 << 14) /* Bit 14: LPTIM5 clock enable during sleep mode */ -#define RCC_APB3LPENR_LPTIM6LPEN (1 << 15) /* Bit 15: LPTIM6 clock enable during sleep mode */ -#define RCC_APB3LPENR_VREFLPEN (1 << 20) /* Bit 20: VREF clock enable during sleep mode */ -#define RCC_APB3LPENR_RTCAPBLPEN (1 << 21) /* Bit 21: RTCABP clock enable during sleep mode */ - -/* Kernel Clock Configuration register 1 */ - -#define RCC_CCIPR1_USART1SEL_SHIFT (0) -#define RCC_CCIPR1_USART1SEL_MASK (7 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_PLL2QCK (1 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_PLL3QCK (2 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_HSIKERCK (3 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_CSIKERCK (4 << RCC_CCIPR1_USART1SEL_SHIFT) -# define RCC_CCIPR1_USART1SEL_LSECK (5 << RCC_CCIPR1_USART1SEL_SHIFT) - -#define RCC_CCIPR1_USART2SEL_SHIFT (3) -#define RCC_CCIPR1_USART2SEL_MASK (7 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_PLL2QCK (1 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_PLL3QCK (2 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_HSIKERCK (3 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_CSIKERCK (4 << RCC_CCIPR1_USART2SEL_SHIFT) -# define RCC_CCIPR1_USART2SEL_LSECK (5 << RCC_CCIPR1_USART2SEL_SHIFT) - -#define RCC_CCIPR1_USART3SEL_SHIFT (6) -#define RCC_CCIPR1_USART3SEL_MASK (7 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_PLL2QCK (1 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_PLL3QCK (2 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_HSIKERCK (3 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_CSIKERCK (4 << RCC_CCIPR1_USART3SEL_SHIFT) -# define RCC_CCIPR1_USART3SEL_LSECK (5 << RCC_CCIPR1_USART3SEL_SHIFT) - -#define RCC_CCIPR1_UART4SEL_SHIFT (9) -#define RCC_CCIPR1_UART4SEL_MASK (7 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_PLL2QCK (1 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_PLL3QCK (2 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_HSIKERCK (3 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_CSIKERCK (4 << RCC_CCIPR1_UART4SEL_SHIFT) -# define RCC_CCIPR1_UART4SEL_LSECK (5 << RCC_CCIPR1_UART4SEL_SHIFT) - -#define RCC_CCIPR1_UART5SEL_SHIFT (12) -#define RCC_CCIPR1_UART5SEL_MASK (7 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_PLL2QCK (1 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_PLL3QCK (2 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_HSIKERCK (3 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_CSIKERCK (4 << RCC_CCIPR1_UART5SEL_SHIFT) -# define RCC_CCIPR1_UART5SEL_LSECK (5 << RCC_CCIPR1_UART5SEL_SHIFT) - -#define RCC_CCIPR1_UART6SEL_SHIFT (15) -#define RCC_CCIPR1_UART6SEL_MASK (7 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_PLL2QCK (1 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_PLL3QCK (2 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_HSIKERCK (3 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_CSIKERCK (4 << RCC_CCIPR1_UART6SEL_SHIFT) -# define RCC_CCIPR1_UART6SEL_LSECK (5 << RCC_CCIPR1_UART6SEL_SHIFT) - -#define RCC_CCIPR1_UART7SEL_SHIFT (18) -#define RCC_CCIPR1_UART7SEL_MASK (7 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_PLL2QCK (1 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_PLL3QCK (2 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_HSIKERCK (3 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_CSIKERCK (4 << RCC_CCIPR1_UART7SEL_SHIFT) -# define RCC_CCIPR1_UART7SEL_LSECK (5 << RCC_CCIPR1_UART7SEL_SHIFT) - -#define RCC_CCIPR1_UART8SEL_SHIFT (21) -#define RCC_CCIPR1_UART8SEL_MASK (7 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_PLL2QCK (1 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_PLL3QCK (2 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_HSIKERCK (3 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_CSIKERCK (4 << RCC_CCIPR1_UART8SEL_SHIFT) -# define RCC_CCIPR1_UART8SEL_LSECK (5 << RCC_CCIPR1_UART8SEL_SHIFT) - -#define RCC_CCIPR1_UART9SEL_SHIFT (24) -#define RCC_CCIPR1_UART9SEL_MASK (7 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_RCCPCLK1 (0 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_PLL2QCK (1 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_PLL3QCK (2 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_HSIKERCK (3 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_CSIKERCK (4 << RCC_CCIPR1_UART9SEL_SHIFT) -# define RCC_CCIPR1_UART9SEL_LSECK (5 << RCC_CCIPR1_UART9SEL_SHIFT) - -#define RCC_CCIPR1_USART10SEL_SHIFT (27) -#define RCC_CCIPR1_USART10SEL_MASK (7 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_RCCPCLK1 (0 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_PLL2QCK (1 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_PLL3QCK (2 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_HSIKERCK (3 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_CSIKERCK (4 << RCC_CCIPR1_USART10SEL_SHIFT) -# define RCC_CCIPR1_USART10SEL_LSECK (5 << RCC_CCIPR1_USART10SEL_SHIFT) - -#define RCC_CCIPR1_TIMICSEL (1 << 31) - -/* Kernel Clock Configuration register 2 */ - -#define RCC_CCIPR2_USART11SEL_SHIFT (0) -#define RCC_CCIPR2_USART11SEL_MASK (7 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_PLL2QCK (1 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_PLL3QCK (2 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_HSIKERCK (3 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_CSIKERCK (4 << RCC_CCIPR2_USART11SEL_SHIFT) -# define RCC_CCIPR2_USART11SEL_LSECK (5 << RCC_CCIPR2_USART11SEL_SHIFT) - -#define RCC_CCIPR2_USART12SEL_SHIFT (4) -#define RCC_CCIPR2_USART12SEL_MASK (7 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_RCCPCLK1 (0 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_PLL2QCK (1 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_PLL3QCK (2 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_HSIKERCK (3 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_CSIKERCK (4 << RCC_CCIPR2_USART12SEL_SHIFT) -# define RCC_CCIPR2_USART12SEL_LSECK (5 << RCC_CCIPR2_USART12SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM1SEL_SHIFT (8) -#define RCC_CCIPR2_LPTIM1SEL_MASK (7 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM1SEL_SHIFT) -# define RCC_CCIPR2_LPTIM1SEL_LSECK (5 << RCC_CCIPR2_LPTIM1SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM2SEL_SHIFT (12) -#define RCC_CCIPR2_LPTIM2SEL_MASK (7 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_RCCPCLK1 (0 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM2SEL_SHIFT) -# define RCC_CCIPR2_LPTIM2SEL_LSECK (5 << RCC_CCIPR2_LPTIM2SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM3SEL_SHIFT (16) -#define RCC_CCIPR2_LPTIM3SEL_MASK (7 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM3SEL_SHIFT) -# define RCC_CCIPR2_LPTIM3SEL_LSECK (5 << RCC_CCIPR2_LPTIM3SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM4SEL_SHIFT (20) -#define RCC_CCIPR2_LPTIM4SEL_MASK (7 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM4SEL_SHIFT) -# define RCC_CCIPR2_LPTIM4SEL_LSECK (5 << RCC_CCIPR2_LPTIM4SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM5SEL_SHIFT (24) -#define RCC_CCIPR2_LPTIM5SEL_MASK (7 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM5SEL_SHIFT) -# define RCC_CCIPR2_LPTIM5SEL_LSECK (5 << RCC_CCIPR2_LPTIM5SEL_SHIFT) - -#define RCC_CCIPR2_LPTIM6SEL_SHIFT (28) -#define RCC_CCIPR2_LPTIM6SEL_MASK (7 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_RCCPCLK3 (0 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_PLL2PCK (1 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_PLL3RCK (2 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_HSIKERCK (3 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_CSIKERCK (4 << RCC_CCIPR2_LPTIM6SEL_SHIFT) -# define RCC_CCIPR2_LPTIM6SEL_LSECK (5 << RCC_CCIPR2_LPTIM6SEL_SHIFT) - -/* Kernel Clock Configuration register 3 */ - -#define RCC_CCIPR3_SPI1SEL_SHIFT (0) -#define RCC_CCIPR3_SPI1SEL_MASK (7 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL1QCK (0 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL2PCK (1 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PLL3PCK (2 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_AUDIOCK (3 << RCC_CCIPR3_SPI1SEL_SHIFT) -# define RCC_CCIPR3_SPI1SEL_PERCK (4 << RCC_CCIPR3_SPI1SEL_SHIFT) - -#define RCC_CCIPR3_SPI2SEL_SHIFT (3) -#define RCC_CCIPR3_SPI2SEL_MASK (7 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL1QCK (0 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL2PCK (1 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PLL3PCK (2 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_AUDIOCK (3 << RCC_CCIPR3_SPI2SEL_SHIFT) -# define RCC_CCIPR3_SPI2SEL_PERCK (4 << RCC_CCIPR3_SPI2SEL_SHIFT) - -#define RCC_CCIPR3_SPI3SEL_SHIFT (6) -#define RCC_CCIPR3_SPI3SEL_MASK (7 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL1QCK (0 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL2PCK (1 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PLL3PCK (2 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_AUDIOCK (3 << RCC_CCIPR3_SPI3SEL_SHIFT) -# define RCC_CCIPR3_SPI3SEL_PERCK (4 << RCC_CCIPR3_SPI3SEL_SHIFT) - -#define RCC_CCIPR3_SPI4SEL_SHIFT (9) -#define RCC_CCIPR3_SPI4SEL_MASK (7 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_PLL2QCK (1 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_PLL3QCK (2 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_HSIKERCK (3 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_CSIKERCK (4 << RCC_CCIPR3_SPI4SEL_SHIFT) -# define RCC_CCIPR3_SPI4SEL_HSECK (5 << RCC_CCIPR3_SPI4SEL_SHIFT) - -#define RCC_CCIPR3_SPI5SEL_SHIFT (12) -#define RCC_CCIPR3_SPI5SEL_MASK (7 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_RCCPCLK3 (0 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_PLL2QCK (1 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_PLL3QCK (2 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_HSIKERCK (3 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_CSIKERCK (4 << RCC_CCIPR3_SPI5SEL_SHIFT) -# define RCC_CCIPR3_SPI5SEL_HSECK (5 << RCC_CCIPR3_SPI5SEL_SHIFT) - -#define RCC_CCIPR3_SPI6SEL_SHIFT (15) -#define RCC_CCIPR3_SPI6SEL_MASK (7 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_RCCPCLK2 (0 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_PLL2QCK (1 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_PLL3QCK (2 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_HSIKERCK (3 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_CSIKERCK (4 << RCC_CCIPR3_SPI6SEL_SHIFT) -# define RCC_CCIPR3_SPI6SEL_HSECK (5 << RCC_CCIPR3_SPI6SEL_SHIFT) - -#define RCC_CCIPR3_LPUART1SEL_SHIFT (24) -#define RCC_CCIPR3_LPUART1SEL_MASK (7 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_RCCPCLK3 (0 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_PLL2QCK (1 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_PLL3QCK (2 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_HSIKERCK (3 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_CSIKERCK (4 << RCC_CCIPR3_LPUART1SEL_SHIFT) -# define RCC_CCIPR3_LPUART1SEL_LSECK (5 << RCC_CCIPR3_LPUART1SEL_SHIFT) - -/* Kernel Clock Configuration register 4 */ - -#define RCC_CCIPR4_OCTOSPI1SEL_SHIFT (0) -#define RCC_CCIPR4_OCTOSPI1SEL_MASK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_RCCHCLK4 (0 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PLL1QCK (1 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PLL2RCK (2 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) -# define RCC_CCIPR4_OCTOSPI1SEL_PERCK (3 << RCC_CCIPR4_OCTOSPI1SEL_SHIFT) - -#define RCC_CCIPR4_SYSTICKSEL_SHIFT (2) -#define RCC_CCIPR4_SYSTICKSEL_MASK (3 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_RCCHCLKd8 (0 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_LSIKERCK1 (1 << RCC_CCIPR4_SYSTICKSEL_SHIFT) -# define RCC_CCIPR4_SYSTICKSEL_LSICK1 (2 << RCC_CCIPR4_SYSTICKSEL_SHIFT) - -#define RCC_CCIPR4_USBSEL_SHIFT (4) -#define RCC_CCIPR4_USBSEL_MASK (3 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_NOCK (0 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_PLL1QCK (1 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_PLL3QCK (2 << RCC_CCIPR4_USBSEL_SHIFT) -# define RCC_CCIPR4_USBSEL_HSI48KERCK (3 << RCC_CCIPR4_USBSEL_SHIFT) - -#define RCC_CCIPR4_SDMMC1SEL (1 << 6) -#define RCC_CCIPR4_SDMMC2SEL (1 << 7) - -#define RCC_CCIPR4_I2C1SEL_SHIFT (16) -#define RCC_CCIPR4_I2C1SEL_MASK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_PLL3RCK (1 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_HSIKERCK (2 << RCC_CCIPR4_I2C1SEL_SHIFT) -# define RCC_CCIPR4_I2C1SEL_CSIKERCK (3 << RCC_CCIPR4_I2C1SEL_SHIFT) - -#define RCC_CCIPR4_I2C2SEL_SHIFT (18) -#define RCC_CCIPR4_I2C2SEL_MASK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_PLL3RCK (1 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_HSIKERCK (2 << RCC_CCIPR4_I2C2SEL_SHIFT) -# define RCC_CCIPR4_I2C2SEL_CSIKERCK (3 << RCC_CCIPR4_I2C2SEL_SHIFT) - -#define RCC_CCIPR4_I2C3SEL_SHIFT (20) -#define RCC_CCIPR4_I2C3SEL_MASK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_PLL3RCK (1 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_HSIKERCK (2 << RCC_CCIPR4_I2C3SEL_SHIFT) -# define RCC_CCIPR4_I2C3SEL_CSIKERCK (3 << RCC_CCIPR4_I2C3SEL_SHIFT) - -#define RCC_CCIPR4_I2C4SEL_SHIFT (22) -#define RCC_CCIPR4_I2C4SEL_MASK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_RCCPCLK3 (0 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_PLL3RCK (1 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_HSIKERCK (2 << RCC_CCIPR4_I2C4SEL_SHIFT) -# define RCC_CCIPR4_I2C4SEL_CSIKERCK (3 << RCC_CCIPR4_I2C4SEL_SHIFT) - -#define RCC_CCIPR4_I3C1SEL_SHIFT (24) -#define RCC_CCIPR4_I3C1SEL_MASK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_PLL3RCK (1 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_HSIKERCK (2 << RCC_CCIPR4_I3C1SEL_SHIFT) -# define RCC_CCIPR4_I3C1SEL_NOCK (3 << RCC_CCIPR4_I3C1SEL_SHIFT) - -#define RCC_CCIPR4_I3C2SEL_SHIFT (24) -#define RCC_CCIPR4_I3C2SEL_MASK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_RCCPCLK1 (0 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_PLL3RCK (1 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_HSIKERCK (2 << RCC_CCIPR4_I3C2SEL_SHIFT) -# define RCC_CCIPR4_I3C2SEL_NOCK (3 << RCC_CCIPR4_I3C2SEL_SHIFT) - -/* Kernel Clock Configuration register 5 */ - -#define RCC_CCIPR5_ADCDACSEL_SHIFT (0) -#define RCC_CCIPR5_ADCDACSEL_MASK (7 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_RCCHCLK (0 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_SYSCK (1 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_PLL2RCK (2 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_HSECK (3 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_HSEKERCK (4 << RCC_CCIPR5_ADCDACSEL_SHIFT) -# define RCC_CCIPR5_ADCDACSEL_CSIKERCK (5 << RCC_CCIPR5_ADCDACSEL_SHIFT) - -#define RCC_CCIPR5_DACSEL (1 << 3) - -#define RCC_CCIPR5_RNGSEL_SHIFT (4) -#define RCC_CCIPR5_RNGSEL_MASK (3 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_HSI48KERCK (0 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_PLL1QCK (1 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_LSECK (2 << RCC_CCIPR5_RNGSEL_SHIFT) -# define RCC_CCIPR5_RNGSEL_LSIKERCK (3 << RCC_CCIPR5_RNGSEL_SHIFT) - -#define RCC_CCIPR5_CECSEL_SHIFT (6) -#define RCC_CCIPR5_CECSEL_MASK (3 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_LSECK (0 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_LSIKERCK (1 << RCC_CCIPR5_CECSEL_SHIFT) -# define RCC_CCIPR5_CECSEL_CSIKERCKd122 (2 << RCC_CCIPR5_CECSEL_SHIFT) - -#define RCC_CCIPR5_FDCANSEL_SHIFT (8) -#define RCC_CCIPR5_FDCANSEL_MASK (3 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_HSECK (0 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_PLL1QCK (1 << RCC_CCIPR5_FDCANSEL_SHIFT) -# define RCC_CCIPR5_FDCANSEL_PLL2QCK (2 << RCC_CCIPR5_FDCANSEL_SHIFT) - -#define RCC_CCIPR5_SAI1SEL_SHIFT (16) -#define RCC_CCIPR5_SAI1SEL_MASK (7 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL1QCK (0 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL2PCK (1 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PLL3PCK (2 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI1SEL_SHIFT) -# define RCC_CCIPR5_SAI1SEL_PERCK (4 << RCC_CCIPR5_SAI1SEL_SHIFT) - -#define RCC_CCIPR5_SAI2SEL_SHIFT (19) -#define RCC_CCIPR5_SAI2SEL_MASK (7 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL1QCK (0 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL2PCK (1 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PLL3PCK (2 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_AUDIOCLK (3 << RCC_CCIPR5_SAI2SEL_SHIFT) -# define RCC_CCIPR5_SAI2SEL_PERCK (4 << RCC_CCIPR5_SAI2SEL_SHIFT) - -#define RCC_CCIPR5_CKPERSEL_SHIFT (30) -#define RCC_CCIPR5_CKPERSEL_MASK (3 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_HSIKERCK (0 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_CSIKERCK (1 << RCC_CCIPR5_CKPERSEL_SHIFT) -# define RCC_CCIPR5_CKPERSEL_HSECK (2 << RCC_CCIPR5_CKPERSEL_SHIFT) - -/* Backup domain control register */ - -#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ - -#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */ -#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) -# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */ -# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */ -# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/ -# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */ - -#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */ -#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */ -#define RCC_BDCR_LSEEXT (1 << 7) /* Bit 7: LSE external clock type in bypass mode */ - -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ -#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) -# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ -# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */ - -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_VSWRST (1 << 16) /* Bit 16: VSwitch domain software reset */ -#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */ -#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */ -# define RCC_BCDR_LSCOSEL_LSI 0 /* LSI selected */ -# define RCC_BDCR_LSCOSEL_LSE RCC_BDCR_LSCOSEL /* LSE selected */ - -#define RCC_BDCR_LSION (1 << 26) /* Bit 26: LSI Oscillator Enable */ -#define RCC_BDCR_LSIRDY (1 << 27) /* Bit 27: LSI Oscillator Ready */ - -/* Reset status register */ - -#define RCC_RSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */ -#define RCC_RSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */ -#define RCC_RSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */ -#define RCC_RSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */ -#define RCC_RSR_IWDGRSTF (1 << 29) /* Bit 29: Independent Watchdog reset flag */ -#define RCC_RSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ -#define RCC_RSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ - -/* Secure Configuration Register */ - -#define RCC_SECCFGR_HSISEC (1 << 0) /* HSI clock configuration and status bits security */ -#define RCC_SECCFGR_HSESEC (1 << 1) /* HSE clock configuration and status bits security */ -#define RCC_SECCFGR_CSISEC (1 << 2) /* CSI clock configuration and status bits security */ -#define RCC_SECCFGR_LSISEC (1 << 3) /* LSI clock configuration and status bits security */ -#define RCC_SECCFGR_LSESEC (1 << 4) /* LSE clock configuration and status bits security */ -#define RCC_SECCFGR_SYSCLKSEC (1 << 5) /* SYSCLK configuration and status bits security */ -#define RCC_SECCFGR_PRESCSEC (1 << 6) /* PRESC configuration and status bits security */ -#define RCC_SECCFGR_PLL1SEC (1 << 7) /* PLL1 configuration and status bits security */ -#define RCC_SECCFGR_PLL2SEC (1 << 8) /* PLL2 configuration and status bits security */ -#define RCC_SECCFGR_PLL3SEC (1 << 9) /* PLL3 configuration and status bits security */ -#define RCC_SECCFGR_HSI48SEC (1 << 11) /* HSI48 configuration and status bits security */ -#define RCC_SECCFGR_RMVRST (1 << 12) /* Remove Reset flag security */ -#define RCC_SECCFGR_CKPERSELSEC (1 << 13) /* PER_CK selection security */ - -/* Privilege Configuration Register */ - -#define RCC_PRIVCFGR_SPRIV (1 << 0) /* Secure functions privilege configuration */ -#define RCC_PRIVCFGR_NSPRIV (1 << 1) /* Non-secure functions privilege configuration */ - -#endif /* CONFIG_STM32_STM32H562XX */ -#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H5XXX_RCC_H */ diff --git a/arch/arm/src/stm32h5/stm32_lsi.c b/arch/arm/src/stm32h5/stm32_lsi.c deleted file mode 100644 index 463f05cd51c20..0000000000000 --- a/arch/arm/src/stm32h5/stm32_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 1333ef56ae551..c80bb699e53f0 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -58,7 +58,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_pinmap.h" #include "hardware/stm32_usbfs.h" -#include "hardware/stm32h5xxx_rcc.h" +#include "hardware/stm32_rcc.h" #include "hardware/stm32h5xxx_pwr.h" #include "stm32_usbdrdhost.h" diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 7965169017968..56808e63dc5b5 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -96,10 +96,6 @@ if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) - list(APPEND SRCS stm32_lsi.c) -endif() - if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index e1f6fd958b949..e08ef3619cea3 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -95,10 +95,6 @@ ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) -CHIP_CSRCS += stm32_lsi.c -endif - ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 67ef3c5d180ed..293ccdca13679 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -28,20 +28,1134 @@ ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32H7X0XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X3XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7B3XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X5XX) -# include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32_STM32H7X7XX) -# include "hardware/stm32h7x3xx_rcc.h" -#else -# error "Unsupported STM32 H7 part" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* TODO: Complete comments */ + +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 +#define STM32_RCC_CRRCR_OFFSET 0x0008 +#define STM32_RCC_CFGR_OFFSET 0x0010 /* Clock configuration register */ +#define STM32_RCC_D1CFGR_OFFSET 0x0018 +#define STM32_RCC_D2CFGR_OFFSET 0x001c +#define STM32_RCC_D3CFGR_OFFSET 0x0020 +#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 +#define STM32_RCC_PLLCFGR_OFFSET 0x002c +#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 +#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 +#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 +#define STM32_RCC_PLL2FRACR_OFFSET 0x003c +#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 +#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 +#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */ +#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */ +#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */ +#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* Domain 3 Kernel Clock configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0060 /* Clock Source Interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x0064 /* Clock Source Interrupt Flag register */ +#define STM32_RCC_CICR_OFFSET 0x0068 /* Clock Source Interrupt Clear register */ +#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup Domain Control register */ +#define STM32_RCC_CSR_OFFSET 0x0074 /* Clock Control and Status register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0080 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x0084 /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x007c /* AHB3 peripheral reset register */ +#define STM32_RCC_AHB4RSTR_OFFSET 0x0088 /* AHB4 peripheral reset register */ +#define STM32_RCC_APB1LRSTR_OFFSET 0x0090 /* APB1 L Peripheral reset register */ +#define STM32_RCC_APB1HRSTR_OFFSET 0x0094 /* APB1 H Peripheral reset register */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */ +#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */ +#define STM32_RCC_GCR_OFFSET 0x00a0 /* RCC Global Control register */ +#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* D3 Autonomous mode register */ +#define STM32_RCC_RSR_OFFSET 0x00d0 /* RCC Reset Status register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_AHB4ENR_OFFSET 0x00e0 /* AHB4 Peripheral Clock enable register */ +#define STM32_RCC_APB1LENR_OFFSET 0x00e8 /* APB1 L Peripheral Clock enable register */ +#define STM32_RCC_APB1HENR_OFFSET 0x00ec /* APB1 H Peripheral Clock enable register */ +#define STM32_RCC_APB2ENR_OFFSET 0x00f0 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_APB3ENR_OFFSET 0x00e4 /* APB3 Peripheral Clock enable register */ +#define STM32_RCC_APB4ENR_OFFSET 0x00f4 /* APB4 Peripheral Clock enable register */ +#define STM32_RCC_AHB1LPENR_OFFSET 0x0100 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2LPENR_OFFSET 0x0104 /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3LPENR_OFFSET 0x00fc /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB4LPENR_OFFSET 0x0108 /* RCC AHB4 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1LLPENR_OFFSET 0x0110 /* RCC APB1 L low power mode peripheral clock enable register */ +#define STM32_RCC_APB1HLPENR_OFFSET 0x0114 /* RCC APB1 H low power mode peripheral clock enable register */ +#define STM32_RCC_APB2LPENR_OFFSET 0x0118 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_APB3LPENR_OFFSET 0x010c /* RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB4LPENR_OFFSET 0x011c /* RCC APB4 low power mode peripheral clock enable register */ + +/* Register Addresses *******************************************************/ + +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_D1CFGR (STM32_RCC_BASE + STM32_RCC_D1CFGR_OFFSET) +#define STM32_RCC_D2CFGR (STM32_RCC_BASE + STM32_RCC_D2CFGR_OFFSET) +#define STM32_RCC_D3CFGR (STM32_RCC_BASE + STM32_RCC_D3CFGR_OFFSET) +#define STM32_RCC_PLLCKSELR (STM32_RCC_BASE + STM32_RCC_PLLCKSELR_OFFSET) +#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET) +#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) +#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) +#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) +#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) +#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) +#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) +#define STM32_RCC_D1CCIPR (STM32_RCC_BASE + STM32_RCC_D1CCIPR_OFFSET) +#define STM32_RCC_D2CCIP1R (STM32_RCC_BASE + STM32_RCC_D2CCIP1R_OFFSET) +#define STM32_RCC_D2CCIP2R (STM32_RCC_BASE + STM32_RCC_D2CCIP2R_OFFSET) +#define STM32_RCC_D3CCIPR (STM32_RCC_BASE + STM32_RCC_D3CCIPR_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) +#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) +#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_APB4RSTR (STM32_RCC_BASE + STM32_RCC_APB4RSTR_OFFSET) +#define STM32_RCC_GCR (STM32_RCC_BASE + STM32_RCC_GCR_OFFSET) +#define STM32_RCC_D3AMR (STM32_RCC_BASE + STM32_RCC_D3AMR_OFFSET) +#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) +#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) +#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) +#define STM32_RCC_APB4ENR (STM32_RCC_BASE + STM32_RCC_APB4ENR_OFFSET) +#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) +#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) +#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE + STM32_RCC_AHB3LPENR_OFFSET) +#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) +#define STM32_RCC_APB1LLPENR (STM32_RCC_BASE + STM32_RCC_APB1LLPENR_OFFSET) +#define STM32_RCC_APB1HLPENR (STM32_RCC_BASE + STM32_RCC_APB1HLPENR_OFFSET) +#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) +#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) +#define STM32_RCC_APB4LPENR (STM32_RCC_BASE + STM32_RCC_APB4LPENR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +/* Source Control Register */ + +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ +#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ +#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) +# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ + /* Bit 6: Reserved */ +#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ + /* Bits 10-11: Reserved */ +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ +#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ +#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ + /* Bits 20-23: Reserved */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ + /* Bits 30-31: Reserved */ + +/* Internal Clock Source Calibration Register */ + +/* HSICAL configuration */ + +#define RCC_ICSCR_HSICAL_SHIFT (0ul) +#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) +#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ + +/* HSITRIM configuration */ + +#define RCC_ICSCR_HSITRIM_SHIFT (12ul) +#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) +#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ + +/* CSICAL configuration */ + +#define RCC_ICSCR_CSICAL_SHIFT (18ul) +#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) +#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ + +/* CSITRIM configuration */ + +#define RCC_ICSCR_CSITRIM_SHIFT (26ul) +#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) +#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ + +/* Clock Recovery RC Register */ + +/* HSI48CAL configuration */ + +#define RCC_CRRCR_HSI48CAL_SHIFT (0ul) +#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) +#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ + +/* Clock Configuration Register (CFGR) */ + +#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ +#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ +# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ +# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ +# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ +# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ +#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ +#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) +#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ +#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ +#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) +#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ +#define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ +# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ +#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) +#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ +#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT) +# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */ +# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */ +# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */ + +/* Bit definitions for RCC_D1CFGR */ + +#define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ +#define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) + +#define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ +#define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) + /* Bit 7: Reserved */ +#define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ +#define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) + /* Bits 12-31: Reserved */ + +/* Bit definitions for RCC_D2CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ +#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) +# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) + /* Bit 7: Reserved */ +#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ +#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) +# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) + /* Bits 11-31: Reserved */ + +/* Bit definitions for RCC_D3CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ +#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) +# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) + /* Bits 7-31: Reserved */ + +/* Bit definitions for RCC_PLLCKSELR register */ + +#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ +#define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK + +#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ + +#define RCC_PLLCKSELR_DIVM1_SHIFT (4ul) +#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM2_SHIFT (12ul) +#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ +#define RCC_PLLCKSELR_DIVM3_SHIFT (20ul) +#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ + +/* Bit definition for RCC_PLLCFGR register */ + +#define RCC_PLLCFGR_RESET ((uint32_t)0x01FF0000) + +#define RCC_PLLCFGR_PLL1FRACEN_SHIFT (0ul) +#define RCC_PLLCFGR_PLL1FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL1FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL1VCOSEL_SHIFT (1ul) +#define RCC_PLLCFGR_PLL1VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL1VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL1RGE_SHIFT (2ul) +#define RCC_PLLCFGR_PLL1RGE_MASK (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) +#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_MASK +#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (4ul) +#define RCC_PLLCFGR_PLL2FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL2FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (5ul) +#define RCC_PLLCFGR_PLL2VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL2VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_SHIFT (6ul) +#define RCC_PLLCFGR_PLL2RGE_MASK (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) +#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_MASK +#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (8ul) +#define RCC_PLLCFGR_PLL3FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL3FRACEN_SHIFT) +#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ +#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (9ul) +#define RCC_PLLCFGR_PLL3VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL3VCOSEL_SHIFT) +#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ +#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_SHIFT (10ul) +#define RCC_PLLCFGR_PLL3RGE_MASK (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) +#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_MASK +#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ +#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ +#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ +#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ + +#define RCC_PLLCFGR_DIVP1EN_SHIFT (16ul) +#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) +#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_MASK +#define RCC_PLLCFGR_DIVQ1EN_SHIFT (17ul) +#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) +#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_MASK +#define RCC_PLLCFGR_DIVR1EN_SHIFT (18ul) +#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) +#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_MASK + +#define RCC_PLLCFGR_DIVP2EN_SHIFT (19ul) +#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) +#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_MASK +#define RCC_PLLCFGR_DIVQ2EN_SHIFT (20ul) +#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) +#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_MASK +#define RCC_PLLCFGR_DIVR2EN_SHIFT (21ul) +#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) +#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_MASK + +#define RCC_PLLCFGR_DIVP3EN_SHIFT (22ul) +#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) +#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_MASK +#define RCC_PLLCFGR_DIVQ3EN_SHIFT (23ul) +#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) +#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_MASK +#define RCC_PLLCFGR_DIVR3EN_SHIFT (24ul) +#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) +#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_MASK + +/* Bit definitions for RCC_PLL1DIVR register */ + +#define RCC_PLL1DIVR_N1_SHIFT (0ul) +#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL1DIVR_P1_SHIFT (9ul) +#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ +#define RCC_PLL1DIVR_Q1_SHIFT (16ul) +#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL1DIVR_R1_SHIFT (24ul) +#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL1FRACR register */ + +#define RCC_PLL1FRACR_FRACN1_SHIFT (3ul) +#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) +#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_MASK + +/* Bit definitions for RCC_PLL2DIVR register */ + +#define RCC_PLL2DIVR_N2_SHIFT (0ul) +#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL2DIVR_P2_SHIFT (9ul) +#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL2DIVR_Q2_SHIFT (16ul) +#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL2DIVR_R2_SHIFT (24ul) +#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL2FRACR register */ + +#define RCC_PLL2FRACR_FRACN2_SHIFT (3ul) +#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) +#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_MASK + +/* Bit definitions for RCC_PLL3DIVR register */ + +#define RCC_PLL3DIVR_N3_SHIFT (0ul) +#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ +#define RCC_PLL3DIVR_P3_SHIFT (9ul) +#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ +#define RCC_PLL3DIVR_Q3_SHIFT (16ul) +#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ +#define RCC_PLL3DIVR_R3_SHIFT (24ul) +#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ + +/* Bit definitions for RCC_PLL3FRACR register */ + +#define RCC_PLL3FRACR_FRACN3_SHIFT (3ul) +#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) +#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK + +/* Bit definitions for RCC_D1CCIPR register */ + +#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ +#define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) +# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) + /* Bits 2-3: Reserved */ +#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ +#define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) +# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) + /* Bits 6-15: Reserved */ +#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ +#define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) +# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) +# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) + /* Bits 17-27: Reserved */ +#define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ +#define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) +# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) + /* Bits 30-31: Reserved */ + +/* Bit definitions for RCC_D2CCIP1R register */ + +#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ +#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) +# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) +# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) + /* Bits 3-5: Reserved */ +#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ +#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) +# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) + /* Bits 9-11: Reserved */ +#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ +#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) +# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) + /* Bit 15: Reserved */ +#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ +#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) +# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) + /* Bit 19: Reserved */ +#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ +#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) +# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) + /* Bits 22-23: Reserved */ +#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ +#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) +# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) +# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) + /* Bits 25-27: Reserved */ +#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ +#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) +# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) + /* Bit 30: Reserved */ +#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ +#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) +# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) +# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) + +/* Bit definitions for RCC_D2CCIP2R register */ + +#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ +# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_RCC (0 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_PLL2 (1 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_PLL3 (2 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_HSI (3 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_CSI (4 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +# define RCC_D2CCIP2R_USART234578SEL_LSE (5 << RCC_D2CCIP2R_USART234578SEL_SHIFT) +#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ +# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_RCC (0 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_PLL2 (1 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_PLL3 (2 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_HSI (3 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_CSI (4 << RCC_D2CCIP2R_USART16SEL_SHIFT) +# define RCC_D2CCIP2R_USART16SEL_LSE (5 << RCC_D2CCIP2R_USART16SEL_SHIFT) + /* Bits 6-7: Reserved */ +#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ +# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) + /* Bits 10-11: Reserved */ +#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ +#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) +# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) + /* Bits 14-19: Reserved */ +#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ +# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT) +# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) +#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ +# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) + /* Bits 24-27: Reserved */ +#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ +# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) + /* Bit 31: Reserved */ + +/* Bit definitions for RCC_D3CCIPR register */ + +#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ +#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) +# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) + /* Bits 3-7: Reserved */ +#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ +#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) +# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) +#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) +#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ +#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) +#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ +#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) +# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) + /* Bits 18-20: Reserved */ +#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) +#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ +#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) +#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ +#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) +# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) + /* Bit 31: Reserved */ + +/* TODO: CIER */ + +/* TODO: CIFR */ + +/* TODO: CICR */ + +/* TODO: BDCR */ + +/* Bit definitions for RCC_CSR register */ + +#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */ +#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */ + +/* AHB3 peripheral reset register */ + +#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */ +#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */ +#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */ +#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */ +#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */ +#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */ +#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */ + +/* AHB1 peripheral reset register */ + +#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ +#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ +#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ + /* Bits 6-14: Reserved */ +#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ + /* Bits 16-24: Reserved */ +#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ + /* Bit 26: Reserved */ +#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ + /* Bits 28-31: Reserved */ + +/* AHB2 peripheral reset register */ + +#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ + /* Bits 1-3: Reserved */ +#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ +#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ +#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ + /* Bits 7-8: Reserved */ +#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ + /* Bits 10-31: Reserved */ + +/* AHB4 peripheral reset register */ + +#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ +#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ +#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ +#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ +#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ +#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ +#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ +#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ +#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ +#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ +#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ + /* Bits 11-18: Reserved */ +#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ + /* Bit 20: Reserved */ +#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ + /* Bits 22-23: Reserved */ +#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ +#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ + /* Bits 26-31: Reserved */ + +/* APB3 peripheral reset register */ + + /* Bits 0-2: Reserved */ +#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ + /* Bits 4-31: Reserved */ + +/* APB3 L peripheral reset register */ + +#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ +#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ +#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ +#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ +#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ +#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ +#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ +#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ +#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ +#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ + /* Bits 10-13: Reserved */ +#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ +#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ +#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ +#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ +#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ +#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ +#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ +#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ +#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ +#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ + /* Bits 24-26: Reserved */ +#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ + /* Bit 28: Reserved */ +#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ +#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ +#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ + +/* APB1 H peripheral reset register */ + + /* Bit 0: Reserved */ +#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ +#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ + +/* Bit 3: Reserved */ + +#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ +#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ + +/* Bits 9-31: Reserved */ + +/* APB2 peripheral reset register */ + +#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ +#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ +#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ +#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ +#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ +#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ +#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ +#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ +#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ +#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ +#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ +#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ +#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ +#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ + +/* APB4 peripheral reset register */ + +#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ +#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ +#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ +#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ +#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ +#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ +#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ +#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ +#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ +#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ +#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ + +/* RCC Global Control register */ + +#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ +#ifdef CONFIG_STM32_HAVE_CM4 +# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ +#endif +#ifdef CONFIG_STM32_HAVE_CM4 +# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ +# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif +/* TODO: D3 Autonomous mode register */ + +/* RCC Reset Status register */ + + /* Bits 0-15: Reserved */ +#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ +#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ + /* Bit 18: Reserved */ +#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ +#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ +#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ +#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ +#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ +#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ + /* Bit 25: Reserved */ +#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ + /* Bit 27: Reserved */ +#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ + /* Bit 29: Reserved */ +#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ + /* Bit 31: Reserved */ + +/* AHB3 Peripheral Clock enable register */ + +#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ +#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ +#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ +#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ +#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ +#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ + +/* AHB1 Peripheral Clock enable register */ + +#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ +#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ +#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ +#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ +#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ +#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ +#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ +#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ + +/* AHB2 Peripheral Clock enable register */ + +#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ +#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ +#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ +#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ +#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ +#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ +#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ +#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ + +/* AHB4 Peripheral Clock enable register */ + +#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ +#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ +#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ +#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ +#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ +#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ +#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ +#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ +#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ +#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ +#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ +#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ +#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ +#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ +#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ +#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ + +/* APB3 Peripheral Clock enable register */ + +#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ +#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ + +/* APB1 L Peripheral Clock enable register */ + +#define RCC_APB1LENR_TIM2EN (1 << 0) /* RCC APB1LENR: TIM2EN */ +#define RCC_APB1LENR_TIM3EN (1 << 1) /* RCC APB1LENR: TIM3EN */ +#define RCC_APB1LENR_TIM4EN (1 << 2) /* RCC APB1LENR: TIM4EN */ +#define RCC_APB1LENR_TIM5EN (1 << 3) /* RCC APB1LENR: TIM5EN */ +#define RCC_APB1LENR_TIM6EN (1 << 4) /* RCC APB1LENR: TIM6EN */ +#define RCC_APB1LENR_TIM7EN (1 << 5) /* RCC APB1LENR: TIM7EN */ +#define RCC_APB1LENR_TIM12EN (1 << 6) /* RCC APB1LENR: TIM12EN */ +#define RCC_APB1LENR_TIM13EN (1 << 7) /* RCC APB1LENR: TIM13EN */ +#define RCC_APB1LENR_TIM14EN (1 << 8) /* RCC APB1LENR: TIM14EN */ +#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* RCC APB1LENR: LPTIM1EN */ + /* Bits 10-13: Reserved */ +#define RCC_APB1LENR_SPI2EN (1 << 14) /* RCC APB1LENR: SPI2EN */ +#define RCC_APB1LENR_SPI3EN (1 << 15) /* RCC APB1LENR: SPI3EN */ +#define RCC_APB1LENR_SPDIFRXEN (1 << 16) /* RCC APB1LENR: SPDIFRXEN */ +#define RCC_APB1LENR_USART2EN (1 << 17) /* RCC APB1LENR: USART2EN */ +#define RCC_APB1LENR_USART3EN (1 << 18) /* RCC APB1LENR: USART3EN */ +#define RCC_APB1LENR_UART4EN (1 << 19) /* RCC APB1LENR: UART4EN */ +#define RCC_APB1LENR_UART5EN (1 << 20) /* RCC APB1LENR: UART5EN */ +#define RCC_APB1LENR_I2C1EN (1 << 21) /* RCC APB1LENR: I2C1EN */ +#define RCC_APB1LENR_I2C2EN (1 << 22) /* RCC APB1LENR: I2C2EN */ +#define RCC_APB1LENR_I2C3EN (1 << 23) /* RCC APB1LENR: I2C3EN */ + /* Bits 24-25: Reserved */ +#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */ + /* Bit 28: Reserved */ +#define RCC_APB1LENR_DAC1EN (1 << 29) /* RCC APB1LENR: DAC1EN */ +#define RCC_APB1LENR_UART7EN (1 << 30) /* RCC APB1LENR: UART7EN */ +#define RCC_APB1LENR_UART8EN (1 << 31) /* RCC APB1LENR: UART8EN */ + +/* APB1 H Peripheral Clock enable register */ + + /* Bit 0: Reserved */ +#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ +#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ + /* Bit 3: Reserved */ +#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ +#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ + /* Bits 6-7: Reserved */ +#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ + /* Bits 9-31: Reserved */ + +/* APB2 Peripheral Clock enable register */ + +#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ +#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ + /* Bits 2-3: Reserved */ +#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ +#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ + /* Bits 6-11: Reserved */ +#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ +#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ + /* Bits 14-15: Reserved */ +#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ +#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ +#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ +#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ + /* Bit 21: Reserved */ +#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ +#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ +#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ + /* Bits 25-27: Reserved */ +#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ +#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ + /* Bits 30-31: Reserved */ + +/* APB4 Peripheral Clock enable register */ + + /* Bit 0: Reserved */ +#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ + /* Bit 2: Reserved */ +#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ + /* Bit 4: Reserved */ +#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ + /* Bit 6: Reserved */ +#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ + /* Bit 8: Reserved */ +#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ +#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ +#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ +#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ + /* Bit 13: Reserved */ +#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ +#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ +#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ + /* Bits 17-20: Reserved */ +#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ + /* Bit2 22-31: Reserved */ + +/* AHB3 low power mode peripheral clock enable register */ + +#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ +#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ +#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ +#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ +#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ +#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ +#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ +#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ +#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ +#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ +#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ + +/* AHB1 low power mode peripheral clock enable register */ + +#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ +#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ +#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ +#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ +#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ +#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ +#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ + +/* AHB2 low power mode peripheral clock enable register */ + +#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ +#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ +#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ +#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ +#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ +#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ +#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ + +/* AHB4 low power mode peripheral clock enable register */ + +#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ +#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ +#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ +#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ +#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ +#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ +#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ +#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ +#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ +#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ +#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ +#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ +#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ +#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ +#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ +#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ + +/* APB3 low power mode peripheral clock enable register */ + +#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ +#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ + +/* APB1 L low power mode peripheral clock enable register */ + +#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ +#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ +#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ +#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ +#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ +#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ +#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ +#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ +#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ +#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ +#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ +#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ +#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ +#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ +#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ +#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ +#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ +#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ +#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ +#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ +#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ +#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ +#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ +#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ + +/* APB1 H low power mode peripheral clock enable register */ + +#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ +#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ +#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ +#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ +#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ + +/* APB2 low power mode peripheral clock enable register */ + +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ +#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ +#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ +#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ +#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ +#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ +#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ +#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ +#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ +#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ +#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ +#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ +#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ + +/* APB4 low power mode peripheral clock enable register */ + +#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ +#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ +#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ +#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ +#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ +#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ +#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ +#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ +#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ +#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ +#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ +#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ + +/* Backup domain control register */ + +#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ +#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ +#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) /* See errata ES0392 Rev 7. 2.2.14 */ +# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ +# define RCC_BDCR_LSEDRV_MEDHI_Y (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability rev y */ +# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium high driving capability */ +# define RCC_BDCR_LSEDRV_MEDLO_Y (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability rev y */ +# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium low driving capability */ +# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ +#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ +#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ + /* Bit 7: Reserved */ +#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ +#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) +# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ +# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ +# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ + /* Bits 10-15: Reserved */ +#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ +#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ + /* Bits 17-31: Reserved */ + #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h deleted file mode 100644 index 308dc30f621db..0000000000000 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ /dev/null @@ -1,1161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H -#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -/* TODO: Complete comments */ - -#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32_RCC_ICSCR_OFFSET 0x0004 -#define STM32_RCC_CRRCR_OFFSET 0x0008 -#define STM32_RCC_CFGR_OFFSET 0x0010 /* Clock configuration register */ -#define STM32_RCC_D1CFGR_OFFSET 0x0018 -#define STM32_RCC_D2CFGR_OFFSET 0x001c -#define STM32_RCC_D3CFGR_OFFSET 0x0020 -#define STM32_RCC_PLLCKSELR_OFFSET 0x0028 -#define STM32_RCC_PLLCFGR_OFFSET 0x002c -#define STM32_RCC_PLL1DIVR_OFFSET 0x0030 -#define STM32_RCC_PLL1FRACR_OFFSET 0x0034 -#define STM32_RCC_PLL2DIVR_OFFSET 0x0038 -#define STM32_RCC_PLL2FRACR_OFFSET 0x003c -#define STM32_RCC_PLL3DIVR_OFFSET 0x0040 -#define STM32_RCC_PLL3FRACR_OFFSET 0x0044 -#define STM32_RCC_D1CCIPR_OFFSET 0x004c /* Domain 1 Kernel Clock configuration register */ -#define STM32_RCC_D2CCIP1R_OFFSET 0x0050 /* Domain 2 Kernel Clock configuration register 1 */ -#define STM32_RCC_D2CCIP2R_OFFSET 0x0054 /* Domain 2 Kernel Clock configuration register 2 */ -#define STM32_RCC_D3CCIPR_OFFSET 0x0058 /* Domain 3 Kernel Clock configuration register */ -#define STM32_RCC_CIER_OFFSET 0x0060 /* Clock Source Interrupt enable register */ -#define STM32_RCC_CIFR_OFFSET 0x0064 /* Clock Source Interrupt Flag register */ -#define STM32_RCC_CICR_OFFSET 0x0068 /* Clock Source Interrupt Clear register */ -#define STM32_RCC_BDCR_OFFSET 0x0070 /* Backup Domain Control register */ -#define STM32_RCC_CSR_OFFSET 0x0074 /* Clock Control and Status register */ -#define STM32_RCC_AHB1RSTR_OFFSET 0x0080 /* AHB1 peripheral reset register */ -#define STM32_RCC_AHB2RSTR_OFFSET 0x0084 /* AHB2 peripheral reset register */ -#define STM32_RCC_AHB3RSTR_OFFSET 0x007c /* AHB3 peripheral reset register */ -#define STM32_RCC_AHB4RSTR_OFFSET 0x0088 /* AHB4 peripheral reset register */ -#define STM32_RCC_APB1LRSTR_OFFSET 0x0090 /* APB1 L Peripheral reset register */ -#define STM32_RCC_APB1HRSTR_OFFSET 0x0094 /* APB1 H Peripheral reset register */ -#define STM32_RCC_APB2RSTR_OFFSET 0x0098 /* APB2 Peripheral reset register */ -#define STM32_RCC_APB3RSTR_OFFSET 0x008c /* APB3 Peripheral reset register */ -#define STM32_RCC_APB4RSTR_OFFSET 0x009c /* APB4 Peripheral reset register */ -#define STM32_RCC_GCR_OFFSET 0x00a0 /* RCC Global Control register */ -#define STM32_RCC_D3AMR_OFFSET 0x00a8 /* D3 Autonomous mode register */ -#define STM32_RCC_RSR_OFFSET 0x00d0 /* RCC Reset Status register */ -#define STM32_RCC_AHB1ENR_OFFSET 0x00d8 /* AHB1 Peripheral Clock enable register */ -#define STM32_RCC_AHB2ENR_OFFSET 0x00dc /* AHB2 Peripheral Clock enable register */ -#define STM32_RCC_AHB3ENR_OFFSET 0x00d4 /* AHB3 Peripheral Clock enable register */ -#define STM32_RCC_AHB4ENR_OFFSET 0x00e0 /* AHB4 Peripheral Clock enable register */ -#define STM32_RCC_APB1LENR_OFFSET 0x00e8 /* APB1 L Peripheral Clock enable register */ -#define STM32_RCC_APB1HENR_OFFSET 0x00ec /* APB1 H Peripheral Clock enable register */ -#define STM32_RCC_APB2ENR_OFFSET 0x00f0 /* APB2 Peripheral Clock enable register */ -#define STM32_RCC_APB3ENR_OFFSET 0x00e4 /* APB3 Peripheral Clock enable register */ -#define STM32_RCC_APB4ENR_OFFSET 0x00f4 /* APB4 Peripheral Clock enable register */ -#define STM32_RCC_AHB1LPENR_OFFSET 0x0100 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB2LPENR_OFFSET 0x0104 /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB3LPENR_OFFSET 0x00fc /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32_RCC_AHB4LPENR_OFFSET 0x0108 /* RCC AHB4 low power mode peripheral clock enable register */ -#define STM32_RCC_APB1LLPENR_OFFSET 0x0110 /* RCC APB1 L low power mode peripheral clock enable register */ -#define STM32_RCC_APB1HLPENR_OFFSET 0x0114 /* RCC APB1 H low power mode peripheral clock enable register */ -#define STM32_RCC_APB2LPENR_OFFSET 0x0118 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32_RCC_APB3LPENR_OFFSET 0x010c /* RCC APB3 low power mode peripheral clock enable register */ -#define STM32_RCC_APB4LPENR_OFFSET 0x011c /* RCC APB4 low power mode peripheral clock enable register */ - -/* Register Addresses *******************************************************/ - -#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) -#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) -#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) -#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) -#define STM32_RCC_D1CFGR (STM32_RCC_BASE + STM32_RCC_D1CFGR_OFFSET) -#define STM32_RCC_D2CFGR (STM32_RCC_BASE + STM32_RCC_D2CFGR_OFFSET) -#define STM32_RCC_D3CFGR (STM32_RCC_BASE + STM32_RCC_D3CFGR_OFFSET) -#define STM32_RCC_PLLCKSELR (STM32_RCC_BASE + STM32_RCC_PLLCKSELR_OFFSET) -#define STM32_RCC_PLLCFGR (STM32_RCC_BASE + STM32_RCC_PLLCFGR_OFFSET) -#define STM32_RCC_PLL1DIVR (STM32_RCC_BASE + STM32_RCC_PLL1DIVR_OFFSET) -#define STM32_RCC_PLL1FRACR (STM32_RCC_BASE + STM32_RCC_PLL1FRACR_OFFSET) -#define STM32_RCC_PLL2DIVR (STM32_RCC_BASE + STM32_RCC_PLL2DIVR_OFFSET) -#define STM32_RCC_PLL2FRACR (STM32_RCC_BASE + STM32_RCC_PLL2FRACR_OFFSET) -#define STM32_RCC_PLL3DIVR (STM32_RCC_BASE + STM32_RCC_PLL3DIVR_OFFSET) -#define STM32_RCC_PLL3FRACR (STM32_RCC_BASE + STM32_RCC_PLL3FRACR_OFFSET) -#define STM32_RCC_D1CCIPR (STM32_RCC_BASE + STM32_RCC_D1CCIPR_OFFSET) -#define STM32_RCC_D2CCIP1R (STM32_RCC_BASE + STM32_RCC_D2CCIP1R_OFFSET) -#define STM32_RCC_D2CCIP2R (STM32_RCC_BASE + STM32_RCC_D2CCIP2R_OFFSET) -#define STM32_RCC_D3CCIPR (STM32_RCC_BASE + STM32_RCC_D3CCIPR_OFFSET) -#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) -#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) -#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) -#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) -#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) -#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) -#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) -#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) -#define STM32_RCC_AHB4RSTR (STM32_RCC_BASE + STM32_RCC_AHB4RSTR_OFFSET) -#define STM32_RCC_APB1LRSTR (STM32_RCC_BASE + STM32_RCC_APB1LRSTR_OFFSET) -#define STM32_RCC_APB1HRSTR (STM32_RCC_BASE + STM32_RCC_APB1HRSTR_OFFSET) -#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) -#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) -#define STM32_RCC_APB4RSTR (STM32_RCC_BASE + STM32_RCC_APB4RSTR_OFFSET) -#define STM32_RCC_GCR (STM32_RCC_BASE + STM32_RCC_GCR_OFFSET) -#define STM32_RCC_D3AMR (STM32_RCC_BASE + STM32_RCC_D3AMR_OFFSET) -#define STM32_RCC_RSR (STM32_RCC_BASE + STM32_RCC_RSR_OFFSET) -#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) -#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) -#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) -#define STM32_RCC_AHB4ENR (STM32_RCC_BASE + STM32_RCC_AHB4ENR_OFFSET) -#define STM32_RCC_APB1LENR (STM32_RCC_BASE + STM32_RCC_APB1LENR_OFFSET) -#define STM32_RCC_APB1HENR (STM32_RCC_BASE + STM32_RCC_APB1HENR_OFFSET) -#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) -#define STM32_RCC_APB3ENR (STM32_RCC_BASE + STM32_RCC_APB3ENR_OFFSET) -#define STM32_RCC_APB4ENR (STM32_RCC_BASE + STM32_RCC_APB4ENR_OFFSET) -#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE + STM32_RCC_AHB1LPENR_OFFSET) -#define STM32_RCC_AHB2LPENR (STM32_RCC_BASE + STM32_RCC_AHB2LPENR_OFFSET) -#define STM32_RCC_AHB3LPENR (STM32_RCC_BASE + STM32_RCC_AHB3LPENR_OFFSET) -#define STM32_RCC_AHB4LPENR (STM32_RCC_BASE + STM32_RCC_AHB4LPENR_OFFSET) -#define STM32_RCC_APB1LLPENR (STM32_RCC_BASE + STM32_RCC_APB1LLPENR_OFFSET) -#define STM32_RCC_APB1HLPENR (STM32_RCC_BASE + STM32_RCC_APB1HLPENR_OFFSET) -#define STM32_RCC_APB2LPENR (STM32_RCC_BASE + STM32_RCC_APB2LPENR_OFFSET) -#define STM32_RCC_APB3LPENR (STM32_RCC_BASE + STM32_RCC_APB3LPENR_OFFSET) -#define STM32_RCC_APB4LPENR (STM32_RCC_BASE + STM32_RCC_APB4LPENR_OFFSET) - -/* Register Bitfield Definitions ********************************************/ - -/* Source Control Register */ - -#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ -#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ -#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ -#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) -# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) -#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ - /* Bit 6: Reserved */ -#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ -#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ -#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ - /* Bits 10-11: Reserved */ -#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ -#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ -#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ -#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ -#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ -#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ -#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ - /* Bits 20-23: Reserved */ -#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ -#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ -#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ -#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ -#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ -#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ - /* Bits 30-31: Reserved */ - -/* Internal Clock Source Calibration Register */ - -/* HSICAL configuration */ - -#define RCC_ICSCR_HSICAL_SHIFT (0ul) -#define RCC_ICSCR_HSICAL_MASK (0xFFFul << RCC_ICSCR_HSICAL_SHIFT) -#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_MASK /* HSICAL[11:0] bits */ - -/* HSITRIM configuration */ - -#define RCC_ICSCR_HSITRIM_SHIFT (12ul) -#define RCC_ICSCR_HSITRIM_MASK (0x3Ful << RCC_ICSCR_HSITRIM_SHIFT) -#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_MASK /* HSITRIM[5:0] bits */ - -/* CSICAL configuration */ - -#define RCC_ICSCR_CSICAL_SHIFT (18ul) -#define RCC_ICSCR_CSICAL_MASK (0xFFul << RCC_ICSCR_CSICAL_SHIFT) -#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_MASK /* CSICAL[7:0] bits */ - -/* CSITRIM configuration */ - -#define RCC_ICSCR_CSITRIM_SHIFT (26ul) -#define RCC_ICSCR_CSITRIM_MASK (0x1Ful << RCC_ICSCR_CSITRIM_SHIFT) -#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_MASK /* CSITRIM[4:0] bits */ - -/* Clock Recovery RC Register */ - -/* HSI48CAL configuration */ - -#define RCC_CRRCR_HSI48CAL_SHIFT (0ul) -#define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) -#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ - -/* Clock Configuration Register (CFGR) */ - -#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-2: System clock Switch */ -#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) -# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ -# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ -# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ -# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ -#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ -#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) -# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ -# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ -# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ -# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ -#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ -#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ -#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ -#define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) -# define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) -#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ -#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ -#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ -#define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) -# define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) -#define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ -#define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) -# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ -# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ -# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ -# define RCC_CFGR_MCO1_PLL1Q (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ -# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ -#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) -# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) -#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ -#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO2_SHIFT) -# define RCC_CFGR_MCO2_SYS (0 << RCC_CFGR_MCO2_SHIFT) /* 000: HSI clock selected */ -# define RCC_CFGR_MCO2_PLL2P (1 << RCC_CFGR_MCO2_SHIFT) /* 001: PLL2 peripheral clock selected */ -# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO2_SHIFT) /* 010: HSE oscillator clock selected */ -# define RCC_CFGR_MCO2_PLL1P (3 << RCC_CFGR_MCO2_SHIFT) /* 011: PLL1 peripheral clock selected */ -# define RCC_CFGR_MCO2_CSI (4 << RCC_CFGR_MCO2_SHIFT) /* 100: CSI clock selected */ -# define RCC_CFGR_MCO2_LSI (5 << RCC_CFGR_MCO2_SHIFT) /* 101: LSI clock selected */ - -/* Bit definitions for RCC_D1CFGR */ - -#define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ -#define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) -# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) - -#define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ -#define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) -# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) - /* Bit 7: Reserved */ -#define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ -#define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) -# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) - /* Bits 12-31: Reserved */ - -/* Bit definitions for RCC_D2CFGR */ - - /* Bits 0-3: Reserved */ -#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ -#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) -# define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) - /* Bit 7: Reserved */ -#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ -#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) -# define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) - /* Bits 11-31: Reserved */ - -/* Bit definitions for RCC_D3CFGR */ - - /* Bits 0-3: Reserved */ -#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ -#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) -# define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) - /* Bits 7-31: Reserved */ - -/* Bit definitions for RCC_PLLCKSELR register */ - -#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ -#define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) -#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK - -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_HSE ((uint32_t)0x00000002) /* HSE source clock selected */ -#define RCC_PLLCKSELR_PLLSRC_NONE ((uint32_t)0x00000003) /* No source clock selected */ - -#define RCC_PLLCKSELR_DIVM1_SHIFT (4ul) -#define RCC_PLLCKSELR_DIVM1(x) ((x) << RCC_PLLCKSELR_DIVM1_SHIFT) /* Prescaler for PLL1: 1 - 63, 0 = disabled */ -#define RCC_PLLCKSELR_DIVM2_SHIFT (12ul) -#define RCC_PLLCKSELR_DIVM2(x) ((x) << RCC_PLLCKSELR_DIVM2_SHIFT) /* Prescaler for PLL2: 1 - 63, 0 = disabled */ -#define RCC_PLLCKSELR_DIVM3_SHIFT (20ul) -#define RCC_PLLCKSELR_DIVM3(x) ((x) << RCC_PLLCKSELR_DIVM3_SHIFT) /* Prescaler for PLL3: 1 - 63, 0 = disabled */ - -/* Bit definition for RCC_PLLCFGR register */ - -#define RCC_PLLCFGR_RESET ((uint32_t)0x01FF0000) - -#define RCC_PLLCFGR_PLL1FRACEN_SHIFT (0ul) -#define RCC_PLLCFGR_PLL1FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL1FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL1VCOSEL_SHIFT (1ul) -#define RCC_PLLCFGR_PLL1VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL1VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL1VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL1RGE_SHIFT (2ul) -#define RCC_PLLCFGR_PLL1RGE_MASK (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) -#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_MASK -#define RCC_PLLCFGR_PLL1RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL1RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL1RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL1RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL1RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_PLL2FRACEN_SHIFT (4ul) -#define RCC_PLLCFGR_PLL2FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL2FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL2VCOSEL_SHIFT (5ul) -#define RCC_PLLCFGR_PLL2VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL2VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL2VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_SHIFT (6ul) -#define RCC_PLLCFGR_PLL2RGE_MASK (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) -#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_MASK -#define RCC_PLLCFGR_PLL2RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL2RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL2RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL2RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL2RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_PLL3FRACEN_SHIFT (8ul) -#define RCC_PLLCFGR_PLL3FRACEN_MASK (0x1ul << RCC_PLLCFGR_PLL3FRACEN_SHIFT) -#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_MASK /* Fractional latch enable */ -#define RCC_PLLCFGR_PLL3VCOSEL_SHIFT (9ul) -#define RCC_PLLCFGR_PLL3VCOSEL_MASK (0x1ul << RCC_PLLCFGR_PLL3VCOSEL_SHIFT) -#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_MASK /* VCO freq range: 1 = Medium VCO range: 150 to 420 MHz, 0 = Wide VCO range: 192 to 836 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_WIDE (0ul) /* VCO freq range: Wide VCO range: 192 to 836 MHz, input clock >= 2 MHz */ -#define RCC_PLLCFGR_PLL3VCOSEL_MEDIUM RCC_PLLCFGR_PLL3VCOSEL /* VCO freq range: Medium VCO range: 150 to 420 MHz, input clock <= 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_SHIFT (10ul) -#define RCC_PLLCFGR_PLL3RGE_MASK (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) -#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_MASK -#define RCC_PLLCFGR_PLL3RGE_1_2_MHZ (0x0ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 1 and 2 MHz */ -#define RCC_PLLCFGR_PLL3RGE_2_4_MHZ (0x1ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 2 and 4 MHz */ -#define RCC_PLLCFGR_PLL3RGE_4_8_MHZ (0x2ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 4 and 8 MHz */ -#define RCC_PLLCFGR_PLL3RGE_8_16_MHZ (0x3ul << RCC_PLLCFGR_PLL3RGE_SHIFT) /* The PLL input clock range frequency is between 8 and 16 MHz */ - -#define RCC_PLLCFGR_DIVP1EN_SHIFT (16ul) -#define RCC_PLLCFGR_DIVP1EN_MASK (0x1ul << RCC_PLLCFGR_DIVP1EN_SHIFT) -#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_MASK -#define RCC_PLLCFGR_DIVQ1EN_SHIFT (17ul) -#define RCC_PLLCFGR_DIVQ1EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ1EN_SHIFT) -#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_MASK -#define RCC_PLLCFGR_DIVR1EN_SHIFT (18ul) -#define RCC_PLLCFGR_DIVR1EN_MASK (0x1ul << RCC_PLLCFGR_DIVR1EN_SHIFT) -#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_MASK - -#define RCC_PLLCFGR_DIVP2EN_SHIFT (19ul) -#define RCC_PLLCFGR_DIVP2EN_MASK (0x1ul << RCC_PLLCFGR_DIVP2EN_SHIFT) -#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_MASK -#define RCC_PLLCFGR_DIVQ2EN_SHIFT (20ul) -#define RCC_PLLCFGR_DIVQ2EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ2EN_SHIFT) -#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_MASK -#define RCC_PLLCFGR_DIVR2EN_SHIFT (21ul) -#define RCC_PLLCFGR_DIVR2EN_MASK (0x1ul << RCC_PLLCFGR_DIVR2EN_SHIFT) -#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_MASK - -#define RCC_PLLCFGR_DIVP3EN_SHIFT (22ul) -#define RCC_PLLCFGR_DIVP3EN_MASK (0x1ul << RCC_PLLCFGR_DIVP3EN_SHIFT) -#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_MASK -#define RCC_PLLCFGR_DIVQ3EN_SHIFT (23ul) -#define RCC_PLLCFGR_DIVQ3EN_MASK (0x1ul << RCC_PLLCFGR_DIVQ3EN_SHIFT) -#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_MASK -#define RCC_PLLCFGR_DIVR3EN_SHIFT (24ul) -#define RCC_PLLCFGR_DIVR3EN_MASK (0x1ul << RCC_PLLCFGR_DIVR3EN_SHIFT) -#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_MASK - -/* Bit definitions for RCC_PLL1DIVR register */ - -#define RCC_PLL1DIVR_N1_SHIFT (0ul) -#define RCC_PLL1DIVR_N1(x) (((x) - 1) << RCC_PLL1DIVR_N1_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL1DIVR_P1_SHIFT (9ul) -#define RCC_PLL1DIVR_P1(x) (((x) - 1) << RCC_PLL1DIVR_P1_SHIFT) /* DIVP division factor: 2 - 128, must be even */ -#define RCC_PLL1DIVR_Q1_SHIFT (16ul) -#define RCC_PLL1DIVR_Q1(x) (((x) - 1) << RCC_PLL1DIVR_Q1_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL1DIVR_R1_SHIFT (24ul) -#define RCC_PLL1DIVR_R1(x) (((x) - 1) << RCC_PLL1DIVR_R1_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL1FRACR register */ - -#define RCC_PLL1FRACR_FRACN1_SHIFT (3ul) -#define RCC_PLL1FRACR_FRACN1_MASK (0x1FFFul << RCC_PLL1FRACR_FRACN1_SHIFT) -#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_MASK - -/* Bit definitions for RCC_PLL2DIVR register */ - -#define RCC_PLL2DIVR_N2_SHIFT (0ul) -#define RCC_PLL2DIVR_N2(x) (((x) - 1) << RCC_PLL2DIVR_N2_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL2DIVR_P2_SHIFT (9ul) -#define RCC_PLL2DIVR_P2(x) (((x) - 1) << RCC_PLL2DIVR_P2_SHIFT) /* DIVP division factor: 2 - 128 */ -#define RCC_PLL2DIVR_Q2_SHIFT (16ul) -#define RCC_PLL2DIVR_Q2(x) (((x) - 1) << RCC_PLL2DIVR_Q2_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL2DIVR_R2_SHIFT (24ul) -#define RCC_PLL2DIVR_R2(x) (((x) - 1) << RCC_PLL2DIVR_R2_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL2FRACR register */ - -#define RCC_PLL2FRACR_FRACN2_SHIFT (3ul) -#define RCC_PLL2FRACR_FRACN2_MASK (0x1FFFul << RCC_PLL2FRACR_FRACN2_SHIFT) -#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_MASK - -/* Bit definitions for RCC_PLL3DIVR register */ - -#define RCC_PLL3DIVR_N3_SHIFT (0ul) -#define RCC_PLL3DIVR_N3(x) (((x) - 1) << RCC_PLL3DIVR_N3_SHIFT) /* Multiplication factor for VCO: 4 - 512 */ -#define RCC_PLL3DIVR_P3_SHIFT (9ul) -#define RCC_PLL3DIVR_P3(x) (((x) - 1) << RCC_PLL3DIVR_P3_SHIFT) /* DIVP division factor: 2 - 128 */ -#define RCC_PLL3DIVR_Q3_SHIFT (16ul) -#define RCC_PLL3DIVR_Q3(x) (((x) - 1) << RCC_PLL3DIVR_Q3_SHIFT) /* DIVQ division factor: 2 - 128 */ -#define RCC_PLL3DIVR_R3_SHIFT (24ul) -#define RCC_PLL3DIVR_R3(x) (((x) - 1) << RCC_PLL3DIVR_R3_SHIFT) /* DIVR division factor: 2 - 128 */ - -/* Bit definitions for RCC_PLL3FRACR register */ - -#define RCC_PLL3FRACR_FRACN3_SHIFT (3ul) -#define RCC_PLL3FRACR_FRACN3_MASK (0x1FFFul << RCC_PLL3FRACR_FRACN3_SHIFT) -#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_MASK - -/* Bit definitions for RCC_D1CCIPR register */ - -#define RCC_D1CCIPR_FMCSEL_SHIFT (0) /* Bits 0-1: */ -#define RCC_D1CCIPR_FMCSEL_MASK (3 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_HCLK (0 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PLL1 (1 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PLL2 (2 << RCC_D1CCIPR_FMCSEL_SHIFT) -# define RCC_D1CCIPR_FMCSEL_PER (3 << RCC_D1CCIPR_FMCSEL_SHIFT) - /* Bits 2-3: Reserved */ -#define RCC_D1CCIPR_QSPISEL_SHIFT (4) /* Bits 4-5: */ -#define RCC_D1CCIPR_QSPISEL_MASK (3 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_HCLK (0 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PLL1 (1 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PLL2 (2 << RCC_D1CCIPR_QSPISEL_SHIFT) -# define RCC_D1CCIPR_QSPISEL_PER (3 << RCC_D1CCIPR_QSPISEL_SHIFT) - /* Bits 6-15: Reserved */ -#define RCC_D1CCIPR_SDMMC_SHIFT (16) /* Bit 16: */ -#define RCC_D1CCIPR_SDMMC_MASK (1 << RCC_D1CCIPR_SDMMC_SHIFT) -# define RCC_D1CCIPR_SDMMC_PLL1 (0 << RCC_D1CCIPR_SDMMC_SHIFT) -# define RCC_D1CCIPR_SDMMC_PLL2 (1 << RCC_D1CCIPR_SDMMC_SHIFT) - /* Bits 17-27: Reserved */ -#define RCC_D1CCIPR_CKPERSEL_SHIFT (28) /* Bits 28-29: */ -#define RCC_D1CCIPR_CKPERSEL_MASK (3 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_HSI (0 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_CSI (1 << RCC_D1CCIPR_CKPERSEL_SHIFT) -# define RCC_D1CCIPR_CKPERSEL_HSE (2 << RCC_D1CCIPR_CKPERSEL_SHIFT) - /* Bits 30-31: Reserved */ - -/* Bit definitions for RCC_D2CCIP1R register */ - -#define RCC_D2CCIP1R_SAI1SEL_SHIFT (0) /* Bits 0-2 */ -#define RCC_D2CCIP1R_SAI1SEL_MASK (7 << RCC_D2CCIP1R_SAI1SEL_MASK) -# define RCC_D2CCIP1R_SAI1SEL_PLL1 (0 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PLL2 (1 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PLL3 (2 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI1SEL_SHIFT) -# define RCC_D2CCIP1R_SAI1SEL_PER (4 << RCC_D2CCIP1R_SAI1SEL_SHIFT) - /* Bits 3-5: Reserved */ -#define RCC_D2CCIP1R_SAI23SEL_SHIFT (6) /* Bits 6-8 */ -#define RCC_D2CCIP1R_SAI23SEL_MASK (7 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL1 (0 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL2 (1 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PLL3 (2 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_I2SCKIN (3 << RCC_D2CCIP1R_SAI23SEL_SHIFT) -# define RCC_D2CCIP1R_SAI23SEL_PER (4 << RCC_D2CCIP1R_SAI23SEL_SHIFT) - /* Bits 9-11: Reserved */ -#define RCC_D2CCIP1R_SPI123SEL_SHIFT (12) /* Bits 12-14 */ -#define RCC_D2CCIP1R_SPI123SEL_MASK (7 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL1 (0 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL2 (1 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PLL3 (2 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_I2SCKIN (3 << RCC_D2CCIP1R_SPI123SEL_SHIFT) -# define RCC_D2CCIP1R_SPI123SEL_PER (4 << RCC_D2CCIP1R_SPI123SEL_SHIFT) - /* Bit 15: Reserved */ -#define RCC_D2CCIP1R_SPI45SEL_SHIFT (16) /* Bits 16-18 */ -#define RCC_D2CCIP1R_SPI45SEL_MASK (7 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_APB (0 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_PLL2 (1 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_PLL3 (2 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_HSI (3 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_CSI (4 << RCC_D2CCIP1R_SPI45SEL_SHIFT) -# define RCC_D2CCIP1R_SPI45SEL_HSE (5 << RCC_D2CCIP1R_SPI45SEL_SHIFT) - /* Bit 19: Reserved */ -#define RCC_D2CCIP1R_SPDIFSEL_SHIFT (20) /* Bits 20-21 */ -#define RCC_D2CCIP1R_SPDIFSEL_MASK (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL1 (0 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL2 (1 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_PLL3 (2 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) -# define RCC_D2CCIP1R_SPDIFSEL_HSI (3 << RCC_D2CCIP1R_SPDIFSEL_SHIFT) - /* Bits 22-23: Reserved */ -#define RCC_D2CCIP1R_DFSDM1SEL_SHIFT (24) /* Bit 24 */ -#define RCC_D2CCIP1R_DFSDM1SEL_MASK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) -# define RCC_D2CCIP1R_DFSDM1SEL_PCLK2 (0 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) -# define RCC_D2CCIP1R_DFSDM1SEL_SYSCLK (1 << RCC_D2CCIP1R_DFSDM1SEL_SHIFT) - /* Bits 25-27: Reserved */ -#define RCC_D2CCIP1R_FDCANSEL_SHIFT (28) /* Bits 28-29 */ -#define RCC_D2CCIP1R_FDCANSEL_MASK (3 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_HSE (0 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_PLL1 (1 << RCC_D2CCIP1R_FDCANSEL_SHIFT) -# define RCC_D2CCIP1R_FDCANSEL_PLL2 (2 << RCC_D2CCIP1R_FDCANSEL_SHIFT) - /* Bit 30: Reserved */ -#define RCC_D2CCIP1R_SWPSEL_SHIFT (31) /* Bit 31 */ -#define RCC_D2CCIP1R_SWPSEL_MASK (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) -# define RCC_D2CCIP1R_SWPSEL_PCLK (0 << RCC_D2CCIP1R_SWPSEL_SHIFT) -# define RCC_D2CCIP1R_SWPSEL_HSI (1 << RCC_D2CCIP1R_SWPSEL_SHIFT) - -/* Bit definitions for RCC_D2CCIP2R register */ - -#define RCC_D2CCIP2R_USART234578SEL_SHIFT (0) /* Bits 0-2 */ -# define RCC_D2CCIP2R_USART234578SEL_MASK (7 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_RCC (0 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_PLL2 (1 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_PLL3 (2 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_HSI (3 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_CSI (4 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -# define RCC_D2CCIP2R_USART234578SEL_LSE (5 << RCC_D2CCIP2R_USART234578SEL_SHIFT) -#define RCC_D2CCIP2R_USART16SEL_SHIFT (3) /* Bits 3-5 */ -# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_MASK (7 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_RCC (0 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_PLL2 (1 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_PLL3 (2 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_HSI (3 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_CSI (4 << RCC_D2CCIP2R_USART16SEL_SHIFT) -# define RCC_D2CCIP2R_USART16SEL_LSE (5 << RCC_D2CCIP2R_USART16SEL_SHIFT) - /* Bits 6-7: Reserved */ -#define RCC_D2CCIP2R_RNGSEL_SHIFT (8) /* Bits 8-9 */ -# define RCC_D2CCIP2R_RNGSEL_MASK (3 << RCC_D2CCIP2R_RNGSEL_SHIFT) - /* Bits 10-11: Reserved */ -#define RCC_D2CCIP2R_I2C123SEL_SHIFT (12) /* Bits 12-13 */ -#define RCC_D2CCIP2R_I2C123SEL_MASK (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_PCLK1 (0 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_PLL3 (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_HSI (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) -# define RCC_D2CCIP2R_I2C123SEL_CSI (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) - /* Bits 14-19: Reserved */ -#define RCC_D2CCIP2R_USBSEL_SHIFT (20) /* Bits 20-21 */ -# define RCC_D2CCIP2R_USBSEL_MASK (3 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_DISABLE (0 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_PLL1 (1 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_PLL3 (2 << RCC_D2CCIP2R_USBSEL_SHIFT) -# define RCC_D2CCIP2R_USBSEL_HSI48 (3 << RCC_D2CCIP2R_USBSEL_SHIFT) -#define RCC_D2CCIP2R_CECSEL_SHIFT (22) /* Bits 22-23 */ -# define RCC_D2CCIP2R_CECSEL_MASK (3 << RCC_D2CCIP2R_CECSEL_SHIFT) - /* Bits 24-27: Reserved */ -#define RCC_D2CCIP2R_LPTIM1SEL_SHIFT (28) /* Bits 28-30 */ -# define RCC_D2CCIP2R_LPTIM1SEL_MASK (3 << RCC_D2CCIP2R_LPTIM1SEL_SHIFT) - /* Bit 31: Reserved */ - -/* Bit definitions for RCC_D3CCIPR register */ - -#define RCC_D3CCIPR_LPUART1SEL_SHIFT (0) /* Bits 0-2: LPUART1 kernel clock source selection */ -#define RCC_D3CCIPR_LPUART1SEL_MASK (7 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PCLK (0 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PLL2 (1 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_PLL3 (2 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_HSI (3 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_CSI (4 << RCC_D3CCIPR_LPUART1SEL_SHIFT) -# define RCC_D3CCIPR_LPUART1SEL_LSE (5 << RCC_D3CCIPR_LPUART1SEL_SHIFT) - /* Bits 3-7: Reserved */ -#define RCC_D3CCIPR_I2C4SEL_SHIFT (8) /* Bits 8-9: I2C4 kernel clock source selection */ -#define RCC_D3CCIPR_I2C4SEL_MASK (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PCLK4 (0 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_PLL3 (1 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_HSI (2 << RCC_D3CCIPR_I2C4SEL_SHIFT) -# define RCC_D3CCIPR_I2C4SEL_CSI (3 << RCC_D3CCIPR_I2C4SEL_SHIFT) -#define RCC_D3CCIPR_LPTIM2SEL_SHIFT (10) /* Bits 10-12: LPTIM2 kernel clock source selection */ -#define RCC_D3CCIPR_LPTIM2SEL_MASK (7 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_LSE (3 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_LSI (4 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM2SEL_PER (5 << RCC_D3CCIPR_LPTIM2SEL_SHIFT) -#define RCC_D3CCIPR_LPTIM345SEL_SHIFT (13) /* Bits 13-15: LPTIM3,4,5 kernel clock source selection */ -#define RCC_D3CCIPR_LPTIM345SEL_MASK (7 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PCLK4 (0 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PLL2 (1 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PLL3 (2 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_LSE (3 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_LSI (4 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -# define RCC_D3CCIPR_LPTIM345SEL_PER (5 << RCC_D3CCIPR_LPTIM345SEL_SHIFT) -#define RCC_D3CCIPR_ADCSEL_SHIFT (16) /* Bits 16-17: SAR ADC kernel clock source selection */ -#define RCC_D3CCIPR_ADCSEL_MASK (3 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PLL2 (0 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PLL3 (1 << RCC_D3CCIPR_ADCSEL_SHIFT) -# define RCC_D3CCIPR_ADCSEL_PER (2 << RCC_D3CCIPR_ADCSEL_SHIFT) - /* Bits 18-20: Reserved */ -#define RCC_D3CCIPR_SAI4ASEL_SHIFT (21) /* Bits 21-23: Sub-Block A of SAI4 kernel clock source selection */ -#define RCC_D3CCIPR_SAI4ASEL_MASK (7 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL1 (0 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL2 (1 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PLL3 (2 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -# define RCC_D3CCIPR_SAI4ASEL_PER (4 << RCC_D3CCIPR_SAI4ASEL_SHIFT) -#define RCC_D3CCIPR_SAI4BSEL_SHIFT (24) /* Bits 24-26: Sub-Block B of SAI4 kernel clock source selection */ -#define RCC_D3CCIPR_SAI4BSEL_MASK (7 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL1 (0 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL2 (1 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PLL3 (2 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_I2CCKIN (3 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -# define RCC_D3CCIPR_SAI4BSEL_PER (4 << RCC_D3CCIPR_SAI4BSEL_SHIFT) -#define RCC_D3CCIPR_SPI6SEL_SHIFT (28) /* Bits 28-30: SPI6 kernel clock source selection */ -#define RCC_D3CCIPR_SPI6SEL_MASK (7 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PCLK4 (0 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PLL2 (1 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_PLL3 (2 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_HSI (3 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_CSI (4 << RCC_D3CCIPR_SPI6SEL_SHIFT) -# define RCC_D3CCIPR_SPI6SEL_HSE (5 << RCC_D3CCIPR_SPI6SEL_SHIFT) - /* Bit 31: Reserved */ - -/* TODO: CIER */ - -/* TODO: CIFR */ - -/* TODO: CICR */ - -/* TODO: BDCR */ - -/* Bit definitions for RCC_CSR register */ - -#define RCC_CSR_LSION (1 << 0) /* RCC CSR: LSION */ -#define RCC_CSR_LSIRDY (1 << 1) /* RCC CSR: LSIRDY */ - -/* AHB3 peripheral reset register */ - -#define RCC_AHB3RSTR_MDMARST (1 << 0) /* RCC AHB3RSTR: MDMARST */ -#define RCC_AHB3RSTR_DMA2DRST (1 << 4) /* RCC AHB3RSTR: DMA2DRST */ -#define RCC_AHB3RSTR_JPGDECRST (1 << 5) /* RCC AHB3RSTR: JPGDECRST */ -#define RCC_AHB3RSTR_FMCRST (1 << 12) /* RCC AHB3RSTR: FMCRST */ -#define RCC_AHB3RSTR_QSPIRST (1 << 14) /* RCC AHB3RSTR: QSPIRST */ -#define RCC_AHB3RSTR_SDMMC1RST (1 << 16) /* RCC AHB3RSTR: SDMMC1RST */ -#define RCC_AHB3RSTR_CPURST (1 << 31) /* RCC AHB3RSTR: CPURST */ - -/* AHB1 peripheral reset register */ - -#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* RCC AHB1RSTR: DMA1RST */ -#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* RCC AHB1RSTR: DMA2RST */ -#define RCC_AHB1RSTR_ADC12RST (1 << 5) /* RCC AHB1RSTR: ADC12RST */ - /* Bits 6-14: Reserved */ -#define RCC_AHB1RSTR_ETH1MACRST (1 << 15) /* RCC AHB1RSTR: ETH1MACRST */ - /* Bits 16-24: Reserved */ -#define RCC_AHB1RSTR_OTGHSRST (1 << 25) /* RCC AHB1RSTR: OTGHSRST */ - /* Bit 26: Reserved */ -#define RCC_AHB1RSTR_OTGFSRST (1 << 27) /* RCC AHB1RSTR: OTGFSRST */ - /* Bits 28-31: Reserved */ - -/* AHB2 peripheral reset register */ - -#define RCC_AHB2RSTR_CAMITFRST (1 << 0) /* RCC AHB2RSTR: CAMITFRST */ - /* Bits 1-3: Reserved */ -#define RCC_AHB2RSTR_CRYPTRST (1 << 4) /* RCC AHB2RSTR: CRYPTRST */ -#define RCC_AHB2RSTR_HASHRST (1 << 5) /* RCC AHB2RSTR: HASHRST */ -#define RCC_AHB2RSTR_RNGRST (1 << 6) /* RCC AHB2RSTR: RNGRST */ - /* Bits 7-8: Reserved */ -#define RCC_AHB2RSTR_SDMMC2RST (1 << 9) /* RCC AHB2RSTR: SDMMC2RST */ - /* Bits 10-31: Reserved */ - -/* AHB4 peripheral reset register */ - -#define RCC_AHB4RSTR_GPIOARST (1 << 0) /* RCC AHB4RSTR: GPIOARST */ -#define RCC_AHB4RSTR_GPIOBRST (1 << 1) /* RCC AHB4RSTR: GPIOBRST */ -#define RCC_AHB4RSTR_GPIOCRST (1 << 2) /* RCC AHB4RSTR: GPIOCRST */ -#define RCC_AHB4RSTR_GPIODRST (1 << 3) /* RCC AHB4RSTR: GPIODRST */ -#define RCC_AHB4RSTR_GPIOERST (1 << 4) /* RCC AHB4RSTR: GPIOERST */ -#define RCC_AHB4RSTR_GPIOFRST (1 << 5) /* RCC AHB4RSTR: GPIOFRST */ -#define RCC_AHB4RSTR_GPIOGRST (1 << 6) /* RCC AHB4RSTR: GPIOGRST */ -#define RCC_AHB4RSTR_GPIOHRST (1 << 7) /* RCC AHB4RSTR: GPIOHRST */ -#define RCC_AHB4RSTR_GPIOIRST (1 << 8) /* RCC AHB4RSTR: GPIOIRST */ -#define RCC_AHB4RSTR_GPIOJRST (1 << 9) /* RCC AHB4RSTR: GPIOJRST */ -#define RCC_AHB4RSTR_GPIOKRST (1 << 10) /* RCC AHB4RSTR: GPIOKRST */ - /* Bits 11-18: Reserved */ -#define RCC_AHB4RSTR_CRCRST (1 << 19) /* RCC AHB4RSTR: CRCRST */ - /* Bit 20: Reserved */ -#define RCC_AHB4RSTR_BDMARST (1 << 21) /* RCC AHB4RSTR: BDMARST */ - /* Bits 22-23: Reserved */ -#define RCC_AHB4RSTR_ADC3RST (1 << 24) /* RCC AHB4RSTR: ADC3RST */ -#define RCC_AHB4RSTR_HSEMRST (1 << 25) /* RCC AHB4RSTR: HSEMRST */ - /* Bits 26-31: Reserved */ - -/* APB3 peripheral reset register */ - - /* Bits 0-2: Reserved */ -#define RCC_APB3RSTR_LTDCRST (1 << 3) /* RCC APB3RSTR: LTDCRST */ - /* Bits 4-31: Reserved */ - -/* APB3 L peripheral reset register */ - -#define RCC_APB1LRSTR_TIM2RST (1 << 0) /* RCC APB1LRSTR: TIM2RST */ -#define RCC_APB1LRSTR_TIM3RST (1 << 1) /* RCC APB1LRSTR: TIM3RST */ -#define RCC_APB1LRSTR_TIM4RST (1 << 2) /* RCC APB1LRSTR: TIM4RST */ -#define RCC_APB1LRSTR_TIM5RST (1 << 3) /* RCC APB1LRSTR: TIM5RST */ -#define RCC_APB1LRSTR_TIM6RST (1 << 4) /* RCC APB1LRSTR: TIM6RST */ -#define RCC_APB1LRSTR_TIM7RST (1 << 5) /* RCC APB1LRSTR: TIM7RST */ -#define RCC_APB1LRSTR_TIM12RST (1 << 6) /* RCC APB1LRSTR: TIM12RST */ -#define RCC_APB1LRSTR_TIM13RST (1 << 7) /* RCC APB1LRSTR: TIM13RST */ -#define RCC_APB1LRSTR_TIM14RST (1 << 8) /* RCC APB1LRSTR: TIM14RST */ -#define RCC_APB1LRSTR_LPTIM1RST (1 << 9) /* RCC APB1LRSTR: LPTIM1RST */ - /* Bits 10-13: Reserved */ -#define RCC_APB1LRSTR_SPI2RST (1 << 14) /* RCC APB1LRSTR: SPI2RST */ -#define RCC_APB1LRSTR_SPI3RST (1 << 15) /* RCC APB1LRSTR: SPI3RST */ -#define RCC_APB1LRSTR_SPDIFRXRST (1 << 16) /* RCC APB1LRSTR: SPDIFRXRST */ -#define RCC_APB1LRSTR_USART2RST (1 << 17) /* RCC APB1LRSTR: USART2RST */ -#define RCC_APB1LRSTR_USART3RST (1 << 18) /* RCC APB1LRSTR: USART3RST */ -#define RCC_APB1LRSTR_UART4RST (1 << 19) /* RCC APB1LRSTR: UART4RST */ -#define RCC_APB1LRSTR_UART5RST (1 << 20) /* RCC APB1LRSTR: UART5RST */ -#define RCC_APB1LRSTR_I2C1RST (1 << 21) /* RCC APB1LRSTR: I2C1RST */ -#define RCC_APB1LRSTR_I2C2RST (1 << 22) /* RCC APB1LRSTR: I2C2RST */ -#define RCC_APB1LRSTR_I2C3RST (1 << 23) /* RCC APB1LRSTR: I2C3RST */ - /* Bits 24-26: Reserved */ -#define RCC_APB1LRSTR_HDMICECRST (1 << 27) /* RCC APB1LRSTR: HDMICECRST */ - /* Bit 28: Reserved */ -#define RCC_APB1LRSTR_DAC1RST (1 << 29) /* RCC APB1LRSTR: DAC1RST */ -#define RCC_APB1LRSTR_UART7RST (1 << 30) /* RCC APB1LRSTR: UART7RST */ -#define RCC_APB1LRSTR_UART8RST (1 << 31) /* RCC APB1LRSTR: UART8RST */ - -/* APB1 H peripheral reset register */ - - /* Bit 0: Reserved */ -#define RCC_APB1HRSTR_CRSRST (1 << 1) /* RCC APB1HRSTR: CRSRST */ -#define RCC_APB1HRSTR_SWPRST (1 << 2) /* RCC APB1HRSTR: SWPRST */ - -/* Bit 3: Reserved */ - -#define RCC_APB1HRSTR_OPAMPRST (1 << 4) /* RCC APB1HRSTR: OPAMPRST*/ -#define RCC_APB1HRSTR_MDIOSRST (1 << 5) /* RCC APB1HRSTR: MDIOSRST */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HRSTR_FDCANRST (1 << 8) /* RCC APB1HRSTR: FDCANRST*/ - -/* Bits 9-31: Reserved */ - -/* APB2 peripheral reset register */ - -#define RCC_APB2RSTR_TIM1RST (1 << 0) /* RCC APB2RSTR: TIM1RST */ -#define RCC_APB2RSTR_TIM8RST (1 << 1) /* RCC APB2RSTR: TIM8RST */ -#define RCC_APB2RSTR_USART1RST (1 << 4) /* RCC APB2RSTR: USART1RST */ -#define RCC_APB2RSTR_USART6RST (1 << 5) /* RCC APB2RSTR: USART6RST */ -#define RCC_APB2RSTR_SPI1RST (1 << 12) /* RCC APB2RSTR: SPI1RST */ -#define RCC_APB2RSTR_SPI4RST (1 << 13) /* RCC APB2RSTR: SPI4RST */ -#define RCC_APB2RSTR_TIM15RST (1 << 16) /* RCC APB2RSTR: TIM15RST */ -#define RCC_APB2RSTR_TIM16RST (1 << 17) /* RCC APB2RSTR: TIM16RST */ -#define RCC_APB2RSTR_TIM17RST (1 << 18) /* RCC APB2RSTR: TIM17RST */ -#define RCC_APB2RSTR_SPI5RST (1 << 20) /* RCC APB2RSTR: SPI5RST */ -#define RCC_APB2RSTR_SAI1RST (1 << 22) /* RCC APB2RSTR: SAI1RST */ -#define RCC_APB2RSTR_SAI2RST (1 << 23) /* RCC APB2RSTR: SAI2RST */ -#define RCC_APB2RSTR_SAI3RST (1 << 24) /* RCC APB2RSTR: SAI3RST */ -#define RCC_APB2RSTR_DFSDM1RST (1 << 28) /* RCC APB2RSTR: DFSDM1RST */ -#define RCC_APB2RSTR_HRTIMRST (1 << 29) /* RCC APB2RSTR: HRTIMRST */ - -/* APB4 peripheral reset register */ - -#define RCC_APB4RSTR_SYSCFGRST (1 << 1) /* RCC APB4RSTR: SYSCFGRST */ -#define RCC_APB4RSTR_LPUART1RST (1 << 3) /* RCC APB4RSTR: LPUART1RST */ -#define RCC_APB4RSTR_SPI6RST (1 << 5) /* RCC APB4RSTR: SPI6RST */ -#define RCC_APB4RSTR_I2C4RST (1 << 7) /* RCC APB4RSTR: I2C4RST */ -#define RCC_APB4RSTR_LPTIM2RST (1 << 9) /* RCC APB4RSTR: LPTIM2RST */ -#define RCC_APB4RSTR_LPTIM3RST (1 << 10) /* RCC APB4RSTR: LPTIM3RST */ -#define RCC_APB4RSTR_LPTIM4RST (1 << 11) /* RCC APB4RSTR: LPTIM4RST */ -#define RCC_APB4RSTR_LPTIM5RST (1 << 12) /* RCC APB4RSTR: LPTIM5RST */ -#define RCC_APB4RSTR_COMP12RST (1 << 14) /* RCC APB4RSTR: COMP12RST */ -#define RCC_APB4RSTR_VREFRST (1 << 15) /* RCC APB4RSTR: VREFRST */ -#define RCC_APB4RSTR_SAI4RST (1 << 21) /* RCC APB4RSTR: SAI4RST */ - -/* RCC Global Control register */ - -#define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32_HAVE_CM4 -# define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ -#endif -#ifdef CONFIG_STM32_HAVE_CM4 -# define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ -# define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ -#endif - -/* TODO: D3 Autonomous mode register */ - -/* RCC Reset Status register */ - - /* Bits 0-15: Reserved */ -#define RCC_RSR_RMVF (1 << 16) /* Bit 16: Remove reset flag */ -#define RCC_RSR_CPURSTF (1 << 17) /* Bit 17: CPU reset flag */ - /* Bit 18: Reserved */ -#define RCC_RSR_D1RSTF (1 << 19) /* Bit 19: D1 domain power switch reset flag */ -#define RCC_RSR_D2RSTF (1 << 20) /* Bit 20: D2 domain power switch reset flag */ -#define RCC_RSR_BORRSTF (1 << 21) /* Bit 21: BOR reset flag */ -#define RCC_RSR_PINRSTF (1 << 22) /* Bit 22: Pin reset flag */ -#define RCC_RSR_PORRSTF (1 << 23) /* Bit 23: POR/PDR reset flag */ -#define RCC_RSR_SFTRSTF (1 << 24) /* Bit 24: System reset from CPU flag */ - /* Bit 25: Reserved */ -#define RCC_RSR_IWDG1RSTF (1 << 26) /* Bit 26: Independent watchdog reset flag */ - /* Bit 27: Reserved */ -#define RCC_RSR_WWDG1RSTF (1 << 28) /* Bit 28: Window watchdog reset flag */ - /* Bit 29: Reserved */ -#define RCC_RSR_LPWRRSTF (1 << 30) /* Bit 30: Reset due to illegal D1 DStandby or CPU Cstop flag */ - /* Bit 31: Reserved */ - -/* AHB3 Peripheral Clock enable register */ - -#define RCC_AHB3ENR_MDMAEN (1 << 0) /* RCC AHB3ENR: MDMAEN */ -#define RCC_AHB3ENR_DMA2DEN (1 << 4) /* RCC AHB3ENR: DMA2DEN */ -#define RCC_AHB3ENR_JPGDECEN (1 << 5) /* RCC AHB3ENR: JPGDECEN */ -#define RCC_AHB3ENR_FMCEN (1 << 12) /* RCC AHB3ENR: FMCEN */ -#define RCC_AHB3ENR_QSPIEN (1 << 14) /* RCC AHB3ENR: QSPIEN */ -#define RCC_AHB3ENR_SDMMC1EN (1 << 16) /* RCC AHB3ENR: SDMMC1EN */ - -/* AHB1 Peripheral Clock enable register */ - -#define RCC_AHB1ENR_DMA1EN (1 << 0) /* RCC AHB1ENR: DMA1EN */ -#define RCC_AHB1ENR_DMA2EN (1 << 1) /* RCC AHB1ENR: DMA2EN */ -#define RCC_AHB1ENR_ADC12EN (1 << 5) /* RCC AHB1ENR: ADC12EN */ -#define RCC_AHB1ENR_ETH1MACEN (1 << 15) /* RCC AHB1ENR: ETH1MACEN */ -#define RCC_AHB1ENR_ETH1TXEN (1 << 16) /* RCC AHB1ENR: ETH1TXEN */ -#define RCC_AHB1ENR_ETH1RXEN (1 << 17) /* RCC AHB1ENR: ETH1RXEN */ -#define RCC_AHB1ENR_OTGHSEN (1 << 25) /* RCC AHB1ENR: OTGHSEN */ -#define RCC_AHB1ENR_OTGHSULPIEN (1 << 26) /* RCC AHB1ENR: OTGHSULPIEN */ -#define RCC_AHB1ENR_OTGFSEN (1 << 27) /* RCC AHB1ENR: OTGFSEN */ - -/* AHB2 Peripheral Clock enable register */ - -#define RCC_AHB2ENR_CAMITFEN (1 << 0) /* RCC AHB2ENR: CAMITFEN */ -#define RCC_AHB2ENR_CRYPTEN (1 << 4) /* RCC AHB2ENR: CRYPTEN */ -#define RCC_AHB2ENR_HASHEN (1 << 5) /* RCC AHB2ENR: HASHEN */ -#define RCC_AHB2ENR_RNGEN (1 << 6) /* RCC AHB2ENR: RNGEN */ -#define RCC_AHB2ENR_SDMMC2EN (1 << 9) /* RCC AHB2ENR: SDMMC2EN */ -#define RCC_AHB2ENR_SRAM1EN (1 << 29) /* RCC AHB2ENR: SRAM1EN */ -#define RCC_AHB2ENR_SRAM2EN (1 << 30) /* RCC AHB2ENR: SRAM2EN */ -#define RCC_AHB2ENR_SRAM3EN (1 << 31) /* RCC AHB2ENR: SRAM3EN */ - -/* AHB4 Peripheral Clock enable register */ - -#define RCC_AHB4ENR_GPIOAEN (1 << 0) /* RCC AHB4ENR: GPIOAEN */ -#define RCC_AHB4ENR_GPIOBEN (1 << 1) /* RCC AHB4ENR: GPIOBEN */ -#define RCC_AHB4ENR_GPIOCEN (1 << 2) /* RCC AHB4ENR: GPIOCEN */ -#define RCC_AHB4ENR_GPIODEN (1 << 3) /* RCC AHB4ENR: GPIODEN */ -#define RCC_AHB4ENR_GPIOEEN (1 << 4) /* RCC AHB4ENR: GPIOEEN */ -#define RCC_AHB4ENR_GPIOFEN (1 << 5) /* RCC AHB4ENR: GPIOFEN */ -#define RCC_AHB4ENR_GPIOGEN (1 << 6) /* RCC AHB4ENR: GPIOGEN */ -#define RCC_AHB4ENR_GPIOHEN (1 << 7) /* RCC AHB4ENR: GPIOHEN */ -#define RCC_AHB4ENR_GPIOIEN (1 << 8) /* RCC AHB4ENR: GPIOIEN */ -#define RCC_AHB4ENR_GPIOJEN (1 << 9) /* RCC AHB4ENR: GPIOJEN */ -#define RCC_AHB4ENR_GPIOKEN (1 << 10) /* RCC AHB4ENR: GPIOKEN */ -#define RCC_AHB4ENR_CRCEN (1 << 19) /* RCC AHB4ENR: CRCEN */ -#define RCC_AHB4ENR_BDMAEN (1 << 21) /* RCC AHB4ENR: BDMAEN and DMAMUX2 */ -#define RCC_AHB4ENR_ADC3EN (1 << 24) /* RCC AHB4ENR: ADC3EN */ -#define RCC_AHB4ENR_HSEMEN (1 << 25) /* RCC AHB4ENR: HSEMEN */ -#define RCC_AHB4ENR_BKPSRAMEN (1 << 28) /* RCC AHB4ENR: BKPRAMEN */ - -/* APB3 Peripheral Clock enable register */ - -#define RCC_APB3ENR_LTDCEN (1 << 3) /* RCC APB3ENR: LTDCEN */ -#define RCC_APB3ENR_WWDG1EN (1 << 6) /* RCC APB3ENR: WWDG1EN */ - -/* APB1 L Peripheral Clock enable register */ - -#define RCC_APB1LENR_TIM2EN (1 << 0) /* RCC APB1LENR: TIM2EN */ -#define RCC_APB1LENR_TIM3EN (1 << 1) /* RCC APB1LENR: TIM3EN */ -#define RCC_APB1LENR_TIM4EN (1 << 2) /* RCC APB1LENR: TIM4EN */ -#define RCC_APB1LENR_TIM5EN (1 << 3) /* RCC APB1LENR: TIM5EN */ -#define RCC_APB1LENR_TIM6EN (1 << 4) /* RCC APB1LENR: TIM6EN */ -#define RCC_APB1LENR_TIM7EN (1 << 5) /* RCC APB1LENR: TIM7EN */ -#define RCC_APB1LENR_TIM12EN (1 << 6) /* RCC APB1LENR: TIM12EN */ -#define RCC_APB1LENR_TIM13EN (1 << 7) /* RCC APB1LENR: TIM13EN */ -#define RCC_APB1LENR_TIM14EN (1 << 8) /* RCC APB1LENR: TIM14EN */ -#define RCC_APB1LENR_LPTIM1EN (1 << 9) /* RCC APB1LENR: LPTIM1EN */ - /* Bits 10-13: Reserved */ -#define RCC_APB1LENR_SPI2EN (1 << 14) /* RCC APB1LENR: SPI2EN */ -#define RCC_APB1LENR_SPI3EN (1 << 15) /* RCC APB1LENR: SPI3EN */ -#define RCC_APB1LENR_SPDIFRXEN (1 << 16) /* RCC APB1LENR: SPDIFRXEN */ -#define RCC_APB1LENR_USART2EN (1 << 17) /* RCC APB1LENR: USART2EN */ -#define RCC_APB1LENR_USART3EN (1 << 18) /* RCC APB1LENR: USART3EN */ -#define RCC_APB1LENR_UART4EN (1 << 19) /* RCC APB1LENR: UART4EN */ -#define RCC_APB1LENR_UART5EN (1 << 20) /* RCC APB1LENR: UART5EN */ -#define RCC_APB1LENR_I2C1EN (1 << 21) /* RCC APB1LENR: I2C1EN */ -#define RCC_APB1LENR_I2C2EN (1 << 22) /* RCC APB1LENR: I2C2EN */ -#define RCC_APB1LENR_I2C3EN (1 << 23) /* RCC APB1LENR: I2C3EN */ - /* Bits 24-25: Reserved */ -#define RCC_APB1LENR_HDMICECEN (1 << 27) /* RCC APB1LENR: HDMICECEN */ - /* Bit 28: Reserved */ -#define RCC_APB1LENR_DAC1EN (1 << 29) /* RCC APB1LENR: DAC1EN */ -#define RCC_APB1LENR_UART7EN (1 << 30) /* RCC APB1LENR: UART7EN */ -#define RCC_APB1LENR_UART8EN (1 << 31) /* RCC APB1LENR: UART8EN */ - -/* APB1 H Peripheral Clock enable register */ - - /* Bit 0: Reserved */ -#define RCC_APB1HENR_CRSEN (1 << 1) /* RCC APB1HENR: CRSEN */ -#define RCC_APB1HENR_SWPEN (1 << 2) /* RCC APB1HENR: SWPEN */ - /* Bit 3: Reserved */ -#define RCC_APB1HENR_OPAMPEN (1 << 4) /* RCC APB1HENR: OPAMPEN */ -#define RCC_APB1HENR_MDIOSEN (1 << 5) /* RCC APB1HENR: MDIOSEN */ - /* Bits 6-7: Reserved */ -#define RCC_APB1HENR_FDCANEN (1 << 8) /* RCC APB1HENR: FDCANEN */ - /* Bits 9-31: Reserved */ - -/* APB2 Peripheral Clock enable register */ - -#define RCC_APB2ENR_TIM1EN (1 << 0) /* Bit 0: RCC APB2ENR: TIM1EN */ -#define RCC_APB2ENR_TIM8EN (1 << 1) /* Bit 1: RCC APB2ENR: TIM8EN */ - /* Bits 2-3: Reserved */ -#define RCC_APB2ENR_USART1EN (1 << 4) /* Bit 4: RCC APB2ENR: USART1EN */ -#define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: RCC APB2ENR: USART6EN */ - /* Bits 6-11: Reserved */ -#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: RCC APB2ENR: SPI1EN */ -#define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: RCC APB2ENR: SPI4EN */ - /* Bits 14-15: Reserved */ -#define RCC_APB2ENR_TIM15EN (1 << 16) /* Bit 16: RCC APB2ENR: TIM15EN */ -#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: RCC APB2ENR: TIM16EN */ -#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: RCC APB2ENR: TIM17EN */ -#define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: RCC APB2ENR: SPI5EN */ - /* Bit 21: Reserved */ -#define RCC_APB2ENR_SAI1EN (1 << 22) /* Bit 22: RCC APB2ENR: SAI1EN */ -#define RCC_APB2ENR_SAI2EN (1 << 23) /* Bit 23: RCC APB2ENR: SAI2EN */ -#define RCC_APB2ENR_SAI3EN (1 << 24) /* Bit 24: RCC APB2ENR: SAI3EN */ - /* Bits 25-27: Reserved */ -#define RCC_APB2ENR_DFSDM1EN (1 << 28) /* Bit 28: RCC APB2ENR: DFSDM1EN */ -#define RCC_APB2ENR_HRTIMEN (1 << 29) /* Bit 29: RCC APB2ENR: HRTIMEN */ - /* Bits 30-31: Reserved */ - -/* APB4 Peripheral Clock enable register */ - - /* Bit 0: Reserved */ -#define RCC_APB4ENR_SYSCFGEN (1 << 1) /* Bit 1: RCC APB4ENR: SYSCFGEN */ - /* Bit 2: Reserved */ -#define RCC_APB4ENR_LPUART1EN (1 << 3) /* Bit 3: RCC APB4ENR: LPUART1EN */ - /* Bit 4: Reserved */ -#define RCC_APB4ENR_SPI6EN (1 << 5) /* Bit 5: RCC APB4ENR: SPI6EN */ - /* Bit 6: Reserved */ -#define RCC_APB4ENR_I2C4EN (1 << 7) /* Bit 7: RCC APB4ENR: I2C4EN */ - /* Bit 8: Reserved */ -#define RCC_APB4ENR_LPTIM2EN (1 << 9) /* Bit 9: RCC APB4ENR: LPTIM2EN */ -#define RCC_APB4ENR_LPTIM3EN (1 << 10) /* Bit 10: RCC APB4ENR: LPTIM3EN */ -#define RCC_APB4ENR_LPTIM4EN (1 << 11) /* Bit 11: RCC APB4ENR: LPTIM4EN */ -#define RCC_APB4ENR_LPTIM5EN (1 << 12) /* Bit 12: RCC APB4ENR: LPTIM5EN */ - /* Bit 13: Reserved */ -#define RCC_APB4ENR_COMP12EN (1 << 14) /* Bit 14: RCC APB4ENR: COMP12EN */ -#define RCC_APB4ENR_VREFEN (1 << 15) /* Bit 15: RCC APB4ENR: VREFEN */ -#define RCC_APB4ENR_RTCAPBEN (1 << 16) /* Bit 16: RCC APB4ENR: RTCAPBEN */ - /* Bits 17-20: Reserved */ -#define RCC_APB4ENR_SAI4EN (1 << 21) /* Bit 21: RCC APB4ENR: SAI4EN */ - /* Bit2 22-31: Reserved */ - -/* AHB3 low power mode peripheral clock enable register */ - -#define RCC_AHB3LPENR_MDMALPEN (1 << 0) /* RCC AHB3LPENR: MDMALPEN */ -#define RCC_AHB3LPENR_DMA2DLPEN (1 << 4) /* RCC AHB3LPENR: DMA2DLPEN */ -#define RCC_AHB3LPENR_JPGDECLPEN (1 << 5) /* RCC AHB3LPENR: JPGDECLPEN */ -#define RCC_AHB3LPENR_FLITFLPEN (1 << 8) /* RCC AHB3LPENR: FLITFLPEN */ -#define RCC_AHB3LPENR_FMCLPEN (1 << 12) /* RCC AHB3LPENR: FMCLPEN */ -#define RCC_AHB3LPENR_QSPILPEN (1 << 14) /* RCC AHB3LPENR: QSPILPEN */ -#define RCC_AHB3LPENR_SDMMC1LPEN (1 << 16) /* RCC AHB3LPENR: SDMMC1LPEN */ -#define RCC_AHB3LPENR_D1DTCM1LPEN (1 << 28) /* RCC AHB3LPENR: D1DTCM1LPEN */ -#define RCC_AHB3LPENR_DTCM2LPEN (1 << 29) /* RCC AHB3LPENR: DTCM2LPEN */ -#define RCC_AHB3LPENR_ITCMLPEN (1 << 30) /* RCC AHB3LPENR: ITCMLPEN */ -#define RCC_AHB3LPENR_AXISRAMLPEN (1 << 31) /* RCC AHB3LPENR: AXISRAMLPEN */ - -/* AHB1 low power mode peripheral clock enable register */ - -#define RCC_AHB1LPENR_DMA1LPEN (1 << 0) /* RCC AHB1LPENR: DMA1LPEN */ -#define RCC_AHB1LPENR_DMA2LPEN (1 << 1) /* RCC AHB1LPENR: DMA2LPEN */ -#define RCC_AHB1LPENR_ADC12LPEN (1 << 5) /* RCC AHB1LPENR: ADC12LPEN */ -#define RCC_AHB1LPENR_ETH1MACLPEN (1 << 15) /* RCC AHB1LPENR: ETH1MACLPEN */ -#define RCC_AHB1LPENR_ETH1TXLPEN (1 << 16) /* RCC AHB1LPENR: ETH1TXLPEN */ -#define RCC_AHB1LPENR_ETH1RXLPEN (1 << 17) /* RCC AHB1LPENR: ETH1RXLPEN */ -#define RCC_AHB1LPENR_OTGHSLPEN (1 << 25) /* RCC AHB1LPENR: OTGHSLPEN */ -#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 26) /* RCC AHB1LPENR: OTGHSULPILPEN */ -#define RCC_AHB1LPENR_OTGFSLPEN (1 << 27) /* RCC AHB1LPENR: OTGFSLPEN */ - -/* AHB2 low power mode peripheral clock enable register */ - -#define RCC_AHB2LPENR_CAMITFLPEN (1 << 0) /* RCC AHB2LPENR: CAMITFLPEN */ -#define RCC_AHB2LPENR_CRYPTLPEN (1 << 4) /* RCC AHB2LPENR: CRYPTLPEN */ -#define RCC_AHB2LPENR_HASHLPEN (1 << 5) /* RCC AHB2LPENR: HASHLPEN */ -#define RCC_AHB2LPENR_SDMMC2LPEN (1 << 6) /* RCC AHB2LPENR: SDMMC2LPEN */ -#define RCC_AHB2LPENR_RNGLPEN (1 << 9) /* RCC AHB2LPENR: RNGLPEN */ -#define RCC_AHB2LPENR_SRAM1LPEN (1 << 29) /* RCC AHB2LPENR: SRAM1LPEN */ -#define RCC_AHB2LPENR_SRAM2LPEN (1 << 30) /* RCC AHB2LPENR: SRAM2LPEN */ -#define RCC_AHB2LPENR_SRAM3LPEN (1 << 31) /* RCC AHB2LPENR: SRAM3LPEN */ - -/* AHB4 low power mode peripheral clock enable register */ - -#define RCC_AHB4LPENR_GPIOALPEN (1 << 0) /* RCC AHB4LPENR: GPIOALPEN */ -#define RCC_AHB4LPENR_GPIOBLPEN (1 << 1) /* RCC AHB4LPENR: GPIOBLPEN */ -#define RCC_AHB4LPENR_GPIOCLPEN (1 << 2) /* RCC AHB4LPENR: GPIOCLPEN */ -#define RCC_AHB4LPENR_GPIODLPEN (1 << 3) /* RCC AHB4LPENR: GPIODLPEN */ -#define RCC_AHB4LPENR_GPIOELPEN (1 << 4) /* RCC AHB4LPENR: GPIOELPEN */ -#define RCC_AHB4LPENR_GPIOFLPEN (1 << 5) /* RCC AHB4LPENR: GPIOFLPEN */ -#define RCC_AHB4LPENR_GPIOGLPEN (1 << 6) /* RCC AHB4LPENR: GPIOGLPEN */ -#define RCC_AHB4LPENR_GPIOHLPEN (1 << 7) /* RCC AHB4LPENR: GPIOHLPEN */ -#define RCC_AHB4LPENR_GPIOILPEN (1 << 8) /* RCC AHB4LPENR: GPIOILPEN */ -#define RCC_AHB4LPENR_GPIOJLPEN (1 << 9) /* RCC AHB4LPENR: GPIOJLPEN */ -#define RCC_AHB4LPENR_GPIOKLPEN (1 << 10) /* RCC AHB4LPENR: GPIOKLPEN */ -#define RCC_AHB4LPENR_CRCLPEN (1 << 19) /* RCC AHB4LPENR: CRCLPEN */ -#define RCC_AHB4LPENR_BDMALPEN (1 << 21) /* RCC AHB4LPENR: BDMALPEN */ -#define RCC_AHB4LPENR_ADC3LPEN (1 << 24) /* RCC AHB4LPENR: ADC3LPEN */ -#define RCC_AHB4LPENR_BKPRAMLPEN (1 << 28) /* RCC AHB4LPENR: BKPRAMLPEN */ -#define RCC_AHB4LPENR_SRAM4LPEN (1 << 29) /* RCC AHB4LPENR: SRAM4LPEN */ - -/* APB3 low power mode peripheral clock enable register */ - -#define RCC_APB3LPENR_LTDCLPEN (1 << 3) /* RCC APB3LPENR: LTDCLPEN */ -#define RCC_APB3LPENR_WWDG1LPEN (1 << 6) /* RCC APB3LPENR: WWDG1LPEN */ - -/* APB1 L low power mode peripheral clock enable register */ - -#define RCC_APB1LLPENR_TIM2LPEN (1 << 0) /* RCC APB1LLPENR: TIM2LPEN */ -#define RCC_APB1LLPENR_TIM3LPEN (1 << 1) /* RCC APB1LLPENR: TIM3LPEN */ -#define RCC_APB1LLPENR_TIM4LPEN (1 << 2) /* RCC APB1LLPENR: TIM4LPEN */ -#define RCC_APB1LLPENR_TIM5LPEN (1 << 3) /* RCC APB1LLPENR: TIM5LPEN */ -#define RCC_APB1LLPENR_TIM6LPEN (1 << 4) /* RCC APB1LLPENR: TIM6LPEN */ -#define RCC_APB1LLPENR_TIM7LPEN (1 << 5) /* RCC APB1LLPENR: TIM7LPEN */ -#define RCC_APB1LLPENR_TIM12LPEN (1 << 6) /* RCC APB1LLPENR: TIM12LPEN */ -#define RCC_APB1LLPENR_TIM13LPEN (1 << 7) /* RCC APB1LLPENR: TIM13LPEN */ -#define RCC_APB1LLPENR_TIM14LPEN (1 << 8) /* RCC APB1LLPENR: TIM14LPEN */ -#define RCC_APB1LLPENR_LPTIM1LPEN (1 << 9) /* RCC APB1LLPENR: LPTIM1LPEN */ -#define RCC_APB1LLPENR_SPI2LPEN (1 << 14) /* RCC APB1LLPENR: SPI2LPEN */ -#define RCC_APB1LLPENR_SPI3LPEN (1 << 15) /* RCC APB1LLPENR: SPI3LPEN */ -#define RCC_APB1LLPENR_SPDIFRXLPEN (1 << 16) /* RCC APB1LLPENR: SPDIFRXLPEN */ -#define RCC_APB1LLPENR_USART2LPEN (1 << 17) /* RCC APB1LLPENR: USART2LPEN */ -#define RCC_APB1LLPENR_USART3LPEN (1 << 18) /* RCC APB1LLPENR: USART3LPEN */ -#define RCC_APB1LLPENR_UART4LPEN (1 << 19) /* RCC APB1LLPENR: UART4LPEN */ -#define RCC_APB1LLPENR_UART5LPEN (1 << 20) /* RCC APB1LLPENR: UART5LPEN */ -#define RCC_APB1LLPENR_I2C1LPEN (1 << 21) /* RCC APB1LLPENR: I2C1LPEN */ -#define RCC_APB1LLPENR_I2C2LPEN (1 << 22) /* RCC APB1LLPENR: I2C2LPEN */ -#define RCC_APB1LLPENR_I2C3LPEN (1 << 23) /* RCC APB1LLPENR: I2C3LPEN */ -#define RCC_APB1LLPENR_HDMICECLPEN (1 << 27) /* RCC APB1LLPENR: HDMICECLPEN */ -#define RCC_APB1LLPENR_DAC1LPEN (1 << 29) /* RCC APB1LLPENR: DAC1LPEN */ -#define RCC_APB1LLPENR_UART7LPEN (1 << 30) /* RCC APB1LLPENR: UART7LPEN */ -#define RCC_APB1LLPENR_UART8LPEN (1 << 31) /* RCC APB1LLPENR: UART8LPEN */ - -/* APB1 H low power mode peripheral clock enable register */ - -#define RCC_APB1HLPENR_CRSLPEN (1 << 1) /* RCC APB1HLPENR: CRSLPEN */ -#define RCC_APB1HLPENR_SWPLPEN (1 << 2) /* RCC APB1HLPENR: SWPLPEN */ -#define RCC_APB1HLPENR_OPAMPLPEN (1 << 4) /* RCC APB1HLPENR: OPAMPLPEN */ -#define RCC_APB1HLPENR_MDIOSLPEN (1 << 5) /* RCC APB1HLPENR: MDIOSLPEN */ -#define RCC_APB1HLPENR_FDCANLPEN (1 << 8) /* RCC APB1HLPENR: FDCANLPEN */ - -/* APB2 low power mode peripheral clock enable register */ - -#define RCC_APB2LPENR_TIM1LPEN (1 << 0) /* RCC APB2LPENR: TIM1LPEN */ -#define RCC_APB2LPENR_TIM8LPEN (1 << 1) /* RCC APB2LPENR: TIM8LPEN */ -#define RCC_APB2LPENR_USART1LPEN (1 << 4) /* RCC APB2LPENR: USART1LPEN */ -#define RCC_APB2LPENR_USART6LPEN (1 << 5) /* RCC APB2LPENR: USART6LPEN */ -#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* RCC APB2LPENR: SPI1LPEN */ -#define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* RCC APB2LPENR: SPI4LPEN */ -#define RCC_APB2LPENR_TIM15LPEN (1 << 16) /* RCC APB2LPENR: TIM15LPEN */ -#define RCC_APB2LPENR_TIM16LPEN (1 << 17) /* RCC APB2LPENR: TIM16LPEN */ -#define RCC_APB2LPENR_TIM17LPEN (1 << 18) /* RCC APB2LPENR: TIM17LPEN */ -#define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* RCC APB2LPENR: SPI5LPEN */ -#define RCC_APB2LPENR_SAI1LPEN (1 << 22) /* RCC APB2LPENR: SAI1LPEN */ -#define RCC_APB2LPENR_SAI2LPEN (1 << 23) /* RCC APB2LPENR: SAI2LPEN */ -#define RCC_APB2LPENR_SAI3LPEN (1 << 24) /* RCC APB2LPENR: SAI3LPEN */ -#define RCC_APB2LPENR_DFSDM1LPEN (1 << 28) /* RCC APB2LPENR: DFSDM1LPEN */ -#define RCC_APB2LPENR_HRTIMLPEN (1 << 29) /* RCC APB2LPENR: HRTIMLPEN */ - -/* APB4 low power mode peripheral clock enable register */ - -#define RCC_APB4LPENR_SYSCFGLPEN (1 << 1) /* RCC APB4LPENR: SYSCFGLPEN */ -#define RCC_APB4LPENR_LPUART1LPEN (1 << 3) /* RCC APB4LPENR: LPUART1LPEN */ -#define RCC_APB4LPENR_SPI6LPEN (1 << 5) /* RCC APB4LPENR: SPI6LPEN */ -#define RCC_APB4LPENR_I2C4LPEN (1 << 7) /* RCC APB4LPENR: I2C4LPEN */ -#define RCC_APB4LPENR_LPTIM2LPEN (1 << 9) /* RCC APB4LPENR: LPTIM2LPEN */ -#define RCC_APB4LPENR_LPTIM3LPEN (1 << 10) /* RCC APB4LPENR: LPTIM3LPEN */ -#define RCC_APB4LPENR_LPTIM4LPEN (1 << 11) /* RCC APB4LPENR: LPTIM4LPEN */ -#define RCC_APB4LPENR_LPTIM5LPEN (1 << 12) /* RCC APB4LPENR: LPTIM5LPEN */ -#define RCC_APB4LPENR_COMP12LPEN (1 << 14) /* RCC APB4LPENR: COMP12LPEN */ -#define RCC_APB4LPENR_VREFLPEN (1 << 15) /* RCC APB4LPENR: VREFLPEN */ -#define RCC_APB4LPENR_RTCAPBLPEN (1 << 16) /* RCC APB4LPENR: RTCAPBLPEN */ -#define RCC_APB4LPENR_SAI4LPEN (1 << 21) /* RCC APB4LPENR: SAI4LPEN */ - -/* Backup domain control register */ - -#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */ -#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 4:3: LSE oscillator Drive selection */ -#define RCC_BDCR_LSEDRV_MASK (3 << RCC_BDCR_LSEDRV_SHIFT) /* See errata ES0392 Rev 7. 2.2.14 */ -# define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Low driving capability */ -# define RCC_BDCR_LSEDRV_MEDHI_Y (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium high driving capability rev y */ -# define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium high driving capability */ -# define RCC_BDCR_LSEDRV_MEDLO_Y (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium low driving capability rev y */ -# define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium low driving capability */ -# define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: High driving capability */ -#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: LSE clock security system enable */ -#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: LSE clock security system failure detection */ - /* Bit 7: Reserved */ -#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 9:8: RTC clock source selection */ -#define RCC_BDCR_RTCSEL_MASK (3 << RCC_BDCR_RTCSEL_SHIFT) -# define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */ -# define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */ -# define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */ - /* Bits 10-15: Reserved */ -#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */ -#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */ - /* Bits 17-31: Reserved */ - -#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */ diff --git a/arch/arm/src/stm32h7/stm32_lsi.c b/arch/arm/src/stm32h7/stm32_lsi.c deleted file mode 100644 index abfa0c0d8ded2..0000000000000 --- a/arch/arm/src/stm32h7/stm32_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal RC 40 kHz oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32l0/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32l0/hardware/stm32_rcc.h index 1b924ce687016..8d4ccc91a9f53 100644 --- a/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32l0/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32l0/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -538,4 +538,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32_rcc.h index c557971f1a356..50690b0bc4536 100644 --- a/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -459,4 +459,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 4683bf3f08207..71b1717f6e9dc 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -36,7 +36,6 @@ list( stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c - stm32l4_lsi.c stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index a073cf3e87a4a..77ee12e985896 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -33,7 +33,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c -CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_lsi.c +CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c diff --git a/arch/arm/src/stm32l4/hardware/stm32_rcc.h b/arch/arm/src/stm32l4/hardware/stm32_rcc.h new file mode 100644 index 0000000000000..25063763b4114 --- /dev/null +++ b/arch/arm/src/stm32l4/hardware/stm32_rcc.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32l4/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32L4X3) +# include "hardware/stm32l4x3xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4X5) +# include "hardware/stm32l4x5xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4X6) +# include "hardware/stm32l4x6xx_rcc.h" +#elif defined(CONFIG_STM32_STM32L4XR) +# include "hardware/stm32l4xrxx_rcc.h" +#else +# error "Unsupported STM32L4 chip" +#endif + +#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c deleted file mode 100644 index ae42b876ca25d..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32l4_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index cfd801d08ab3e..e5e91d82a2d15 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -35,7 +35,6 @@ list( stm32l5_start.c stm32l5_spi.c stm32l5_lse.c - stm32l5_lsi.c stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index b01e736c4c8f7..e2588b6c50674 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -36,7 +36,7 @@ CHIP_ASRCS = CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c -CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c stm32l5_lsi.c +CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h rename to arch/arm/src/stm32l5/hardware/stm32_rcc.h index 64d4f7215e239..e9e15bb3f62e4 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h + * arch/arm/src/stm32l5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H -#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files @@ -866,4 +866,4 @@ # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) #endif /* CONFIG_STM32_STM32L562XX */ -#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c deleted file mode 100644 index 6d57b07aac4ae..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32l5_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index efa70a2ef9275..b14e619b3e66c 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -33,7 +33,7 @@ #include "chip.h" #if defined(CONFIG_STM32_STM32L562XX) -# include "hardware/stm32l562xx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error "Unsupported STM32L5 chip" #endif diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 70f5a875c1306..20e50c3bb84b3 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -32,7 +32,6 @@ set(SRCS stm32_start.c stm32_spi.c stm32_lse.c - stm32_lsi.c stm32u5xx_rcc.c stm32_pwr.c stm32_tim.c diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index a884bf0cbf33a..9c44a7c632047 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -36,7 +36,7 @@ CHIP_ASRCS = CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c CHIP_CSRCS += stm32_serial.c stm32_start.c -CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c stm32u5xx_rcc.c +CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32u5xx_rcc.c CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h rename to arch/arm/src/stm32u5/hardware/stm32_rcc.h index f78e13bfccdc5..aaebbddb012b0 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h + * arch/arm/src/stm32u5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H -#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U5xx_RCC_H +#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_RCC_H /**************************************************************************** * Included Files diff --git a/arch/arm/src/stm32u5/stm32_lsi.c b/arch/arm/src/stm32u5/stm32_lsi.c deleted file mode 100644 index 34e53e22ac4a2..0000000000000 --- a/arch/arm/src/stm32u5/stm32_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC BDCR register. - */ - - modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the - * LSION bit the RCC BDCR register. - */ - - modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index ae75e4a235666..7354a096ab031 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -33,7 +33,7 @@ #include "chip.h" #if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) -# include "hardware/stm32u5xx_rcc.h" +# include "hardware/stm32_rcc.h" #else # error "Unsupported STM32U5 chip" #endif diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 03f9157eed58e..5d716f780a4fb 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -34,7 +34,6 @@ set(SRCS stm32wb_i2c.c stm32wb_start.c stm32wb_rcc_lse.c - stm32wb_rcc_lsi.c stm32wb_pwr.c stm32wb_tim.c stm32wb_flash.c) diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 5a4bdcdb88e24..5c14a1271b091 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -33,7 +33,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c -CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c +CHIP_CSRCS += stm32wb_rcc_lse.c CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c CHIP_CSRCS += stm32wb_flash.c diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32wb/hardware/stm32wb_rcc.h rename to arch/arm/src/stm32wb/hardware/stm32_rcc.h index 3c22fdb4251ab..c627addfabc24 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/hardware/stm32wb_rcc.h + * arch/arm/src/stm32wb/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index c9b889aec9a02..b03cb6534406c 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32wb_ipcc.h" -#include "hardware/stm32wb_rcc.h" +#include "hardware/stm32_rcc.h" #include "hardware/stm32wb_exti.h" #include "hardware/stm32wb_pwr.h" diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index bd2878d4523b0..7c1a73c5c44bd 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -789,7 +789,7 @@ static void stm32_stdclockconfig(void) #if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32_rcc_enable_lsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index 7fbbbd8ab19e4..8254254b26a7e 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -31,7 +31,7 @@ #include "arm_internal.h" #include "chip.h" -#include "hardware/stm32wb_rcc.h" +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -190,24 +190,24 @@ void stm32_clockenable(void); void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32_rcc_enable_lsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_rcc_enable_lsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32_rcc_disable_lsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_rcc_disable_lsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** * Name: stm32_rcc_enable_hsi48 diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c deleted file mode 100644 index 7dcdc39a50b48..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_rcc_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "stm32wb_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enable_lsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enable_lsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disable_lsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disable_lsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index b13a427ce34d6..ee8a4d6b07d13 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -32,7 +32,6 @@ set(SRCS stm32wl5_serial.c stm32wl5_start.c stm32wl5_lse.c - stm32wl5_lsi.c stm32wl5_idle.c stm32wl5_pwr.c stm32wl5_tim.c diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index d61921e8c127b..200082d446380 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -33,7 +33,7 @@ include common/stm32/Make.defs CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c -CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c +CHIP_CSRCS += stm32wl5_lse.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32_rcc.h similarity index 99% rename from arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h rename to arch/arm/src/stm32wl5/hardware/stm32_rcc.h index d0bfdf1b601ab..aecb3c463cf5e 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h + * arch/arm/src/stm32wl5/hardware/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c deleted file mode 100644 index 12ce587823d89..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_lsi.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "arm_internal.h" -#include "stm32wl5_rcc.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); - - /* Wait for the internal LSI oscillator to be stable. */ - - while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); -} - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void) -{ - /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION - * bit the RCC CSR register. - */ - - modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); - - /* LSIRDY should go low after 3 LSI clock cycles */ -} diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 5b1cd5dc7ef67..d5cfe3bb02d0b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "hardware/stm32wl5_rcc.h" +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions From 101b04300d7988c9d786d23c8916d6c97c18b868 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 12:58:53 +0200 Subject: [PATCH 48/52] !arch/arm/src/stm32: unify timer driver and STM32_TIMn_CLKIN across all families Collapse the per-IP and per-family STM32 timer drivers into a single implementation under arch/arm/src/common/stm32 shared by all 18 families (M0, M3/M4, and the formerly self-contained F7/H7/H5/L4/L5/U5/ WL5/WB chips), and standardize the timer input-clock board option. This step allows you to unify all other drivers that depend on stm32_tim. Changes for timer drivers: - stm32_tim_m3m4_v1v2v3.c -> common/stm32/stm32_tim.c (single driver) and stm32_tim_m0_v1_lowerhalf.c -> common/stm32/stm32_tim_lowerhalf.c. - Delete stm32_tim_m0_v1.{c,h}, stm32_tim_m3m4_v1v2v3.h and the per-family drivers/headers; M0 now uses the same driver as everyone else. - Build it from the common build system with a single gate (CONFIG_STM32_TIM); no chip Make.defs/CMakeLists lists it. - Per-family RCC clock-enable register/bit differences are handled by define aliases in common/stm32/stm32_tim_clk.h; the timer input clock is bus-agnostic in the driver. WB register unification: - Delete arch/arm/src/stm32wb/hardware/stm32wb_tim.h (non-standard TIMn_* names). WB selects STM32_HAVE_IP_TIMERS_M3M4_V2 and uses the common GTIM_*/ATIM_* register header like every other M3/M4 family. Board timer input clock: - Replace the two divergent board conventions, STM32_APBx_TIMn_CLKIN and BOARD_TIMn_FREQUENCY, with a single uniform STM32_TIMn_CLKIN provided by every board, and drop the CLKIN aliasing from stm32_tim_clk.h. All STM32 consumers (pwm/adc/dac/capture/sdadc/dfsdm/pulsecount) updated to match. Boards reach the common timer header via the existing STM32_COMMON_SRCDIR pattern in boards/arm//common/Makefile (added for WB). BREAKING CHANGE: The timer input-clock board macros STM32_APBx_TIMn_CLKIN and BOARD_TIMn_FREQUENCY are removed in favor of a single STM32_TIMn_CLKIN. Out-of-tree boards must define STM32_TIMn_CLKIN (drop the APB bus from the name, keep the value), and out-of-tree drivers referencing the old names must be updated. The per-family/per-IP timer drivers and headers (stm32_tim_m0_v1.*, stm32_tim_m3m4_v1v2v3.*, /stm32_tim.*, and stm32wb/hardware/stm32wb_tim.h) are removed; include the common arch/arm/src/common/stm32/stm32_tim.h instead. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 42 +- Documentation/guides/stm32_ports.rst | 41 + arch/arm/src/common/stm32/CMakeLists.txt | 18 +- arch/arm/src/common/stm32/Kconfig.have | 13 + arch/arm/src/common/stm32/Make.defs | 17 +- arch/arm/src/common/stm32/stm32_adc_m0_v1.h | 8 +- .../src/common/stm32/stm32_adc_m3m4_v1v2.h | 74 +- .../src/common/stm32/stm32_capture_m3m4_v1.c | 24 +- arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c | 14 +- arch/arm/src/common/stm32/stm32_pulsecount.c | 5 +- arch/arm/src/common/stm32/stm32_pwm_m0_v1.c | 14 +- .../src/common/stm32/stm32_pwm_m3m4_v1v2v3.c | 58 +- .../src/common/stm32/stm32_sdadc_m3m4_v1.h | 36 +- .../{stm32_tim_m3m4_v1v2v3.c => stm32_tim.c} | 653 ++++-- arch/arm/src/common/stm32/stm32_tim.h | 210 +- arch/arm/src/common/stm32/stm32_tim_clk.h | 260 +++ ...0_v1_lowerhalf.c => stm32_tim_lowerhalf.c} | 94 +- arch/arm/src/common/stm32/stm32_tim_m0_v1.c | 1502 ------------- arch/arm/src/common/stm32/stm32_tim_m0_v1.h | 233 -- .../src/common/stm32/stm32_tim_m3m4_v1v2v3.h | 225 -- .../stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c | 588 ----- arch/arm/src/stm32c0/stm32.h | 1 - arch/arm/src/stm32f0/stm32.h | 1 - arch/arm/src/stm32f1/stm32.h | 1 - arch/arm/src/stm32f2/Kconfig | 2 + arch/arm/src/stm32f2/stm32.h | 1 - arch/arm/src/stm32f3/Kconfig | 4 + arch/arm/src/stm32f3/stm32.h | 1 - arch/arm/src/stm32f4/Kconfig | 2 + arch/arm/src/stm32f4/stm32.h | 1 - arch/arm/src/stm32f7/CMakeLists.txt | 2 +- arch/arm/src/stm32f7/Kconfig | 12 + arch/arm/src/stm32f7/Make.defs | 2 +- .../hardware/{stm32_tim.h => stm32f7_tim.h} | 2 +- arch/arm/src/stm32f7/stm32.h | 1 - arch/arm/src/stm32f7/stm32_adc.h | 40 +- arch/arm/src/stm32f7/stm32_capture.h | 2 +- arch/arm/src/stm32f7/stm32_pwm.c | 24 +- arch/arm/src/stm32f7/stm32_pwm.h | 2 +- arch/arm/src/stm32f7/stm32_tim.c | 1572 -------------- arch/arm/src/stm32f7/stm32_tim.h | 221 -- arch/arm/src/stm32f7/stm32_tim_lowerhalf.c | 591 ----- arch/arm/src/stm32g0/stm32.h | 1 - arch/arm/src/stm32g4/Kconfig | 2 + arch/arm/src/stm32g4/stm32.h | 1 - arch/arm/src/stm32h5/CMakeLists.txt | 6 +- arch/arm/src/stm32h5/Kconfig | 2 + arch/arm/src/stm32h5/Make.defs | 6 +- .../hardware/{stm32_tim.h => stm32h5_tim.h} | 2 +- arch/arm/src/stm32h5/stm32.h | 1 - arch/arm/src/stm32h5/stm32_adc.h | 28 +- arch/arm/src/stm32h5/stm32_pwm.c | 24 +- arch/arm/src/stm32h5/stm32_pwm.h | 2 +- arch/arm/src/stm32h5/stm32_tim.c | 1553 ------------- arch/arm/src/stm32h5/stm32_tim.h | 223 -- arch/arm/src/stm32h5/stm32_tim_lowerhalf.c | 586 ----- arch/arm/src/stm32h7/CMakeLists.txt | 6 +- arch/arm/src/stm32h7/Kconfig | 10 + arch/arm/src/stm32h7/Make.defs | 6 +- .../hardware/{stm32_tim.h => stm32h7_tim.h} | 2 +- arch/arm/src/stm32h7/stm32.h | 1 - arch/arm/src/stm32h7/stm32_adc.h | 42 +- arch/arm/src/stm32h7/stm32_capture.c | 24 +- arch/arm/src/stm32h7/stm32_capture.h | 2 +- arch/arm/src/stm32h7/stm32_pwm.c | 24 +- arch/arm/src/stm32h7/stm32_pwm.h | 2 +- arch/arm/src/stm32h7/stm32_tim.c | 1558 -------------- arch/arm/src/stm32h7/stm32_tim.h | 223 -- arch/arm/src/stm32h7/stm32_tim_lowerhalf.c | 582 ----- arch/arm/src/stm32l0/stm32.h | 1 - arch/arm/src/stm32l1/Kconfig | 1 + arch/arm/src/stm32l1/stm32.h | 1 - arch/arm/src/stm32l4/CMakeLists.txt | 5 - arch/arm/src/stm32l4/Kconfig | 8 + arch/arm/src/stm32l4/Make.defs | 6 +- arch/arm/src/stm32l4/stm32.h | 1 - arch/arm/src/stm32l4/stm32l4_adc.c | 2 +- arch/arm/src/stm32l4/stm32l4_adc.h | 42 +- arch/arm/src/stm32l4/stm32l4_dac.c | 14 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 2 +- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 14 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 2 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 2 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 18 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 2 +- arch/arm/src/stm32l4/stm32l4_tim.c | 1912 ----------------- arch/arm/src/stm32l4/stm32l4_tim.h | 231 -- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 626 ------ arch/arm/src/stm32l5/CMakeLists.txt | 5 - arch/arm/src/stm32l5/Make.defs | 6 +- arch/arm/src/stm32l5/stm32.h | 1 - arch/arm/src/stm32l5/stm32l5_tim.c | 1695 --------------- arch/arm/src/stm32l5/stm32l5_tim.h | 222 -- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 607 ------ arch/arm/src/stm32u5/CMakeLists.txt | 5 - arch/arm/src/stm32u5/Kconfig | 4 + arch/arm/src/stm32u5/Make.defs | 6 +- .../hardware/{stm32_tim.h => stm32u5_tim.h} | 2 +- arch/arm/src/stm32u5/stm32.h | 1 - arch/arm/src/stm32u5/stm32_tim.c | 1695 --------------- arch/arm/src/stm32u5/stm32_tim.h | 216 -- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 607 ------ arch/arm/src/stm32wb/CMakeLists.txt | 2 - arch/arm/src/stm32wb/Kconfig | 6 + arch/arm/src/stm32wb/Make.defs | 3 +- arch/arm/src/stm32wb/hardware/stm32wb_tim.h | 1387 ------------ arch/arm/src/stm32wb/stm32.h | 2 + arch/arm/src/stm32wb/stm32wb_tim.c | 1289 ----------- arch/arm/src/stm32wb/stm32wb_tim.h | 254 --- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 488 ----- arch/arm/src/stm32wl5/CMakeLists.txt | 1 - arch/arm/src/stm32wl5/Make.defs | 2 +- arch/arm/src/stm32wl5/stm32.h | 1 - arch/arm/src/stm32wl5/stm32wl5_tim.c | 1697 --------------- arch/arm/src/stm32wl5/stm32wl5_tim.h | 214 -- .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 607 ------ boards/arm/at32/at32f437-mini/include/board.h | 16 +- .../arm/stm32c0/nucleo-c071rb/include/board.h | 14 +- .../arm/stm32c0/nucleo-c092rc/include/board.h | 14 +- .../arm/stm32f0/nucleo-f072rb/include/board.h | 18 +- .../arm/stm32f0/nucleo-f091rc/include/board.h | 18 +- .../stm32f051-discovery/include/board.h | 18 +- .../stm32f072-discovery/include/board.h | 18 +- boards/arm/stm32f1/cloudctrl/include/board.h | 16 +- .../stm32f1/et-stm32-stamp/include/board.h | 32 +- .../arm/stm32f1/fire-stm32v2/include/board.h | 32 +- .../arm/stm32f1/hymini-stm32v/include/board.h | 32 +- .../stm32f1/hymini-stm32v/src/stm32_r61505u.c | 1 + .../stm32f1/hymini-stm32v/src/stm32_ssd1289.c | 1 + boards/arm/stm32f1/maple/include/board.h | 32 +- boards/arm/stm32f1/maple/src/stm32_lcd.c | 1 + .../arm/stm32f1/nucleo-f103rb/include/board.h | 8 +- .../stm32f1/olimex-stm32-p107/include/board.h | 16 +- .../stm32f1/olimexino-stm32/include/board.h | 32 +- boards/arm/stm32f1/shenzhou/include/board.h | 16 +- .../arm/stm32f1/stm3210e-eval/include/board.h | 32 +- .../arm/stm32f1/stm3210e-eval/src/stm32_lcd.c | 1 + boards/arm/stm32f1/stm32_tiny/include/board.h | 32 +- .../stm32f1/stm32butterfly2/include/board.h | 12 +- .../stm32f1/stm32f103-minimum/include/board.h | 32 +- .../stm32f1/stm32vldiscovery/include/board.h | 42 +- .../include/board-stm32f103vct6.h | 32 +- .../include/board-stm32f107vct6.h | 16 +- .../viewtool-stm32f107/src/stm32_highpri.c | 6 +- .../viewtool-stm32f107/src/stm32_ssd1289.c | 1 + .../arm/stm32f2/nucleo-f207zg/include/board.h | 28 +- .../stm32f2/olimex-stm32-p207/include/board.h | 44 +- boards/arm/stm32f2/photon/include/board.h | 44 +- .../arm/stm32f2/stm3220g-eval/include/board.h | 44 +- .../arm/stm32f3/nucleo-f302r8/include/board.h | 36 +- .../arm/stm32f3/nucleo-f303re/include/board.h | 36 +- .../arm/stm32f3/nucleo-f303ze/include/board.h | 36 +- .../arm/stm32f3/nucleo-f334r8/include/board.h | 36 +- .../stm32f3/nucleo-f334r8/src/stm32_spwm.c | 4 +- .../stm32f3/stm32f334-disco/include/board.h | 36 +- .../stm32f3/stm32f3discovery/include/board.h | 36 +- .../stm32f4/clicker2-stm32/include/board.h | 44 +- .../stm32f4/mikroe-stm32f4/include/board.h | 44 +- .../arm/stm32f4/nucleo-f401re/include/board.h | 44 +- .../arm/stm32f4/nucleo-f410rb/include/board.h | 16 +- .../arm/stm32f4/nucleo-f411re/include/board.h | 44 +- .../arm/stm32f4/nucleo-f412zg/include/board.h | 38 +- .../arm/stm32f4/nucleo-f429zi/include/board.h | 44 +- .../arm/stm32f4/nucleo-f446re/include/board.h | 44 +- boards/arm/stm32f4/odrive36/include/board.h | 44 +- .../stm32f4/olimex-stm32-e407/include/board.h | 44 +- .../stm32f4/olimex-stm32-h405/include/board.h | 44 +- .../stm32f4/olimex-stm32-h407/include/board.h | 44 +- .../stm32f4/olimex-stm32-p407/include/board.h | 44 +- boards/arm/stm32f4/omnibusf4/include/board.h | 44 +- .../arm/stm32f4/stm3240g-eval/include/board.h | 58 +- .../stm32f4/stm32f401rc-rs485/include/board.h | 44 +- .../stm32f4/stm32f411-minimum/include/board.h | 44 +- .../stm32f4/stm32f411e-disco/include/board.h | 44 +- .../stm32f4/stm32f429i-disco/include/board.h | 44 +- .../stm32f4/stm32f4discovery/include/board.h | 44 +- .../arm/stm32f7/nucleo-f722ze/include/board.h | 28 +- .../arm/stm32f7/nucleo-f746zg/include/board.h | 28 +- .../arm/stm32f7/nucleo-f767zi/include/board.h | 28 +- .../stm32f7/steval-eth001v1/include/board.h | 28 +- .../arm/stm32f7/stm32f746-ws/include/board.h | 28 +- .../stm32f7/stm32f746g-disco/include/board.h | 28 +- .../stm32f7/stm32f769i-disco/include/board.h | 28 +- .../stm32f777zit6-meadow/include/board.h | 28 +- .../arm/stm32g0/nucleo-g070rb/include/board.h | 16 +- .../arm/stm32g4/b-g431b-esc1/include/board.h | 44 +- .../arm/stm32g4/nucleo-g431kb/include/board.h | 44 +- .../arm/stm32g4/nucleo-g431rb/include/board.h | 44 +- .../arm/stm32h5/nucleo-h563zi/include/board.h | 54 +- .../stm32h7/linum-stm32h753bi/include/board.h | 28 +- .../arm/stm32h7/nucleo-h723zg/include/board.h | 28 +- .../arm/stm32h7/nucleo-h743zi/include/board.h | 28 +- .../stm32h7/nucleo-h743zi2/include/board.h | 28 +- .../arm/stm32h7/nucleo-h745zi/include/board.h | 28 +- .../arm/stm32h7/nucleo-h753zi/include/board.h | 28 +- boards/arm/stm32h7/openh743i/include/board.h | 28 +- .../arm/stm32h7/portenta-h7/include/board.h | 28 +- .../stm32h7/stm32h745i-disco/include/board.h | 28 +- .../stm32h7/stm32h747i-disco/include/board.h | 28 +- .../arm/stm32h7/stm32h750b-dk/include/board.h | 28 +- .../stm32h7/weact-stm32h743/include/board.h | 28 +- .../stm32h7/weact-stm32h750/include/board.h | 28 +- .../stm32l1/stm32ldiscovery/include/board.h | 18 +- .../include/b-l475e-iot01a_clock.h | 65 +- .../stm32l4/b-l475e-iot01a/src/stm32_timer.c | 2 +- .../nucleo-l432kc/include/nucleo-l432kc.h | 48 +- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 2 +- .../stm32l4/nucleo-l432kc/src/stm32_timer.c | 2 +- .../nucleo-l452re/include/nucleo-l452re.h | 72 +- .../nucleo-l476rg/include/nucleo-l476rg.h | 88 +- .../stm32l4/nucleo-l476rg/src/stm32_timer.c | 2 +- .../arm/stm32l4/nucleo-l496zg/include/board.h | 88 +- .../stm32l4/steval-stlcs01v1/include/board.h | 44 +- .../include/stm32l476-mdk-clocking.h | 54 +- .../include/stm32l476vg-disco-clocking.h | 70 +- .../include/stm32l4r9ai-disco-clocking.h | 70 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 36 +- .../arm/stm32l5/stm32l562e-dk/include/board.h | 18 +- .../stm32u5/b-u585i-iot02a/include/board.h | 36 +- .../stm32u5/nucleo-u5a5zj-q/include/board.h | 36 +- boards/arm/stm32wb/common/Makefile | 3 + .../include/flipperzero-clocking.h | 13 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 2 +- .../nucleo-wb55rg/include/nucleo-wb55rg.h | 13 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 2 +- .../stm32wl5/nucleo-wl55jc/include/board.h | 16 +- 226 files changed, 3164 insertions(+), 25655 deletions(-) rename arch/arm/src/common/stm32/{stm32_tim_m3m4_v1v2v3.c => stm32_tim.c} (80%) create mode 100644 arch/arm/src/common/stm32/stm32_tim_clk.h rename arch/arm/src/common/stm32/{stm32_tim_m0_v1_lowerhalf.c => stm32_tim_lowerhalf.c} (89%) delete mode 100644 arch/arm/src/common/stm32/stm32_tim_m0_v1.c delete mode 100644 arch/arm/src/common/stm32/stm32_tim_m0_v1.h delete mode 100644 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h delete mode 100644 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c rename arch/arm/src/stm32f7/hardware/{stm32_tim.h => stm32f7_tim.h} (97%) delete mode 100644 arch/arm/src/stm32f7/stm32_tim.c delete mode 100644 arch/arm/src/stm32f7/stm32_tim.h delete mode 100644 arch/arm/src/stm32f7/stm32_tim_lowerhalf.c rename arch/arm/src/stm32h5/hardware/{stm32_tim.h => stm32h5_tim.h} (99%) delete mode 100644 arch/arm/src/stm32h5/stm32_tim.c delete mode 100644 arch/arm/src/stm32h5/stm32_tim.h delete mode 100644 arch/arm/src/stm32h5/stm32_tim_lowerhalf.c rename arch/arm/src/stm32h7/hardware/{stm32_tim.h => stm32h7_tim.h} (99%) delete mode 100644 arch/arm/src/stm32h7/stm32_tim.c delete mode 100644 arch/arm/src/stm32h7/stm32_tim.h delete mode 100644 arch/arm/src/stm32h7/stm32_tim_lowerhalf.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_tim.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_tim.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c delete mode 100644 arch/arm/src/stm32l5/stm32l5_tim.c delete mode 100644 arch/arm/src/stm32l5/stm32l5_tim.h delete mode 100644 arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c rename arch/arm/src/stm32u5/hardware/{stm32_tim.h => stm32u5_tim.h} (99%) delete mode 100644 arch/arm/src/stm32u5/stm32_tim.c delete mode 100644 arch/arm/src/stm32u5/stm32_tim.h delete mode 100644 arch/arm/src/stm32u5/stm32_tim_lowerhalf.c delete mode 100644 arch/arm/src/stm32wb/hardware/stm32wb_tim.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_tim.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_tim.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_tim.c delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_tim.h delete mode 100644 arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index ab0a3ce2e222a..591d48960d21d 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -1860,13 +1860,10 @@ arch/arm/src/common/stm32/stm32_start_m0_v1.c alin.jerpelea@sony.com acassis@gma arch/arm/src/common/stm32/stm32_start_m3m4_v1.c xiaoxiang@xiaomi.com avyhovanec@yahoo.com alin.jerpelea@sony.com raiden00@railab.me anjiahao@xiaomi.com arch/arm/src/common/stm32/stm32_syscfg.h alin.jerpelea@sony.com raiden00@railab.me paul-a.patience@polymtl.ca david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c kpberezenko@gmail.com macscomp@gmail.com anthony@vergeaero.com rajanjg89@gmail.com xiaoxiang@xiaomi.com +arch/arm/src/common/stm32/stm32_tim.c pn_bouteville@yahoo.fr 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com paul-a.patience@polymtl.ca anthony@vergeaero.com arch/arm/src/common/stm32/stm32_tim.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m0_v1.c pn_bouteville@yahoo.fr jukka.laitinen@iki.fi david_s5@nscdg.com dpo@certi.org.br raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m0_v1.h pn_bouteville@yahoo.fr jukka.laitinen@iki.fi xiaoxiang@xiaomi.com dpo@certi.org.br wail.khemir@polymtl.ca -arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca dpo@certi.org.br mark@mjs.pw walmis@gmail.com -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c pn_bouteville@yahoo.fr 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com paul-a.patience@polymtl.ca anthony@vergeaero.com -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h alin.jerpelea@sony.com pn_bouteville@yahoo.fr xiaoxiang@xiaomi.com wail.khemir@polymtl.ca raiden00@railab.me -arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca mark@mjs.pw xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/src/common/stm32/stm32_tim_clk.h raiden00@railab.me +arch/arm/src/common/stm32/stm32_tim_lowerhalf.c wail.khemir@polymtl.ca paul-a.patience@polymtl.ca dpo@certi.org.br mark@mjs.pw walmis@gmail.com arch/arm/src/common/stm32/stm32_timerisr_armv6m.c alin.jerpelea@sony.com acassis@gmail.com xiaoxiang@xiaomi.com raiden00@railab.me mark@mjs.pw arch/arm/src/common/stm32/stm32_timerisr_armv7m.c jpa@git.mail.kapsi.fi alin.jerpelea@sony.com huangqi3@xiaomi.com xiaoxiang@xiaomi.com mark@mjs.pw arch/arm/src/common/stm32/stm32_uart.h alin.jerpelea@sony.com raiden00@railab.me 407652334@qq.com zhangyuan21@xiaomi.com @@ -3909,7 +3906,7 @@ arch/arm/src/stm32f7/hardware/stm32_sai.h cuichaochao916@gmail.com alin.jerpelea arch/arm/src/stm32f7/hardware/stm32_sdmmc.h julian@oes.ch alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_spi.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_syscfg.h alin.jerpelea@sony.com -arch/arm/src/stm32f7/hardware/stm32_tim.h alin.jerpelea@sony.com +arch/arm/src/stm32f7/hardware/stm32f7_tim.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32_uart.h alin.jerpelea@sony.com arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h alin.jerpelea@sony.com petro.karashchenko@gmail.com raiden00@railab.me arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h alin.jerpelea@sony.com petro.karashchenko@gmail.com xiaoxiang@xiaomi.com @@ -4031,9 +4028,6 @@ arch/arm/src/stm32f7/stm32_spi.h 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32f7/stm32_start.c xiaoxiang@xiaomi.com alin.jerpelea@sony.com raiden00@railab.me lipengfei28@xiaomi.com arch/arm/src/stm32f7/stm32_start.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32f7/stm32_tickless.c walmis@gmail.com anthony@vergeaero.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32f7/stm32_tim.c peter.kolesnikov@external.telekom.de david_s5@nscdg.com alin.jerpelea@sony.com walmis@gmail.com anthony@vergeaero.com -arch/arm/src/stm32f7/stm32_tim.h 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com walmis@gmail.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com -arch/arm/src/stm32f7/stm32_tim_lowerhalf.c walmis@gmail.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com petro.karashchenko@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32f7/stm32_timerisr.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com mark@mjs.pw anthony@vergeaero.com arch/arm/src/stm32f7/stm32_uart.h David.Sidrane@NscDg.com alin.jerpelea@sony.com jussi.kivilinna@haltian.com david_s5@nscdg.com arch/arm/src/stm32f7/stm32_uid.c walmis@gmail.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com gustavo.nihei@espressif.com @@ -4107,7 +4101,7 @@ arch/arm/src/stm32h5/hardware/stm32_pwr.h kwilson@2g-eng.com alin.jerpelea@sony. arch/arm/src/stm32h5/hardware/stm32_qspi.h kwilson@2g-eng.com arch/arm/src/stm32h5/hardware/stm32_rcc.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_sbs.h tbennett@2g-eng.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com -arch/arm/src/stm32h5/hardware/stm32_tim.h tbennett@2g-eng.com kwilson@2g-eng.com 101105604+simbit18@users.noreply.github.com devel@sumpfralle.de +arch/arm/src/stm32h5/hardware/stm32h5_tim.h tbennett@2g-eng.com kwilson@2g-eng.com 101105604+simbit18@users.noreply.github.com devel@sumpfralle.de arch/arm/src/stm32h5/hardware/stm32_uart.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_usbfs.h kwilson@2g-eng.com arch/arm/src/stm32h5/hardware/stm32h56x_dmasigmap.h kwilson@2g-eng.com @@ -4159,9 +4153,6 @@ arch/arm/src/stm32h5/stm32_spi.c kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_spi.h kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_start.c tbennett@2g-eng.com jlange@2g-eng.com kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_start.h tbennett@2g-eng.com alin.jerpelea@sony.com -arch/arm/src/stm32h5/stm32_tim.c kwilson@2g-eng.com -arch/arm/src/stm32h5/stm32_tim.h kwilson@2g-eng.com -arch/arm/src/stm32h5/stm32_tim_lowerhalf.c kwilson@2g-eng.com arch/arm/src/stm32h5/stm32_timerisr.c tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_uart.h tbennett@2g-eng.com jlange@2g-eng.com kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/stm32_uid.c tbennett@2g-eng.com @@ -4200,7 +4191,7 @@ arch/arm/src/stm32h7/hardware/stm32_rtcc.h david.sidrane@nscdg.com alin.jerpelea arch/arm/src/stm32h7/hardware/stm32_sdmmc.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com po@lambdaconcept.com arch/arm/src/stm32h7/hardware/stm32_spi.h raiden00@railab.me alin.jerpelea@sony.com alexanderlunev@mail.ru javiercasas@geotab.com arch/arm/src/stm32h7/hardware/stm32_syscfg.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com lwazeh@gmail.com -arch/arm/src/stm32h7/hardware/stm32_tim.h raiden00pl@gmail.com alin.jerpelea@sony.com anthony@vergeaero.com dpo@certi.org.br +arch/arm/src/stm32h7/hardware/stm32h7_tim.h raiden00pl@gmail.com alin.jerpelea@sony.com anthony@vergeaero.com dpo@certi.org.br arch/arm/src/stm32h7/hardware/stm32_uart.h alin.jerpelea@sony.com raiden00@railab.me javiercasas@geotab.com lwazeh@gmail.com arch/arm/src/stm32h7/hardware/stm32_wdg.h jlange@2g-eng.com alin.jerpelea@sony.com petro.karashchenko@gmail.com arch/arm/src/stm32h7/hardware/stm32h7b3xx_flash.h javiercasas@geotab.com 101105604+simbit18@users.noreply.github.com alin.jerpelea@sony.com @@ -4301,9 +4292,6 @@ arch/arm/src/stm32h7/stm32_spi_slave.c jukka.laitinen@intel.com alin.jerpelea@so arch/arm/src/stm32h7/stm32_start.c simon@leitwert.ch xiaoxiang@xiaomi.com raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com arch/arm/src/stm32h7/stm32_start.h simon@leitwert.ch alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32h7/stm32_tickless.c anthony@vergeaero.com xiaoxiang@xiaomi.com zhangyuan21@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32h7/stm32_tim.c jukka.laitinen@iki.fi anthony@vergeaero.com xiaoxiang@xiaomi.com alin.jerpelea@sony.com petro.karashchenko@gmail.com -arch/arm/src/stm32h7/stm32_tim.h jukka.laitinen@iki.fi alin.jerpelea@sony.com xiaoxiang@xiaomi.com anthony@vergeaero.com zapparello@ya.ru -arch/arm/src/stm32h7/stm32_tim_lowerhalf.c max.kriegleder@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32h7/stm32_timerisr.c simon@leitwert.ch alin.jerpelea@sony.com raiden00pl@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32h7/stm32_uart.h David.Sidrane@NscDg.com raiden00pl@gmail.com alin.jerpelea@sony.com abdelatif.guettouche@gmail.com markus.bernet@hexagon.com arch/arm/src/stm32h7/stm32_uid.c david.sidrane@nscdg.com alin.jerpelea@sony.com gustavo.nihei@espressif.com 59230071+hartmannathan@users.noreply.github.com @@ -4488,9 +4476,6 @@ arch/arm/src/stm32l4/stm32l4_spi.h sebastien@lorquet.fr alin.jerpelea@sony.com x arch/arm/src/stm32l4/stm32l4_start.c sebastien@lorquet.fr xiaoxiang@xiaomi.com alin.jerpelea@sony.com dev@ziggurat29.com arch/arm/src/stm32l4/stm32l4_start.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_tickless.c dev@ziggurat29.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com sebastien@lorquet.fr -arch/arm/src/stm32l4/stm32l4_tim.c dev@ziggurat29.com sebastien@lorquet.fr danieloak@gmail.com godenfreemans@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32l4/stm32l4_tim.h dev@ziggurat29.com alin.jerpelea@sony.com godenfreemans@gmail.com danieloak@gmail.com xiaoxiang@xiaomi.com -arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c dev@ziggurat29.com sebastien@lorquet.fr mark@mjs.pw godenfreemans@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/stm32l4_timerisr.c sebastien@lorquet.fr alin.jerpelea@sony.com xiaoxiang@xiaomi.com mark@mjs.pw arch/arm/src/stm32l4/stm32l4_uart.h sebastien@lorquet.fr juha.niskanen@haltian.com alin.jerpelea@sony.com harri.luhtala@haltian.com jussi.kivilinna@haltian.com arch/arm/src/stm32l4/stm32l4_uid.c dev@ziggurat29.com alin.jerpelea@sony.com @@ -4555,9 +4540,6 @@ arch/arm/src/stm32l5/stm32l5_spi.c mijung@gmx.net alin.jerpelea@sony.com xiaoxia arch/arm/src/stm32l5/stm32l5_spi.h mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l5/stm32l5_start.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com anjiahao@xiaomi.com raiden00@railab.me arch/arm/src/stm32l5/stm32l5_start.h mijung@gmx.net alin.jerpelea@sony.com -arch/arm/src/stm32l5/stm32l5_tim.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com anthony@vergeaero.com danieloak@gmail.com -arch/arm/src/stm32l5/stm32l5_tim.h mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com danieloak@gmail.com -arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com arch/arm/src/stm32l5/stm32l5_timerisr.c mijung@gmx.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32l5/stm32l5_uart.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32l5/stm32l5_uid.c mijung@gmx.net alin.jerpelea@sony.com @@ -4577,7 +4559,7 @@ arch/arm/src/stm32u5/hardware/stm32_pinmap.h mijung@gmx.net cheshmedzhiev@gmail. arch/arm/src/stm32u5/hardware/stm32_pwr.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/src/stm32u5/hardware/stm32_spi.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com 101105604+simbit18@users.noreply.github.com arch/arm/src/stm32u5/hardware/stm32_syscfg.h mijung@gmx.net cheshmedzhiev@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/hardware/stm32_tim.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com +arch/arm/src/stm32u5/hardware/stm32u5_tim.h mijung@gmx.net devel@sumpfralle.de alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_dbgmcu.h cheshmedzhiev@gmail.com alin.jerpelea@sony.com arch/arm/src/stm32u5/hardware/stm32u5xx_pinmap.h cheshmedzhiev@gmail.com devel@sumpfralle.de alin.jerpelea@sony.com @@ -4613,9 +4595,6 @@ arch/arm/src/stm32u5/stm32_spi.c mijung@gmx.net xiaoxiang@xiaomi.com anjiahao@xi arch/arm/src/stm32u5/stm32_spi.h mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32u5/stm32_start.c mijung@gmx.net xiaoxiang@xiaomi.com anjiahao@xiaomi.com raiden00@railab.me cheshmedzhiev@gmail.com arch/arm/src/stm32u5/stm32_start.h mijung@gmx.net alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim.c mijung@gmx.net xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim.h mijung@gmx.net xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32u5/stm32_tim_lowerhalf.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com petro.karashchenko@gmail.com arch/arm/src/stm32u5/stm32_timerisr.c mijung@gmx.net xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32u5/stm32_uart.h mijung@gmx.net alin.jerpelea@sony.com cheshmedzhiev@gmail.com arch/arm/src/stm32u5/stm32_uid.c mijung@gmx.net alin.jerpelea@sony.com @@ -4642,7 +4621,6 @@ arch/arm/src/stm32wb/hardware/stm32wb_rcc.h s.nikitenko@me.com alin.jerpelea@son arch/arm/src/stm32wb/hardware/stm32wb_rtc.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_spi.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/hardware/stm32wb_tim.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wb_uart.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h David.Sidrane@NscDg.com alin.jerpelea@sony.com arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap_legacy.h David.Sidrane@NscDg.com alin.jerpelea@sony.com @@ -4703,9 +4681,6 @@ arch/arm/src/stm32wb/stm32wb_spi.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_start.c s.nikitenko@me.com xiaoxiang@xiaomi.com anjiahao@xiaomi.com raiden00@railab.me yinshengkai@xiaomi.com arch/arm/src/stm32wb/stm32wb_start.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_tickless.c s.nikitenko@me.com zhangyuan21@xiaomi.com gustavo.nihei@espressif.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim.c s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim.h s.nikitenko@me.com alin.jerpelea@sony.com -arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_timerisr.c s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_uart.h s.nikitenko@me.com alin.jerpelea@sony.com arch/arm/src/stm32wb/stm32wb_uid.c s.nikitenko@me.com alin.jerpelea@sony.com @@ -4755,9 +4730,6 @@ arch/arm/src/stm32wl5/stm32wl5_spi.c 49699333+dependabot[bot]@users.noreply.gith arch/arm/src/stm32wl5/stm32wl5_spi.h 49699333+dependabot[bot]@users.noreply.github.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_start.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com raiden00@railab.me yinshengkai@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_start.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com -arch/arm/src/stm32wl5/stm32wl5_tim.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com huangqi3@xiaomi.com -arch/arm/src/stm32wl5/stm32wl5_tim.h michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com danieloak@gmail.com alin.jerpelea@sony.com -arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c michal.lyszczek@bofc.pl xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_timerisr.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com huangqi3@xiaomi.com arch/arm/src/stm32wl5/stm32wl5_uart.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com arch/arm/src/stm32wl5/stm32wl5_uid.c michal.lyszczek@bofc.pl alin.jerpelea@sony.com diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst index 8121a5c241b3c..e3374699e1eb6 100644 --- a/Documentation/guides/stm32_ports.rst +++ b/Documentation/guides/stm32_ports.rst @@ -137,6 +137,47 @@ Watchdog ``STM32_HAVE_IP_WDG_M0_V1``, ``STM32_HAVE_IP_WDG_M3M4_V1`` DMA public interfaces are shared by channel and stream DMA; register maps and request mappings stay split by hardware shape. +Timer (TIM) IP cores +==================== + +All STM32 general-purpose and advanced-control timers share essentially one +register-compatible IP design. The ``STM32_HAVE_IP_TIMERS_*`` selectors only +distinguish minor register-map revisions, and they are largely upward +compatible - a more advanced version adds a few register bits and features but +keeps the same programming model: + +========== ================================= ================================= +IP core Selector Families +========== ================================= ================================= +M0_V1 ``STM32_HAVE_IP_TIMERS_M0_V1`` Cortex-M0 (C0, F0, G0, L0) +M3M4_V1 ``STM32_HAVE_IP_TIMERS_M3M4_V1`` F1, F2, F4, L1, F37x +M3M4_V2 ``STM32_HAVE_IP_TIMERS_M3M4_V2`` F30x, F33x +M3M4_V3 ``STM32_HAVE_IP_TIMERS_M3M4_V3`` G4 +========== ================================= ================================= + +Families with their own timer register driver (F7, H7, H5, L4, L5, U5, WB, +WL5) implement the same ``STM32_TIM_*`` programming model and are being folded +onto the common driver as their headers are normalized. + +The one functional difference that matters to a generic timer user is the +**counter width**. Every timer is 16-bit except TIM2 and TIM5, which are +32-bit on most families. Because counter width does not follow the IP-core +version (e.g. TIM2 is 16-bit on F1 but 32-bit on F4, both ``M3M4_V1``), it is +carried by its own capability flags rather than by the IP selector or a chip +``#ifdef``: + +============================ =================================================== +Capability flag Meaning +============================ =================================================== +``STM32_HAVE_TIM2_32BITS`` TIM2 is a 32-bit counter on this family. +``STM32_HAVE_TIM5_32BITS`` TIM5 is a 32-bit counter on this family. +============================ =================================================== + +These are prompt-less ``bool`` flags in ``Kconfig.have`` (the default is 16-bit) +that the chip Kconfig ``select``-s next to its timer IP-core selector. The +16-bit cases - TIM2 on STM32F10xx/STM32L15xx, TIM5 on STM32F10xx/STM32F30xx, +and every timer on the Cortex-M0 ``M0_V1`` IP - simply leave them unset. + Kconfig option organization =========================== diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 2a13abd4ace44..37ce8f404482a 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -35,6 +35,14 @@ list(APPEND SRCS stm32_waste.c) list(APPEND SRCS stm32_uid.c) list(APPEND SRCS stm32_lsi.c) +if(CONFIG_TIMER AND CONFIG_STM32_TIM) + list(APPEND SRCS stm32_tim_lowerhalf.c) +endif() + +if(CONFIG_STM32_TIM) + list(APPEND SRCS stm32_tim.c) +endif() + if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() @@ -76,9 +84,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdio_m3m4_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_TIMERS) - list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) - endif() if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) list(APPEND SRCS stm32_ccm_m3m4_v1.c) @@ -151,10 +156,6 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) - list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) - endif() - if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) endif() @@ -456,9 +457,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_rng_m0_v1.c) endif() - if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) - list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) - endif() if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) list(APPEND SRCS stm32_iwdg_m0_v1.c) diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have index b7845fd96f313..aa0bed2eea211 100644 --- a/arch/arm/src/common/stm32/Kconfig.have +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -977,6 +977,19 @@ config STM32_HAVE_TIM19 config STM32_HAVE_TIM20 bool +# Timer counter width. TIM2 and TIM5 are 32-bit on most families; these +# capability flags carry that per-family knowledge so the common timer +# lower-half driver does not need chip-line #ifdefs. A family whose TIM2 or +# TIM5 is 32-bit selects the matching flag from its chip Kconfig; every other +# timer (and the 16-bit STM32F10xx/STM32L15xx/STM32F30xx/Cortex-M0 lines) is +# left at the default 16-bit width. + +config STM32_HAVE_TIM2_32BITS + bool + +config STM32_HAVE_TIM5_32BITS + bool + config STM32_HAVE_LPTIM1 bool diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index c1b981d38a514..0b2b6a4c9b3dc 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -43,6 +43,13 @@ CHIP_CSRCS += stm32_waste.c CHIP_CSRCS += stm32_uid.c CHIP_CSRCS += stm32_lsi.c +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_TIM),yy) +CHIP_CSRCS += stm32_tim_lowerhalf.c +endif +ifeq ($(CONFIG_STM32_TIM),y) +CHIP_CSRCS += stm32_tim.c +endif + ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif @@ -91,9 +98,6 @@ endif ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) CHIP_CSRCS += stm32_sdio_m3m4_v1.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) -CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c -endif ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) CHIP_CSRCS += stm32_ccm_m3m4_v1.c endif @@ -152,10 +156,6 @@ CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c endif endif -ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) -CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot_m3m4_v1.c CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c @@ -506,9 +506,6 @@ ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) CHIP_CSRCS += stm32_rng_m0_v1.c endif -ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) -CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c -endif ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) CHIP_CSRCS += stm32_iwdg_m0_v1.c diff --git a/arch/arm/src/common/stm32/stm32_adc_m0_v1.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h index 1cd50f60f7c5b..9413a2c5bc9b7 100644 --- a/arch/arm/src/common/stm32/stm32_adc_m0_v1.h +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -94,19 +94,19 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #else # undef ADC1_HAVE_TIMER #endif diff --git a/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h index b6317b5e32d5c..3d6e01da79a15 100644 --- a/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h @@ -352,47 +352,47 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM7_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM7_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #elif defined(CONFIG_STM32_TIM9_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM9_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM9_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM9_CLKIN #elif defined(CONFIG_STM32_TIM10_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM10_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM10_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM10_CLKIN #elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #else # undef ADC1_HAVE_TIMER #endif @@ -417,35 +417,35 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #else # undef ADC2_HAVE_TIMER #endif @@ -470,39 +470,39 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM7_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM7_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #elif defined(CONFIG_STM32_TIM20_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM20_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM20_CLKIN #else # undef ADC3_HAVE_TIMER #endif @@ -520,39 +520,39 @@ #if defined(CONFIG_STM32_TIM1_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM1_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM2_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM3_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM4_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM5_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM7_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM7_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM8_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #elif defined(CONFIG_STM32_TIM15_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM15_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #elif defined(CONFIG_STM32_TIM20_ADC4) # define ADC4_HAVE_TIMER 1 # define ADC4_TIMER_BASE STM32_TIM20_BASE -# define ADC4_TIMER_PCLK_FREQUENCY STM32_APB2_TIM20_CLKIN +# define ADC4_TIMER_PCLK_FREQUENCY STM32_TIM20_CLKIN #else # undef ADC4_HAVE_TIMER #endif diff --git a/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c index 48fcfe57c7390..f80e991692fe4 100644 --- a/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c @@ -645,62 +645,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; + freqin = STM32_TIM1_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; + freqin = STM32_TIM2_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; + freqin = STM32_TIM3_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; + freqin = STM32_TIM4_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; + freqin = STM32_TIM5_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; + freqin = STM32_TIM8_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; + freqin = STM32_TIM9_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; + freqin = STM32_TIM10_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; + freqin = STM32_TIM11_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; + freqin = STM32_TIM12_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; + freqin = STM32_TIM13_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; + freqin = STM32_TIM14_CLKIN; break; #endif diff --git a/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c index c9cb731658fb6..d54552ae80029 100644 --- a/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c @@ -1359,44 +1359,44 @@ static int dac_timinit(struct stm32_chan_s *chan) #ifdef NEED_TIM2 case 2: setbits = RCC_APB1ENR_TIM2EN; - pclk = BOARD_TIM2_FREQUENCY; + pclk = STM32_TIM2_CLKIN; break; #endif #ifdef NEED_TIM3 case 3: setbits = RCC_APB1ENR_TIM3EN; - pclk = BOARD_TIM3_FREQUENCY; + pclk = STM32_TIM3_CLKIN; break; #endif #ifdef NEED_TIM4 case 4: setbits = RCC_APB1ENR_TIM4EN; - pclk = BOARD_TIM4_FREQUENCY; + pclk = STM32_TIM4_CLKIN; break; #endif #ifdef NEED_TIM5 case 5: setbits = RCC_APB1ENR_TIM5EN; - pclk = BOARD_TIM5_FREQUENCY; + pclk = STM32_TIM5_CLKIN; break; #endif #ifdef NEED_TIM6 case 6: setbits = RCC_APB1ENR_TIM6EN; - pclk = BOARD_TIM6_FREQUENCY; + pclk = STM32_TIM6_CLKIN; break; #endif #ifdef NEED_TIM7 case 7: setbits = RCC_APB1ENR_TIM7EN; - pclk = BOARD_TIM7_FREQUENCY; + pclk = STM32_TIM7_CLKIN; break; #endif #ifdef NEED_TIM8 case 8: regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; - pclk = BOARD_TIM8_FREQUENCY; + pclk = STM32_TIM8_CLKIN; break; #endif default: diff --git a/arch/arm/src/common/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount.c index fd98e42ef061a..e46aa4e383196 100644 --- a/arch/arm/src/common/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount.c @@ -40,6 +40,7 @@ #include "chip.h" #include "stm32_pulsecount.h" #include "stm32.h" +#include "stm32_tim.h" /* Generalized pulse count support for all STM32 families */ @@ -59,12 +60,12 @@ * RCC RST offset, reset bit to use */ -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +#define TIMCLK_TIM1 STM32_TIM1_CLKIN #define TIMRCCEN_TIM1 STM32_RCC_APB2ENR #define TIMEN_TIM1 RCC_APB2ENR_TIM1EN #define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR #define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +#define TIMCLK_TIM8 STM32_TIM8_CLKIN #define TIMRCCEN_TIM8 STM32_RCC_APB2ENR #define TIMEN_TIM8 RCC_APB2ENR_TIM8EN #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR diff --git a/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c index cf7e6a3b23843..e5b9289c685dd 100644 --- a/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c @@ -280,7 +280,7 @@ static struct stm32_pwmtimer_s g_pwm1dev = .timtype = TIMTYPE_TIM1, .mode = CONFIG_STM32_TIM1_MODE, .base = STM32_TIM1_BASE, - .pclk = STM32_APB2_TIM1_CLKIN, + .pclk = STM32_TIM1_CLKIN, }; #endif @@ -327,7 +327,7 @@ static struct stm32_pwmtimer_s g_pwm2dev = .timtype = TIMTYPE_TIM2, .mode = CONFIG_STM32_TIM2_MODE, .base = STM32_TIM2_BASE, - .pclk = STM32_APB1_TIM2_CLKIN, + .pclk = STM32_TIM2_CLKIN, }; #endif @@ -374,7 +374,7 @@ static struct stm32_pwmtimer_s g_pwm3dev = .timtype = TIMTYPE_TIM3, .mode = CONFIG_STM32_TIM3_MODE, .base = STM32_TIM3_BASE, - .pclk = STM32_APB1_TIM3_CLKIN, + .pclk = STM32_TIM3_CLKIN, }; #endif @@ -397,7 +397,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .timtype = TIMTYPE_TIM14, .mode = STM32_TIMMODE_COUNTUP, .base = STM32_TIM14_BASE, - .pclk = STM32_APB2_TIM14_CLKIN, + .pclk = STM32_TIM14_CLKIN, }; #endif @@ -428,7 +428,7 @@ static struct stm32_pwmtimer_s g_pwm15dev = .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, .base = STM32_TIM15_BASE, - .pclk = STM32_APB2_TIM15_CLKIN, + .pclk = STM32_TIM15_CLKIN, }; #endif @@ -451,7 +451,7 @@ static struct stm32_pwmtimer_s g_pwm16dev = .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, .base = STM32_TIM16_BASE, - .pclk = STM32_APB2_TIM16_CLKIN, + .pclk = STM32_TIM16_CLKIN, }; #endif @@ -474,7 +474,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, .base = STM32_TIM17_BASE, - .pclk = STM32_APB2_TIM17_CLKIN, + .pclk = STM32_TIM17_CLKIN, }; #endif diff --git a/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c index 17fff3b6e3e7f..85cf6fafad0e5 100644 --- a/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c @@ -106,148 +106,148 @@ */ #if defined(CONFIG_STM32_STM32F37XX) -# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMCLK_TIM2 STM32_TIM2_CLKIN # define TIMRCCEN_TIM2 STM32_RCC_APB1ENR # define TIMEN_TIM2 RCC_APB1ENR_TIM2EN # define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR # define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST -# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMCLK_TIM3 STM32_TIM3_CLKIN # define TIMRCCEN_TIM3 STM32_RCC_APB1ENR # define TIMEN_TIM3 RCC_APB1ENR_TIM3EN # define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR # define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST -# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMCLK_TIM4 STM32_TIM4_CLKIN # define TIMRCCEN_TIM4 STM32_RCC_APB1ENR # define TIMEN_TIM4 RCC_APB1ENR_TIM4EN # define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR # define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST -# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMCLK_TIM5 STM32_TIM5_CLKIN # define TIMRCCEN_TIM5 STM32_RCC_APB1ENR # define TIMEN_TIM5 RCC_APB1ENR_TIM5EN # define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR # define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST -# define TIMCLK_TIM6 STM32_APB1_TIM6_CLKIN +# define TIMCLK_TIM6 STM32_TIM6_CLKIN # define TIMRCCEN_TIM6 STM32_RCC_APB1ENR # define TIMEN_TIM6 RCC_APB1ENR_TIM6EN # define TIMRCCRST_TIM6 STM32_RCC_APB1RSTR # define TIMRST_TIM6 RCC_APB1RSTR_TIM6RST -# define TIMCLK_TIM7 STM32_APB1_TIM7_CLKIN +# define TIMCLK_TIM7 STM32_TIM7_CLKIN # define TIMRCCEN_TIM7 STM32_RCC_APB1ENR # define TIMEN_TIM7 RCC_APB1ENR_TIM7EN # define TIMRCCRST_TIM7 STM32_RCC_APB1RSTR # define TIMRST_TIM7 RCC_APB1RSTR_TIM7RST -# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMCLK_TIM12 STM32_TIM12_CLKIN # define TIMRCCEN_TIM12 STM32_RCC_APB1ENR # define TIMEN_TIM12 RCC_APB1ENR_TIM12EN # define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR # define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST -# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMCLK_TIM13 STM32_TIM13_CLKIN # define TIMRCCEN_TIM13 STM32_RCC_APB1ENR # define TIMEN_TIM13 RCC_APB1ENR_TIM13EN # define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR # define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST -# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMCLK_TIM14 STM32_TIM14_CLKIN # define TIMRCCEN_TIM14 STM32_RCC_APB1ENR # define TIMEN_TIM14 RCC_APB1ENR_TIM14EN # define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR # define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST -# define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +# define TIMCLK_TIM15 STM32_TIM15_CLKIN # define TIMRCCEN_TIM15 STM32_RCC_APB2ENR # define TIMEN_TIM15 RCC_APB2ENR_TIM15EN # define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR # define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST -# define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +# define TIMCLK_TIM16 STM32_TIM16_CLKIN # define TIMRCCEN_TIM16 STM32_RCC_APB2ENR # define TIMEN_TIM16 RCC_APB2ENR_TIM16EN # define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR # define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST -# define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +# define TIMCLK_TIM17 STM32_TIM17_CLKIN # define TIMRCCEN_TIM17 STM32_RCC_APB2ENR # define TIMEN_TIM17 RCC_APB2ENR_TIM17EN # define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR # define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST -# define TIMCLK_TIM18 STM32_APB1_TIM18_CLKIN +# define TIMCLK_TIM18 STM32_TIM18_CLKIN # define TIMRCCEN_TIM18 STM32_RCC_APB1ENR # define TIMEN_TIM18 RCC_APB1ENR_TIM18EN # define TIMRCCRST_TIM18 STM32_RCC_APB1RSTR # define TIMRST_TIM18 RCC_APB1RSTR_TIM18RST -# define TIMCLK_TIM19 STM32_APB2_TIM19_CLKIN +# define TIMCLK_TIM19 STM32_TIM19_CLKIN # define TIMRCCEN_TIM19 STM32_RCC_APB2ENR # define TIMEN_TIM19 RCC_APB2ENR_TIM19EN # define TIMRCCRST_TIM19 STM32_RCC_APB2RSTR # define TIMRST_TIM19 RCC_APB2RSTR_TIM19RST #else -# define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +# define TIMCLK_TIM1 STM32_TIM1_CLKIN # define TIMRCCEN_TIM1 STM32_RCC_APB2ENR # define TIMEN_TIM1 RCC_APB2ENR_TIM1EN # define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR # define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -# define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +# define TIMCLK_TIM2 STM32_TIM2_CLKIN # define TIMRCCEN_TIM2 STM32_RCC_APB1ENR # define TIMEN_TIM2 RCC_APB1ENR_TIM2EN # define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR # define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST -# define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +# define TIMCLK_TIM3 STM32_TIM3_CLKIN # define TIMRCCEN_TIM3 STM32_RCC_APB1ENR # define TIMEN_TIM3 RCC_APB1ENR_TIM3EN # define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR # define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST -# define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +# define TIMCLK_TIM4 STM32_TIM4_CLKIN # define TIMRCCEN_TIM4 STM32_RCC_APB1ENR # define TIMEN_TIM4 RCC_APB1ENR_TIM4EN # define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR # define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST -# define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +# define TIMCLK_TIM5 STM32_TIM5_CLKIN # define TIMRCCEN_TIM5 STM32_RCC_APB1ENR # define TIMEN_TIM5 RCC_APB1ENR_TIM5EN # define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR # define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST -# define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +# define TIMCLK_TIM8 STM32_TIM8_CLKIN # define TIMRCCEN_TIM8 STM32_RCC_APB2ENR # define TIMEN_TIM8 RCC_APB2ENR_TIM8EN # define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR # define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -# define TIMCLK_TIM9 STM32_APB2_TIM9_CLKIN +# define TIMCLK_TIM9 STM32_TIM9_CLKIN # define TIMRCCEN_TIM9 STM32_RCC_APB2ENR # define TIMEN_TIM9 RCC_APB2ENR_TIM9EN # define TIMRCCRST_TIM9 STM32_RCC_APB2RSTR # define TIMRST_TIM9 RCC_APB2RSTR_TIM9RST -# define TIMCLK_TIM10 STM32_APB2_TIM10_CLKIN +# define TIMCLK_TIM10 STM32_TIM10_CLKIN # define TIMRCCEN_TIM10 STM32_RCC_APB2ENR # define TIMEN_TIM10 RCC_APB2ENR_TIM10EN # define TIMRCCRST_TIM10 STM32_RCC_APB2RSTR # define TIMRST_TIM10 RCC_APB2RSTR_TIM10RST -# define TIMCLK_TIM11 STM32_APB2_TIM11_CLKIN +# define TIMCLK_TIM11 STM32_TIM11_CLKIN # define TIMRCCEN_TIM11 STM32_RCC_APB2ENR # define TIMEN_TIM11 RCC_APB2ENR_TIM11EN # define TIMRCCRST_TIM11 STM32_RCC_APB2RSTR # define TIMRST_TIM11 RCC_APB2RSTR_TIM11RST -# define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +# define TIMCLK_TIM12 STM32_TIM12_CLKIN # define TIMRCCEN_TIM12 STM32_RCC_APB1ENR # define TIMEN_TIM12 RCC_APB1ENR_TIM12EN # define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR # define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST -# define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +# define TIMCLK_TIM13 STM32_TIM13_CLKIN # define TIMRCCEN_TIM13 STM32_RCC_APB1ENR # define TIMEN_TIM13 RCC_APB1ENR_TIM13EN # define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR # define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST -# define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +# define TIMCLK_TIM14 STM32_TIM14_CLKIN # define TIMRCCEN_TIM14 STM32_RCC_APB1ENR # define TIMEN_TIM14 RCC_APB1ENR_TIM14EN # define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR # define TIMRST_TIM14 RCC_APB1RSTR_TIM14RST -# define TIMCLK_TIM15 STM32_APB1_TIM15_CLKIN +# define TIMCLK_TIM15 STM32_TIM15_CLKIN # define TIMRCCEN_TIM15 STM32_RCC_APB1ENR # define TIMEN_TIM15 RCC_APB1ENR_TIM15EN # define TIMRCCRST_TIM15 STM32_RCC_APB1RSTR # define TIMRST_TIM15 RCC_APB1RSTR_TIM15RST -# define TIMCLK_TIM16 STM32_APB1_TIM16_CLKIN +# define TIMCLK_TIM16 STM32_TIM16_CLKIN # define TIMRCCEN_TIM16 STM32_RCC_APB1ENR # define TIMEN_TIM16 RCC_APB1ENR_TIM16EN # define TIMRCCRST_TIM16 STM32_RCC_APB1RSTR # define TIMRST_TIM16 RCC_APB1RSTR_TIM16RST -# define TIMCLK_TIM17 STM32_APB1_TIM17_CLKIN +# define TIMCLK_TIM17 STM32_TIM17_CLKIN # define TIMRCCEN_TIM17 STM32_RCC_APB1ENR # define TIMEN_TIM17 RCC_APB1ENR_TIM17EN # define TIMRCCRST_TIM17 STM32_RCC_APB1RSTR diff --git a/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h index 6906d43f07c11..4aacf8eaa525d 100644 --- a/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h @@ -142,27 +142,27 @@ #if defined(CONFIG_STM32_TIM3_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM3_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM4_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM13_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM13_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM13_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM13_CLKIN #elif defined(CONFIG_STM32_TIM14_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM14_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM14_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM14_CLKIN #elif defined(CONFIG_STM32_TIM15_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM15_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN #elif defined(CONFIG_STM32_TIM19_SDADC1) # define SDADC1_HAVE_TIMER 1 # define SDADC1_TIMER_BASE STM32_TIM19_BASE -# define SDADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +# define SDADC1_TIMER_PCLK_FREQUENCY STM32_TIM19_CLKIN #else # undef SDADC1_HAVE_TIMER #endif @@ -180,27 +180,27 @@ #if defined(CONFIG_STM32_TIM2_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM2_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM3_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM4_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM12_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM12_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM12_CLKIN #elif defined(CONFIG_STM32_TIM17_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM17_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM17_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM17_CLKIN #elif defined(CONFIG_STM32_TIM19_SDADC2) # define SDADC2_HAVE_TIMER 1 # define SDADC2_TIMER_BASE STM32_TIM19_BASE -# define SDADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +# define SDADC2_TIMER_PCLK_FREQUENCY STM32_TIM19_CLKIN #else # undef SDADC2_HAVE_TIMER #endif @@ -218,27 +218,27 @@ #if defined(CONFIG_STM32_TIM2_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM2_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM3_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM4_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM12_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM12_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM12_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM12_CLKIN #elif defined(CONFIG_STM32_TIM16_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM16_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM16_CLKIN #elif defined(CONFIG_STM32_TIM19_SDADC3) # define SDADC3_HAVE_TIMER 1 # define SDADC3_TIMER_BASE STM32_TIM19_BASE -# define SDADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM19_CLKIN +# define SDADC3_TIMER_PCLK_FREQUENCY STM32_TIM19_CLKIN #else # undef SDADC3_HAVE_TIMER #endif diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_tim.c similarity index 80% rename from arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c rename to arch/arm/src/common/stm32/stm32_tim.c index 65a9a062d05bd..b531c9f5892e0 100644 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +++ b/arch/arm/src/common/stm32/stm32_tim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c + * arch/arm/src/common/stm32/stm32_tim.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,8 +40,8 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" -#include "stm32_gpio.h" #include "stm32_tim.h" +#include "stm32_tim_clk.h" /**************************************************************************** * Pre-processor Definitions @@ -333,8 +333,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, + uint32_t freq); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, uint32_t count); @@ -364,7 +369,10 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .disable = stm32_tim_disable, .setmode = stm32_tim_setmode, .setclock = stm32_tim_setclock, + .setfreq = stm32_tim_setfreq, + .getclock = stm32_tim_getclock, .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, .getcounter = stm32_tim_getcounter, .setcounter = stm32_tim_setcounter, .getwidth = stm32_tim_getwidth, @@ -376,6 +384,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .disableint = stm32_tim_disableint, .ackint = stm32_tim_ackint, .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32_TIM1 @@ -742,7 +751,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Advanced registers require Main Output Enable */ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -#ifdef STM32_TIM8_BASE +#ifdef CONFIG_STM32_HAVE_TIM8 || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE #endif ) @@ -783,87 +792,87 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; + freqin = STM32_TIM1_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; + freqin = STM32_TIM2_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; + freqin = STM32_TIM3_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; + freqin = STM32_TIM4_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; + freqin = STM32_TIM5_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; + freqin = STM32_TIM6_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; + freqin = STM32_TIM7_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; + freqin = STM32_TIM8_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; + freqin = STM32_TIM9_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; + freqin = STM32_TIM10_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; + freqin = STM32_TIM11_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; + freqin = STM32_TIM12_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; + freqin = STM32_TIM13_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; + freqin = STM32_TIM14_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; + freqin = STM32_TIM15_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; + freqin = STM32_TIM16_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; + freqin = STM32_TIM17_CLKIN; break; #endif @@ -899,6 +908,304 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) return prescaler; } +/**************************************************************************** + * Name: stm32_tim_getclock + ****************************************************************************/ + +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) +{ + uint32_t freqin; + int prescaler; + uint32_t reload; + uint32_t timclk; + + DEBUGASSERT(dev != NULL); + + /* Disable Timer? */ + + if (freq == 0) + { + stm32_tim_disable(dev); + return 0; + } + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_TIM17_CLKIN; + break; +#endif + default: + return -EINVAL; + } + + /* Pick the largest reload and smallest prescaler for the best accuracy */ + + prescaler = (freqin / freq + 65534) / 65535; + if (prescaler < 1) + { + prescaler = 1; + } + + if (prescaler > 65536) + { + prescaler = 65536; + } + + timclk = freqin / prescaler; + + reload = timclk / freq; + if (reload < 1) + { + reload = 1; + } + else if (reload > 65535) + { + reload = 65535; + } + + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); + + return (timclk / reload); +} + +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) +{ + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; + + ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET)); + ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", + stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET)); + ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET)); + ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", + stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET)); + +#if STM32_NATIM > 0 + if (priv->base == STM32_TIM1_BASE +#ifdef CONFIG_STM32_HAVE_TIM8 + || priv->base == STM32_TIM8_BASE +#endif + ) + { + ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", + stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); + } + else +#endif + { + ainfo(" DCR: %04x DMAR: %04x\n", + stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); + } +} + +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) +{ + uint32_t freqin; + uint32_t prescaler; + + DEBUGASSERT(dev != NULL); + + /* Get the input clock frequency for this timer. These vary with + * different timer clock sources, MCU-specific timer configuration, and + * board-specific clock configuration. The correct input clock frequency + * must be defined in the board.h header file. + */ + + switch (((struct stm32_tim_priv_s *)dev)->base) + { +#ifdef CONFIG_STM32_TIM1 + case STM32_TIM1_BASE: + freqin = STM32_TIM1_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case STM32_TIM2_BASE: + freqin = STM32_TIM2_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case STM32_TIM3_BASE: + freqin = STM32_TIM3_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case STM32_TIM4_BASE: + freqin = STM32_TIM4_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case STM32_TIM5_BASE: + freqin = STM32_TIM5_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case STM32_TIM6_BASE: + freqin = STM32_TIM6_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case STM32_TIM7_BASE: + freqin = STM32_TIM7_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case STM32_TIM8_BASE: + freqin = STM32_TIM8_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case STM32_TIM9_BASE: + freqin = STM32_TIM9_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case STM32_TIM10_BASE: + freqin = STM32_TIM10_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case STM32_TIM11_BASE: + freqin = STM32_TIM11_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case STM32_TIM12_BASE: + freqin = STM32_TIM12_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case STM32_TIM13_BASE: + freqin = STM32_TIM13_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case STM32_TIM14_BASE: + freqin = STM32_TIM14_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case STM32_TIM15_BASE: + freqin = STM32_TIM15_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case STM32_TIM16_BASE: + freqin = STM32_TIM16_CLKIN; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case STM32_TIM17_BASE: + freqin = STM32_TIM17_CLKIN; + break; +#endif + + default: + return 0; + } + + prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); + return freqin / (prescaler + 1); +} + /**************************************************************************** * Name: stm32_tim_setperiod ****************************************************************************/ @@ -910,6 +1217,16 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } +/**************************************************************************** + * Name: stm32_tim_getperiod + ****************************************************************************/ + +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + return stm32_getreg32(dev, STM32_GTIM_ARR_OFFSET); +} + /**************************************************************************** * Name: stm32_tim_getcounter ****************************************************************************/ @@ -1723,239 +2040,329 @@ static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) * Pubic Functions ****************************************************************************/ -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ +/* RCC timer-clock gating: the register/bit per timer come from the + * per-family aliases in stm32_tim_rcc.h; the logic below is common. + */ -struct stm32_tim_dev_s *stm32_tim_init(int timer) +static void stm32_tim_enableclk(uint32_t base) { - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) + switch (base) { #ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_TIM1_EN_REG, STM32_RCC_TIM1_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_TIM2_EN_REG, STM32_RCC_TIM2_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_TIM3_EN_REG, STM32_RCC_TIM3_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_TIM4_EN_REG, STM32_RCC_TIM4_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_TIM5_EN_REG, STM32_RCC_TIM5_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_TIM6_EN_REG, STM32_RCC_TIM6_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_TIM7_EN_REG, STM32_RCC_TIM7_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_TIM8_EN_REG, STM32_RCC_TIM8_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM9 - case 9: - dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); + case STM32_TIM9_BASE: + modifyreg32(STM32_RCC_TIM9_EN_REG, STM32_RCC_TIM9_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM10 - case 10: - dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); + case STM32_TIM10_BASE: + modifyreg32(STM32_RCC_TIM10_EN_REG, STM32_RCC_TIM10_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM11 - case 11: - dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); + case STM32_TIM11_BASE: + modifyreg32(STM32_RCC_TIM11_EN_REG, STM32_RCC_TIM11_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); + case STM32_TIM12_BASE: + modifyreg32(STM32_RCC_TIM12_EN_REG, STM32_RCC_TIM12_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); + case STM32_TIM13_BASE: + modifyreg32(STM32_RCC_TIM13_EN_REG, STM32_RCC_TIM13_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); + case STM32_TIM14_BASE: + modifyreg32(STM32_RCC_TIM14_EN_REG, STM32_RCC_TIM14_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_TIM15_EN_REG, STM32_RCC_TIM15_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_TIM16_EN_REG, STM32_RCC_TIM16_EN, 0); break; #endif #ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_TIM17_EN_REG, STM32_RCC_TIM17_EN, 0); break; #endif default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; + break; } - - stm32_tim_reset(dev); - - return dev; } -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +static void stm32_tim_disableclk(uint32_t base) { - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) + switch (base) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + modifyreg32(STM32_RCC_TIM1_EN_REG, 0, STM32_RCC_TIM1_EN); break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + modifyreg32(STM32_RCC_TIM2_EN_REG, 0, STM32_RCC_TIM2_EN); break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + modifyreg32(STM32_RCC_TIM3_EN_REG, 0, STM32_RCC_TIM3_EN); break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + modifyreg32(STM32_RCC_TIM4_EN_REG, 0, STM32_RCC_TIM4_EN); break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + modifyreg32(STM32_RCC_TIM5_EN_REG, 0, STM32_RCC_TIM5_EN); break; #endif #ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); + modifyreg32(STM32_RCC_TIM6_EN_REG, 0, STM32_RCC_TIM6_EN); break; #endif #ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); + modifyreg32(STM32_RCC_TIM7_EN_REG, 0, STM32_RCC_TIM7_EN); break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + modifyreg32(STM32_RCC_TIM8_EN_REG, 0, STM32_RCC_TIM8_EN); break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); + modifyreg32(STM32_RCC_TIM9_EN_REG, 0, STM32_RCC_TIM9_EN); break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); + modifyreg32(STM32_RCC_TIM10_EN_REG, 0, STM32_RCC_TIM10_EN); break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); + modifyreg32(STM32_RCC_TIM11_EN_REG, 0, STM32_RCC_TIM11_EN); break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); + modifyreg32(STM32_RCC_TIM12_EN_REG, 0, STM32_RCC_TIM12_EN); break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); + modifyreg32(STM32_RCC_TIM13_EN_REG, 0, STM32_RCC_TIM13_EN); break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); + modifyreg32(STM32_RCC_TIM14_EN_REG, 0, STM32_RCC_TIM14_EN); break; #endif #ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + modifyreg32(STM32_RCC_TIM15_EN_REG, 0, STM32_RCC_TIM15_EN); break; #endif #ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + modifyreg32(STM32_RCC_TIM16_EN_REG, 0, STM32_RCC_TIM16_EN); break; #endif #ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + modifyreg32(STM32_RCC_TIM17_EN_REG, 0, STM32_RCC_TIM17_EN); break; #endif default: - return -EINVAL; + break; } +} + +/**************************************************************************** + * Name: stm32_tim_init + ****************************************************************************/ + +struct stm32_tim_dev_s *stm32_tim_init(int timer) +{ + struct stm32_tim_dev_s *dev = NULL; + + /* Get structure and enable power */ + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1 + case 1: + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM2 + case 2: + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM3 + case 3: + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM4 + case 4: + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM5 + case 5: + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM6 + case 6: + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM7 + case 7: + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM8 + case 8: + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM9 + case 9: + dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM12 + case 12: + dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM13 + case 13: + dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM14 + case 14: + dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM15 + case 15: + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM16 + case 16: + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; + break; +#endif +#ifdef CONFIG_STM32_TIM17 + case 17: + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; + break; +#endif + default: + return NULL; + } + + /* Is device already allocated */ + + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + { + return NULL; + } + + /* Enable the timer's RCC clock (family-specific) */ + + stm32_tim_enableclk(((struct stm32_tim_priv_s *)dev)->base); + + stm32_tim_reset(dev); + + return dev; +} + +/**************************************************************************** + * Name: stm32_tim_deinit + * + * TODO: Detach interrupts, and close down all TIM Channels + * + ****************************************************************************/ + +int stm32_tim_deinit(struct stm32_tim_dev_s * dev) +{ + DEBUGASSERT(dev != NULL); + + /* Disable the timer's RCC clock (family-specific) */ + + stm32_tim_disableclk(((struct stm32_tim_priv_s *)dev)->base); /* Mark it as free */ diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h index 77d884e06727a..60c26af45edbf 100644 --- a/arch/arm/src/common/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H -#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H /**************************************************************************** * Included Files @@ -29,14 +29,204 @@ #include -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) -# include "stm32_tim_m0_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) -# include "stm32_tim_m3m4_v1v2v3.h" +#include "chip.h" + +/* This is the common STM32 timer API, shared by every family. The timer + * register layouts differ between families, so the concrete hardware header + * is selected here while the programming model below stays the same. + */ + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "hardware/stm32_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L4) +# include "hardware/stm32l4_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L5) +# include "hardware/stm32l5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32WL5) +# include "hardware/stm32wl5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F7) +# include "hardware/stm32f7_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32H7) +# include "hardware/stm32h7_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32H5) +# include "hardware/stm32h5_tim.h" +#elif defined(CONFIG_ARCH_CHIP_STM32U5) +# include "hardware/stm32u5_tim.h" +#endif + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ #else -# error "Unsupported STM32 TIM" +#define EXTERN extern +#endif + +/* TIM Device Structure */ + +struct stm32_tim_dev_s +{ + struct stm32_tim_ops_s *ops; +}; + +/* TIM Modes of Operation */ + +typedef enum stm32_tim_mode_e +{ + STM32_TIM_MODE_UNUSED = -1, + + /* One of the following */ + + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, + + /* One of the following */ + + STM32_TIM_MODE_CK_INT = 0x0000, +} stm32_tim_mode_t; + +/* TIM Channel Modes */ + +typedef enum stm32_tim_channel_e +{ + STM32_TIM_CH_DISABLED = 0x00, + + /* Common configuration */ + + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, + + /* MODES: */ + + STM32_TIM_CH_MODE_MASK = 0x0e, + + /* Output Compare Modes */ + + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTTOGGLE = 0x08, /* Toggle TIM_CHx output on update event */ +} stm32_tim_channel_t; + +/* TIM Operations */ + +struct stm32_tim_ops_s +{ + /* Basic Timers */ + + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); + + /* General and Advanced Timers Adds */ + + int (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); + + /* Timer interrupts */ + + int (*setisr)(struct stm32_tim_dev_s *dev, + xcpt_t handler, void * arg, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); + + /* Debug */ + + void (*dump_regs)(struct stm32_tim_dev_s *dev); +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/* Power-up timer and get its structure */ + +struct stm32_tim_dev_s *stm32_tim_init(int timer); + +/* Power-down timer, mark it as unused */ + +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); + +/**************************************************************************** + * Name: stm32_timer_initialize + * + * Description: + * Bind the configuration timer to a timer lower half instance and + * register the timer drivers at 'devpath' + * + * Input Parameters: + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 + * timer - the timer number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_TIMER +int stm32_timer_initialize(const char *devpath, int timer); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} #endif -#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_clk.h b/arch/arm/src/common/stm32/stm32_tim_clk.h new file mode 100644 index 0000000000000..afbcb7bd24627 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim_clk.h @@ -0,0 +1,260 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim_clk.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H + +/* Per-family RCC clock-enable aliases for the common timer driver. Only the + * timer RCC clock-enable register/bit differs between families; the timer + * input clock is provided uniformly by each board as STM32_TIMn_CLKIN. + */ + +#include + +#include "stm32.h" + +#if defined(CONFIG_ARCH_CHIP_STM32H7) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32F7) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +#elif defined(CONFIG_ARCH_CHIP_STM32H5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR +# define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32U5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32L5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32WL5) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32L4) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#elif defined(CONFIG_ARCH_CHIP_STM32WB) +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 +# define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#else /* Classic M3/M4 (and M0) layout: APB1ENR/APB2ENR */ +# define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR +# define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +# define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR +# define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_lowerhalf.c similarity index 89% rename from arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_lowerhalf.c index 356a3e9e6c782..fab9090a6690f 100644 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_lowerhalf.c @@ -1,11 +1,14 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. + * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. + * SPDX-FileCopyrightText: 2016 Sebastien Lorquet All rights reserved. * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato * SPDX-FileContributor: Wail Khemir * SPDX-FileContributor: Paul Alexander Patience + * SPDX-FileContributor: Daniel Pereira Volpato * SPDX-FileContributor: dev@ziggurat29.com * SPDX-FileContributor: Sebastien Lorquet * @@ -65,19 +68,39 @@ defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* The timer counter width (16 or 32 bits). TIM2 and TIM5 are 32-bit on + * most families; the STM32_HAVE_TIMn_32BITS capability flags carry that + * per-family knowledge instead of chip-line #ifdefs. Every other timer is + * 16-bit. + */ + #define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 16 + +#ifdef CONFIG_STM32_HAVE_TIM2_32BITS +# define STM32_TIM2_RES 32 +#else +# define STM32_TIM2_RES 16 +#endif + #define STM32_TIM3_RES 16 #define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 16 + +#ifdef CONFIG_STM32_HAVE_TIM5_32BITS +# define STM32_TIM5_RES 32 +#else +# define STM32_TIM5_RES 16 +#endif + #define STM32_TIM6_RES 16 #define STM32_TIM7_RES 16 #define STM32_TIM8_RES 16 @@ -207,6 +230,30 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif +#ifdef CONFIG_STM32_TIM9 +static struct stm32_lowerhalf_s g_tim9_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM9_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM10 +static struct stm32_lowerhalf_s g_tim10_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM10_RES, +}; +#endif + +#ifdef CONFIG_STM32_TIM11 +static struct stm32_lowerhalf_s g_tim11_lowerhalf = +{ + .ops = &g_timer_ops, + .resolution = STM32_TIM11_RES, +}; +#endif + #ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { @@ -276,7 +323,7 @@ static int stm32_timer_handler(int irq, void * context, void * arg) struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { @@ -321,7 +368,7 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -355,7 +402,7 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; @@ -438,8 +485,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, * Set a new timeout value (and reset the timer) * * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. * timeout - The new timeout value in microseconds. * * Returned Value: @@ -518,11 +565,11 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } @@ -554,6 +601,7 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, int stm32_timer_initialize(const char *devpath, int timer) { struct stm32_lowerhalf_s *lower; + void *drvr; tmrinfo("Init TIM%d\n", timer); @@ -599,6 +647,21 @@ int stm32_timer_initialize(const char *devpath, int timer) lower = &g_tim8_lowerhalf; break; #endif +#ifdef CONFIG_STM32_TIM9 + case 9: + lower = &g_tim9_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM10 + case 10: + lower = &g_tim10_lowerhalf; + break; +#endif +#ifdef CONFIG_STM32_TIM11 + case 11: + lower = &g_tim11_lowerhalf; + break; +#endif #ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; @@ -649,8 +712,7 @@ int stm32_timer_initialize(const char *devpath, int timer) * REVISIT: The returned handle is discard here. */ - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); + drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower); if (drvr == NULL) { /* The actual cause of the failure may have been a failure to allocate diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c deleted file mode 100644 index 9401a884a27c0..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1.c +++ /dev/null @@ -1,1502 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM - * may also be defined to indicate that the timer is intended to be used - * for pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ - defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ - defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ - defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ - defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ - defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ - defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ - defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ - defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, - uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, - void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .getclock = &stm32_tim_getclock, - .setperiod = &stm32_tim_setperiod, - .getperiod = &stm32_tim_getperiod, - .getcounter = &stm32_tim_getcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM6_GPIOCONFIG) || \ - defined(HAVE_TIM7_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM12_GPIOCONFIG) || defined(HAVE_TIM13_GPIOCONFIG) || \ - defined(HAVE_TIM14_GPIOCONFIG) || defined(HAVE_TIM15_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - tmrinfo("Set clock=%" PRId32 "\n", freq); - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB2_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - tmrinfo(" timer freq=%" PRId32 "\n", freqin); - tmrinfo(" prescaler=%d\n", prescaler); - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - tmrinfo(" prescaler (adjusted)=%d\n", prescaler); - - /* PSC_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - uint32_t prescaler; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB2_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - prescaler = stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET); - clock = freqin / (prescaler + 1); - return clock; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - tmrinfo("Set period=%" PRId32 "\n", period); - DEBUGASSERT(dev != NULL); - - /* ARR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - -#ifdef HAVE_TIM2_32BIT - /* TIM2 is 16-bit on L0 */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return 32; - } -#endif - - /* All other timers are 16-bit */ - - return 16; -} - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - tmrinfo("Set ISR\n"); - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_BRK; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - - /* DIER_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - /* SR_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - tmrinfo("Set mode=%d\n", mode); - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - - /* CR1_OFFSET is the same for ATIM, BTIM or GTIM */ - - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -# if defined(CONFIG_STM32_TIM8) - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE -# endif - ) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */ - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - - /* CCER_OFFSET and CCMR1_OFFSET are the same for ATIM and GTIM */ - - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#ifdef STM32_TIM6_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE) - { - return -EINVAL; - } -#endif - -#ifdef STM32_TIM7_BASE - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m0_v1.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h deleted file mode 100644 index 07c0ef1f7e592..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m0_v1.h +++ /dev/null @@ -1,233 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m0_v1.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. - * SPDX-FileContributor: Daniel Pereira Volpato - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* TODO external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - int (*getwidth)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h deleted file mode 100644 index 9bd99fb862f29..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H -#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, - - /* STM32_TIM_MODE_CK_INT_TRIG = 0x0400, */ - - /* STM32_TIM_MODE_CK_EXT = 0x0800, */ - - /* STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00, */ - - /* Clock sources, OR'ed with CK_EXT */ - - /* STM32_TIM_MODE_CK_CHINVALID = 0x0000, */ - - /* STM32_TIM_MODE_CK_CH1 = 0x0001, */ - - /* STM32_TIM_MODE_CK_CH2 = 0x0002, */ - - /* STM32_TIM_MODE_CK_CH3 = 0x0003, */ - - /* STM32_TIM_MODE_CK_CH4 = 0x0004 */ - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ - - /* STM32_TIM_CH_OUTCOMPARE = 0x06, */ - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - /* STM32_TIM_CH_INCAPTURE = 0x10, */ - - /* STM32_TIM_CH_INPWM = 0x20 */ - - /* STM32_TIM_CH_DRIVE_OC -- open collector mode */ -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void * arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. - * This should be of the form /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c deleted file mode 100644 index 25d5b63192639..0000000000000 --- a/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c +++ /dev/null @@ -1,588 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32c0/stm32.h b/arch/arm/src/stm32c0/stm32.h index b12ea4f456513..7d1c5ae34764f 100644 --- a/arch/arm/src/stm32c0/stm32.h +++ b/arch/arm/src/stm32c0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f0/stm32.h b/arch/arm/src/stm32f0/stm32.h index bd3ce82e9d74e..fabdd48a6255b 100644 --- a/arch/arm/src/stm32f0/stm32.h +++ b/arch/arm/src/stm32f0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32f1/stm32.h b/arch/arm/src/stm32f1/stm32.h index 5707089d7b890..8b2f3364b1878 100644 --- a/arch/arm/src/stm32f1/stm32.h +++ b/arch/arm/src/stm32f1/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig index 139cff56f9059..0a81ba511e513 100644 --- a/arch/arm/src/stm32f2/Kconfig +++ b/arch/arm/src/stm32f2/Kconfig @@ -162,6 +162,8 @@ config STM32_STM32F20XX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f2/stm32.h b/arch/arm/src/stm32f2/stm32.h index 9069ebcbca61e..6563efa5ae627 100644 --- a/arch/arm/src/stm32f2/stm32.h +++ b/arch/arm/src/stm32f2/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig index ace83673f311d..44e7612000d59 100644 --- a/arch/arm/src/stm32f3/Kconfig +++ b/arch/arm/src/stm32f3/Kconfig @@ -445,6 +445,7 @@ config STM32_STM32F30XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -534,6 +535,7 @@ config STM32_STM32F33XX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_IP_USART_V3 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS @@ -578,6 +580,8 @@ config STM32_STM32F37XX select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM select STM32_HAVE_IP_CRYPTO_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_ADC_M3M4_V1_BASIC select STM32_HAVE_COMMON_FOC select STM32_HAVE_IP_DCMI_V1 diff --git a/arch/arm/src/stm32f3/stm32.h b/arch/arm/src/stm32f3/stm32.h index f7eb0f45c819d..4999babf72256 100644 --- a/arch/arm/src/stm32f3/stm32.h +++ b/arch/arm/src/stm32f3/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig index 698e52b602f85..6eeb7ef4a9e43 100644 --- a/arch/arm/src/stm32f4/Kconfig +++ b/arch/arm/src/stm32f4/Kconfig @@ -276,6 +276,8 @@ config STM32_STM32F4XXX select STM32_HAVE_IP_SPI_V2 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32f4/stm32.h b/arch/arm/src/stm32f4/stm32.h index 56a9dbc8151a7..ec4aa1768ed7d 100644 --- a/arch/arm/src/stm32f4/stm32.h +++ b/arch/arm/src/stm32f4/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 518e0b6997f0e..f8fae791d2ade 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -119,7 +119,7 @@ if(CONFIG_USBHOST) endif() if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) + list(APPEND SRCS) endif() if(CONFIG_STM32_ADC) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index c1d9712cd83dc..918079d37a1a5 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -647,9 +647,11 @@ config STM32_STM32F72XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -666,9 +668,11 @@ config STM32_STM32F73XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -685,9 +689,11 @@ config STM32_STM32F74XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -704,9 +710,11 @@ config STM32_STM32F75XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -723,9 +731,11 @@ config STM32_STM32F76XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -742,9 +752,11 @@ config STM32_STM32F77XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index b10e4068ae5b7..7f0dbeb3e9297 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -120,7 +120,7 @@ endif endif ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c +CHIP_CSRCS += endif ifeq ($(CONFIG_STM32_ADC),y) diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32f7_tim.h similarity index 97% rename from arch/arm/src/stm32f7/hardware/stm32_tim.h rename to arch/arm/src/stm32f7/hardware/stm32f7_tim.h index 6dfc200978cb5..41c96becc5e10 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f7_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f7/hardware/stm32_tim.h + * arch/arm/src/stm32f7/hardware/stm32f7_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f7/stm32.h b/arch/arm/src/stm32f7/stm32.h index 99c030c63377e..9f45242187e4b 100644 --- a/arch/arm/src/stm32f7/stm32.h +++ b/arch/arm/src/stm32f7/stm32.h @@ -52,7 +52,6 @@ #include "stm32_sdmmc.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_ethernet.h" diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index 58b2aff989260..867966ee49196 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -152,31 +152,31 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #else # undef ADC1_HAVE_TIMER #endif @@ -194,31 +194,31 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #else # undef ADC2_HAVE_TIMER #endif @@ -236,27 +236,27 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN #elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM5_CLKIN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #else # undef ADC3_HAVE_TIMER #endif diff --git a/arch/arm/src/stm32f7/stm32_capture.h b/arch/arm/src/stm32f7/stm32_capture.h index e5614788cb29c..3aca5ecbb70d9 100644 --- a/arch/arm/src/stm32f7/stm32_capture.h +++ b/arch/arm/src/stm32f7/stm32_capture.h @@ -31,7 +31,7 @@ #include "chip.h" #include -#include "hardware/stm32_tim.h" +#include "hardware/stm32f7_tim.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index 1494220031ae0..1d7edacc121bd 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -82,62 +82,62 @@ * RCC RST offset, reset bit to use */ -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +#define TIMCLK_TIM1 STM32_TIM1_CLKIN #define TIMRCCEN_TIM1 STM32_RCC_APB2ENR #define TIMEN_TIM1 RCC_APB2ENR_TIM1EN #define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR #define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +#define TIMCLK_TIM2 STM32_TIM2_CLKIN #define TIMRCCEN_TIM2 STM32_RCC_APB1ENR #define TIMEN_TIM2 RCC_APB1ENR_TIM2EN #define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR #define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST -#define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +#define TIMCLK_TIM3 STM32_TIM3_CLKIN #define TIMRCCEN_TIM3 STM32_RCC_APB1ENR #define TIMEN_TIM3 RCC_APB1ENR_TIM3EN #define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR #define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST -#define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +#define TIMCLK_TIM4 STM32_TIM4_CLKIN #define TIMRCCEN_TIM4 STM32_RCC_APB1ENR #define TIMEN_TIM4 RCC_APB1ENR_TIM4EN #define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR #define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST -#define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +#define TIMCLK_TIM5 STM32_TIM5_CLKIN #define TIMRCCEN_TIM5 STM32_RCC_APB1ENR #define TIMEN_TIM5 RCC_APB1ENR_TIM5EN #define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR #define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +#define TIMCLK_TIM8 STM32_TIM8_CLKIN #define TIMRCCEN_TIM8 STM32_RCC_APB2ENR #define TIMEN_TIM8 RCC_APB2ENR_TIM8EN #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -#define TIMCLK_TIM9 STM32_APB2_TIM9_CLKIN +#define TIMCLK_TIM9 STM32_TIM9_CLKIN #define TIMRCCEN_TIM9 STM32_RCC_APB2ENR #define TIMEN_TIM9 RCC_APB2ENR_TIM9EN #define TIMRCCRST_TIM9 STM32_RCC_APB2RSTR #define TIMRST_TIM9 RCC_APB2RSTR_TIM9RST -#define TIMCLK_TIM10 STM32_APB2_TIM10_CLKIN +#define TIMCLK_TIM10 STM32_TIM10_CLKIN #define TIMRCCEN_TIM10 STM32_RCC_APB2ENR #define TIMEN_TIM10 RCC_APB2ENR_TIM10EN #define TIMRCCRST_TIM10 STM32_RCC_APB2RSTR #define TIMRST_TIM10 RCC_APB2RSTR_TIM10RST -#define TIMCLK_TIM11 STM32_APB2_TIM11_CLKIN +#define TIMCLK_TIM11 STM32_TIM11_CLKIN #define TIMRCCEN_TIM11 STM32_RCC_APB2ENR #define TIMEN_TIM11 RCC_APB2ENR_TIM11EN #define TIMRCCRST_TIM11 STM32_RCC_APB2RSTR #define TIMRST_TIM11 RCC_APB2RSTR_TIM11RST -#define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +#define TIMCLK_TIM12 STM32_TIM12_CLKIN #define TIMRCCEN_TIM12 STM32_RCC_APB1ENR #define TIMEN_TIM12 RCC_APB1ENR_TIM12EN #define TIMRCCRST_TIM12 STM32_RCC_APB1RSTR #define TIMRST_TIM12 RCC_APB1RSTR_TIM12RST -#define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +#define TIMCLK_TIM13 STM32_TIM13_CLKIN #define TIMRCCEN_TIM13 STM32_RCC_APB1ENR #define TIMEN_TIM13 RCC_APB1ENR_TIM13EN #define TIMRCCRST_TIM13 STM32_RCC_APB1RSTR #define TIMRST_TIM13 RCC_APB1RSTR_TIM13RST -#define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +#define TIMCLK_TIM14 STM32_TIM14_CLKIN #define TIMRCCEN_TIM14 STM32_RCC_APB1ENR #define TIMEN_TIM14 RCC_APB1ENR_TIM14EN #define TIMRCCRST_TIM14 STM32_RCC_APB1RSTR diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 0aa3aed6d7143..9843953f65bce 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32f7_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c deleted file mode 100644 index b69490b7e4666..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ /dev/null @@ -1,1572 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer - * "n" is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif -#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32_TIM9_ADC) || \ - defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32_TIM9_QE) -# undef CONFIG_STM32_TIM9 -#endif -#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32_TIM10_ADC) || \ - defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32_TIM10_QE) -# undef CONFIG_STM32_TIM10 -#endif -#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32_TIM11_ADC) || \ - defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32_TIM11_QE) -# undef CONFIG_STM32_TIM11 -#endif -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif -#if defined(CONFIG_STM32_TIM9) -# if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ - defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) -# define HAVE_TIM9_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM10) -# if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ - defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) -# define HAVE_TIM10_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM11) -# if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ - defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) -# define HAVE_TIM11_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ - defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ - defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ - defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, - uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, - clearbits, setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, - uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width - * - * Reference Table 2 of en.DM00042534.pdf - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { - /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ - -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - - /* TIM5 is 32-bits on all except F10x lines */ - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_GTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_GTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, - * but do not affect output/input pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - vectorno = STM32_IRQ_TIM9; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - vectorno = STM32_IRQ_TIM10; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - vectorno = STM32_IRQ_TIM11; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - val |= GTIM_CR1_CENTER1; - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -# ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - switch (channel) - { -# if defined(GPIO_TIM9_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM9_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM9_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM9_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - switch (channel) - { -# if defined(GPIO_TIM10_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM10_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM10_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM10_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM10_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM10_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - switch (channel) - { -# if defined(GPIO_TIM11_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM11_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM11_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM11_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM11_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM11_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM12_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM12_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM13_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM13_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM13_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM13_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM14_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM14_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM14_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM14_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, - uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Advanced Functions - ****************************************************************************/ - -/* TODO: Advanced functions for the STM32_ATIM */ - -/**************************************************************************** - * Device Structures, Instantiation - ****************************************************************************/ - -struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .setperiod = stm32_tim_setperiod, - .getcounter = stm32_tim_getcounter, - .setcounter = stm32_tim_setcounter, - .getwidth = stm32_tim_getwidth, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -struct stm32_tim_priv_s stm32_tim9_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM9_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -struct stm32_tim_priv_s stm32_tim10_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM10_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -struct stm32_tim_priv_s stm32_tim11_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM11_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -/**************************************************************************** - * Public Function - Initialization - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h deleted file mode 100644 index e09b9b569b585..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim.h +++ /dev/null @@ -1,221 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F7_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, /* TODO: Not supported */ - STM32_TIM_MODE_CK_EXT = 0x0800, /* TODO: Not supported */ - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, /* TODO: Not supported */ -#endif - - /* Clock sources, OR'ed with CK_EXT */ -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH1 = 0x0001, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH2 = 0x0002, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH3 = 0x0003, /* TODO: Not supported */ - STM32_TIM_MODE_CK_CH4 = 0x0004 /* TODO: Not supported */ -#endif - - /* TODO: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, /* TODO: Not supported */ -#endif - STM32_TIM_CH_OUTTOGGLE = 0x08, - -#if 0 - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC /* -- open collector mode */ -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, - void * arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c deleted file mode 100644 index 1005d174f7569..0000000000000 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,591 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) -# define STM32_TIM2_RES 16 -#else -# define STM32_TIM2_RES 32 -#endif - -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# define STM32_TIM5_RES 16 -#else -# define STM32_TIM5_RES 32 -#endif - -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback. - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h index 243e25e7d3915..9e70f1bf95f02 100644 --- a/arch/arm/src/stm32g0/stm32.h +++ b/arch/arm/src/stm32g0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig index b46ea854ddfe0..d4b3a6c721384 100644 --- a/arch/arm/src/stm32g4/Kconfig +++ b/arch/arm/src/stm32g4/Kconfig @@ -127,6 +127,8 @@ config STM32_STM32G4XXX select STM32_HAVE_IP_SPI_V3 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V4 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32g4/stm32.h b/arch/arm/src/stm32g4/stm32.h index 07776d682753f..b87f810ac7d80 100644 --- a/arch/arm/src/stm32g4/stm32.h +++ b/arch/arm/src/stm32g4/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 8d6fa1308f51e..02b9e0419e355 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -50,10 +50,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() @@ -83,7 +79,7 @@ if(CONFIG_STM32_QSPI1) endif() if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c) + list(APPEND SRCS) endif() if(CONFIG_STM32_HAVE_HSI48) diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 002e693e1a9ec..90b79759b8ff3 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -65,9 +65,11 @@ config STM32_STM32H56XXX select STM32_HAVE_IP_CORDIC_M3M4_V1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index e48727247eee3..beda69592fe85 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -48,10 +48,6 @@ ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif @@ -81,7 +77,7 @@ CHIP_CSRCS += stm32_qspi.c endif ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c +CHIP_CSRCS += endif ifeq ($(CONFIG_STM32_HAVE_HSI48),y) diff --git a/arch/arm/src/stm32h5/hardware/stm32_tim.h b/arch/arm/src/stm32h5/hardware/stm32h5_tim.h similarity index 99% rename from arch/arm/src/stm32h5/hardware/stm32_tim.h rename to arch/arm/src/stm32h5/hardware/stm32h5_tim.h index 58b92a9174859..a0b617810d172 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h5/hardware/stm32_tim.h + * arch/arm/src/stm32h5/hardware/stm32h5_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32h5/stm32.h b/arch/arm/src/stm32h5/stm32.h index 25d810170aae5..7011cf4f5d2ee 100644 --- a/arch/arm/src/stm32h5/stm32.h +++ b/arch/arm/src/stm32h5/stm32.h @@ -47,7 +47,6 @@ #include "stm32_lowputc.h" #include "stm32_pwr.h" #include "stm32_rcc.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_usbfs.h" diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index ec1aca6e19b41..4985f50bed299 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -139,43 +139,43 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN #elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN #elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN #elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN #elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM15EN #else @@ -195,43 +195,43 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN #elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN #elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN #elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN #elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN #elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM15EN #else diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index 1caf1ddc04bb3..43848bae35b04 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -88,62 +88,62 @@ * TODO: simplify this and move somewhere else. */ -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +#define TIMCLK_TIM1 STM32_TIM1_CLKIN #define TIMRCCEN_TIM1 STM32_RCC_APB2ENR #define TIMEN_TIM1 RCC_APB2ENR_TIM1EN #define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR #define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +#define TIMCLK_TIM2 STM32_TIM2_CLKIN #define TIMRCCEN_TIM2 STM32_RCC_APB1LENR #define TIMEN_TIM2 RCC_APB1LENR_TIM2EN #define TIMRCCRST_TIM2 STM32_RCC_APB1LRSTR #define TIMRST_TIM2 RCC_APB1LRSTR_TIM2RST -#define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +#define TIMCLK_TIM3 STM32_TIM3_CLKIN #define TIMRCCEN_TIM3 STM32_RCC_APB1LENR #define TIMEN_TIM3 RCC_APB1LENR_TIM3EN #define TIMRCCRST_TIM3 STM32_RCC_APB1LRSTR #define TIMRST_TIM3 RCC_APB1LRSTR_TIM3RST -#define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +#define TIMCLK_TIM4 STM32_TIM4_CLKIN #define TIMRCCEN_TIM4 STM32_RCC_APB1LENR #define TIMEN_TIM4 RCC_APB1LENR_TIM4EN #define TIMRCCRST_TIM4 STM32_RCC_APB1LRSTR #define TIMRST_TIM4 RCC_APB1LRSTR_TIM4RST -#define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +#define TIMCLK_TIM5 STM32_TIM5_CLKIN #define TIMRCCEN_TIM5 STM32_RCC_APB1LENR #define TIMEN_TIM5 RCC_APB1LENR_TIM5EN #define TIMRCCRST_TIM5 STM32_RCC_APB1LRSTR #define TIMRST_TIM5 RCC_APB1LRSTR_TIM5RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +#define TIMCLK_TIM8 STM32_TIM8_CLKIN #define TIMRCCEN_TIM8 STM32_RCC_APB2ENR #define TIMEN_TIM8 RCC_APB2ENR_TIM8EN #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -#define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +#define TIMCLK_TIM12 STM32_TIM12_CLKIN #define TIMRCCEN_TIM12 STM32_RCC_APB1LENR #define TIMEN_TIM12 RCC_APB1LENR_TIM12EN #define TIMRCCRST_TIM12 STM32_RCC_APB1LRSTR #define TIMRST_TIM12 RCC_APB1LRSTR_TIM12RST -#define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +#define TIMCLK_TIM13 STM32_TIM13_CLKIN #define TIMRCCEN_TIM13 STM32_RCC_APB1LENR #define TIMEN_TIM13 RCC_APB1LENR_TIM13EN #define TIMRCCRST_TIM13 STM32_RCC_APB1LRSTR #define TIMRST_TIM13 RCC_APB1LRSTR_TIM13RST -#define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +#define TIMCLK_TIM14 STM32_TIM14_CLKIN #define TIMRCCEN_TIM14 STM32_RCC_APB1LENR #define TIMEN_TIM14 RCC_APB1LENR_TIM14EN #define TIMRCCRST_TIM14 STM32_RCC_APB1LRSTR #define TIMRST_TIM14 RCC_APB1LRSTR_TIM14RST -#define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +#define TIMCLK_TIM15 STM32_TIM15_CLKIN #define TIMRCCEN_TIM15 STM32_RCC_APB2ENR #define TIMEN_TIM15 RCC_APB2ENR_TIM15EN #define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR #define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST -#define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +#define TIMCLK_TIM16 STM32_TIM16_CLKIN #define TIMRCCEN_TIM16 STM32_RCC_APB2ENR #define TIMEN_TIM16 RCC_APB2ENR_TIM16EN #define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR #define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST -#define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +#define TIMCLK_TIM17 STM32_TIM17_CLKIN #define TIMRCCEN_TIM17 STM32_RCC_APB2ENR #define TIMEN_TIM17 RCC_APB2ENR_TIM17EN #define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index 138d2ad573b13..445511f9d177b 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32h5_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c deleted file mode 100644 index 555afe3c72d74..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ /dev/null @@ -1,1553 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ - defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ - defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer methods */ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .setperiod = &stm32_tim_setperiod, - .getcounter = &stm32_tim_getcounter, - .setcounter = &stm32_tim_setcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint, - .checkint = &stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM6_GPIOCONFIG)||\ - defined(HAVE_TIM7_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)||\ - defined(HAVE_TIM12_GPIOCONFIG)||defined(HAVE_TIM13_GPIOCONFIG)||\ - defined(HAVE_TIM14_GPIOCONFIG)||defined(HAVE_TIM15_GPIOCONFIG)||\ - defined(HAVE_TIM16_GPIOCONFIG)||defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1_UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8_UP; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT); - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h5/stm32_tim.h b/arch/arm/src/stm32h5/stm32_tim.h deleted file mode 100644 index b571fcb7159ba..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim.h +++ /dev/null @@ -1,223 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32H5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, - - /* Clock sources, OR'ed with CK_EXT */ - - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - /* Enable standard PWM mode, active high when counter < compare */ - - STM32_TIM_CH_OUTPWM = 0x04, - - /* Toggle TIM_CHx output on UEV */ - - STM32_TIM_CH_OUTTOGGLE = 0x08, -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC - open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c deleted file mode 100644 index d0a77244157be..0000000000000 --- a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,586 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h5/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2023 Max Kriegleder. All rights reserved. - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: Max Kriegleder - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 56808e63dc5b5..22ce914736dd2 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -137,10 +137,6 @@ if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -169,7 +165,7 @@ if(CONFIG_USBHOST) endif() if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c) + list(APPEND SRCS) endif() if(CONFIG_STM32_LPTIM) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 17a8fc57014c3..7320fcfbe8918 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -521,9 +521,11 @@ config STM32_STM32H7X0XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -552,9 +554,11 @@ config STM32_STM32H7X3XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -581,9 +585,11 @@ config STM32_STM32H7B3XX select ARCH_HAVE_DPFPU select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -612,9 +618,11 @@ config STM32_STM32H7X5XX select STM32_HAVE_FDCAN2 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 @@ -643,9 +651,11 @@ config STM32_STM32H7X7XX select ARCH_HAVE_DPFPU select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index e08ef3619cea3..994875de36094 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -136,10 +136,6 @@ ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -168,7 +164,7 @@ endif endif ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c +CHIP_CSRCS += endif ifeq ($(CONFIG_STM32_LPTIM),y) diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32h7_tim.h similarity index 99% rename from arch/arm/src/stm32h7/hardware/stm32_tim.h rename to arch/arm/src/stm32h7/hardware/stm32h7_tim.h index d50bedadd0830..790157d0a0412 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/hardware/stm32_tim.h + * arch/arm/src/stm32h7/hardware/stm32h7_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32h7/stm32.h b/arch/arm/src/stm32h7/stm32.h index a6d99c1774357..fa614de2da3d9 100644 --- a/arch/arm/src/stm32h7/stm32.h +++ b/arch/arm/src/stm32h7/stm32.h @@ -43,7 +43,6 @@ #include "stm32_i2c.h" #include "stm32_spi.h" #include "stm32_rcc.h" -#include "stm32_tim.h" #include "stm32_lowputc.h" #endif /* __ARCH_ARM_SRC_STM32H7_STM32_H */ diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index a22ebb45e0cff..0944fff6db255 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -157,43 +157,43 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN #elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN #elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN #elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN #elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM15EN #else @@ -213,43 +213,43 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN #elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN #elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN #elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN #elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN #elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM15EN #else @@ -269,43 +269,43 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM1EN #elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM2EN #elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM3EN #elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM4EN #elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM6EN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM8EN #elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM15EN #else diff --git a/arch/arm/src/stm32h7/stm32_capture.c b/arch/arm/src/stm32h7/stm32_capture.c index 32ef41e9d9cac..8da02961672dc 100644 --- a/arch/arm/src/stm32h7/stm32_capture.c +++ b/arch/arm/src/stm32h7/stm32_capture.c @@ -746,62 +746,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; + freqin = STM32_TIM1_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; + freqin = STM32_TIM2_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; + freqin = STM32_TIM3_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; + freqin = STM32_TIM4_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; + freqin = STM32_TIM5_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; + freqin = STM32_TIM8_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - freqin = STM32_APB2_TIM9_CLKIN; + freqin = STM32_TIM9_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - freqin = STM32_APB2_TIM10_CLKIN; + freqin = STM32_TIM10_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - freqin = STM32_APB2_TIM11_CLKIN; + freqin = STM32_TIM11_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; + freqin = STM32_TIM12_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; + freqin = STM32_TIM13_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; + freqin = STM32_TIM14_CLKIN; break; #endif diff --git a/arch/arm/src/stm32h7/stm32_capture.h b/arch/arm/src/stm32h7/stm32_capture.h index 89d09b5c5f4e9..b11ec5c1416e1 100644 --- a/arch/arm/src/stm32h7/stm32_capture.h +++ b/arch/arm/src/stm32h7/stm32_capture.h @@ -31,7 +31,7 @@ #include "chip.h" #include -#include "hardware/stm32_tim.h" +#include "hardware/stm32h7_tim.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index 70b434b741b99..95b095fc1ea7a 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -90,62 +90,62 @@ * TODO: simplify this and move somewhere else. */ -#define TIMCLK_TIM1 STM32_APB2_TIM1_CLKIN +#define TIMCLK_TIM1 STM32_TIM1_CLKIN #define TIMRCCEN_TIM1 STM32_RCC_APB2ENR #define TIMEN_TIM1 RCC_APB2ENR_TIM1EN #define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR #define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST -#define TIMCLK_TIM2 STM32_APB1_TIM2_CLKIN +#define TIMCLK_TIM2 STM32_TIM2_CLKIN #define TIMRCCEN_TIM2 STM32_RCC_APB1LENR #define TIMEN_TIM2 RCC_APB1LENR_TIM2EN #define TIMRCCRST_TIM2 STM32_RCC_APB1LRSTR #define TIMRST_TIM2 RCC_APB1LRSTR_TIM2RST -#define TIMCLK_TIM3 STM32_APB1_TIM3_CLKIN +#define TIMCLK_TIM3 STM32_TIM3_CLKIN #define TIMRCCEN_TIM3 STM32_RCC_APB1LENR #define TIMEN_TIM3 RCC_APB1LENR_TIM3EN #define TIMRCCRST_TIM3 STM32_RCC_APB1LRSTR #define TIMRST_TIM3 RCC_APB1LRSTR_TIM3RST -#define TIMCLK_TIM4 STM32_APB1_TIM4_CLKIN +#define TIMCLK_TIM4 STM32_TIM4_CLKIN #define TIMRCCEN_TIM4 STM32_RCC_APB1LENR #define TIMEN_TIM4 RCC_APB1LENR_TIM4EN #define TIMRCCRST_TIM4 STM32_RCC_APB1LRSTR #define TIMRST_TIM4 RCC_APB1LRSTR_TIM4RST -#define TIMCLK_TIM5 STM32_APB1_TIM5_CLKIN +#define TIMCLK_TIM5 STM32_TIM5_CLKIN #define TIMRCCEN_TIM5 STM32_RCC_APB1LENR #define TIMEN_TIM5 RCC_APB1LENR_TIM5EN #define TIMRCCRST_TIM5 STM32_RCC_APB1LRSTR #define TIMRST_TIM5 RCC_APB1LRSTR_TIM5RST -#define TIMCLK_TIM8 STM32_APB2_TIM8_CLKIN +#define TIMCLK_TIM8 STM32_TIM8_CLKIN #define TIMRCCEN_TIM8 STM32_RCC_APB2ENR #define TIMEN_TIM8 RCC_APB2ENR_TIM8EN #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -#define TIMCLK_TIM12 STM32_APB1_TIM12_CLKIN +#define TIMCLK_TIM12 STM32_TIM12_CLKIN #define TIMRCCEN_TIM12 STM32_RCC_APB1LENR #define TIMEN_TIM12 RCC_APB1LENR_TIM12EN #define TIMRCCRST_TIM12 STM32_RCC_APB1LRSTR #define TIMRST_TIM12 RCC_APB1LRSTR_TIM12RST -#define TIMCLK_TIM13 STM32_APB1_TIM13_CLKIN +#define TIMCLK_TIM13 STM32_TIM13_CLKIN #define TIMRCCEN_TIM13 STM32_RCC_APB1LENR #define TIMEN_TIM13 RCC_APB1LENR_TIM13EN #define TIMRCCRST_TIM13 STM32_RCC_APB1LRSTR #define TIMRST_TIM13 RCC_APB1LRSTR_TIM13RST -#define TIMCLK_TIM14 STM32_APB1_TIM14_CLKIN +#define TIMCLK_TIM14 STM32_TIM14_CLKIN #define TIMRCCEN_TIM14 STM32_RCC_APB1LENR #define TIMEN_TIM14 RCC_APB1LENR_TIM14EN #define TIMRCCRST_TIM14 STM32_RCC_APB1LRSTR #define TIMRST_TIM14 RCC_APB1LRSTR_TIM14RST -#define TIMCLK_TIM15 STM32_APB2_TIM15_CLKIN +#define TIMCLK_TIM15 STM32_TIM15_CLKIN #define TIMRCCEN_TIM15 STM32_RCC_APB2ENR #define TIMEN_TIM15 RCC_APB2ENR_TIM15EN #define TIMRCCRST_TIM15 STM32_RCC_APB2RSTR #define TIMRST_TIM15 RCC_APB2RSTR_TIM15RST -#define TIMCLK_TIM16 STM32_APB2_TIM16_CLKIN +#define TIMCLK_TIM16 STM32_TIM16_CLKIN #define TIMRCCEN_TIM16 STM32_RCC_APB2ENR #define TIMEN_TIM16 RCC_APB2ENR_TIM16EN #define TIMRCCRST_TIM16 STM32_RCC_APB2RSTR #define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST -#define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN +#define TIMCLK_TIM17 STM32_TIM17_CLKIN #define TIMRCCEN_TIM17 STM32_RCC_APB2ENR #define TIMEN_TIM17 RCC_APB2ENR_TIM17EN #define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index de9b791109a56..ec6b8f603bfd0 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -41,7 +41,7 @@ #ifdef CONFIG_STM32_PWM # include -# include "hardware/stm32_tim.h" +# include "hardware/stm32h7_tim.h" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c deleted file mode 100644 index 4fe8974731987..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ /dev/null @@ -1,1558 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32_TIM12_ADC) || \ - defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) -# undef CONFIG_STM32_TIM12 -#endif - -#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32_TIM13_ADC) || \ - defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) -# undef CONFIG_STM32_TIM13 -#endif - -#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32_TIM14_ADC) || \ - defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) -# undef CONFIG_STM32_TIM14 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ - defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ - defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM12) -# if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) -# define HAVE_TIM12_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM13) -# if defined(GPIO_TIM13_CH1OUT) -# define HAVE_TIM13_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM14) -# if defined(GPIO_TIM14_CH1OUT) -# define HAVE_TIM14_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -# endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -# endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ - defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count); -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - stm32_tim_channel_t mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = &stm32_tim_enable, - .disable = &stm32_tim_disable, - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .setperiod = &stm32_tim_setperiod, - .getcounter = &stm32_tim_getcounter, - .setcounter = &stm32_tim_setcounter, - .getwidth = &stm32_tim_getwidth, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint, - .checkint = &stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get a 16-bit register value by offset */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 16-bit register value by offset */ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Modify a 16-bit register value by offset */ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 and TIM5 timers may be 32-bits in width */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#if defined(CONFIG_STM32_TIM2) - case STM32_TIM2_BASE: - return 32; -#endif - -#if defined(CONFIG_STM32_TIM5) - case STM32_TIM5_BASE: - return 32; -#endif - - /* All others are 16-bit times */ - - default: - return 16; - } -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_tim_getwidth(dev) > 16 ? - stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) : - (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_setcounter - ****************************************************************************/ - -static void stm32_tim_setcounter(struct stm32_tim_dev_s *dev, - uint32_t count) -{ - DEBUGASSERT(dev != NULL); - - if (stm32_tim_getwidth(dev) > 16) - { - stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count); - } - else - { - stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count); - } -} - -/* Reset timer into system default state, but do not affect output/input - * pins - */ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ - defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ - defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM6_GPIOCONFIG)||\ - defined(HAVE_TIM7_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)||\ - defined(HAVE_TIM12_GPIOCONFIG)||defined(HAVE_TIM13_GPIOCONFIG)||\ - defined(HAVE_TIM14_GPIOCONFIG)||defined(HAVE_TIM15_GPIOCONFIG)||\ - defined(HAVE_TIM16_GPIOCONFIG)||defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Basic Functions - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = STM32_APB2_TIM1_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = STM32_APB1_TIM2_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = STM32_APB1_TIM3_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = STM32_APB1_TIM4_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = STM32_APB1_TIM5_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = STM32_APB1_TIM6_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = STM32_APB1_TIM7_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = STM32_APB2_TIM8_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - freqin = STM32_APB1_TIM12_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - freqin = STM32_APB1_TIM13_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - freqin = STM32_APB1_TIM14_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = STM32_APB2_TIM15_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = STM32_APB2_TIM16_CLKIN; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = STM32_APB2_TIM17_CLKIN; - break; -#endif - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, source); -} - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, source, 0); -} - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * General Functions - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - stm32_tim_mode_t mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } - - return OK; -} - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, stm32_tim_channel_t mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val &= ~(3 << GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \ - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE) - { - return -EINVAL; - } - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTTOGGLE: - ccmr_val = (GTIM_CCMR_MODE_OCREFTOG << GTIM_CCMR1_OC1M_SHIFT); - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -# if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM1_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -# if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -# if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -# if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -# if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -# endif -# if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -# if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH5OUT) - case 4: - stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break; -# endif -# if defined(GPIO_TIM8_CH6OUT) - case 5: - stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - switch (channel) - { -# if defined(GPIO_TIM12_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM12_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - switch (channel) - { -# if defined(GPIO_TIM13_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - switch (channel) - { -# if defined(GPIO_TIM14_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -# if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -# endif -# if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -# if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -# if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -# endif - default: - return -EINVAL; - } - break; -#endif - } - - return OK; -} - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; - modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/* TODO: Detach interrupts, and close down all TIM Channels */ - -int stm32_tim_deinit(struct stm32_tim_dev_s * dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim.h b/arch/arm/src/stm32h7/stm32_tim.h deleted file mode 100644 index 245386f9f0544..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim.h +++ /dev/null @@ -1,223 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32H7_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -typedef enum -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, - - /* Clock sources, OR'ed with CK_EXT */ - - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -} stm32_tim_mode_t; - -/* TIM Channel Modes */ - -typedef enum -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x0e, - - /* Output Compare Modes */ - - /* Enable standard PWM mode, active high when counter < compare */ - - STM32_TIM_CH_OUTPWM = 0x04, - - /* Toggle TIM_CHx output on UEV */ - - STM32_TIM_CH_OUTTOGGLE = 0x08, -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC - open collector mode -#endif -} stm32_tim_channel_t; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count); - - /* General and Advanced Timers Adds */ - - int (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - stm32_tim_channel_t mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, - int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer number. - * - * Returned Values: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_TIM_H */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c deleted file mode 100644 index cc5e18737e5a7..0000000000000 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,582 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2023 Max Kriegleder. All rights reserved. - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: Max Kriegleder - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ - defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ - defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM9_RES 16 -#define STM32_TIM10_RES 16 -#define STM32_TIM11_RES 16 -#define STM32_TIM12_RES 16 -#define STM32_TIM13_RES 16 -#define STM32_TIM14_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current user interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = NULL, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM9 -static struct stm32_lowerhalf_s g_tim9_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM9_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM10 -static struct stm32_lowerhalf_s g_tim10_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM10_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM11 -static struct stm32_lowerhalf_s g_tim11_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM11_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM12 -static struct stm32_lowerhalf_s g_tim12_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM12_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM13 -static struct stm32_lowerhalf_s g_tim13_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM13_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM14 -static struct stm32_lowerhalf_s g_tim14_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM14_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void * context, void * arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, ATIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_setcallback - * - * Description: - * Call this user provided timeout callback. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, ATIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, ATIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case 9: - lower = &g_tim9_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case 10: - lower = &g_tim10_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case 11: - lower = &g_tim11_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case 12: - lower = &g_tim12_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case 13: - lower = &g_tim13_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case 14: - lower = &g_tim14_lowerhalf; - break; -#endif - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h index 5b77af6b01b83..cdcdb2d4aa714 100644 --- a/arch/arm/src/stm32l0/stm32.h +++ b/arch/arm/src/stm32l0/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" #include "stm32_adc.h" diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig index 1fdceba40c2bd..4ee1a23fbcd3f 100644 --- a/arch/arm/src/stm32l1/Kconfig +++ b/arch/arm/src/stm32l1/Kconfig @@ -292,6 +292,7 @@ config STM32_STM32L15XX select STM32_HAVE_IP_SPI_V1 select STM32_HAVE_IP_SYSCFG_M3M4_V1 select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS diff --git a/arch/arm/src/stm32l1/stm32.h b/arch/arm/src/stm32l1/stm32.h index 2aed55b33cac0..5d8b38a25598c 100644 --- a/arch/arm/src/stm32l1/stm32.h +++ b/arch/arm/src/stm32l1/stm32.h @@ -57,7 +57,6 @@ #include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" -#include "stm32_tim.h" #include "stm32_uart.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) # include "stm32_usbdev.h" diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 71b1717f6e9dc..6819874852428 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -37,7 +37,6 @@ list( stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c - stm32l4_tim.c stm32l4_flash.c stm32l4_dfumode.c) @@ -45,10 +44,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32l4_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32l4_tim_lowerhalf.c) -endif() - if(NOT CONFIG_SCHED_TICKLESS) list(APPEND SRCS stm32l4_timerisr.c) else() diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 8c7e33356dac8..b3b2c1be26cee 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -615,6 +615,7 @@ config STM32_STM32L4X3 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -637,6 +638,7 @@ config STM32_STM32L4X5 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -653,6 +655,7 @@ config STM32_STM32L4X5 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -674,6 +677,7 @@ config STM32_STM32L4X6 select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -690,6 +694,7 @@ config STM32_STM32L4X6 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -711,6 +716,7 @@ config STM32_STM32L4XR select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 @@ -725,6 +731,7 @@ config STM32_STM32L4XR select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM7 select STM32_HAVE_TIM8 select STM32_HAVE_TIM17 @@ -836,6 +843,7 @@ config STM32_STM32L471XX select STM32_HAVE_CAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 77ee12e985896..71f2b4cc9ace3 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -34,17 +34,13 @@ CHIP_CSRCS += stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c CHIP_CSRCS += stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c -CHIP_CSRCS += stm32l4_pwr.c stm32l4_tim.c stm32l4_flash.c +CHIP_CSRCS += stm32l4_pwr.c stm32l4_flash.c CHIP_CSRCS += stm32l4_dfumode.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32l4_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32l4_tim_lowerhalf.c -endif - ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32l4_timerisr.c else diff --git a/arch/arm/src/stm32l4/stm32.h b/arch/arm/src/stm32l4/stm32.h index b996ad1a7d9ca..553fcbfe21057 100644 --- a/arch/arm/src/stm32l4/stm32.h +++ b/arch/arm/src/stm32l4/stm32.h @@ -52,7 +52,6 @@ #include "stm32l4_rtc.h" #include "stm32l4_sdmmc.h" #include "stm32l4_spi.h" -#include "stm32l4_tim.h" #include "stm32l4_uart.h" #include "stm32l4_usbdev.h" #include "stm32l4_wdg.h" diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index ee7347f7f56fd..62ed9deda4903 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -46,7 +46,7 @@ #include "chip.h" #include "stm32l4_rcc.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "stm32l4_dma.h" #include "stm32l4_adc.h" diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index da39bab518e9e..b0a1a5bd40686 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -179,37 +179,37 @@ #if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN #elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN #elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN #elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN #elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN #elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN #elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC1_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER @@ -228,37 +228,37 @@ #if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN #elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN #elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN #elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN #elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN #elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN #elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC2_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER @@ -277,37 +277,37 @@ #if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN #elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM2_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN #elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN #elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN #elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN #elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN #elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN +# define ADC3_TIMER_PCLK_FREQUENCY STM32_TIM15_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index 15cd9f3e4f57c..7792465cfba5a 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -930,44 +930,44 @@ static int dac_timinit(struct stm32_chan_s *chan) #ifdef NEED_TIM2 case 2: setbits = RCC_APB1ENR1_TIM2EN; - pclk = BOARD_TIM2_FREQUENCY; + pclk = STM32_TIM2_CLKIN; break; #endif #ifdef NEED_TIM3 case 3: setbits = RCC_APB1ENR1_TIM3EN; - pclk = BOARD_TIM3_FREQUENCY; + pclk = STM32_TIM3_CLKIN; break; #endif #ifdef NEED_TIM4 case 4: setbits = RCC_APB1ENR1_TIM4EN; - pclk = BOARD_TIM4_FREQUENCY; + pclk = STM32_TIM4_CLKIN; break; #endif #ifdef NEED_TIM5 case 5: setbits = RCC_APB1ENR1_TIM5EN; - pclk = BOARD_TIM5_FREQUENCY; + pclk = STM32_TIM5_CLKIN; break; #endif #ifdef NEED_TIM6 case 6: setbits = RCC_APB1ENR1_TIM6EN; - pclk = BOARD_TIM6_FREQUENCY; + pclk = STM32_TIM6_CLKIN; break; #endif #ifdef NEED_TIM7 case 7: setbits = RCC_APB1ENR1_TIM7EN; - pclk = BOARD_TIM7_FREQUENCY; + pclk = STM32_TIM7_CLKIN; break; #endif #ifdef NEED_TIM8 case 8: regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; - pclk = BOARD_TIM8_FREQUENCY; + pclk = STM32_TIM8_CLKIN; break; #endif default: diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 61293972da312..f52779bcfc8ae 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -43,7 +43,7 @@ #include "chip.h" #include "stm32l4_rcc.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "stm32l4_dma.h" #include "stm32l4_dfsdm.h" diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index aa0768b5a3cd9..95b27a986cc16 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -92,31 +92,31 @@ #if defined(CONFIG_STM32_TIM1_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM1_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM1_CLKIN #elif defined(CONFIG_STM32_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM3_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM3_CLKIN #elif defined(CONFIG_STM32_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM4_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM4_CLKIN #elif defined(CONFIG_STM32_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM6_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM6_CLKIN #elif defined(CONFIG_STM32_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM7_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM7_CLKIN #elif defined(CONFIG_STM32_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM8_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM8_CLKIN #elif defined(CONFIG_STM32_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 # define DFSDM_TIMER_BASE STM32_TIM16_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_TIM16_CLKIN #else # undef DFSDM_HAVE_TIMER #endif diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index c1aeacf7afdcb..74fbb860d2812 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -33,7 +33,7 @@ #include #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_STM32_FREERUN diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index d8e77479d2080..6fc35b5e7a798 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -34,7 +34,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_STM32_ONESHOT diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index dabf608f7b6cf..a26e5bcbc6302 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -455,7 +455,7 @@ static struct stm32_pwmtimer_s g_pwm1dev = .trgo = STM32_TIM1_TRGO, #endif .base = STM32_TIM1_BASE, - .pclk = STM32_APB2_TIM1_CLKIN, + .pclk = STM32_TIM1_CLKIN, }; #endif /* CONFIG_STM32_TIM1_PWM */ @@ -551,7 +551,7 @@ static struct stm32_pwmtimer_s g_pwm2dev = .trgo = STM32_TIM2_TRGO, #endif .base = STM32_TIM2_BASE, - .pclk = STM32_APB1_TIM2_CLKIN, + .pclk = STM32_TIM2_CLKIN, }; #endif /* CONFIG_STM32_TIM2_PWM */ @@ -648,7 +648,7 @@ static struct stm32_pwmtimer_s g_pwm3dev = .trgo = STM32_TIM3_TRGO, #endif .base = STM32_TIM3_BASE, - .pclk = STM32_APB1_TIM3_CLKIN, + .pclk = STM32_TIM3_CLKIN, }; #endif /* CONFIG_STM32_TIM3_PWM */ @@ -744,7 +744,7 @@ static struct stm32_pwmtimer_s g_pwm4dev = .trgo = STM32_TIM4_TRGO, #endif .base = STM32_TIM4_BASE, - .pclk = STM32_APB1_TIM4_CLKIN, + .pclk = STM32_TIM4_CLKIN, }; #endif /* CONFIG_STM32_TIM4_PWM */ @@ -838,7 +838,7 @@ static struct stm32_pwmtimer_s g_pwm5dev = .trgo = STM32_TIM5_TRGO #endif .base = STM32_TIM5_BASE, - .pclk = STM32_APB1_TIM5_CLKIN, + .pclk = STM32_TIM5_CLKIN, }; #endif /* CONFIG_STM32_TIM5_PWM */ @@ -1001,7 +1001,7 @@ static struct stm32_pwmtimer_s g_pwm8dev = .trgo = STM32_TIM8_TRGO, #endif .base = STM32_TIM8_BASE, - .pclk = STM32_APB2_TIM8_CLKIN, + .pclk = STM32_TIM8_CLKIN, }; #endif /* CONFIG_STM32_TIM8_PWM */ @@ -1083,7 +1083,7 @@ static struct stm32_pwmtimer_s g_pwm15dev = .trgo = STM32_TIM15_TRGO, #endif .base = STM32_TIM15_BASE, - .pclk = STM32_APB2_TIM15_CLKIN, + .pclk = STM32_TIM15_CLKIN, }; #endif /* CONFIG_STM32_TIM15_PWM */ @@ -1149,7 +1149,7 @@ static struct stm32_pwmtimer_s g_pwm16dev = .trgo = 0, /* TRGO not supported for TIM16 */ #endif .base = STM32_TIM16_BASE, - .pclk = STM32_APB2_TIM16_CLKIN, + .pclk = STM32_TIM16_CLKIN, }; #endif /* CONFIG_STM32_TIM16_PWM */ @@ -1215,7 +1215,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .trgo = 0, /* TRGO not supported for TIM17 */ #endif .base = STM32_TIM17_BASE, - .pclk = STM32_APB2_TIM17_CLKIN, + .pclk = STM32_TIM17_CLKIN, }; #endif /* CONFIG_STM32_TIM17_PWM */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 18ca8468adf45..3287632209cbc 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -42,7 +42,7 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32l4_gpio.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "stm32l4_qencoder.h" #ifdef CONFIG_SENSORS_QENCODER diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c deleted file mode 100644 index 65a83b9158990..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ /dev/null @@ -1,1912 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l4_gpio.h" -#include "stm32l4_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, - uint32_t freq); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setfreq = stm32_tim_setfreq, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, - .dump_regs = stm32_tim_dumpregs, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the STM32 - * F4 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: - * Add support for input capture and bipolar dual outputs for TIM8 - */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_dumpregs - ****************************************************************************/ - -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) -{ - struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; - - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET) - ); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) - ); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET) - ); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET) - ); - - if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); - } - else - { - ainfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - break; - - case STM32_TIM_MODE_UP: - val &= ~GTIM_CR1_DIR; - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setfreq - ****************************************************************************/ - -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - uint32_t reload; - uint32_t timclk; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - * - * Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So ( prescaler = pclck / 65535 / freq ) would be optimal. - */ - - prescaler = (freqin / freq + 65534) / 65535; - - /* We need to decrement value for '1', but only if that will not to - * cause underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow as well. */ - - if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = freqin / prescaler; - - reload = timclk / freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Set the reload and prescaler values */ - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); - stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); - - return (timclk / reload); -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 3) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h deleted file mode 100644 index 46cd7a6e2efa1..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ /dev/null @@ -1,231 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32L4_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32l4_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active - * high when counter < compare - */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); - - /* Debug */ - - void (*dump_regs)(struct stm32_tim_dev_s *dev); -}; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c deleted file mode 100644 index 1c60f9abcf5e6..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ /dev/null @@ -1,626 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. - * SPDX-FileCopyrightText: 2015 Omni Hoverboards Inc. All rights reserved. - * SPDX-FileCopyrightText: 2016 Sebastien Lorquet All rights reserved. - * SPDX-FileContributor: Wail Khemir - * SPDX-FileContributor: Paul Alexander Patience - * SPDX-FileContributor: dev@ziggurat29.com - * SPDX-FileContributor: Sebastien Lorquet - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32l4_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *) arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower- half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index e5e91d82a2d15..dfd692b4daf4a 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -36,7 +36,6 @@ list( stm32l5_spi.c stm32l5_lse.c stm32l5_pwr.c - stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c) @@ -44,10 +43,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32l5_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32l5_tim_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l5_userspace.c stm32l5_mpuinit.c) endif() diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index e2588b6c50674..48988f3a2b3ae 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -37,16 +37,12 @@ CHIP_CSRCS += stm32l5_allocateheap.c stm32l5_exti_gpio.c stm32l5_gpio.c CHIP_CSRCS += stm32l5_irq.c stm32l5_lowputc.c stm32l5_rcc.c CHIP_CSRCS += stm32l5_serial.c stm32l5_start.c CHIP_CSRCS += stm32l5_spi.c stm32l5_lse.c -CHIP_CSRCS += stm32l5_pwr.c stm32l5_tim.c stm32l5_flash.c stm32l5_timerisr.c +CHIP_CSRCS += stm32l5_pwr.c stm32l5_flash.c stm32l5_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32l5_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32l5_tim_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l5_userspace.c stm32l5_mpuinit.c endif diff --git a/arch/arm/src/stm32l5/stm32.h b/arch/arm/src/stm32l5/stm32.h index 9ce64f1178564..9b00abf59838a 100644 --- a/arch/arm/src/stm32l5/stm32.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -43,7 +43,6 @@ #include "stm32l5_pwr.h" #include "stm32l5_rcc.h" #include "stm32l5_spi.h" -#include "stm32l5_tim.h" #include "stm32l5_uart.h" #include "stm32l5_lowputc.h" diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c deleted file mode 100644 index dc176524d9fa6..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ /dev/null @@ -1,1695 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l5_gpio.h" -#include "stm32l5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32L5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32L5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h deleted file mode 100644 index 10218a23018a2..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ /dev/null @@ -1,222 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32L5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32l5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC = open collector mode -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32L5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c deleted file mode 100644 index 789b50c7bdc61..0000000000000 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32l5_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index 20e50c3bb84b3..c247cb91bfc3a 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -34,7 +34,6 @@ set(SRCS stm32_lse.c stm32u5xx_rcc.c stm32_pwr.c - stm32_tim.c stm32_flash.c stm32_timerisr.c) @@ -42,10 +41,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index ddd50dece4b7e..f46b5c09a6b14 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -108,6 +108,8 @@ config STM32_STM32U5A5XX select STM32_HAVE_FDCAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -138,6 +140,8 @@ config STM32_STM32U585XX select STM32_HAVE_FDCAN1 select STM32_HAVE_TIM1 select STM32_HAVE_TIM2 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 diff --git a/arch/arm/src/stm32u5/Make.defs b/arch/arm/src/stm32u5/Make.defs index 9c44a7c632047..11afa0aff67df 100644 --- a/arch/arm/src/stm32u5/Make.defs +++ b/arch/arm/src/stm32u5/Make.defs @@ -37,16 +37,12 @@ CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_i2c.c CHIP_CSRCS += stm32_serial.c stm32_start.c CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32u5xx_rcc.c -CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c +CHIP_CSRCS += stm32_pwr.c stm32_flash.c stm32_timerisr.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32u5_tim.h similarity index 99% rename from arch/arm/src/stm32u5/hardware/stm32_tim.h rename to arch/arm/src/stm32u5/hardware/stm32u5_tim.h index e180a60d773a3..1ffca4e83683b 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32u5/hardware/stm32_tim.h + * arch/arm/src/stm32u5/hardware/stm32u5_tim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32u5/stm32.h b/arch/arm/src/stm32u5/stm32.h index b53e091765453..35fef1862fb72 100644 --- a/arch/arm/src/stm32u5/stm32.h +++ b/arch/arm/src/stm32u5/stm32.h @@ -43,7 +43,6 @@ #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_spi.h" -#include "stm32_tim.h" #include "stm32_uart.h" #include "stm32_lowputc.h" diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c deleted file mode 100644 index 66879e72e8a2a..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ /dev/null @@ -1,1695 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32U5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32U5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h deleted file mode 100644 index f61751552dd49..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ /dev/null @@ -1,216 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32U5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32U5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32U5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c deleted file mode 100644 index a564a8af52538..0000000000000 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32u5/stm32_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 5d716f780a4fb..114d8d7e4c40a 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -35,7 +35,6 @@ set(SRCS stm32wb_start.c stm32wb_rcc_lse.c stm32wb_pwr.c - stm32wb_tim.c stm32wb_flash.c) if(NOT CONFIG_ARCH_IDLE_CUSTOM) @@ -43,7 +42,6 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) endif() if(CONFIG_TIMER) - list(APPEND SRCS stm32wb_tim_lowerhalf.c) endif() if(NOT CONFIG_SCHED_TICKLESS) diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index 107f025ac2dfa..60ef9b9716c72 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -165,6 +165,7 @@ config STM32_STM32WB10 bool default n select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TSC @@ -173,6 +174,7 @@ config STM32_STM32WB15 bool default n select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TSC select STM32_HAVE_LPUART @@ -184,6 +186,7 @@ config STM32_STM32WB30 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -194,6 +197,7 @@ config STM32_STM32WB50 default n select STM32_HAVE_HSI48 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -205,6 +209,7 @@ config STM32_STM32WB35 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 @@ -222,6 +227,7 @@ config STM32_STM32WB55 select STM32_HAVE_HSI48 select STM32_HAVE_DMA2 select STM32_HAVE_TIM1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 select STM32_HAVE_TIM2 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 5c14a1271b091..344959083e3ef 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -34,7 +34,7 @@ CHIP_CSRCS += stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c CHIP_CSRCS += stm32wb_serial.c stm32wb_i2c.c stm32wb_start.c CHIP_CSRCS += stm32wb_rcc_lse.c -CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c +CHIP_CSRCS += stm32wb_pwr.c CHIP_CSRCS += stm32wb_flash.c ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) @@ -42,7 +42,6 @@ CHIP_CSRCS += stm32wb_idle.c endif ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32wb_tim_lowerhalf.c endif ifneq ($(CONFIG_SCHED_TICKLESS),y) diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h deleted file mode 100644 index e4936d2ac8bc0..0000000000000 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ /dev/null @@ -1,1387 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/hardware/stm32wb_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ - -/* Register Addresses *******************************************************/ - -/* Advanced Timer TIM1 */ - -#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) -#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) -#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) -#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) -#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) -#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) -#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) -#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) -#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) -#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) - -/* General 32-bit Timer TIM2 */ - -#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) -#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) -#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) -#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) -#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) -#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) - -/* General Timers TIM16/TIM17 */ - -#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) - -#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) -#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) -#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) -#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) -#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) -#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) -#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) -#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) -#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) -#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) -#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) -#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) -#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) -#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) -#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) -#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) -#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) -#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) - -/* Register Value Constants *************************************************/ - -/* Digital Filter options */ - -#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define TIM1_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM1_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM1_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM1_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM1_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM1_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM1_CR1_DIR (1 << 4) /* Bit 4: Counter direction */ -# define TIM1_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */ -# define TIM1_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */ - -#define TIM1_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define TIM1_CR1_CMS_MASK (0x3 << TIM1_CR1_CMS_SHIFT) -# define TIM1_CR1_CMS_EDGE (0x0 << TIM1_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define TIM1_CR1_CMS_CNTR1 (0x1 << TIM1_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define TIM1_CR1_CMS_CNTR2 (0x2 << TIM1_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define TIM1_CR1_CMS_CNTR3 (0x3 << TIM1_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define TIM1_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM1_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM1_CR1_CKD_MASK (0x3 << TIM1_CR1_CKD_SHIFT) -# define TIM1_CR1_CKD_TCKINT (0x0 << TIM1_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM1_CR1_CKD_2TCKINT (0x1 << TIM1_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM1_CR1_CKD_4TCKINT (0x2 << TIM1_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM1_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM2_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM2_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM2_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM2_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM2_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM2_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM2_CR1_DIR (1 << 4) /* Bit 4: Counter direction */ -# define TIM2_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */ -# define TIM2_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */ - -#define TIM2_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */ -#define TIM2_CR1_CMS_MASK (0x3 << TIM2_CR1_CMS_SHIFT) -# define TIM2_CR1_CMS_EDGE (0x0 << TIM2_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */ -# define TIM2_CR1_CMS_CNTR1 (0x1 << TIM2_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */ -# define TIM2_CR1_CMS_CNTR2 (0x2 << TIM2_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */ -# define TIM2_CR1_CMS_CNTR3 (0x3 << TIM2_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */ - -#define TIM2_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM2_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM2_CR1_CKD_MASK (0x3 << TIM2_CR1_CKD_SHIFT) -# define TIM2_CR1_CKD_TCKINT (0x0 << TIM2_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM2_CR1_CKD_2TCKINT (0x1 << TIM2_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM2_CR1_CKD_4TCKINT (0x2 << TIM2_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM2_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM16_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM16_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM16_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM16_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM16_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM16_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM16_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM16_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM16_CR1_CKD_MASK (0x3 << TIM16_CR1_CKD_SHIFT) -# define TIM16_CR1_CKD_TCKINT (0x0 << TIM16_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM16_CR1_CKD_2TCKINT (0x1 << TIM16_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM16_CR1_CKD_4TCKINT (0x2 << TIM16_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM16_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -#define TIM17_CR1_CEN (1 << 0) /* Bit 0: Counter enable */ -#define TIM17_CR1_UDIS (1 << 1) /* Bit 1: Update disable */ -#define TIM17_CR1_URS (1 << 2) /* Bit 2: Update request source */ -# define TIM17_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */ -# define TIM17_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */ - -#define TIM17_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */ -#define TIM17_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */ -#define TIM17_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */ -#define TIM17_CR1_CKD_MASK (0x3 << TIM17_CR1_CKD_SHIFT) -# define TIM17_CR1_CKD_TCKINT (0x0 << TIM17_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */ -# define TIM17_CR1_CKD_2TCKINT (0x1 << TIM17_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */ -# define TIM17_CR1_CKD_4TCKINT (0x2 << TIM17_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */ - -#define TIM17_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */ - -/* Control register 2 */ - -#define TIM1_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM1_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM1_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM1_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM1_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM1_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM1_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM1_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */ -#define TIM1_CR2_MMS_MASK (0x7 << TIM1_CR2_MMS_SHIFT) -# define TIM1_CR2_MMS_RESET (0x0 << TIM1_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define TIM1_CR2_MMS_ENABLE (0x1 << TIM1_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define TIM1_CR2_MMS_UPDATE (0x2 << TIM1_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define TIM1_CR2_MMS_COMPP (0x3 << TIM1_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */ -# define TIM1_CR2_MMS_OC1REF (0x4 << TIM1_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define TIM1_CR2_MMS_OC2REF (0x5 << TIM1_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define TIM1_CR2_MMS_OC3REF (0x6 << TIM1_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define TIM1_CR2_MMS_OC4REF (0x7 << TIM1_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ - -#define TIM1_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -# define TIM1_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */ -# define TIM1_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */ - -#define TIM1_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM1_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ -#define TIM1_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */ -#define TIM1_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */ -#define TIM1_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */ -#define TIM1_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */ -#define TIM1_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */ -#define TIM1_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */ -#define TIM1_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */ -#define TIM1_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */ -#define TIM1_CR2_MMS2_MASK (0xf << TIM1_CR2_MMS2_SHIFT) -# define TIM1_CR2_MMS2_RESET (0x0 << TIM1_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */ -# define TIM1_CR2_MMS2_ENABLE (0x1 << TIM1_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */ -# define TIM1_CR2_MMS2_UPDATE (0x2 << TIM1_CR2_MMS2_SHIFT) /* 0010: Update event is TRGO2 */ -# define TIM1_CR2_MMS2_COMPP (0x3 << TIM1_CR2_MMS2_SHIFT) /* 0011: Compare Pulse - CC1IF flag */ -# define TIM1_CR2_MMS2_OC1REF (0x4 << TIM1_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC2REF (0x5 << TIM1_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC3REF (0x6 << TIM1_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC4REF (0x7 << TIM1_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC5REF (0x8 << TIM1_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */ -# define TIM1_CR2_MMS2_OC6REF (0x9 << TIM1_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC4 (0xa << TIM1_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC6 (0xb << TIM1_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */ -# define TIM1_CR2_MMS2_CMPOC4R6R (0xc << TIM1_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */ -# define TIM1_CR2_MMS2_CMPOC4R6F (0xd << TIM1_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */ -# define TIM1_CR2_MMS2_CMPOC5R6R (0xe << TIM1_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */ -# define TIM1_CR2_MMS2_CMPOC5R6F (0xf << TIM1_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */ - -#define TIM2_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM2_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM2_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM2_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */ -#define TIM2_CR2_MMS_MASK (0x7 << TIM2_CR2_MMS_SHIFT) -# define TIM2_CR2_MMS_RESET (0x0 << TIM2_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */ -# define TIM2_CR2_MMS_ENABLE (0x1 << TIM2_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */ -# define TIM2_CR2_MMS_UPDATE (0x2 << TIM2_CR2_MMS_SHIFT) /* 010: Update event is TRGO */ -# define TIM2_CR2_MMS_COMPP (0x3 << TIM2_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */ -# define TIM2_CR2_MMS_OC1REF (0x4 << TIM2_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */ -# define TIM2_CR2_MMS_OC2REF (0x5 << TIM2_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */ -# define TIM2_CR2_MMS_OC3REF (0x6 << TIM2_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */ -# define TIM2_CR2_MMS_OC4REF (0x7 << TIM2_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */ - -#define TIM2_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */ -# define TIM2_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */ -# define TIM2_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */ - -#define TIM16_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM16_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM16_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM16_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM16_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM16_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM16_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM16_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM16_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ - -#define TIM17_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */ -#define TIM17_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */ -# define TIM17_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */ -# define TIM17_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */ - -#define TIM17_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */ -# define TIM17_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */ -# define TIM17_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */ - -#define TIM17_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */ -#define TIM17_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */ - -/* Slave mode control register */ - -#define TIM1_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */ -#define TIM1_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */ -#define TIM1_SMCR_SMS_BITS(h,l) (((h) << TIM1_SMCR_SMS_HI_SHIFT) | ((l) << TIM1_SMCR_SMS_LO_SHIFT)) -#define TIM1_SMCR_SMS_MASK TIM1_SMCR_SMS_BITS(0x1, 0x7) -# define TIM1_SMCR_DISAB TIM1_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */ -# define TIM1_SMCR_ENCMD1 TIM1_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */ -# define TIM1_SMCR_ENCMD2 TIM1_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */ -# define TIM1_SMCR_ENCMD3 TIM1_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */ -# define TIM1_SMCR_RESET TIM1_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */ -# define TIM1_SMCR_GATED TIM1_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */ -# define TIM1_SMCR_TRIGGER TIM1_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */ -# define TIM1_SMCR_EXTCLK1 TIM1_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */ -# define TIM1_SMCR_SMS_COMBINED TIM1_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */ - -#define TIM1_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -# define TIM1_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */ -# define TIM1_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */ - -#define TIM1_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */ -#define TIM1_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */ -#define TIM1_SMCR_TS_BITS(h,l) (((h) << TIM1_SMCR_TS_HI_SHIFT) | ((l) << TIM1_SMCR_TS_LO_SHIFT)) -#define TIM1_SMCR_TS_MASK TIM1_SMCR_TS_BITS(0x3, 0x7) -# define TIM1_SMCR_ITR0 TIM1_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */ -# define TIM1_SMCR_ITR1 TIM1_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */ -# define TIM1_SMCR_ITR2 TIM1_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */ -# define TIM1_SMCR_ITR3 TIM1_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */ -# define TIM1_SMCR_T1FED TIM1_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */ -# define TIM1_SMCR_TI1FP1 TIM1_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer input 1 (TI1FP1) */ -# define TIM1_SMCR_T12FP2 TIM1_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer input 2 (TI2FP2) */ -# define TIM1_SMCR_ETRF TIM1_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */ - -#define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) -# define TIM1_SMCR_PSCOFF (0x0 << TIM1_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define TIM1_SMCR_ETRPd2 (0x1 << TIM1_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define TIM1_SMCR_ETRPd4 (0x2 << TIM1_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define TIM1_SMCR_ETRPd8 (0x3 << TIM1_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define TIM1_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define TIM1_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -# define TIM1_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */ -# define TIM1_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */ - -#define TIM2_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */ -#define TIM2_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */ -#define TIM2_SMCR_SMS_BITS(h,l) (((h) << TIM2_SMCR_SMS_HI_SHIFT) | ((l) << TIM2_SMCR_SMS_LO_SHIFT)) -#define TIM2_SMCR_SMS_MASK TIM2_SMCR_SMS_BITS(0x1, 0x7) -# define TIM2_SMCR_DISAB TIM2_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */ -# define TIM2_SMCR_ENCMD1 TIM2_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */ -# define TIM2_SMCR_ENCMD2 TIM2_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */ -# define TIM2_SMCR_ENCMD3 TIM2_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */ -# define TIM2_SMCR_RESET TIM2_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */ -# define TIM2_SMCR_GATED TIM2_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */ -# define TIM2_SMCR_TRIGGER TIM2_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */ -# define TIM2_SMCR_EXTCLK1 TIM2_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */ -# define TIM2_SMCR_SMS_COMBINED TIM2_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */ - -#define TIM2_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */ -# define TIM2_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */ -# define TIM2_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */ - -#define TIM2_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */ -#define TIM2_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */ -#define TIM2_SMCR_TS_BITS(h,l) (((h) << TIM2_SMCR_TS_HI_SHIFT) | ((l) << TIM2_SMCR_TS_LO_SHIFT)) -#define TIM2_SMCR_TS_MASK TIM2_SMCR_TS_BITS(0x3, 0x7) -# define TIM2_SMCR_ITR0 TIM2_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */ -# define TIM2_SMCR_ITR1 TIM2_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */ -# define TIM2_SMCR_ITR2 TIM2_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */ -# define TIM2_SMCR_ITR3 TIM2_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */ -# define TIM2_SMCR_T1FED TIM2_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */ -# define TIM2_SMCR_TI1FP1 TIM2_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer Input 1 (TI1FP1) */ -# define TIM2_SMCR_T12FP2 TIM2_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer Input 2 (TI2FP2) */ -# define TIM2_SMCR_ETRF TIM2_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */ -# define TIM2_SMCR_ITR4 TIM2_SMCR_TS_BITS(0x1, 0x0) /* 01,000: Internal trigger 4 (ITR4) */ -# define TIM2_SMCR_ITR5 TIM2_SMCR_TS_BITS(0x1, 0x1) /* 01,001: Internal trigger 5 (ITR5) */ -# define TIM2_SMCR_ITR6 TIM2_SMCR_TS_BITS(0x1, 0x2) /* 01,010: Internal trigger 6 (ITR6) */ -# define TIM2_SMCR_ITR7 TIM2_SMCR_TS_BITS(0x1, 0x3) /* 01,011: Internal trigger 7 (ITR7) */ -# define TIM2_SMCR_ITR8 TIM2_SMCR_TS_BITS(0x1, 0x4) /* 01,100: Internal trigger 8 (ITR8) */ - -#define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ -#define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ -#define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ -#define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) -# define TIM2_SMCR_PSCOFF (0x0 << TIM2_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */ -# define TIM2_SMCR_ETRPd2 (0x1 << TIM2_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */ -# define TIM2_SMCR_ETRPd4 (0x2 << TIM2_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */ -# define TIM2_SMCR_ETRPd8 (0x3 << TIM2_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */ - -#define TIM2_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */ -#define TIM2_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */ -# define TIM2_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */ -# define TIM2_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */ - -/* Timer DMA / Interrupt enable register */ - -#define TIM1_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM1_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM1_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define TIM1_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define TIM1_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define TIM1_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM1_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define TIM1_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM1_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM1_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define TIM1_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define TIM1_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define TIM1_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ -#define TIM1_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */ -#define TIM1_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */ - -#define TIM2_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM2_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM2_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */ -#define TIM2_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */ -#define TIM2_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */ -#define TIM2_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */ -#define TIM2_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM2_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ -#define TIM2_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */ -#define TIM2_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */ -#define TIM2_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */ - -#define TIM16_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM16_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM16_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM16_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM16_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM16_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ - -#define TIM17_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */ -#define TIM17_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */ -#define TIM17_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */ -#define TIM17_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */ -#define TIM17_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */ -#define TIM17_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */ - -/* Status register */ - -#define TIM1_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM1_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM1_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define TIM1_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define TIM1_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define TIM1_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM1_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define TIM1_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM1_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */ -#define TIM1_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define TIM1_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define TIM1_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define TIM1_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ -#define TIM1_SR_SBIF (1 << 13) /* Bit 13: System break interrupt Flag */ -#define TIM1_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */ -#define TIM1_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */ - -#define TIM2_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM2_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM2_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */ -#define TIM2_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */ -#define TIM2_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */ -#define TIM2_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */ -#define TIM2_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ -#define TIM2_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */ -#define TIM2_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */ -#define TIM2_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */ - -#define TIM16_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM16_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM16_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM16_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM16_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ - -#define TIM17_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */ -#define TIM17_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */ -#define TIM17_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */ -#define TIM17_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */ -#define TIM17_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */ - -/* Event generation register */ - -#define TIM1_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM1_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM1_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define TIM1_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define TIM1_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define TIM1_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM1_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ -#define TIM1_EGR_BG (1 << 7) /* Bit 7: Break Generation */ -#define TIM1_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */ - -#define TIM2_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM2_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM2_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */ -#define TIM2_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */ -#define TIM2_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */ -#define TIM2_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */ - -#define TIM16_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM16_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM16_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM16_EGR_BG (1 << 7) /* Bit 7: Break Generation */ - -#define TIM17_EGR_UG (1 << 0) /* Bit 0: Update Generation */ -#define TIM17_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */ -#define TIM17_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */ -#define TIM17_EGR_BG (1 << 7) /* Bit 7: Break Generation */ - -/* Capture/compare mode registers - capture/compare mode selection */ - -#define TIM1_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM1_CCMR1_CC1S_MASK (0x3 << TIM1_CCMR1_CC1S_SHIFT) -# define TIM1_CCMR1_CC1S_CCOUT (0x0 << TIM1_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM1_CCMR1_CC1S_CCIN1 (0x1 << TIM1_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ -# define TIM1_CCMR1_CC1S_CCIN2 (0x2 << TIM1_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */ -# define TIM1_CCMR1_CC1S_CCINTRC (0x3 << TIM1_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */ - -#define TIM1_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define TIM1_CCMR1_CC2S_MASK (0x3 << TIM1_CCMR1_CC2S_SHIFT) -# define TIM1_CCMR1_CC2S_CCOUT (0x0 << TIM1_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */ -# define TIM1_CCMR1_CC2S_CCIN1 (0x1 << TIM1_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */ -# define TIM1_CCMR1_CC2S_CCIN2 (0x2 << TIM1_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */ -# define TIM1_CCMR1_CC2S_CCINTRC (0x3 << TIM1_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */ - -#define TIM1_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define TIM1_CCMR2_CC3S_MASK (0x3 << TIM1_CCMR2_CC3S_SHIFT) -# define TIM1_CCMR2_CC3S_CCOUT (0x0 << TIM1_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */ -# define TIM1_CCMR2_CC3S_CCIN1 (0x1 << TIM1_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */ -# define TIM1_CCMR2_CC3S_CCIN2 (0x2 << TIM1_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */ -# define TIM1_CCMR2_CC3S_CCINTRC (0x3 << TIM1_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */ - -#define TIM1_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define TIM1_CCMR2_CC4S_MASK (0x3 << TIM1_CCMR2_CC4S_SHIFT) -# define TIM1_CCMR2_CC4S_CCOUT (0x0 << TIM1_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */ -# define TIM1_CCMR2_CC4S_CCIN1 (0x1 << TIM1_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */ -# define TIM1_CCMR2_CC4S_CCIN2 (0x2 << TIM1_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */ -# define TIM1_CCMR2_CC4S_CCINTRC (0x3 << TIM1_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */ - -#define TIM2_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM2_CCMR1_CC1S_MASK (0x3 << TIM2_CCMR1_CC1S_SHIFT) -# define TIM2_CCMR1_CC1S_CCOUT (0x0 << TIM2_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM2_CCMR1_CC1S_CCIN1 (0x1 << TIM2_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ -# define TIM2_CCMR1_CC1S_CCIN2 (0x2 << TIM2_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */ -# define TIM2_CCMR1_CC1S_CCINTRC (0x3 << TIM2_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */ - -#define TIM2_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */ -#define TIM2_CCMR1_CC2S_MASK (0x3 << TIM2_CCMR1_CC2S_SHIFT) -# define TIM2_CCMR1_CC2S_CCOUT (0x0 << TIM2_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */ -# define TIM2_CCMR1_CC2S_CCIN1 (0x1 << TIM2_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */ -# define TIM2_CCMR1_CC2S_CCIN2 (0x2 << TIM2_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */ -# define TIM2_CCMR1_CC2S_CCINTRC (0x3 << TIM2_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */ - -#define TIM2_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */ -#define TIM2_CCMR2_CC3S_MASK (0x3 << TIM2_CCMR2_CC3S_SHIFT) -# define TIM2_CCMR2_CC3S_CCOUT (0x0 << TIM2_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */ -# define TIM2_CCMR2_CC3S_CCIN1 (0x1 << TIM2_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */ -# define TIM2_CCMR2_CC3S_CCIN2 (0x2 << TIM2_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */ -# define TIM2_CCMR2_CC3S_CCINTRC (0x3 << TIM2_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */ - -#define TIM2_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */ -#define TIM2_CCMR2_CC4S_MASK (0x3 << TIM2_CCMR2_CC4S_SHIFT) -# define TIM2_CCMR2_CC4S_CCOUT (0x0 << TIM2_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */ -# define TIM2_CCMR2_CC4S_CCIN1 (0x1 << TIM2_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */ -# define TIM2_CCMR2_CC4S_CCIN2 (0x2 << TIM2_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */ -# define TIM2_CCMR2_CC4S_CCINTRC (0x3 << TIM2_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */ - -#define TIM16_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM16_CCMR1_CC1S_MASK (0x3 << TIM16_CCMR1_CC1S_SHIFT) -# define TIM16_CCMR1_CC1S_CCOUT (0x0 << TIM16_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM16_CCMR1_CC1S_CCIN1 (0x1 << TIM16_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ - -#define TIM17_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */ -#define TIM17_CCMR1_CC1S_MASK (0x3 << TIM17_CCMR1_CC1S_SHIFT) -# define TIM17_CCMR1_CC1S_CCOUT (0x0 << TIM17_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */ -# define TIM17_CCMR1_CC1S_CCIN1 (0x1 << TIM17_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */ - -/* Capture/compare mode registers - Output compare mode */ - -#define TIM1_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM1_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM1_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM1_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM1_CCMR1_OC1M_BITS(h,l) (((h) << TIM1_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC1M_LO_SHIFT)) -#define TIM1_CCMR1_OC1M_MASK TIM1_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM1_CCMR1_OC1M_FRZN TIM1_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR1_OC1M_CHACT TIM1_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM1_CCMR1_OC1M_CHINACT TIM1_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM1_CCMR1_OC1M_OCREFTOG TIM1_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM1_CCMR1_OC1M_OCREFLO TIM1_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM1_CCMR1_OC1M_OCREFHI TIM1_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM1_CCMR1_OC1M_PWM1 TIM1_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR1_OC1M_PWM2 TIM1_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR1_OC1M_OPM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR1_OC1M_OPM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR1_OC1M_COMBINED1 TIM1_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR1_OC1M_COMBINED2 TIM1_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR1_OC1M_ASYMM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR1_OC1M_ASYMM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */ - -#define TIM1_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define TIM1_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define TIM1_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */ -#define TIM1_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */ -#define TIM1_CCMR1_OC2M_BITS(h,l) (((h) << TIM1_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC2M_LO_SHIFT)) -#define TIM1_CCMR1_OC2M_MASK TIM1_CCMR1_OC2M_BITS(0x1, 0x7) -# define TIM1_CCMR1_OC2M_FRZN TIM1_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR1_OC2M_CHACT TIM1_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */ -# define TIM1_CCMR1_OC2M_CHINACT TIM1_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */ -# define TIM1_CCMR1_OC2M_OCREFTOG TIM1_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */ -# define TIM1_CCMR1_OC2M_OCREFLO TIM1_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */ -# define TIM1_CCMR1_OC2M_OCREFHI TIM1_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */ -# define TIM1_CCMR1_OC2M_PWM1 TIM1_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR1_OC2M_PWM2 TIM1_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR1_OC2M_OPM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR1_OC2M_OPM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR1_OC2M_COMBINED1 TIM1_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR1_OC2M_COMBINED2 TIM1_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR1_OC2M_ASYMM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR1_OC2M_ASYMM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -#define TIM1_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define TIM1_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define TIM1_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */ -#define TIM1_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */ -#define TIM1_CCMR2_OC3M_BITS(h,l) (((h) << TIM1_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC3M_LO_SHIFT)) -#define TIM1_CCMR2_OC3M_MASK TIM1_CCMR2_OC3M_BITS(0x1, 0x7) -# define TIM1_CCMR2_OC3M_FRZN TIM1_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR2_OC3M_CHACT TIM1_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */ -# define TIM1_CCMR2_OC3M_CHINACT TIM1_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */ -# define TIM1_CCMR2_OC3M_OCREFTOG TIM1_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */ -# define TIM1_CCMR2_OC3M_OCREFLO TIM1_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */ -# define TIM1_CCMR2_OC3M_OCREFHI TIM1_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */ -# define TIM1_CCMR2_OC3M_PWM1 TIM1_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR2_OC3M_PWM2 TIM1_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR2_OC3M_OPM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR2_OC3M_OPM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR2_OC3M_COMBINED1 TIM1_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR2_OC3M_COMBINED2 TIM1_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR2_OC3M_ASYMM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR2_OC3M_ASYMM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ - -#define TIM1_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define TIM1_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define TIM1_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */ -#define TIM1_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */ -#define TIM1_CCMR2_OC4M_BITS(h,l) (((h) << TIM1_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC4M_LO_SHIFT)) -#define TIM1_CCMR2_OC4M_MASK TIM1_CCMR2_OC4M_BITS(0x1, 0x7) -# define TIM1_CCMR2_OC4M_FRZN TIM1_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR2_OC4M_CHACT TIM1_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */ -# define TIM1_CCMR2_OC4M_CHINACT TIM1_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */ -# define TIM1_CCMR2_OC4M_OCREFTOG TIM1_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */ -# define TIM1_CCMR2_OC4M_OCREFLO TIM1_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */ -# define TIM1_CCMR2_OC4M_OCREFHI TIM1_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */ -# define TIM1_CCMR2_OC4M_PWM1 TIM1_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR2_OC4M_PWM2 TIM1_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR2_OC4M_OPM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR2_OC4M_OPM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR2_OC4M_COMBINED1 TIM1_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR2_OC4M_COMBINED2 TIM1_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR2_OC4M_ASYMM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR2_OC4M_ASYMM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -#define TIM1_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */ -#define TIM1_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */ -#define TIM1_CCMR3_OC5M_LO_SHIFT (4) /* Bits 4-6: Output Compare 5 Mode, bits [2:0] */ -#define TIM1_CCMR3_OC5M_HI_SHIFT (16) /* Bit 16: Output Compare 5 Mode, bits [3] */ -#define TIM1_CCMR3_OC5M_BITS(h,l) (((h) << TIM1_CCMR3_OC5M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC5M_LO_SHIFT)) -#define TIM1_CCMR3_OC5M_MASK TIM1_CCMR3_OC5M_BITS(0x1, 0x7) -# define TIM1_CCMR3_OC5M_FRZN TIM1_CCMR3_OC5M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR3_OC5M_CHACT TIM1_CCMR3_OC5M_BITS(0x0, 0x1) /* 0,001: Channel 5 active on match */ -# define TIM1_CCMR3_OC5M_CHINACT TIM1_CCMR3_OC5M_BITS(0x0, 0x2) /* 0,010: Channel 5 inactive on match */ -# define TIM1_CCMR3_OC5M_OCREFTOG TIM1_CCMR3_OC5M_BITS(0x0, 0x3) /* 0,011: OC5REF toggle TIM_CNT=TIM_CCR5 */ -# define TIM1_CCMR3_OC5M_OCREFLO TIM1_CCMR3_OC5M_BITS(0x0, 0x4) /* 0,100: OC5REF forced low */ -# define TIM1_CCMR3_OC5M_OCREFHI TIM1_CCMR3_OC5M_BITS(0x0, 0x5) /* 0,101: OC5REF forced high */ -# define TIM1_CCMR3_OC5M_PWM1 TIM1_CCMR3_OC5M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR3_OC5M_PWM2 TIM1_CCMR3_OC5M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR3_OC5M_OPM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR3_OC5M_OPM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR3_OC5M_COMBINED1 TIM1_CCMR3_OC5M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR3_OC5M_COMBINED2 TIM1_CCMR3_OC5M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR3_OC5M_ASYMM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR3_OC5M_ASYMM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */ - -#define TIM1_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */ -#define TIM1_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */ -#define TIM1_CCMR3_OC6M_LO_SHIFT (12) /* Bits 12-14: Output Compare 6 Mode, bits [2:0] */ -#define TIM1_CCMR3_OC6M_HI_SHIFT (24) /* Bit 24: Output Compare 6 Mode, bits [3] */ -#define TIM1_CCMR3_OC6M_BITS(h,l) (((h) << TIM1_CCMR3_OC6M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC6M_LO_SHIFT)) -#define TIM1_CCMR3_OC6M_MASK TIM1_CCMR3_OC6M_BITS(0x1, 0x7) -# define TIM1_CCMR3_OC6M_FRZN TIM1_CCMR3_OC6M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM1_CCMR3_OC6M_CHACT TIM1_CCMR3_OC6M_BITS(0x0, 0x1) /* 0,001: Channel 6 active on match */ -# define TIM1_CCMR3_OC6M_CHINACT TIM1_CCMR3_OC6M_BITS(0x0, 0x2) /* 0,010: Channel 6 inactive on match */ -# define TIM1_CCMR3_OC6M_OCREFTOG TIM1_CCMR3_OC6M_BITS(0x0, 0x3) /* 0,011: OC6REF toggle TIM_CNT=TIM_CCR6 */ -# define TIM1_CCMR3_OC6M_OCREFLO TIM1_CCMR3_OC6M_BITS(0x0, 0x4) /* 0,100: OC6REF forced low */ -# define TIM1_CCMR3_OC6M_OCREFHI TIM1_CCMR3_OC6M_BITS(0x0, 0x5) /* 0,101: OC6REF forced high */ -# define TIM1_CCMR3_OC6M_PWM1 TIM1_CCMR3_OC6M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM1_CCMR3_OC6M_PWM2 TIM1_CCMR3_OC6M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM1_CCMR3_OC6M_OPM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM1_CCMR3_OC6M_OPM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM1_CCMR3_OC6M_COMBINED1 TIM1_CCMR3_OC6M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM1_CCMR3_OC6M_COMBINED2 TIM1_CCMR3_OC6M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM1_CCMR3_OC6M_ASYMM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM1_CCMR3_OC6M_ASYMM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM1_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 6 Clear Enable */ - -#define TIM2_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM2_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM2_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM2_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM2_CCMR1_OC1M_BITS(h,l) (((h) << TIM2_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC1M_LO_SHIFT)) -#define TIM2_CCMR1_OC1M_MASK TIM2_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM2_CCMR1_OC1M_FRZN TIM2_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR1_OC1M_CHACT TIM2_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM2_CCMR1_OC1M_CHINACT TIM2_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM2_CCMR1_OC1M_OCREFTOG TIM2_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM2_CCMR1_OC1M_OCREFLO TIM2_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM2_CCMR1_OC1M_OCREFHI TIM2_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM2_CCMR1_OC1M_PWM1 TIM2_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR1_OC1M_PWM2 TIM2_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR1_OC1M_OPM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR1_OC1M_OPM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR1_OC1M_COMBINED1 TIM2_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR1_OC1M_COMBINED2 TIM2_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR1_OC1M_ASYMM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR1_OC1M_ASYMM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */ - -#define TIM2_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */ -#define TIM2_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */ -#define TIM2_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */ -#define TIM2_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */ -#define TIM2_CCMR1_OC2M_BITS(h,l) (((h) << TIM2_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC2M_LO_SHIFT)) -#define TIM2_CCMR1_OC2M_MASK TIM2_CCMR1_OC2M_BITS(0x1, 0x7) -# define TIM2_CCMR1_OC2M_FRZN TIM2_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR1_OC2M_CHACT TIM2_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */ -# define TIM2_CCMR1_OC2M_CHINACT TIM2_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */ -# define TIM2_CCMR1_OC2M_OCREFTOG TIM2_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */ -# define TIM2_CCMR1_OC2M_OCREFLO TIM2_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */ -# define TIM2_CCMR1_OC2M_OCREFHI TIM2_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */ -# define TIM2_CCMR1_OC2M_PWM1 TIM2_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR1_OC2M_PWM2 TIM2_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR1_OC2M_OPM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR1_OC2M_OPM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR1_OC2M_COMBINED1 TIM2_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR1_OC2M_COMBINED2 TIM2_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR1_OC2M_ASYMM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR1_OC2M_ASYMM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */ - -#define TIM2_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */ -#define TIM2_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */ -#define TIM2_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */ -#define TIM2_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */ -#define TIM2_CCMR2_OC3M_BITS(h,l) (((h) << TIM2_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC3M_LO_SHIFT)) -#define TIM2_CCMR2_OC3M_MASK TIM2_CCMR2_OC3M_BITS(0x1, 0x7) -# define TIM2_CCMR2_OC3M_FRZN TIM2_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR2_OC3M_CHACT TIM2_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */ -# define TIM2_CCMR2_OC3M_CHINACT TIM2_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */ -# define TIM2_CCMR2_OC3M_OCREFTOG TIM2_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */ -# define TIM2_CCMR2_OC3M_OCREFLO TIM2_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */ -# define TIM2_CCMR2_OC3M_OCREFHI TIM2_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */ -# define TIM2_CCMR2_OC3M_PWM1 TIM2_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR2_OC3M_PWM2 TIM2_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR2_OC3M_OPM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR2_OC3M_OPM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR2_OC3M_COMBINED1 TIM2_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR2_OC3M_COMBINED2 TIM2_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR2_OC3M_ASYMM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR2_OC3M_ASYMM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */ - -#define TIM2_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */ -#define TIM2_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */ -#define TIM2_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */ -#define TIM2_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */ -#define TIM2_CCMR2_OC4M_BITS(h,l) (((h) << TIM2_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC4M_LO_SHIFT)) -#define TIM2_CCMR2_OC4M_MASK TIM2_CCMR2_OC4M_BITS(0x1, 0x7) -# define TIM2_CCMR2_OC4M_FRZN TIM2_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM2_CCMR2_OC4M_CHACT TIM2_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */ -# define TIM2_CCMR2_OC4M_CHINACT TIM2_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */ -# define TIM2_CCMR2_OC4M_OCREFTOG TIM2_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */ -# define TIM2_CCMR2_OC4M_OCREFLO TIM2_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */ -# define TIM2_CCMR2_OC4M_OCREFHI TIM2_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */ -# define TIM2_CCMR2_OC4M_PWM1 TIM2_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM2_CCMR2_OC4M_PWM2 TIM2_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ -# define TIM2_CCMR2_OC4M_OPM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */ -# define TIM2_CCMR2_OC4M_OPM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */ -# define TIM2_CCMR2_OC4M_COMBINED1 TIM2_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */ -# define TIM2_CCMR2_OC4M_COMBINED2 TIM2_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */ -# define TIM2_CCMR2_OC4M_ASYMM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */ -# define TIM2_CCMR2_OC4M_ASYMM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */ - -#define TIM2_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */ - -#define TIM16_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM16_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM16_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM16_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM16_CCMR1_OC1M_BITS(h,l) (((h) << TIM16_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM16_CCMR1_OC1M_LO_SHIFT)) -#define TIM16_CCMR1_OC1M_MASK TIM16_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM16_CCMR1_OC1M_FRZN TIM16_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM16_CCMR1_OC1M_CHACT TIM16_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM16_CCMR1_OC1M_CHINACT TIM16_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM16_CCMR1_OC1M_OCREFTOG TIM16_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM16_CCMR1_OC1M_OCREFLO TIM16_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM16_CCMR1_OC1M_OCREFHI TIM16_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM16_CCMR1_OC1M_PWM1 TIM16_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM16_CCMR1_OC1M_PWM2 TIM16_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ - -#define TIM17_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */ -#define TIM17_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */ -#define TIM17_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */ -#define TIM17_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */ -#define TIM17_CCMR1_OC1M_BITS(h,l) (((h) << TIM17_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM17_CCMR1_OC1M_LO_SHIFT)) -#define TIM17_CCMR1_OC1M_MASK TIM17_CCMR1_OC1M_BITS(0x1, 0x7) -# define TIM17_CCMR1_OC1M_FRZN TIM17_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */ -# define TIM17_CCMR1_OC1M_CHACT TIM17_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */ -# define TIM17_CCMR1_OC1M_CHINACT TIM17_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */ -# define TIM17_CCMR1_OC1M_OCREFTOG TIM17_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */ -# define TIM17_CCMR1_OC1M_OCREFLO TIM17_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */ -# define TIM17_CCMR1_OC1M_OCREFHI TIM17_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */ -# define TIM17_CCMR1_OC1M_PWM1 TIM17_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */ -# define TIM17_CCMR1_OC1M_PWM2 TIM17_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */ - -/* Capture/compare mode registers -- Input Capture mode */ - -#define TIM1_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM1_CCMR1_IC1PSC_MASK (0x3 << TIM1_CCMR1_IC1PSC_SHIFT) -# define TIM1_CCMR1_IC1PSC_NOPSC (0x0 << TIM1_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR1_IC1PSC_EVERY2 (0x1 << TIM1_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR1_IC1PSC_EVERY4 (0x2 << TIM1_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR1_IC1PSC_EVERY8 (0x3 << TIM1_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) -# define TIM1_CCMR1_IC2PSC_NOPSC (0x0 << TIM1_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR1_IC2PSC_EVERY2 (0x1 << TIM1_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR1_IC2PSC_EVERY4 (0x2 << TIM1_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR1_IC2PSC_EVERY8 (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) -# define TIM1_CCMR2_IC3PSC_NOPSC (0x0 << TIM1_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR2_IC3PSC_EVERY2 (0x1 << TIM1_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR2_IC3PSC_EVERY4 (0x2 << TIM1_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR2_IC3PSC_EVERY8 (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) -# define TIM1_CCMR2_IC4PSC_NOPSC (0x0 << TIM1_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM1_CCMR2_IC4PSC_EVERY2 (0x1 << TIM1_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM1_CCMR2_IC4PSC_EVERY4 (0x2 << TIM1_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM1_CCMR2_IC4PSC_EVERY8 (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) -# define TIM2_CCMR1_IC1PSC_NOPSC (0x0 << TIM2_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR1_IC1PSC_EVERY2 (0x1 << TIM2_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR1_IC1PSC_EVERY4 (0x2 << TIM2_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR1_IC1PSC_EVERY8 (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ -#define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) -# define TIM2_CCMR1_IC2PSC_NOPSC (0x0 << TIM2_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR1_IC2PSC_EVERY2 (0x1 << TIM2_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR1_IC2PSC_EVERY4 (0x2 << TIM2_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR1_IC2PSC_EVERY8 (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ -#define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ -#define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) -# define TIM2_CCMR2_IC3PSC_NOPSC (0x0 << TIM2_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR2_IC3PSC_EVERY2 (0x1 << TIM2_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR2_IC3PSC_EVERY4 (0x2 << TIM2_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR2_IC3PSC_EVERY8 (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ -#define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ -#define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) -# define TIM2_CCMR2_IC4PSC_NOPSC (0x0 << TIM2_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM2_CCMR2_IC4PSC_EVERY2 (0x1 << TIM2_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM2_CCMR2_IC4PSC_EVERY4 (0x2 << TIM2_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM2_CCMR2_IC4PSC_EVERY8 (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ -#define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) -# define TIM16_CCMR1_IC1PSC_NOPSC (0x0 << TIM16_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM16_CCMR1_IC1PSC_EVERY2 (0x1 << TIM16_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM16_CCMR1_IC1PSC_EVERY4 (0x2 << TIM16_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM16_CCMR1_IC1PSC_EVERY8 (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ -#define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) -# define TIM17_CCMR1_IC1PSC_NOPSC (0x0 << TIM17_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */ -# define TIM17_CCMR1_IC1PSC_EVERY2 (0x1 << TIM17_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */ -# define TIM17_CCMR1_IC1PSC_EVERY4 (0x2 << TIM17_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */ -# define TIM17_CCMR1_IC1PSC_EVERY8 (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */ - -#define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ -#define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -/* Capture/compare enable register */ - -#define TIM1_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM1_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM1_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM1_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ -#define TIM1_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define TIM1_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */ -#define TIM1_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable */ -#define TIM1_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */ -#define TIM1_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define TIM1_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */ -#define TIM1_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable */ -#define TIM1_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */ -#define TIM1_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define TIM1_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */ -#define TIM1_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */ -#define TIM1_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */ -#define TIM1_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output polarity */ -#define TIM1_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */ -#define TIM1_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output polarity */ - -#define TIM2_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM2_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM2_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ -#define TIM2_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */ -#define TIM2_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */ -#define TIM2_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */ -#define TIM2_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */ -#define TIM2_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */ -#define TIM2_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */ -#define TIM2_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */ -#define TIM2_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */ -#define TIM2_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */ - -#define TIM16_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM16_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM16_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM16_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ - -#define TIM17_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */ -#define TIM17_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */ -#define TIM17_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */ -#define TIM17_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */ - -/* Counter register */ - -#define TIM1_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM1_CNT_MASK (0xffff << TIM1_CNT_SHIFT) -#define TIM1_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -#define TIM2_CNT_SHIFT (0) /* Bits 0-32: Timer counter value, UIFREMAP = 0 */ - /* Bits 0-31: Timer counter value, UIFREMAP = 1 */ -#define TIM2_CNT_MASK (0xffffffff << TIM2_CNT_SHIFT) -#define TIM2_CNT_MASK31 (0x7fffffff << TIM2_CNT_SHIFT) - -#define TIM2_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy, if UIFREMAP = 1 */ - -#define TIM16_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM16_CNT_MASK (0xffff << TIM16_CNT_SHIFT) -#define TIM16_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -#define TIM17_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */ -#define TIM17_CNT_MASK (0xffff << TIM17_CNT_SHIFT) -#define TIM17_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ - -/* Prescaler register */ - -#define TIM1_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM1_PSC_MASK (0xffff << TIM1_PSC_SHIFT) - -#define TIM2_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM2_PSC_MASK (0xffff << TIM2_PSC_SHIFT) - -#define TIM16_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM16_PSC_MASK (0xffff << TIM16_PSC_SHIFT) - -#define TIM17_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */ -#define TIM17_PSC_MASK (0xffff << TIM17_PSC_SHIFT) - -/* Auto-reload register */ - -#define TIM1_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM1_ARR_MASK (0xffff << TIM1_ARR_SHIFT) - -#define TIM2_ARR_SHIFT (0) /* Bits 0-31: Timer auto-reload value */ -#define TIM2_ARR_MASK (0xffffffff << TIM2_ARR_SHIFT) - -#define TIM16_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM16_ARR_MASK (0xffff << TIM16_ARR_SHIFT) - -#define TIM17_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */ -#define TIM17_ARR_MASK (0xffff << TIM17_ARR_SHIFT) - -/* Repetition counter register */ - -#define TIM1_RCR_SHIFT (0) /* Bits 0-15: Repetition Counter Value */ -#define TIM1_RCR_MASK (0xffff << TIM1_RCR_SHIFT) - -#define TIM16_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define TIM16_RCR_MASK (0xff << TIM16_RCR_SHIFT) - -#define TIM17_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */ -#define TIM17_RCR_MASK (0xff << TIM17_RCR_SHIFT) - -/* Capture/compare registers */ - -#define TIM1_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM1_CCR1_MASK (0xffff << TIM1_CCR1_SHIFT) -#define TIM1_CCR2_SHIFT (0) /* Bits 0-15: Capture/Compare 2 value */ -#define TIM1_CCR2_MASK (0xffff << TIM1_CCR2_SHIFT) -#define TIM1_CCR3_SHIFT (0) /* Bits 0-15: Capture/Compare 3 value */ -#define TIM1_CCR3_MASK (0xffff << TIM1_CCR3_SHIFT) -#define TIM1_CCR4_SHIFT (0) /* Bits 0-15: Capture/Compare 4 value */ -#define TIM1_CCR4_MASK (0xffff << TIM1_CCR4_SHIFT) -#define TIM1_CCR5_SHIFT (0) /* Bits 0-15: Capture/Compare 5 value */ -#define TIM1_CCR5_MASK (0xffff << TIM1_CCR5_SHIFT) -#define TIM1_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */ -#define TIM1_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */ -#define TIM1_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */ -#define TIM1_CCR6_SHIFT (0) /* Bits 0-15: Capture/Compare 6 value */ -#define TIM1_CCR6_MASK (0xffff << TIM1_CCR6_SHIFT) - -#define TIM2_CCR1_SHIFT (0) /* Bits 0-31: Capture/Compare 1 value */ -#define TIM2_CCR1_MASK (0xffffffff << TIM2_CCR1_SHIFT) -#define TIM2_CCR2_SHIFT (0) /* Bits 0-31: Capture/Compare 2 value */ -#define TIM2_CCR2_MASK (0xffffffff << TIM2_CCR2_SHIFT) -#define TIM2_CCR3_SHIFT (0) /* Bits 0-31: Capture/Compare 3 value */ -#define TIM2_CCR3_MASK (0xffffffff << TIM2_CCR3_SHIFT) -#define TIM2_CCR4_SHIFT (0) /* Bits 0-31: Capture/Compare 4 value */ -#define TIM2_CCR4_MASK (0xffffffff << TIM2_CCR4_SHIFT) - -#define TIM16_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM16_CCR1_MASK (0xffff << TIM16_CCR1_SHIFT) - -#define TIM17_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */ -#define TIM17_CCR1_MASK (0xffff << TIM17_CCR1_SHIFT) - -/* Break and dead-time register */ - -#define TIM1_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM1_BDTR_DTG_MASK (0xff << TIM1_BDTR_DTG_SHIFT) -#define TIM1_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM1_BDTR_LOCK_MASK (0x3 << TIM1_BDTR_LOCK_SHIFT) -# define TIM1_BDTR_LOCKOFF (0x0 << TIM1_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM1_BDTR_LOCK1 (0x1 << TIM1_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM1_BDTR_LOCK2 (0x2 << TIM1_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM1_BDTR_LOCK3 (0x3 << TIM1_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM1_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM1_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM1_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM1_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM1_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ -#define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ -#define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ - -#define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ -#define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ -#define TIM1_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM1_BDTR_BK2DSRM (1 << 27) /* Bit 27: Break 2 Disarm */ -#define TIM1_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ -#define TIM1_BDTR_BK2BID (1 << 29) /* Bit 29: Break 2 Bidirectional */ - -#define TIM16_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM16_BDTR_DTG_MASK (0xff << TIM16_BDTR_DTG_SHIFT) -#define TIM16_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM16_BDTR_LOCK_MASK (0x3 << TIM16_BDTR_LOCK_SHIFT) -# define TIM16_BDTR_LOCKOFF (0x0 << TIM16_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM16_BDTR_LOCK1 (0x1 << TIM16_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM16_BDTR_LOCK2 (0x2 << TIM16_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM16_BDTR_LOCK3 (0x3 << TIM16_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM16_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM16_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM16_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM16_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM16_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM16_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM16_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM16_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ - -#define TIM17_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */ -#define TIM17_BDTR_DTG_MASK (0xff << TIM17_BDTR_DTG_SHIFT) -#define TIM17_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */ -#define TIM17_BDTR_LOCK_MASK (0x3 << TIM17_BDTR_LOCK_SHIFT) -# define TIM17_BDTR_LOCKOFF (0x0 << TIM17_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */ -# define TIM17_BDTR_LOCK1 (0x1 << TIM17_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */ -# define TIM17_BDTR_LOCK2 (0x2 << TIM17_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */ -# define TIM17_BDTR_LOCK3 (0x3 << TIM17_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ - -#define TIM17_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */ -#define TIM17_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */ -#define TIM17_BDTR_BKE (1 << 12) /* Bit 12: Break enable */ -#define TIM17_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */ -#define TIM17_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */ -#define TIM17_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ -#define TIM17_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */ -#define TIM17_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */ - -/* DMA control register */ - -#define TIM1_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM1_DCR_DBA_MASK (0x1f << TIM1_DCR_DBA_SHIFT) -#define TIM1_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM1_DCR_DBL_MASK (0x1f << TIM1_DCR_DBL_SHIFT) -# define TIM1_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM2_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM2_DCR_DBA_MASK (0x1f << TIM2_DCR_DBA_SHIFT) -#define TIM2_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM2_DCR_DBL_MASK (0x1f << TIM2_DCR_DBL_SHIFT) -# define TIM2_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM16_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM16_DCR_DBA_MASK (0x1f << TIM16_DCR_DBA_SHIFT) -#define TIM16_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM16_DCR_DBL_MASK (0x1f << TIM16_DCR_DBL_SHIFT) -# define TIM16_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -#define TIM17_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */ -#define TIM17_DCR_DBA_MASK (0x1f << TIM17_DCR_DBA_SHIFT) -#define TIM17_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */ -#define TIM17_DCR_DBL_MASK (0x1f << TIM17_DCR_DBL_SHIFT) -# define TIM17_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */ - -/* DMA address register */ - -#define TIM1_DMAR_SHIFT (0) /* Bits 0-31: DMA register for burst accesses */ -#define TIM1_DMAR_MASK (0xffffffff << TIM1_DMAR_SHIFT) - -#define TIM2_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM2_DMAR_MASK (0xffff << TIM2_DMAR_SHIFT) - -#define TIM16_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM16_DMAR_MASK (0xffff << TIM16_DMAR_SHIFT) - -#define TIM17_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */ -#define TIM17_DMAR_MASK (0xffff << TIM17_DMAR_SHIFT) - -/* Option register 1 */ - -#define TIM1_OR1_ETR_ADC_RMP_SHIFT (0) /* Bits 0-1: TIM1 ETR to ADC AWD remap */ -#define TIM1_OR1_ETR_ADC_RMP_MASK (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT) -# define TIM1_OR1_ETR_ADC_RMP_NC (0x0 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 00: ETR not connected to ADC AWD */ -# define TIM1_OR1_ETR_ADC_RMP_AWD1 (0x1 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 01: ETR connected to ADC AWD1 */ -# define TIM1_OR1_ETR_ADC_RMP_AWD2 (0x2 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 10: ETR connected to ADC AWD2 */ -# define TIM1_OR1_ETR_ADC_RMP_AWD3 (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 11: ETR connected to ADC AWD3 */ - -#define TIM1_OR1_TI1_RMP (1 << 4) /* Bit 4: Input capture 1 remap */ -# define TIM1_OR1_TI1_RMP_IO (0 << 4) /* 0: TIM1 Input capture 1 is connected to I/O */ -# define TIM1_OR1_TI1_RMP_CMP1OUT (1 << 4) /* 1: TIM1 Input capture 1 is connected to COMP1 output */ - -#define TIM2_OR1_ITR_RMP (1 << 0) /* Bit 0: Internal trigger remap */ -# define TIM2_OR1_ITR_RMP_NC (0 << 0) /* 0: TIM2 Internal trigger ITR2 is not connected */ -# define TIM2_OR1_ITR_RMP_USB_SOF (1 << 0) /* 1: TIM2 Internal trigger ITR2 is connected to USB SOF */ - -#define TIM2_OR1_ETR_RMP (1 << 1) /* Bit 1: External trigger 1 remap */ -# define TIM2_OR1_ETR_RMP_GPIO (0 << 1) /* 0: TIM2 ETR2 is connected to GPIO */ -# define TIM2_OR1_ETR_RMP_LSE (1 << 1) /* 1: LSE internal clock is connected to TIM2 ETR */ - -#define TIM2_OR1_TI4_RMP_SHIFT (2) /* Bits 2-3: Timer input 4 remap */ -#define TIM2_OR1_TI4_RMP_MASK (0x3 << TIM2_OR1_TI4_RMP_SHIFT) -# define TIM2_OR1_TI4_RMP_GPIO (0x0 << TIM2_OR1_TI4_RMP_SHIFT) /* 00: TI4 connected to GPIO */ -# define TIM2_OR1_TI4_RMP_CMP1OUT (0x1 << TIM2_OR1_TI4_RMP_SHIFT) /* 01: TI4 connected to COMP1 output */ -# define TIM2_OR1_TI4_RMP_CMP2OUT (0x2 << TIM2_OR1_TI4_RMP_SHIFT) /* 10: TI4 connected to COMP2 output */ -# define TIM2_OR1_TI4_RMP_CMP1CMP2 (0x3 << TIM2_OR1_TI4_RMP_SHIFT) /* 11: TI4 connected to OR between COMP1-2 */ - -#define TIM16_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM16 input 1 connection */ -#define TIM16_OR1_TI1_RMP_MASK (0x3 << TIM16_OR1_TI1_RMP_SHIFT) -# define TIM16_OR1_TI1_RMP_GPIO (0x0 << TIM16_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */ -# define TIM16_OR1_TI1_RMP_LSI (0x1 << TIM16_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to LSI */ -# define TIM16_OR1_TI1_RMP_LSE (0x2 << TIM16_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to LSE */ -# define TIM16_OR1_TI1_RMP_RTCWKUP (0x3 << TIM16_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to RTC wake-up interrupt */ - -#define TIM17_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM17 input 1 connection */ -#define TIM17_OR1_TI1_RMP_MASK (0x3 << TIM17_OR1_TI1_RMP_SHIFT) -# define TIM17_OR1_TI1_RMP_GPIO (0x0 << TIM17_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */ -# define TIM17_OR1_TI1_RMP_MSI (0x1 << TIM17_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to MSI */ -# define TIM17_OR1_TI1_RMP_HSEd32 (0x2 << TIM17_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to HSE/32 */ -# define TIM17_OR1_TI1_RMP_MCO (0x3 << TIM17_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to MCO */ - -/* Alternate function registers */ - -#define TIM1_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM1_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM1_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM1_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM1_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM1_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ -#define TIM1_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ -#define TIM1_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_SHIFT) -# define TIM1_AF1_ETRSEL_LEGACY (0x0 << TIM1_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */ -# define TIM1_AF1_ETRSEL_CMP1OUT (0x1 << TIM1_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */ -# define TIM1_AF1_ETRSEL_CMP2OUT (0x2 << TIM1_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */ - -#define TIM1_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ -#define TIM1_AF2_BK2CMP1E (1 << 1) /* Bit 1: BRK2 COMP1 enable */ -#define TIM1_AF2_BK2CMP2E (1 << 2) /* Bit 2: BRK2 COMP2 enable */ -#define TIM1_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN input polarity */ -#define TIM1_AF2_BK2CMP1P (1 << 10) /* Bit 10: BRK2 COMP1 input polarity */ -#define TIM1_AF2_BK2CMP2P (1 << 11) /* Bit 11: BRK2 COMP2 input polarity */ - -#define TIM2_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */ -#define TIM2_AF1_ETRSEL_MASK (0xf << TIM2_AF1_ETRSEL_SHIFT) -# define TIM2_AF1_ETRSEL_GPIO_LSE (0x0 << TIM2_AF1_ETRSEL_SHIFT) /* 0000: GPIO or LSE clock */ -# define TIM2_AF1_ETRSEL_CMP1OUT (0x1 << TIM2_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */ -# define TIM2_AF1_ETRSEL_CMP2OUT (0x2 << TIM2_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */ - -#define TIM16_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM16_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM16_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM16_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM16_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM16_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ - -#define TIM17_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */ -#define TIM17_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */ -#define TIM17_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */ -#define TIM17_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */ -#define TIM17_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */ -#define TIM17_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */ - -/* Timer input selection register */ - -#define TIM1_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM1_TISEL_TI1SEL_MASK (0xf << TIM1_TISEL_TI1SEL_SHIFT) -# define TIM1_TISEL_TI1SEL_CH1 (0x0 << TIM1_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM1_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */ -#define TIM1_TISEL_TI2SEL_MASK (0xf << TIM1_TISEL_TI2SEL_SHIFT) -# define TIM1_TISEL_TI2SEL_CH2 (0x0 << TIM1_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */ - -#define TIM1_TISEL_TI3SEL_SHIFT (16) /* Bits 16-19: selects TI3[0] to TI3[15] input */ -#define TIM1_TISEL_TI3SEL_MASK (0xf << TIM1_TISEL_TI3SEL_SHIFT) -# define TIM1_TISEL_TI3SEL_CH3 (0x0 << TIM1_TISEL_TI3SEL_SHIFT) /* 0000: CH3 input */ - -#define TIM1_TISEL_TI4SEL_SHIFT (24) /* Bits 24-27: selects TI4[0] to TI4[15] input */ -#define TIM1_TISEL_TI4SEL_MASK (0xf << TIM1_TISEL_TI4SEL_SHIFT) -# define TIM1_TISEL_TI4SEL_CH4 (0x0 << TIM1_TISEL_TI4SEL_SHIFT) /* 0000: CH4 input */ - -#define TIM2_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM2_TISEL_TI1SEL_MASK (0xf << TIM2_TISEL_TI1SEL_SHIFT) -# define TIM2_TISEL_TI1SEL_CH1 (0x0 << TIM2_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM2_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */ -#define TIM2_TISEL_TI2SEL_MASK (0xf << TIM2_TISEL_TI2SEL_SHIFT) -# define TIM2_TISEL_TI2SEL_CH2 (0x0 << TIM2_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */ - -#define TIM16_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM16_TISEL_TI1SEL_MASK (0xf << TIM16_TISEL_TI1SEL_SHIFT) -# define TIM16_TISEL_TI1SEL_CH1 (0x0 << TIM16_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#define TIM17_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */ -#define TIM17_TISEL_TI1SEL_MASK (0xf << TIM17_TISEL_TI1SEL_SHIFT) -# define TIM17_TISEL_TI1SEL_CH1 (0x0 << TIM17_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */ - -#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32.h b/arch/arm/src/stm32wb/stm32.h index ef7f8b5db4872..f993e85946f46 100644 --- a/arch/arm/src/stm32wb/stm32.h +++ b/arch/arm/src/stm32wb/stm32.h @@ -37,6 +37,8 @@ /* Peripherals **************************************************************/ #include "chip.h" +#include "stm32wb_rcc.h" +#include "stm32wb_gpio.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c deleted file mode 100644 index 22402ed4da183..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ /dev/null @@ -1,1289 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32.h" -#include "stm32wb_tim.h" -#include "stm32wb_gpio.h" -#include "stm32wb_rcc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. - * Such special purposes include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may also - * be defined to indicate that the timer is intended to be used for pulsed - * output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ - defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ - defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ - defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ - defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setfreq = stm32_tim_setfreq, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .getwidth = stm32_tim_getwidth, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, - .dump_regs = stm32_tim_dumpregs, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the STM32WB - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2. - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the STM32WB - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2. - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); - - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_dumpregs - ****************************************************************************/ - -static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) -{ - struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; - - ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), - stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) - ); - ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(dev, STM32_TIM_SR_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) - ); - ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), - stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), - stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), - stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) - ); - ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), - stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) - ); - - if (priv->base == STM32_TIM1_BASE) - { - ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); - } - else - { - ainfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); - } -} - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val; - - DEBUGASSERT(dev != NULL); - - /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ - -#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) - if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) - { -#if defined(CONFIG_STM32_TIM16) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) - { - return -EINVAL; - } -#endif - -#if defined(CONFIG_STM32_TIM17) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) - { - return -EINVAL; - } -#endif - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_UP: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - break; - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) - case STM32_TIM_MODE_DOWN: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; - break; - - case STM32_TIM_MODE_UPDOWN: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; - - /* Our default: - * Interrupts are generated on compare, when counting down - */ - - break; -#endif - - case STM32_TIM_MODE_PULSE: - val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); - -#ifdef CONFIG_STM32_TIM1 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) - { - stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setfreq - ****************************************************************************/ - -static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - uint32_t reload; - uint32_t timclk; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - * - * Calculate optimal values for the timer prescaler and for the timer - * reload register. If freq is the desired frequency, then - * - * reload = timclk / freq - * reload = (pclck / prescaler) / freq - * - * There are many solutions to do this, but the best solution will be the - * one that has the largest reload value and the smallest prescaler value. - * That is the solution that should give us the most accuracy in the timer - * control. Subject to: - * - * 0 <= prescaler <= 65536 - * 1 <= reload <= 65535 - * - * So ( prescaler = pclck / 65535 / freq ) would be optimal. - */ - - prescaler = (freqin / freq + 65534) / 65535; - - /* We need to decrement value for '1', but only if that will not to - * cause underflow. - */ - - if (prescaler < 1) - { - awarn("WARNING: Prescaler underflowed.\n"); - prescaler = 1; - } - - /* Check for overflow as well. */ - - if (prescaler > 65536) - { - awarn("WARNING: Prescaler overflowed.\n"); - prescaler = 65536; - } - - timclk = freqin / prescaler; - - reload = timclk / freq; - if (reload < 1) - { - awarn("WARNING: Reload value underflowed.\n"); - reload = 1; - } - else if (reload > 65535) - { - awarn("WARNING: Reload value overflowed.\n"); - reload = 65535; - } - - /* Set the reload and prescaler values */ - - stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); - stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); - - return (timclk / reload); -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); - - /* TIM2 is a 32-bit timer. */ - -#if defined(CONFIG_STM32_TIM2) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return counter; - } -#endif - - return counter & 0x0000ffff; -} - -/**************************************************************************** - * Name: stm32_tim_getwidth - ****************************************************************************/ - -static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) -{ - /* Only TIM2 is a 32-bit timer. */ - -#if defined(CONFIG_STM32_TIM2) - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) - { - return 32; - } -#endif - - /* All others are 16-bit timers. */ - - return 16; -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 3) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); - ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); - ccer_val |= GTIM_CCER_CCXE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CCXP(channel); - } - - if (channel > 1) - { - ccmr_offset = STM32_TIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); - return (regval & source) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h deleted file mode 100644 index e928d3e6ddd9b..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ /dev/null @@ -1,254 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32WB_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32wb_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Generalized register definitions */ - -#define GTIM_CR1_CEN TIM1_CR1_CEN -#define GTIM_CR1_OPM TIM1_CR1_OPM -#define GTIM_CR1_ARPE TIM1_CR1_ARPE -#define GTIM_DIER_UIE TIM1_DIER_UIE -#define GTIM_SR_UIF TIM1_SR_UIF -#define GTIM_EGR_UG TIM1_EGR_UG -#define TIM_1_2_CR1_DIR TIM1_CR1_DIR -#define TIM_1_2_CR1_CMS_CNTR1 TIM1_CR1_CMS_CNTR1 - -#define GTIM_CCER_CCX_SHIFT(ch) ((ch) << 2) /* 4-bits shift - * per channel */ -#define GTIM_CCMR_OCX_SHIFT(ch) (((ch) & 0x1) << 3) /* 8-bits shift - * per channel */ - -#define GTIM_CCER_CCXE(ch) (TIM1_CCER_CC1E << GTIM_CCER_CCX_SHIFT(ch)) -#define GTIM_CCER_CCXP(ch) (TIM1_CCER_CC1P << GTIM_CCER_CCX_SHIFT(ch)) -#define GTIM_CCMR_OCXPE(ch) (TIM1_CCMR1_OC1PE << GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_MASK(ch) (TIM1_CCMR1_OC1M_MASK << \ - GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_FRZN(ch) (TIM1_CCMR1_OC1M_FRZN << \ - GTIM_CCMR_OCX_SHIFT(ch)) -#define GTIM_CCMR_OCXM_PWM1(ch) (TIM1_CCMR1_OC1M_PWM1 << \ - GTIM_CCMR_OCX_SHIFT(ch)) - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active - * high when counter < compare - */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif - - /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ - -#if 0 - STM32_TIM_CH_INCAPTURE = 0x10, - STM32_TIM_CH_INPWM = 0x20 - STM32_TIM_CH_DRIVE_OC /* Open collector mode */ -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); - - /* Debug */ - - void (*dump_regs)(struct stm32_tim_dev_s *dev); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c deleted file mode 100644 index 38e8db5b4aabb..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ /dev/null @@ -1,488 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include - -#include "stm32wb_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index ee8a4d6b07d13..2fc5af18c597d 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -34,7 +34,6 @@ set(SRCS stm32wl5_lse.c stm32wl5_idle.c stm32wl5_pwr.c - stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c stm32wl5_spi.c) diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index 200082d446380..d38f6c0ae48ab 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -34,7 +34,7 @@ CHIP_CSRCS += stm32wl5_allocateheap.c stm32wl5_exti_gpio.c stm32wl5_gpio.c CHIP_CSRCS += stm32wl5_irq.c stm32wl5_lowputc.c stm32wl5_rcc.c CHIP_CSRCS += stm32wl5_serial.c stm32wl5_start.c CHIP_CSRCS += stm32wl5_lse.c stm32wl5_idle.c -CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c +CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c diff --git a/arch/arm/src/stm32wl5/stm32.h b/arch/arm/src/stm32wl5/stm32.h index 3fe581bc7f3d3..9b0cc0a7ff49c 100644 --- a/arch/arm/src/stm32wl5/stm32.h +++ b/arch/arm/src/stm32wl5/stm32.h @@ -43,7 +43,6 @@ #include "stm32wl5_pwr.h" #include "stm32wl5_rcc.h" #include "stm32wl5_spi.h" -#include "stm32wl5_tim.h" #include "stm32wl5_uart.h" /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c deleted file mode 100644 index 56bcfa281f6a2..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ /dev/null @@ -1,1697 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" - -#include "stm32.h" -#include "stm32wl5_gpio.h" -#include "stm32wl5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Timer devices may be used for different purposes. Such special purposes - * include: - * - * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM may - * also be defined to indicate that the timer is intended to be used for - * pulsed output modulation. - * - * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is - * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate - * that timer "n" is intended to be used for that purpose. - * - * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined - * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that - * timer "n" is intended to be used for that purpose. - * - * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then - * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer "n" - * is intended to be used for that purpose. - * - * In any of these cases, the timer will not be used by this timer module. - */ - -#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ - defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) -# undef CONFIG_STM32_TIM1 -#endif - -#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ - defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) -# undef CONFIG_STM32_TIM2 -#endif - -#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ - defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) -# undef CONFIG_STM32_TIM3 -#endif - -#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ - defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) -# undef CONFIG_STM32_TIM4 -#endif - -#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ - defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) -# undef CONFIG_STM32_TIM5 -#endif - -#if defined(CONFIG_STM32_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ - defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) -# undef CONFIG_STM32_TIM6 -#endif - -#if defined(CONFIG_STM32_TIM7_PWM) || defined (CONFIG_STM32_TIM7_ADC) || \ - defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) -# undef CONFIG_STM32_TIM7 -#endif - -#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ - defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) -# undef CONFIG_STM32_TIM8 -#endif - -#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ - defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) -# undef CONFIG_STM32_TIM15 -#endif - -#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32_TIM16_ADC) || \ - defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) -# undef CONFIG_STM32_TIM16 -#endif - -#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32_TIM17_ADC) || \ - defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) -# undef CONFIG_STM32_TIM17 -#endif - -#if defined(CONFIG_STM32_TIM1) -# if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ - defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) -# define HAVE_TIM1_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM2) -# if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ - defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) -# define HAVE_TIM2_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM3) -# if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ - defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) -# define HAVE_TIM3_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM4) -# if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ - defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) -# define HAVE_TIM4_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM5) -# if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ - defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) -# define HAVE_TIM5_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM8) -# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ - defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) -# define HAVE_TIM8_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM15) -# if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ - defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) -# define HAVE_TIM15_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM16) -# if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ - defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) -# define HAVE_TIM16_GPIOCONFIG 1 -#endif -#endif - -#if defined(CONFIG_STM32_TIM17) -# if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ - defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) -# define HAVE_TIM17_GPIOCONFIG 1 -#endif -#endif - -/* This module then only compiles if there are enabled timers that are not - * intended for some other purpose. - */ - -#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* TIM Device Structure */ - -struct stm32_tim_priv_s -{ - const struct stm32_tim_ops_s *ops; - enum stm32_tim_mode_e mode; - uint32_t base; /* TIMn base address */ -}; - -/**************************************************************************** - * Private Function prototypes - ****************************************************************************/ - -/* Register helpers */ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value); -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits); -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset); -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value); - -/* Timer helpers */ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); -static void stm32_tim_enable(struct stm32_tim_dev_s *dev); -static void stm32_tim_disable(struct stm32_tim_dev_s *dev); -static void stm32_tim_reset(struct stm32_tim_dev_s *dev); -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode); -#endif - -/* Timer methods */ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq); -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period); -static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode); -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare); -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel); -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source); -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, - int source); -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct stm32_tim_ops_s stm32_tim_ops = -{ - .enable = stm32_tim_enable, - .disable = stm32_tim_disable, - .setmode = stm32_tim_setmode, - .setclock = stm32_tim_setclock, - .getclock = stm32_tim_getclock, - .setperiod = stm32_tim_setperiod, - .getperiod = stm32_tim_getperiod, - .getcounter = stm32_tim_getcounter, - .setchannel = stm32_tim_setchannel, - .setcompare = stm32_tim_setcompare, - .getcapture = stm32_tim_getcapture, - .setisr = stm32_tim_setisr, - .enableint = stm32_tim_enableint, - .disableint = stm32_tim_disableint, - .ackint = stm32_tim_ackint, - .checkint = stm32_tim_checkint, -}; - -#ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; -#endif -#ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Get a 16-bit register value by offset - * - ****************************************************************************/ - -static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Put a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t value) -{ - putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_modifyreg16 - * - * Description: - * Modify a 16-bit register value by offset - * - ****************************************************************************/ - -static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, - uint8_t offset, uint16_t clearbits, - uint16_t setbits) -{ - modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, - setbits); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Get a 32-bit register value by offset. This applies only for the - * STM32WL5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * - ****************************************************************************/ - -static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, - uint8_t offset) -{ - return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Put a 32-bit register value by offset. This applies only for the - * STM32WL5 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 - * - ****************************************************************************/ - -static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, - uint8_t offset, uint32_t value) -{ - putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); -} - -/**************************************************************************** - * Name: stm32_tim_reload_counter - ****************************************************************************/ - -static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); - val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_enable - ****************************************************************************/ - -static void stm32_tim_enable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val |= GTIM_CR1_CEN; - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_disable - ****************************************************************************/ - -static void stm32_tim_disable(struct stm32_tim_dev_s *dev) -{ - uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); - val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -} - -/**************************************************************************** - * Name: stm32_tim_reset - * - * Description: - * Reset timer into system default state, but do not affect output/input - * pins - * - ****************************************************************************/ - -static void stm32_tim_reset(struct stm32_tim_dev_s *dev) -{ - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32_tim_disable(dev); -} - -/**************************************************************************** - * Name: stm32_tim_gpioconfig - ****************************************************************************/ - -#if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ - defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ - defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ - defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ - defined(HAVE_TIM17_GPIOCONFIG) -static void stm32_tim_gpioconfig(uint32_t cfg, - enum stm32_tim_channel_e mode) -{ - /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - - if (mode & STM32_TIM_CH_MODE_MASK) - { - stm32_configgpio(cfg); - } - else - { - stm32_unconfiggpio(cfg); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim_setmode - ****************************************************************************/ - -static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode) -{ - uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; - - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= GTIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= GTIM_CR1_CENTER1; - - /* Our default: Interrupts are generated on compare, when counting - * down - */ - - break; - - case STM32_TIM_MODE_PULSE: - val |= GTIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, - 0, ATIM_BDTR_MOE); - } -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setclock - ****************************************************************************/ - -static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, - uint32_t freq) -{ - uint32_t freqin; - int prescaler; - - DEBUGASSERT(dev != NULL); - - /* Disable Timer? */ - - if (freq == 0) - { - stm32_tim_disable(dev); - return 0; - } - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - - default: - return -EINVAL; - } - - /* Select a pre-scaler value for this timer using the input clock - * frequency. - */ - - prescaler = freqin / freq; - - /* We need to decrement value for '1', but only, if that will not to - * cause underflow. - */ - - if (prescaler > 0) - { - prescaler--; - } - - /* Check for overflow as well. */ - - if (prescaler > 0xffff) - { - prescaler = 0xffff; - } - - stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32_tim_enable(dev); - - return prescaler; -} - -/**************************************************************************** - * Name: stm32_tim_getclock - ****************************************************************************/ - -static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) -{ - uint32_t freqin; - uint32_t clock; - DEBUGASSERT(dev != NULL); - - /* Get the input clock frequency for this timer. These vary with - * different timer clock sources, MCU-specific timer configuration, and - * board-specific clock configuration. The correct input clock frequency - * must be defined in the board.h header file. - */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; - break; -#endif - default: - return -EINVAL; - } - - /* From chip datasheet, at page 1179. */ - - clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); - return clock; -} - -/**************************************************************************** - * Name: stm32_tim_setperiod - ****************************************************************************/ - -static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, - uint32_t period) -{ - DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); -} - -/**************************************************************************** - * Name: stm32_tim_getperiod - ****************************************************************************/ - -static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); -} - -/**************************************************************************** - * Name: stm32_tim_getcounter - ****************************************************************************/ - -static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); - - /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. - * reset it it result when not TIM2 or TIM5. - */ - -#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: -#endif - return counter; - - default: - return counter & 0x0000ffff; - } -#else - return counter & 0x0000ffff; -#endif -} - -/**************************************************************************** - * Name: stm32_tim_setchannel - ****************************************************************************/ - -static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, - uint8_t channel, - enum stm32_tim_channel_e mode) -{ - uint16_t ccmr_orig = 0; - uint16_t ccmr_val = 0; - uint16_t ccmr_mask = 0xff; - uint16_t ccer_val; - uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; - - DEBUGASSERT(dev != NULL); - - /* Further we use range as 0..3; if channel=0 it will also overflow here */ - - if (--channel > 4) - { - return -EINVAL; - } - - /* Assume that channel is disabled and polarity is active high */ - - ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); - ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << - GTIM_CCER_CCXBASE(channel)); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode configuration */ - - switch (mode & STM32_TIM_CH_MODE_MASK) - { - case STM32_TIM_CH_DISABLED: - break; - - case STM32_TIM_CH_OUTPWM: - ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + - GTIM_CCMR1_OC1PE; - ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); - break; - - default: - return -EINVAL; - } - - /* Set polarity */ - - if (mode & STM32_TIM_CH_POLARITY_NEG) - { - ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); - } - - /* Define its position (shift) and get register offset */ - - if (channel & 1) - { - ccmr_val <<= 8; - ccmr_mask <<= 8; - } - - if (channel > 1) - { - ccmr_offset = STM32_GTIM_CCMR2_OFFSET; - } - - ccmr_orig = stm32_getreg16(dev, ccmr_offset); - ccmr_orig &= ~ccmr_mask; - ccmr_orig |= ccmr_val; - stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); - - /* set GPIO */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - switch (channel) - { -#if defined(GPIO_TIM1_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM1_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - switch (channel) - { -#if defined(GPIO_TIM2_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM2_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - switch (channel) - { -#if defined(GPIO_TIM3_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM3_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - switch (channel) - { -#if defined(GPIO_TIM4_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); - break; -#endif -#if defined(GPIO_TIM4_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM4_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - switch (channel) - { -#if defined(GPIO_TIM5_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM5_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - switch (channel) - { -#if defined(GPIO_TIM8_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM8_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - switch (channel) - { -#if defined(GPIO_TIM15_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM15_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - switch (channel) - { -#if defined(GPIO_TIM16_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM16_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - switch (channel) - { -#if defined(GPIO_TIM17_CH1OUT) - case 0: - stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH2OUT) - case 1: - stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH3OUT) - case 2: - stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); - break; -#endif - -#if defined(GPIO_TIM17_CH4OUT) - case 3: - stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); - break; -#endif - - default: - return -EINVAL; - } - break; -#endif - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_setcompare - ****************************************************************************/ - -static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, - uint8_t channel, uint32_t compare) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); - break; - - case 2: - stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); - break; - - case 3: - stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); - break; - - case 4: - stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); - break; - - default: - return -EINVAL; - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_getcapture - ****************************************************************************/ - -static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, - uint8_t channel) -{ - DEBUGASSERT(dev != NULL); - - switch (channel) - { - case 1: - return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); - - case 2: - return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); - - case 3: - return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); - - case 4: - return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); - } - - return -EINVAL; -} - -/**************************************************************************** - * Name: stm32_tim_setisr - ****************************************************************************/ - -static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler, arg); - up_enable_irq(vectorno); - - return OK; -} - -/**************************************************************************** - * Name: stm32_tim_enableint - ****************************************************************************/ - -static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); -} - -/**************************************************************************** - * Name: stm32_tim_disableint - ****************************************************************************/ - -static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, - int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); -} - -/**************************************************************************** - * Name: stm32_tim_ackint - ****************************************************************************/ - -static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); -} - -/**************************************************************************** - * Name: stm32_tim_checkint - ****************************************************************************/ - -static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, - int source) -{ - uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); - return (regval & GTIM_SR_UIF) ? 1 : 0; -} - -/**************************************************************************** - * Pubic Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_tim_init - ****************************************************************************/ - -struct stm32_tim_dev_s *stm32_tim_init(int timer) -{ - struct stm32_tim_dev_s *dev = NULL; - - /* Get structure and enable power */ - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case 6: - dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case 7: - dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); - break; -#endif - - default: - return NULL; - } - - /* Is device already allocated */ - - if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) - { - return NULL; - } - - stm32_tim_reset(dev); - - return dev; -} - -/**************************************************************************** - * Name: stm32_tim_deinit - * - * TODO: Detach interrupts, and close down all TIM Channels - * - ****************************************************************************/ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev) -{ - DEBUGASSERT(dev != NULL); - - /* Disable power */ - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); - break; -#endif - - default: - return -EINVAL; - } - - /* Mark it as free */ - - ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; - - return OK; -} - -#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h deleted file mode 100644 index 7bdffaa7800fa..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ /dev/null @@ -1,214 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32wl5_tim.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* TIM Device Structure */ - -struct stm32_tim_dev_s -{ - struct stm32_tim_ops_s *ops; -}; - -/* TIM Modes of Operation */ - -enum stm32_tim_mode_e -{ - STM32_TIM_MODE_UNUSED = -1, - - /* One of the following */ - - STM32_TIM_MODE_MASK = 0x0310, - STM32_TIM_MODE_DISABLED = 0x0000, - STM32_TIM_MODE_UP = 0x0100, - STM32_TIM_MODE_DOWN = 0x0110, - STM32_TIM_MODE_UPDOWN = 0x0200, - STM32_TIM_MODE_PULSE = 0x0300, - - /* One of the following */ - - STM32_TIM_MODE_CK_INT = 0x0000, -#if 0 - STM32_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32_TIM_MODE_CK_EXT = 0x0800, - STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, -#endif - - /* Clock sources, OR'ed with CK_EXT */ - -#if 0 - STM32_TIM_MODE_CK_CHINVALID = 0x0000, - STM32_TIM_MODE_CK_CH1 = 0x0001, - STM32_TIM_MODE_CK_CH2 = 0x0002, - STM32_TIM_MODE_CK_CH3 = 0x0003, - STM32_TIM_MODE_CK_CH4 = 0x0004 -#endif - - /* Todo: external trigger block */ -}; - -/* TIM Channel Modes */ - -enum stm32_tim_channel_e -{ - STM32_TIM_CH_DISABLED = 0x00, - - /* Common configuration */ - - STM32_TIM_CH_POLARITY_POS = 0x00, - STM32_TIM_CH_POLARITY_NEG = 0x01, - - /* MODES: */ - - STM32_TIM_CH_MODE_MASK = 0x06, - - /* Output Compare Modes */ - - STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ -#if 0 - STM32_TIM_CH_OUTCOMPARE = 0x06, -#endif -}; - -/* TIM Operations */ - -struct stm32_tim_ops_s -{ - /* Basic Timers */ - - void (*enable)(struct stm32_tim_dev_s *dev); - void (*disable)(struct stm32_tim_dev_s *dev); - int (*setmode)(struct stm32_tim_dev_s *dev, - enum stm32_tim_mode_e mode); - int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32_tim_dev_s *dev); - void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); - - /* General and Advanced Timers Adds */ - - int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32_tim_channel_e mode); - int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, - uint32_t compare); - int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); - - /* Timer interrupts */ - - int (*setisr)(struct stm32_tim_dev_s *dev, - xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32_tim_dev_s *dev, int source); - void (*disableint)(struct stm32_tim_dev_s *dev, int source); - void (*ackint)(struct stm32_tim_dev_s *dev, int source); - int (*checkint)(struct stm32_tim_dev_s *dev, int source); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - -struct stm32_tim_dev_s *stm32_tim_init(int timer); - -/* Power-down timer, mark it as unused */ - -int stm32_tim_deinit(struct stm32_tim_dev_s *dev); - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the form - * /dev/timer0 - * timer - the timer number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_TIMER -int stm32_timer_initialize(const char *devpath, int timer); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32WL5_STM32_TIM_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c deleted file mode 100644 index 233008d82f047..0000000000000 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ /dev/null @@ -1,607 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include "stm32wl5_tim.h" - -#if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ - defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ - defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ - defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ - defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ - defined(CONFIG_STM32_TIM17)) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define STM32_TIM1_RES 16 -#define STM32_TIM2_RES 32 -#define STM32_TIM3_RES 16 -#define STM32_TIM4_RES 16 -#define STM32_TIM5_RES 32 -#define STM32_TIM6_RES 16 -#define STM32_TIM7_RES 16 -#define STM32_TIM8_RES 16 -#define STM32_TIM15_RES 16 -#define STM32_TIM16_RES 16 -#define STM32_TIM17_RES 16 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * timer_lowerhalf_s structure. - */ - -struct stm32_lowerhalf_s -{ - const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32_tim_dev_s *tim; /* stm32 timer driver */ - tccb_t callback; /* Current upper half interrupt callback */ - void *arg; /* Argument passed to upper half callback */ - bool started; /* True: Timer has been started */ - const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower); -static int stm32_stop(struct timer_lowerhalf_s *lower); -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status); -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout); -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct timer_ops_s g_timer_ops = -{ - .start = stm32_start, - .stop = stm32_stop, - .getstatus = stm32_getstatus, - .settimeout = stm32_settimeout, - .setcallback = stm32_setcallback, - .ioctl = NULL, -}; - -#ifdef CONFIG_STM32_TIM1 -static struct stm32_lowerhalf_s g_tim1_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM1_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM2 -static struct stm32_lowerhalf_s g_tim2_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM2_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM3 -static struct stm32_lowerhalf_s g_tim3_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM3_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM4 -static struct stm32_lowerhalf_s g_tim4_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM4_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM5 -static struct stm32_lowerhalf_s g_tim5_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM5_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM6 -static struct stm32_lowerhalf_s g_tim6_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM6_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM7 -static struct stm32_lowerhalf_s g_tim7_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM7_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM8 -static struct stm32_lowerhalf_s g_tim8_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM8_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM15 -static struct stm32_lowerhalf_s g_tim15_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM15_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM16 -static struct stm32_lowerhalf_s g_tim16_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM16_RES, -}; -#endif - -#ifdef CONFIG_STM32_TIM17 -static struct stm32_lowerhalf_s g_tim17_lowerhalf = -{ - .ops = &g_timer_ops, - .resolution = STM32_TIM17_RES, -}; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_handler - * - * Description: - * timer interrupt handler - * - * Input Parameters: - * - * Returned Value: - * - ****************************************************************************/ - -static int stm32_timer_handler(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *lower = - (struct stm32_lowerhalf_s *)arg; - uint32_t next_interval_us = 0; - - STM32_TIM_ACKINT(lower->tim, 0); - - if (lower->callback(&next_interval_us, lower->arg)) - { - if (next_interval_us > 0) - { - STM32_TIM_SETPERIOD(lower->tim, next_interval_us); - } - } - else - { - stm32_stop((struct timer_lowerhalf_s *)lower); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the timer, resetting the time to the current timeout, - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_start(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (!priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); - - if (priv->callback != NULL) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - - priv->started = true; - return OK; - } - - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; -} - -/**************************************************************************** - * Name: stm32_stop - * - * Description: - * Stop the timer - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_stop(struct timer_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - - if (priv->started) - { - STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - priv->started = false; - return OK; - } - - /* Return ENODEV to indicate that the timer was not running */ - - return -ENODEV; -} - -/**************************************************************************** - * Name: stm32_getstatus - * - * Description: - * get timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the "lower- - * half" driver state structure. - * status - The location to return the status information. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_getstatus(struct timer_lowerhalf_s *lower, - struct timer_status_s *status) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - uint32_t timeout; - uint32_t clock; - uint32_t period; - uint32_t clock_factor; - - DEBUGASSERT(priv); - - /* Return the status bit */ - - status->flags = 0; - if (priv->started) - { - status->flags |= TCFLAGS_ACTIVE; - } - - if (priv->callback) - { - status->flags |= TCFLAGS_HANDLER; - } - - /* Get timeout */ - - maxtimeout = (1 << priv->resolution) - 1; - clock = STM32_TIM_GETCLOCK(priv->tim); - period = STM32_TIM_GETPERIOD(priv->tim); - - if (clock == 1000000) - { - timeout = period; - } - else - { - timeout = (maxtimeout * 1000000) / clock; - } - - status->timeout = timeout; - - /* Get the time remaining until the timer expires (in microseconds) */ - - clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * - clock_factor; - return OK; -} - -/**************************************************************************** - * Name: stm32_settimeout - * - * Description: - * Set a new timeout value (and reset the timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in microseconds. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int stm32_settimeout(struct timer_lowerhalf_s *lower, - uint32_t timeout) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint64_t maxtimeout; - - if (priv->started) - { - return -EPERM; - } - - maxtimeout = (1 << priv->resolution) - 1; - if (timeout > maxtimeout) - { - uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32_TIM_SETCLOCK(priv->tim, freq); - STM32_TIM_SETPERIOD(priv->tim, maxtimeout); - } - else - { - STM32_TIM_SETCLOCK(priv->tim, 1000000); - STM32_TIM_SETPERIOD(priv->tim, timeout); - } - - return OK; -} - -/**************************************************************************** - * Name: stm32_sethandler - * - * Description: - * Call this user provided timeout handler. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * callback - The new timer expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored, - * arg - Argument that will be provided in the callback - * - * Returned Value: - * The previous timer expiration function pointer or NULL is there was - * no previous function pointer. - * - ****************************************************************************/ - -static void stm32_setcallback(struct timer_lowerhalf_s *lower, - tccb_t callback, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags = enter_critical_section(); - - /* Save the new callback */ - - priv->callback = callback; - priv->arg = arg; - - if (callback != NULL && priv->started) - { - STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32_TIM_ENABLEINT(priv->tim, 0); - } - else - { - STM32_TIM_DISABLEINT(priv->tim, 0); - STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_timer_initialize - * - * Description: - * Bind the configuration timer to a timer lower half instance and - * register the timer drivers at 'devpath' - * - * Input Parameters: - * devpath - The full path to the timer device. This should be of the - * form /dev/timer0 - * timer - the timer's number. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int stm32_timer_initialize(const char *devpath, int timer) -{ - struct stm32_lowerhalf_s *lower; - - switch (timer) - { -#ifdef CONFIG_STM32_TIM1 - case 1: - lower = &g_tim1_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM2 - case 2: - lower = &g_tim2_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM3 - case 3: - lower = &g_tim3_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM4 - case 4: - lower = &g_tim4_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM5 - case 5: - lower = &g_tim5_lowerhalf; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case 6: - lower = &g_tim6_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM7 - case 7: - lower = &g_tim7_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM8 - case 8: - lower = &g_tim8_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM15 - case 15: - lower = &g_tim15_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM16 - case 16: - lower = &g_tim16_lowerhalf; - break; -#endif - -#ifdef CONFIG_STM32_TIM17 - case 17: - lower = &g_tim17_lowerhalf; - break; -#endif - - default: - return -ENODEV; - } - - /* Initialize the elements of lower half state structure */ - - lower->started = false; - lower->callback = NULL; - lower->tim = stm32_tim_init(timer); - - if (lower->tim == NULL) - { - return -EINVAL; - } - - /* Register the timer driver as /dev/timerX. The returned value from - * timer_register is a handle that could be used with timer_unregister(). - * REVISIT: The returned handle is discard here. - */ - - void *drvr = timer_register(devpath, - (struct timer_lowerhalf_s *)lower); - if (drvr == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the timer driver (such as if the - * 'depath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - return OK; -} - -#endif /* CONFIG_TIMER */ diff --git a/boards/arm/at32/at32f437-mini/include/board.h b/boards/arm/at32/at32f437-mini/include/board.h index 1042725632afe..9fdb844fc8941 100644 --- a/boards/arm/at32/at32f437-mini/include/board.h +++ b/boards/arm/at32/at32f437-mini/include/board.h @@ -130,14 +130,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (AT32_HCLK_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (AT32_HCLK_FREQUENCY) +#define STM32_TIM1_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM2_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM3_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM4_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM5_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM6_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM7_CLKIN (AT32_HCLK_FREQUENCY) +#define STM32_TIM8_CLKIN (AT32_HCLK_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32c0/nucleo-c071rb/include/board.h b/boards/arm/stm32c0/nucleo-c071rb/include/board.h index 500badf7dcb78..48cc0f74eba03 100644 --- a/boards/arm/stm32c0/nucleo-c071rb/include/board.h +++ b/boards/arm/stm32c0/nucleo-c071rb/include/board.h @@ -74,13 +74,13 @@ /* All timers on PCLK x1 (48 MHz) */ -#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM14_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM15_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM16_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM17_CLKIN STM32_PCLK1_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32c0/nucleo-c092rc/include/board.h b/boards/arm/stm32c0/nucleo-c092rc/include/board.h index 0422106dda396..3ba92033529a9 100644 --- a/boards/arm/stm32c0/nucleo-c092rc/include/board.h +++ b/boards/arm/stm32c0/nucleo-c092rc/include/board.h @@ -79,13 +79,13 @@ /* All timers on PCLK x1 (48 MHz) */ -#define STM32_APB2_TIM1_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM14_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM14_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM15_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM16_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM17_CLKIN STM32_PCLK1_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0/nucleo-f072rb/include/board.h index ecbb09cd8db12..2a028f5bf9305 100644 --- a/boards/arm/stm32f0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0/nucleo-f072rb/include/board.h @@ -139,17 +139,17 @@ /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0/nucleo-f091rc/include/board.h index 745d8a6644332..b5d8ffb2fa1d5 100644 --- a/boards/arm/stm32f0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0/nucleo-f091rc/include/board.h @@ -139,17 +139,17 @@ /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0/stm32f051-discovery/include/board.h index 64aa156add7cd..12b0e213bc70a 100644 --- a/boards/arm/stm32f0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f051-discovery/include/board.h @@ -139,17 +139,17 @@ /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0/stm32f072-discovery/include/board.h index 52a339aee2a6f..b7370d1ad9bec 100644 --- a/boards/arm/stm32f0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f072-discovery/include/board.h @@ -139,17 +139,17 @@ /* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */ -#define STM32_APB1_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f1/cloudctrl/include/board.h b/boards/arm/stm32f1/cloudctrl/include/board.h index df0ae697667cd..376150cdff226 100644 --- a/boards/arm/stm32f1/cloudctrl/include/board.h +++ b/boards/arm/stm32f1/cloudctrl/include/board.h @@ -75,8 +75,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -85,12 +85,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* MCO output driven by PLL3. From above, we already have PLL3 input * frequency as: diff --git a/boards/arm/stm32f1/et-stm32-stamp/include/board.h b/boards/arm/stm32f1/et-stm32-stamp/include/board.h index 7cb521fadc8b8..fea335874aac1 100644 --- a/boards/arm/stm32f1/et-stm32-stamp/include/board.h +++ b/boards/arm/stm32f1/et-stm32-stamp/include/board.h @@ -69,8 +69,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -79,26 +79,26 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/fire-stm32v2/include/board.h b/boards/arm/stm32f1/fire-stm32v2/include/board.h index 27e228b92572c..1bc4ca7261406 100644 --- a/boards/arm/stm32f1/fire-stm32v2/include/board.h +++ b/boards/arm/stm32f1/fire-stm32v2/include/board.h @@ -80,8 +80,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -90,12 +90,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -106,14 +106,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/hymini-stm32v/include/board.h b/boards/arm/stm32f1/hymini-stm32v/include/board.h index 820d03a162b66..f9e44d9f31291 100644 --- a/boards/arm/stm32f1/hymini-stm32v/include/board.h +++ b/boards/arm/stm32f1/hymini-stm32v/include/board.h @@ -66,8 +66,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -76,12 +76,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -92,14 +92,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c index a43d7b85e278f..da5649eee2dae 100644 --- a/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c @@ -41,6 +41,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "hymini-stm32v.h" #include /* Should always be included last due to dependencies */ diff --git a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c index 679d23535de72..169cd28555019 100644 --- a/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c @@ -42,6 +42,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "hymini-stm32v.h" #include /* Should always be included last due to dependencies */ diff --git a/boards/arm/stm32f1/maple/include/board.h b/boards/arm/stm32f1/maple/include/board.h index af797c5453d2b..1ae06c237f851 100644 --- a/boards/arm/stm32f1/maple/include/board.h +++ b/boards/arm/stm32f1/maple/include/board.h @@ -69,8 +69,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -79,12 +79,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -95,14 +95,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/maple/src/stm32_lcd.c b/boards/arm/stm32f1/maple/src/stm32_lcd.c index 58f5831a33fe8..c744dbd936f79 100644 --- a/boards/arm/stm32f1/maple/src/stm32_lcd.c +++ b/boards/arm/stm32f1/maple/src/stm32_lcd.c @@ -43,6 +43,7 @@ #include "chip.h" #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "maple.h" /**************************************************************************** diff --git a/boards/arm/stm32f1/nucleo-f103rb/include/board.h b/boards/arm/stm32f1/nucleo-f103rb/include/board.h index 508c91177a32b..4e410d1df3de3 100644 --- a/boards/arm/stm32f1/nucleo-f103rb/include/board.h +++ b/boards/arm/stm32f1/nucleo-f103rb/include/board.h @@ -86,13 +86,13 @@ /* APB2 TIM 1 will receive PCLK2 (72MHz) */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f1/olimex-stm32-p107/include/board.h b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h index 612ecb223fdcf..f940eca98dbde 100644 --- a/boards/arm/stm32f1/olimex-stm32-p107/include/board.h +++ b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h @@ -73,8 +73,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -83,12 +83,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* MCO output driven by PLL3. From above, we already have PLL3 input * frequency as: diff --git a/boards/arm/stm32f1/olimexino-stm32/include/board.h b/boards/arm/stm32f1/olimexino-stm32/include/board.h index 43d1b956c90f3..abadc741c0102 100644 --- a/boards/arm/stm32f1/olimexino-stm32/include/board.h +++ b/boards/arm/stm32f1/olimexino-stm32/include/board.h @@ -80,8 +80,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -90,12 +90,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -106,14 +106,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* Buttons ******************************************************************/ diff --git a/boards/arm/stm32f1/shenzhou/include/board.h b/boards/arm/stm32f1/shenzhou/include/board.h index 858074f77dfe5..58fb89b959d4b 100644 --- a/boards/arm/stm32f1/shenzhou/include/board.h +++ b/boards/arm/stm32f1/shenzhou/include/board.h @@ -75,8 +75,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -85,12 +85,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* MCO output driven by PLL3. * From above, we already have PLL3 input frequency as: diff --git a/boards/arm/stm32f1/stm3210e-eval/include/board.h b/boards/arm/stm32f1/stm3210e-eval/include/board.h index ad0c8628d22e4..cb056a9c0623c 100644 --- a/boards/arm/stm32f1/stm3210e-eval/include/board.h +++ b/boards/arm/stm32f1/stm3210e-eval/include/board.h @@ -76,8 +76,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -86,12 +86,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -102,14 +102,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c index f0b29a830d7b0..e384b346e7df0 100644 --- a/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c @@ -64,6 +64,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "stm3210e-eval.h" /**************************************************************************** diff --git a/boards/arm/stm32f1/stm32_tiny/include/board.h b/boards/arm/stm32f1/stm32_tiny/include/board.h index 2a9a1ac8c9218..925388a176a89 100644 --- a/boards/arm/stm32f1/stm32_tiny/include/board.h +++ b/boards/arm/stm32f1/stm32_tiny/include/board.h @@ -69,8 +69,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -79,12 +79,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -95,14 +95,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/stm32butterfly2/include/board.h b/boards/arm/stm32f1/stm32butterfly2/include/board.h index cef38c97de014..2659deaa76759 100644 --- a/boards/arm/stm32f1/stm32butterfly2/include/board.h +++ b/boards/arm/stm32f1/stm32butterfly2/include/board.h @@ -82,12 +82,12 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f1/stm32f103-minimum/include/board.h b/boards/arm/stm32f1/stm32f103-minimum/include/board.h index 52c125f7cc8c1..138d226726159 100644 --- a/boards/arm/stm32f1/stm32f103-minimum/include/board.h +++ b/boards/arm/stm32f1/stm32f103-minimum/include/board.h @@ -69,8 +69,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -79,12 +79,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -95,14 +95,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_PCLK1_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f1/stm32vldiscovery/include/board.h b/boards/arm/stm32f1/stm32vldiscovery/include/board.h index cde0a062e8e30..35696ce65cb8f 100644 --- a/boards/arm/stm32f1/stm32vldiscovery/include/board.h +++ b/boards/arm/stm32f1/stm32vldiscovery/include/board.h @@ -70,10 +70,10 @@ /* APB2 timers (1, 15-17) will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* APB1 clock (PCLK1) is HCLK (24MHz) */ @@ -82,29 +82,29 @@ /* APB1 timers (2-7, 12-14) will receive PCLK1. */ -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM12_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM13_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM14_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM12_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM13_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM14_CLKIN STM32_PCLK1_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,15-17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h index 75e96c764593d..a5460556cbc33 100644 --- a/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -72,8 +72,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -82,12 +82,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 * @@ -101,14 +101,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h index ac40282bdcc68..166998bf11496 100644 --- a/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -73,8 +73,8 @@ /* APB2 timers 1 and 8 will receive PCLK2. */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -83,12 +83,12 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c index d7a113d035b63..e39fbf248231a 100644 --- a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c @@ -70,8 +70,8 @@ #endif #ifndef CONFIG_VIEWTOOL_TIM6_FREQUENCY -# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_APB1_TIM6_CLKIN -# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +# warning CONFIG_VIEWTOOL_TIM6_FREQUENCY defaulting to STM32_TIM6_CLKIN +# define CONFIG_VIEWTOOL_TIM6_FREQUENCY STM32_TIM6_CLKIN #endif #ifndef CONFIG_VIEWTOOL_TIM6_PERIOD @@ -184,7 +184,7 @@ int highpri_main(int argc, char *argv[]) prescaler = STM32_TIM_SETCLOCK(dev, CONFIG_VIEWTOOL_TIM6_FREQUENCY); printf("TIM6 CLKIN=%jd Hz, Frequency=%d Hz, prescaler=%d\n", - (uintmax_t)STM32_APB1_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, + (uintmax_t)STM32_TIM6_CLKIN, CONFIG_VIEWTOOL_TIM6_FREQUENCY, prescaler); STM32_TIM_SETPERIOD(dev, CONFIG_VIEWTOOL_TIM6_PERIOD); diff --git a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c index 4d80b05f9d86f..7231e2c83f6df 100644 --- a/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c @@ -43,6 +43,7 @@ #include "arm_internal.h" #include "stm32.h" +#include "stm32_tim.h" #include "viewtool_stm32f107.h" #ifdef CONFIG_LCD_SSD1289 diff --git a/boards/arm/stm32f2/nucleo-f207zg/include/board.h b/boards/arm/stm32f2/nucleo-f207zg/include/board.h index 62f9ed1e30ef6..53b6fda0142bb 100644 --- a/boards/arm/stm32f2/nucleo-f207zg/include/board.h +++ b/boards/arm/stm32f2/nucleo-f207zg/include/board.h @@ -104,23 +104,23 @@ /* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timers driven from APB1 will be twice PCLK1 (50MHz) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f2/olimex-stm32-p207/include/board.h b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h index 7ad51256922fb..3e89a03c3ffb8 100644 --- a/boards/arm/stm32f2/olimex-stm32-p207/include/board.h +++ b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h @@ -85,15 +85,15 @@ /* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ @@ -102,25 +102,25 @@ /* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f2/photon/include/board.h b/boards/arm/stm32f2/photon/include/board.h index a26b8826bffae..d8fec01ed03ce 100644 --- a/boards/arm/stm32f2/photon/include/board.h +++ b/boards/arm/stm32f2/photon/include/board.h @@ -109,15 +109,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ @@ -126,25 +126,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* USB OTG HS definitions ***************************************************/ diff --git a/boards/arm/stm32f2/stm3220g-eval/include/board.h b/boards/arm/stm32f2/stm3220g-eval/include/board.h index fb3043eada22d..df8f18fc31519 100644 --- a/boards/arm/stm32f2/stm3220g-eval/include/board.h +++ b/boards/arm/stm32f2/stm3220g-eval/include/board.h @@ -119,15 +119,15 @@ /* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ @@ -136,25 +136,25 @@ /* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f3/nucleo-f302r8/include/board.h b/boards/arm/stm32f3/nucleo-f302r8/include/board.h index 14529925ce35c..c745732f4ade9 100644 --- a/boards/arm/stm32f3/nucleo-f302r8/include/board.h +++ b/boards/arm/stm32f3/nucleo-f302r8/include/board.h @@ -83,11 +83,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -96,11 +96,11 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -111,14 +111,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f3/nucleo-f303re/include/board.h b/boards/arm/stm32f3/nucleo-f303re/include/board.h index a27906b0a72a9..32d4bbd067773 100644 --- a/boards/arm/stm32f3/nucleo-f303re/include/board.h +++ b/boards/arm/stm32f3/nucleo-f303re/include/board.h @@ -85,11 +85,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -98,11 +98,11 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -113,14 +113,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f3/nucleo-f303ze/include/board.h b/boards/arm/stm32f3/nucleo-f303ze/include/board.h index 2f7b5950dd010..f37156152f9d3 100644 --- a/boards/arm/stm32f3/nucleo-f303ze/include/board.h +++ b/boards/arm/stm32f3/nucleo-f303ze/include/board.h @@ -84,11 +84,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -97,11 +97,11 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -112,14 +112,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f3/nucleo-f334r8/include/board.h b/boards/arm/stm32f3/nucleo-f334r8/include/board.h index 52d5fbd8889cf..2b71c070f3913 100644 --- a/boards/arm/stm32f3/nucleo-f334r8/include/board.h +++ b/boards/arm/stm32f3/nucleo-f334r8/include/board.h @@ -83,11 +83,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -97,25 +97,25 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) #define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c index 3fd7576b0120c..2b7c929f28469 100644 --- a/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c @@ -749,7 +749,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) */ freq = spwm->samples * spwm->waveform_freq; - per = BOARD_TIM6_FREQUENCY / freq; + per = STM32_TIM6_CLKIN / freq; if (per > 0xffff) { printf("ERROR: can not achieve TIM6 frequency\n"); @@ -759,7 +759,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) /* TODO: TIM_SETFREQ */ - STM32_TIM_SETCLOCK(tim, BOARD_TIM6_FREQUENCY); + STM32_TIM_SETCLOCK(tim, STM32_TIM6_CLKIN); STM32_TIM_SETPERIOD(tim, per); /* Attach TIM6 ram vector */ diff --git a/boards/arm/stm32f3/stm32f334-disco/include/board.h b/boards/arm/stm32f3/stm32f334-disco/include/board.h index b4c5ffeca08aa..8e451090f50f9 100644 --- a/boards/arm/stm32f3/stm32f334-disco/include/board.h +++ b/boards/arm/stm32f3/stm32f334-disco/include/board.h @@ -83,11 +83,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) #define STM32_APB1_THRTIM1_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -97,25 +97,25 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) #define BOARD_HRTIM1_FREQUENCY STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f3/stm32f3discovery/include/board.h b/boards/arm/stm32f3/stm32f3discovery/include/board.h index 0e989224f4505..9219918e28e5d 100644 --- a/boards/arm/stm32f3/stm32f3discovery/include/board.h +++ b/boards/arm/stm32f3/stm32f3discovery/include/board.h @@ -83,11 +83,11 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */ @@ -96,11 +96,11 @@ /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -111,14 +111,14 @@ * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f4/clicker2-stm32/include/board.h b/boards/arm/stm32f4/clicker2-stm32/include/board.h index 5234be7f4f8b6..41a2025d5fe9f 100644 --- a/boards/arm/stm32f4/clicker2-stm32/include/board.h +++ b/boards/arm/stm32f4/clicker2-stm32/include/board.h @@ -111,15 +111,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -128,25 +128,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/mikroe-stm32f4/include/board.h b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h index 8c6d5b2833ef7..be169bd0d1f6b 100644 --- a/boards/arm/stm32f4/mikroe-stm32f4/include/board.h +++ b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h @@ -108,15 +108,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -125,25 +125,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f4/nucleo-f401re/include/board.h b/boards/arm/stm32f4/nucleo-f401re/include/board.h index f8cff6a2383a6..9101d162b269c 100644 --- a/boards/arm/stm32f4/nucleo-f401re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f401re/include/board.h @@ -131,15 +131,15 @@ /* REVISIT */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (84MHz) */ @@ -150,11 +150,11 @@ /* REVISIT */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -163,14 +163,14 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/nucleo-f410rb/include/board.h b/boards/arm/stm32f4/nucleo-f410rb/include/board.h index 4a264975b6f73..388092e708859 100644 --- a/boards/arm/stm32f4/nucleo-f410rb/include/board.h +++ b/boards/arm/stm32f4/nucleo-f410rb/include/board.h @@ -118,8 +118,8 @@ /* REVISIT */ -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (100MHz) */ @@ -130,9 +130,9 @@ /* REVISIT */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -141,12 +141,6 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN -#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN - /* DMA Channel/Stream Selections ********************************************/ /* Stream selections are arbitrary for now but might become important in the diff --git a/boards/arm/stm32f4/nucleo-f411re/include/board.h b/boards/arm/stm32f4/nucleo-f411re/include/board.h index 6613554b8c486..5b882a288158a 100644 --- a/boards/arm/stm32f4/nucleo-f411re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f411re/include/board.h @@ -128,15 +128,15 @@ /* REVISIT */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (104MHz) */ @@ -147,11 +147,11 @@ /* REVISIT */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -160,14 +160,14 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/nucleo-f412zg/include/board.h b/boards/arm/stm32f4/nucleo-f412zg/include/board.h index 35a7fa13dd5b1..b17489b2f4bd1 100644 --- a/boards/arm/stm32f4/nucleo-f412zg/include/board.h +++ b/boards/arm/stm32f4/nucleo-f412zg/include/board.h @@ -81,13 +81,13 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (96MHz) */ @@ -96,24 +96,24 @@ /* Timers driven from APB2 will be PCLK2 since no prescale division */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) /* Alternate function pin selections ****************************************/ diff --git a/boards/arm/stm32f4/nucleo-f429zi/include/board.h b/boards/arm/stm32f4/nucleo-f429zi/include/board.h index 4e259c13a929c..f4bbba26e1631 100644 --- a/boards/arm/stm32f4/nucleo-f429zi/include/board.h +++ b/boards/arm/stm32f4/nucleo-f429zi/include/board.h @@ -108,15 +108,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -125,25 +125,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ diff --git a/boards/arm/stm32f4/nucleo-f446re/include/board.h b/boards/arm/stm32f4/nucleo-f446re/include/board.h index dc46e111057ad..2d54e7aca73d3 100644 --- a/boards/arm/stm32f4/nucleo-f446re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f446re/include/board.h @@ -126,15 +126,15 @@ /* Timers driven from APB1 will be twice PCLK1 (REVISIT) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (104MHz) */ @@ -143,25 +143,25 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/odrive36/include/board.h b/boards/arm/stm32f4/odrive36/include/board.h index 88d42164eaf24..d3f67e16c1803 100644 --- a/boards/arm/stm32f4/odrive36/include/board.h +++ b/boards/arm/stm32f4/odrive36/include/board.h @@ -86,15 +86,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -103,25 +103,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ diff --git a/boards/arm/stm32f4/olimex-stm32-e407/include/board.h b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h index a12b129b4ddcc..f4e357b47fc83 100644 --- a/boards/arm/stm32f4/olimex-stm32-e407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h @@ -118,15 +118,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 */ @@ -135,25 +135,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same as APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f4/olimex-stm32-h405/include/board.h b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h index 139fac64fa5c8..5807df9720215 100644 --- a/boards/arm/stm32f4/olimex-stm32-h405/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h @@ -85,15 +85,15 @@ /* Timers driven from APB1 will be twice PCLK1 (60Mhz) */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (60MHz) */ @@ -102,25 +102,25 @@ /* Timers driven from APB2 will be twice PCLK2 (120Mhz) */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f4/olimex-stm32-h407/include/board.h b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h index 231db8e186534..f27835663b53d 100644 --- a/boards/arm/stm32f4/olimex-stm32-h407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h @@ -118,15 +118,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 */ @@ -135,25 +135,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/olimex-stm32-p407/include/board.h b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h index e1d157fa0dd95..662d457fcca76 100644 --- a/boards/arm/stm32f4/olimex-stm32-p407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h @@ -84,15 +84,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -101,25 +101,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/omnibusf4/include/board.h b/boards/arm/stm32f4/omnibusf4/include/board.h index 3fd9a21b8f2a6..1f2631beacb69 100644 --- a/boards/arm/stm32f4/omnibusf4/include/board.h +++ b/boards/arm/stm32f4/omnibusf4/include/board.h @@ -110,15 +110,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -127,25 +127,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* Pin configurations *******************************************************/ diff --git a/boards/arm/stm32f4/stm3240g-eval/include/board.h b/boards/arm/stm32f4/stm3240g-eval/include/board.h index 702e2d93d9084..ca39489607954 100644 --- a/boards/arm/stm32f4/stm3240g-eval/include/board.h +++ b/boards/arm/stm32f4/stm3240g-eval/include/board.h @@ -124,15 +124,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -141,32 +141,32 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same as APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8-11 are on APB2, others on APB1 */ -#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN -#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN -#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN -#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN - -#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN -#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN -#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN -#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN -#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN +#define STM32_TIM2_CLKIN    STM32_TIM2_CLKIN +#define STM32_TIM3_CLKIN    STM32_TIM3_CLKIN +#define STM32_TIM4_CLKIN    STM32_TIM4_CLKIN +#define STM32_TIM5_CLKIN    STM32_TIM5_CLKIN +#define STM32_TIM6_CLKIN    STM32_TIM6_CLKIN +#define STM32_TIM7_CLKIN    STM32_TIM7_CLKIN +#define STM32_TIM12_CLKIN   STM32_TIM12_CLKIN +#define STM32_TIM13_CLKIN   STM32_TIM13_CLKIN +#define STM32_TIM14_CLKIN   STM32_TIM14_CLKIN + +#define STM32_TIM1_CLKIN    STM32_TIM1_CLKIN +#define STM32_TIM8_CLKIN    STM32_TIM8_CLKIN +#define STM32_TIM9_CLKIN    STM32_TIM9_CLKIN +#define STM32_TIM10_CLKIN   STM32_TIM10_CLKIN +#define STM32_TIM11_CLKIN   STM32_TIM11_CLKIN /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h index 4225ee4db7475..5299b34afda45 100644 --- a/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h +++ b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h @@ -130,15 +130,15 @@ /* REVISIT */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (84MHz) */ @@ -149,11 +149,11 @@ /* REVISIT */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -162,14 +162,14 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY (2*STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2*STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/stm32f411-minimum/include/board.h b/boards/arm/stm32f4/stm32f411-minimum/include/board.h index c90a3ade986b2..59ba97101bb1b 100644 --- a/boards/arm/stm32f4/stm32f411-minimum/include/board.h +++ b/boards/arm/stm32f4/stm32f411-minimum/include/board.h @@ -119,15 +119,15 @@ /* REVISIT */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ @@ -136,11 +136,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -149,14 +149,14 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/stm32f411e-disco/include/board.h b/boards/arm/stm32f4/stm32f411e-disco/include/board.h index ce8aadff51251..30b98882525dc 100644 --- a/boards/arm/stm32f4/stm32f411e-disco/include/board.h +++ b/boards/arm/stm32f4/stm32f411e-disco/include/board.h @@ -123,15 +123,15 @@ /* REVISIT */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (48MHz) */ @@ -140,11 +140,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -153,14 +153,14 @@ /* REVISIT */ -#define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY) /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f4/stm32f429i-disco/include/board.h b/boards/arm/stm32f4/stm32f429i-disco/include/board.h index 8d06febb0a6ad..bf87f53bc2136 100644 --- a/boards/arm/stm32f4/stm32f429i-disco/include/board.h +++ b/boards/arm/stm32f4/stm32f429i-disco/include/board.h @@ -112,15 +112,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -129,25 +129,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY/2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY/2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32f4/stm32f4discovery/include/board.h b/boards/arm/stm32f4/stm32f4discovery/include/board.h index d8bebb7ef980d..da1f01a90bba5 100644 --- a/boards/arm/stm32f4/stm32f4discovery/include/board.h +++ b/boards/arm/stm32f4/stm32f4discovery/include/board.h @@ -113,15 +113,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */ @@ -130,25 +130,25 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY /* SDIO dividers. Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses diff --git a/boards/arm/stm32f7/nucleo-f722ze/include/board.h b/boards/arm/stm32f7/nucleo-f722ze/include/board.h index ad312ccc4d4aa..32d2b7f8b047d 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/include/board.h +++ b/boards/arm/stm32f7/nucleo-f722ze/include/board.h @@ -170,15 +170,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -187,11 +187,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDMMC dividers. Note that slower clocking is required when DMA * is disabledin order to avoid RX overrun/TX underrun errors due diff --git a/boards/arm/stm32f7/nucleo-f746zg/include/board.h b/boards/arm/stm32f7/nucleo-f746zg/include/board.h index 95d61afca086b..91dce6a762015 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/include/board.h +++ b/boards/arm/stm32f7/nucleo-f746zg/include/board.h @@ -170,15 +170,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -187,11 +187,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDMMC dividers. Note that slower clocking is required when DMA * is disabledin order to avoid RX overrun/TX underrun errors due diff --git a/boards/arm/stm32f7/nucleo-f767zi/include/board.h b/boards/arm/stm32f7/nucleo-f767zi/include/board.h index 357e8d0129241..f3fb8fcb21044 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/include/board.h +++ b/boards/arm/stm32f7/nucleo-f767zi/include/board.h @@ -170,15 +170,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -187,11 +187,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* SDMMC dividers. Note that slower clocking is required when DMA * is disabledin order to avoid RX overrun/TX underrun errors due diff --git a/boards/arm/stm32f7/steval-eth001v1/include/board.h b/boards/arm/stm32f7/steval-eth001v1/include/board.h index 8b6cb2f790f61..3772149a57c56 100644 --- a/boards/arm/stm32f7/steval-eth001v1/include/board.h +++ b/boards/arm/stm32f7/steval-eth001v1/include/board.h @@ -141,15 +141,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -158,11 +158,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* FLASH wait states * diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index 9bc6dc43c7c33..2a6e52ab733ec 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -171,15 +171,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -188,11 +188,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* FLASH wait states * diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index f082dfa5aa885..34554004767f5 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -212,15 +212,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -229,11 +229,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* FLASH wait states * diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 21f6d2ffc77ed..9d128fb62c378 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -210,15 +210,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -227,11 +227,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* FLASH wait states * diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index fd495d6838f09..e0c16934e09a7 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -222,15 +222,15 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */ @@ -239,11 +239,11 @@ /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) /* FLASH wait states * diff --git a/boards/arm/stm32g0/nucleo-g070rb/include/board.h b/boards/arm/stm32g0/nucleo-g070rb/include/board.h index 2a65558b105d0..40ddd0bdb1fd3 100644 --- a/boards/arm/stm32g0/nucleo-g070rb/include/board.h +++ b/boards/arm/stm32g0/nucleo-g070rb/include/board.h @@ -116,17 +116,17 @@ /* Timers driven from APB1. Frequency = PCLK1 */ -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 is equal to PCLK1 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32g4/b-g431b-esc1/include/board.h b/boards/arm/stm32g4/b-g431b-esc1/include/board.h index 006e80f98f3c8..379a8488e786e 100644 --- a/boards/arm/stm32g4/b-g431b-esc1/include/board.h +++ b/boards/arm/stm32g4/b-g431b-esc1/include/board.h @@ -214,19 +214,19 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -236,18 +236,18 @@ * otherwise frequency is 2xAPBx. */ -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM20_CLKIN (STM32_PCLK2_FREQUENCY) #ifdef CONFIG_STM32_FDCAN # ifdef CONFIG_BOARD_STM32_BG431BESC1_USE_HSE diff --git a/boards/arm/stm32g4/nucleo-g431kb/include/board.h b/boards/arm/stm32g4/nucleo-g431kb/include/board.h index c3a80f1c3122c..13dfc366b64af 100644 --- a/boards/arm/stm32g4/nucleo-g431kb/include/board.h +++ b/boards/arm/stm32g4/nucleo-g431kb/include/board.h @@ -139,19 +139,19 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -161,18 +161,18 @@ * otherwise frequency is 2xAPBx. */ -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM20_CLKIN (STM32_PCLK2_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32g4/nucleo-g431rb/include/board.h b/boards/arm/stm32g4/nucleo-g431rb/include/board.h index 75cc137c57439..beef76050907e 100644 --- a/boards/arm/stm32g4/nucleo-g431rb/include/board.h +++ b/boards/arm/stm32g4/nucleo-g431rb/include/board.h @@ -214,19 +214,19 @@ /* Timers driven from APB2 will be PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 timers 2-7 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* USB divider -- Divide PLL clock by 1.5 */ @@ -236,18 +236,18 @@ * otherwise frequency is 2xAPBx. */ -#define BOARD_TIM1_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM2_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM3_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM4_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM5_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM6_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM7_FREQUENCY (STM32_PCLK1_FREQUENCY) -#define BOARD_TIM8_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM15_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM16_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM17_FREQUENCY (STM32_PCLK2_FREQUENCY) -#define BOARD_TIM20_FREQUENCY (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM20_CLKIN (STM32_PCLK2_FREQUENCY) #ifdef CONFIG_STM32_FDCAN # ifdef CONFIG_BOARD_NUCLEO_G431RB_USE_HSE diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index 1c9caa9d66353..306036bc2ebd8 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -214,15 +214,15 @@ #define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1d2 /* PCLK1 = HCLK / 2 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ @@ -230,11 +230,11 @@ #define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK1 /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (STM32_PCLK2_FREQUENCY) /* Configure the APB3 prescaler */ @@ -251,19 +251,19 @@ * frequency as that of the APB domain. Otherwise they are set to twice. */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM12_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM13_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM14_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM12_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM13_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM14_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index d4283242bc221..8c251c0084236 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -206,23 +206,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/nucleo-h723zg/include/board.h b/boards/arm/stm32h7/nucleo-h723zg/include/board.h index 41d7e715f06a1..c17128c6bff08 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/include/board.h +++ b/boards/arm/stm32h7/nucleo-h723zg/include/board.h @@ -193,23 +193,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/nucleo-h743zi/include/board.h b/boards/arm/stm32h7/nucleo-h743zi/include/board.h index 744ddeede6069..a65dbd01d3322 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi/include/board.h @@ -193,23 +193,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h index d9a2041fb6716..8dcf40f8aa4e0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/include/board.h @@ -193,23 +193,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h index 5ac9a8b7a4690..e24c53373b53c 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h @@ -193,23 +193,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/nucleo-h753zi/include/board.h b/boards/arm/stm32h7/nucleo-h753zi/include/board.h index 66b77b6ff83ef..2b6c7db42fb06 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h753zi/include/board.h @@ -193,23 +193,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/openh743i/include/board.h b/boards/arm/stm32h7/openh743i/include/board.h index ac18190003e0a..b6fade811bd75 100644 --- a/boards/arm/stm32h7/openh743i/include/board.h +++ b/boards/arm/stm32h7/openh743i/include/board.h @@ -196,23 +196,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/portenta-h7/include/board.h b/boards/arm/stm32h7/portenta-h7/include/board.h index 14d214598f0d3..5bf781dea0b67 100644 --- a/boards/arm/stm32h7/portenta-h7/include/board.h +++ b/boards/arm/stm32h7/portenta-h7/include/board.h @@ -190,23 +190,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h index 51fa696247120..0488e67225e5a 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h @@ -189,23 +189,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/stm32h747i-disco/include/board.h b/boards/arm/stm32h7/stm32h747i-disco/include/board.h index 54701cc1ac72d..eb00f8f236b43 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h747i-disco/include/board.h @@ -185,23 +185,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/stm32h750b-dk/include/board.h b/boards/arm/stm32h7/stm32h750b-dk/include/board.h index 6f7b603a38cbd..aabeaf45d2b88 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h750b-dk/include/board.h @@ -187,23 +187,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/weact-stm32h743/include/board.h b/boards/arm/stm32h7/weact-stm32h743/include/board.h index 366a3af7cdb76..3341174e043e1 100644 --- a/boards/arm/stm32h7/weact-stm32h743/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h743/include/board.h @@ -208,23 +208,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32h7/weact-stm32h750/include/board.h b/boards/arm/stm32h7/weact-stm32h750/include/board.h index 321f5f4417cc4..db11c4a465db8 100644 --- a/boards/arm/stm32h7/weact-stm32h750/include/board.h +++ b/boards/arm/stm32h7/weact-stm32h750/include/board.h @@ -208,23 +208,23 @@ /* Timers driven from APB1 will be twice PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be twice PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Kernel Clock Configuration * diff --git a/boards/arm/stm32l1/stm32ldiscovery/include/board.h b/boards/arm/stm32l1/stm32ldiscovery/include/board.h index 9e1c58d534cde..2bf01551dbb6f 100644 --- a/boards/arm/stm32l1/stm32ldiscovery/include/board.h +++ b/boards/arm/stm32l1/stm32ldiscovery/include/board.h @@ -132,9 +132,9 @@ /* APB2 timers 9, 10, and 11 will receive PCLK2. */ -#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM9_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM10_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM11_CLKIN (STM32_PCLK2_FREQUENCY) /* APB1 clock (PCLK1) is HCLK (32MHz) */ @@ -143,12 +143,12 @@ /* APB1 timers 2-7 will receive PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 508ba420e0d30..3b89f03d2eba3 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -298,12 +298,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY -#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_TIM7_CLKIN STM32_PCLK1_FREQUENCY #define STM32_APB1_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY #define STM32_APB1_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY @@ -316,11 +316,11 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM8_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM8_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -394,20 +394,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -473,20 +473,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -495,17 +495,6 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN -#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN -#define BOARD_TIM15_FREQUENCY STM32_APB2_TIM15_CLKIN -#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN #define BOARD_LPTIM1_FREQUENCY STM32_APB1_LPTIM1_CLKIN #define BOARD_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index ecfabfc0424d3..8fec793b89ee1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "b-l475e-iot01a.h" /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index 097de375d1032..5487ffb5d50c0 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -293,9 +293,9 @@ * REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) @@ -311,9 +311,9 @@ * REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -390,9 +390,9 @@ * REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ @@ -406,9 +406,9 @@ * REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -477,9 +477,9 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) #define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) @@ -488,9 +488,9 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -500,12 +500,12 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index c1842f4e555f5..97b530c714264 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -44,7 +44,7 @@ #include "ram_vectors.h" #include "stm32l4_pwm.h" -#include "stm32l4_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_NUCLEOL432KC_SPWM diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c index 8d7ac77627f2f..50a21574bffed 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "nucleo-l432kc.h" #ifdef CONFIG_TIMER diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 1cdf8d97ca8a2..7e8b0b2f4d79a 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -289,12 +289,12 @@ * REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -308,9 +308,9 @@ * REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -380,21 +380,21 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -463,21 +463,21 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -487,15 +487,15 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 07dd18aa069c8..87ccb81fa585a 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -291,12 +291,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -307,11 +307,11 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -385,23 +385,23 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -467,23 +467,23 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -492,17 +492,17 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c index 7ae7885ca8bfe..a29fd9da67f92 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c @@ -29,7 +29,7 @@ #include -#include "stm32l4_tim.h" +#include "stm32_tim.h" #include "nucleo-l476rg.h" #ifdef CONFIG_TIMER diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index e753e7f0952cc..b4f3b55f74f21 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -143,12 +143,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -159,11 +159,11 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -253,12 +253,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -269,11 +269,11 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -364,12 +364,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -380,11 +380,11 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -400,17 +400,17 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 0526495312eb5..6a52b579acc2c 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -237,12 +237,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -253,28 +253,28 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index 7522919c39291..80dc22d1b42df 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -157,12 +157,12 @@ /* REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -173,8 +173,8 @@ /* REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -241,20 +241,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -263,17 +263,17 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM3_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM4_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM5_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM6_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM7_CLKIN (STM32_HCLK_FREQUENCY / 2) +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index 95845e26c5e2a..6d1f2b998ff87 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -155,12 +155,12 @@ * REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ @@ -174,8 +174,8 @@ * REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) @@ -240,20 +240,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -319,20 +319,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -343,17 +343,17 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index 1ed98a871a886..d3bcd950fcd7d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -165,12 +165,12 @@ * REVISIT : this can be configured */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (120 MHz) */ @@ -184,8 +184,8 @@ * REVISIT : this can be configured */ -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) @@ -268,20 +268,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) @@ -365,20 +365,20 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif /* clock selection */ @@ -388,17 +388,17 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM8_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 7b8d6d255d865..094897bbc3d01 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -128,21 +128,21 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -150,15 +150,15 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index ec882f5582b2e..be266e4725b47 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -83,15 +83,15 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h index e0165c42c9d9e..097cd12579b2c 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h +++ b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h @@ -102,21 +102,21 @@ #define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* Configure the APB3 prescaler */ @@ -129,15 +129,15 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h index 3ba1bc1f1346b..eed9f712db485 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/include/board.h @@ -102,21 +102,21 @@ #define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) -#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ #define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* Configure the APB3 prescaler */ @@ -129,15 +129,15 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM3_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM4_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM5_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM6_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM7_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM15_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY diff --git a/boards/arm/stm32wb/common/Makefile b/boards/arm/stm32wb/common/Makefile index 37068a4128551..da97d77279947 100644 --- a/boards/arm/stm32wb/common/Makefile +++ b/boards/arm/stm32wb/common/Makefile @@ -23,6 +23,7 @@ include $(TOPDIR)/Make.defs STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 include board/Make.defs include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs @@ -34,3 +35,5 @@ include $(TOPDIR)/boards/Board.mk ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src BOARDDIR = $(ARCHSRCDIR)$(DELIM)board CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +CXXFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index a2ac79cd543a2..c8acd40d7bfdf 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -218,18 +218,13 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) - -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define STM32_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) /* Higher SYSCLK requires more flash wait states. */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index 2f549b32aac0a..aa5f77a85a7a5 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -40,7 +40,7 @@ #include -#include "stm32wb_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_RTC_DRIVER # include diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index 8c3ef4e018927..58dfad13b3027 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -219,18 +219,13 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) - -#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define STM32_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) /* Higher SYSCLK requires more flash wait states. */ diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index ff849aff0dbc2..6420d71a69874 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -40,7 +40,7 @@ #include -#include "stm32wb_tim.h" +#include "stm32_tim.h" #ifdef CONFIG_RTC_DRIVER # include diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 9616e510d43d0..b5ff367de60cf 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -87,7 +87,7 @@ * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ @@ -99,9 +99,9 @@ * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY -#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -109,10 +109,10 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM1_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM2_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM16_CLKIN STM32_HCLK_FREQUENCY +#define STM32_TIM17_CLKIN STM32_HCLK_FREQUENCY #define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY From c588fc75bcf49dbf5065e442acc6f9b051c4d7b4 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 15:29:56 +0200 Subject: [PATCH 49/52] arch/arm/src/stm32: unify TIM free-running wrapper into common/stm32 Merge the per-IP and per-family free-running timer wrappers into a single common/stm32/stm32_freerun.c, following the timer-driver unification. - Rename stm32_freerun_m3m4_v1.c -> common/stm32/stm32_freerun.c (the most complete variant: CONFIG_CLOCK_TIMEKEEPING handling, timer-width based period, GTIM_SR_UIF/GTIM_DIER_UIE). - Delete the stm32l4_freerun.{c,h} and stm32wb_freerun.{c,h} copies Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 7 +- arch/arm/src/common/stm32/Make.defs | 6 +- ...tm32_freerun_m3m4_v1.c => stm32_freerun.c} | 4 +- arch/arm/src/stm32l4/CMakeLists.txt | 4 - arch/arm/src/stm32l4/Make.defs | 4 - arch/arm/src/stm32l4/stm32l4_freerun.c | 275 ---------------- arch/arm/src/stm32l4/stm32l4_freerun.h | 144 --------- arch/arm/src/stm32l4/stm32l4_tickless.c | 2 +- arch/arm/src/stm32wb/CMakeLists.txt | 4 - arch/arm/src/stm32wb/Make.defs | 4 - arch/arm/src/stm32wb/stm32wb_freerun.c | 300 ------------------ arch/arm/src/stm32wb/stm32wb_freerun.h | 162 ---------- 12 files changed, 10 insertions(+), 906 deletions(-) rename arch/arm/src/common/stm32/{stm32_freerun_m3m4_v1.c => stm32_freerun.c} (99%) delete mode 100644 arch/arm/src/stm32l4/stm32l4_freerun.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_freerun.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_freerun.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_freerun.h diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 37ce8f404482a..42abf1271ccf6 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -43,6 +43,10 @@ if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() +if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun.c) +endif() + if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() @@ -160,9 +164,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) endif() - if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun_m3m4_v1.c) - endif() if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 0b2b6a4c9b3dc..15273053cc7e4 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -49,6 +49,9 @@ endif ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun.c +endif ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c @@ -161,9 +164,6 @@ CHIP_CSRCS += stm32_oneshot_m3m4_v1.c CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c endif -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun_m3m4_v1.c -endif ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) ifeq ($(CONFIG_STM32_I2C_ALT),y) diff --git a/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_freerun.c similarity index 99% rename from arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c rename to arch/arm/src/common/stm32/stm32_freerun.c index e8122d5ef413c..9acf845613104 100644 --- a/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_freerun.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c + * arch/arm/src/common/stm32/stm32_freerun.c * * SPDX-License-Identifier: Apache-2.0 * @@ -298,4 +298,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32_ONESHOT */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 6819874852428..f9ac93729f508 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -54,10 +54,6 @@ if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32l4_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 71f2b4cc9ace3..1037364814b30 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -51,10 +51,6 @@ ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32l4_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c deleted file mode 100644 index c768b6237e352..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ /dev/null @@ -1,275 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_freerun.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "stm32l4_freerun.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * tch - The handle that represents the timer state - * arg - An opaque argument provided when the interrupt was registered - * sr - The value of the timer interrupt status register at the time - * that the interrupt occurred. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static int stm32_freerun_handler(int irq, void *context, void *arg) -{ - struct stm32_freerun_s *freerun = - (struct stm32_freerun_s *)arg; - - DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); - freerun->overflow++; - - STM32_TIM_ACKINT(freerun->tch, 0); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, - int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(freerun != NULL && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - freerun->frequency = frequency; - - freerun->tch = stm32_tim_init(chan); - if (!freerun->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(freerun->tch, frequency); - - /* Initialize the remaining fields in the state structure and return - * success. - */ - - freerun->chan = chan; - freerun->overflow = 0; - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); - - /* Set timer period */ - - STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); - - /* Start the counter */ - - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); - STM32_TIM_ACKINT(freerun->tch, 0); - STM32_TIM_ENABLEINT(freerun->tch, 0); - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time from the free-running - * timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(freerun && freerun->tch && ts); - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = freerun->overflow; - counter = STM32_TIM_GETCOUNTER(freerun->tch); - pending = STM32_TIM_CHECKINT(freerun->tch, 0); - verify = STM32_TIM_GETCOUNTER(freerun->tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(freerun->tch, 0); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update freerun overflow counter. */ - - freerun->overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", - (unsigned long)counter, (unsigned long)verify, - (unsigned long)overflow, pending); - tmrinfo("frequency=%u\n", freerun->frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) / - freerun->frequency; - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) -{ - DEBUGASSERT(freerun && freerun->tch); - - /* Now we can disable the timer interrupt and disable the timer. */ - - STM32_TIM_DISABLEINT(freerun->tch, 0); - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); - - /* Free the timer */ - - stm32_tim_deinit(freerun->tch); - freerun->tch = NULL; - - return OK; -} - -#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h deleted file mode 100644 index 74fbb860d2812..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ /dev/null @@ -1,144 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since the - * contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint32_t overflow; /* Timer counter overflow */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index 541399ba03829..d89d00a753d32 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -79,7 +79,7 @@ #include #include "stm32l4_oneshot.h" -#include "stm32l4_freerun.h" +#include "stm32_freerun.h" #ifdef CONFIG_SCHED_TICKLESS diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 114d8d7e4c40a..d4fb4c0a6348f 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -54,10 +54,6 @@ if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32wb_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 344959083e3ef..6b937e68c04ed 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -54,10 +54,6 @@ ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32wb_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c deleted file mode 100644 index c308a611db3c9..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ /dev/null @@ -1,300 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_freerun.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "stm32wb_freerun.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_handler - * - * Description: - * Timer interrupt callback. When the freerun timer counter overflows, - * this interrupt will occur. We will just increment an overflow count. - * - * Input Parameters: - * tch - The handle that represents the timer state - * arg - An opaque argument provided when the interrupt was registered - * sr - The value of the timer interrupt status register at the time - * that the interrupt occurred. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32_freerun_handler(int irq, void *context, void *arg) -{ - struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; - - DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); - freerun->overflow++; - - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - return OK; -} -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(freerun != NULL && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - freerun->frequency = frequency; - - freerun->tch = stm32_tim_init(chan); - if (!freerun->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(freerun->tch, frequency); - - /* Initialize the remaining fields in the state structure and return - * success. - */ - - freerun->chan = chan; - freerun->width = STM32_TIM_GETWIDTH(freerun->tch); - -#ifdef CONFIG_CLOCK_TIMEKEEPING - freerun->counter_mask = 0xffffffff; -#endif - -#ifndef CONFIG_CLOCK_TIMEKEEPING - freerun->overflow = 0; - - /* Set up to receive the callback when the counter overflow occurs */ - - STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); -#endif - - /* Set timer period */ - - STM32_TIM_SETPERIOD(freerun->tch, - (uint32_t)((1ull << freerun->width) - 1)); - - /* Start the counter */ - - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); - -#ifndef CONFIG_CLOCK_TIMEKEEPING - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time from the free-running - * timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts) -{ - uint64_t usec; - uint32_t counter; - uint32_t verify; - uint32_t overflow; - uint32_t sec; - int pending; - irqstate_t flags; - - DEBUGASSERT(freerun && freerun->tch && ts); - - /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32_tc_getpending() will reset the pending - * interrupt status. If we do not handle the overflow here then, it will - * be lost. - */ - - flags = enter_critical_section(); - - overflow = freerun->overflow; - counter = STM32_TIM_GETCOUNTER(freerun->tch); - pending = STM32_TIM_CHECKINT(freerun->tch, 0); - verify = STM32_TIM_GETCOUNTER(freerun->tch); - - /* If an interrupt was pending before we re-enabled interrupts, - * then the overflow needs to be incremented. - */ - - if (pending) - { - STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - - /* Increment the overflow count and use the value of the - * guaranteed to be AFTER the overflow occurred. - */ - - overflow++; - counter = verify; - - /* Update freerun overflow counter. */ - - freerun->overflow = overflow; - } - - leave_critical_section(flags); - - tmrinfo("counter=%" PRIu32 " (%" PRIu32 ") overflow=%" PRIu32 - ", pending=%i\n", - counter, verify, overflow, pending); - tmrinfo("frequency=%" PRIu32 "\n", freerun->frequency); - - /* Convert the whole thing to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = ((((uint64_t)overflow << freerun->width) + - (uint64_t)counter) * USEC_PER_SEC) / freerun->frequency; - - /* And return the value of the timer */ - - sec = (uint32_t)(usec / USEC_PER_SEC); - ts->tv_sec = sec; - ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - tmrinfo("usec=%llu ts=(%jd, %ld)\n", - usec, (intmax_t)ts->tv_sec, ts->tv_nsec); - - return OK; -} - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter) -{ - *counter = STM32_TIM_GETCOUNTER(freerun->tch); - return OK; -} - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) -{ - DEBUGASSERT(freerun && freerun->tch); - - /* Now we can disable the timer interrupt and disable the timer. */ - - STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); - - /* Free the timer */ - - stm32_tim_deinit(freerun->tch); - freerun->tch = NULL; - - return OK; -} - -#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h deleted file mode 100644 index ae4dd49ba9c3a..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ /dev/null @@ -1,162 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32wb_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ From 5bbf345b75213c3d03549ba5b6fb5fd86d9e723b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 16:12:08 +0200 Subject: [PATCH 50/52] arch/arm/src/stm32: unify TIM one-shot wrapper into common/stm32 Merge the per-IP and per-family one-shot timer wrappers (driver + lower-half) into a single common/stm32/stm32_oneshot.c and stm32_oneshot_lowerhalf.c, following the timer-driver and free-run unification. - Rename stm32_oneshot_m3m4_v1{,_lowerhalf}.c -> common/stm32/stm32_oneshot {,_lowerhalf}.c (the most complete variant: full counter/period cancel logic). - Delete the stm32h7/stm32_oneshot*, stm32l4_oneshot* and stm32wb_oneshot* copies Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 8 +- arch/arm/src/common/stm32/Make.defs | 8 +- .../{stm32h7 => common/stm32}/stm32_oneshot.c | 78 ++- .../stm32}/stm32_oneshot_lowerhalf.c | 2 +- .../src/common/stm32/stm32_oneshot_m3m4_v1.c | 458 ----------------- .../stm32/stm32_oneshot_m3m4_v1_lowerhalf.c | 309 ------------ arch/arm/src/stm32h7/CMakeLists.txt | 4 - arch/arm/src/stm32h7/Make.defs | 4 - arch/arm/src/stm32h7/stm32_oneshot.h | 197 -------- arch/arm/src/stm32l4/CMakeLists.txt | 4 - arch/arm/src/stm32l4/Make.defs | 4 - arch/arm/src/stm32l4/stm32l4_oneshot.c | 460 ------------------ arch/arm/src/stm32l4/stm32l4_oneshot.h | 198 -------- .../src/stm32l4/stm32l4_oneshot_lowerhalf.c | 310 ------------ arch/arm/src/stm32l4/stm32l4_tickless.c | 2 +- arch/arm/src/stm32wb/CMakeLists.txt | 5 +- arch/arm/src/stm32wb/Make.defs | 4 - arch/arm/src/stm32wb/stm32wb_oneshot.c | 459 ----------------- arch/arm/src/stm32wb/stm32wb_oneshot.h | 198 -------- .../src/stm32wb/stm32wb_oneshot_lowerhalf.c | 309 ------------ 20 files changed, 77 insertions(+), 2944 deletions(-) rename arch/arm/src/{stm32h7 => common/stm32}/stm32_oneshot.c (84%) rename arch/arm/src/{stm32h7 => common/stm32}/stm32_oneshot_lowerhalf.c (99%) delete mode 100644 arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c delete mode 100644 arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c delete mode 100644 arch/arm/src/stm32h7/stm32_oneshot.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_oneshot.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_oneshot.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_oneshot.c delete mode 100644 arch/arm/src/stm32wb/stm32wb_oneshot.h delete mode 100644 arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 42abf1271ccf6..6acfd2a2b20c6 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -47,6 +47,10 @@ if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32_freerun.c) endif() +if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) +endif() + if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() @@ -160,10 +164,6 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) - endif() - if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 15273053cc7e4..cd03a02b85179 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -52,6 +52,10 @@ endif ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32_freerun.c endif +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot.c +CHIP_CSRCS += stm32_oneshot_lowerhalf.c +endif ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c @@ -159,10 +163,6 @@ CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c endif endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot_m3m4_v1.c -CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c -endif ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/common/stm32/stm32_oneshot.c similarity index 84% rename from arch/arm/src/stm32h7/stm32_oneshot.c rename to arch/arm/src/common/stm32/stm32_oneshot.c index e1fc56718ec77..fa11cb6e2465b 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/common/stm32/stm32_oneshot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot.c + * arch/arm/src/common/stm32/stm32_oneshot.c * * SPDX-License-Identifier: Apache-2.0 * @@ -79,7 +79,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) oneshot_handler_t oneshot_handler; void *oneshot_arg; - tmrinfo("Expired (Interrupt)...\n"); + tmrinfo("Expired...\n"); DEBUGASSERT(oneshot != NULL && oneshot->handler); /* The clock was stopped, but not disabled when the RC match occurred. @@ -185,14 +185,12 @@ int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, { uint32_t frequency; - tmrinfo("chan=%d resolution=%u usec, USEC_PER_SEC:%ld\n", chan, resolution, - USEC_PER_SEC); + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); DEBUGASSERT(oneshot && resolution > 0); /* Get the TC frequency the corresponds to the requested resolution */ frequency = USEC_PER_SEC / (uint32_t)resolution; - tmrinfo("frequency: %" PRIu32 "\n", frequency); oneshot->frequency = frequency; oneshot->tch = stm32_tim_init(chan); @@ -228,8 +226,6 @@ int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); - tmrinfo("frequency: %" PRIu32 ", USEC_PER_SEC: %ld\n", oneshot->frequency, - USEC_PER_SEC); *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * (uint64_t)USEC_PER_SEC; return OK; @@ -263,8 +259,8 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, uint64_t period; irqstate_t flags; - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", handler, arg, - (intmax_t)ts->tv_sec, ts->tv_nsec); + tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", + handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); DEBUGASSERT(oneshot && handler && ts); DEBUGASSERT(oneshot->tch); @@ -356,6 +352,11 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; /* Was the timer running? */ @@ -373,8 +374,22 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } + /* Yes.. Get the timer counter and period registers and stop the counter. + * If the counter expires while we are doing this, the counter clock will + * be stopped, but the clock will not be disabled. + * + * The expected behavior is that the counter register will freezes at + * a value equal to the RC register when the timer expires. The counter + * should have values between 0 and RC in all other cased. + * + * REVISIT: This does not appear to be the case. + */ + tmrinfo("Cancelling...\n"); + count = STM32_TIM_GETCOUNTER(oneshot->tch); + period = oneshot->period; + /* Now we can disable the interrupt and stop the timer. */ STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); @@ -392,10 +407,49 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, if (ts) { - /* Not implemented */ + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ - ts->tv_sec = 0; - ts->tv_nsec = 0; + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + /* REVISIT: I am not certain why the timer counter value sometimes + * exceeds RC. Might be a bug, or perhaps the counter does not stop + * in all cases. + */ + + if (count >= period) + { + /* No time remaining (?) */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + oneshot->frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = sec; + ts->tv_nsec = nsec; + } + + tmrinfo("remaining (%jd, %ld)\n", + (intmax_t)ts->tv_sec, ts->tv_nsec); } return OK; diff --git a/arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c index edec93ec7ecc5..d7aa7dd6d60c7 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot_lowerhalf.c + * arch/arm/src/common/stm32/stm32_oneshot_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c deleted file mode 100644 index e8ba155e9daf7..0000000000000 --- a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c +++ /dev/null @@ -1,458 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irg_num, void * context, void *arg) -{ - struct stm32_oneshot_s * oneshot = (struct stm32_oneshot_s *) arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c deleted file mode 100644 index 729adb4078c3e..0000000000000 --- a/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c +++ /dev/null @@ -1,309 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, - uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index 22ce914736dd2..b1a0e18f08705 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -56,10 +56,6 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - if(CONFIG_ARM_MPU) list(APPEND SRCS stm32_mpuinit.c) endif() diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 994875de36094..0d26445cb16ef 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -55,10 +55,6 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - ifeq ($(CONFIG_ARM_MPU),y) CHIP_CSRCS += stm32_mpuinit.c endif diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h deleted file mode 100644 index f16523985ff1f..0000000000000 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The client - * should not access the contents of this structure directly since the - * contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index f9ac93729f508..3b96f6c2c67b0 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -50,10 +50,6 @@ else() list(APPEND SRCS stm32l4_tickless.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 1037364814b30..c348535830112 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -47,10 +47,6 @@ else CHIP_CSRCS += stm32l4_tickless.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c deleted file mode 100644 index ebacd10a6096c..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ /dev/null @@ -1,460 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32l4_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg) -{ - struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *) arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, 0); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, - int chan, uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period > 0); - DEBUGASSERT(period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, 0); - STM32_TIM_ENABLEINT(oneshot->tch, 0); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, 0); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h deleted file mode 100644 index 6fc35b5e7a798..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H -#define __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c deleted file mode 100644 index 12474e6080762..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ /dev/null @@ -1,310 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32l4_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half - * driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, - uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index d89d00a753d32..a10568f71076e 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -78,7 +78,7 @@ #include #include -#include "stm32l4_oneshot.h" +#include "stm32_oneshot.h" #include "stm32_freerun.h" #ifdef CONFIG_SCHED_TICKLESS diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index d4fb4c0a6348f..5670aff03817e 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -42,6 +42,7 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) endif() if(CONFIG_TIMER) + endif() if(NOT CONFIG_SCHED_TICKLESS) @@ -50,10 +51,6 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index 6b937e68c04ed..33bd782620d9c 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -50,10 +50,6 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c deleted file mode 100644 index 80e63c4b4e9f8..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ /dev/null @@ -1,459 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "stm32wb_oneshot.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Common timer interrupt callback. When any oneshot timer interrupt - * expires, this function will be called. It will forward the call to - * the next level up. - * - * Input Parameters: - * oneshot - The state associated with the expired timer - * - * Returned Value: - * Always returns OK - * - ****************************************************************************/ - -static int stm32_oneshot_handler(int irq, void *context, void *arg) -{ - struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; - oneshot_handler_t oneshot_handler; - void *oneshot_arg; - - tmrinfo("Expired...\n"); - DEBUGASSERT(oneshot != NULL && oneshot->handler); - - /* The clock was stopped, but not disabled when the RC match occurred. - * Disable the TC now and disable any further interrupts. - */ - - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - - /* The timer is no longer running */ - - oneshot->running = false; - - /* Forward the event, clearing out any vestiges */ - - oneshot_handler = (oneshot_handler_t)oneshot->handler; - oneshot->handler = NULL; - oneshot_arg = (void *)oneshot->arg; - oneshot->arg = NULL; - - oneshot_handler(oneshot_arg); - return OK; -} - -/**************************************************************************** - * Name: stm32_allocate_handler - * - * Description: - * Allocate a timer callback handler for the oneshot instance. - * - * Input Parameters: - * oneshot - The state instance the new oneshot timer - * - * Returned Value: - * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. - * - ****************************************************************************/ - -static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) -{ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - int ret = -EBUSY; - int i; - - /* Search for an unused handler */ - - for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) - { - /* Is this handler available? */ - - if (g_oneshot[i] == NULL) - { - /* Yes... assign it to this oneshot */ - - g_oneshot[i] = oneshot; - oneshot->cbndx = i; - ret = OK; - break; - } - } - - return ret; - -#else - if (g_oneshot[0] == NULL) - { - g_oneshot[0] = oneshot; - return OK; - } - - return -EBUSY; -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, - int chan, uint16_t resolution) -{ - uint32_t frequency; - - tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); - DEBUGASSERT(oneshot && resolution > 0); - - /* Get the TC frequency the corresponds to the requested resolution */ - - frequency = USEC_PER_SEC / (uint32_t)resolution; - oneshot->frequency = frequency; - - oneshot->tch = stm32_tim_init(chan); - if (!oneshot->tch) - { - tmrerr("ERROR: Failed to allocate TIM%d\n", chan); - return -EBUSY; - } - - STM32_TIM_SETCLOCK(oneshot->tch, frequency); - - /* Initialize the remaining fields in the state structure. */ - - oneshot->chan = chan; - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - - /* Assign a callback handler to the oneshot */ - - return stm32_allocate_handler(oneshot); -} - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec) -{ - DEBUGASSERT(oneshot != NULL && usec != NULL); - - *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * - (uint64_t)USEC_PER_SEC; - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts) -{ - uint64_t usec; - uint64_t period; - irqstate_t flags; - - tmrinfo("handler=%p arg=%p, ts=(%jd, %ld)\n", - handler, arg, (intmax_t)ts->tv_sec, ts->tv_nsec); - DEBUGASSERT(oneshot && handler && ts); - DEBUGASSERT(oneshot->tch); - - /* Was the oneshot already running? */ - - flags = enter_critical_section(); - if (oneshot->running) - { - /* Yes.. then cancel it */ - - tmrinfo("Already running... cancelling\n"); - stm32_oneshot_cancel(oneshot, NULL); - } - - /* Save the new handler and its argument */ - - oneshot->handler = handler; - oneshot->arg = arg; - - /* Express the delay in microseconds */ - - usec = ts->tv_sec * USEC_PER_SEC + - (ts->tv_nsec / NSEC_PER_USEC); - - /* Get the timer counter frequency and determine the number of counts need - * to achieve the requested delay. - * - * frequency = ticks / second - * ticks = seconds * frequency - * = (usecs * frequency) / USEC_PER_SEC; - */ - - period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; - - tmrinfo("usec=%llu period=%08llx\n", usec, period); - DEBUGASSERT(period > 0 && period <= UINT32_MAX); - - /* Set up to receive the callback when the interrupt occurs */ - - STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); - - /* Set timer period */ - - oneshot->period = (uint32_t)period; - STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); - - /* Start the counter */ - - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - - STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); - - /* Enable interrupts. We should get the callback when the interrupt - * occurs. - */ - - oneshot->running = true; - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. ts may be zero in which case the time remaining - * is not returned. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts) -{ - irqstate_t flags; - uint64_t usec; - uint64_t sec; - uint64_t nsec; - uint32_t count; - uint32_t period; - - /* Was the timer running? */ - - flags = enter_critical_section(); - if (!oneshot->running) - { - /* No.. Just return zero timer remaining and successful cancellation. - * This function may execute at a high rate with no timer running - * (as when pre-emption is enabled and disabled). - */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - leave_critical_section(flags); - return OK; - } - - /* Yes.. Get the timer counter and period registers and stop the counter. - * If the counter expires while we are doing this, the counter clock will - * be stopped, but the clock will not be disabled. - * - * The expected behavior is that the counter register will freezes at - * a value equal to the RC register when the timer expires. The counter - * should have values between 0 and RC in all other cased. - * - * REVISIT: This does not appear to be the case. - */ - - tmrinfo("Cancelling...\n"); - - count = STM32_TIM_GETCOUNTER(oneshot->tch); - period = oneshot->period; - - /* Now we can disable the interrupt and stop the timer. */ - - STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); - - oneshot->running = false; - oneshot->handler = NULL; - oneshot->arg = NULL; - leave_critical_section(flags); - - /* Did the caller provide us with a location to return the time - * remaining? - */ - - if (ts) - { - /* Yes.. then calculate and return the time remaining on the - * oneshot timer. - */ - - tmrinfo("period=%lu count=%lu\n", - (unsigned long)period, (unsigned long)count); - - /* REVISIT: I am not certain why the timer counter value sometimes - * exceeds RC. Might be a bug, or perhaps the counter does not stop - * in all cases. - */ - - if (count >= period) - { - /* No time remaining (?) */ - - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - else - { - /* The total time remaining is the difference. Convert that - * to units of microseconds. - * - * frequency = ticks / second - * seconds = ticks * frequency - * usecs = (ticks * USEC_PER_SEC) / frequency; - */ - - usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / - oneshot->frequency; - - /* Return the time remaining in the correct form */ - - sec = usec / USEC_PER_SEC; - nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; - - ts->tv_sec = sec; - ts->tv_nsec = nsec; - } - - tmrinfo("remaining (%jd, %ld)\n", - (intmax_t)ts->tv_sec, ts->tv_nsec); - } - - return OK; -} - -#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h deleted file mode 100644 index 9b02e37ca1cd4..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H -#define __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32wb_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, - uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c deleted file mode 100644 index d98270362c4b7..0000000000000 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ /dev/null @@ -1,309 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "stm32wb_oneshot.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure describes the state of the oneshot timer lower-half - * driver - */ - -struct stm32_oneshot_lowerhalf_s -{ - /* This is the part of the lower half driver that is visible to the upper- - * half client of the driver. This must be the first thing in this - * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. - */ - - struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ - - /* Private lower half data follows */ - - struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg); - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts); -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Lower half operations */ - -static const struct oneshot_operations_s g_oneshot_ops = -{ - .max_delay = stm32_max_delay, - .start = stm32_start, - .cancel = stm32_cancel, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_handler - * - * Description: - * Timer expiration handler - * - * Input Parameters: - * arg - Should be the same argument provided when stm32_oneshot_start() - * was called. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_oneshot_handler(void *arg) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)arg; - - DEBUGASSERT(priv != NULL); - - /* Perhaps the callback was nullified in a race condition with - * stm32_cancel? - */ - - oneshot_process_callback(&priv->lh); -} - -/**************************************************************************** - * Name: stm32_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the maximum delay. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - uint64_t usecs; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); - if (ret >= 0) - { - uint64_t sec = usecs / 1000000; - usecs -= 1000000 * sec; - - ts->tv_sec = sec; - ts->tv_nsec = usecs * 1000; - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * lower An instance of the lower-half oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -static int stm32_start(struct oneshot_lowerhalf_s *lower, - const struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL && ts != NULL); - - /* Save the callback information and start the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_start(&priv->oneshot, - stm32_oneshot_handler, priv, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Name: stm32_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * lower Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int stm32_cancel(struct oneshot_lowerhalf_s *lower, - struct timespec *ts) -{ - struct stm32_oneshot_lowerhalf_s *priv = - (struct stm32_oneshot_lowerhalf_s *)lower; - irqstate_t flags; - int ret; - - DEBUGASSERT(priv != NULL); - - /* Cancel the timer */ - - flags = enter_critical_section(); - ret = stm32_oneshot_cancel(&priv->oneshot, ts); - leave_critical_section(flags); - - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); - } - - return ret; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: oneshot_initialize - * - * Description: - * Initialize the oneshot timer and return a oneshot lower half driver - * instance. - * - * Input Parameters: - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * On success, a non-NULL instance of the oneshot lower-half driver is - * returned. NULL is return on any failure. - * - ****************************************************************************/ - -struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) -{ - struct stm32_oneshot_lowerhalf_s *priv; - int ret; - - /* Allocate an instance of the lower half driver */ - - priv = (struct stm32_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); - - if (priv == NULL) - { - tmrerr("ERROR: Failed to initialized state structure\n"); - return NULL; - } - - /* Initialize the lower-half driver structure */ - - priv->lh.ops = &g_oneshot_ops; - - /* Initialize the contained STM32 oneshot timer */ - - ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); - if (ret < 0) - { - tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); - kmm_free(priv); - return NULL; - } - - return &priv->lh; -} From af52953657e8e65655eaac4bbe26053da11f9903 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 18:58:42 +0200 Subject: [PATCH 51/52] arch/arm/src/stm32: unify TIM1/TIM8 interrupt vector names across families The TIM1 and TIM8 interrupt vectors are the same interrupts on every family, but were named inconsistently: - 21 families: STM32_IRQ_TIM1UP / TIM1BRK / TIM1TRGCOM / TIM1CC - H5/L5/U5/N6: STM32_IRQ_TIM1_UP / _BRK / _TRG_COM / _CC - Cortex-M0 (C0/F0/G0): combined STM32_IRQ_TIM1_BRK (BRK_UP_TRG_COM) Standardize on the majority no-underscore form so a driver can refer to e.g. STM32_IRQ_TIM1UP on any family. Signed-off-by: raiden00pl --- arch/arm/include/stm32c0/irq.h | 4 ++-- arch/arm/include/stm32f0/irq.h | 4 ++-- arch/arm/include/stm32g0/irq.h | 4 ++-- arch/arm/include/stm32h5/stm32h5xx_irq.h | 16 +++++++------- arch/arm/include/stm32l5/stm32l562xx_irq.h | 16 +++++++------- arch/arm/include/stm32n6/stm32n6xx_irq.h | 16 +++++++------- arch/arm/include/stm32u5/stm32u5xx_irq.h | 16 +++++++------- arch/arm/src/common/stm32/stm32_pulsecount.c | 22 ++------------------ 8 files changed, 40 insertions(+), 58 deletions(-) diff --git a/arch/arm/include/stm32c0/irq.h b/arch/arm/include/stm32c0/irq.h index aba16028025fb..6088325be6d9b 100644 --- a/arch/arm/include/stm32c0/irq.h +++ b/arch/arm/include/stm32c0/irq.h @@ -86,8 +86,8 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32f0/irq.h b/arch/arm/include/stm32f0/irq.h index c142f9068bef7..02cb919f01dc2 100644 --- a/arch/arm/include/stm32f0/irq.h +++ b/arch/arm/include/stm32f0/irq.h @@ -91,8 +91,8 @@ #define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */ #define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */ #define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */ #define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */ #define STM32_IRQ_TIM6 (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */ diff --git a/arch/arm/include/stm32g0/irq.h b/arch/arm/include/stm32g0/irq.h index 1edbcd2b85070..9eb1c521ac049 100644 --- a/arch/arm/include/stm32g0/irq.h +++ b/arch/arm/include/stm32g0/irq.h @@ -119,8 +119,8 @@ # define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ #endif -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index b6582c3ec075f..9207ef5a75df2 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -88,10 +88,10 @@ # define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ # define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ # define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -# define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -# define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -# define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -# define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +# define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +# define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +# define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +# define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ # define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ # define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ # define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ @@ -112,10 +112,10 @@ # define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 62) /* 62: UART5 global interrupt */ # define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 63) /* 63: LPUART1 global interrupt */ # define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 64) /* 64: LPTIM1 global interrupt */ -# define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ -# define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ -# define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ -# define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ +# define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 65) /* 65: TIM8_BRK global interrupt */ +# define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 66) /* 66: TIM8_UP global interrupt */ +# define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 67) /* 67: TIM8_TRG_COM global interrupt */ +# define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 68) /* 68: TIM8_CC global interrupt */ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index 35e326d15b003..b60e9e852446f 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -91,20 +91,20 @@ #define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/include/stm32n6/stm32n6xx_irq.h b/arch/arm/include/stm32n6/stm32n6xx_irq.h index ef186921d2791..71af964ef67ab 100644 --- a/arch/arm/include/stm32n6/stm32n6xx_irq.h +++ b/arch/arm/include/stm32n6/stm32n6xx_irq.h @@ -145,20 +145,20 @@ #define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 109) /* 109: I3C1 error interrupt */ #define STM32_IRQ_I3C2_EV (STM32_IRQ_FIRST + 110) /* 110: I3C2 event interrupt */ #define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 111) /* 111: I3C2 error interrupt */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 112) /* 112: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 113) /* 113: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 114) /* 114: TIM1 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 115) /* 115: TIM1 Capture Compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 116) /* 116: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 117) /* 117: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 118) /* 118: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 119) /* 119: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 120) /* 120: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 121) /* 121: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 122) /* 122: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 123) /* 123: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 124) /* 124: TIM8 Trigger and Commutation interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 125) /* 125: TIM8 Capture Compare interrupt */ #define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 126) /* 126: TIM9 global interrupt */ #define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 127) /* 127: TIM10 global interrupt */ #define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 128) /* 128: TIM11 global interrupt */ diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index bb629ca1eeb0e..57a3fe56b3671 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -90,28 +90,28 @@ #define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */ #define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */ #define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */ -#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ #define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */ #define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */ -#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ #define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */ #define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */ -#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ #define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ #define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ #define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ #define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ #define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ #define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ #define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 transition error */ #define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 index error */ -#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ #define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 53) /* 53: TIM8 direction change interrupt */ #define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 53) /* 53: TIM8 index */ -#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ #define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ #define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ #define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ diff --git a/arch/arm/src/common/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount.c index e46aa4e383196..14ed92dcfd248 100644 --- a/arch/arm/src/common/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount.c @@ -71,24 +71,6 @@ #define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR #define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST -/* The TIM1/TIM8 update-event interrupt vector is named differently across - * families - */ - -#if defined(STM32_IRQ_TIM1UP) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1UP -#elif defined(STM32_IRQ_TIM1_UP) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_UP -#elif defined(STM32_IRQ_TIM1_BRK) -# define PULSECOUNT_TIM1_IRQ STM32_IRQ_TIM1_BRK -#endif - -#if defined(STM32_IRQ_TIM8UP) -# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8UP -#elif defined(STM32_IRQ_TIM8_UP) -# define PULSECOUNT_TIM8_IRQ STM32_IRQ_TIM8_UP -#endif - /* Default GPIO pins state */ #if defined(CONFIG_STM32_STM32F10XX) @@ -270,7 +252,7 @@ static struct stm32_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM1_IRQ, + .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; @@ -321,7 +303,7 @@ static struct stm32_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, - .irq = PULSECOUNT_TIM8_IRQ, + .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; From 81c7a2b634ba3fa6f60706c125235f03385f1a62 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 19:10:25 +0200 Subject: [PATCH 52/52] arch/arm/src/stm32: unify quadrature encoder driver into common/stm32 Merge the per-IP (m0_v1, m3m4_v1v2v3) and per-family (f7/h7/l4) quadrature encoder drivers into a single common/stm32/stm32_qencoder.c, generalized for every STM32 family: - RCC clock-enable and reset use the common stm32_tim_clk.h aliases instead of per-chip register blocks. - 16/32-bit timer width is selected via STM32_HAVE_TIM2_32BITS / STM32_HAVE_TIM5_32BITS instead of per-chip-line #ifdefs. - The TIM1/TIM8 update interrupt uses the unified STM32_IRQ_TIM1UP / TIM8UP names (no per-family fallback). - GPIO input-float configuration is F1 vs. every other family. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/CMakeLists.txt | 13 +- arch/arm/src/common/stm32/Make.defs | 9 +- ...encoder_m3m4_v1v2v3.c => stm32_qencoder.c} | 174 +-- .../src/common/stm32/stm32_qencoder_m0_v1.c | 1254 ----------------- arch/arm/src/common/stm32/stm32_tim_clk.h | 233 ++- arch/arm/src/stm32f7/CMakeLists.txt | 3 - arch/arm/src/stm32f7/Make.defs | 3 - arch/arm/src/stm32f7/stm32_qencoder.c | 1183 ---------------- arch/arm/src/stm32f7/stm32_qencoder.h | 102 -- arch/arm/src/stm32h7/CMakeLists.txt | 3 - arch/arm/src/stm32h7/Make.defs | 3 - arch/arm/src/stm32h7/stm32_qencoder.c | 1184 ---------------- arch/arm/src/stm32h7/stm32_qencoder.h | 102 -- arch/arm/src/stm32l4/CMakeLists.txt | 3 - arch/arm/src/stm32l4/Make.defs | 3 - arch/arm/src/stm32l4/stm32l4_qencoder.c | 1189 ---------------- arch/arm/src/stm32l4/stm32l4_qencoder.h | 101 -- 17 files changed, 299 insertions(+), 5263 deletions(-) rename arch/arm/src/common/stm32/{stm32_qencoder_m3m4_v1v2v3.c => stm32_qencoder.c} (90%) delete mode 100644 arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c delete mode 100644 arch/arm/src/stm32f7/stm32_qencoder.c delete mode 100644 arch/arm/src/stm32f7/stm32_qencoder.h delete mode 100644 arch/arm/src/stm32h7/stm32_qencoder.c delete mode 100644 arch/arm/src/stm32h7/stm32_qencoder.h delete mode 100644 arch/arm/src/stm32l4/stm32l4_qencoder.c delete mode 100644 arch/arm/src/stm32l4/stm32l4_qencoder.h diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index 6acfd2a2b20c6..eee6cab0f36ba 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -50,6 +50,9 @@ endif() if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) endif() +if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder.c) +endif() if(CONFIG_STM32_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) @@ -92,7 +95,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdio_m3m4_v1.c) endif() - if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) list(APPEND SRCS stm32_ccm_m3m4_v1.c) endif() @@ -164,7 +166,6 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) @@ -291,10 +292,6 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) endif() - if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) - endif() - if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can_m3m4_v1.c) @@ -458,7 +455,6 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_rng_m0_v1.c) endif() - if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) list(APPEND SRCS stm32_iwdg_m0_v1.c) endif() @@ -476,9 +472,6 @@ if(CONFIG_ARCH_CORTEXM0) endif() endif() - if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder_m0_v1.c) - endif() endif() if(CONFIG_SENSORS_HALL3PHASE) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index cd03a02b85179..926fb42994aa4 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -56,6 +56,9 @@ ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot.c CHIP_CSRCS += stm32_oneshot_lowerhalf.c endif +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder.c +endif ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c @@ -322,9 +325,6 @@ ifeq ($(CONFIG_STM32_CAP),y) CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c endif -ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) -CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c -endif ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) @@ -526,9 +526,6 @@ endif endif endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder_m0_v1.c -endif endif diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c b/arch/arm/src/common/stm32/stm32_qencoder.c similarity index 90% rename from arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c rename to arch/arm/src/common/stm32/stm32_qencoder.c index f5c4bea0d22a0..dc2533949bee1 100644 --- a/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c +++ b/arch/arm/src/common/stm32/stm32_qencoder.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c + * arch/arm/src/common/stm32/stm32_qencoder.c * * SPDX-License-Identifier: Apache-2.0 * @@ -44,6 +44,7 @@ #include "stm32.h" #include "stm32_gpio.h" #include "stm32_tim.h" +#include "stm32_tim_clk.h" #include "stm32_qencoder.h" #ifdef CONFIG_SENSORS_QENCODER @@ -57,49 +58,44 @@ #undef HAVE_32BIT_TIMERS #undef HAVE_16BIT_TIMERS -/* On the F1 series, all timers are 16-bit. */ - -#if defined(CONFIG_STM32_STM32F10XX) - -# define HAVE_16BIT_TIMERS 1 +/* The width in bits of each timer. TIM2 and TIM5 are 32-bit on the families + * that select STM32_HAVE_TIM2_32BITS / STM32_HAVE_TIM5_32BITS; every other + * quadrature-capable timer is 16-bit. + */ - /* The width in bits of each timer */ +#define TIM1_BITWIDTH 16 -# define TIM1_BITWIDTH 16 +#ifdef CONFIG_STM32_HAVE_TIM2_32BITS +# define TIM2_BITWIDTH 32 +#else # define TIM2_BITWIDTH 16 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 16 -# define TIM8_BITWIDTH 16 - -/* On the F2, F3, F4 and G4 series, TIM2 and TIM5 are 32-bit. - * All of the rest are 16-bit - */ +#endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) +#define TIM3_BITWIDTH 16 +#define TIM4_BITWIDTH 16 - /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ +#ifdef CONFIG_STM32_HAVE_TIM5_32BITS +# define TIM5_BITWIDTH 32 +#else +# define TIM5_BITWIDTH 16 +#endif -# if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -# endif +#define TIM8_BITWIDTH 16 - /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ +/* If an enabled quadrature timer is 32-bit, then we have 32-bit timers */ -# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -# endif +#if (defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 32) || \ + (defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 32) +# define HAVE_32BIT_TIMERS 1 +#endif - /* The width in bits of each timer */ +/* If an enabled quadrature timer is 16-bit, then we have 16-bit timers */ -# define TIM1_BITWIDTH 16 -# define TIM2_BITWIDTH 32 -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 -# define TIM5_BITWIDTH 32 -# define TIM8_BITWIDTH 16 +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) || \ + (defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16) || \ + (defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16) +# define HAVE_16BIT_TIMERS 1 #endif /* Do we need to support mixed 16- and 32-bit timers */ @@ -172,85 +168,45 @@ #if defined(CONFIG_STM32_STM32F10XX) # define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_CNF_INFLOAT | \ GPIO_MODE_INPUT) -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F4XXX) || \ - defined(CONFIG_STM32_STM32G4XXX) -# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) #else -# error "Unrecognized STM32 chip" +# define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) #endif -/* RCC definitions */ - -#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR -# define TIMEN_TIM2 RCC_APB1ENR_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR -# define TIMRST_TIM2 RCC_APB1RSTR_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR -# define TIMEN_TIM3 RCC_APB1ENR_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR -# define TIMRST_TIM3 RCC_APB1RSTR_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR -# define TIMEN_TIM4 RCC_APB1ENR_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR -# define TIMRST_TIM4 RCC_APB1RSTR_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR -# define TIMEN_TIM5 RCC_APB1ENR_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR -# define TIMRST_TIM5 RCC_APB1RSTR_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST - -#elif defined(CONFIG_STM32_STM32G4XXX) - -# define TIMRCCEN_TIM1 STM32_RCC_APB2ENR -# define TIMEN_TIM1 RCC_APB2ENR_TIM1EN -# define TIMRCCRST_TIM1 STM32_RCC_APB2RSTR -# define TIMRST_TIM1 RCC_APB2RSTR_TIM1RST - -# define TIMRCCEN_TIM2 STM32_RCC_APB1ENR1 -# define TIMEN_TIM2 RCC_APB1ENR1_TIM2EN -# define TIMRCCRST_TIM2 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM2 RCC_APB1RSTR1_TIM2RST - -# define TIMRCCEN_TIM3 STM32_RCC_APB1ENR1 -# define TIMEN_TIM3 RCC_APB1ENR1_TIM3EN -# define TIMRCCRST_TIM3 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM3 RCC_APB1RSTR1_TIM3RST - -# define TIMRCCEN_TIM4 STM32_RCC_APB1ENR1 -# define TIMEN_TIM4 RCC_APB1ENR1_TIM4EN -# define TIMRCCRST_TIM4 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM4 RCC_APB1RSTR1_TIM4RST - -# define TIMRCCEN_TIM5 STM32_RCC_APB1ENR1 -# define TIMEN_TIM5 RCC_APB1ENR1_TIM5EN -# define TIMRCCRST_TIM5 STM32_RCC_APB1RSTR1 -# define TIMRST_TIM5 RCC_APB1RSTR1_TIM5RST - -# define TIMRCCEN_TIM8 STM32_RCC_APB2ENR -# define TIMEN_TIM8 RCC_APB2ENR_TIM8EN -# define TIMRCCRST_TIM8 STM32_RCC_APB2RSTR -# define TIMRST_TIM8 RCC_APB2RSTR_TIM8RST +/* RCC definitions + * + * The timer RCC clock-enable and reset register/bit are provided per family + * by the common stm32_tim_clk.h aliases. + */ -#else -# error "Unrecognized STM32 chip" -#endif +#define TIMRCCEN_TIM1 STM32_RCC_TIM1_EN_REG +#define TIMEN_TIM1 STM32_RCC_TIM1_EN +#define TIMRCCRST_TIM1 STM32_RCC_TIM1_RST_REG +#define TIMRST_TIM1 STM32_RCC_TIM1_RST + +#define TIMRCCEN_TIM2 STM32_RCC_TIM2_EN_REG +#define TIMEN_TIM2 STM32_RCC_TIM2_EN +#define TIMRCCRST_TIM2 STM32_RCC_TIM2_RST_REG +#define TIMRST_TIM2 STM32_RCC_TIM2_RST + +#define TIMRCCEN_TIM3 STM32_RCC_TIM3_EN_REG +#define TIMEN_TIM3 STM32_RCC_TIM3_EN +#define TIMRCCRST_TIM3 STM32_RCC_TIM3_RST_REG +#define TIMRST_TIM3 STM32_RCC_TIM3_RST + +#define TIMRCCEN_TIM4 STM32_RCC_TIM4_EN_REG +#define TIMEN_TIM4 STM32_RCC_TIM4_EN +#define TIMRCCRST_TIM4 STM32_RCC_TIM4_RST_REG +#define TIMRST_TIM4 STM32_RCC_TIM4_RST + +#define TIMRCCEN_TIM5 STM32_RCC_TIM5_EN_REG +#define TIMEN_TIM5 STM32_RCC_TIM5_EN +#define TIMRCCRST_TIM5 STM32_RCC_TIM5_RST_REG +#define TIMRST_TIM5 STM32_RCC_TIM5_RST + +#define TIMRCCEN_TIM8 STM32_RCC_TIM8_EN_REG +#define TIMEN_TIM8 STM32_RCC_TIM8_EN +#define TIMRCCRST_TIM8 STM32_RCC_TIM8_RST_REG +#define TIMRST_TIM8 STM32_RCC_TIM8_RST /* Debug ********************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c deleted file mode 100644 index e88ff33418d2b..0000000000000 --- a/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c +++ /dev/null @@ -1,1254 +0,0 @@ -/**************************************************************************** - * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -# undef HAVE_32BIT_TIMERS -# undef HAVE_16BIT_TIMERS - -/* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ - -# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT) -# define HAVE_32BIT_TIMERS 1 -# endif - -/* If TIM1, TIM2 (16-bit variant), TIM3, or TIM4 are enabled, we have - * 16-bit timers - */ - -# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || \ - (defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT)) -# define HAVE_16BIT_TIMERS 1 -# endif - -/* The width in bits of each timer */ - -# define TIM1_BITWIDTH 16 -# ifdef HAVE_TIM2_16BIT -# define TIM2_BITWIDTH 16 -# else -# define TIM2_BITWIDTH 32 -# endif -# define TIM3_BITWIDTH 16 -# define TIM4_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -# undef HAVE_MIXEDWIDTH_TIMERS -# if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -# endif -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Encoder pulses prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - uint32_t index_pin; /* Index pin GPIO */ - bool index_use; /* True: Index pin is configured */ - int32_t index_offset; /* Index pin offset */ -#endif - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv, msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg); -#endif - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = stm32_setposmax, - .reset = stm32_reset, - .setindex = stm32_setindex, - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1_BRK, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 - " CCMR2: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" - " ARR: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); - sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) - if (priv->config->timid == 1) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_qe_index_irq - * - * Description: - * Common encoder index pin interrupt. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -static int stm32_qe_index_irq(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv; - bool valid = false; - - DEBUGASSERT(arg); - - priv = (struct stm32_lowerhalf_s *)arg; - - valid = stm32_gpioread(priv->index_pin); - - if (valid == true) - { - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, priv->index_offset); - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. - * Nothing else is expected. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x0000ffff; - } - else - { - priv->position += (int32_t)0x0000ffff; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - uint16_t regval; - int ret; -#endif - - /* NOTE: - * Clocking should have been enabled in the low-level RCC logic at boot-up - */ - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) - * (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. */ - - stm32_putreg16(priv, - STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) - if (priv->config->timid == 1) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - priv->index_offset = 0; -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. - * Interrupts are disabled to make this atomic (if possible) - */ - - flags = spin_lock_irqsave(&priv->lock); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - spin_unlock_irqrestore(&priv->lock, flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_setposmax - * - * Description: - * Set the maximum encoder position. - * - ****************************************************************************/ - -static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - - DEBUGASSERT(lower && priv->inuse); - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, pos); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, pos); -#endif - - return OK; -} - -/**************************************************************************** - * Name: stm32_setindex - * - * Description: - * Set the index pin position - * - ****************************************************************************/ - -static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) -{ -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - int ret = OK; - - sninfo("Set QE TIM%d the index pin position %" PRIx32 "\n", - priv->config->timid, pos); - DEBUGASSERT(lower && priv->inuse); - - if (priv->index_use == false) - { - snerr("ERROR: QE TIM%d index not registered\n", - priv->config->timid); - ret = -EPERM; - goto errout; - } - - priv->index_offset = pos; - -errout: - return ret; -#else - return -ENOTTY; -#endif -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the priv-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio) -{ - struct stm32_lowerhalf_s *priv; - int ret = OK; - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - if (priv->inuse == false) - { - snerr("ERROR: TIM%d is not in-use\n", tim); - ret = -EINVAL; - } - - priv->index_pin = gpio; - stm32_configgpio(priv->index_pin); - - ret = stm32_gpiosetevent(gpio, true, false, true, - stm32_qe_index_irq, priv); - if (ret < 0) - { - snerr("ERROR: QE TIM%d failed register irq\n", tim); - goto errout; - } - - priv->index_use = true; - -errout: - return ret; -} -#endif diff --git a/arch/arm/src/common/stm32/stm32_tim_clk.h b/arch/arm/src/common/stm32/stm32_tim_clk.h index afbcb7bd24627..b3484f2f79aad 100644 --- a/arch/arm/src/common/stm32/stm32_tim_clk.h +++ b/arch/arm/src/common/stm32/stm32_tim_clk.h @@ -23,238 +23,461 @@ #ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H #define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H -/* Per-family RCC clock-enable aliases for the common timer driver. Only the - * timer RCC clock-enable register/bit differs between families; the timer - * input clock is provided uniformly by each board as STM32_TIMn_CLKIN. - */ +/**************************************************************************** + * Included Files + ****************************************************************************/ #include #include "stm32.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Per-family RCC clock-enable and reset aliases for the common timer + * drivers. Only the timer RCC enable/reset register and bit differ between + * families; the timer input clock is provided uniformly by each board as + * STM32_TIMn_CLKIN. + */ + #if defined(CONFIG_ARCH_CHIP_STM32H7) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM2_RST RCC_APB1LRSTR_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM3_RST RCC_APB1LRSTR_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM4_RST RCC_APB1LRSTR_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM5_RST RCC_APB1LRSTR_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM6_RST RCC_APB1LRSTR_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM7_RST RCC_APB1LRSTR_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM12_RST RCC_APB1LRSTR_TIM12RST # define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM13_RST RCC_APB1LRSTR_TIM13RST # define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM14_RST RCC_APB1LRSTR_TIM14RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32F7) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM2_RST RCC_APB1RSTR_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM3_RST RCC_APB1RSTR_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM4_RST RCC_APB1RSTR_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM5_RST RCC_APB1RSTR_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM6_RST RCC_APB1RSTR_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM7_RST RCC_APB1RSTR_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM9_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM9_RST RCC_APB2RSTR_TIM9RST # define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST # define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST # define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM12_RST RCC_APB1RSTR_TIM12RST # define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM13_RST RCC_APB1RSTR_TIM13RST # define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM14_RST RCC_APB1RSTR_TIM14RST #elif defined(CONFIG_ARCH_CHIP_STM32H5) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM2_EN RCC_APB1LENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM2_RST RCC_APB1LRSTR_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM3_EN RCC_APB1LENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM3_RST RCC_APB1LRSTR_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM4_EN RCC_APB1LENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM4_RST RCC_APB1LRSTR_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM5_EN RCC_APB1LENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM5_RST RCC_APB1LRSTR_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM6_EN RCC_APB1LENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM6_RST RCC_APB1LRSTR_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM7_EN RCC_APB1LENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM7_RST RCC_APB1LRSTR_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM12_EN RCC_APB1LENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM12_RST RCC_APB1LRSTR_TIM12RST # define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM13_EN RCC_APB1LENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM13_RST RCC_APB1LRSTR_TIM13RST # define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1LENR # define STM32_RCC_TIM14_EN RCC_APB1LENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1LRSTR +# define STM32_RCC_TIM14_RST RCC_APB1LRSTR_TIM14RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32U5) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32L5) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32WL5) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32L4) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM3_EN RCC_APB1ENR1_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM3_RST RCC_APB1RSTR1_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM4_EN RCC_APB1ENR1_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM4_RST RCC_APB1RSTR1_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM5_EN RCC_APB1ENR1_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM5_RST RCC_APB1RSTR1_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM6_EN RCC_APB1ENR1_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM6_RST RCC_APB1RSTR1_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM7_EN RCC_APB1ENR1_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM7_RST RCC_APB1RSTR1_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #elif defined(CONFIG_ARCH_CHIP_STM32WB) # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR1 # define STM32_RCC_TIM2_EN RCC_APB1ENR1_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR1 +# define STM32_RCC_TIM2_RST RCC_APB1RSTR1_TIM2RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN -#else /* Classic M3/M4 (and M0) layout: APB1ENR/APB2ENR */ +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST +#else /* Classic M3/M4 + M0: APB1ENR/APB2ENR */ # define STM32_RCC_TIM1_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM1_EN RCC_APB2ENR_TIM1EN +# define STM32_RCC_TIM1_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM1_RST RCC_APB2RSTR_TIM1RST # define STM32_RCC_TIM2_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM2_EN RCC_APB1ENR_TIM2EN +# define STM32_RCC_TIM2_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM2_RST RCC_APB1RSTR_TIM2RST # define STM32_RCC_TIM3_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM3_EN RCC_APB1ENR_TIM3EN +# define STM32_RCC_TIM3_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM3_RST RCC_APB1RSTR_TIM3RST # define STM32_RCC_TIM4_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM4_EN RCC_APB1ENR_TIM4EN +# define STM32_RCC_TIM4_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM4_RST RCC_APB1RSTR_TIM4RST # define STM32_RCC_TIM5_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM5_EN RCC_APB1ENR_TIM5EN +# define STM32_RCC_TIM5_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM5_RST RCC_APB1RSTR_TIM5RST # define STM32_RCC_TIM6_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM6_EN RCC_APB1ENR_TIM6EN +# define STM32_RCC_TIM6_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM6_RST RCC_APB1RSTR_TIM6RST # define STM32_RCC_TIM7_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM7_EN RCC_APB1ENR_TIM7EN +# define STM32_RCC_TIM7_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM7_RST RCC_APB1RSTR_TIM7RST # define STM32_RCC_TIM8_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM8_EN RCC_APB2ENR_TIM8EN +# define STM32_RCC_TIM8_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM8_RST RCC_APB2RSTR_TIM8RST # define STM32_RCC_TIM9_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM9_EN RCC_APB2ENR_TIM9EN +# define STM32_RCC_TIM9_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM9_RST RCC_APB2RSTR_TIM9RST # define STM32_RCC_TIM10_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM10_EN RCC_APB2ENR_TIM10EN +# define STM32_RCC_TIM10_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM10_RST RCC_APB2RSTR_TIM10RST # define STM32_RCC_TIM11_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM11_EN RCC_APB2ENR_TIM11EN +# define STM32_RCC_TIM11_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM11_RST RCC_APB2RSTR_TIM11RST # define STM32_RCC_TIM12_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM12_EN RCC_APB1ENR_TIM12EN +# define STM32_RCC_TIM12_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM12_RST RCC_APB1RSTR_TIM12RST # define STM32_RCC_TIM13_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM13_EN RCC_APB1ENR_TIM13EN +# define STM32_RCC_TIM13_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM13_RST RCC_APB1RSTR_TIM13RST # define STM32_RCC_TIM14_EN_REG STM32_RCC_APB1ENR # define STM32_RCC_TIM14_EN RCC_APB1ENR_TIM14EN +# define STM32_RCC_TIM14_RST_REG STM32_RCC_APB1RSTR +# define STM32_RCC_TIM14_RST RCC_APB1RSTR_TIM14RST # define STM32_RCC_TIM15_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM15_EN RCC_APB2ENR_TIM15EN +# define STM32_RCC_TIM15_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM15_RST RCC_APB2RSTR_TIM15RST # define STM32_RCC_TIM16_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM16_EN RCC_APB2ENR_TIM16EN +# define STM32_RCC_TIM16_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM16_RST RCC_APB2RSTR_TIM16RST # define STM32_RCC_TIM17_EN_REG STM32_RCC_APB2ENR # define STM32_RCC_TIM17_EN RCC_APB2ENR_TIM17EN +# define STM32_RCC_TIM17_RST_REG STM32_RCC_APB2RSTR +# define STM32_RCC_TIM17_RST RCC_APB2RSTR_TIM17RST #endif #endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_CLK_H */ diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index f8fae791d2ade..0d99c5e951368 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -160,9 +160,6 @@ if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 7f0dbeb3e9297..e5c50adb786cd 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -161,9 +161,6 @@ ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c deleted file mode 100644 index fdf06b3bb0d4a..0000000000000 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ /dev/null @@ -1,1183 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_rcc.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the F7 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif -#ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ -#else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ -#endif - uintptr_t regaddr; /* RCC clock enable register address */ - uint32_t enable; /* RCC clock enable bit */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM1EN, - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM2EN, - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM3EN, - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM4EN, - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1ENR, - .enable = RCC_APB1ENR_TIM5EN, - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM8EN, - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. This applies for the STM32 - * F7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but - * works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Write a value to a 32-bit timer register. This applies for the STM32 F7 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5 (but - * works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value + 1, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x00010000; - } - else - { - priv->position += (int32_t)0x00010000; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* Enable clocking to the timer */ - - modifyreg32(priv->config->regaddr, 0, priv->config->enable); - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32 has direct config control on the pulse count prescaler. - * This input clock just limits the incoming pulse rate, which should be - * lower than the peripheral clock due to resynchronization, but it is the - * responsibility of the system designer to decide the correct prescaler - * value, because it has a direct influence on the encoder resolution. - */ - - stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1RSTR; - resetbit = RCC_APB1RSTR_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Disable clocking to the timer */ - - modifyreg32(priv->config->regaddr, priv->config->enable, 0); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. Interrupts are disabled to make this - * atomic (if possible) - */ - - flags = enter_critical_section(); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - leave_critical_section(flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the upper-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h deleted file mode 100644 index cb0399814da57..0000000000000 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f7/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - * (at least for the STM32 F7) - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM9_QE -#undef CONFIG_STM32_TIM10_QE -#undef CONFIG_STM32_TIM11_QE -#undef CONFIG_STM32_TIM12_QE -#undef CONFIG_STM32_TIM13_QE -#undef CONFIG_STM32_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F7_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index b1a0e18f08705..d5f3c712108f2 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -180,9 +180,6 @@ if(CONFIG_MDIO_BUS) list(APPEND SRCS stm32_mdio.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() if(CONFIG_PM) list(APPEND SRCS stm32_pmsleep.c stm32_pmstandby.c stm32_pmstop.c) diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 0d26445cb16ef..fd867226c4826 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -179,9 +179,6 @@ ifeq ($(CONFIG_MDIO_BUS),y) CHIP_CSRCS += stm32_mdio.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif ifeq ($(CONFIG_PM),y) CHIP_CSRCS += stm32_pmsleep.c stm32_pmstandby.c stm32_pmstop.c diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c deleted file mode 100644 index d3d29deb35cb7..0000000000000 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ /dev/null @@ -1,1184 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_gpio.h" -#include "stm32_tim.h" -#include "stm32_qencoder.h" -#include "stm32_rcc.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the H7 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif -#ifdef CONFIG_STM32_STM32F10XX - uint16_t ti1cfg; /* TI1 input pin configuration (16-bit encoding) */ - uint16_t ti2cfg; /* TI2 input pin configuration (16-bit encoding) */ -#else - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ -#endif - uintptr_t regaddr; /* RCC clock enable register address */ - uint32_t enable; /* RCC clock enable bit */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Timer input clock prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM1EN, - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM2EN, - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM3EN, - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM4EN, - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB1LENR, - .enable = RCC_APB1LENR_TIM5EN, - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .regaddr = STM32_RCC_APB2ENR, - .enable = RCC_APB2ENR_TIM8EN, - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. This applies for the - * STM32 H7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers - * TIM2-5 (but works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg32 - * - * Description: - * Write a value to a 32-bit timer register. This applies for the - * STM32 H7 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers - * TIM2-5 (but works OK with the 16-bit TIM1,8 as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg16(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require - * timer interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. Nothing else is expected. */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value + 1, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x00010000; - } - else - { - priv->position += (int32_t)0x00010000; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* Enable clocking to the timer */ - - modifyreg32(priv->config->regaddr, 0, priv->config->enable); - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32 has direct config control on the pulse count prescaler. - * This input clock just limits the incoming pulse rate, which should be - * lower than the peripheral clock due to resynchronization, but it is the - * responsibility of the system designer to decide the correct prescaler - * value, because it has a direct influence on the encoder resolution. - */ - - stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half - * driver should stop data collection, free any resources, disable timer - * hardware, and put the system into the lowest possible power usage - * state - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1LRSTR; - resetbit = RCC_APB1LRSTR_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Disable clocking to the timer */ - - modifyreg32(priv->config->regaddr, priv->config->enable, 0); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. Interrupts are disabled to make this - * atomic (if possible) - */ - - flags = enter_critical_section(); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - leave_critical_section(flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the upper-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h deleted file mode 100644 index 6ad6f0f392eb3..0000000000000 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32h7/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - * (at least for the STM32 H7) - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM9_QE -#undef CONFIG_STM32_TIM10_QE -#undef CONFIG_STM32_TIM11_QE -#undef CONFIG_STM32_TIM12_QE -#undef CONFIG_STM32_TIM13_QE -#undef CONFIG_STM32_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. This function must be - * called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32H7_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 3b96f6c2c67b0..ab7323dc1cde8 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -148,9 +148,6 @@ if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32l4_qencoder.c) -endif() if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32l4_qspi.c) diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index c348535830112..f6c621cc181c5 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -146,9 +146,6 @@ ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32l4_qencoder.c -endif ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c deleted file mode 100644 index 3287632209cbc..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ /dev/null @@ -1,1189 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32.h" -#include "stm32l4_gpio.h" -#include "stm32_tim.h" -#include "stm32l4_qencoder.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -/* Timers *******************************************************************/ - -#undef HAVE_32BIT_TIMERS -#undef HAVE_16BIT_TIMERS - -/* On the L4 series, TIM2 and TIM5 are 32-bit. All of the rest are 16-bit */ - -/* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ - -#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) -# define HAVE_32BIT_TIMERS 1 -#endif - -/* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ - defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) -# define HAVE_16BIT_TIMERS 1 -#endif - -/* The width in bits of each timer */ - -#define TIM1_BITWIDTH 16 -#define TIM2_BITWIDTH 32 -#define TIM3_BITWIDTH 16 -#define TIM4_BITWIDTH 16 -#define TIM5_BITWIDTH 32 -#define TIM8_BITWIDTH 16 - -/* Do we need to support mixed 16- and 32-bit timers */ - -#undef HAVE_MIXEDWIDTH_TIMERS -#if defined(HAVE_16BIT_TIMERS) && defined(HAVE_32BIT_TIMERS) -# define HAVE_MIXEDWIDTH_TIMERS 1 -#endif - -/* Input filter *************************************************************/ - -#ifdef CONFIG_STM32_QENCODER_FILTER -# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 -# endif -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 -# endif -# endif - -# ifndef STM32_QENCODER_ICF -# warning "Invalid encoder filter combination, filter disabled" -# endif -#endif - -#ifndef STM32_QENCODER_ICF -# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT -#endif - -#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) - -/* Debug ********************************************************************/ - -/* Non-standard debug that may be enabled just for testing the quadrature - * encoder - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_SENSORS -#endif - -#ifdef CONFIG_DEBUG_SENSORS -# ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) -# else -# define qe_dumpgpio(p,m) -# endif -#else -# define qe_dumpgpio(p,m) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Constant configuration structure that is retained in FLASH */ - -struct stm32_qeconfig_s -{ - uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ - uint8_t irq; /* Timer update IRQ */ -#ifdef HAVE_MIXEDWIDTH_TIMERS - uint8_t width; /* Timer width (16- or 32-bits) */ -#endif - uint32_t ti1cfg; /* TI1 input pin configuration (20-bit encoding) */ - uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ - uint32_t base; /* Register base address */ - uint32_t psc; /* Encoder pulses prescaler */ -}; - -/* Overall, RAM-based state structure */ - -struct stm32_lowerhalf_s -{ - /* The first field of this state structure must be a pointer to the lower- - * half callback structure: - */ - - const struct qe_ops_s *ops; /* Lower half callback structure */ - - /* STM32 driver-specific fields: */ - - const struct stm32_qeconfig_s *config; /* static onfiguration */ - - bool inuse; /* True: The lower-half driver is in-use */ - -#ifdef HAVE_16BIT_TIMERS - volatile int32_t position; /* The current position offset */ -#endif - spinlock_t lock; /* Spinlock */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Helper functions */ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, - int offset, uint16_t value); -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset); -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, - int offset, uint32_t value); - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg); -#else -# define stm32_dumpregs(priv,msg) -#endif - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); - -/* Interrupt handling */ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg); -#endif - -/* Lower-half Quadrature Encoder Driver Methods */ - -static int stm32_setup(struct qe_lowerhalf_s *lower); -static int stm32_shutdown(struct qe_lowerhalf_s *lower); -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos); -static int stm32_reset(struct qe_lowerhalf_s *lower); -static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, - unsigned long arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* The lower half callback structure */ - -static const struct qe_ops_s g_qecallbacks = -{ - .setup = stm32_setup, - .shutdown = stm32_shutdown, - .position = stm32_position, - .setposmax = NULL, /* not supported yet */ - .reset = stm32_reset, - .setindex = NULL, /* not supported yet */ - .ioctl = stm32_ioctl, -}; - -/* Per-timer state structures */ - -#ifdef CONFIG_STM32_TIM1_QE -static const struct stm32_qeconfig_s g_tim1config = -{ - .timid = 1, - .irq = STM32_IRQ_TIM1UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM1_BITWIDTH, -#endif - .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32_TIM1_QEPSC, - .ti1cfg = GPIO_TIM1_CH1IN, - .ti2cfg = GPIO_TIM1_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim1lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim1config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM2_QE -static const struct stm32_qeconfig_s g_tim2config = -{ - .timid = 2, - .irq = STM32_IRQ_TIM2, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM2_BITWIDTH, -#endif - .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32_TIM2_QEPSC, - .ti1cfg = GPIO_TIM2_CH1IN, - .ti2cfg = GPIO_TIM2_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim2lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim2config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM3_QE -static const struct stm32_qeconfig_s g_tim3config = -{ - .timid = 3, - .irq = STM32_IRQ_TIM3, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM3_BITWIDTH, -#endif - .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32_TIM3_QEPSC, - .ti1cfg = GPIO_TIM3_CH1IN, - .ti2cfg = GPIO_TIM3_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim3lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim3config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM4_QE -static const struct stm32_qeconfig_s g_tim4config = -{ - .timid = 4, - .irq = STM32_IRQ_TIM4, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM4_BITWIDTH, -#endif - .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32_TIM4_QEPSC, - .ti1cfg = GPIO_TIM4_CH1IN, - .ti2cfg = GPIO_TIM4_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim4lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim4config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM5_QE -static const struct stm32_qeconfig_s g_tim5config = -{ - .timid = 5, - .irq = STM32_IRQ_TIM5, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM5_BITWIDTH, -#endif - .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32_TIM5_QEPSC, - .ti1cfg = GPIO_TIM5_CH1IN, - .ti2cfg = GPIO_TIM5_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim5lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim5config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -#ifdef CONFIG_STM32_TIM8_QE -static const struct stm32_qeconfig_s g_tim8config = -{ - .timid = 8, - .irq = STM32_IRQ_TIM8UP, -#ifdef HAVE_MIXEDWIDTH_TIMERS - .width = TIM8_BITWIDTH, -#endif - .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32_TIM8_QEPSC, - .ti1cfg = GPIO_TIM8_CH1IN, - .ti2cfg = GPIO_TIM8_CH2IN, -}; - -static struct stm32_lowerhalf_s g_tim8lower = -{ - .ops = &g_qecallbacks, - .config = &g_tim8config, - .inuse = false, - .lock = SP_UNLOCKED, -}; - -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_getreg16 - * - * Description: - * Read the value of a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg16(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 16-bit timer register. - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg16(struct stm32_lowerhalf_s *priv, - int offset, - uint16_t value) -{ - putreg16(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_getreg32 - * - * Description: - * Read the value of a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers as well). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * The current contents of the specified register - * - ****************************************************************************/ - -static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, - int offset) -{ - return getreg32(priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_putreg16 - * - * Description: - * Write a value to a 32-bit timer register. - * This applies only for the STM32 F4 32-bit registers (CNT, ARR, CRR1-4) - * in the 32-bit timers TIM2-5 (but works OK with the 16-bit TIM1,8 - * and F1 registers). - * - * Input Parameters: - * priv - A reference to the lower half status - * offset - The offset to the register to read - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void stm32_putreg32(struct stm32_lowerhalf_s *priv, - int offset, - uint32_t value) -{ - putreg32(value, priv->config->base + offset); -} - -/**************************************************************************** - * Name: stm32_dumpregs - * - * Description: - * Dump all timer registers. - * - * Input Parameters: - * priv - A reference to the QENCODER block status - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, - const char *msg) -{ - sninfo("%s:\n", msg); - sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); - sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 - " CCMR2: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); - sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" - " ARR: %08" PRIx32 "\n", - stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); - sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); - sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); - } - else -#endif - { - sninfo(" DCR: %04x DMAR: %04x\n", - stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); - } -} -#endif - -/**************************************************************************** - * Name: stm32_tim2lower - * - * Description: - * Map a timer number to a device structure - * - ****************************************************************************/ - -static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) -{ - switch (tim) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - return &g_tim1lower; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - return &g_tim2lower; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - return &g_tim3lower; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - return &g_tim4lower; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - return &g_tim5lower; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - return &g_tim8lower; -#endif - default: - return NULL; - } -} - -/**************************************************************************** - * Name: stm32_interrupt - * - * Description: - * Common timer interrupt handling. NOTE: Only 16-bit timers require timer - * interrupts. - * - ****************************************************************************/ - -#ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(int irq, void *context, void *arg) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)arg; - uint16_t regval; - - DEBUGASSERT(priv != NULL); - - /* Verify that this is an update interrupt. - * Nothing else is expected. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - DEBUGASSERT((regval & ATIM_SR_UIF) != 0); - - /* Clear the UIF interrupt bit */ - - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Check the direction bit in the CR1 register and add or subtract the - * maximum value, as appropriate. - */ - - regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - if ((regval & ATIM_CR1_DIR) != 0) - { - priv->position -= (int32_t)0x0000ffff; - } - else - { - priv->position += (int32_t)0x0000ffff; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: stm32_setup - * - * Description: - * This method is called when the driver is opened. The lower half driver - * should configure and initialize the device so that it is ready for use. - * The initial position value should be zero. * - * - ****************************************************************************/ - -static int stm32_setup(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - uint16_t dier; - uint32_t smcr; - uint32_t ccmr1; - uint16_t ccer; - uint16_t cr1; -#ifdef HAVE_16BIT_TIMERS - uint16_t regval; - int ret; -#endif - - /* NOTE: - * Clocking should have been enabled in the low-level RCC logic at boot-up - */ - - /* Timer base configuration */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - - /* Clear the direction bit (0=count up) and select the Counter Mode - * (0=Edge aligned) - * (Timers 2-5 and 1-8 only) - */ - - cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Set the Autoreload value */ - -#if defined(HAVE_MIXEDWIDTH_TIMERS) - if (priv->config->width == 32) - { - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); - } - else - { - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); - } -#elif defined(HAVE_32BIT_TIMERS) - stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); -#else - stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); -#endif - - /* Set the timer prescaler value. - * - * Previously, and still in the stm32fx driver, the clock input value - * (CLKIN) was based on the peripheral clock (PCLK) and a multiplier. - * These CLKIN values are provided in the board.h file. - * The prescaler value is then that CLKIN value divided by the configured - * CLKOUT value (minus one). - * - * It was determined that this configuration makes no sense for a qencoder. - * If we are doing precise shaft positioning, each qe pulse is important. - * So the STM32L4 has direct config control on the pulse count prescaler, - * instead of deriving this value from an obscure "output" setting AND the - * timer input clock. This input clock just limits the incoming pulse rate, - * which should be lower than the peripheral clock due to - * resynchronization, but it is the responsibility of the system designer - * to decide the correct prescaler value, because it has a direct influence - * on the encoder resolution. - */ - - stm32_putreg16(priv, - STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); - -#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) - if (priv->config->timid == 1 || priv->config->timid == 8) - { - /* Clear the Repetition Counter value */ - - stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); - } -#endif - - /* Generate an update event to reload the Prescaler - * and the repetition counter (only for TIM1 and TIM8) value immediately - */ - - stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); - - /* GPIO pin configuration */ - - stm32_configgpio(priv->config->ti1cfg); - stm32_configgpio(priv->config->ti2cfg); - - /* Set the encoder Mode 3 */ - - smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); - smcr &= ~GTIM_SMCR_SMS_MASK; - smcr |= GTIM_SMCR_ENCMD3; - stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); - - /* TI1 Channel Configuration */ - - /* Disable the Channel 1: Reset the CC1E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC1E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; - - /* Select the Polarity=rising and set the CC1E Bit */ - - ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP); - ccer |= GTIM_CCER_CC1E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* TI2 Channel Configuration */ - - /* Disable the Channel 2: Reset the CC2E Bit */ - - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - ccer &= ~GTIM_CCER_CC2E; - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); - - /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ - - ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); - ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; - - /* Select the Polarity=rising and set the CC2E Bit */ - - ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP); - ccer |= GTIM_CCER_CC2E; - - /* Write to TIM CCMR1 and CCER registers */ - - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - - /* Set the Input Capture Prescaler value: Capture performed each time an - * edge is detected on the capture input. - */ - - ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; - ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - - /* Disable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier &= ~GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Attach the interrupt handler */ - - ret = irq_attach(priv->config->irq, stm32_interrupt, priv); - if (ret < 0) - { - stm32_shutdown(lower); - return ret; - } - - /* Enable the update/global interrupt at the NVIC */ - - up_enable_irq(priv->config->irq); - } -#endif - - /* Reset the Update Disable Bit */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 &= ~GTIM_CR1_UDIS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* Reset the URS Bit */ - - cr1 &= ~GTIM_CR1_URS; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - /* There is no need for interrupts with 32-bit timers */ - -#ifdef HAVE_16BIT_TIMERS -#ifdef HAVE_MIXEDWIDTH_TIMERS - if (priv->config->width != 32) -#endif - { - /* Clear any pending update interrupts */ - - regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); - - /* Then enable the update interrupt */ - - dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); - dier |= GTIM_DIER_UIE; - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); - } -#endif - - /* Enable the TIM Counter */ - - cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); - cr1 |= GTIM_CR1_CEN; - stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - - stm32_dumpregs(priv, "After setup"); - - return OK; -} - -/**************************************************************************** - * Name: stm32_shutdown - * - * Description: - * This method is called when the driver is closed. The lower half driver - * should stop data collection, free any resources, disable timer hardware, - * and put the system into the lowest possible power usage state * - * - ****************************************************************************/ - -static int stm32_shutdown(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; - irqstate_t flags; - uint32_t regaddr; - uint32_t regval; - uint32_t resetbit; - uint32_t pincfg; - - /* Disable the update/global interrupt at the NVIC */ - - flags = enter_critical_section(); - up_disable_irq(priv->config->irq); - - /* Detach the interrupt handler */ - - irq_detach(priv->config->irq); - - /* Disable interrupts momentary to stop any ongoing timer processing and - * to prevent any concurrent access to the reset register. - */ - - /* Disable further interrupts and stop the timer */ - - stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); - - /* Determine which timer to reset */ - - switch (priv->config->timid) - { -#ifdef CONFIG_STM32_TIM1_QE - case 1: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM1RST; - break; -#endif -#ifdef CONFIG_STM32_TIM2_QE - case 2: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM2RST; - break; -#endif -#ifdef CONFIG_STM32_TIM3_QE - case 3: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM3RST; - break; -#endif -#ifdef CONFIG_STM32_TIM4_QE - case 4: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM4RST; - break; -#endif -#ifdef CONFIG_STM32_TIM5_QE - case 5: - regaddr = STM32_RCC_APB1RSTR1; - resetbit = RCC_APB1RSTR1_TIM5RST; - break; -#endif -#ifdef CONFIG_STM32_TIM8_QE - case 8: - regaddr = STM32_RCC_APB2RSTR; - resetbit = RCC_APB2RSTR_TIM8RST; - break; -#endif - default: - leave_critical_section(flags); - return -EINVAL; - } - - /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32_start() can be called. - */ - - regval = getreg32(regaddr); - regval |= resetbit; - putreg32(regval, regaddr); - - regval &= ~resetbit; - putreg32(regval, regaddr); - leave_critical_section(flags); - - sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", - regaddr, resetbit); - stm32_dumpregs(priv, "After stop"); - - /* Put the TI1 GPIO pin back to its default state */ - - pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - - /* Put the TI2 GPIO pin back to its default state */ - - pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32_GPIO_INPUT_FLOAT; - - stm32_configgpio(pincfg); - return OK; -} - -/**************************************************************************** - * Name: stm32_position - * - * Description: - * Return the current position measurement. - * - ****************************************************************************/ - -static int stm32_position(struct qe_lowerhalf_s *lower, - int32_t *pos) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - int32_t position; - int32_t verify; - uint32_t count; - - DEBUGASSERT(lower && priv->inuse); - - /* Loop until we are certain that no interrupt occurred between samples */ - - flags = spin_lock_irqsave(&priv->lock); - do - { - position = priv->position; - count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); - verify = priv->position; - } - while (position != verify); - spin_unlock_irqrestore(&priv->lock, flags); - - /* Return the position measurement */ - - *pos = position + (int32_t)count; -#else - /* Return the counter value */ - - *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_reset - * - * Description: - * Reset the position measurement to zero. - * - ****************************************************************************/ - -static int stm32_reset(struct qe_lowerhalf_s *lower) -{ - struct stm32_lowerhalf_s *priv = - (struct stm32_lowerhalf_s *)lower; -#ifdef HAVE_16BIT_TIMERS - irqstate_t flags; - - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the timer and the counter. - * Interrupts are disabled to make this atomic (if possible) - */ - - flags = spin_lock_irqsave(&priv->lock); - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); - priv->position = 0; - spin_unlock_irqrestore(&priv->lock, flags); -#else - sninfo("Resetting position to zero\n"); - DEBUGASSERT(lower && priv->inuse); - - /* Reset the counter to zero */ - - stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); -#endif - return OK; -} - -/**************************************************************************** - * Name: stm32_ioctl - * - * Description: - * Lower-half logic may support platform-specific ioctl commands - * - ****************************************************************************/ - -static int stm32_ioctl(struct qe_lowerhalf_s *lower, - int cmd, unsigned long arg) -{ - /* No ioctl commands supported */ - - /* TODO add an IOCTL to control the encoder pulse count prescaler */ - - return -ENOTTY; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim) -{ - struct stm32_lowerhalf_s *priv; - int ret; - - /* Find the pre-allocated timer state structure corresponding to this - * timer - */ - - priv = stm32_tim2lower(tim); - if (!priv) - { - snerr("ERROR: TIM%d support not configured\n", tim); - return -ENXIO; - } - - /* Make sure that it is available */ - - if (priv->inuse) - { - snerr("ERROR: TIM%d is in-use\n", tim); - return -EBUSY; - } - - /* Register the priv-half driver */ - - ret = qe_register(devpath, (struct qe_lowerhalf_s *)priv); - if (ret < 0) - { - snerr("ERROR: qe_register failed: %d\n", ret); - return ret; - } - - /* Make sure that the timer is in the shutdown state */ - - stm32_shutdown((struct qe_lowerhalf_s *)priv); - - /* The driver is now in-use */ - - priv->inuse = true; - return OK; -} - -#endif /* CONFIG_SENSORS_QENCODER */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h deleted file mode 100644 index 1197bdfc67acc..0000000000000 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32l4/stm32l4_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that - * timer "n" is intended to be used for as a quadrature encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif -#ifndef CONFIG_STM32_TIM5 -# undef CONFIG_STM32_TIM5_QE -#endif -#ifndef CONFIG_STM32_TIM8 -# undef CONFIG_STM32_TIM8_QE -#endif - -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM9_QE -#undef CONFIG_STM32_TIM10_QE -#undef CONFIG_STM32_TIM11_QE -#undef CONFIG_STM32_TIM12_QE -#undef CONFIG_STM32_TIM13_QE -#undef CONFIG_STM32_TIM14_QE - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic.. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4,5,8} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32_QENCODER_H */